1 // SPDX-License-Identifier: GPL-2.0+
3 #include <linux/types.h>
5 #include <linux/platform_device.h>
6 #include <linux/pm_runtime.h>
7 #include <linux/acpi.h>
8 #include <linux/of_mdio.h>
9 #include <linux/etherdevice.h>
10 #include <linux/interrupt.h>
12 #include <linux/netlink.h>
13 #include <linux/bpf.h>
14 #include <linux/bpf_trace.h>
17 #include <net/page_pool.h>
18 #include <net/ip6_checksum.h>
20 #define NETSEC_REG_SOFT_RST 0x104
21 #define NETSEC_REG_COM_INIT 0x120
23 #define NETSEC_REG_TOP_STATUS 0x200
24 #define NETSEC_IRQ_RX BIT(1)
25 #define NETSEC_IRQ_TX BIT(0)
27 #define NETSEC_REG_TOP_INTEN 0x204
28 #define NETSEC_REG_INTEN_SET 0x234
29 #define NETSEC_REG_INTEN_CLR 0x238
31 #define NETSEC_REG_NRM_TX_STATUS 0x400
32 #define NETSEC_REG_NRM_TX_INTEN 0x404
33 #define NETSEC_REG_NRM_TX_INTEN_SET 0x428
34 #define NETSEC_REG_NRM_TX_INTEN_CLR 0x42c
35 #define NRM_TX_ST_NTOWNR BIT(17)
36 #define NRM_TX_ST_TR_ERR BIT(16)
37 #define NRM_TX_ST_TXDONE BIT(15)
38 #define NRM_TX_ST_TMREXP BIT(14)
40 #define NETSEC_REG_NRM_RX_STATUS 0x440
41 #define NETSEC_REG_NRM_RX_INTEN 0x444
42 #define NETSEC_REG_NRM_RX_INTEN_SET 0x468
43 #define NETSEC_REG_NRM_RX_INTEN_CLR 0x46c
44 #define NRM_RX_ST_RC_ERR BIT(16)
45 #define NRM_RX_ST_PKTCNT BIT(15)
46 #define NRM_RX_ST_TMREXP BIT(14)
48 #define NETSEC_REG_PKT_CMD_BUF 0xd0
50 #define NETSEC_REG_CLK_EN 0x100
52 #define NETSEC_REG_PKT_CTRL 0x140
54 #define NETSEC_REG_DMA_TMR_CTRL 0x20c
55 #define NETSEC_REG_F_TAIKI_MC_VER 0x22c
56 #define NETSEC_REG_F_TAIKI_VER 0x230
57 #define NETSEC_REG_DMA_HM_CTRL 0x214
58 #define NETSEC_REG_DMA_MH_CTRL 0x220
59 #define NETSEC_REG_ADDR_DIS_CORE 0x218
60 #define NETSEC_REG_DMAC_HM_CMD_BUF 0x210
61 #define NETSEC_REG_DMAC_MH_CMD_BUF 0x21c
63 #define NETSEC_REG_NRM_TX_PKTCNT 0x410
65 #define NETSEC_REG_NRM_TX_DONE_PKTCNT 0x414
66 #define NETSEC_REG_NRM_TX_DONE_TXINT_PKTCNT 0x418
68 #define NETSEC_REG_NRM_TX_TMR 0x41c
70 #define NETSEC_REG_NRM_RX_PKTCNT 0x454
71 #define NETSEC_REG_NRM_RX_RXINT_PKTCNT 0x458
72 #define NETSEC_REG_NRM_TX_TXINT_TMR 0x420
73 #define NETSEC_REG_NRM_RX_RXINT_TMR 0x460
75 #define NETSEC_REG_NRM_RX_TMR 0x45c
77 #define NETSEC_REG_NRM_TX_DESC_START_UP 0x434
78 #define NETSEC_REG_NRM_TX_DESC_START_LW 0x408
79 #define NETSEC_REG_NRM_RX_DESC_START_UP 0x474
80 #define NETSEC_REG_NRM_RX_DESC_START_LW 0x448
82 #define NETSEC_REG_NRM_TX_CONFIG 0x430
83 #define NETSEC_REG_NRM_RX_CONFIG 0x470
85 #define MAC_REG_STATUS 0x1024
86 #define MAC_REG_DATA 0x11c0
87 #define MAC_REG_CMD 0x11c4
88 #define MAC_REG_FLOW_TH 0x11cc
89 #define MAC_REG_INTF_SEL 0x11d4
90 #define MAC_REG_DESC_INIT 0x11fc
91 #define MAC_REG_DESC_SOFT_RST 0x1204
92 #define NETSEC_REG_MODE_TRANS_COMP_STATUS 0x500
94 #define GMAC_REG_MCR 0x0000
95 #define GMAC_REG_MFFR 0x0004
96 #define GMAC_REG_GAR 0x0010
97 #define GMAC_REG_GDR 0x0014
98 #define GMAC_REG_FCR 0x0018
99 #define GMAC_REG_BMR 0x1000
100 #define GMAC_REG_RDLAR 0x100c
101 #define GMAC_REG_TDLAR 0x1010
102 #define GMAC_REG_OMR 0x1018
104 #define MHZ(n) ((n) * 1000 * 1000)
106 #define NETSEC_TX_SHIFT_OWN_FIELD 31
107 #define NETSEC_TX_SHIFT_LD_FIELD 30
108 #define NETSEC_TX_SHIFT_DRID_FIELD 24
109 #define NETSEC_TX_SHIFT_PT_FIELD 21
110 #define NETSEC_TX_SHIFT_TDRID_FIELD 16
111 #define NETSEC_TX_SHIFT_CC_FIELD 15
112 #define NETSEC_TX_SHIFT_FS_FIELD 9
113 #define NETSEC_TX_LAST 8
114 #define NETSEC_TX_SHIFT_CO 7
115 #define NETSEC_TX_SHIFT_SO 6
116 #define NETSEC_TX_SHIFT_TRS_FIELD 4
118 #define NETSEC_RX_PKT_OWN_FIELD 31
119 #define NETSEC_RX_PKT_LD_FIELD 30
120 #define NETSEC_RX_PKT_SDRID_FIELD 24
121 #define NETSEC_RX_PKT_FR_FIELD 23
122 #define NETSEC_RX_PKT_ER_FIELD 21
123 #define NETSEC_RX_PKT_ERR_FIELD 16
124 #define NETSEC_RX_PKT_TDRID_FIELD 12
125 #define NETSEC_RX_PKT_FS_FIELD 9
126 #define NETSEC_RX_PKT_LS_FIELD 8
127 #define NETSEC_RX_PKT_CO_FIELD 6
129 #define NETSEC_RX_PKT_ERR_MASK 3
131 #define NETSEC_MAX_TX_PKT_LEN 1518
132 #define NETSEC_MAX_TX_JUMBO_PKT_LEN 9018
134 #define NETSEC_RING_GMAC 15
135 #define NETSEC_RING_MAX 2
137 #define NETSEC_TCP_SEG_LEN_MAX 1460
138 #define NETSEC_TCP_JUMBO_SEG_LEN_MAX 8960
140 #define NETSEC_RX_CKSUM_NOTAVAIL 0
141 #define NETSEC_RX_CKSUM_OK 1
142 #define NETSEC_RX_CKSUM_NG 2
144 #define NETSEC_TOP_IRQ_REG_CODE_LOAD_END BIT(20)
145 #define NETSEC_IRQ_TRANSITION_COMPLETE BIT(4)
147 #define NETSEC_MODE_TRANS_COMP_IRQ_N2T BIT(20)
148 #define NETSEC_MODE_TRANS_COMP_IRQ_T2N BIT(19)
150 #define NETSEC_INT_PKTCNT_MAX 2047
152 #define NETSEC_FLOW_START_TH_MAX 95
153 #define NETSEC_FLOW_STOP_TH_MAX 95
154 #define NETSEC_FLOW_PAUSE_TIME_MIN 5
156 #define NETSEC_CLK_EN_REG_DOM_ALL 0x3f
158 #define NETSEC_PKT_CTRL_REG_MODE_NRM BIT(28)
159 #define NETSEC_PKT_CTRL_REG_EN_JUMBO BIT(27)
160 #define NETSEC_PKT_CTRL_REG_LOG_CHKSUM_ER BIT(3)
161 #define NETSEC_PKT_CTRL_REG_LOG_HD_INCOMPLETE BIT(2)
162 #define NETSEC_PKT_CTRL_REG_LOG_HD_ER BIT(1)
163 #define NETSEC_PKT_CTRL_REG_DRP_NO_MATCH BIT(0)
165 #define NETSEC_CLK_EN_REG_DOM_G BIT(5)
166 #define NETSEC_CLK_EN_REG_DOM_C BIT(1)
167 #define NETSEC_CLK_EN_REG_DOM_D BIT(0)
169 #define NETSEC_COM_INIT_REG_DB BIT(2)
170 #define NETSEC_COM_INIT_REG_CLS BIT(1)
171 #define NETSEC_COM_INIT_REG_ALL (NETSEC_COM_INIT_REG_CLS | \
172 NETSEC_COM_INIT_REG_DB)
174 #define NETSEC_SOFT_RST_REG_RESET 0
175 #define NETSEC_SOFT_RST_REG_RUN BIT(31)
177 #define NETSEC_DMA_CTRL_REG_STOP 1
178 #define MH_CTRL__MODE_TRANS BIT(20)
180 #define NETSEC_GMAC_CMD_ST_READ 0
181 #define NETSEC_GMAC_CMD_ST_WRITE BIT(28)
182 #define NETSEC_GMAC_CMD_ST_BUSY BIT(31)
184 #define NETSEC_GMAC_BMR_REG_COMMON 0x00412080
185 #define NETSEC_GMAC_BMR_REG_RESET 0x00020181
186 #define NETSEC_GMAC_BMR_REG_SWR 0x00000001
188 #define NETSEC_GMAC_OMR_REG_ST BIT(13)
189 #define NETSEC_GMAC_OMR_REG_SR BIT(1)
191 #define NETSEC_GMAC_MCR_REG_IBN BIT(30)
192 #define NETSEC_GMAC_MCR_REG_CST BIT(25)
193 #define NETSEC_GMAC_MCR_REG_JE BIT(20)
194 #define NETSEC_MCR_PS BIT(15)
195 #define NETSEC_GMAC_MCR_REG_FES BIT(14)
196 #define NETSEC_GMAC_MCR_REG_FULL_DUPLEX_COMMON 0x0000280c
197 #define NETSEC_GMAC_MCR_REG_HALF_DUPLEX_COMMON 0x0001a00c
199 #define NETSEC_FCR_RFE BIT(2)
200 #define NETSEC_FCR_TFE BIT(1)
202 #define NETSEC_GMAC_GAR_REG_GW BIT(1)
203 #define NETSEC_GMAC_GAR_REG_GB BIT(0)
205 #define NETSEC_GMAC_GAR_REG_SHIFT_PA 11
206 #define NETSEC_GMAC_GAR_REG_SHIFT_GR 6
207 #define GMAC_REG_SHIFT_CR_GAR 2
209 #define NETSEC_GMAC_GAR_REG_CR_25_35_MHZ 2
210 #define NETSEC_GMAC_GAR_REG_CR_35_60_MHZ 3
211 #define NETSEC_GMAC_GAR_REG_CR_60_100_MHZ 0
212 #define NETSEC_GMAC_GAR_REG_CR_100_150_MHZ 1
213 #define NETSEC_GMAC_GAR_REG_CR_150_250_MHZ 4
214 #define NETSEC_GMAC_GAR_REG_CR_250_300_MHZ 5
216 #define NETSEC_GMAC_RDLAR_REG_COMMON 0x18000
217 #define NETSEC_GMAC_TDLAR_REG_COMMON 0x1c000
219 #define NETSEC_REG_NETSEC_VER_F_TAIKI 0x50000
221 #define NETSEC_REG_DESC_RING_CONFIG_CFG_UP BIT(31)
222 #define NETSEC_REG_DESC_RING_CONFIG_CH_RST BIT(30)
223 #define NETSEC_REG_DESC_TMR_MODE 4
224 #define NETSEC_REG_DESC_ENDIAN 0
226 #define NETSEC_MAC_DESC_SOFT_RST_SOFT_RST 1
227 #define NETSEC_MAC_DESC_INIT_REG_INIT 1
229 #define NETSEC_EEPROM_MAC_ADDRESS 0x00
230 #define NETSEC_EEPROM_HM_ME_ADDRESS_H 0x08
231 #define NETSEC_EEPROM_HM_ME_ADDRESS_L 0x0C
232 #define NETSEC_EEPROM_HM_ME_SIZE 0x10
233 #define NETSEC_EEPROM_MH_ME_ADDRESS_H 0x14
234 #define NETSEC_EEPROM_MH_ME_ADDRESS_L 0x18
235 #define NETSEC_EEPROM_MH_ME_SIZE 0x1C
236 #define NETSEC_EEPROM_PKT_ME_ADDRESS 0x20
237 #define NETSEC_EEPROM_PKT_ME_SIZE 0x24
241 #define NETSEC_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN)
242 #define NETSEC_RXBUF_HEADROOM (max(XDP_PACKET_HEADROOM, NET_SKB_PAD) + \
244 #define NETSEC_RX_BUF_NON_DATA (NETSEC_RXBUF_HEADROOM + \
245 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
246 #define NETSEC_RX_BUF_SIZE (PAGE_SIZE - NETSEC_RX_BUF_NON_DATA)
248 #define DESC_SZ sizeof(struct netsec_de)
250 #define NETSEC_F_NETSEC_VER_MAJOR_NUM(x) ((x) & 0xffff0000)
252 #define NETSEC_XDP_PASS 0
253 #define NETSEC_XDP_CONSUMED BIT(0)
254 #define NETSEC_XDP_TX BIT(1)
255 #define NETSEC_XDP_REDIR BIT(2)
271 struct xdp_frame *xdpf;
279 struct netsec_desc_ring {
281 struct netsec_desc *desc;
284 u16 xdp_xmit; /* netsec_xdp_xmit packets */
285 struct page_pool *page_pool;
286 struct xdp_rxq_info xdp_rxq;
287 spinlock_t lock; /* XDP tx queue locking */
291 struct netsec_desc_ring desc_ring[NETSEC_RING_MAX];
292 struct ethtool_coalesce et_coalesce;
293 struct bpf_prog *xdp_prog;
294 spinlock_t reglock; /* protect reg access */
295 struct napi_struct napi;
296 phy_interface_t phy_interface;
297 struct net_device *ndev;
298 struct device_node *phy_np;
299 struct phy_device *phydev;
300 struct mii_bus *mii_bus;
301 void __iomem *ioaddr;
302 void __iomem *eeprom_base;
308 bool rx_cksum_offload_flag;
311 struct netsec_de { /* Netsec Descriptor layout */
313 u32 data_buf_addr_up;
314 u32 data_buf_addr_lw;
318 struct netsec_tx_pkt_ctrl {
320 bool tcp_seg_offload_flag;
321 bool cksum_offload_flag;
324 struct netsec_rx_pkt_info {
330 static void netsec_write(struct netsec_priv *priv, u32 reg_addr, u32 val)
332 writel(val, priv->ioaddr + reg_addr);
335 static u32 netsec_read(struct netsec_priv *priv, u32 reg_addr)
337 return readl(priv->ioaddr + reg_addr);
340 /************* MDIO BUS OPS FOLLOW *************/
342 #define TIMEOUT_SPINS_MAC 1000
343 #define TIMEOUT_SECONDARY_MS_MAC 100
345 static u32 netsec_clk_type(u32 freq)
348 return NETSEC_GMAC_GAR_REG_CR_25_35_MHZ;
350 return NETSEC_GMAC_GAR_REG_CR_35_60_MHZ;
352 return NETSEC_GMAC_GAR_REG_CR_60_100_MHZ;
354 return NETSEC_GMAC_GAR_REG_CR_100_150_MHZ;
356 return NETSEC_GMAC_GAR_REG_CR_150_250_MHZ;
358 return NETSEC_GMAC_GAR_REG_CR_250_300_MHZ;
361 static int netsec_wait_while_busy(struct netsec_priv *priv, u32 addr, u32 mask)
363 u32 timeout = TIMEOUT_SPINS_MAC;
365 while (--timeout && netsec_read(priv, addr) & mask)
370 timeout = TIMEOUT_SECONDARY_MS_MAC;
371 while (--timeout && netsec_read(priv, addr) & mask)
372 usleep_range(1000, 2000);
377 netdev_WARN(priv->ndev, "%s: timeout\n", __func__);
382 static int netsec_mac_write(struct netsec_priv *priv, u32 addr, u32 value)
384 netsec_write(priv, MAC_REG_DATA, value);
385 netsec_write(priv, MAC_REG_CMD, addr | NETSEC_GMAC_CMD_ST_WRITE);
386 return netsec_wait_while_busy(priv,
387 MAC_REG_CMD, NETSEC_GMAC_CMD_ST_BUSY);
390 static int netsec_mac_read(struct netsec_priv *priv, u32 addr, u32 *read)
394 netsec_write(priv, MAC_REG_CMD, addr | NETSEC_GMAC_CMD_ST_READ);
395 ret = netsec_wait_while_busy(priv,
396 MAC_REG_CMD, NETSEC_GMAC_CMD_ST_BUSY);
400 *read = netsec_read(priv, MAC_REG_DATA);
405 static int netsec_mac_wait_while_busy(struct netsec_priv *priv,
408 u32 timeout = TIMEOUT_SPINS_MAC;
412 ret = netsec_mac_read(priv, addr, &data);
416 } while (--timeout && (data & mask));
421 timeout = TIMEOUT_SECONDARY_MS_MAC;
423 usleep_range(1000, 2000);
425 ret = netsec_mac_read(priv, addr, &data);
429 } while (--timeout && (data & mask));
434 netdev_WARN(priv->ndev, "%s: timeout\n", __func__);
439 static int netsec_mac_update_to_phy_state(struct netsec_priv *priv)
441 struct phy_device *phydev = priv->ndev->phydev;
444 value = phydev->duplex ? NETSEC_GMAC_MCR_REG_FULL_DUPLEX_COMMON :
445 NETSEC_GMAC_MCR_REG_HALF_DUPLEX_COMMON;
447 if (phydev->speed != SPEED_1000)
448 value |= NETSEC_MCR_PS;
450 if (priv->phy_interface != PHY_INTERFACE_MODE_GMII &&
451 phydev->speed == SPEED_100)
452 value |= NETSEC_GMAC_MCR_REG_FES;
454 value |= NETSEC_GMAC_MCR_REG_CST | NETSEC_GMAC_MCR_REG_JE;
456 if (phy_interface_mode_is_rgmii(priv->phy_interface))
457 value |= NETSEC_GMAC_MCR_REG_IBN;
459 if (netsec_mac_write(priv, GMAC_REG_MCR, value))
465 static int netsec_phy_read(struct mii_bus *bus, int phy_addr, int reg_addr);
467 static int netsec_phy_write(struct mii_bus *bus,
468 int phy_addr, int reg, u16 val)
471 struct netsec_priv *priv = bus->priv;
473 if (netsec_mac_write(priv, GMAC_REG_GDR, val))
475 if (netsec_mac_write(priv, GMAC_REG_GAR,
476 phy_addr << NETSEC_GMAC_GAR_REG_SHIFT_PA |
477 reg << NETSEC_GMAC_GAR_REG_SHIFT_GR |
478 NETSEC_GMAC_GAR_REG_GW | NETSEC_GMAC_GAR_REG_GB |
479 (netsec_clk_type(priv->freq) <<
480 GMAC_REG_SHIFT_CR_GAR)))
483 status = netsec_mac_wait_while_busy(priv, GMAC_REG_GAR,
484 NETSEC_GMAC_GAR_REG_GB);
486 /* Developerbox implements RTL8211E PHY and there is
487 * a compatibility problem with F_GMAC4.
488 * RTL8211E expects MDC clock must be kept toggling for several
489 * clock cycle with MDIO high before entering the IDLE state.
490 * To meet this requirement, netsec driver needs to issue dummy
491 * read(e.g. read PHYID1(offset 0x2) register) right after write.
493 netsec_phy_read(bus, phy_addr, MII_PHYSID1);
498 static int netsec_phy_read(struct mii_bus *bus, int phy_addr, int reg_addr)
500 struct netsec_priv *priv = bus->priv;
504 if (netsec_mac_write(priv, GMAC_REG_GAR, NETSEC_GMAC_GAR_REG_GB |
505 phy_addr << NETSEC_GMAC_GAR_REG_SHIFT_PA |
506 reg_addr << NETSEC_GMAC_GAR_REG_SHIFT_GR |
507 (netsec_clk_type(priv->freq) <<
508 GMAC_REG_SHIFT_CR_GAR)))
511 ret = netsec_mac_wait_while_busy(priv, GMAC_REG_GAR,
512 NETSEC_GMAC_GAR_REG_GB);
516 ret = netsec_mac_read(priv, GMAC_REG_GDR, &data);
523 /************* ETHTOOL_OPS FOLLOW *************/
525 static void netsec_et_get_drvinfo(struct net_device *net_device,
526 struct ethtool_drvinfo *info)
528 strlcpy(info->driver, "netsec", sizeof(info->driver));
529 strlcpy(info->bus_info, dev_name(net_device->dev.parent),
530 sizeof(info->bus_info));
533 static int netsec_et_get_coalesce(struct net_device *net_device,
534 struct ethtool_coalesce *et_coalesce)
536 struct netsec_priv *priv = netdev_priv(net_device);
538 *et_coalesce = priv->et_coalesce;
543 static int netsec_et_set_coalesce(struct net_device *net_device,
544 struct ethtool_coalesce *et_coalesce)
546 struct netsec_priv *priv = netdev_priv(net_device);
548 priv->et_coalesce = *et_coalesce;
550 if (priv->et_coalesce.tx_coalesce_usecs < 50)
551 priv->et_coalesce.tx_coalesce_usecs = 50;
552 if (priv->et_coalesce.tx_max_coalesced_frames < 1)
553 priv->et_coalesce.tx_max_coalesced_frames = 1;
555 netsec_write(priv, NETSEC_REG_NRM_TX_DONE_TXINT_PKTCNT,
556 priv->et_coalesce.tx_max_coalesced_frames);
557 netsec_write(priv, NETSEC_REG_NRM_TX_TXINT_TMR,
558 priv->et_coalesce.tx_coalesce_usecs);
559 netsec_write(priv, NETSEC_REG_NRM_TX_INTEN_SET, NRM_TX_ST_TXDONE);
560 netsec_write(priv, NETSEC_REG_NRM_TX_INTEN_SET, NRM_TX_ST_TMREXP);
562 if (priv->et_coalesce.rx_coalesce_usecs < 50)
563 priv->et_coalesce.rx_coalesce_usecs = 50;
564 if (priv->et_coalesce.rx_max_coalesced_frames < 1)
565 priv->et_coalesce.rx_max_coalesced_frames = 1;
567 netsec_write(priv, NETSEC_REG_NRM_RX_RXINT_PKTCNT,
568 priv->et_coalesce.rx_max_coalesced_frames);
569 netsec_write(priv, NETSEC_REG_NRM_RX_RXINT_TMR,
570 priv->et_coalesce.rx_coalesce_usecs);
571 netsec_write(priv, NETSEC_REG_NRM_RX_INTEN_SET, NRM_RX_ST_PKTCNT);
572 netsec_write(priv, NETSEC_REG_NRM_RX_INTEN_SET, NRM_RX_ST_TMREXP);
577 static u32 netsec_et_get_msglevel(struct net_device *dev)
579 struct netsec_priv *priv = netdev_priv(dev);
581 return priv->msg_enable;
584 static void netsec_et_set_msglevel(struct net_device *dev, u32 datum)
586 struct netsec_priv *priv = netdev_priv(dev);
588 priv->msg_enable = datum;
591 static const struct ethtool_ops netsec_ethtool_ops = {
592 .get_drvinfo = netsec_et_get_drvinfo,
593 .get_link_ksettings = phy_ethtool_get_link_ksettings,
594 .set_link_ksettings = phy_ethtool_set_link_ksettings,
595 .get_link = ethtool_op_get_link,
596 .get_coalesce = netsec_et_get_coalesce,
597 .set_coalesce = netsec_et_set_coalesce,
598 .get_msglevel = netsec_et_get_msglevel,
599 .set_msglevel = netsec_et_set_msglevel,
602 /************* NETDEV_OPS FOLLOW *************/
605 static void netsec_set_rx_de(struct netsec_priv *priv,
606 struct netsec_desc_ring *dring, u16 idx,
607 const struct netsec_desc *desc)
609 struct netsec_de *de = dring->vaddr + DESC_SZ * idx;
610 u32 attr = (1 << NETSEC_RX_PKT_OWN_FIELD) |
611 (1 << NETSEC_RX_PKT_FS_FIELD) |
612 (1 << NETSEC_RX_PKT_LS_FIELD);
614 if (idx == DESC_NUM - 1)
615 attr |= (1 << NETSEC_RX_PKT_LD_FIELD);
617 de->data_buf_addr_up = upper_32_bits(desc->dma_addr);
618 de->data_buf_addr_lw = lower_32_bits(desc->dma_addr);
619 de->buf_len_info = desc->len;
623 dring->desc[idx].dma_addr = desc->dma_addr;
624 dring->desc[idx].addr = desc->addr;
625 dring->desc[idx].len = desc->len;
628 static bool netsec_clean_tx_dring(struct netsec_priv *priv)
630 struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_TX];
631 struct netsec_de *entry;
632 int tail = dring->tail;
636 spin_lock(&dring->lock);
639 entry = dring->vaddr + DESC_SZ * tail;
641 while (!(entry->attr & (1U << NETSEC_TX_SHIFT_OWN_FIELD)) &&
643 struct netsec_desc *desc;
646 desc = &dring->desc[tail];
647 eop = (entry->attr >> NETSEC_TX_LAST) & 1;
650 /* if buf_type is either TYPE_NETSEC_SKB or
651 * TYPE_NETSEC_XDP_NDO we mapped it
653 if (desc->buf_type != TYPE_NETSEC_XDP_TX)
654 dma_unmap_single(priv->dev, desc->dma_addr, desc->len,
660 if (desc->buf_type == TYPE_NETSEC_SKB) {
661 bytes += desc->skb->len;
662 dev_kfree_skb(desc->skb);
664 bytes += desc->xdpf->len;
665 xdp_return_frame(desc->xdpf);
668 /* clean up so netsec_uninit_pkt_dring() won't free the skb
671 *desc = (struct netsec_desc){};
673 /* entry->attr is not going to be accessed by the NIC until
674 * netsec_set_tx_de() is called. No need for a dma_wmb() here
676 entry->attr = 1U << NETSEC_TX_SHIFT_OWN_FIELD;
677 /* move tail ahead */
678 dring->tail = (tail + 1) % DESC_NUM;
681 entry = dring->vaddr + DESC_SZ * tail;
685 spin_unlock(&dring->lock);
690 /* reading the register clears the irq */
691 netsec_read(priv, NETSEC_REG_NRM_TX_DONE_PKTCNT);
693 priv->ndev->stats.tx_packets += cnt;
694 priv->ndev->stats.tx_bytes += bytes;
696 netdev_completed_queue(priv->ndev, cnt, bytes);
701 static void netsec_process_tx(struct netsec_priv *priv)
703 struct net_device *ndev = priv->ndev;
706 cleaned = netsec_clean_tx_dring(priv);
708 if (cleaned && netif_queue_stopped(ndev)) {
709 /* Make sure we update the value, anyone stopping the queue
710 * after this will read the proper consumer idx
713 netif_wake_queue(ndev);
717 static void *netsec_alloc_rx_data(struct netsec_priv *priv,
718 dma_addr_t *dma_handle, u16 *desc_len)
722 struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_RX];
725 page = page_pool_dev_alloc_pages(dring->page_pool);
729 /* We allocate the same buffer length for XDP and non-XDP cases.
730 * page_pool API will map the whole page, skip what's needed for
731 * network payloads and/or XDP
733 *dma_handle = page_pool_get_dma_addr(page) + NETSEC_RXBUF_HEADROOM;
734 /* Make sure the incoming payload fits in the page for XDP and non-XDP
735 * cases and reserve enough space for headroom + skb_shared_info
737 *desc_len = NETSEC_RX_BUF_SIZE;
739 return page_address(page);
742 static void netsec_rx_fill(struct netsec_priv *priv, u16 from, u16 num)
744 struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_RX];
748 netsec_set_rx_de(priv, dring, idx, &dring->desc[idx]);
756 static void netsec_xdp_ring_tx_db(struct netsec_priv *priv, u16 pkts)
759 netsec_write(priv, NETSEC_REG_NRM_TX_PKTCNT, pkts);
762 static void netsec_finalize_xdp_rx(struct netsec_priv *priv, u32 xdp_res,
765 if (xdp_res & NETSEC_XDP_REDIR)
768 if (xdp_res & NETSEC_XDP_TX)
769 netsec_xdp_ring_tx_db(priv, pkts);
772 static void netsec_set_tx_de(struct netsec_priv *priv,
773 struct netsec_desc_ring *dring,
774 const struct netsec_tx_pkt_ctrl *tx_ctrl,
775 const struct netsec_desc *desc, void *buf)
777 int idx = dring->head;
778 struct netsec_de *de;
781 de = dring->vaddr + (DESC_SZ * idx);
783 attr = (1 << NETSEC_TX_SHIFT_OWN_FIELD) |
784 (1 << NETSEC_TX_SHIFT_PT_FIELD) |
785 (NETSEC_RING_GMAC << NETSEC_TX_SHIFT_TDRID_FIELD) |
786 (1 << NETSEC_TX_SHIFT_FS_FIELD) |
787 (1 << NETSEC_TX_LAST) |
788 (tx_ctrl->cksum_offload_flag << NETSEC_TX_SHIFT_CO) |
789 (tx_ctrl->tcp_seg_offload_flag << NETSEC_TX_SHIFT_SO) |
790 (1 << NETSEC_TX_SHIFT_TRS_FIELD);
791 if (idx == DESC_NUM - 1)
792 attr |= (1 << NETSEC_TX_SHIFT_LD_FIELD);
794 de->data_buf_addr_up = upper_32_bits(desc->dma_addr);
795 de->data_buf_addr_lw = lower_32_bits(desc->dma_addr);
796 de->buf_len_info = (tx_ctrl->tcp_seg_len << 16) | desc->len;
799 dring->desc[idx] = *desc;
800 if (desc->buf_type == TYPE_NETSEC_SKB)
801 dring->desc[idx].skb = buf;
802 else if (desc->buf_type == TYPE_NETSEC_XDP_TX ||
803 desc->buf_type == TYPE_NETSEC_XDP_NDO)
804 dring->desc[idx].xdpf = buf;
806 /* move head ahead */
807 dring->head = (dring->head + 1) % DESC_NUM;
810 /* The current driver only supports 1 Txq, this should run under spin_lock() */
811 static u32 netsec_xdp_queue_one(struct netsec_priv *priv,
812 struct xdp_frame *xdpf, bool is_ndo)
815 struct netsec_desc_ring *tx_ring = &priv->desc_ring[NETSEC_RING_TX];
816 struct page *page = virt_to_page(xdpf->data);
817 struct netsec_tx_pkt_ctrl tx_ctrl = {};
818 struct netsec_desc tx_desc;
819 dma_addr_t dma_handle;
822 if (tx_ring->head >= tx_ring->tail)
823 filled = tx_ring->head - tx_ring->tail;
825 filled = tx_ring->head + DESC_NUM - tx_ring->tail;
827 if (DESC_NUM - filled <= 1)
828 return NETSEC_XDP_CONSUMED;
831 /* this is for ndo_xdp_xmit, the buffer needs mapping before
834 dma_handle = dma_map_single(priv->dev, xdpf->data, xdpf->len,
836 if (dma_mapping_error(priv->dev, dma_handle))
837 return NETSEC_XDP_CONSUMED;
838 tx_desc.buf_type = TYPE_NETSEC_XDP_NDO;
840 /* This is the device Rx buffer from page_pool. No need to remap
841 * just sync and send it
843 struct netsec_desc_ring *rx_ring =
844 &priv->desc_ring[NETSEC_RING_RX];
845 enum dma_data_direction dma_dir =
846 page_pool_get_dma_dir(rx_ring->page_pool);
848 dma_handle = page_pool_get_dma_addr(page) + xdpf->headroom +
850 dma_sync_single_for_device(priv->dev, dma_handle, xdpf->len,
852 tx_desc.buf_type = TYPE_NETSEC_XDP_TX;
855 tx_desc.dma_addr = dma_handle;
856 tx_desc.addr = xdpf->data;
857 tx_desc.len = xdpf->len;
859 netdev_sent_queue(priv->ndev, xdpf->len);
860 netsec_set_tx_de(priv, tx_ring, &tx_ctrl, &tx_desc, xdpf);
862 return NETSEC_XDP_TX;
865 static u32 netsec_xdp_xmit_back(struct netsec_priv *priv, struct xdp_buff *xdp)
867 struct netsec_desc_ring *tx_ring = &priv->desc_ring[NETSEC_RING_TX];
868 struct xdp_frame *xdpf = convert_to_xdp_frame(xdp);
872 return NETSEC_XDP_CONSUMED;
874 spin_lock(&tx_ring->lock);
875 ret = netsec_xdp_queue_one(priv, xdpf, false);
876 spin_unlock(&tx_ring->lock);
881 static u32 netsec_run_xdp(struct netsec_priv *priv, struct bpf_prog *prog,
882 struct xdp_buff *xdp)
884 struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_RX];
885 unsigned int len = xdp->data_end - xdp->data;
886 u32 ret = NETSEC_XDP_PASS;
890 act = bpf_prog_run_xdp(prog, xdp);
894 ret = NETSEC_XDP_PASS;
897 ret = netsec_xdp_xmit_back(priv, xdp);
898 if (ret != NETSEC_XDP_TX)
899 __page_pool_put_page(dring->page_pool,
900 virt_to_head_page(xdp->data),
904 err = xdp_do_redirect(priv->ndev, xdp, prog);
906 ret = NETSEC_XDP_REDIR;
908 ret = NETSEC_XDP_CONSUMED;
909 __page_pool_put_page(dring->page_pool,
910 virt_to_head_page(xdp->data),
915 bpf_warn_invalid_xdp_action(act);
918 trace_xdp_exception(priv->ndev, prog, act);
919 /* fall through -- handle aborts by dropping packet */
921 ret = NETSEC_XDP_CONSUMED;
922 __page_pool_put_page(dring->page_pool,
923 virt_to_head_page(xdp->data),
931 static int netsec_process_rx(struct netsec_priv *priv, int budget)
933 struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_RX];
934 struct net_device *ndev = priv->ndev;
935 struct netsec_rx_pkt_info rx_info;
936 enum dma_data_direction dma_dir;
937 struct bpf_prog *xdp_prog;
943 xdp_prog = READ_ONCE(priv->xdp_prog);
944 dma_dir = page_pool_get_dma_dir(dring->page_pool);
946 while (done < budget) {
947 u16 idx = dring->tail;
948 struct netsec_de *de = dring->vaddr + (DESC_SZ * idx);
949 struct netsec_desc *desc = &dring->desc[idx];
950 struct page *page = virt_to_page(desc->addr);
951 u32 xdp_result = NETSEC_XDP_PASS;
952 struct sk_buff *skb = NULL;
953 u16 pkt_len, desc_len;
954 dma_addr_t dma_handle;
958 if (de->attr & (1U << NETSEC_RX_PKT_OWN_FIELD)) {
959 /* reading the register clears the irq */
960 netsec_read(priv, NETSEC_REG_NRM_RX_PKTCNT);
964 /* This barrier is needed to keep us from reading
965 * any other fields out of the netsec_de until we have
966 * verified the descriptor has been written back
971 pkt_len = de->buf_len_info >> 16;
972 rx_info.err_code = (de->attr >> NETSEC_RX_PKT_ERR_FIELD) &
973 NETSEC_RX_PKT_ERR_MASK;
974 rx_info.err_flag = (de->attr >> NETSEC_RX_PKT_ER_FIELD) & 1;
975 if (rx_info.err_flag) {
976 netif_err(priv, drv, priv->ndev,
977 "%s: rx fail err(%d)\n", __func__,
979 ndev->stats.rx_dropped++;
980 dring->tail = (dring->tail + 1) % DESC_NUM;
981 /* reuse buffer page frag */
982 netsec_rx_fill(priv, idx, 1);
985 rx_info.rx_cksum_result =
986 (de->attr >> NETSEC_RX_PKT_CO_FIELD) & 3;
988 /* allocate a fresh buffer and map it to the hardware.
989 * This will eventually replace the old buffer in the hardware
991 buf_addr = netsec_alloc_rx_data(priv, &dma_handle, &desc_len);
993 if (unlikely(!buf_addr))
996 dma_sync_single_for_cpu(priv->dev, desc->dma_addr, pkt_len,
998 prefetch(desc->addr);
1000 xdp.data_hard_start = desc->addr;
1001 xdp.data = desc->addr + NETSEC_RXBUF_HEADROOM;
1002 xdp_set_data_meta_invalid(&xdp);
1003 xdp.data_end = xdp.data + pkt_len;
1004 xdp.rxq = &dring->xdp_rxq;
1007 xdp_result = netsec_run_xdp(priv, xdp_prog, &xdp);
1008 if (xdp_result != NETSEC_XDP_PASS) {
1009 xdp_act |= xdp_result;
1010 if (xdp_result == NETSEC_XDP_TX)
1015 skb = build_skb(desc->addr, desc->len + NETSEC_RX_BUF_NON_DATA);
1017 if (unlikely(!skb)) {
1018 /* If skb fails recycle_direct will either unmap and
1019 * free the page or refill the cache depending on the
1020 * cache state. Since we paid the allocation cost if
1021 * building an skb fails try to put the page into cache
1023 __page_pool_put_page(dring->page_pool, page,
1025 netif_err(priv, drv, priv->ndev,
1026 "rx failed to build skb\n");
1029 page_pool_release_page(dring->page_pool, page);
1031 skb_reserve(skb, xdp.data - xdp.data_hard_start);
1032 skb_put(skb, xdp.data_end - xdp.data);
1033 skb->protocol = eth_type_trans(skb, priv->ndev);
1035 if (priv->rx_cksum_offload_flag &&
1036 rx_info.rx_cksum_result == NETSEC_RX_CKSUM_OK)
1037 skb->ip_summed = CHECKSUM_UNNECESSARY;
1040 if ((skb && napi_gro_receive(&priv->napi, skb) != GRO_DROP) ||
1042 ndev->stats.rx_packets++;
1043 ndev->stats.rx_bytes += xdp.data_end - xdp.data;
1046 /* Update the descriptor with fresh buffers */
1047 desc->len = desc_len;
1048 desc->dma_addr = dma_handle;
1049 desc->addr = buf_addr;
1051 netsec_rx_fill(priv, idx, 1);
1052 dring->tail = (dring->tail + 1) % DESC_NUM;
1054 netsec_finalize_xdp_rx(priv, xdp_act, xdp_xmit);
1061 static int netsec_napi_poll(struct napi_struct *napi, int budget)
1063 struct netsec_priv *priv;
1066 priv = container_of(napi, struct netsec_priv, napi);
1068 netsec_process_tx(priv);
1069 done = netsec_process_rx(priv, budget);
1071 if (done < budget && napi_complete_done(napi, done)) {
1072 unsigned long flags;
1074 spin_lock_irqsave(&priv->reglock, flags);
1075 netsec_write(priv, NETSEC_REG_INTEN_SET,
1076 NETSEC_IRQ_RX | NETSEC_IRQ_TX);
1077 spin_unlock_irqrestore(&priv->reglock, flags);
1084 static int netsec_desc_used(struct netsec_desc_ring *dring)
1088 if (dring->head >= dring->tail)
1089 used = dring->head - dring->tail;
1091 used = dring->head + DESC_NUM - dring->tail;
1096 static int netsec_check_stop_tx(struct netsec_priv *priv, int used)
1098 struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_TX];
1100 /* keep tail from touching the queue */
1101 if (DESC_NUM - used < 2) {
1102 netif_stop_queue(priv->ndev);
1104 /* Make sure we read the updated value in case
1105 * descriptors got freed
1109 used = netsec_desc_used(dring);
1110 if (DESC_NUM - used < 2)
1111 return NETDEV_TX_BUSY;
1113 netif_wake_queue(priv->ndev);
1119 static netdev_tx_t netsec_netdev_start_xmit(struct sk_buff *skb,
1120 struct net_device *ndev)
1122 struct netsec_priv *priv = netdev_priv(ndev);
1123 struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_TX];
1124 struct netsec_tx_pkt_ctrl tx_ctrl = {};
1125 struct netsec_desc tx_desc;
1126 u16 tso_seg_len = 0;
1129 spin_lock_bh(&dring->lock);
1130 filled = netsec_desc_used(dring);
1131 if (netsec_check_stop_tx(priv, filled)) {
1132 spin_unlock_bh(&dring->lock);
1133 net_warn_ratelimited("%s %s Tx queue full\n",
1134 dev_name(priv->dev), ndev->name);
1135 return NETDEV_TX_BUSY;
1138 if (skb->ip_summed == CHECKSUM_PARTIAL)
1139 tx_ctrl.cksum_offload_flag = true;
1141 if (skb_is_gso(skb))
1142 tso_seg_len = skb_shinfo(skb)->gso_size;
1144 if (tso_seg_len > 0) {
1145 if (skb->protocol == htons(ETH_P_IP)) {
1146 ip_hdr(skb)->tot_len = 0;
1147 tcp_hdr(skb)->check =
1148 ~tcp_v4_check(0, ip_hdr(skb)->saddr,
1149 ip_hdr(skb)->daddr, 0);
1151 ipv6_hdr(skb)->payload_len = 0;
1152 tcp_hdr(skb)->check =
1153 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
1154 &ipv6_hdr(skb)->daddr,
1158 tx_ctrl.tcp_seg_offload_flag = true;
1159 tx_ctrl.tcp_seg_len = tso_seg_len;
1162 tx_desc.dma_addr = dma_map_single(priv->dev, skb->data,
1163 skb_headlen(skb), DMA_TO_DEVICE);
1164 if (dma_mapping_error(priv->dev, tx_desc.dma_addr)) {
1165 spin_unlock_bh(&dring->lock);
1166 netif_err(priv, drv, priv->ndev,
1167 "%s: DMA mapping failed\n", __func__);
1168 ndev->stats.tx_dropped++;
1169 dev_kfree_skb_any(skb);
1170 return NETDEV_TX_OK;
1172 tx_desc.addr = skb->data;
1173 tx_desc.len = skb_headlen(skb);
1174 tx_desc.buf_type = TYPE_NETSEC_SKB;
1176 skb_tx_timestamp(skb);
1177 netdev_sent_queue(priv->ndev, skb->len);
1179 netsec_set_tx_de(priv, dring, &tx_ctrl, &tx_desc, skb);
1180 spin_unlock_bh(&dring->lock);
1181 netsec_write(priv, NETSEC_REG_NRM_TX_PKTCNT, 1); /* submit another tx */
1183 return NETDEV_TX_OK;
1186 static void netsec_uninit_pkt_dring(struct netsec_priv *priv, int id)
1188 struct netsec_desc_ring *dring = &priv->desc_ring[id];
1189 struct netsec_desc *desc;
1192 if (!dring->vaddr || !dring->desc)
1194 for (idx = 0; idx < DESC_NUM; idx++) {
1195 desc = &dring->desc[idx];
1199 if (id == NETSEC_RING_RX) {
1200 struct page *page = virt_to_page(desc->addr);
1202 page_pool_put_page(dring->page_pool, page, false);
1203 } else if (id == NETSEC_RING_TX) {
1204 dma_unmap_single(priv->dev, desc->dma_addr, desc->len,
1206 dev_kfree_skb(desc->skb);
1210 /* Rx is currently using page_pool */
1211 if (id == NETSEC_RING_RX) {
1212 if (xdp_rxq_info_is_reg(&dring->xdp_rxq))
1213 xdp_rxq_info_unreg(&dring->xdp_rxq);
1214 page_pool_destroy(dring->page_pool);
1217 memset(dring->desc, 0, sizeof(struct netsec_desc) * DESC_NUM);
1218 memset(dring->vaddr, 0, DESC_SZ * DESC_NUM);
1223 if (id == NETSEC_RING_TX)
1224 netdev_reset_queue(priv->ndev);
1227 static void netsec_free_dring(struct netsec_priv *priv, int id)
1229 struct netsec_desc_ring *dring = &priv->desc_ring[id];
1232 dma_free_coherent(priv->dev, DESC_SZ * DESC_NUM,
1233 dring->vaddr, dring->desc_dma);
1234 dring->vaddr = NULL;
1241 static int netsec_alloc_dring(struct netsec_priv *priv, enum ring_id id)
1243 struct netsec_desc_ring *dring = &priv->desc_ring[id];
1245 dring->vaddr = dma_alloc_coherent(priv->dev, DESC_SZ * DESC_NUM,
1246 &dring->desc_dma, GFP_KERNEL);
1250 dring->desc = kcalloc(DESC_NUM, sizeof(*dring->desc), GFP_KERNEL);
1256 netsec_free_dring(priv, id);
1261 static void netsec_setup_tx_dring(struct netsec_priv *priv)
1263 struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_TX];
1266 for (i = 0; i < DESC_NUM; i++) {
1267 struct netsec_de *de;
1269 de = dring->vaddr + (DESC_SZ * i);
1270 /* de->attr is not going to be accessed by the NIC
1271 * until netsec_set_tx_de() is called.
1272 * No need for a dma_wmb() here
1274 de->attr = 1U << NETSEC_TX_SHIFT_OWN_FIELD;
1278 static int netsec_setup_rx_dring(struct netsec_priv *priv)
1280 struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_RX];
1281 struct bpf_prog *xdp_prog = READ_ONCE(priv->xdp_prog);
1282 struct page_pool_params pp_params = {
1284 /* internal DMA mapping in page_pool */
1285 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV,
1286 .pool_size = DESC_NUM,
1287 .nid = NUMA_NO_NODE,
1289 .dma_dir = xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE,
1290 .offset = NETSEC_RXBUF_HEADROOM,
1291 .max_len = NETSEC_RX_BUF_SIZE,
1295 dring->page_pool = page_pool_create(&pp_params);
1296 if (IS_ERR(dring->page_pool)) {
1297 err = PTR_ERR(dring->page_pool);
1298 dring->page_pool = NULL;
1302 err = xdp_rxq_info_reg(&dring->xdp_rxq, priv->ndev, 0);
1306 err = xdp_rxq_info_reg_mem_model(&dring->xdp_rxq, MEM_TYPE_PAGE_POOL,
1311 for (i = 0; i < DESC_NUM; i++) {
1312 struct netsec_desc *desc = &dring->desc[i];
1313 dma_addr_t dma_handle;
1317 buf = netsec_alloc_rx_data(priv, &dma_handle, &len);
1323 desc->dma_addr = dma_handle;
1328 netsec_rx_fill(priv, 0, DESC_NUM);
1333 netsec_uninit_pkt_dring(priv, NETSEC_RING_RX);
1337 static int netsec_netdev_load_ucode_region(struct netsec_priv *priv, u32 reg,
1338 u32 addr_h, u32 addr_l, u32 size)
1340 u64 base = (u64)addr_h << 32 | addr_l;
1341 void __iomem *ucode;
1344 ucode = ioremap(base, size * sizeof(u32));
1348 for (i = 0; i < size; i++)
1349 netsec_write(priv, reg, readl(ucode + i * 4));
1355 static int netsec_netdev_load_microcode(struct netsec_priv *priv)
1357 u32 addr_h, addr_l, size;
1360 addr_h = readl(priv->eeprom_base + NETSEC_EEPROM_HM_ME_ADDRESS_H);
1361 addr_l = readl(priv->eeprom_base + NETSEC_EEPROM_HM_ME_ADDRESS_L);
1362 size = readl(priv->eeprom_base + NETSEC_EEPROM_HM_ME_SIZE);
1363 err = netsec_netdev_load_ucode_region(priv, NETSEC_REG_DMAC_HM_CMD_BUF,
1364 addr_h, addr_l, size);
1368 addr_h = readl(priv->eeprom_base + NETSEC_EEPROM_MH_ME_ADDRESS_H);
1369 addr_l = readl(priv->eeprom_base + NETSEC_EEPROM_MH_ME_ADDRESS_L);
1370 size = readl(priv->eeprom_base + NETSEC_EEPROM_MH_ME_SIZE);
1371 err = netsec_netdev_load_ucode_region(priv, NETSEC_REG_DMAC_MH_CMD_BUF,
1372 addr_h, addr_l, size);
1377 addr_l = readl(priv->eeprom_base + NETSEC_EEPROM_PKT_ME_ADDRESS);
1378 size = readl(priv->eeprom_base + NETSEC_EEPROM_PKT_ME_SIZE);
1379 err = netsec_netdev_load_ucode_region(priv, NETSEC_REG_PKT_CMD_BUF,
1380 addr_h, addr_l, size);
1387 static int netsec_reset_hardware(struct netsec_priv *priv,
1393 /* stop DMA engines */
1394 if (!netsec_read(priv, NETSEC_REG_ADDR_DIS_CORE)) {
1395 netsec_write(priv, NETSEC_REG_DMA_HM_CTRL,
1396 NETSEC_DMA_CTRL_REG_STOP);
1397 netsec_write(priv, NETSEC_REG_DMA_MH_CTRL,
1398 NETSEC_DMA_CTRL_REG_STOP);
1400 while (netsec_read(priv, NETSEC_REG_DMA_HM_CTRL) &
1401 NETSEC_DMA_CTRL_REG_STOP)
1404 while (netsec_read(priv, NETSEC_REG_DMA_MH_CTRL) &
1405 NETSEC_DMA_CTRL_REG_STOP)
1409 netsec_write(priv, NETSEC_REG_SOFT_RST, NETSEC_SOFT_RST_REG_RESET);
1410 netsec_write(priv, NETSEC_REG_SOFT_RST, NETSEC_SOFT_RST_REG_RUN);
1411 netsec_write(priv, NETSEC_REG_COM_INIT, NETSEC_COM_INIT_REG_ALL);
1413 while (netsec_read(priv, NETSEC_REG_COM_INIT) != 0)
1416 /* set desc_start addr */
1417 netsec_write(priv, NETSEC_REG_NRM_RX_DESC_START_UP,
1418 upper_32_bits(priv->desc_ring[NETSEC_RING_RX].desc_dma));
1419 netsec_write(priv, NETSEC_REG_NRM_RX_DESC_START_LW,
1420 lower_32_bits(priv->desc_ring[NETSEC_RING_RX].desc_dma));
1422 netsec_write(priv, NETSEC_REG_NRM_TX_DESC_START_UP,
1423 upper_32_bits(priv->desc_ring[NETSEC_RING_TX].desc_dma));
1424 netsec_write(priv, NETSEC_REG_NRM_TX_DESC_START_LW,
1425 lower_32_bits(priv->desc_ring[NETSEC_RING_TX].desc_dma));
1427 /* set normal tx dring ring config */
1428 netsec_write(priv, NETSEC_REG_NRM_TX_CONFIG,
1429 1 << NETSEC_REG_DESC_ENDIAN);
1430 netsec_write(priv, NETSEC_REG_NRM_RX_CONFIG,
1431 1 << NETSEC_REG_DESC_ENDIAN);
1434 err = netsec_netdev_load_microcode(priv);
1436 netif_err(priv, probe, priv->ndev,
1437 "%s: failed to load microcode (%d)\n",
1443 /* start DMA engines */
1444 netsec_write(priv, NETSEC_REG_DMA_TMR_CTRL, priv->freq / 1000000 - 1);
1445 netsec_write(priv, NETSEC_REG_ADDR_DIS_CORE, 0);
1447 usleep_range(1000, 2000);
1449 if (!(netsec_read(priv, NETSEC_REG_TOP_STATUS) &
1450 NETSEC_TOP_IRQ_REG_CODE_LOAD_END)) {
1451 netif_err(priv, probe, priv->ndev,
1452 "microengine start failed\n");
1455 netsec_write(priv, NETSEC_REG_TOP_STATUS,
1456 NETSEC_TOP_IRQ_REG_CODE_LOAD_END);
1458 value = NETSEC_PKT_CTRL_REG_MODE_NRM;
1459 if (priv->ndev->mtu > ETH_DATA_LEN)
1460 value |= NETSEC_PKT_CTRL_REG_EN_JUMBO;
1462 /* change to normal mode */
1463 netsec_write(priv, NETSEC_REG_DMA_MH_CTRL, MH_CTRL__MODE_TRANS);
1464 netsec_write(priv, NETSEC_REG_PKT_CTRL, value);
1466 while ((netsec_read(priv, NETSEC_REG_MODE_TRANS_COMP_STATUS) &
1467 NETSEC_MODE_TRANS_COMP_IRQ_T2N) == 0)
1470 /* clear any pending EMPTY/ERR irq status */
1471 netsec_write(priv, NETSEC_REG_NRM_TX_STATUS, ~0);
1473 /* Disable TX & RX intr */
1474 netsec_write(priv, NETSEC_REG_INTEN_CLR, ~0);
1479 static int netsec_start_gmac(struct netsec_priv *priv)
1481 struct phy_device *phydev = priv->ndev->phydev;
1485 if (phydev->speed != SPEED_1000)
1486 value = (NETSEC_GMAC_MCR_REG_CST |
1487 NETSEC_GMAC_MCR_REG_HALF_DUPLEX_COMMON);
1489 if (netsec_mac_write(priv, GMAC_REG_MCR, value))
1491 if (netsec_mac_write(priv, GMAC_REG_BMR,
1492 NETSEC_GMAC_BMR_REG_RESET))
1495 /* Wait soft reset */
1496 usleep_range(1000, 5000);
1498 ret = netsec_mac_read(priv, GMAC_REG_BMR, &value);
1501 if (value & NETSEC_GMAC_BMR_REG_SWR)
1504 netsec_write(priv, MAC_REG_DESC_SOFT_RST, 1);
1505 if (netsec_wait_while_busy(priv, MAC_REG_DESC_SOFT_RST, 1))
1508 netsec_write(priv, MAC_REG_DESC_INIT, 1);
1509 if (netsec_wait_while_busy(priv, MAC_REG_DESC_INIT, 1))
1512 if (netsec_mac_write(priv, GMAC_REG_BMR,
1513 NETSEC_GMAC_BMR_REG_COMMON))
1515 if (netsec_mac_write(priv, GMAC_REG_RDLAR,
1516 NETSEC_GMAC_RDLAR_REG_COMMON))
1518 if (netsec_mac_write(priv, GMAC_REG_TDLAR,
1519 NETSEC_GMAC_TDLAR_REG_COMMON))
1521 if (netsec_mac_write(priv, GMAC_REG_MFFR, 0x80000001))
1524 ret = netsec_mac_update_to_phy_state(priv);
1528 ret = netsec_mac_read(priv, GMAC_REG_OMR, &value);
1532 value |= NETSEC_GMAC_OMR_REG_SR;
1533 value |= NETSEC_GMAC_OMR_REG_ST;
1535 netsec_write(priv, NETSEC_REG_NRM_RX_INTEN_CLR, ~0);
1536 netsec_write(priv, NETSEC_REG_NRM_TX_INTEN_CLR, ~0);
1538 netsec_et_set_coalesce(priv->ndev, &priv->et_coalesce);
1540 if (netsec_mac_write(priv, GMAC_REG_OMR, value))
1546 static int netsec_stop_gmac(struct netsec_priv *priv)
1551 ret = netsec_mac_read(priv, GMAC_REG_OMR, &value);
1554 value &= ~NETSEC_GMAC_OMR_REG_SR;
1555 value &= ~NETSEC_GMAC_OMR_REG_ST;
1557 /* disable all interrupts */
1558 netsec_write(priv, NETSEC_REG_NRM_RX_INTEN_CLR, ~0);
1559 netsec_write(priv, NETSEC_REG_NRM_TX_INTEN_CLR, ~0);
1561 return netsec_mac_write(priv, GMAC_REG_OMR, value);
1564 static void netsec_phy_adjust_link(struct net_device *ndev)
1566 struct netsec_priv *priv = netdev_priv(ndev);
1568 if (ndev->phydev->link)
1569 netsec_start_gmac(priv);
1571 netsec_stop_gmac(priv);
1573 phy_print_status(ndev->phydev);
1576 static irqreturn_t netsec_irq_handler(int irq, void *dev_id)
1578 struct netsec_priv *priv = dev_id;
1579 u32 val, status = netsec_read(priv, NETSEC_REG_TOP_STATUS);
1580 unsigned long flags;
1582 /* Disable interrupts */
1583 if (status & NETSEC_IRQ_TX) {
1584 val = netsec_read(priv, NETSEC_REG_NRM_TX_STATUS);
1585 netsec_write(priv, NETSEC_REG_NRM_TX_STATUS, val);
1587 if (status & NETSEC_IRQ_RX) {
1588 val = netsec_read(priv, NETSEC_REG_NRM_RX_STATUS);
1589 netsec_write(priv, NETSEC_REG_NRM_RX_STATUS, val);
1592 spin_lock_irqsave(&priv->reglock, flags);
1593 netsec_write(priv, NETSEC_REG_INTEN_CLR, NETSEC_IRQ_RX | NETSEC_IRQ_TX);
1594 spin_unlock_irqrestore(&priv->reglock, flags);
1596 napi_schedule(&priv->napi);
1601 static int netsec_netdev_open(struct net_device *ndev)
1603 struct netsec_priv *priv = netdev_priv(ndev);
1606 pm_runtime_get_sync(priv->dev);
1608 netsec_setup_tx_dring(priv);
1609 ret = netsec_setup_rx_dring(priv);
1611 netif_err(priv, probe, priv->ndev,
1612 "%s: fail setup ring\n", __func__);
1616 ret = request_irq(priv->ndev->irq, netsec_irq_handler,
1617 IRQF_SHARED, "netsec", priv);
1619 netif_err(priv, drv, priv->ndev, "request_irq failed\n");
1623 if (dev_of_node(priv->dev)) {
1624 if (!of_phy_connect(priv->ndev, priv->phy_np,
1625 netsec_phy_adjust_link, 0,
1626 priv->phy_interface)) {
1627 netif_err(priv, link, priv->ndev, "missing PHY\n");
1632 ret = phy_connect_direct(priv->ndev, priv->phydev,
1633 netsec_phy_adjust_link,
1634 priv->phy_interface);
1636 netif_err(priv, link, priv->ndev,
1637 "phy_connect_direct() failed (%d)\n", ret);
1642 phy_start(ndev->phydev);
1644 netsec_start_gmac(priv);
1645 napi_enable(&priv->napi);
1646 netif_start_queue(ndev);
1648 /* Enable TX+RX intr. */
1649 netsec_write(priv, NETSEC_REG_INTEN_SET, NETSEC_IRQ_RX | NETSEC_IRQ_TX);
1653 free_irq(priv->ndev->irq, priv);
1655 netsec_uninit_pkt_dring(priv, NETSEC_RING_RX);
1657 pm_runtime_put_sync(priv->dev);
1661 static int netsec_netdev_stop(struct net_device *ndev)
1664 struct netsec_priv *priv = netdev_priv(ndev);
1666 netif_stop_queue(priv->ndev);
1669 napi_disable(&priv->napi);
1671 netsec_write(priv, NETSEC_REG_INTEN_CLR, ~0);
1672 netsec_stop_gmac(priv);
1674 free_irq(priv->ndev->irq, priv);
1676 netsec_uninit_pkt_dring(priv, NETSEC_RING_TX);
1677 netsec_uninit_pkt_dring(priv, NETSEC_RING_RX);
1679 phy_stop(ndev->phydev);
1680 phy_disconnect(ndev->phydev);
1682 ret = netsec_reset_hardware(priv, false);
1684 pm_runtime_put_sync(priv->dev);
1689 static int netsec_netdev_init(struct net_device *ndev)
1691 struct netsec_priv *priv = netdev_priv(ndev);
1695 BUILD_BUG_ON_NOT_POWER_OF_2(DESC_NUM);
1697 ret = netsec_alloc_dring(priv, NETSEC_RING_TX);
1701 ret = netsec_alloc_dring(priv, NETSEC_RING_RX);
1705 /* set phy power down */
1706 data = netsec_phy_read(priv->mii_bus, priv->phy_addr, MII_BMCR) |
1708 netsec_phy_write(priv->mii_bus, priv->phy_addr, MII_BMCR, data);
1710 ret = netsec_reset_hardware(priv, true);
1714 spin_lock_init(&priv->desc_ring[NETSEC_RING_TX].lock);
1715 spin_lock_init(&priv->desc_ring[NETSEC_RING_RX].lock);
1719 netsec_free_dring(priv, NETSEC_RING_RX);
1721 netsec_free_dring(priv, NETSEC_RING_TX);
1725 static void netsec_netdev_uninit(struct net_device *ndev)
1727 struct netsec_priv *priv = netdev_priv(ndev);
1729 netsec_free_dring(priv, NETSEC_RING_RX);
1730 netsec_free_dring(priv, NETSEC_RING_TX);
1733 static int netsec_netdev_set_features(struct net_device *ndev,
1734 netdev_features_t features)
1736 struct netsec_priv *priv = netdev_priv(ndev);
1738 priv->rx_cksum_offload_flag = !!(features & NETIF_F_RXCSUM);
1743 static int netsec_xdp_xmit(struct net_device *ndev, int n,
1744 struct xdp_frame **frames, u32 flags)
1746 struct netsec_priv *priv = netdev_priv(ndev);
1747 struct netsec_desc_ring *tx_ring = &priv->desc_ring[NETSEC_RING_TX];
1751 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK))
1754 spin_lock(&tx_ring->lock);
1755 for (i = 0; i < n; i++) {
1756 struct xdp_frame *xdpf = frames[i];
1759 err = netsec_xdp_queue_one(priv, xdpf, true);
1760 if (err != NETSEC_XDP_TX) {
1761 xdp_return_frame_rx_napi(xdpf);
1764 tx_ring->xdp_xmit++;
1767 spin_unlock(&tx_ring->lock);
1769 if (unlikely(flags & XDP_XMIT_FLUSH)) {
1770 netsec_xdp_ring_tx_db(priv, tx_ring->xdp_xmit);
1771 tx_ring->xdp_xmit = 0;
1777 static int netsec_xdp_setup(struct netsec_priv *priv, struct bpf_prog *prog,
1778 struct netlink_ext_ack *extack)
1780 struct net_device *dev = priv->ndev;
1781 struct bpf_prog *old_prog;
1783 /* For now just support only the usual MTU sized frames */
1784 if (prog && dev->mtu > 1500) {
1785 NL_SET_ERR_MSG_MOD(extack, "Jumbo frames not supported on XDP");
1789 if (netif_running(dev))
1790 netsec_netdev_stop(dev);
1792 /* Detach old prog, if any */
1793 old_prog = xchg(&priv->xdp_prog, prog);
1795 bpf_prog_put(old_prog);
1797 if (netif_running(dev))
1798 netsec_netdev_open(dev);
1803 static int netsec_xdp(struct net_device *ndev, struct netdev_bpf *xdp)
1805 struct netsec_priv *priv = netdev_priv(ndev);
1807 switch (xdp->command) {
1808 case XDP_SETUP_PROG:
1809 return netsec_xdp_setup(priv, xdp->prog, xdp->extack);
1810 case XDP_QUERY_PROG:
1811 xdp->prog_id = priv->xdp_prog ? priv->xdp_prog->aux->id : 0;
1818 static const struct net_device_ops netsec_netdev_ops = {
1819 .ndo_init = netsec_netdev_init,
1820 .ndo_uninit = netsec_netdev_uninit,
1821 .ndo_open = netsec_netdev_open,
1822 .ndo_stop = netsec_netdev_stop,
1823 .ndo_start_xmit = netsec_netdev_start_xmit,
1824 .ndo_set_features = netsec_netdev_set_features,
1825 .ndo_set_mac_address = eth_mac_addr,
1826 .ndo_validate_addr = eth_validate_addr,
1827 .ndo_do_ioctl = phy_do_ioctl,
1828 .ndo_xdp_xmit = netsec_xdp_xmit,
1829 .ndo_bpf = netsec_xdp,
1832 static int netsec_of_probe(struct platform_device *pdev,
1833 struct netsec_priv *priv, u32 *phy_addr)
1835 priv->phy_np = of_parse_phandle(pdev->dev.of_node, "phy-handle", 0);
1836 if (!priv->phy_np) {
1837 dev_err(&pdev->dev, "missing required property 'phy-handle'\n");
1841 *phy_addr = of_mdio_parse_addr(&pdev->dev, priv->phy_np);
1843 priv->clk = devm_clk_get(&pdev->dev, NULL); /* get by 'phy_ref_clk' */
1844 if (IS_ERR(priv->clk)) {
1845 dev_err(&pdev->dev, "phy_ref_clk not found\n");
1846 return PTR_ERR(priv->clk);
1848 priv->freq = clk_get_rate(priv->clk);
1853 static int netsec_acpi_probe(struct platform_device *pdev,
1854 struct netsec_priv *priv, u32 *phy_addr)
1858 if (!IS_ENABLED(CONFIG_ACPI))
1861 ret = device_property_read_u32(&pdev->dev, "phy-channel", phy_addr);
1864 "missing required property 'phy-channel'\n");
1868 ret = device_property_read_u32(&pdev->dev,
1869 "socionext,phy-clock-frequency",
1873 "missing required property 'socionext,phy-clock-frequency'\n");
1877 static void netsec_unregister_mdio(struct netsec_priv *priv)
1879 struct phy_device *phydev = priv->phydev;
1881 if (!dev_of_node(priv->dev) && phydev) {
1882 phy_device_remove(phydev);
1883 phy_device_free(phydev);
1886 mdiobus_unregister(priv->mii_bus);
1889 static int netsec_register_mdio(struct netsec_priv *priv, u32 phy_addr)
1891 struct mii_bus *bus;
1894 bus = devm_mdiobus_alloc(priv->dev);
1898 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", dev_name(priv->dev));
1900 bus->name = "SNI NETSEC MDIO";
1901 bus->read = netsec_phy_read;
1902 bus->write = netsec_phy_write;
1903 bus->parent = priv->dev;
1904 priv->mii_bus = bus;
1906 if (dev_of_node(priv->dev)) {
1907 struct device_node *mdio_node, *parent = dev_of_node(priv->dev);
1909 mdio_node = of_get_child_by_name(parent, "mdio");
1913 /* older f/w doesn't populate the mdio subnode,
1914 * allow relaxed upgrade of f/w in due time.
1916 dev_info(priv->dev, "Upgrade f/w for mdio subnode!\n");
1919 ret = of_mdiobus_register(bus, parent);
1920 of_node_put(mdio_node);
1923 dev_err(priv->dev, "mdiobus register err(%d)\n", ret);
1927 /* Mask out all PHYs from auto probing. */
1929 ret = mdiobus_register(bus);
1931 dev_err(priv->dev, "mdiobus register err(%d)\n", ret);
1935 priv->phydev = get_phy_device(bus, phy_addr, false);
1936 if (IS_ERR(priv->phydev)) {
1937 ret = PTR_ERR(priv->phydev);
1938 dev_err(priv->dev, "get_phy_device err(%d)\n", ret);
1939 priv->phydev = NULL;
1943 ret = phy_device_register(priv->phydev);
1945 mdiobus_unregister(bus);
1947 "phy_device_register err(%d)\n", ret);
1954 static int netsec_probe(struct platform_device *pdev)
1956 struct resource *mmio_res, *eeprom_res, *irq_res;
1957 u8 *mac, macbuf[ETH_ALEN];
1958 struct netsec_priv *priv;
1959 u32 hw_ver, phy_addr = 0;
1960 struct net_device *ndev;
1963 mmio_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1965 dev_err(&pdev->dev, "No MMIO resource found.\n");
1969 eeprom_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1971 dev_info(&pdev->dev, "No EEPROM resource found.\n");
1975 irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1977 dev_err(&pdev->dev, "No IRQ resource found.\n");
1981 ndev = alloc_etherdev(sizeof(*priv));
1985 priv = netdev_priv(ndev);
1987 spin_lock_init(&priv->reglock);
1988 SET_NETDEV_DEV(ndev, &pdev->dev);
1989 platform_set_drvdata(pdev, priv);
1990 ndev->irq = irq_res->start;
1991 priv->dev = &pdev->dev;
1994 priv->msg_enable = NETIF_MSG_TX_ERR | NETIF_MSG_HW | NETIF_MSG_DRV |
1995 NETIF_MSG_LINK | NETIF_MSG_PROBE;
1997 priv->phy_interface = device_get_phy_mode(&pdev->dev);
1998 if ((int)priv->phy_interface < 0) {
1999 dev_err(&pdev->dev, "missing required property 'phy-mode'\n");
2004 priv->ioaddr = devm_ioremap(&pdev->dev, mmio_res->start,
2005 resource_size(mmio_res));
2006 if (!priv->ioaddr) {
2007 dev_err(&pdev->dev, "devm_ioremap() failed\n");
2012 priv->eeprom_base = devm_ioremap(&pdev->dev, eeprom_res->start,
2013 resource_size(eeprom_res));
2014 if (!priv->eeprom_base) {
2015 dev_err(&pdev->dev, "devm_ioremap() failed for EEPROM\n");
2020 mac = device_get_mac_address(&pdev->dev, macbuf, sizeof(macbuf));
2022 ether_addr_copy(ndev->dev_addr, mac);
2024 if (priv->eeprom_base &&
2025 (!mac || !is_valid_ether_addr(ndev->dev_addr))) {
2026 void __iomem *macp = priv->eeprom_base +
2027 NETSEC_EEPROM_MAC_ADDRESS;
2029 ndev->dev_addr[0] = readb(macp + 3);
2030 ndev->dev_addr[1] = readb(macp + 2);
2031 ndev->dev_addr[2] = readb(macp + 1);
2032 ndev->dev_addr[3] = readb(macp + 0);
2033 ndev->dev_addr[4] = readb(macp + 7);
2034 ndev->dev_addr[5] = readb(macp + 6);
2037 if (!is_valid_ether_addr(ndev->dev_addr)) {
2038 dev_warn(&pdev->dev, "No MAC address found, using random\n");
2039 eth_hw_addr_random(ndev);
2042 if (dev_of_node(&pdev->dev))
2043 ret = netsec_of_probe(pdev, priv, &phy_addr);
2045 ret = netsec_acpi_probe(pdev, priv, &phy_addr);
2049 priv->phy_addr = phy_addr;
2052 dev_err(&pdev->dev, "missing PHY reference clock frequency\n");
2057 /* default for throughput */
2058 priv->et_coalesce.rx_coalesce_usecs = 500;
2059 priv->et_coalesce.rx_max_coalesced_frames = 8;
2060 priv->et_coalesce.tx_coalesce_usecs = 500;
2061 priv->et_coalesce.tx_max_coalesced_frames = 8;
2063 ret = device_property_read_u32(&pdev->dev, "max-frame-size",
2066 ndev->max_mtu = ETH_DATA_LEN;
2068 /* runtime_pm coverage just for probe, open/close also cover it */
2069 pm_runtime_enable(&pdev->dev);
2070 pm_runtime_get_sync(&pdev->dev);
2072 hw_ver = netsec_read(priv, NETSEC_REG_F_TAIKI_VER);
2073 /* this driver only supports F_TAIKI style NETSEC */
2074 if (NETSEC_F_NETSEC_VER_MAJOR_NUM(hw_ver) !=
2075 NETSEC_F_NETSEC_VER_MAJOR_NUM(NETSEC_REG_NETSEC_VER_F_TAIKI)) {
2080 dev_info(&pdev->dev, "hardware revision %d.%d\n",
2081 hw_ver >> 16, hw_ver & 0xffff);
2083 netif_napi_add(ndev, &priv->napi, netsec_napi_poll, NAPI_POLL_WEIGHT);
2085 ndev->netdev_ops = &netsec_netdev_ops;
2086 ndev->ethtool_ops = &netsec_ethtool_ops;
2088 ndev->features |= NETIF_F_HIGHDMA | NETIF_F_RXCSUM | NETIF_F_GSO |
2089 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
2090 ndev->hw_features = ndev->features;
2092 priv->rx_cksum_offload_flag = true;
2094 ret = netsec_register_mdio(priv, phy_addr);
2098 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(40)))
2099 dev_warn(&pdev->dev, "Failed to set DMA mask\n");
2101 ret = register_netdev(ndev);
2103 netif_err(priv, probe, ndev, "register_netdev() failed\n");
2107 pm_runtime_put_sync(&pdev->dev);
2111 netsec_unregister_mdio(priv);
2113 netif_napi_del(&priv->napi);
2115 pm_runtime_put_sync(&pdev->dev);
2116 pm_runtime_disable(&pdev->dev);
2119 dev_err(&pdev->dev, "init failed\n");
2124 static int netsec_remove(struct platform_device *pdev)
2126 struct netsec_priv *priv = platform_get_drvdata(pdev);
2128 unregister_netdev(priv->ndev);
2130 netsec_unregister_mdio(priv);
2132 netif_napi_del(&priv->napi);
2134 pm_runtime_disable(&pdev->dev);
2135 free_netdev(priv->ndev);
2141 static int netsec_runtime_suspend(struct device *dev)
2143 struct netsec_priv *priv = dev_get_drvdata(dev);
2145 netsec_write(priv, NETSEC_REG_CLK_EN, 0);
2147 clk_disable_unprepare(priv->clk);
2152 static int netsec_runtime_resume(struct device *dev)
2154 struct netsec_priv *priv = dev_get_drvdata(dev);
2156 clk_prepare_enable(priv->clk);
2158 netsec_write(priv, NETSEC_REG_CLK_EN, NETSEC_CLK_EN_REG_DOM_D |
2159 NETSEC_CLK_EN_REG_DOM_C |
2160 NETSEC_CLK_EN_REG_DOM_G);
2165 static const struct dev_pm_ops netsec_pm_ops = {
2166 SET_RUNTIME_PM_OPS(netsec_runtime_suspend, netsec_runtime_resume, NULL)
2169 static const struct of_device_id netsec_dt_ids[] = {
2170 { .compatible = "socionext,synquacer-netsec" },
2173 MODULE_DEVICE_TABLE(of, netsec_dt_ids);
2176 static const struct acpi_device_id netsec_acpi_ids[] = {
2180 MODULE_DEVICE_TABLE(acpi, netsec_acpi_ids);
2183 static struct platform_driver netsec_driver = {
2184 .probe = netsec_probe,
2185 .remove = netsec_remove,
2188 .pm = &netsec_pm_ops,
2189 .of_match_table = netsec_dt_ids,
2190 .acpi_match_table = ACPI_PTR(netsec_acpi_ids),
2193 module_platform_driver(netsec_driver);
2195 MODULE_AUTHOR("Jassi Brar <jaswinder.singh@linaro.org>");
2196 MODULE_AUTHOR("Ard Biesheuvel <ard.biesheuvel@linaro.org>");
2197 MODULE_DESCRIPTION("NETSEC Ethernet driver");
2198 MODULE_LICENSE("GPL");