drivers/net/ethernet/socionext/netsec.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2
   3 #include <linux/types.h>
   4 #include <linux/clk.h>
   5 #include <linux/platform_device.h>
   6 #include <linux/pm_runtime.h>
   7 #include <linux/acpi.h>
   8 #include <linux/of_mdio.h>
   9 #include <linux/etherdevice.h>
  10 #include <linux/interrupt.h>
  11 #include <linux/io.h>
  12
  13 #include <net/tcp.h>
  14 #include <net/ip6_checksum.h>
  15
  16 #define NETSEC_REG_SOFT_RST                     0x104
  17 #define NETSEC_REG_COM_INIT                     0x120
  18
  19 #define NETSEC_REG_TOP_STATUS                   0x200
  20 #define NETSEC_IRQ_RX                           BIT(1)
  21 #define NETSEC_IRQ_TX                           BIT(0)
  22
  23 #define NETSEC_REG_TOP_INTEN                    0x204
  24 #define NETSEC_REG_INTEN_SET                    0x234
  25 #define NETSEC_REG_INTEN_CLR                    0x238
  26
  27 #define NETSEC_REG_NRM_TX_STATUS                0x400
  28 #define NETSEC_REG_NRM_TX_INTEN                 0x404
  29 #define NETSEC_REG_NRM_TX_INTEN_SET             0x428
  30 #define NETSEC_REG_NRM_TX_INTEN_CLR             0x42c
  31 #define NRM_TX_ST_NTOWNR        BIT(17)
  32 #define NRM_TX_ST_TR_ERR        BIT(16)
  33 #define NRM_TX_ST_TXDONE        BIT(15)
  34 #define NRM_TX_ST_TMREXP        BIT(14)
  35
  36 #define NETSEC_REG_NRM_RX_STATUS                0x440
  37 #define NETSEC_REG_NRM_RX_INTEN                 0x444
  38 #define NETSEC_REG_NRM_RX_INTEN_SET             0x468
  39 #define NETSEC_REG_NRM_RX_INTEN_CLR             0x46c
  40 #define NRM_RX_ST_RC_ERR        BIT(16)
  41 #define NRM_RX_ST_PKTCNT        BIT(15)
  42 #define NRM_RX_ST_TMREXP        BIT(14)
  43
  44 #define NETSEC_REG_PKT_CMD_BUF                  0xd0
  45
  46 #define NETSEC_REG_CLK_EN                       0x100
  47
  48 #define NETSEC_REG_PKT_CTRL                     0x140
  49
  50 #define NETSEC_REG_DMA_TMR_CTRL                 0x20c
  51 #define NETSEC_REG_F_TAIKI_MC_VER               0x22c
  52 #define NETSEC_REG_F_TAIKI_VER                  0x230
  53 #define NETSEC_REG_DMA_HM_CTRL                  0x214
  54 #define NETSEC_REG_DMA_MH_CTRL                  0x220
  55 #define NETSEC_REG_ADDR_DIS_CORE                0x218
  56 #define NETSEC_REG_DMAC_HM_CMD_BUF              0x210
  57 #define NETSEC_REG_DMAC_MH_CMD_BUF              0x21c
  58
  59 #define NETSEC_REG_NRM_TX_PKTCNT                0x410
  60
  61 #define NETSEC_REG_NRM_TX_DONE_PKTCNT           0x414
  62 #define NETSEC_REG_NRM_TX_DONE_TXINT_PKTCNT     0x418
  63
  64 #define NETSEC_REG_NRM_TX_TMR                   0x41c
  65
  66 #define NETSEC_REG_NRM_RX_PKTCNT                0x454
  67 #define NETSEC_REG_NRM_RX_RXINT_PKTCNT          0x458
  68 #define NETSEC_REG_NRM_TX_TXINT_TMR             0x420
  69 #define NETSEC_REG_NRM_RX_RXINT_TMR             0x460
  70
  71 #define NETSEC_REG_NRM_RX_TMR                   0x45c
  72
  73 #define NETSEC_REG_NRM_TX_DESC_START_UP         0x434
  74 #define NETSEC_REG_NRM_TX_DESC_START_LW         0x408
  75 #define NETSEC_REG_NRM_RX_DESC_START_UP         0x474
  76 #define NETSEC_REG_NRM_RX_DESC_START_LW         0x448
  77
  78 #define NETSEC_REG_NRM_TX_CONFIG                0x430
  79 #define NETSEC_REG_NRM_RX_CONFIG                0x470
  80
  81 #define MAC_REG_STATUS                          0x1024
  82 #define MAC_REG_DATA                            0x11c0
  83 #define MAC_REG_CMD                             0x11c4
  84 #define MAC_REG_FLOW_TH                         0x11cc
  85 #define MAC_REG_INTF_SEL                        0x11d4
  86 #define MAC_REG_DESC_INIT                       0x11fc
  87 #define MAC_REG_DESC_SOFT_RST                   0x1204
  88 #define NETSEC_REG_MODE_TRANS_COMP_STATUS       0x500
  89
  90 #define GMAC_REG_MCR                            0x0000
  91 #define GMAC_REG_MFFR                           0x0004
  92 #define GMAC_REG_GAR                            0x0010
  93 #define GMAC_REG_GDR                            0x0014
  94 #define GMAC_REG_FCR                            0x0018
  95 #define GMAC_REG_BMR                            0x1000
  96 #define GMAC_REG_RDLAR                          0x100c
  97 #define GMAC_REG_TDLAR                          0x1010
  98 #define GMAC_REG_OMR                            0x1018
  99
 100 #define MHZ(n)          ((n) * 1000 * 1000)
 101
 102 #define NETSEC_TX_SHIFT_OWN_FIELD               31
 103 #define NETSEC_TX_SHIFT_LD_FIELD                30
 104 #define NETSEC_TX_SHIFT_DRID_FIELD              24
 105 #define NETSEC_TX_SHIFT_PT_FIELD                21
 106 #define NETSEC_TX_SHIFT_TDRID_FIELD             16
 107 #define NETSEC_TX_SHIFT_CC_FIELD                15
 108 #define NETSEC_TX_SHIFT_FS_FIELD                9
 109 #define NETSEC_TX_LAST                          8
 110 #define NETSEC_TX_SHIFT_CO                      7
 111 #define NETSEC_TX_SHIFT_SO                      6
 112 #define NETSEC_TX_SHIFT_TRS_FIELD               4
 113
 114 #define NETSEC_RX_PKT_OWN_FIELD                 31
 115 #define NETSEC_RX_PKT_LD_FIELD                  30
 116 #define NETSEC_RX_PKT_SDRID_FIELD               24
 117 #define NETSEC_RX_PKT_FR_FIELD                  23
 118 #define NETSEC_RX_PKT_ER_FIELD                  21
 119 #define NETSEC_RX_PKT_ERR_FIELD                 16
 120 #define NETSEC_RX_PKT_TDRID_FIELD               12
 121 #define NETSEC_RX_PKT_FS_FIELD                  9
 122 #define NETSEC_RX_PKT_LS_FIELD                  8
 123 #define NETSEC_RX_PKT_CO_FIELD                  6
 124
 125 #define NETSEC_RX_PKT_ERR_MASK                  3
 126
 127 #define NETSEC_MAX_TX_PKT_LEN                   1518
 128 #define NETSEC_MAX_TX_JUMBO_PKT_LEN             9018
 129
 130 #define NETSEC_RING_GMAC                        15
 131 #define NETSEC_RING_MAX                         2
 132
 133 #define NETSEC_TCP_SEG_LEN_MAX                  1460
 134 #define NETSEC_TCP_JUMBO_SEG_LEN_MAX            8960
 135
 136 #define NETSEC_RX_CKSUM_NOTAVAIL                0
 137 #define NETSEC_RX_CKSUM_OK                      1
 138 #define NETSEC_RX_CKSUM_NG                      2
 139
 140 #define NETSEC_TOP_IRQ_REG_CODE_LOAD_END        BIT(20)
 141 #define NETSEC_IRQ_TRANSITION_COMPLETE          BIT(4)
 142
 143 #define NETSEC_MODE_TRANS_COMP_IRQ_N2T          BIT(20)
 144 #define NETSEC_MODE_TRANS_COMP_IRQ_T2N          BIT(19)
 145
 146 #define NETSEC_INT_PKTCNT_MAX                   2047
 147
 148 #define NETSEC_FLOW_START_TH_MAX                95
 149 #define NETSEC_FLOW_STOP_TH_MAX                 95
 150 #define NETSEC_FLOW_PAUSE_TIME_MIN              5
 151
 152 #define NETSEC_CLK_EN_REG_DOM_ALL               0x3f
 153
 154 #define NETSEC_PKT_CTRL_REG_MODE_NRM            BIT(28)
 155 #define NETSEC_PKT_CTRL_REG_EN_JUMBO            BIT(27)
 156 #define NETSEC_PKT_CTRL_REG_LOG_CHKSUM_ER       BIT(3)
 157 #define NETSEC_PKT_CTRL_REG_LOG_HD_INCOMPLETE   BIT(2)
 158 #define NETSEC_PKT_CTRL_REG_LOG_HD_ER           BIT(1)
 159 #define NETSEC_PKT_CTRL_REG_DRP_NO_MATCH        BIT(0)
 160
 161 #define NETSEC_CLK_EN_REG_DOM_G                 BIT(5)
 162 #define NETSEC_CLK_EN_REG_DOM_C                 BIT(1)
 163 #define NETSEC_CLK_EN_REG_DOM_D                 BIT(0)
 164
 165 #define NETSEC_COM_INIT_REG_DB                  BIT(2)
 166 #define NETSEC_COM_INIT_REG_CLS                 BIT(1)
 167 #define NETSEC_COM_INIT_REG_ALL                 (NETSEC_COM_INIT_REG_CLS | \
 168                                                  NETSEC_COM_INIT_REG_DB)
 169
 170 #define NETSEC_SOFT_RST_REG_RESET               0
 171 #define NETSEC_SOFT_RST_REG_RUN                 BIT(31)
 172
 173 #define NETSEC_DMA_CTRL_REG_STOP                1
 174 #define MH_CTRL__MODE_TRANS                     BIT(20)
 175
 176 #define NETSEC_GMAC_CMD_ST_READ                 0
 177 #define NETSEC_GMAC_CMD_ST_WRITE                BIT(28)
 178 #define NETSEC_GMAC_CMD_ST_BUSY                 BIT(31)
 179
 180 #define NETSEC_GMAC_BMR_REG_COMMON              0x00412080
 181 #define NETSEC_GMAC_BMR_REG_RESET               0x00020181
 182 #define NETSEC_GMAC_BMR_REG_SWR                 0x00000001
 183
 184 #define NETSEC_GMAC_OMR_REG_ST                  BIT(13)
 185 #define NETSEC_GMAC_OMR_REG_SR                  BIT(1)
 186
 187 #define NETSEC_GMAC_MCR_REG_IBN                 BIT(30)
 188 #define NETSEC_GMAC_MCR_REG_CST                 BIT(25)
 189 #define NETSEC_GMAC_MCR_REG_JE                  BIT(20)
 190 #define NETSEC_MCR_PS                           BIT(15)
 191 #define NETSEC_GMAC_MCR_REG_FES                 BIT(14)
 192 #define NETSEC_GMAC_MCR_REG_FULL_DUPLEX_COMMON  0x0000280c
 193 #define NETSEC_GMAC_MCR_REG_HALF_DUPLEX_COMMON  0x0001a00c
 194
 195 #define NETSEC_FCR_RFE                          BIT(2)
 196 #define NETSEC_FCR_TFE                          BIT(1)
 197
 198 #define NETSEC_GMAC_GAR_REG_GW                  BIT(1)
 199 #define NETSEC_GMAC_GAR_REG_GB                  BIT(0)
 200
 201 #define NETSEC_GMAC_GAR_REG_SHIFT_PA            11
 202 #define NETSEC_GMAC_GAR_REG_SHIFT_GR            6
 203 #define GMAC_REG_SHIFT_CR_GAR                   2
 204
 205 #define NETSEC_GMAC_GAR_REG_CR_25_35_MHZ        2
 206 #define NETSEC_GMAC_GAR_REG_CR_35_60_MHZ        3
 207 #define NETSEC_GMAC_GAR_REG_CR_60_100_MHZ       0
 208 #define NETSEC_GMAC_GAR_REG_CR_100_150_MHZ      1
 209 #define NETSEC_GMAC_GAR_REG_CR_150_250_MHZ      4
 210 #define NETSEC_GMAC_GAR_REG_CR_250_300_MHZ      5
 211
 212 #define NETSEC_GMAC_RDLAR_REG_COMMON            0x18000
 213 #define NETSEC_GMAC_TDLAR_REG_COMMON            0x1c000
 214
 215 #define NETSEC_REG_NETSEC_VER_F_TAIKI           0x50000
 216
 217 #define NETSEC_REG_DESC_RING_CONFIG_CFG_UP      BIT(31)
 218 #define NETSEC_REG_DESC_RING_CONFIG_CH_RST      BIT(30)
 219 #define NETSEC_REG_DESC_TMR_MODE                4
 220 #define NETSEC_REG_DESC_ENDIAN                  0
 221
 222 #define NETSEC_MAC_DESC_SOFT_RST_SOFT_RST       1
 223 #define NETSEC_MAC_DESC_INIT_REG_INIT           1
 224
 225 #define NETSEC_EEPROM_MAC_ADDRESS               0x00
 226 #define NETSEC_EEPROM_HM_ME_ADDRESS_H           0x08
 227 #define NETSEC_EEPROM_HM_ME_ADDRESS_L           0x0C
 228 #define NETSEC_EEPROM_HM_ME_SIZE                0x10
 229 #define NETSEC_EEPROM_MH_ME_ADDRESS_H           0x14
 230 #define NETSEC_EEPROM_MH_ME_ADDRESS_L           0x18
 231 #define NETSEC_EEPROM_MH_ME_SIZE                0x1C
 232 #define NETSEC_EEPROM_PKT_ME_ADDRESS            0x20
 233 #define NETSEC_EEPROM_PKT_ME_SIZE               0x24
 234
 235 #define DESC_NUM        256
 236
 237 #define DESC_SZ sizeof(struct netsec_de)
 238
 239 #define NETSEC_F_NETSEC_VER_MAJOR_NUM(x)        ((x) & 0xffff0000)
 240
 241 enum ring_id {
 242         NETSEC_RING_TX = 0,
 243         NETSEC_RING_RX
 244 };
 245
 246 struct netsec_desc {
 247         struct sk_buff *skb;
 248         dma_addr_t dma_addr;
 249         void *addr;
 250         u16 len;
 251 };
 252
 253 struct netsec_desc_ring {
 254         dma_addr_t desc_dma;
 255         struct netsec_desc *desc;
 256         void *vaddr;
 257         u16 pkt_cnt;
 258         u16 head, tail;
 259 };
 260
 261 struct netsec_priv {
 262         struct netsec_desc_ring desc_ring[NETSEC_RING_MAX];
 263         struct ethtool_coalesce et_coalesce;
 264         spinlock_t reglock; /* protect reg access */
 265         struct napi_struct napi;
 266         phy_interface_t phy_interface;
 267         struct net_device *ndev;
 268         struct device_node *phy_np;
 269         struct phy_device *phydev;
 270         struct mii_bus *mii_bus;
 271         void __iomem *ioaddr;
 272         void __iomem *eeprom_base;
 273         struct device *dev;
 274         struct clk *clk;
 275         u32 msg_enable;
 276         u32 freq;
 277         bool rx_cksum_offload_flag;
 278 };
 279
 280 struct netsec_de { /* Netsec Descriptor layout */
 281         u32 attr;
 282         u32 data_buf_addr_up;
 283         u32 data_buf_addr_lw;
 284         u32 buf_len_info;
 285 };
 286
 287 struct netsec_tx_pkt_ctrl {
 288         u16 tcp_seg_len;
 289         bool tcp_seg_offload_flag;
 290         bool cksum_offload_flag;
 291 };
 292
 293 struct netsec_rx_pkt_info {
 294         int rx_cksum_result;
 295         int err_code;
 296         bool err_flag;
 297 };
 298
 299 static void netsec_write(struct netsec_priv *priv, u32 reg_addr, u32 val)
 300 {
 301         writel(val, priv->ioaddr + reg_addr);
 302 }
 303
 304 static u32 netsec_read(struct netsec_priv *priv, u32 reg_addr)
 305 {
 306         return readl(priv->ioaddr + reg_addr);
 307 }
 308
 309 /************* MDIO BUS OPS FOLLOW *************/
 310
 311 #define TIMEOUT_SPINS_MAC               1000
 312 #define TIMEOUT_SECONDARY_MS_MAC        100
 313
 314 static u32 netsec_clk_type(u32 freq)
 315 {
 316         if (freq < MHZ(35))
 317                 return NETSEC_GMAC_GAR_REG_CR_25_35_MHZ;
 318         if (freq < MHZ(60))
 319                 return NETSEC_GMAC_GAR_REG_CR_35_60_MHZ;
 320         if (freq < MHZ(100))
 321                 return NETSEC_GMAC_GAR_REG_CR_60_100_MHZ;
 322         if (freq < MHZ(150))
 323                 return NETSEC_GMAC_GAR_REG_CR_100_150_MHZ;
 324         if (freq < MHZ(250))
 325                 return NETSEC_GMAC_GAR_REG_CR_150_250_MHZ;
 326
 327         return NETSEC_GMAC_GAR_REG_CR_250_300_MHZ;
 328 }
 329
 330 static int netsec_wait_while_busy(struct netsec_priv *priv, u32 addr, u32 mask)
 331 {
 332         u32 timeout = TIMEOUT_SPINS_MAC;
 333
 334         while (--timeout && netsec_read(priv, addr) & mask)
 335                 cpu_relax();
 336         if (timeout)
 337                 return 0;
 338
 339         timeout = TIMEOUT_SECONDARY_MS_MAC;
 340         while (--timeout && netsec_read(priv, addr) & mask)
 341                 usleep_range(1000, 2000);
 342
 343         if (timeout)
 344                 return 0;
 345
 346         netdev_WARN(priv->ndev, "%s: timeout\n", __func__);
 347
 348         return -ETIMEDOUT;
 349 }
 350
 351 static int netsec_mac_write(struct netsec_priv *priv, u32 addr, u32 value)
 352 {
 353         netsec_write(priv, MAC_REG_DATA, value);
 354         netsec_write(priv, MAC_REG_CMD, addr | NETSEC_GMAC_CMD_ST_WRITE);
 355         return netsec_wait_while_busy(priv,
 356                                       MAC_REG_CMD, NETSEC_GMAC_CMD_ST_BUSY);
 357 }
 358
 359 static int netsec_mac_read(struct netsec_priv *priv, u32 addr, u32 *read)
 360 {
 361         int ret;
 362
 363         netsec_write(priv, MAC_REG_CMD, addr | NETSEC_GMAC_CMD_ST_READ);
 364         ret = netsec_wait_while_busy(priv,
 365                                      MAC_REG_CMD, NETSEC_GMAC_CMD_ST_BUSY);
 366         if (ret)
 367                 return ret;
 368
 369         *read = netsec_read(priv, MAC_REG_DATA);
 370
 371         return 0;
 372 }
 373
 374 static int netsec_mac_wait_while_busy(struct netsec_priv *priv,
 375                                       u32 addr, u32 mask)
 376 {
 377         u32 timeout = TIMEOUT_SPINS_MAC;
 378         int ret, data;
 379
 380         do {
 381                 ret = netsec_mac_read(priv, addr, &data);
 382                 if (ret)
 383                         break;
 384                 cpu_relax();
 385         } while (--timeout && (data & mask));
 386
 387         if (timeout)
 388                 return 0;
 389
 390         timeout = TIMEOUT_SECONDARY_MS_MAC;
 391         do {
 392                 usleep_range(1000, 2000);
 393
 394                 ret = netsec_mac_read(priv, addr, &data);
 395                 if (ret)
 396                         break;
 397                 cpu_relax();
 398         } while (--timeout && (data & mask));
 399
 400         if (timeout && !ret)
 401                 return 0;
 402
 403         netdev_WARN(priv->ndev, "%s: timeout\n", __func__);
 404
 405         return -ETIMEDOUT;
 406 }
 407
 408 static int netsec_mac_update_to_phy_state(struct netsec_priv *priv)
 409 {
 410         struct phy_device *phydev = priv->ndev->phydev;
 411         u32 value = 0;
 412
 413         value = phydev->duplex ? NETSEC_GMAC_MCR_REG_FULL_DUPLEX_COMMON :
 414                                  NETSEC_GMAC_MCR_REG_HALF_DUPLEX_COMMON;
 415
 416         if (phydev->speed != SPEED_1000)
 417                 value |= NETSEC_MCR_PS;
 418
 419         if (priv->phy_interface != PHY_INTERFACE_MODE_GMII &&
 420             phydev->speed == SPEED_100)
 421                 value |= NETSEC_GMAC_MCR_REG_FES;
 422
 423         value |= NETSEC_GMAC_MCR_REG_CST | NETSEC_GMAC_MCR_REG_JE;
 424
 425         if (phy_interface_mode_is_rgmii(priv->phy_interface))
 426                 value |= NETSEC_GMAC_MCR_REG_IBN;
 427
 428         if (netsec_mac_write(priv, GMAC_REG_MCR, value))
 429                 return -ETIMEDOUT;
 430
 431         return 0;
 432 }
 433
 434 static int netsec_phy_write(struct mii_bus *bus,
 435                             int phy_addr, int reg, u16 val)
 436 {
 437         struct netsec_priv *priv = bus->priv;
 438
 439         if (netsec_mac_write(priv, GMAC_REG_GDR, val))
 440                 return -ETIMEDOUT;
 441         if (netsec_mac_write(priv, GMAC_REG_GAR,
 442                              phy_addr << NETSEC_GMAC_GAR_REG_SHIFT_PA |
 443                              reg << NETSEC_GMAC_GAR_REG_SHIFT_GR |
 444                              NETSEC_GMAC_GAR_REG_GW | NETSEC_GMAC_GAR_REG_GB |
 445                              (netsec_clk_type(priv->freq) <<
 446                               GMAC_REG_SHIFT_CR_GAR)))
 447                 return -ETIMEDOUT;
 448
 449         return netsec_mac_wait_while_busy(priv, GMAC_REG_GAR,
 450                                           NETSEC_GMAC_GAR_REG_GB);
 451 }
 452
 453 static int netsec_phy_read(struct mii_bus *bus, int phy_addr, int reg_addr)
 454 {
 455         struct netsec_priv *priv = bus->priv;
 456         u32 data;
 457         int ret;
 458
 459         if (netsec_mac_write(priv, GMAC_REG_GAR, NETSEC_GMAC_GAR_REG_GB |
 460                              phy_addr << NETSEC_GMAC_GAR_REG_SHIFT_PA |
 461                              reg_addr << NETSEC_GMAC_GAR_REG_SHIFT_GR |
 462                              (netsec_clk_type(priv->freq) <<
 463                               GMAC_REG_SHIFT_CR_GAR)))
 464                 return -ETIMEDOUT;
 465
 466         ret = netsec_mac_wait_while_busy(priv, GMAC_REG_GAR,
 467                                          NETSEC_GMAC_GAR_REG_GB);
 468         if (ret)
 469                 return ret;
 470
 471         ret = netsec_mac_read(priv, GMAC_REG_GDR, &data);
 472         if (ret)
 473                 return ret;
 474
 475         return data;
 476 }
 477
 478 /************* ETHTOOL_OPS FOLLOW *************/
 479
 480 static void netsec_et_get_drvinfo(struct net_device *net_device,
 481                                   struct ethtool_drvinfo *info)
 482 {
 483         strlcpy(info->driver, "netsec", sizeof(info->driver));
 484         strlcpy(info->bus_info, dev_name(net_device->dev.parent),
 485                 sizeof(info->bus_info));
 486 }
 487
 488 static int netsec_et_get_coalesce(struct net_device *net_device,
 489                                   struct ethtool_coalesce *et_coalesce)
 490 {
 491         struct netsec_priv *priv = netdev_priv(net_device);
 492
 493         *et_coalesce = priv->et_coalesce;
 494
 495         return 0;
 496 }
 497
 498 static int netsec_et_set_coalesce(struct net_device *net_device,
 499                                   struct ethtool_coalesce *et_coalesce)
 500 {
 501         struct netsec_priv *priv = netdev_priv(net_device);
 502
 503         priv->et_coalesce = *et_coalesce;
 504
 505         if (priv->et_coalesce.tx_coalesce_usecs < 50)
 506                 priv->et_coalesce.tx_coalesce_usecs = 50;
 507         if (priv->et_coalesce.tx_max_coalesced_frames < 1)
 508                 priv->et_coalesce.tx_max_coalesced_frames = 1;
 509
 510         netsec_write(priv, NETSEC_REG_NRM_TX_DONE_TXINT_PKTCNT,
 511                      priv->et_coalesce.tx_max_coalesced_frames);
 512         netsec_write(priv, NETSEC_REG_NRM_TX_TXINT_TMR,
 513                      priv->et_coalesce.tx_coalesce_usecs);
 514         netsec_write(priv, NETSEC_REG_NRM_TX_INTEN_SET, NRM_TX_ST_TXDONE);
 515         netsec_write(priv, NETSEC_REG_NRM_TX_INTEN_SET, NRM_TX_ST_TMREXP);
 516
 517         if (priv->et_coalesce.rx_coalesce_usecs < 50)
 518                 priv->et_coalesce.rx_coalesce_usecs = 50;
 519         if (priv->et_coalesce.rx_max_coalesced_frames < 1)
 520                 priv->et_coalesce.rx_max_coalesced_frames = 1;
 521
 522         netsec_write(priv, NETSEC_REG_NRM_RX_RXINT_PKTCNT,
 523                      priv->et_coalesce.rx_max_coalesced_frames);
 524         netsec_write(priv, NETSEC_REG_NRM_RX_RXINT_TMR,
 525                      priv->et_coalesce.rx_coalesce_usecs);
 526         netsec_write(priv, NETSEC_REG_NRM_RX_INTEN_SET, NRM_RX_ST_PKTCNT);
 527         netsec_write(priv, NETSEC_REG_NRM_RX_INTEN_SET, NRM_RX_ST_TMREXP);
 528
 529         return 0;
 530 }
 531
 532 static u32 netsec_et_get_msglevel(struct net_device *dev)
 533 {
 534         struct netsec_priv *priv = netdev_priv(dev);
 535
 536         return priv->msg_enable;
 537 }
 538
 539 static void netsec_et_set_msglevel(struct net_device *dev, u32 datum)
 540 {
 541         struct netsec_priv *priv = netdev_priv(dev);
 542
 543         priv->msg_enable = datum;
 544 }
 545
 546 static const struct ethtool_ops netsec_ethtool_ops = {
 547         .get_drvinfo            = netsec_et_get_drvinfo,
 548         .get_link_ksettings     = phy_ethtool_get_link_ksettings,
 549         .set_link_ksettings     = phy_ethtool_set_link_ksettings,
 550         .get_link               = ethtool_op_get_link,
 551         .get_coalesce           = netsec_et_get_coalesce,
 552         .set_coalesce           = netsec_et_set_coalesce,
 553         .get_msglevel           = netsec_et_get_msglevel,
 554         .set_msglevel           = netsec_et_set_msglevel,
 555 };
 556
 557 /************* NETDEV_OPS FOLLOW *************/
 558
 559 static struct sk_buff *netsec_alloc_skb(struct netsec_priv *priv,
 560                                         struct netsec_desc *desc)
 561 {
 562         struct sk_buff *skb;
 563
 564         if (device_get_dma_attr(priv->dev) == DEV_DMA_COHERENT) {
 565                 skb = netdev_alloc_skb_ip_align(priv->ndev, desc->len);
 566         } else {
 567                 desc->len = L1_CACHE_ALIGN(desc->len);
 568                 skb = netdev_alloc_skb(priv->ndev, desc->len);
 569         }
 570         if (!skb)
 571                 return NULL;
 572
 573         desc->addr = skb->data;
 574         desc->dma_addr = dma_map_single(priv->dev, desc->addr, desc->len,
 575                                         DMA_FROM_DEVICE);
 576         if (dma_mapping_error(priv->dev, desc->dma_addr)) {
 577                 dev_kfree_skb_any(skb);
 578                 return NULL;
 579         }
 580         return skb;
 581 }
 582
 583 static void netsec_set_rx_de(struct netsec_priv *priv,
 584                              struct netsec_desc_ring *dring, u16 idx,
 585                              const struct netsec_desc *desc,
 586                              struct sk_buff *skb)
 587 {
 588         struct netsec_de *de = dring->vaddr + DESC_SZ * idx;
 589         u32 attr = (1 << NETSEC_RX_PKT_OWN_FIELD) |
 590                    (1 << NETSEC_RX_PKT_FS_FIELD) |
 591                    (1 << NETSEC_RX_PKT_LS_FIELD);
 592
 593         if (idx == DESC_NUM - 1)
 594                 attr |= (1 << NETSEC_RX_PKT_LD_FIELD);
 595
 596         de->data_buf_addr_up = upper_32_bits(desc->dma_addr);
 597         de->data_buf_addr_lw = lower_32_bits(desc->dma_addr);
 598         de->buf_len_info = desc->len;
 599         de->attr = attr;
 600         dma_wmb();
 601
 602         dring->desc[idx].dma_addr = desc->dma_addr;
 603         dring->desc[idx].addr = desc->addr;
 604         dring->desc[idx].len = desc->len;
 605         dring->desc[idx].skb = skb;
 606 }
 607
 608 static struct sk_buff *netsec_get_rx_de(struct netsec_priv *priv,
 609                                         struct netsec_desc_ring *dring,
 610                                         u16 idx,
 611                                         struct netsec_rx_pkt_info *rxpi,
 612                                         struct netsec_desc *desc, u16 *len)
 613 {
 614         struct netsec_de de = {};
 615
 616         memcpy(&de, dring->vaddr + DESC_SZ * idx, DESC_SZ);
 617
 618         *len = de.buf_len_info >> 16;
 619
 620         rxpi->err_flag = (de.attr >> NETSEC_RX_PKT_ER_FIELD) & 1;
 621         rxpi->rx_cksum_result = (de.attr >> NETSEC_RX_PKT_CO_FIELD) & 3;
 622         rxpi->err_code = (de.attr >> NETSEC_RX_PKT_ERR_FIELD) &
 623                                                         NETSEC_RX_PKT_ERR_MASK;
 624         *desc = dring->desc[idx];
 625         return desc->skb;
 626 }
 627
 628 static struct sk_buff *netsec_get_rx_pkt_data(struct netsec_priv *priv,
 629                                               struct netsec_rx_pkt_info *rxpi,
 630                                               struct netsec_desc *desc,
 631                                               u16 *len)
 632 {
 633         struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_RX];
 634         struct sk_buff *tmp_skb, *skb = NULL;
 635         struct netsec_desc td;
 636         int tail;
 637
 638         *rxpi = (struct netsec_rx_pkt_info){};
 639
 640         td.len = priv->ndev->mtu + 22;
 641
 642         tmp_skb = netsec_alloc_skb(priv, &td);
 643
 644         tail = dring->tail;
 645
 646         if (!tmp_skb) {
 647                 netsec_set_rx_de(priv, dring, tail, &dring->desc[tail],
 648                                  dring->desc[tail].skb);
 649         } else {
 650                 skb = netsec_get_rx_de(priv, dring, tail, rxpi, desc, len);
 651                 netsec_set_rx_de(priv, dring, tail, &td, tmp_skb);
 652         }
 653
 654         /* move tail ahead */
 655         dring->tail = (dring->tail + 1) % DESC_NUM;
 656
 657         return skb;
 658 }
 659
 660 static int netsec_clean_tx_dring(struct netsec_priv *priv, int budget)
 661 {
 662         struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_TX];
 663         unsigned int pkts, bytes;
 664
 665         dring->pkt_cnt += netsec_read(priv, NETSEC_REG_NRM_TX_DONE_PKTCNT);
 666
 667         if (dring->pkt_cnt < budget)
 668                 budget = dring->pkt_cnt;
 669
 670         pkts = 0;
 671         bytes = 0;
 672
 673         while (pkts < budget) {
 674                 struct netsec_desc *desc;
 675                 struct netsec_de *entry;
 676                 int tail, eop;
 677
 678                 tail = dring->tail;
 679
 680                 /* move tail ahead */
 681                 dring->tail = (tail + 1) % DESC_NUM;
 682
 683                 desc = &dring->desc[tail];
 684                 entry = dring->vaddr + DESC_SZ * tail;
 685
 686                 eop = (entry->attr >> NETSEC_TX_LAST) & 1;
 687
 688                 dma_unmap_single(priv->dev, desc->dma_addr, desc->len,
 689                                  DMA_TO_DEVICE);
 690                 if (eop) {
 691                         pkts++;
 692                         bytes += desc->skb->len;
 693                         dev_kfree_skb(desc->skb);
 694                 }
 695                 *desc = (struct netsec_desc){};
 696         }
 697         dring->pkt_cnt -= budget;
 698
 699         priv->ndev->stats.tx_packets += budget;
 700         priv->ndev->stats.tx_bytes += bytes;
 701
 702         netdev_completed_queue(priv->ndev, budget, bytes);
 703
 704         return budget;
 705 }
 706
 707 static int netsec_process_tx(struct netsec_priv *priv, int budget)
 708 {
 709         struct net_device *ndev = priv->ndev;
 710         int new, done = 0;
 711
 712         do {
 713                 new = netsec_clean_tx_dring(priv, budget);
 714                 done += new;
 715                 budget -= new;
 716         } while (new);
 717
 718         if (done && netif_queue_stopped(ndev))
 719                 netif_wake_queue(ndev);
 720
 721         return done;
 722 }
 723
 724 static int netsec_process_rx(struct netsec_priv *priv, int budget)
 725 {
 726         struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_RX];
 727         struct net_device *ndev = priv->ndev;
 728         struct netsec_rx_pkt_info rx_info;
 729         int done = 0;
 730         struct netsec_desc desc;
 731         struct sk_buff *skb;
 732         u16 len;
 733
 734         while (done < budget) {
 735                 u16 idx = dring->tail;
 736                 struct netsec_de *de = dring->vaddr + (DESC_SZ * idx);
 737
 738                 if (de->attr & (1U << NETSEC_RX_PKT_OWN_FIELD))
 739                         break;
 740
 741                 /* This  barrier is needed to keep us from reading
 742                  * any other fields out of the netsec_de until we have
 743                  * verified the descriptor has been written back
 744                  */
 745                 dma_rmb();
 746                 done++;
 747                 skb = netsec_get_rx_pkt_data(priv, &rx_info, &desc, &len);
 748                 if (unlikely(!skb) || rx_info.err_flag) {
 749                         netif_err(priv, drv, priv->ndev,
 750                                   "%s: rx fail err(%d)\n",
 751                                   __func__, rx_info.err_code);
 752                         ndev->stats.rx_dropped++;
 753                         continue;
 754                 }
 755
 756                 dma_unmap_single(priv->dev, desc.dma_addr, desc.len,
 757                                  DMA_FROM_DEVICE);
 758                 skb_put(skb, len);
 759                 skb->protocol = eth_type_trans(skb, priv->ndev);
 760
 761                 if (priv->rx_cksum_offload_flag &&
 762                     rx_info.rx_cksum_result == NETSEC_RX_CKSUM_OK)
 763                         skb->ip_summed = CHECKSUM_UNNECESSARY;
 764
 765                 if (napi_gro_receive(&priv->napi, skb) != GRO_DROP) {
 766                         ndev->stats.rx_packets++;
 767                         ndev->stats.rx_bytes += len;
 768                 }
 769         }
 770
 771         return done;
 772 }
 773
 774 static int netsec_napi_poll(struct napi_struct *napi, int budget)
 775 {
 776         struct netsec_priv *priv;
 777         int tx, rx, done, todo;
 778
 779         priv = container_of(napi, struct netsec_priv, napi);
 780
 781         todo = budget;
 782         do {
 783                 if (!todo)
 784                         break;
 785
 786                 tx = netsec_process_tx(priv, todo);
 787                 todo -= tx;
 788
 789                 if (!todo)
 790                         break;
 791
 792                 rx = netsec_process_rx(priv, todo);
 793                 todo -= rx;
 794         } while (rx || tx);
 795
 796         done = budget - todo;
 797
 798         if (done < budget && napi_complete_done(napi, done)) {
 799                 unsigned long flags;
 800
 801                 spin_lock_irqsave(&priv->reglock, flags);
 802                 netsec_write(priv, NETSEC_REG_INTEN_SET,
 803                              NETSEC_IRQ_RX | NETSEC_IRQ_TX);
 804                 spin_unlock_irqrestore(&priv->reglock, flags);
 805         }
 806
 807         return done;
 808 }
 809
 810 static void netsec_set_tx_de(struct netsec_priv *priv,
 811                              struct netsec_desc_ring *dring,
 812                              const struct netsec_tx_pkt_ctrl *tx_ctrl,
 813                              const struct netsec_desc *desc,
 814                              struct sk_buff *skb)
 815 {
 816         int idx = dring->head;
 817         struct netsec_de *de;
 818         u32 attr;
 819
 820         de = dring->vaddr + (DESC_SZ * idx);
 821
 822         attr = (1 << NETSEC_TX_SHIFT_OWN_FIELD) |
 823                (1 << NETSEC_TX_SHIFT_PT_FIELD) |
 824                (NETSEC_RING_GMAC << NETSEC_TX_SHIFT_TDRID_FIELD) |
 825                (1 << NETSEC_TX_SHIFT_FS_FIELD) |
 826                (1 << NETSEC_TX_LAST) |
 827                (tx_ctrl->cksum_offload_flag << NETSEC_TX_SHIFT_CO) |
 828                (tx_ctrl->tcp_seg_offload_flag << NETSEC_TX_SHIFT_SO) |
 829                (1 << NETSEC_TX_SHIFT_TRS_FIELD);
 830         if (idx == DESC_NUM - 1)
 831                 attr |= (1 << NETSEC_TX_SHIFT_LD_FIELD);
 832
 833         de->data_buf_addr_up = upper_32_bits(desc->dma_addr);
 834         de->data_buf_addr_lw = lower_32_bits(desc->dma_addr);
 835         de->buf_len_info = (tx_ctrl->tcp_seg_len << 16) | desc->len;
 836         de->attr = attr;
 837         dma_wmb();
 838
 839         dring->desc[idx] = *desc;
 840         dring->desc[idx].skb = skb;
 841
 842         /* move head ahead */
 843         dring->head = (dring->head + 1) % DESC_NUM;
 844 }
 845
 846 static netdev_tx_t netsec_netdev_start_xmit(struct sk_buff *skb,
 847                                             struct net_device *ndev)
 848 {
 849         struct netsec_priv *priv = netdev_priv(ndev);
 850         struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_TX];
 851         struct netsec_tx_pkt_ctrl tx_ctrl = {};
 852         struct netsec_desc tx_desc;
 853         u16 tso_seg_len = 0;
 854         int filled;
 855
 856         /* differentiate between full/emtpy ring */
 857         if (dring->head >= dring->tail)
 858                 filled = dring->head - dring->tail;
 859         else
 860                 filled = dring->head + DESC_NUM - dring->tail;
 861
 862         if (DESC_NUM - filled < 2) { /* if less than 2 available */
 863                 netif_err(priv, drv, priv->ndev, "%s: TxQFull!\n", __func__);
 864                 netif_stop_queue(priv->ndev);
 865                 dma_wmb();
 866                 return NETDEV_TX_BUSY;
 867         }
 868
 869         if (skb->ip_summed == CHECKSUM_PARTIAL)
 870                 tx_ctrl.cksum_offload_flag = true;
 871
 872         if (skb_is_gso(skb))
 873                 tso_seg_len = skb_shinfo(skb)->gso_size;
 874
 875         if (tso_seg_len > 0) {
 876                 if (skb->protocol == htons(ETH_P_IP)) {
 877                         ip_hdr(skb)->tot_len = 0;
 878                         tcp_hdr(skb)->check =
 879                                 ~tcp_v4_check(0, ip_hdr(skb)->saddr,
 880                                               ip_hdr(skb)->daddr, 0);
 881                 } else {
 882                         ipv6_hdr(skb)->payload_len = 0;
 883                         tcp_hdr(skb)->check =
 884                                 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
 885                                                  &ipv6_hdr(skb)->daddr,
 886                                                  0, IPPROTO_TCP, 0);
 887                 }
 888
 889                 tx_ctrl.tcp_seg_offload_flag = true;
 890                 tx_ctrl.tcp_seg_len = tso_seg_len;
 891         }
 892
 893         tx_desc.dma_addr = dma_map_single(priv->dev, skb->data,
 894                                           skb_headlen(skb), DMA_TO_DEVICE);
 895         if (dma_mapping_error(priv->dev, tx_desc.dma_addr)) {
 896                 netif_err(priv, drv, priv->ndev,
 897                           "%s: DMA mapping failed\n", __func__);
 898                 ndev->stats.tx_dropped++;
 899                 dev_kfree_skb_any(skb);
 900                 return NETDEV_TX_OK;
 901         }
 902         tx_desc.addr = skb->data;
 903         tx_desc.len = skb_headlen(skb);
 904
 905         skb_tx_timestamp(skb);
 906         netdev_sent_queue(priv->ndev, skb->len);
 907
 908         netsec_set_tx_de(priv, dring, &tx_ctrl, &tx_desc, skb);
 909         netsec_write(priv, NETSEC_REG_NRM_TX_PKTCNT, 1); /* submit another tx */
 910
 911         return NETDEV_TX_OK;
 912 }
 913
 914 static void netsec_uninit_pkt_dring(struct netsec_priv *priv, int id)
 915 {
 916         struct netsec_desc_ring *dring = &priv->desc_ring[id];
 917         struct netsec_desc *desc;
 918         u16 idx;
 919
 920         if (!dring->vaddr || !dring->desc)
 921                 return;
 922
 923         for (idx = 0; idx < DESC_NUM; idx++) {
 924                 desc = &dring->desc[idx];
 925                 if (!desc->addr)
 926                         continue;
 927
 928                 dma_unmap_single(priv->dev, desc->dma_addr, desc->len,
 929                                  id == NETSEC_RING_RX ? DMA_FROM_DEVICE :
 930                                                               DMA_TO_DEVICE);
 931                 dev_kfree_skb(desc->skb);
 932         }
 933
 934         memset(dring->desc, 0, sizeof(struct netsec_desc) * DESC_NUM);
 935         memset(dring->vaddr, 0, DESC_SZ * DESC_NUM);
 936
 937         dring->head = 0;
 938         dring->tail = 0;
 939         dring->pkt_cnt = 0;
 940 }
 941
 942 static void netsec_free_dring(struct netsec_priv *priv, int id)
 943 {
 944         struct netsec_desc_ring *dring = &priv->desc_ring[id];
 945
 946         if (dring->vaddr) {
 947                 dma_free_coherent(priv->dev, DESC_SZ * DESC_NUM,
 948                                   dring->vaddr, dring->desc_dma);
 949                 dring->vaddr = NULL;
 950         }
 951
 952         kfree(dring->desc);
 953         dring->desc = NULL;
 954 }
 955
 956 static int netsec_alloc_dring(struct netsec_priv *priv, enum ring_id id)
 957 {
 958         struct netsec_desc_ring *dring = &priv->desc_ring[id];
 959         int ret = 0;
 960
 961         dring->vaddr = dma_zalloc_coherent(priv->dev, DESC_SZ * DESC_NUM,
 962                                            &dring->desc_dma, GFP_KERNEL);
 963         if (!dring->vaddr) {
 964                 ret = -ENOMEM;
 965                 goto err;
 966         }
 967
 968         dring->desc = kcalloc(DESC_NUM, sizeof(*dring->desc), GFP_KERNEL);
 969         if (!dring->desc) {
 970                 ret = -ENOMEM;
 971                 goto err;
 972         }
 973
 974         return 0;
 975 err:
 976         netsec_free_dring(priv, id);
 977
 978         return ret;
 979 }
 980
 981 static int netsec_setup_rx_dring(struct netsec_priv *priv)
 982 {
 983         struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_RX];
 984         struct netsec_desc desc;
 985         struct sk_buff *skb;
 986         int n;
 987
 988         desc.len = priv->ndev->mtu + 22;
 989
 990         for (n = 0; n < DESC_NUM; n++) {
 991                 skb = netsec_alloc_skb(priv, &desc);
 992                 if (!skb) {
 993                         netsec_uninit_pkt_dring(priv, NETSEC_RING_RX);
 994                         return -ENOMEM;
 995                 }
 996                 netsec_set_rx_de(priv, dring, n, &desc, skb);
 997         }
 998
 999         return 0;
1000 }
1001
1002 static int netsec_netdev_load_ucode_region(struct netsec_priv *priv, u32 reg,
1003                                            u32 addr_h, u32 addr_l, u32 size)
1004 {
1005         u64 base = (u64)addr_h << 32 | addr_l;
1006         void __iomem *ucode;
1007         u32 i;
1008
1009         ucode = ioremap(base, size * sizeof(u32));
1010         if (!ucode)
1011                 return -ENOMEM;
1012
1013         for (i = 0; i < size; i++)
1014                 netsec_write(priv, reg, readl(ucode + i * 4));
1015
1016         iounmap(ucode);
1017         return 0;
1018 }
1019
1020 static int netsec_netdev_load_microcode(struct netsec_priv *priv)
1021 {
1022         u32 addr_h, addr_l, size;
1023         int err;
1024
1025         addr_h = readl(priv->eeprom_base + NETSEC_EEPROM_HM_ME_ADDRESS_H);
1026         addr_l = readl(priv->eeprom_base + NETSEC_EEPROM_HM_ME_ADDRESS_L);
1027         size = readl(priv->eeprom_base + NETSEC_EEPROM_HM_ME_SIZE);
1028         err = netsec_netdev_load_ucode_region(priv, NETSEC_REG_DMAC_HM_CMD_BUF,
1029                                               addr_h, addr_l, size);
1030         if (err)
1031                 return err;
1032
1033         addr_h = readl(priv->eeprom_base + NETSEC_EEPROM_MH_ME_ADDRESS_H);
1034         addr_l = readl(priv->eeprom_base + NETSEC_EEPROM_MH_ME_ADDRESS_L);
1035         size = readl(priv->eeprom_base + NETSEC_EEPROM_MH_ME_SIZE);
1036         err = netsec_netdev_load_ucode_region(priv, NETSEC_REG_DMAC_MH_CMD_BUF,
1037                                               addr_h, addr_l, size);
1038         if (err)
1039                 return err;
1040
1041         addr_h = 0;
1042         addr_l = readl(priv->eeprom_base + NETSEC_EEPROM_PKT_ME_ADDRESS);
1043         size = readl(priv->eeprom_base + NETSEC_EEPROM_PKT_ME_SIZE);
1044         err = netsec_netdev_load_ucode_region(priv, NETSEC_REG_PKT_CMD_BUF,
1045                                               addr_h, addr_l, size);
1046         if (err)
1047                 return err;
1048
1049         return 0;
1050 }
1051
1052 static int netsec_reset_hardware(struct netsec_priv *priv,
1053                                  bool load_ucode)
1054 {
1055         u32 value;
1056         int err;
1057
1058         /* stop DMA engines */
1059         if (!netsec_read(priv, NETSEC_REG_ADDR_DIS_CORE)) {
1060                 netsec_write(priv, NETSEC_REG_DMA_HM_CTRL,
1061                              NETSEC_DMA_CTRL_REG_STOP);
1062                 netsec_write(priv, NETSEC_REG_DMA_MH_CTRL,
1063                              NETSEC_DMA_CTRL_REG_STOP);
1064
1065                 while (netsec_read(priv, NETSEC_REG_DMA_HM_CTRL) &
1066                        NETSEC_DMA_CTRL_REG_STOP)
1067                         cpu_relax();
1068
1069                 while (netsec_read(priv, NETSEC_REG_DMA_MH_CTRL) &
1070                        NETSEC_DMA_CTRL_REG_STOP)
1071                         cpu_relax();
1072         }
1073
1074         netsec_write(priv, NETSEC_REG_SOFT_RST, NETSEC_SOFT_RST_REG_RESET);
1075         netsec_write(priv, NETSEC_REG_SOFT_RST, NETSEC_SOFT_RST_REG_RUN);
1076         netsec_write(priv, NETSEC_REG_COM_INIT, NETSEC_COM_INIT_REG_ALL);
1077
1078         while (netsec_read(priv, NETSEC_REG_COM_INIT) != 0)
1079                 cpu_relax();
1080
1081         /* set desc_start addr */
1082         netsec_write(priv, NETSEC_REG_NRM_RX_DESC_START_UP,
1083                      upper_32_bits(priv->desc_ring[NETSEC_RING_RX].desc_dma));
1084         netsec_write(priv, NETSEC_REG_NRM_RX_DESC_START_LW,
1085                      lower_32_bits(priv->desc_ring[NETSEC_RING_RX].desc_dma));
1086
1087         netsec_write(priv, NETSEC_REG_NRM_TX_DESC_START_UP,
1088                      upper_32_bits(priv->desc_ring[NETSEC_RING_TX].desc_dma));
1089         netsec_write(priv, NETSEC_REG_NRM_TX_DESC_START_LW,
1090                      lower_32_bits(priv->desc_ring[NETSEC_RING_TX].desc_dma));
1091
1092         /* set normal tx dring ring config */
1093         netsec_write(priv, NETSEC_REG_NRM_TX_CONFIG,
1094                      1 << NETSEC_REG_DESC_ENDIAN);
1095         netsec_write(priv, NETSEC_REG_NRM_RX_CONFIG,
1096                      1 << NETSEC_REG_DESC_ENDIAN);
1097
1098         if (load_ucode) {
1099                 err = netsec_netdev_load_microcode(priv);
1100                 if (err) {
1101                         netif_err(priv, probe, priv->ndev,
1102                                   "%s: failed to load microcode (%d)\n",
1103                                   __func__, err);
1104                         return err;
1105                 }
1106         }
1107
1108         /* start DMA engines */
1109         netsec_write(priv, NETSEC_REG_DMA_TMR_CTRL, priv->freq / 1000000 - 1);
1110         netsec_write(priv, NETSEC_REG_ADDR_DIS_CORE, 0);
1111
1112         usleep_range(1000, 2000);
1113
1114         if (!(netsec_read(priv, NETSEC_REG_TOP_STATUS) &
1115               NETSEC_TOP_IRQ_REG_CODE_LOAD_END)) {
1116                 netif_err(priv, probe, priv->ndev,
1117                           "microengine start failed\n");
1118                 return -ENXIO;
1119         }
1120         netsec_write(priv, NETSEC_REG_TOP_STATUS,
1121                      NETSEC_TOP_IRQ_REG_CODE_LOAD_END);
1122
1123         value = NETSEC_PKT_CTRL_REG_MODE_NRM;
1124         if (priv->ndev->mtu > ETH_DATA_LEN)
1125                 value |= NETSEC_PKT_CTRL_REG_EN_JUMBO;
1126
1127         /* change to normal mode */
1128         netsec_write(priv, NETSEC_REG_DMA_MH_CTRL, MH_CTRL__MODE_TRANS);
1129         netsec_write(priv, NETSEC_REG_PKT_CTRL, value);
1130
1131         while ((netsec_read(priv, NETSEC_REG_MODE_TRANS_COMP_STATUS) &
1132                 NETSEC_MODE_TRANS_COMP_IRQ_T2N) == 0)
1133                 cpu_relax();
1134
1135         /* clear any pending EMPTY/ERR irq status */
1136         netsec_write(priv, NETSEC_REG_NRM_TX_STATUS, ~0);
1137
1138         /* Disable TX & RX intr */
1139         netsec_write(priv, NETSEC_REG_INTEN_CLR, ~0);
1140
1141         return 0;
1142 }
1143
1144 static int netsec_start_gmac(struct netsec_priv *priv)
1145 {
1146         struct phy_device *phydev = priv->ndev->phydev;
1147         u32 value = 0;
1148         int ret;
1149
1150         if (phydev->speed != SPEED_1000)
1151                 value = (NETSEC_GMAC_MCR_REG_CST |
1152                          NETSEC_GMAC_MCR_REG_HALF_DUPLEX_COMMON);
1153
1154         if (netsec_mac_write(priv, GMAC_REG_MCR, value))
1155                 return -ETIMEDOUT;
1156         if (netsec_mac_write(priv, GMAC_REG_BMR,
1157                              NETSEC_GMAC_BMR_REG_RESET))
1158                 return -ETIMEDOUT;
1159
1160         /* Wait soft reset */
1161         usleep_range(1000, 5000);
1162
1163         ret = netsec_mac_read(priv, GMAC_REG_BMR, &value);
1164         if (ret)
1165                 return ret;
1166         if (value & NETSEC_GMAC_BMR_REG_SWR)
1167                 return -EAGAIN;
1168
1169         netsec_write(priv, MAC_REG_DESC_SOFT_RST, 1);
1170         if (netsec_wait_while_busy(priv, MAC_REG_DESC_SOFT_RST, 1))
1171                 return -ETIMEDOUT;
1172
1173         netsec_write(priv, MAC_REG_DESC_INIT, 1);
1174         if (netsec_wait_while_busy(priv, MAC_REG_DESC_INIT, 1))
1175                 return -ETIMEDOUT;
1176
1177         if (netsec_mac_write(priv, GMAC_REG_BMR,
1178                              NETSEC_GMAC_BMR_REG_COMMON))
1179                 return -ETIMEDOUT;
1180         if (netsec_mac_write(priv, GMAC_REG_RDLAR,
1181                              NETSEC_GMAC_RDLAR_REG_COMMON))
1182                 return -ETIMEDOUT;
1183         if (netsec_mac_write(priv, GMAC_REG_TDLAR,
1184                              NETSEC_GMAC_TDLAR_REG_COMMON))
1185                 return -ETIMEDOUT;
1186         if (netsec_mac_write(priv, GMAC_REG_MFFR, 0x80000001))
1187                 return -ETIMEDOUT;
1188
1189         ret = netsec_mac_update_to_phy_state(priv);
1190         if (ret)
1191                 return ret;
1192
1193         ret = netsec_mac_read(priv, GMAC_REG_OMR, &value);
1194         if (ret)
1195                 return ret;
1196
1197         value |= NETSEC_GMAC_OMR_REG_SR;
1198         value |= NETSEC_GMAC_OMR_REG_ST;
1199
1200         netsec_write(priv, NETSEC_REG_NRM_RX_INTEN_CLR, ~0);
1201         netsec_write(priv, NETSEC_REG_NRM_TX_INTEN_CLR, ~0);
1202
1203         netsec_et_set_coalesce(priv->ndev, &priv->et_coalesce);
1204
1205         if (netsec_mac_write(priv, GMAC_REG_OMR, value))
1206                 return -ETIMEDOUT;
1207
1208         return 0;
1209 }
1210
1211 static int netsec_stop_gmac(struct netsec_priv *priv)
1212 {
1213         u32 value;
1214         int ret;
1215
1216         ret = netsec_mac_read(priv, GMAC_REG_OMR, &value);
1217         if (ret)
1218                 return ret;
1219         value &= ~NETSEC_GMAC_OMR_REG_SR;
1220         value &= ~NETSEC_GMAC_OMR_REG_ST;
1221
1222         /* disable all interrupts */
1223         netsec_write(priv, NETSEC_REG_NRM_RX_INTEN_CLR, ~0);
1224         netsec_write(priv, NETSEC_REG_NRM_TX_INTEN_CLR, ~0);
1225
1226         return netsec_mac_write(priv, GMAC_REG_OMR, value);
1227 }
1228
1229 static void netsec_phy_adjust_link(struct net_device *ndev)
1230 {
1231         struct netsec_priv *priv = netdev_priv(ndev);
1232
1233         if (ndev->phydev->link)
1234                 netsec_start_gmac(priv);
1235         else
1236                 netsec_stop_gmac(priv);
1237
1238         phy_print_status(ndev->phydev);
1239 }
1240
1241 static irqreturn_t netsec_irq_handler(int irq, void *dev_id)
1242 {
1243         struct netsec_priv *priv = dev_id;
1244         u32 val, status = netsec_read(priv, NETSEC_REG_TOP_STATUS);
1245         unsigned long flags;
1246
1247         /* Disable interrupts */
1248         if (status & NETSEC_IRQ_TX) {
1249                 val = netsec_read(priv, NETSEC_REG_NRM_TX_STATUS);
1250                 netsec_write(priv, NETSEC_REG_NRM_TX_STATUS, val);
1251         }
1252         if (status & NETSEC_IRQ_RX) {
1253                 val = netsec_read(priv, NETSEC_REG_NRM_RX_STATUS);
1254                 netsec_write(priv, NETSEC_REG_NRM_RX_STATUS, val);
1255         }
1256
1257         spin_lock_irqsave(&priv->reglock, flags);
1258         netsec_write(priv, NETSEC_REG_INTEN_CLR, NETSEC_IRQ_RX | NETSEC_IRQ_TX);
1259         spin_unlock_irqrestore(&priv->reglock, flags);
1260
1261         napi_schedule(&priv->napi);
1262
1263         return IRQ_HANDLED;
1264 }
1265
1266 static int netsec_netdev_open(struct net_device *ndev)
1267 {
1268         struct netsec_priv *priv = netdev_priv(ndev);
1269         int ret;
1270
1271         pm_runtime_get_sync(priv->dev);
1272
1273         ret = netsec_setup_rx_dring(priv);
1274         if (ret) {
1275                 netif_err(priv, probe, priv->ndev,
1276                           "%s: fail setup ring\n", __func__);
1277                 goto err1;
1278         }
1279
1280         ret = request_irq(priv->ndev->irq, netsec_irq_handler,
1281                           IRQF_SHARED, "netsec", priv);
1282         if (ret) {
1283                 netif_err(priv, drv, priv->ndev, "request_irq failed\n");
1284                 goto err2;
1285         }
1286
1287         if (dev_of_node(priv->dev)) {
1288                 if (!of_phy_connect(priv->ndev, priv->phy_np,
1289                                     netsec_phy_adjust_link, 0,
1290                                     priv->phy_interface)) {
1291                         netif_err(priv, link, priv->ndev, "missing PHY\n");
1292                         ret = -ENODEV;
1293                         goto err3;
1294                 }
1295         } else {
1296                 ret = phy_connect_direct(priv->ndev, priv->phydev,
1297                                          netsec_phy_adjust_link,
1298                                          priv->phy_interface);
1299                 if (ret) {
1300                         netif_err(priv, link, priv->ndev,
1301                                   "phy_connect_direct() failed (%d)\n", ret);
1302                         goto err3;
1303                 }
1304         }
1305
1306         phy_start(ndev->phydev);
1307
1308         netsec_start_gmac(priv);
1309         napi_enable(&priv->napi);
1310         netif_start_queue(ndev);
1311
1312         /* Enable TX+RX intr. */
1313         netsec_write(priv, NETSEC_REG_INTEN_SET, NETSEC_IRQ_RX | NETSEC_IRQ_TX);
1314
1315         return 0;
1316 err3:
1317         free_irq(priv->ndev->irq, priv);
1318 err2:
1319         netsec_uninit_pkt_dring(priv, NETSEC_RING_RX);
1320 err1:
1321         pm_runtime_put_sync(priv->dev);
1322         return ret;
1323 }
1324
1325 static int netsec_netdev_stop(struct net_device *ndev)
1326 {
1327         int ret;
1328         struct netsec_priv *priv = netdev_priv(ndev);
1329
1330         netif_stop_queue(priv->ndev);
1331         dma_wmb();
1332
1333         napi_disable(&priv->napi);
1334
1335         netsec_write(priv, NETSEC_REG_INTEN_CLR, ~0);
1336         netsec_stop_gmac(priv);
1337
1338         free_irq(priv->ndev->irq, priv);
1339
1340         netsec_uninit_pkt_dring(priv, NETSEC_RING_TX);
1341         netsec_uninit_pkt_dring(priv, NETSEC_RING_RX);
1342
1343         ret = netsec_reset_hardware(priv, false);
1344
1345         phy_stop(ndev->phydev);
1346         phy_disconnect(ndev->phydev);
1347
1348         pm_runtime_put_sync(priv->dev);
1349
1350         return ret;
1351 }
1352
1353 static int netsec_netdev_init(struct net_device *ndev)
1354 {
1355         struct netsec_priv *priv = netdev_priv(ndev);
1356         int ret;
1357
1358         ret = netsec_alloc_dring(priv, NETSEC_RING_TX);
1359         if (ret)
1360                 return ret;
1361
1362         ret = netsec_alloc_dring(priv, NETSEC_RING_RX);
1363         if (ret)
1364                 goto err1;
1365
1366         ret = netsec_reset_hardware(priv, true);
1367         if (ret)
1368                 goto err2;
1369
1370         return 0;
1371 err2:
1372         netsec_free_dring(priv, NETSEC_RING_RX);
1373 err1:
1374         netsec_free_dring(priv, NETSEC_RING_TX);
1375         return ret;
1376 }
1377
1378 static void netsec_netdev_uninit(struct net_device *ndev)
1379 {
1380         struct netsec_priv *priv = netdev_priv(ndev);
1381
1382         netsec_free_dring(priv, NETSEC_RING_RX);
1383         netsec_free_dring(priv, NETSEC_RING_TX);
1384 }
1385
1386 static int netsec_netdev_set_features(struct net_device *ndev,
1387                                       netdev_features_t features)
1388 {
1389         struct netsec_priv *priv = netdev_priv(ndev);
1390
1391         priv->rx_cksum_offload_flag = !!(features & NETIF_F_RXCSUM);
1392
1393         return 0;
1394 }
1395
1396 static int netsec_netdev_ioctl(struct net_device *ndev, struct ifreq *ifr,
1397                                int cmd)
1398 {
1399         return phy_mii_ioctl(ndev->phydev, ifr, cmd);
1400 }
1401
1402 static const struct net_device_ops netsec_netdev_ops = {
1403         .ndo_init               = netsec_netdev_init,
1404         .ndo_uninit             = netsec_netdev_uninit,
1405         .ndo_open               = netsec_netdev_open,
1406         .ndo_stop               = netsec_netdev_stop,
1407         .ndo_start_xmit         = netsec_netdev_start_xmit,
1408         .ndo_set_features       = netsec_netdev_set_features,
1409         .ndo_set_mac_address    = eth_mac_addr,
1410         .ndo_validate_addr      = eth_validate_addr,
1411         .ndo_do_ioctl           = netsec_netdev_ioctl,
1412 };
1413
1414 static int netsec_of_probe(struct platform_device *pdev,
1415                            struct netsec_priv *priv)
1416 {
1417         priv->phy_np = of_parse_phandle(pdev->dev.of_node, "phy-handle", 0);
1418         if (!priv->phy_np) {
1419                 dev_err(&pdev->dev, "missing required property 'phy-handle'\n");
1420                 return -EINVAL;
1421         }
1422
1423         priv->clk = devm_clk_get(&pdev->dev, NULL); /* get by 'phy_ref_clk' */
1424         if (IS_ERR(priv->clk)) {
1425                 dev_err(&pdev->dev, "phy_ref_clk not found\n");
1426                 return PTR_ERR(priv->clk);
1427         }
1428         priv->freq = clk_get_rate(priv->clk);
1429
1430         return 0;
1431 }
1432
1433 static int netsec_acpi_probe(struct platform_device *pdev,
1434                              struct netsec_priv *priv, u32 *phy_addr)
1435 {
1436         int ret;
1437
1438         if (!IS_ENABLED(CONFIG_ACPI))
1439                 return -ENODEV;
1440
1441         ret = device_property_read_u32(&pdev->dev, "phy-channel", phy_addr);
1442         if (ret) {
1443                 dev_err(&pdev->dev,
1444                         "missing required property 'phy-channel'\n");
1445                 return ret;
1446         }
1447
1448         ret = device_property_read_u32(&pdev->dev,
1449                                        "socionext,phy-clock-frequency",
1450                                        &priv->freq);
1451         if (ret)
1452                 dev_err(&pdev->dev,
1453                         "missing required property 'socionext,phy-clock-frequency'\n");
1454         return ret;
1455 }
1456
1457 static void netsec_unregister_mdio(struct netsec_priv *priv)
1458 {
1459         struct phy_device *phydev = priv->phydev;
1460
1461         if (!dev_of_node(priv->dev) && phydev) {
1462                 phy_device_remove(phydev);
1463                 phy_device_free(phydev);
1464         }
1465
1466         mdiobus_unregister(priv->mii_bus);
1467 }
1468
1469 static int netsec_register_mdio(struct netsec_priv *priv, u32 phy_addr)
1470 {
1471         struct mii_bus *bus;
1472         int ret;
1473
1474         bus = devm_mdiobus_alloc(priv->dev);
1475         if (!bus)
1476                 return -ENOMEM;
1477
1478         snprintf(bus->id, MII_BUS_ID_SIZE, "%s", dev_name(priv->dev));
1479         bus->priv = priv;
1480         bus->name = "SNI NETSEC MDIO";
1481         bus->read = netsec_phy_read;
1482         bus->write = netsec_phy_write;
1483         bus->parent = priv->dev;
1484         priv->mii_bus = bus;
1485
1486         if (dev_of_node(priv->dev)) {
1487                 struct device_node *mdio_node, *parent = dev_of_node(priv->dev);
1488
1489                 mdio_node = of_get_child_by_name(parent, "mdio");
1490                 if (mdio_node) {
1491                         parent = mdio_node;
1492                 } else {
1493                         /* older f/w doesn't populate the mdio subnode,
1494                          * allow relaxed upgrade of f/w in due time.
1495                          */
1496                         dev_info(priv->dev, "Upgrade f/w for mdio subnode!\n");
1497                 }
1498
1499                 ret = of_mdiobus_register(bus, parent);
1500                 of_node_put(mdio_node);
1501
1502                 if (ret) {
1503                         dev_err(priv->dev, "mdiobus register err(%d)\n", ret);
1504                         return ret;
1505                 }
1506         } else {
1507                 /* Mask out all PHYs from auto probing. */
1508                 bus->phy_mask = ~0;
1509                 ret = mdiobus_register(bus);
1510                 if (ret) {
1511                         dev_err(priv->dev, "mdiobus register err(%d)\n", ret);
1512                         return ret;
1513                 }
1514
1515                 priv->phydev = get_phy_device(bus, phy_addr, false);
1516                 if (IS_ERR(priv->phydev)) {
1517                         ret = PTR_ERR(priv->phydev);
1518                         dev_err(priv->dev, "get_phy_device err(%d)\n", ret);
1519                         priv->phydev = NULL;
1520                         return -ENODEV;
1521                 }
1522
1523                 ret = phy_device_register(priv->phydev);
1524                 if (ret) {
1525                         mdiobus_unregister(bus);
1526                         dev_err(priv->dev,
1527                                 "phy_device_register err(%d)\n", ret);
1528                 }
1529         }
1530
1531         return ret;
1532 }
1533
1534 static int netsec_probe(struct platform_device *pdev)
1535 {
1536         struct resource *mmio_res, *eeprom_res, *irq_res;
1537         u8 *mac, macbuf[ETH_ALEN];
1538         struct netsec_priv *priv;
1539         u32 hw_ver, phy_addr = 0;
1540         struct net_device *ndev;
1541         int ret;
1542
1543         mmio_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1544         if (!mmio_res) {
1545                 dev_err(&pdev->dev, "No MMIO resource found.\n");
1546                 return -ENODEV;
1547         }
1548
1549         eeprom_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1550         if (!eeprom_res) {
1551                 dev_info(&pdev->dev, "No EEPROM resource found.\n");
1552                 return -ENODEV;
1553         }
1554
1555         irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1556         if (!irq_res) {
1557                 dev_err(&pdev->dev, "No IRQ resource found.\n");
1558                 return -ENODEV;
1559         }
1560
1561         ndev = alloc_etherdev(sizeof(*priv));
1562         if (!ndev)
1563                 return -ENOMEM;
1564
1565         priv = netdev_priv(ndev);
1566
1567         spin_lock_init(&priv->reglock);
1568         SET_NETDEV_DEV(ndev, &pdev->dev);
1569         platform_set_drvdata(pdev, priv);
1570         ndev->irq = irq_res->start;
1571         priv->dev = &pdev->dev;
1572         priv->ndev = ndev;
1573
1574         priv->msg_enable = NETIF_MSG_TX_ERR | NETIF_MSG_HW | NETIF_MSG_DRV |
1575                            NETIF_MSG_LINK | NETIF_MSG_PROBE;
1576
1577         priv->phy_interface = device_get_phy_mode(&pdev->dev);
1578         if (priv->phy_interface < 0) {
1579                 dev_err(&pdev->dev, "missing required property 'phy-mode'\n");
1580                 ret = -ENODEV;
1581                 goto free_ndev;
1582         }
1583
1584         priv->ioaddr = devm_ioremap(&pdev->dev, mmio_res->start,
1585                                     resource_size(mmio_res));
1586         if (!priv->ioaddr) {
1587                 dev_err(&pdev->dev, "devm_ioremap() failed\n");
1588                 ret = -ENXIO;
1589                 goto free_ndev;
1590         }
1591
1592         priv->eeprom_base = devm_ioremap(&pdev->dev, eeprom_res->start,
1593                                          resource_size(eeprom_res));
1594         if (!priv->eeprom_base) {
1595                 dev_err(&pdev->dev, "devm_ioremap() failed for EEPROM\n");
1596                 ret = -ENXIO;
1597                 goto free_ndev;
1598         }
1599
1600         mac = device_get_mac_address(&pdev->dev, macbuf, sizeof(macbuf));
1601         if (mac)
1602                 ether_addr_copy(ndev->dev_addr, mac);
1603
1604         if (priv->eeprom_base &&
1605             (!mac || !is_valid_ether_addr(ndev->dev_addr))) {
1606                 void __iomem *macp = priv->eeprom_base +
1607                                         NETSEC_EEPROM_MAC_ADDRESS;
1608
1609                 ndev->dev_addr[0] = readb(macp + 3);
1610                 ndev->dev_addr[1] = readb(macp + 2);
1611                 ndev->dev_addr[2] = readb(macp + 1);
1612                 ndev->dev_addr[3] = readb(macp + 0);
1613                 ndev->dev_addr[4] = readb(macp + 7);
1614                 ndev->dev_addr[5] = readb(macp + 6);
1615         }
1616
1617         if (!is_valid_ether_addr(ndev->dev_addr)) {
1618                 dev_warn(&pdev->dev, "No MAC address found, using random\n");
1619                 eth_hw_addr_random(ndev);
1620         }
1621
1622         if (dev_of_node(&pdev->dev))
1623                 ret = netsec_of_probe(pdev, priv);
1624         else
1625                 ret = netsec_acpi_probe(pdev, priv, &phy_addr);
1626         if (ret)
1627                 goto free_ndev;
1628
1629         if (!priv->freq) {
1630                 dev_err(&pdev->dev, "missing PHY reference clock frequency\n");
1631                 ret = -ENODEV;
1632                 goto free_ndev;
1633         }
1634
1635         /* default for throughput */
1636         priv->et_coalesce.rx_coalesce_usecs = 500;
1637         priv->et_coalesce.rx_max_coalesced_frames = 8;
1638         priv->et_coalesce.tx_coalesce_usecs = 500;
1639         priv->et_coalesce.tx_max_coalesced_frames = 8;
1640
1641         ret = device_property_read_u32(&pdev->dev, "max-frame-size",
1642                                        &ndev->max_mtu);
1643         if (ret < 0)
1644                 ndev->max_mtu = ETH_DATA_LEN;
1645
1646         /* runtime_pm coverage just for probe, open/close also cover it */
1647         pm_runtime_enable(&pdev->dev);
1648         pm_runtime_get_sync(&pdev->dev);
1649
1650         hw_ver = netsec_read(priv, NETSEC_REG_F_TAIKI_VER);
1651         /* this driver only supports F_TAIKI style NETSEC */
1652         if (NETSEC_F_NETSEC_VER_MAJOR_NUM(hw_ver) !=
1653             NETSEC_F_NETSEC_VER_MAJOR_NUM(NETSEC_REG_NETSEC_VER_F_TAIKI)) {
1654                 ret = -ENODEV;
1655                 goto pm_disable;
1656         }
1657
1658         dev_info(&pdev->dev, "hardware revision %d.%d\n",
1659                  hw_ver >> 16, hw_ver & 0xffff);
1660
1661         netif_napi_add(ndev, &priv->napi, netsec_napi_poll, NAPI_POLL_WEIGHT);
1662
1663         ndev->netdev_ops = &netsec_netdev_ops;
1664         ndev->ethtool_ops = &netsec_ethtool_ops;
1665
1666         ndev->features |= NETIF_F_HIGHDMA | NETIF_F_RXCSUM | NETIF_F_GSO |
1667                                 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
1668         ndev->hw_features = ndev->features;
1669
1670         priv->rx_cksum_offload_flag = true;
1671
1672         ret = netsec_register_mdio(priv, phy_addr);
1673         if (ret)
1674                 goto unreg_napi;
1675
1676         if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(40)))
1677                 dev_warn(&pdev->dev, "Failed to set DMA mask\n");
1678
1679         ret = register_netdev(ndev);
1680         if (ret) {
1681                 netif_err(priv, probe, ndev, "register_netdev() failed\n");
1682                 goto unreg_mii;
1683         }
1684
1685         pm_runtime_put_sync(&pdev->dev);
1686         return 0;
1687
1688 unreg_mii:
1689         netsec_unregister_mdio(priv);
1690 unreg_napi:
1691         netif_napi_del(&priv->napi);
1692 pm_disable:
1693         pm_runtime_put_sync(&pdev->dev);
1694         pm_runtime_disable(&pdev->dev);
1695 free_ndev:
1696         free_netdev(ndev);
1697         dev_err(&pdev->dev, "init failed\n");
1698
1699         return ret;
1700 }
1701
1702 static int netsec_remove(struct platform_device *pdev)
1703 {
1704         struct netsec_priv *priv = platform_get_drvdata(pdev);
1705
1706         unregister_netdev(priv->ndev);
1707
1708         netsec_unregister_mdio(priv);
1709
1710         netif_napi_del(&priv->napi);
1711
1712         pm_runtime_disable(&pdev->dev);
1713         free_netdev(priv->ndev);
1714
1715         return 0;
1716 }
1717
1718 #ifdef CONFIG_PM
1719 static int netsec_runtime_suspend(struct device *dev)
1720 {
1721         struct netsec_priv *priv = dev_get_drvdata(dev);
1722
1723         netsec_write(priv, NETSEC_REG_CLK_EN, 0);
1724
1725         clk_disable_unprepare(priv->clk);
1726
1727         return 0;
1728 }
1729
1730 static int netsec_runtime_resume(struct device *dev)
1731 {
1732         struct netsec_priv *priv = dev_get_drvdata(dev);
1733
1734         clk_prepare_enable(priv->clk);
1735
1736         netsec_write(priv, NETSEC_REG_CLK_EN, NETSEC_CLK_EN_REG_DOM_D |
1737                                                NETSEC_CLK_EN_REG_DOM_C |
1738                                                NETSEC_CLK_EN_REG_DOM_G);
1739         return 0;
1740 }
1741 #endif
1742
1743 static const struct dev_pm_ops netsec_pm_ops = {
1744         SET_RUNTIME_PM_OPS(netsec_runtime_suspend, netsec_runtime_resume, NULL)
1745 };
1746
1747 static const struct of_device_id netsec_dt_ids[] = {
1748         { .compatible = "socionext,synquacer-netsec" },
1749         { }
1750 };
1751 MODULE_DEVICE_TABLE(of, netsec_dt_ids);
1752
1753 #ifdef CONFIG_ACPI
1754 static const struct acpi_device_id netsec_acpi_ids[] = {
1755         { "SCX0001" },
1756         { }
1757 };
1758 MODULE_DEVICE_TABLE(acpi, netsec_acpi_ids);
1759 #endif
1760
1761 static struct platform_driver netsec_driver = {
1762         .probe  = netsec_probe,
1763         .remove = netsec_remove,
1764         .driver = {
1765                 .name = "netsec",
1766                 .pm = &netsec_pm_ops,
1767                 .of_match_table = netsec_dt_ids,
1768                 .acpi_match_table = ACPI_PTR(netsec_acpi_ids),
1769         },
1770 };
1771 module_platform_driver(netsec_driver);
1772
1773 MODULE_AUTHOR("Jassi Brar <jaswinder.singh@linaro.org>");
1774 MODULE_AUTHOR("Ard Biesheuvel <ard.biesheuvel@linaro.org>");
1775 MODULE_DESCRIPTION("NETSEC Ethernet driver");
1776 MODULE_LICENSE("GPL");