1 // SPDX-License-Identifier: GPL-2.0-only
2 /****************************************************************************
3 * Driver for Solarflare network controllers and boards
4 * Copyright 2005-2006 Fen Systems Ltd.
5 * Copyright 2006-2013 Solarflare Communications Inc.
8 #include <linux/bitops.h>
9 #include <linux/delay.h>
10 #include <linux/pci.h>
11 #include <linux/module.h>
12 #include <linux/slab.h>
13 #include <linux/random.h>
14 #include "net_driver.h"
17 #include "efx_common.h"
19 #include "farch_regs.h"
21 #include "workarounds.h"
23 #include "mcdi_pcol.h"
24 #include "mcdi_port_common.h"
26 #include "siena_sriov.h"
28 /* Hardware control for SFC9000 family including SFL9021 (aka Siena). */
30 static void siena_init_wol(struct efx_nic *efx);
33 static void siena_push_irq_moderation(struct efx_channel *channel)
35 struct efx_nic *efx = channel->efx;
36 efx_dword_t timer_cmd;
38 if (channel->irq_moderation_us) {
41 ticks = efx_usecs_to_ticks(efx, channel->irq_moderation_us);
42 EFX_POPULATE_DWORD_2(timer_cmd,
44 FFE_CZ_TIMER_MODE_INT_HLDOFF,
48 EFX_POPULATE_DWORD_2(timer_cmd,
50 FFE_CZ_TIMER_MODE_DIS,
51 FRF_CZ_TC_TIMER_VAL, 0);
53 efx_writed_page_locked(channel->efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0,
57 void siena_prepare_flush(struct efx_nic *efx)
59 if (efx->fc_disable++ == 0)
60 efx_mcdi_set_mac(efx);
63 void siena_finish_flush(struct efx_nic *efx)
65 if (--efx->fc_disable == 0)
66 efx_mcdi_set_mac(efx);
69 static const struct efx_farch_register_test siena_register_tests[] = {
71 EFX_OWORD32(0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF) },
73 EFX_OWORD32(0x000103FF, 0x00000000, 0x00000000, 0x00000000) },
75 EFX_OWORD32(0xFFFFFFFE, 0xFFFFFFFF, 0x0003FFFF, 0x00000000) },
77 EFX_OWORD32(0x7FFF0037, 0xFFFF8000, 0xFFFFFFFF, 0x03FFFFFF) },
79 EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
80 { FR_AZ_SRM_TX_DC_CFG,
81 EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
83 EFX_OWORD32(0x00000003, 0x00000000, 0x00000000, 0x00000000) },
85 EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
87 EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
89 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
90 { FR_CZ_RX_RSS_IPV6_REG1,
91 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
92 { FR_CZ_RX_RSS_IPV6_REG2,
93 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
94 { FR_CZ_RX_RSS_IPV6_REG3,
95 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0x00000007, 0x00000000) },
98 static int siena_test_chip(struct efx_nic *efx, struct efx_self_tests *tests)
100 enum reset_type reset_method = RESET_TYPE_ALL;
103 efx_reset_down(efx, reset_method);
105 /* Reset the chip immediately so that it is completely
106 * quiescent regardless of what any VF driver does.
108 rc = efx_mcdi_reset(efx, reset_method);
113 efx_farch_test_registers(efx, siena_register_tests,
114 ARRAY_SIZE(siena_register_tests))
117 rc = efx_mcdi_reset(efx, reset_method);
119 rc2 = efx_reset_up(efx, reset_method, rc == 0);
120 return rc ? rc : rc2;
123 /**************************************************************************
127 **************************************************************************
130 static void siena_ptp_write_host_time(struct efx_nic *efx, u32 host_time)
132 _efx_writed(efx, cpu_to_le32(host_time),
133 FR_CZ_MC_TREG_SMEM + MC_SMEM_P0_PTP_TIME_OFST);
136 static int siena_ptp_set_ts_config(struct efx_nic *efx,
137 struct hwtstamp_config *init)
141 switch (init->rx_filter) {
142 case HWTSTAMP_FILTER_NONE:
143 /* if TX timestamping is still requested then leave PTP on */
144 return efx_ptp_change_mode(efx,
145 init->tx_type != HWTSTAMP_TX_OFF,
146 efx_ptp_get_mode(efx));
147 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
148 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
149 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
150 init->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
151 return efx_ptp_change_mode(efx, true, MC_CMD_PTP_MODE_V1);
152 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
153 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
154 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
155 init->rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
156 rc = efx_ptp_change_mode(efx, true,
157 MC_CMD_PTP_MODE_V2_ENHANCED);
158 /* bug 33070 - old versions of the firmware do not support the
159 * improved UUID filtering option. Similarly old versions of the
160 * application do not expect it to be enabled. If the firmware
161 * does not accept the enhanced mode, fall back to the standard
162 * PTP v2 UUID filtering. */
164 rc = efx_ptp_change_mode(efx, true, MC_CMD_PTP_MODE_V2);
171 /**************************************************************************
175 **************************************************************************
178 static int siena_map_reset_flags(u32 *flags)
181 SIENA_RESET_PORT = (ETH_RESET_DMA | ETH_RESET_FILTER |
182 ETH_RESET_OFFLOAD | ETH_RESET_MAC |
184 SIENA_RESET_MC = (SIENA_RESET_PORT |
185 ETH_RESET_MGMT << ETH_RESET_SHARED_SHIFT),
188 if ((*flags & SIENA_RESET_MC) == SIENA_RESET_MC) {
189 *flags &= ~SIENA_RESET_MC;
190 return RESET_TYPE_WORLD;
193 if ((*flags & SIENA_RESET_PORT) == SIENA_RESET_PORT) {
194 *flags &= ~SIENA_RESET_PORT;
195 return RESET_TYPE_ALL;
198 /* no invisible reset implemented */
204 /* When a PCI device is isolated from the bus, a subsequent MMIO read is
205 * required for the kernel EEH mechanisms to notice. As the Solarflare driver
206 * was written to minimise MMIO read (for latency) then a periodic call to check
207 * the EEH status of the device is required so that device recovery can happen
208 * in a timely fashion.
210 static void siena_monitor(struct efx_nic *efx)
212 struct eeh_dev *eehdev = pci_dev_to_eeh_dev(efx->pci_dev);
214 eeh_dev_check_failure(eehdev);
218 static int siena_probe_nvconfig(struct efx_nic *efx)
223 rc = efx_mcdi_get_board_cfg(efx, efx->net_dev->perm_addr, NULL, &caps);
225 efx->timer_quantum_ns =
226 (caps & (1 << MC_CMD_CAPABILITIES_TURBO_ACTIVE_LBN)) ?
227 3072 : 6144; /* 768 cycles */
228 efx->timer_max_ns = efx->type->timer_period_max *
229 efx->timer_quantum_ns;
234 static int siena_dimension_resources(struct efx_nic *efx)
236 /* Each port has a small block of internal SRAM dedicated to
237 * the buffer table and descriptor caches. In theory we can
238 * map both blocks to one port, but we don't.
240 efx_farch_dimension_resources(efx, FR_CZ_BUF_FULL_TBL_ROWS / 2);
244 /* On all Falcon-architecture NICs, PFs use BAR 0 for I/O space and BAR 2(&3)
247 static unsigned int siena_mem_bar(struct efx_nic *efx)
252 static unsigned int siena_mem_map_size(struct efx_nic *efx)
254 return FR_CZ_MC_TREG_SMEM +
255 FR_CZ_MC_TREG_SMEM_STEP * FR_CZ_MC_TREG_SMEM_ROWS;
258 static int siena_probe_nic(struct efx_nic *efx)
260 struct siena_nic_data *nic_data;
264 /* Allocate storage for hardware specific data */
265 nic_data = kzalloc(sizeof(struct siena_nic_data), GFP_KERNEL);
269 efx->nic_data = nic_data;
271 if (efx_farch_fpga_ver(efx) != 0) {
272 netif_err(efx, probe, efx->net_dev,
273 "Siena FPGA not supported\n");
278 efx->max_channels = EFX_MAX_CHANNELS;
279 efx->max_tx_channels = EFX_MAX_CHANNELS;
281 efx_reado(efx, ®, FR_AZ_CS_DEBUG);
282 efx->port_num = EFX_OWORD_FIELD(reg, FRF_CZ_CS_PORT_NUM) - 1;
284 rc = efx_mcdi_init(efx);
288 /* Now we can reset the NIC */
289 rc = efx_mcdi_reset(efx, RESET_TYPE_ALL);
291 netif_err(efx, probe, efx->net_dev, "failed to reset NIC\n");
297 /* Allocate memory for INT_KER */
298 rc = efx_nic_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t),
302 BUG_ON(efx->irq_status.dma_addr & 0x0f);
304 netif_dbg(efx, probe, efx->net_dev,
305 "INT_KER at %llx (virt %p phys %llx)\n",
306 (unsigned long long)efx->irq_status.dma_addr,
307 efx->irq_status.addr,
308 (unsigned long long)virt_to_phys(efx->irq_status.addr));
310 /* Read in the non-volatile configuration */
311 rc = siena_probe_nvconfig(efx);
313 netif_err(efx, probe, efx->net_dev,
314 "NVRAM is invalid therefore using defaults\n");
315 efx->phy_type = PHY_TYPE_NONE;
316 efx->mdio.prtad = MDIO_PRTAD_NONE;
321 rc = efx_mcdi_mon_probe(efx);
325 #ifdef CONFIG_SFC_SRIOV
326 efx_siena_sriov_probe(efx);
328 efx_ptp_defer_probe_with_channel(efx);
333 efx_nic_free_buffer(efx, &efx->irq_status);
336 efx_mcdi_detach(efx);
339 kfree(efx->nic_data);
343 static int siena_rx_pull_rss_config(struct efx_nic *efx)
347 /* Read from IPv6 RSS key as that's longer (the IPv4 key is just the
348 * first 128 bits of the same key, assuming it's been set by
349 * siena_rx_push_rss_config, below)
351 efx_reado(efx, &temp, FR_CZ_RX_RSS_IPV6_REG1);
352 memcpy(efx->rss_context.rx_hash_key, &temp, sizeof(temp));
353 efx_reado(efx, &temp, FR_CZ_RX_RSS_IPV6_REG2);
354 memcpy(efx->rss_context.rx_hash_key + sizeof(temp), &temp, sizeof(temp));
355 efx_reado(efx, &temp, FR_CZ_RX_RSS_IPV6_REG3);
356 memcpy(efx->rss_context.rx_hash_key + 2 * sizeof(temp), &temp,
357 FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8);
358 efx_farch_rx_pull_indir_table(efx);
362 static int siena_rx_push_rss_config(struct efx_nic *efx, bool user,
363 const u32 *rx_indir_table, const u8 *key)
367 /* Set hash key for IPv4 */
369 memcpy(efx->rss_context.rx_hash_key, key, sizeof(temp));
370 memcpy(&temp, efx->rss_context.rx_hash_key, sizeof(temp));
371 efx_writeo(efx, &temp, FR_BZ_RX_RSS_TKEY);
373 /* Enable IPv6 RSS */
374 BUILD_BUG_ON(sizeof(efx->rss_context.rx_hash_key) <
375 2 * sizeof(temp) + FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8 ||
376 FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN != 0);
377 memcpy(&temp, efx->rss_context.rx_hash_key, sizeof(temp));
378 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG1);
379 memcpy(&temp, efx->rss_context.rx_hash_key + sizeof(temp), sizeof(temp));
380 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG2);
381 EFX_POPULATE_OWORD_2(temp, FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 1,
382 FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE, 1);
383 memcpy(&temp, efx->rss_context.rx_hash_key + 2 * sizeof(temp),
384 FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8);
385 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG3);
387 memcpy(efx->rss_context.rx_indir_table, rx_indir_table,
388 sizeof(efx->rss_context.rx_indir_table));
389 efx_farch_rx_push_indir_table(efx);
394 /* This call performs hardware-specific global initialisation, such as
395 * defining the descriptor cache sizes and number of RSS channels.
396 * It does not set up any buffers, descriptor rings or event queues.
398 static int siena_init_nic(struct efx_nic *efx)
403 /* Recover from a failed assertion post-reset */
404 rc = efx_mcdi_handle_assertion(efx);
408 /* Squash TX of packets of 16 bytes or less */
409 efx_reado(efx, &temp, FR_AZ_TX_RESERVED);
410 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1);
411 efx_writeo(efx, &temp, FR_AZ_TX_RESERVED);
413 /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
414 * descriptors (which is bad).
416 efx_reado(efx, &temp, FR_AZ_TX_CFG);
417 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0);
418 EFX_SET_OWORD_FIELD(temp, FRF_CZ_TX_FILTER_EN_BIT, 1);
419 efx_writeo(efx, &temp, FR_AZ_TX_CFG);
421 efx_reado(efx, &temp, FR_AZ_RX_CFG);
422 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_DESC_PUSH_EN, 0);
423 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_INGR_EN, 1);
424 /* Enable hash insertion. This is broken for the 'Falcon' hash
425 * if IPv6 hashing is also enabled, so also select Toeplitz
426 * TCP/IPv4 and IPv4 hashes. */
427 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_HASH_INSRT_HDR, 1);
428 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_HASH_ALG, 1);
429 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_IP_HASH, 1);
430 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_USR_BUF_SIZE,
431 EFX_RX_USR_BUF_SIZE >> 5);
432 efx_writeo(efx, &temp, FR_AZ_RX_CFG);
434 siena_rx_push_rss_config(efx, false, efx->rss_context.rx_indir_table, NULL);
435 efx->rss_context.context_id = 0; /* indicates RSS is active */
437 /* Enable event logging */
438 rc = efx_mcdi_log_ctrl(efx, true, false, 0);
442 /* Set destination of both TX and RX Flush events */
443 EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0);
444 efx_writeo(efx, &temp, FR_BZ_DP_CTRL);
446 EFX_POPULATE_OWORD_1(temp, FRF_CZ_USREV_DIS, 1);
447 efx_writeo(efx, &temp, FR_CZ_USR_EV_CFG);
449 efx_farch_init_common(efx);
453 static void siena_remove_nic(struct efx_nic *efx)
455 efx_mcdi_mon_remove(efx);
457 efx_nic_free_buffer(efx, &efx->irq_status);
459 efx_mcdi_reset(efx, RESET_TYPE_ALL);
461 efx_mcdi_detach(efx);
464 /* Tear down the private nic state */
465 kfree(efx->nic_data);
466 efx->nic_data = NULL;
469 #define SIENA_DMA_STAT(ext_name, mcdi_name) \
470 [SIENA_STAT_ ## ext_name] = \
471 { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
472 #define SIENA_OTHER_STAT(ext_name) \
473 [SIENA_STAT_ ## ext_name] = { #ext_name, 0, 0 }
474 #define GENERIC_SW_STAT(ext_name) \
475 [GENERIC_STAT_ ## ext_name] = { #ext_name, 0, 0 }
477 static const struct efx_hw_stat_desc siena_stat_desc[SIENA_STAT_COUNT] = {
478 SIENA_DMA_STAT(tx_bytes, TX_BYTES),
479 SIENA_OTHER_STAT(tx_good_bytes),
480 SIENA_DMA_STAT(tx_bad_bytes, TX_BAD_BYTES),
481 SIENA_DMA_STAT(tx_packets, TX_PKTS),
482 SIENA_DMA_STAT(tx_bad, TX_BAD_FCS_PKTS),
483 SIENA_DMA_STAT(tx_pause, TX_PAUSE_PKTS),
484 SIENA_DMA_STAT(tx_control, TX_CONTROL_PKTS),
485 SIENA_DMA_STAT(tx_unicast, TX_UNICAST_PKTS),
486 SIENA_DMA_STAT(tx_multicast, TX_MULTICAST_PKTS),
487 SIENA_DMA_STAT(tx_broadcast, TX_BROADCAST_PKTS),
488 SIENA_DMA_STAT(tx_lt64, TX_LT64_PKTS),
489 SIENA_DMA_STAT(tx_64, TX_64_PKTS),
490 SIENA_DMA_STAT(tx_65_to_127, TX_65_TO_127_PKTS),
491 SIENA_DMA_STAT(tx_128_to_255, TX_128_TO_255_PKTS),
492 SIENA_DMA_STAT(tx_256_to_511, TX_256_TO_511_PKTS),
493 SIENA_DMA_STAT(tx_512_to_1023, TX_512_TO_1023_PKTS),
494 SIENA_DMA_STAT(tx_1024_to_15xx, TX_1024_TO_15XX_PKTS),
495 SIENA_DMA_STAT(tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS),
496 SIENA_DMA_STAT(tx_gtjumbo, TX_GTJUMBO_PKTS),
497 SIENA_OTHER_STAT(tx_collision),
498 SIENA_DMA_STAT(tx_single_collision, TX_SINGLE_COLLISION_PKTS),
499 SIENA_DMA_STAT(tx_multiple_collision, TX_MULTIPLE_COLLISION_PKTS),
500 SIENA_DMA_STAT(tx_excessive_collision, TX_EXCESSIVE_COLLISION_PKTS),
501 SIENA_DMA_STAT(tx_deferred, TX_DEFERRED_PKTS),
502 SIENA_DMA_STAT(tx_late_collision, TX_LATE_COLLISION_PKTS),
503 SIENA_DMA_STAT(tx_excessive_deferred, TX_EXCESSIVE_DEFERRED_PKTS),
504 SIENA_DMA_STAT(tx_non_tcpudp, TX_NON_TCPUDP_PKTS),
505 SIENA_DMA_STAT(tx_mac_src_error, TX_MAC_SRC_ERR_PKTS),
506 SIENA_DMA_STAT(tx_ip_src_error, TX_IP_SRC_ERR_PKTS),
507 SIENA_DMA_STAT(rx_bytes, RX_BYTES),
508 SIENA_OTHER_STAT(rx_good_bytes),
509 SIENA_DMA_STAT(rx_bad_bytes, RX_BAD_BYTES),
510 SIENA_DMA_STAT(rx_packets, RX_PKTS),
511 SIENA_DMA_STAT(rx_good, RX_GOOD_PKTS),
512 SIENA_DMA_STAT(rx_bad, RX_BAD_FCS_PKTS),
513 SIENA_DMA_STAT(rx_pause, RX_PAUSE_PKTS),
514 SIENA_DMA_STAT(rx_control, RX_CONTROL_PKTS),
515 SIENA_DMA_STAT(rx_unicast, RX_UNICAST_PKTS),
516 SIENA_DMA_STAT(rx_multicast, RX_MULTICAST_PKTS),
517 SIENA_DMA_STAT(rx_broadcast, RX_BROADCAST_PKTS),
518 SIENA_DMA_STAT(rx_lt64, RX_UNDERSIZE_PKTS),
519 SIENA_DMA_STAT(rx_64, RX_64_PKTS),
520 SIENA_DMA_STAT(rx_65_to_127, RX_65_TO_127_PKTS),
521 SIENA_DMA_STAT(rx_128_to_255, RX_128_TO_255_PKTS),
522 SIENA_DMA_STAT(rx_256_to_511, RX_256_TO_511_PKTS),
523 SIENA_DMA_STAT(rx_512_to_1023, RX_512_TO_1023_PKTS),
524 SIENA_DMA_STAT(rx_1024_to_15xx, RX_1024_TO_15XX_PKTS),
525 SIENA_DMA_STAT(rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS),
526 SIENA_DMA_STAT(rx_gtjumbo, RX_GTJUMBO_PKTS),
527 SIENA_DMA_STAT(rx_bad_gtjumbo, RX_JABBER_PKTS),
528 SIENA_DMA_STAT(rx_overflow, RX_OVERFLOW_PKTS),
529 SIENA_DMA_STAT(rx_false_carrier, RX_FALSE_CARRIER_PKTS),
530 SIENA_DMA_STAT(rx_symbol_error, RX_SYMBOL_ERROR_PKTS),
531 SIENA_DMA_STAT(rx_align_error, RX_ALIGN_ERROR_PKTS),
532 SIENA_DMA_STAT(rx_length_error, RX_LENGTH_ERROR_PKTS),
533 SIENA_DMA_STAT(rx_internal_error, RX_INTERNAL_ERROR_PKTS),
534 SIENA_DMA_STAT(rx_nodesc_drop_cnt, RX_NODESC_DROPS),
535 GENERIC_SW_STAT(rx_nodesc_trunc),
536 GENERIC_SW_STAT(rx_noskb_drops),
538 static const unsigned long siena_stat_mask[] = {
539 [0 ... BITS_TO_LONGS(SIENA_STAT_COUNT) - 1] = ~0UL,
542 static size_t siena_describe_nic_stats(struct efx_nic *efx, u8 *names)
544 return efx_nic_describe_stats(siena_stat_desc, SIENA_STAT_COUNT,
545 siena_stat_mask, names);
548 static int siena_try_update_nic_stats(struct efx_nic *efx)
550 struct siena_nic_data *nic_data = efx->nic_data;
551 u64 *stats = nic_data->stats;
553 __le64 generation_start, generation_end;
555 dma_stats = efx->stats_buffer.addr;
557 generation_end = dma_stats[efx->num_mac_stats - 1];
558 if (generation_end == EFX_MC_STATS_GENERATION_INVALID)
561 efx_nic_update_stats(siena_stat_desc, SIENA_STAT_COUNT, siena_stat_mask,
562 stats, efx->stats_buffer.addr, false);
564 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
565 if (generation_end != generation_start)
568 /* Update derived statistics */
569 efx_nic_fix_nodesc_drop_stat(efx,
570 &stats[SIENA_STAT_rx_nodesc_drop_cnt]);
571 efx_update_diff_stat(&stats[SIENA_STAT_tx_good_bytes],
572 stats[SIENA_STAT_tx_bytes] -
573 stats[SIENA_STAT_tx_bad_bytes]);
574 stats[SIENA_STAT_tx_collision] =
575 stats[SIENA_STAT_tx_single_collision] +
576 stats[SIENA_STAT_tx_multiple_collision] +
577 stats[SIENA_STAT_tx_excessive_collision] +
578 stats[SIENA_STAT_tx_late_collision];
579 efx_update_diff_stat(&stats[SIENA_STAT_rx_good_bytes],
580 stats[SIENA_STAT_rx_bytes] -
581 stats[SIENA_STAT_rx_bad_bytes]);
582 efx_update_sw_stats(efx, stats);
586 static size_t siena_update_nic_stats(struct efx_nic *efx, u64 *full_stats,
587 struct rtnl_link_stats64 *core_stats)
589 struct siena_nic_data *nic_data = efx->nic_data;
590 u64 *stats = nic_data->stats;
593 /* If we're unlucky enough to read statistics wduring the DMA, wait
594 * up to 10ms for it to finish (typically takes <500us) */
595 for (retry = 0; retry < 100; ++retry) {
596 if (siena_try_update_nic_stats(efx) == 0)
602 memcpy(full_stats, stats, sizeof(u64) * SIENA_STAT_COUNT);
605 core_stats->rx_packets = stats[SIENA_STAT_rx_packets];
606 core_stats->tx_packets = stats[SIENA_STAT_tx_packets];
607 core_stats->rx_bytes = stats[SIENA_STAT_rx_bytes];
608 core_stats->tx_bytes = stats[SIENA_STAT_tx_bytes];
609 core_stats->rx_dropped = stats[SIENA_STAT_rx_nodesc_drop_cnt] +
610 stats[GENERIC_STAT_rx_nodesc_trunc] +
611 stats[GENERIC_STAT_rx_noskb_drops];
612 core_stats->multicast = stats[SIENA_STAT_rx_multicast];
613 core_stats->collisions = stats[SIENA_STAT_tx_collision];
614 core_stats->rx_length_errors =
615 stats[SIENA_STAT_rx_gtjumbo] +
616 stats[SIENA_STAT_rx_length_error];
617 core_stats->rx_crc_errors = stats[SIENA_STAT_rx_bad];
618 core_stats->rx_frame_errors = stats[SIENA_STAT_rx_align_error];
619 core_stats->rx_fifo_errors = stats[SIENA_STAT_rx_overflow];
620 core_stats->tx_window_errors =
621 stats[SIENA_STAT_tx_late_collision];
623 core_stats->rx_errors = (core_stats->rx_length_errors +
624 core_stats->rx_crc_errors +
625 core_stats->rx_frame_errors +
626 stats[SIENA_STAT_rx_symbol_error]);
627 core_stats->tx_errors = (core_stats->tx_window_errors +
628 stats[SIENA_STAT_tx_bad]);
631 return SIENA_STAT_COUNT;
634 static int siena_mac_reconfigure(struct efx_nic *efx)
636 MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_MCAST_HASH_IN_LEN);
639 BUILD_BUG_ON(MC_CMD_SET_MCAST_HASH_IN_LEN !=
640 MC_CMD_SET_MCAST_HASH_IN_HASH0_OFST +
641 sizeof(efx->multicast_hash));
643 efx_farch_filter_sync_rx_mode(efx);
645 WARN_ON(!mutex_is_locked(&efx->mac_lock));
647 rc = efx_mcdi_set_mac(efx);
651 memcpy(MCDI_PTR(inbuf, SET_MCAST_HASH_IN_HASH0),
652 efx->multicast_hash.byte, sizeof(efx->multicast_hash));
653 return efx_mcdi_rpc(efx, MC_CMD_SET_MCAST_HASH,
654 inbuf, sizeof(inbuf), NULL, 0, NULL);
657 /**************************************************************************
661 **************************************************************************
664 static void siena_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
666 struct siena_nic_data *nic_data = efx->nic_data;
668 wol->supported = WAKE_MAGIC;
669 if (nic_data->wol_filter_id != -1)
670 wol->wolopts = WAKE_MAGIC;
673 memset(&wol->sopass, 0, sizeof(wol->sopass));
677 static int siena_set_wol(struct efx_nic *efx, u32 type)
679 struct siena_nic_data *nic_data = efx->nic_data;
682 if (type & ~WAKE_MAGIC)
685 if (type & WAKE_MAGIC) {
686 if (nic_data->wol_filter_id != -1)
687 efx_mcdi_wol_filter_remove(efx,
688 nic_data->wol_filter_id);
689 rc = efx_mcdi_wol_filter_set_magic(efx, efx->net_dev->dev_addr,
690 &nic_data->wol_filter_id);
694 pci_wake_from_d3(efx->pci_dev, true);
696 rc = efx_mcdi_wol_filter_reset(efx);
697 nic_data->wol_filter_id = -1;
698 pci_wake_from_d3(efx->pci_dev, false);
705 netif_err(efx, hw, efx->net_dev, "%s failed: type=%d rc=%d\n",
711 static void siena_init_wol(struct efx_nic *efx)
713 struct siena_nic_data *nic_data = efx->nic_data;
716 rc = efx_mcdi_wol_filter_get_magic(efx, &nic_data->wol_filter_id);
719 /* If it failed, attempt to get into a synchronised
720 * state with MC by resetting any set WoL filters */
721 efx_mcdi_wol_filter_reset(efx);
722 nic_data->wol_filter_id = -1;
723 } else if (nic_data->wol_filter_id != -1) {
724 pci_wake_from_d3(efx->pci_dev, true);
728 /**************************************************************************
732 **************************************************************************
735 #define MCDI_PDU(efx) \
736 (efx_port_num(efx) ? MC_SMEM_P1_PDU_OFST : MC_SMEM_P0_PDU_OFST)
737 #define MCDI_DOORBELL(efx) \
738 (efx_port_num(efx) ? MC_SMEM_P1_DOORBELL_OFST : MC_SMEM_P0_DOORBELL_OFST)
739 #define MCDI_STATUS(efx) \
740 (efx_port_num(efx) ? MC_SMEM_P1_STATUS_OFST : MC_SMEM_P0_STATUS_OFST)
742 static void siena_mcdi_request(struct efx_nic *efx,
743 const efx_dword_t *hdr, size_t hdr_len,
744 const efx_dword_t *sdu, size_t sdu_len)
746 unsigned pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
747 unsigned doorbell = FR_CZ_MC_TREG_SMEM + MCDI_DOORBELL(efx);
749 unsigned int inlen_dw = DIV_ROUND_UP(sdu_len, 4);
751 EFX_WARN_ON_PARANOID(hdr_len != 4);
753 efx_writed(efx, hdr, pdu);
755 for (i = 0; i < inlen_dw; i++)
756 efx_writed(efx, &sdu[i], pdu + hdr_len + 4 * i);
758 /* Ensure the request is written out before the doorbell */
761 /* ring the doorbell with a distinctive value */
762 _efx_writed(efx, (__force __le32) 0x45789abc, doorbell);
765 static bool siena_mcdi_poll_response(struct efx_nic *efx)
767 unsigned int pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
770 efx_readd(efx, &hdr, pdu);
772 /* All 1's indicates that shared memory is in reset (and is
773 * not a valid hdr). Wait for it to come out reset before
774 * completing the command
776 return EFX_DWORD_FIELD(hdr, EFX_DWORD_0) != 0xffffffff &&
777 EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE);
780 static void siena_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf,
781 size_t offset, size_t outlen)
783 unsigned int pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
784 unsigned int outlen_dw = DIV_ROUND_UP(outlen, 4);
787 for (i = 0; i < outlen_dw; i++)
788 efx_readd(efx, &outbuf[i], pdu + offset + 4 * i);
791 static int siena_mcdi_poll_reboot(struct efx_nic *efx)
793 struct siena_nic_data *nic_data = efx->nic_data;
794 unsigned int addr = FR_CZ_MC_TREG_SMEM + MCDI_STATUS(efx);
798 efx_readd(efx, ®, addr);
799 value = EFX_DWORD_FIELD(reg, EFX_DWORD_0);
805 efx_writed(efx, ®, addr);
807 /* MAC statistics have been cleared on the NIC; clear the local
808 * copies that we update with efx_update_diff_stat().
810 nic_data->stats[SIENA_STAT_tx_good_bytes] = 0;
811 nic_data->stats[SIENA_STAT_rx_good_bytes] = 0;
813 if (value == MC_STATUS_DWORD_ASSERT)
819 /**************************************************************************
823 **************************************************************************
826 #ifdef CONFIG_SFC_MTD
828 struct siena_nvram_type_info {
833 static const struct siena_nvram_type_info siena_nvram_types[] = {
834 [MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO] = { 0, "sfc_dummy_phy" },
835 [MC_CMD_NVRAM_TYPE_MC_FW] = { 0, "sfc_mcfw" },
836 [MC_CMD_NVRAM_TYPE_MC_FW_BACKUP] = { 0, "sfc_mcfw_backup" },
837 [MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT0] = { 0, "sfc_static_cfg" },
838 [MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT1] = { 1, "sfc_static_cfg" },
839 [MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0] = { 0, "sfc_dynamic_cfg" },
840 [MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1] = { 1, "sfc_dynamic_cfg" },
841 [MC_CMD_NVRAM_TYPE_EXP_ROM] = { 0, "sfc_exp_rom" },
842 [MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT0] = { 0, "sfc_exp_rom_cfg" },
843 [MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT1] = { 1, "sfc_exp_rom_cfg" },
844 [MC_CMD_NVRAM_TYPE_PHY_PORT0] = { 0, "sfc_phy_fw" },
845 [MC_CMD_NVRAM_TYPE_PHY_PORT1] = { 1, "sfc_phy_fw" },
846 [MC_CMD_NVRAM_TYPE_FPGA] = { 0, "sfc_fpga" },
849 static int siena_mtd_probe_partition(struct efx_nic *efx,
850 struct efx_mcdi_mtd_partition *part,
853 const struct siena_nvram_type_info *info;
854 size_t size, erase_size;
858 if (type >= ARRAY_SIZE(siena_nvram_types) ||
859 siena_nvram_types[type].name == NULL)
862 info = &siena_nvram_types[type];
864 if (info->port != efx_port_num(efx))
867 rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected);
871 return -ENODEV; /* hide it */
873 part->nvram_type = type;
874 part->common.dev_type_name = "Siena NVRAM manager";
875 part->common.type_name = info->name;
877 part->common.mtd.type = MTD_NORFLASH;
878 part->common.mtd.flags = MTD_CAP_NORFLASH;
879 part->common.mtd.size = size;
880 part->common.mtd.erasesize = erase_size;
885 static int siena_mtd_get_fw_subtypes(struct efx_nic *efx,
886 struct efx_mcdi_mtd_partition *parts,
889 uint16_t fw_subtype_list[
890 MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MAXNUM];
894 rc = efx_mcdi_get_board_cfg(efx, NULL, fw_subtype_list, NULL);
898 for (i = 0; i < n_parts; i++)
899 parts[i].fw_subtype = fw_subtype_list[parts[i].nvram_type];
904 static int siena_mtd_probe(struct efx_nic *efx)
906 struct efx_mcdi_mtd_partition *parts;
914 rc = efx_mcdi_nvram_types(efx, &nvram_types);
918 parts = kcalloc(hweight32(nvram_types), sizeof(*parts), GFP_KERNEL);
925 while (nvram_types != 0) {
926 if (nvram_types & 1) {
927 rc = siena_mtd_probe_partition(efx, &parts[n_parts],
931 else if (rc != -ENODEV)
938 rc = siena_mtd_get_fw_subtypes(efx, parts, n_parts);
942 rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts));
949 #endif /* CONFIG_SFC_MTD */
951 unsigned int siena_check_caps(const struct efx_nic *efx,
954 /* Siena did not support MC_CMD_GET_CAPABILITIES */
958 /**************************************************************************
960 * Revision-dependent attributes used by efx.c and nic.c
962 **************************************************************************
965 const struct efx_nic_type siena_a0_nic_type = {
967 .mem_bar = siena_mem_bar,
968 .mem_map_size = siena_mem_map_size,
969 .probe = siena_probe_nic,
970 .remove = siena_remove_nic,
971 .init = siena_init_nic,
972 .dimension_resources = siena_dimension_resources,
973 .fini = efx_port_dummy_op_void,
975 .monitor = siena_monitor,
979 .map_reset_reason = efx_mcdi_map_reset_reason,
980 .map_reset_flags = siena_map_reset_flags,
981 .reset = efx_mcdi_reset,
982 .probe_port = efx_mcdi_port_probe,
983 .remove_port = efx_mcdi_port_remove,
984 .fini_dmaq = efx_farch_fini_dmaq,
985 .prepare_flush = siena_prepare_flush,
986 .finish_flush = siena_finish_flush,
987 .prepare_flr = efx_port_dummy_op_void,
988 .finish_flr = efx_farch_finish_flr,
989 .describe_stats = siena_describe_nic_stats,
990 .update_stats = siena_update_nic_stats,
991 .start_stats = efx_mcdi_mac_start_stats,
992 .pull_stats = efx_mcdi_mac_pull_stats,
993 .stop_stats = efx_mcdi_mac_stop_stats,
994 .set_id_led = efx_mcdi_set_id_led,
995 .push_irq_moderation = siena_push_irq_moderation,
996 .reconfigure_mac = siena_mac_reconfigure,
997 .check_mac_fault = efx_mcdi_mac_check_fault,
998 .reconfigure_port = efx_mcdi_port_reconfigure,
999 .get_wol = siena_get_wol,
1000 .set_wol = siena_set_wol,
1001 .resume_wol = siena_init_wol,
1002 .test_chip = siena_test_chip,
1003 .test_nvram = efx_mcdi_nvram_test_all,
1004 .mcdi_request = siena_mcdi_request,
1005 .mcdi_poll_response = siena_mcdi_poll_response,
1006 .mcdi_read_response = siena_mcdi_read_response,
1007 .mcdi_poll_reboot = siena_mcdi_poll_reboot,
1008 .irq_enable_master = efx_farch_irq_enable_master,
1009 .irq_test_generate = efx_farch_irq_test_generate,
1010 .irq_disable_non_ev = efx_farch_irq_disable_master,
1011 .irq_handle_msi = efx_farch_msi_interrupt,
1012 .irq_handle_legacy = efx_farch_legacy_interrupt,
1013 .tx_probe = efx_farch_tx_probe,
1014 .tx_init = efx_farch_tx_init,
1015 .tx_remove = efx_farch_tx_remove,
1016 .tx_write = efx_farch_tx_write,
1017 .tx_limit_len = efx_farch_tx_limit_len,
1018 .rx_push_rss_config = siena_rx_push_rss_config,
1019 .rx_pull_rss_config = siena_rx_pull_rss_config,
1020 .rx_probe = efx_farch_rx_probe,
1021 .rx_init = efx_farch_rx_init,
1022 .rx_remove = efx_farch_rx_remove,
1023 .rx_write = efx_farch_rx_write,
1024 .rx_defer_refill = efx_farch_rx_defer_refill,
1025 .ev_probe = efx_farch_ev_probe,
1026 .ev_init = efx_farch_ev_init,
1027 .ev_fini = efx_farch_ev_fini,
1028 .ev_remove = efx_farch_ev_remove,
1029 .ev_process = efx_farch_ev_process,
1030 .ev_read_ack = efx_farch_ev_read_ack,
1031 .ev_test_generate = efx_farch_ev_test_generate,
1032 .filter_table_probe = efx_farch_filter_table_probe,
1033 .filter_table_restore = efx_farch_filter_table_restore,
1034 .filter_table_remove = efx_farch_filter_table_remove,
1035 .filter_update_rx_scatter = efx_farch_filter_update_rx_scatter,
1036 .filter_insert = efx_farch_filter_insert,
1037 .filter_remove_safe = efx_farch_filter_remove_safe,
1038 .filter_get_safe = efx_farch_filter_get_safe,
1039 .filter_clear_rx = efx_farch_filter_clear_rx,
1040 .filter_count_rx_used = efx_farch_filter_count_rx_used,
1041 .filter_get_rx_id_limit = efx_farch_filter_get_rx_id_limit,
1042 .filter_get_rx_ids = efx_farch_filter_get_rx_ids,
1043 #ifdef CONFIG_RFS_ACCEL
1044 .filter_rfs_expire_one = efx_farch_filter_rfs_expire_one,
1046 #ifdef CONFIG_SFC_MTD
1047 .mtd_probe = siena_mtd_probe,
1048 .mtd_rename = efx_mcdi_mtd_rename,
1049 .mtd_read = efx_mcdi_mtd_read,
1050 .mtd_erase = efx_mcdi_mtd_erase,
1051 .mtd_write = efx_mcdi_mtd_write,
1052 .mtd_sync = efx_mcdi_mtd_sync,
1054 .ptp_write_host_time = siena_ptp_write_host_time,
1055 .ptp_set_ts_config = siena_ptp_set_ts_config,
1056 #ifdef CONFIG_SFC_SRIOV
1057 .sriov_configure = efx_siena_sriov_configure,
1058 .sriov_init = efx_siena_sriov_init,
1059 .sriov_fini = efx_siena_sriov_fini,
1060 .sriov_wanted = efx_siena_sriov_wanted,
1061 .sriov_reset = efx_siena_sriov_reset,
1062 .sriov_flr = efx_siena_sriov_flr,
1063 .sriov_set_vf_mac = efx_siena_sriov_set_vf_mac,
1064 .sriov_set_vf_vlan = efx_siena_sriov_set_vf_vlan,
1065 .sriov_set_vf_spoofchk = efx_siena_sriov_set_vf_spoofchk,
1066 .sriov_get_vf_config = efx_siena_sriov_get_vf_config,
1067 .vswitching_probe = efx_port_dummy_op_int,
1068 .vswitching_restore = efx_port_dummy_op_int,
1069 .vswitching_remove = efx_port_dummy_op_void,
1070 .set_mac_address = efx_siena_sriov_mac_address_changed,
1073 .revision = EFX_REV_SIENA_A0,
1074 .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL,
1075 .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL,
1076 .buf_tbl_base = FR_BZ_BUF_FULL_TBL,
1077 .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL,
1078 .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR,
1079 .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
1080 .rx_prefix_size = FS_BZ_RX_PREFIX_SIZE,
1081 .rx_hash_offset = FS_BZ_RX_PREFIX_HASH_OFST,
1082 .rx_buffer_padding = 0,
1083 .can_rx_scatter = true,
1084 .option_descriptors = false,
1085 .min_interrupt_mode = EFX_INT_MODE_LEGACY,
1086 .max_interrupt_mode = EFX_INT_MODE_MSIX,
1087 .timer_period_max = 1 << FRF_CZ_TC_TIMER_VAL_WIDTH,
1088 .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
1089 NETIF_F_RXHASH | NETIF_F_NTUPLE),
1091 .max_rx_ip_filters = FR_BZ_RX_FILTER_TBL0_ROWS,
1092 .hwtstamp_filters = (1 << HWTSTAMP_FILTER_NONE |
1093 1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT |
1094 1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT),
1095 .rx_hash_key_size = 16,