1 // SPDX-License-Identifier: GPL-2.0-only
2 /****************************************************************************
3 * Driver for Solarflare network controllers and boards
4 * Copyright 2005-2006 Fen Systems Ltd.
5 * Copyright 2006-2013 Solarflare Communications Inc.
8 #include <linux/bitops.h>
9 #include <linux/delay.h>
10 #include <linux/interrupt.h>
11 #include <linux/pci.h>
12 #include <linux/module.h>
13 #include <linux/seq_file.h>
14 #include <linux/cpu_rmap.h>
15 #include "net_driver.h"
19 #include "ef10_regs.h"
20 #include "farch_regs.h"
22 #include "workarounds.h"
23 #include "mcdi_pcol.h"
25 /**************************************************************************
27 * Generic buffer handling
28 * These buffers are used for interrupt status, MAC stats, etc.
30 **************************************************************************/
32 int efx_nic_alloc_buffer(struct efx_nic *efx, struct efx_buffer *buffer,
33 unsigned int len, gfp_t gfp_flags)
35 buffer->addr = dma_alloc_coherent(&efx->pci_dev->dev, len,
36 &buffer->dma_addr, gfp_flags);
43 void efx_nic_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer)
46 dma_free_coherent(&efx->pci_dev->dev, buffer->len,
47 buffer->addr, buffer->dma_addr);
52 /* Check whether an event is present in the eventq at the current
53 * read pointer. Only useful for self-test.
55 bool efx_nic_event_present(struct efx_channel *channel)
57 return efx_event_present(efx_event(channel, channel->eventq_read_ptr));
60 void efx_nic_event_test_start(struct efx_channel *channel)
62 channel->event_test_cpu = -1;
64 channel->efx->type->ev_test_generate(channel);
67 int efx_nic_irq_test_start(struct efx_nic *efx)
69 efx->last_irq_cpu = -1;
71 return efx->type->irq_test_generate(efx);
74 /* Hook interrupt handler(s)
75 * Try MSI and then legacy interrupts.
77 int efx_nic_init_interrupt(struct efx_nic *efx)
79 struct efx_channel *channel;
83 if (!EFX_INT_MODE_USE_MSI(efx)) {
84 rc = request_irq(efx->legacy_irq,
85 efx->type->irq_handle_legacy, IRQF_SHARED,
88 netif_err(efx, drv, efx->net_dev,
89 "failed to hook legacy IRQ %d\n",
96 #ifdef CONFIG_RFS_ACCEL
97 if (efx->interrupt_mode == EFX_INT_MODE_MSIX) {
98 efx->net_dev->rx_cpu_rmap =
99 alloc_irq_cpu_rmap(efx->n_rx_channels);
100 if (!efx->net_dev->rx_cpu_rmap) {
107 /* Hook MSI or MSI-X interrupt */
109 efx_for_each_channel(channel, efx) {
110 rc = request_irq(channel->irq, efx->type->irq_handle_msi,
111 IRQF_PROBE_SHARED, /* Not shared */
112 efx->msi_context[channel->channel].name,
113 &efx->msi_context[channel->channel]);
115 netif_err(efx, drv, efx->net_dev,
116 "failed to hook IRQ %d\n", channel->irq);
121 #ifdef CONFIG_RFS_ACCEL
122 if (efx->interrupt_mode == EFX_INT_MODE_MSIX &&
123 channel->channel < efx->n_rx_channels) {
124 rc = irq_cpu_rmap_add(efx->net_dev->rx_cpu_rmap,
135 #ifdef CONFIG_RFS_ACCEL
136 free_irq_cpu_rmap(efx->net_dev->rx_cpu_rmap);
137 efx->net_dev->rx_cpu_rmap = NULL;
139 efx_for_each_channel(channel, efx) {
142 free_irq(channel->irq, &efx->msi_context[channel->channel]);
148 void efx_nic_fini_interrupt(struct efx_nic *efx)
150 struct efx_channel *channel;
152 #ifdef CONFIG_RFS_ACCEL
153 free_irq_cpu_rmap(efx->net_dev->rx_cpu_rmap);
154 efx->net_dev->rx_cpu_rmap = NULL;
157 if (EFX_INT_MODE_USE_MSI(efx)) {
158 /* Disable MSI/MSI-X interrupts */
159 efx_for_each_channel(channel, efx)
160 free_irq(channel->irq,
161 &efx->msi_context[channel->channel]);
163 /* Disable legacy interrupt */
164 free_irq(efx->legacy_irq, efx);
170 #define REGISTER_REVISION_FA 1
171 #define REGISTER_REVISION_FB 2
172 #define REGISTER_REVISION_FC 3
173 #define REGISTER_REVISION_FZ 3 /* last Falcon arch revision */
174 #define REGISTER_REVISION_ED 4
175 #define REGISTER_REVISION_EZ 4 /* latest EF10 revision */
179 u32 min_revision:3, max_revision:3;
182 #define REGISTER(name, arch, min_rev, max_rev) { \
183 arch ## R_ ## min_rev ## max_rev ## _ ## name, \
184 REGISTER_REVISION_ ## arch ## min_rev, \
185 REGISTER_REVISION_ ## arch ## max_rev \
187 #define REGISTER_AA(name) REGISTER(name, F, A, A)
188 #define REGISTER_AB(name) REGISTER(name, F, A, B)
189 #define REGISTER_AZ(name) REGISTER(name, F, A, Z)
190 #define REGISTER_BB(name) REGISTER(name, F, B, B)
191 #define REGISTER_BZ(name) REGISTER(name, F, B, Z)
192 #define REGISTER_CZ(name) REGISTER(name, F, C, Z)
193 #define REGISTER_DZ(name) REGISTER(name, E, D, Z)
195 static const struct efx_nic_reg efx_nic_regs[] = {
196 REGISTER_AZ(ADR_REGION),
197 REGISTER_AZ(INT_EN_KER),
198 REGISTER_BZ(INT_EN_CHAR),
199 REGISTER_AZ(INT_ADR_KER),
200 REGISTER_BZ(INT_ADR_CHAR),
201 /* INT_ACK_KER is WO */
203 REGISTER_AZ(HW_INIT),
204 REGISTER_CZ(USR_EV_CFG),
205 REGISTER_AB(EE_SPI_HCMD),
206 REGISTER_AB(EE_SPI_HADR),
207 REGISTER_AB(EE_SPI_HDATA),
208 REGISTER_AB(EE_BASE_PAGE),
209 REGISTER_AB(EE_VPD_CFG0),
210 /* EE_VPD_SW_CNTL and EE_VPD_SW_DATA are not used */
211 /* PMBX_DBG_IADDR and PBMX_DBG_IDATA are indirect */
212 /* PCIE_CORE_INDIRECT is indirect */
213 REGISTER_AB(NIC_STAT),
214 REGISTER_AB(GPIO_CTL),
215 REGISTER_AB(GLB_CTL),
216 /* FATAL_INTR_KER and FATAL_INTR_CHAR are partly RC */
217 REGISTER_BZ(DP_CTRL),
218 REGISTER_AZ(MEM_STAT),
219 REGISTER_AZ(CS_DEBUG),
220 REGISTER_AZ(ALTERA_BUILD),
221 REGISTER_AZ(CSR_SPARE),
222 REGISTER_AB(PCIE_SD_CTL0123),
223 REGISTER_AB(PCIE_SD_CTL45),
224 REGISTER_AB(PCIE_PCS_CTL_STAT),
225 /* DEBUG_DATA_OUT is not used */
227 REGISTER_AZ(EVQ_CTL),
228 REGISTER_AZ(EVQ_CNT1),
229 REGISTER_AZ(EVQ_CNT2),
230 REGISTER_AZ(BUF_TBL_CFG),
231 REGISTER_AZ(SRM_RX_DC_CFG),
232 REGISTER_AZ(SRM_TX_DC_CFG),
233 REGISTER_AZ(SRM_CFG),
234 /* BUF_TBL_UPD is WO */
235 REGISTER_AZ(SRM_UPD_EVQ),
236 REGISTER_AZ(SRAM_PARITY),
238 REGISTER_BZ(RX_FILTER_CTL),
239 /* RX_FLUSH_DESCQ is WO */
240 REGISTER_AZ(RX_DC_CFG),
241 REGISTER_AZ(RX_DC_PF_WM),
242 REGISTER_BZ(RX_RSS_TKEY),
243 /* RX_NODESC_DROP is RC */
244 REGISTER_AA(RX_SELF_RST),
245 /* RX_DEBUG, RX_PUSH_DROP are not used */
246 REGISTER_CZ(RX_RSS_IPV6_REG1),
247 REGISTER_CZ(RX_RSS_IPV6_REG2),
248 REGISTER_CZ(RX_RSS_IPV6_REG3),
249 /* TX_FLUSH_DESCQ is WO */
250 REGISTER_AZ(TX_DC_CFG),
251 REGISTER_AA(TX_CHKSM_CFG),
253 /* TX_PUSH_DROP is not used */
254 REGISTER_AZ(TX_RESERVED),
255 REGISTER_BZ(TX_PACE),
256 /* TX_PACE_DROP_QID is RC */
257 REGISTER_BB(TX_VLAN),
258 REGISTER_BZ(TX_IPFIL_PORTEN),
262 REGISTER_AB(MD_PHY_ADR),
265 REGISTER_AB(MAC_STAT_DMA),
266 REGISTER_AB(MAC_CTRL),
267 REGISTER_BB(GEN_MODE),
268 REGISTER_AB(MAC_MC_HASH_REG0),
269 REGISTER_AB(MAC_MC_HASH_REG1),
270 REGISTER_AB(GM_CFG1),
271 REGISTER_AB(GM_CFG2),
272 /* GM_IPG and GM_HD are not used */
273 REGISTER_AB(GM_MAX_FLEN),
274 /* GM_TEST is not used */
275 REGISTER_AB(GM_ADR1),
276 REGISTER_AB(GM_ADR2),
277 REGISTER_AB(GMF_CFG0),
278 REGISTER_AB(GMF_CFG1),
279 REGISTER_AB(GMF_CFG2),
280 REGISTER_AB(GMF_CFG3),
281 REGISTER_AB(GMF_CFG4),
282 REGISTER_AB(GMF_CFG5),
283 REGISTER_BB(TX_SRC_MAC_CTL),
284 REGISTER_AB(XM_ADR_LO),
285 REGISTER_AB(XM_ADR_HI),
286 REGISTER_AB(XM_GLB_CFG),
287 REGISTER_AB(XM_TX_CFG),
288 REGISTER_AB(XM_RX_CFG),
289 REGISTER_AB(XM_MGT_INT_MASK),
291 REGISTER_AB(XM_PAUSE_TIME),
292 REGISTER_AB(XM_TX_PARAM),
293 REGISTER_AB(XM_RX_PARAM),
294 /* XM_MGT_INT_MSK (note no 'A') is RC */
295 REGISTER_AB(XX_PWR_RST),
296 REGISTER_AB(XX_SD_CTL),
297 REGISTER_AB(XX_TXDRV_CTL),
298 /* XX_PRBS_CTL, XX_PRBS_CHK and XX_PRBS_ERR are not used */
299 /* XX_CORE_STAT is partly RC */
300 REGISTER_DZ(BIU_HW_REV_ID),
301 REGISTER_DZ(MC_DB_LWRD),
302 REGISTER_DZ(MC_DB_HWRD),
305 struct efx_nic_reg_table {
307 u32 min_revision:3, max_revision:3;
311 #define REGISTER_TABLE_DIMENSIONS(_, offset, arch, min_rev, max_rev, step, rows) { \
313 REGISTER_REVISION_ ## arch ## min_rev, \
314 REGISTER_REVISION_ ## arch ## max_rev, \
317 #define REGISTER_TABLE(name, arch, min_rev, max_rev) \
318 REGISTER_TABLE_DIMENSIONS( \
319 name, arch ## R_ ## min_rev ## max_rev ## _ ## name, \
320 arch, min_rev, max_rev, \
321 arch ## R_ ## min_rev ## max_rev ## _ ## name ## _STEP, \
322 arch ## R_ ## min_rev ## max_rev ## _ ## name ## _ROWS)
323 #define REGISTER_TABLE_AA(name) REGISTER_TABLE(name, F, A, A)
324 #define REGISTER_TABLE_AZ(name) REGISTER_TABLE(name, F, A, Z)
325 #define REGISTER_TABLE_BB(name) REGISTER_TABLE(name, F, B, B)
326 #define REGISTER_TABLE_BZ(name) REGISTER_TABLE(name, F, B, Z)
327 #define REGISTER_TABLE_BB_CZ(name) \
328 REGISTER_TABLE_DIMENSIONS(name, FR_BZ_ ## name, F, B, B, \
329 FR_BZ_ ## name ## _STEP, \
330 FR_BB_ ## name ## _ROWS), \
331 REGISTER_TABLE_DIMENSIONS(name, FR_BZ_ ## name, F, C, Z, \
332 FR_BZ_ ## name ## _STEP, \
333 FR_CZ_ ## name ## _ROWS)
334 #define REGISTER_TABLE_CZ(name) REGISTER_TABLE(name, F, C, Z)
335 #define REGISTER_TABLE_DZ(name) REGISTER_TABLE(name, E, D, Z)
337 static const struct efx_nic_reg_table efx_nic_reg_tables[] = {
338 /* DRIVER is not used */
339 /* EVQ_RPTR, TIMER_COMMAND, USR_EV and {RX,TX}_DESC_UPD are WO */
340 REGISTER_TABLE_BB(TX_IPFIL_TBL),
341 REGISTER_TABLE_BB(TX_SRC_MAC_TBL),
342 REGISTER_TABLE_AA(RX_DESC_PTR_TBL_KER),
343 REGISTER_TABLE_BB_CZ(RX_DESC_PTR_TBL),
344 REGISTER_TABLE_AA(TX_DESC_PTR_TBL_KER),
345 REGISTER_TABLE_BB_CZ(TX_DESC_PTR_TBL),
346 REGISTER_TABLE_AA(EVQ_PTR_TBL_KER),
347 REGISTER_TABLE_BB_CZ(EVQ_PTR_TBL),
348 /* We can't reasonably read all of the buffer table (up to 8MB!).
349 * However this driver will only use a few entries. Reading
350 * 1K entries allows for some expansion of queue count and
351 * size before we need to change the version. */
352 REGISTER_TABLE_DIMENSIONS(BUF_FULL_TBL_KER, FR_AA_BUF_FULL_TBL_KER,
354 REGISTER_TABLE_DIMENSIONS(BUF_FULL_TBL, FR_BZ_BUF_FULL_TBL,
356 REGISTER_TABLE_CZ(RX_MAC_FILTER_TBL0),
357 REGISTER_TABLE_BB_CZ(TIMER_TBL),
358 REGISTER_TABLE_BB_CZ(TX_PACE_TBL),
359 REGISTER_TABLE_BZ(RX_INDIRECTION_TBL),
360 /* TX_FILTER_TBL0 is huge and not used by this driver */
361 REGISTER_TABLE_CZ(TX_MAC_FILTER_TBL0),
362 REGISTER_TABLE_CZ(MC_TREG_SMEM),
363 /* MSIX_PBA_TABLE is not mapped */
364 /* SRM_DBG is not mapped (and is redundant with BUF_FLL_TBL) */
365 REGISTER_TABLE_BZ(RX_FILTER_TBL0),
366 REGISTER_TABLE_DZ(BIU_MC_SFT_STATUS),
369 size_t efx_nic_get_regs_len(struct efx_nic *efx)
371 const struct efx_nic_reg *reg;
372 const struct efx_nic_reg_table *table;
375 for (reg = efx_nic_regs;
376 reg < efx_nic_regs + ARRAY_SIZE(efx_nic_regs);
378 if (efx->type->revision >= reg->min_revision &&
379 efx->type->revision <= reg->max_revision)
380 len += sizeof(efx_oword_t);
382 for (table = efx_nic_reg_tables;
383 table < efx_nic_reg_tables + ARRAY_SIZE(efx_nic_reg_tables);
385 if (efx->type->revision >= table->min_revision &&
386 efx->type->revision <= table->max_revision)
387 len += table->rows * min_t(size_t, table->step, 16);
392 void efx_nic_get_regs(struct efx_nic *efx, void *buf)
394 const struct efx_nic_reg *reg;
395 const struct efx_nic_reg_table *table;
397 for (reg = efx_nic_regs;
398 reg < efx_nic_regs + ARRAY_SIZE(efx_nic_regs);
400 if (efx->type->revision >= reg->min_revision &&
401 efx->type->revision <= reg->max_revision) {
402 efx_reado(efx, (efx_oword_t *)buf, reg->offset);
403 buf += sizeof(efx_oword_t);
407 for (table = efx_nic_reg_tables;
408 table < efx_nic_reg_tables + ARRAY_SIZE(efx_nic_reg_tables);
412 if (!(efx->type->revision >= table->min_revision &&
413 efx->type->revision <= table->max_revision))
416 size = min_t(size_t, table->step, 16);
418 for (i = 0; i < table->rows; i++) {
419 switch (table->step) {
420 case 4: /* 32-bit SRAM */
421 efx_readd(efx, buf, table->offset + 4 * i);
423 case 8: /* 64-bit SRAM */
425 efx->membase + table->offset,
428 case 16: /* 128-bit-readable register */
429 efx_reado_table(efx, buf, table->offset, i);
431 case 32: /* 128-bit register, interleaved */
432 efx_reado_table(efx, buf, table->offset, 2 * i);
444 * efx_nic_describe_stats - Describe supported statistics for ethtool
445 * @desc: Array of &struct efx_hw_stat_desc describing the statistics
446 * @count: Length of the @desc array
447 * @mask: Bitmask of which elements of @desc are enabled
448 * @names: Buffer to copy names to, or %NULL. The names are copied
449 * starting at intervals of %ETH_GSTRING_LEN bytes.
451 * Returns the number of visible statistics, i.e. the number of set
452 * bits in the first @count bits of @mask for which a name is defined.
454 size_t efx_nic_describe_stats(const struct efx_hw_stat_desc *desc, size_t count,
455 const unsigned long *mask, u8 *names)
460 for_each_set_bit(index, mask, count) {
461 if (desc[index].name) {
463 strlcpy(names, desc[index].name,
465 names += ETH_GSTRING_LEN;
475 * efx_nic_copy_stats - Copy stats from the DMA buffer in to an
476 * intermediate buffer. This is used to get a consistent
477 * set of stats while the DMA buffer can be written at any time
479 * @efx: The associated NIC.
480 * @dest: Destination buffer. Must be the same size as the DMA buffer.
482 int efx_nic_copy_stats(struct efx_nic *efx, __le64 *dest)
484 __le64 *dma_stats = efx->stats_buffer.addr;
485 __le64 generation_start, generation_end;
494 /* If we're unlucky enough to read statistics during the DMA, wait
495 * up to 10ms for it to finish (typically takes <500us)
497 for (retry = 0; retry < 100; ++retry) {
498 generation_end = dma_stats[efx->num_mac_stats - 1];
499 if (generation_end == EFX_MC_STATS_GENERATION_INVALID)
502 memcpy(dest, dma_stats, efx->num_mac_stats * sizeof(__le64));
504 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
505 if (generation_end == generation_start)
506 return 0; /* return good data */
513 memset(dest, 0, efx->num_mac_stats * sizeof(u64));
518 * efx_nic_update_stats - Convert statistics DMA buffer to array of u64
519 * @desc: Array of &struct efx_hw_stat_desc describing the DMA buffer
520 * layout. DMA widths of 0, 16, 32 and 64 are supported; where
521 * the width is specified as 0 the corresponding element of
522 * @stats is not updated.
523 * @count: Length of the @desc array
524 * @mask: Bitmask of which elements of @desc are enabled
525 * @stats: Buffer to update with the converted statistics. The length
526 * of this array must be at least @count.
527 * @dma_buf: DMA buffer containing hardware statistics
528 * @accumulate: If set, the converted values will be added rather than
529 * directly stored to the corresponding elements of @stats
531 void efx_nic_update_stats(const struct efx_hw_stat_desc *desc, size_t count,
532 const unsigned long *mask,
533 u64 *stats, const void *dma_buf, bool accumulate)
537 for_each_set_bit(index, mask, count) {
538 if (desc[index].dma_width) {
539 const void *addr = dma_buf + desc[index].offset;
542 switch (desc[index].dma_width) {
544 val = le16_to_cpup((__le16 *)addr);
547 val = le32_to_cpup((__le32 *)addr);
550 val = le64_to_cpup((__le64 *)addr);
566 void efx_nic_fix_nodesc_drop_stat(struct efx_nic *efx, u64 *rx_nodesc_drops)
568 /* if down, or this is the first update after coming up */
569 if (!(efx->net_dev->flags & IFF_UP) || !efx->rx_nodesc_drops_prev_state)
570 efx->rx_nodesc_drops_while_down +=
571 *rx_nodesc_drops - efx->rx_nodesc_drops_total;
572 efx->rx_nodesc_drops_total = *rx_nodesc_drops;
573 efx->rx_nodesc_drops_prev_state = !!(efx->net_dev->flags & IFF_UP);
574 *rx_nodesc_drops -= efx->rx_nodesc_drops_while_down;