1 // SPDX-License-Identifier: GPL-2.0-only
2 /****************************************************************************
3 * Driver for Solarflare network controllers and boards
4 * Copyright 2019 Solarflare Communications Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
11 #include "net_driver.h"
14 #include "mcdi_functions.h"
16 #include "mcdi_pcol.h"
18 int efx_mcdi_free_vis(struct efx_nic *efx)
20 MCDI_DECLARE_BUF_ERR(outbuf);
22 int rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FREE_VIS, NULL, 0,
23 outbuf, sizeof(outbuf), &outlen);
25 /* -EALREADY means nothing to free, so ignore */
29 efx_mcdi_display_error(efx, MC_CMD_FREE_VIS, 0, outbuf, outlen,
34 int efx_mcdi_alloc_vis(struct efx_nic *efx, unsigned int min_vis,
35 unsigned int max_vis, unsigned int *vi_base,
36 unsigned int *allocated_vis)
38 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_VIS_OUT_LEN);
39 MCDI_DECLARE_BUF(inbuf, MC_CMD_ALLOC_VIS_IN_LEN);
43 MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MIN_VI_COUNT, min_vis);
44 MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MAX_VI_COUNT, max_vis);
45 rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_VIS, inbuf, sizeof(inbuf),
46 outbuf, sizeof(outbuf), &outlen);
50 if (outlen < MC_CMD_ALLOC_VIS_OUT_LEN)
53 netif_dbg(efx, drv, efx->net_dev, "base VI is A0x%03x\n",
54 MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE));
57 *vi_base = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE);
59 *allocated_vis = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_COUNT);
63 int efx_mcdi_ev_probe(struct efx_channel *channel)
65 return efx_nic_alloc_buffer(channel->efx, &channel->eventq.buf,
66 (channel->eventq_mask + 1) *
71 int efx_mcdi_ev_init(struct efx_channel *channel, bool v1_cut_thru, bool v2)
73 MCDI_DECLARE_BUF(inbuf,
74 MC_CMD_INIT_EVQ_V2_IN_LEN(EFX_MAX_EVQ_SIZE * 8 /
76 MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_EVQ_V2_OUT_LEN);
77 size_t entries = channel->eventq.buf.len / EFX_BUF_SIZE;
78 struct efx_nic *efx = channel->efx;
83 /* Fill event queue with all ones (i.e. empty events) */
84 memset(channel->eventq.buf.addr, 0xff, channel->eventq.buf.len);
86 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_SIZE, channel->eventq_mask + 1);
87 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_INSTANCE, channel->channel);
88 /* INIT_EVQ expects index in vector table, not absolute */
89 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_IRQ_NUM, channel->channel);
90 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_MODE,
91 MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS);
92 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_LOAD, 0);
93 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_RELOAD, 0);
94 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_MODE,
95 MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS);
96 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_THRSHLD, 0);
99 /* Use the new generic approach to specifying event queue
100 * configuration, requesting lower latency or higher throughput.
101 * The options that actually get used appear in the output.
103 MCDI_POPULATE_DWORD_2(inbuf, INIT_EVQ_V2_IN_FLAGS,
104 INIT_EVQ_V2_IN_FLAG_INTERRUPTING, 1,
105 INIT_EVQ_V2_IN_FLAG_TYPE,
106 MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_AUTO);
108 MCDI_POPULATE_DWORD_4(inbuf, INIT_EVQ_IN_FLAGS,
109 INIT_EVQ_IN_FLAG_INTERRUPTING, 1,
110 INIT_EVQ_IN_FLAG_RX_MERGE, 1,
111 INIT_EVQ_IN_FLAG_TX_MERGE, 1,
112 INIT_EVQ_IN_FLAG_CUT_THRU, v1_cut_thru);
115 dma_addr = channel->eventq.buf.dma_addr;
116 for (i = 0; i < entries; ++i) {
117 MCDI_SET_ARRAY_QWORD(inbuf, INIT_EVQ_IN_DMA_ADDR, i, dma_addr);
118 dma_addr += EFX_BUF_SIZE;
121 inlen = MC_CMD_INIT_EVQ_IN_LEN(entries);
123 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_EVQ, inbuf, inlen,
124 outbuf, sizeof(outbuf), &outlen);
126 if (outlen >= MC_CMD_INIT_EVQ_V2_OUT_LEN)
127 netif_dbg(efx, drv, efx->net_dev,
128 "Channel %d using event queue flags %08x\n",
130 MCDI_DWORD(outbuf, INIT_EVQ_V2_OUT_FLAGS));
135 void efx_mcdi_ev_remove(struct efx_channel *channel)
137 efx_nic_free_buffer(channel->efx, &channel->eventq.buf);
140 void efx_mcdi_ev_fini(struct efx_channel *channel)
142 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_EVQ_IN_LEN);
143 MCDI_DECLARE_BUF_ERR(outbuf);
144 struct efx_nic *efx = channel->efx;
148 MCDI_SET_DWORD(inbuf, FINI_EVQ_IN_INSTANCE, channel->channel);
150 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_EVQ, inbuf, sizeof(inbuf),
151 outbuf, sizeof(outbuf), &outlen);
153 if (rc && rc != -EALREADY)
159 efx_mcdi_display_error(efx, MC_CMD_FINI_EVQ, MC_CMD_FINI_EVQ_IN_LEN,
163 int efx_mcdi_tx_init(struct efx_tx_queue *tx_queue, bool tso_v2)
165 MCDI_DECLARE_BUF(inbuf, MC_CMD_INIT_TXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
167 bool csum_offload = tx_queue->label & EFX_TXQ_TYPE_OFFLOAD;
168 size_t entries = tx_queue->txd.buf.len / EFX_BUF_SIZE;
169 struct efx_channel *channel = tx_queue->channel;
170 struct efx_nic *efx = tx_queue->efx;
175 BUILD_BUG_ON(MC_CMD_INIT_TXQ_OUT_LEN != 0);
177 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_SIZE, tx_queue->ptr_mask + 1);
178 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_TARGET_EVQ, channel->channel);
179 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_LABEL, tx_queue->label);
180 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_INSTANCE, tx_queue->queue);
181 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_OWNER_ID, 0);
182 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_PORT_ID, efx->vport_id);
184 dma_addr = tx_queue->txd.buf.dma_addr;
186 netif_dbg(efx, hw, efx->net_dev, "pushing TXQ %d. %zu entries (%llx)\n",
187 tx_queue->queue, entries, (u64)dma_addr);
189 for (i = 0; i < entries; ++i) {
190 MCDI_SET_ARRAY_QWORD(inbuf, INIT_TXQ_IN_DMA_ADDR, i, dma_addr);
191 dma_addr += EFX_BUF_SIZE;
194 inlen = MC_CMD_INIT_TXQ_IN_LEN(entries);
197 MCDI_POPULATE_DWORD_4(inbuf, INIT_TXQ_IN_FLAGS,
198 /* This flag was removed from mcdi_pcol.h for
199 * the non-_EXT version of INIT_TXQ. However,
200 * firmware still honours it.
202 INIT_TXQ_EXT_IN_FLAG_TSOV2_EN, tso_v2,
203 INIT_TXQ_IN_FLAG_IP_CSUM_DIS, !csum_offload,
204 INIT_TXQ_IN_FLAG_TCP_CSUM_DIS, !csum_offload,
205 INIT_TXQ_EXT_IN_FLAG_TIMESTAMP,
206 tx_queue->timestamping);
208 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_INIT_TXQ, inbuf, inlen,
210 if (rc == -ENOSPC && tso_v2) {
211 /* Retry without TSOv2 if we're short on contexts. */
213 netif_warn(efx, probe, efx->net_dev,
214 "TSOv2 context not available to segment in "
215 "hardware. TCP performance may be reduced.\n"
218 efx_mcdi_display_error(efx, MC_CMD_INIT_TXQ,
219 MC_CMD_INIT_TXQ_EXT_IN_LEN,
231 void efx_mcdi_tx_remove(struct efx_tx_queue *tx_queue)
233 efx_nic_free_buffer(tx_queue->efx, &tx_queue->txd.buf);
236 void efx_mcdi_tx_fini(struct efx_tx_queue *tx_queue)
238 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_TXQ_IN_LEN);
239 MCDI_DECLARE_BUF_ERR(outbuf);
240 struct efx_nic *efx = tx_queue->efx;
244 MCDI_SET_DWORD(inbuf, FINI_TXQ_IN_INSTANCE,
247 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_TXQ, inbuf, sizeof(inbuf),
248 outbuf, sizeof(outbuf), &outlen);
250 if (rc && rc != -EALREADY)
256 efx_mcdi_display_error(efx, MC_CMD_FINI_TXQ, MC_CMD_FINI_TXQ_IN_LEN,
260 int efx_mcdi_rx_probe(struct efx_rx_queue *rx_queue)
262 return efx_nic_alloc_buffer(rx_queue->efx, &rx_queue->rxd.buf,
263 (rx_queue->ptr_mask + 1) *
268 void efx_mcdi_rx_init(struct efx_rx_queue *rx_queue)
270 struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
271 size_t entries = rx_queue->rxd.buf.len / EFX_BUF_SIZE;
272 MCDI_DECLARE_BUF(inbuf, MC_CMD_INIT_RXQ_V4_IN_LEN);
273 struct efx_nic *efx = rx_queue->efx;
274 unsigned int buffer_size;
278 BUILD_BUG_ON(MC_CMD_INIT_RXQ_OUT_LEN != 0);
280 rx_queue->scatter_n = 0;
281 rx_queue->scatter_len = 0;
282 if (efx->type->revision == EFX_REV_EF100)
283 buffer_size = efx->rx_page_buf_step;
287 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_SIZE, rx_queue->ptr_mask + 1);
288 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_TARGET_EVQ, channel->channel);
289 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_LABEL, efx_rx_queue_index(rx_queue));
290 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_INSTANCE,
291 efx_rx_queue_index(rx_queue));
292 MCDI_POPULATE_DWORD_2(inbuf, INIT_RXQ_IN_FLAGS,
293 INIT_RXQ_IN_FLAG_PREFIX, 1,
294 INIT_RXQ_IN_FLAG_TIMESTAMP, 1);
295 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_OWNER_ID, 0);
296 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_PORT_ID, efx->vport_id);
297 MCDI_SET_DWORD(inbuf, INIT_RXQ_V4_IN_BUFFER_SIZE_BYTES, buffer_size);
299 dma_addr = rx_queue->rxd.buf.dma_addr;
301 netif_dbg(efx, hw, efx->net_dev, "pushing RXQ %d. %zu entries (%llx)\n",
302 efx_rx_queue_index(rx_queue), entries, (u64)dma_addr);
304 for (i = 0; i < entries; ++i) {
305 MCDI_SET_ARRAY_QWORD(inbuf, INIT_RXQ_IN_DMA_ADDR, i, dma_addr);
306 dma_addr += EFX_BUF_SIZE;
309 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_RXQ, inbuf, sizeof(inbuf),
312 netdev_WARN(efx->net_dev, "failed to initialise RXQ %d\n",
313 efx_rx_queue_index(rx_queue));
316 void efx_mcdi_rx_remove(struct efx_rx_queue *rx_queue)
318 efx_nic_free_buffer(rx_queue->efx, &rx_queue->rxd.buf);
321 void efx_mcdi_rx_fini(struct efx_rx_queue *rx_queue)
323 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_RXQ_IN_LEN);
324 MCDI_DECLARE_BUF_ERR(outbuf);
325 struct efx_nic *efx = rx_queue->efx;
329 MCDI_SET_DWORD(inbuf, FINI_RXQ_IN_INSTANCE,
330 efx_rx_queue_index(rx_queue));
332 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_RXQ, inbuf, sizeof(inbuf),
333 outbuf, sizeof(outbuf), &outlen);
335 if (rc && rc != -EALREADY)
341 efx_mcdi_display_error(efx, MC_CMD_FINI_RXQ, MC_CMD_FINI_RXQ_IN_LEN,
345 int efx_fini_dmaq(struct efx_nic *efx)
347 struct efx_tx_queue *tx_queue;
348 struct efx_rx_queue *rx_queue;
349 struct efx_channel *channel;
352 /* If the MC has just rebooted, the TX/RX queues will have already been
353 * torn down, but efx->active_queues needs to be set to zero.
355 if (efx->must_realloc_vis) {
356 atomic_set(&efx->active_queues, 0);
360 /* Do not attempt to write to the NIC during EEH recovery */
361 if (efx->state != STATE_RECOVERY) {
362 efx_for_each_channel(channel, efx) {
363 efx_for_each_channel_rx_queue(rx_queue, channel)
364 efx_mcdi_rx_fini(rx_queue);
365 efx_for_each_channel_tx_queue(tx_queue, channel)
366 efx_mcdi_tx_fini(tx_queue);
369 wait_event_timeout(efx->flush_wq,
370 atomic_read(&efx->active_queues) == 0,
371 msecs_to_jiffies(EFX_MAX_FLUSH_TIME));
372 pending = atomic_read(&efx->active_queues);
374 netif_err(efx, hw, efx->net_dev, "failed to flush %d queues\n",
383 int efx_mcdi_window_mode_to_stride(struct efx_nic *efx, u8 vi_window_mode)
385 switch (vi_window_mode) {
386 case MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_8K:
387 efx->vi_stride = 8192;
389 case MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_16K:
390 efx->vi_stride = 16384;
392 case MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_64K:
393 efx->vi_stride = 65536;
396 netif_err(efx, probe, efx->net_dev,
397 "Unrecognised VI window mode %d\n",
401 netif_dbg(efx, probe, efx->net_dev, "vi_stride = %u\n",
406 int efx_get_pf_index(struct efx_nic *efx, unsigned int *pf_index)
408 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN);
412 rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf,
413 sizeof(outbuf), &outlen);
416 if (outlen < sizeof(outbuf))
419 *pf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_PF);