drivers/net/ethernet/sfc/farch.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /****************************************************************************
   3  * Driver for Solarflare network controllers and boards
   4  * Copyright 2005-2006 Fen Systems Ltd.
   5  * Copyright 2006-2013 Solarflare Communications Inc.
   6  */
   7
   8 #include <linux/bitops.h>
   9 #include <linux/delay.h>
  10 #include <linux/interrupt.h>
  11 #include <linux/pci.h>
  12 #include <linux/module.h>
  13 #include <linux/seq_file.h>
  14 #include <linux/crc32.h>
  15 #include "net_driver.h"
  16 #include "bitfield.h"
  17 #include "efx.h"
  18 #include "rx_common.h"
  19 #include "nic.h"
  20 #include "farch_regs.h"
  21 #include "sriov.h"
  22 #include "siena_sriov.h"
  23 #include "io.h"
  24 #include "workarounds.h"
  25
  26 /* Falcon-architecture (SFC9000-family) support */
  27
  28 /**************************************************************************
  29  *
  30  * Configurable values
  31  *
  32  **************************************************************************
  33  */
  34
  35 /* This is set to 16 for a good reason.  In summary, if larger than
  36  * 16, the descriptor cache holds more than a default socket
  37  * buffer's worth of packets (for UDP we can only have at most one
  38  * socket buffer's worth outstanding).  This combined with the fact
  39  * that we only get 1 TX event per descriptor cache means the NIC
  40  * goes idle.
  41  */
  42 #define TX_DC_ENTRIES 16
  43 #define TX_DC_ENTRIES_ORDER 1
  44
  45 #define RX_DC_ENTRIES 64
  46 #define RX_DC_ENTRIES_ORDER 3
  47
  48 /* If EFX_MAX_INT_ERRORS internal errors occur within
  49  * EFX_INT_ERROR_EXPIRE seconds, we consider the NIC broken and
  50  * disable it.
  51  */
  52 #define EFX_INT_ERROR_EXPIRE 3600
  53 #define EFX_MAX_INT_ERRORS 5
  54
  55 /* Depth of RX flush request fifo */
  56 #define EFX_RX_FLUSH_COUNT 4
  57
  58 /* Driver generated events */
  59 #define _EFX_CHANNEL_MAGIC_TEST         0x000101
  60 #define _EFX_CHANNEL_MAGIC_FILL         0x000102
  61 #define _EFX_CHANNEL_MAGIC_RX_DRAIN     0x000103
  62 #define _EFX_CHANNEL_MAGIC_TX_DRAIN     0x000104
  63
  64 #define _EFX_CHANNEL_MAGIC(_code, _data)        ((_code) << 8 | (_data))
  65 #define _EFX_CHANNEL_MAGIC_CODE(_magic)         ((_magic) >> 8)
  66
  67 #define EFX_CHANNEL_MAGIC_TEST(_channel)                                \
  68         _EFX_CHANNEL_MAGIC(_EFX_CHANNEL_MAGIC_TEST, (_channel)->channel)
  69 #define EFX_CHANNEL_MAGIC_FILL(_rx_queue)                               \
  70         _EFX_CHANNEL_MAGIC(_EFX_CHANNEL_MAGIC_FILL,                     \
  71                            efx_rx_queue_index(_rx_queue))
  72 #define EFX_CHANNEL_MAGIC_RX_DRAIN(_rx_queue)                           \
  73         _EFX_CHANNEL_MAGIC(_EFX_CHANNEL_MAGIC_RX_DRAIN,                 \
  74                            efx_rx_queue_index(_rx_queue))
  75 #define EFX_CHANNEL_MAGIC_TX_DRAIN(_tx_queue)                           \
  76         _EFX_CHANNEL_MAGIC(_EFX_CHANNEL_MAGIC_TX_DRAIN,                 \
  77                            (_tx_queue)->queue)
  78
  79 static void efx_farch_magic_event(struct efx_channel *channel, u32 magic);
  80
  81 /**************************************************************************
  82  *
  83  * Hardware access
  84  *
  85  **************************************************************************/
  86
  87 static inline void efx_write_buf_tbl(struct efx_nic *efx, efx_qword_t *value,
  88                                      unsigned int index)
  89 {
  90         efx_sram_writeq(efx, efx->membase + efx->type->buf_tbl_base,
  91                         value, index);
  92 }
  93
  94 static bool efx_masked_compare_oword(const efx_oword_t *a, const efx_oword_t *b,
  95                                      const efx_oword_t *mask)
  96 {
  97         return ((a->u64[0] ^ b->u64[0]) & mask->u64[0]) ||
  98                 ((a->u64[1] ^ b->u64[1]) & mask->u64[1]);
  99 }
 100
 101 int efx_farch_test_registers(struct efx_nic *efx,
 102                              const struct efx_farch_register_test *regs,
 103                              size_t n_regs)
 104 {
 105         unsigned address = 0;
 106         int i, j;
 107         efx_oword_t mask, imask, original, reg, buf;
 108
 109         for (i = 0; i < n_regs; ++i) {
 110                 address = regs[i].address;
 111                 mask = imask = regs[i].mask;
 112                 EFX_INVERT_OWORD(imask);
 113
 114                 efx_reado(efx, &original, address);
 115
 116                 /* bit sweep on and off */
 117                 for (j = 0; j < 128; j++) {
 118                         if (!EFX_EXTRACT_OWORD32(mask, j, j))
 119                                 continue;
 120
 121                         /* Test this testable bit can be set in isolation */
 122                         EFX_AND_OWORD(reg, original, mask);
 123                         EFX_SET_OWORD32(reg, j, j, 1);
 124
 125                         efx_writeo(efx, &reg, address);
 126                         efx_reado(efx, &buf, address);
 127
 128                         if (efx_masked_compare_oword(&reg, &buf, &mask))
 129                                 goto fail;
 130
 131                         /* Test this testable bit can be cleared in isolation */
 132                         EFX_OR_OWORD(reg, original, mask);
 133                         EFX_SET_OWORD32(reg, j, j, 0);
 134
 135                         efx_writeo(efx, &reg, address);
 136                         efx_reado(efx, &buf, address);
 137
 138                         if (efx_masked_compare_oword(&reg, &buf, &mask))
 139                                 goto fail;
 140                 }
 141
 142                 efx_writeo(efx, &original, address);
 143         }
 144
 145         return 0;
 146
 147 fail:
 148         netif_err(efx, hw, efx->net_dev,
 149                   "wrote "EFX_OWORD_FMT" read "EFX_OWORD_FMT
 150                   " at address 0x%x mask "EFX_OWORD_FMT"\n", EFX_OWORD_VAL(reg),
 151                   EFX_OWORD_VAL(buf), address, EFX_OWORD_VAL(mask));
 152         return -EIO;
 153 }
 154
 155 /**************************************************************************
 156  *
 157  * Special buffer handling
 158  * Special buffers are used for event queues and the TX and RX
 159  * descriptor rings.
 160  *
 161  *************************************************************************/
 162
 163 /*
 164  * Initialise a special buffer
 165  *
 166  * This will define a buffer (previously allocated via
 167  * efx_alloc_special_buffer()) in the buffer table, allowing
 168  * it to be used for event queues, descriptor rings etc.
 169  */
 170 static void
 171 efx_init_special_buffer(struct efx_nic *efx, struct efx_special_buffer *buffer)
 172 {
 173         efx_qword_t buf_desc;
 174         unsigned int index;
 175         dma_addr_t dma_addr;
 176         int i;
 177
 178         EFX_WARN_ON_PARANOID(!buffer->buf.addr);
 179
 180         /* Write buffer descriptors to NIC */
 181         for (i = 0; i < buffer->entries; i++) {
 182                 index = buffer->index + i;
 183                 dma_addr = buffer->buf.dma_addr + (i * EFX_BUF_SIZE);
 184                 netif_dbg(efx, probe, efx->net_dev,
 185                           "mapping special buffer %d at %llx\n",
 186                           index, (unsigned long long)dma_addr);
 187                 EFX_POPULATE_QWORD_3(buf_desc,
 188                                      FRF_AZ_BUF_ADR_REGION, 0,
 189                                      FRF_AZ_BUF_ADR_FBUF, dma_addr >> 12,
 190                                      FRF_AZ_BUF_OWNER_ID_FBUF, 0);
 191                 efx_write_buf_tbl(efx, &buf_desc, index);
 192         }
 193 }
 194
 195 /* Unmaps a buffer and clears the buffer table entries */
 196 static void
 197 efx_fini_special_buffer(struct efx_nic *efx, struct efx_special_buffer *buffer)
 198 {
 199         efx_oword_t buf_tbl_upd;
 200         unsigned int start = buffer->index;
 201         unsigned int end = (buffer->index + buffer->entries - 1);
 202
 203         if (!buffer->entries)
 204                 return;
 205
 206         netif_dbg(efx, hw, efx->net_dev, "unmapping special buffers %d-%d\n",
 207                   buffer->index, buffer->index + buffer->entries - 1);
 208
 209         EFX_POPULATE_OWORD_4(buf_tbl_upd,
 210                              FRF_AZ_BUF_UPD_CMD, 0,
 211                              FRF_AZ_BUF_CLR_CMD, 1,
 212                              FRF_AZ_BUF_CLR_END_ID, end,
 213                              FRF_AZ_BUF_CLR_START_ID, start);
 214         efx_writeo(efx, &buf_tbl_upd, FR_AZ_BUF_TBL_UPD);
 215 }
 216
 217 /*
 218  * Allocate a new special buffer
 219  *
 220  * This allocates memory for a new buffer, clears it and allocates a
 221  * new buffer ID range.  It does not write into the buffer table.
 222  *
 223  * This call will allocate 4KB buffers, since 8KB buffers can't be
 224  * used for event queues and descriptor rings.
 225  */
 226 static int efx_alloc_special_buffer(struct efx_nic *efx,
 227                                     struct efx_special_buffer *buffer,
 228                                     unsigned int len)
 229 {
 230 #ifdef CONFIG_SFC_SRIOV
 231         struct siena_nic_data *nic_data = efx->nic_data;
 232 #endif
 233         len = ALIGN(len, EFX_BUF_SIZE);
 234
 235         if (efx_nic_alloc_buffer(efx, &buffer->buf, len, GFP_KERNEL))
 236                 return -ENOMEM;
 237         buffer->entries = len / EFX_BUF_SIZE;
 238         BUG_ON(buffer->buf.dma_addr & (EFX_BUF_SIZE - 1));
 239
 240         /* Select new buffer ID */
 241         buffer->index = efx->next_buffer_table;
 242         efx->next_buffer_table += buffer->entries;
 243 #ifdef CONFIG_SFC_SRIOV
 244         BUG_ON(efx_siena_sriov_enabled(efx) &&
 245                nic_data->vf_buftbl_base < efx->next_buffer_table);
 246 #endif
 247
 248         netif_dbg(efx, probe, efx->net_dev,
 249                   "allocating special buffers %d-%d at %llx+%x "
 250                   "(virt %p phys %llx)\n", buffer->index,
 251                   buffer->index + buffer->entries - 1,
 252                   (u64)buffer->buf.dma_addr, len,
 253                   buffer->buf.addr, (u64)virt_to_phys(buffer->buf.addr));
 254
 255         return 0;
 256 }
 257
 258 static void
 259 efx_free_special_buffer(struct efx_nic *efx, struct efx_special_buffer *buffer)
 260 {
 261         if (!buffer->buf.addr)
 262                 return;
 263
 264         netif_dbg(efx, hw, efx->net_dev,
 265                   "deallocating special buffers %d-%d at %llx+%x "
 266                   "(virt %p phys %llx)\n", buffer->index,
 267                   buffer->index + buffer->entries - 1,
 268                   (u64)buffer->buf.dma_addr, buffer->buf.len,
 269                   buffer->buf.addr, (u64)virt_to_phys(buffer->buf.addr));
 270
 271         efx_nic_free_buffer(efx, &buffer->buf);
 272         buffer->entries = 0;
 273 }
 274
 275 /**************************************************************************
 276  *
 277  * TX path
 278  *
 279  **************************************************************************/
 280
 281 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
 282 static inline void efx_farch_notify_tx_desc(struct efx_tx_queue *tx_queue)
 283 {
 284         unsigned write_ptr;
 285         efx_dword_t reg;
 286
 287         write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
 288         EFX_POPULATE_DWORD_1(reg, FRF_AZ_TX_DESC_WPTR_DWORD, write_ptr);
 289         efx_writed_page(tx_queue->efx, &reg,
 290                         FR_AZ_TX_DESC_UPD_DWORD_P0, tx_queue->queue);
 291 }
 292
 293 /* Write pointer and first descriptor for TX descriptor ring */
 294 static inline void efx_farch_push_tx_desc(struct efx_tx_queue *tx_queue,
 295                                           const efx_qword_t *txd)
 296 {
 297         unsigned write_ptr;
 298         efx_oword_t reg;
 299
 300         BUILD_BUG_ON(FRF_AZ_TX_DESC_LBN != 0);
 301         BUILD_BUG_ON(FR_AA_TX_DESC_UPD_KER != FR_BZ_TX_DESC_UPD_P0);
 302
 303         write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
 304         EFX_POPULATE_OWORD_2(reg, FRF_AZ_TX_DESC_PUSH_CMD, true,
 305                              FRF_AZ_TX_DESC_WPTR, write_ptr);
 306         reg.qword[0] = *txd;
 307         efx_writeo_page(tx_queue->efx, &reg,
 308                         FR_BZ_TX_DESC_UPD_P0, tx_queue->queue);
 309 }
 310
 311
 312 /* For each entry inserted into the software descriptor ring, create a
 313  * descriptor in the hardware TX descriptor ring (in host memory), and
 314  * write a doorbell.
 315  */
 316 void efx_farch_tx_write(struct efx_tx_queue *tx_queue)
 317 {
 318         struct efx_tx_buffer *buffer;
 319         efx_qword_t *txd;
 320         unsigned write_ptr;
 321         unsigned old_write_count = tx_queue->write_count;
 322
 323         tx_queue->xmit_pending = false;
 324         if (unlikely(tx_queue->write_count == tx_queue->insert_count))
 325                 return;
 326
 327         do {
 328                 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
 329                 buffer = &tx_queue->buffer[write_ptr];
 330                 txd = efx_tx_desc(tx_queue, write_ptr);
 331                 ++tx_queue->write_count;
 332
 333                 EFX_WARN_ON_ONCE_PARANOID(buffer->flags & EFX_TX_BUF_OPTION);
 334
 335                 /* Create TX descriptor ring entry */
 336                 BUILD_BUG_ON(EFX_TX_BUF_CONT != 1);
 337                 EFX_POPULATE_QWORD_4(*txd,
 338                                      FSF_AZ_TX_KER_CONT,
 339                                      buffer->flags & EFX_TX_BUF_CONT,
 340                                      FSF_AZ_TX_KER_BYTE_COUNT, buffer->len,
 341                                      FSF_AZ_TX_KER_BUF_REGION, 0,
 342                                      FSF_AZ_TX_KER_BUF_ADDR, buffer->dma_addr);
 343         } while (tx_queue->write_count != tx_queue->insert_count);
 344
 345         wmb(); /* Ensure descriptors are written before they are fetched */
 346
 347         if (efx_nic_may_push_tx_desc(tx_queue, old_write_count)) {
 348                 txd = efx_tx_desc(tx_queue,
 349                                   old_write_count & tx_queue->ptr_mask);
 350                 efx_farch_push_tx_desc(tx_queue, txd);
 351                 ++tx_queue->pushes;
 352         } else {
 353                 efx_farch_notify_tx_desc(tx_queue);
 354         }
 355 }
 356
 357 unsigned int efx_farch_tx_limit_len(struct efx_tx_queue *tx_queue,
 358                                     dma_addr_t dma_addr, unsigned int len)
 359 {
 360         /* Don't cross 4K boundaries with descriptors. */
 361         unsigned int limit = (~dma_addr & (EFX_PAGE_SIZE - 1)) + 1;
 362
 363         len = min(limit, len);
 364
 365         return len;
 366 }
 367
 368
 369 /* Allocate hardware resources for a TX queue */
 370 int efx_farch_tx_probe(struct efx_tx_queue *tx_queue)
 371 {
 372         struct efx_nic *efx = tx_queue->efx;
 373         unsigned entries;
 374
 375         entries = tx_queue->ptr_mask + 1;
 376         return efx_alloc_special_buffer(efx, &tx_queue->txd,
 377                                         entries * sizeof(efx_qword_t));
 378 }
 379
 380 void efx_farch_tx_init(struct efx_tx_queue *tx_queue)
 381 {
 382         int csum = tx_queue->label & EFX_TXQ_TYPE_OFFLOAD;
 383         struct efx_nic *efx = tx_queue->efx;
 384         efx_oword_t reg;
 385
 386         /* Pin TX descriptor ring */
 387         efx_init_special_buffer(efx, &tx_queue->txd);
 388
 389         /* Push TX descriptor ring to card */
 390         EFX_POPULATE_OWORD_10(reg,
 391                               FRF_AZ_TX_DESCQ_EN, 1,
 392                               FRF_AZ_TX_ISCSI_DDIG_EN, 0,
 393                               FRF_AZ_TX_ISCSI_HDIG_EN, 0,
 394                               FRF_AZ_TX_DESCQ_BUF_BASE_ID, tx_queue->txd.index,
 395                               FRF_AZ_TX_DESCQ_EVQ_ID,
 396                               tx_queue->channel->channel,
 397                               FRF_AZ_TX_DESCQ_OWNER_ID, 0,
 398                               FRF_AZ_TX_DESCQ_LABEL, tx_queue->label,
 399                               FRF_AZ_TX_DESCQ_SIZE,
 400                               __ffs(tx_queue->txd.entries),
 401                               FRF_AZ_TX_DESCQ_TYPE, 0,
 402                               FRF_BZ_TX_NON_IP_DROP_DIS, 1);
 403
 404         EFX_SET_OWORD_FIELD(reg, FRF_BZ_TX_IP_CHKSM_DIS, !csum);
 405         EFX_SET_OWORD_FIELD(reg, FRF_BZ_TX_TCP_CHKSM_DIS, !csum);
 406
 407         efx_writeo_table(efx, &reg, efx->type->txd_ptr_tbl_base,
 408                          tx_queue->queue);
 409
 410         EFX_POPULATE_OWORD_1(reg,
 411                              FRF_BZ_TX_PACE,
 412                              (tx_queue->label & EFX_TXQ_TYPE_HIGHPRI) ?
 413                              FFE_BZ_TX_PACE_OFF :
 414                              FFE_BZ_TX_PACE_RESERVED);
 415         efx_writeo_table(efx, &reg, FR_BZ_TX_PACE_TBL, tx_queue->queue);
 416 }
 417
 418 static void efx_farch_flush_tx_queue(struct efx_tx_queue *tx_queue)
 419 {
 420         struct efx_nic *efx = tx_queue->efx;
 421         efx_oword_t tx_flush_descq;
 422
 423         WARN_ON(atomic_read(&tx_queue->flush_outstanding));
 424         atomic_set(&tx_queue->flush_outstanding, 1);
 425
 426         EFX_POPULATE_OWORD_2(tx_flush_descq,
 427                              FRF_AZ_TX_FLUSH_DESCQ_CMD, 1,
 428                              FRF_AZ_TX_FLUSH_DESCQ, tx_queue->queue);
 429         efx_writeo(efx, &tx_flush_descq, FR_AZ_TX_FLUSH_DESCQ);
 430 }
 431
 432 void efx_farch_tx_fini(struct efx_tx_queue *tx_queue)
 433 {
 434         struct efx_nic *efx = tx_queue->efx;
 435         efx_oword_t tx_desc_ptr;
 436
 437         /* Remove TX descriptor ring from card */
 438         EFX_ZERO_OWORD(tx_desc_ptr);
 439         efx_writeo_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
 440                          tx_queue->queue);
 441
 442         /* Unpin TX descriptor ring */
 443         efx_fini_special_buffer(efx, &tx_queue->txd);
 444 }
 445
 446 /* Free buffers backing TX queue */
 447 void efx_farch_tx_remove(struct efx_tx_queue *tx_queue)
 448 {
 449         efx_free_special_buffer(tx_queue->efx, &tx_queue->txd);
 450 }
 451
 452 /**************************************************************************
 453  *
 454  * RX path
 455  *
 456  **************************************************************************/
 457
 458 /* This creates an entry in the RX descriptor queue */
 459 static inline void
 460 efx_farch_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned index)
 461 {
 462         struct efx_rx_buffer *rx_buf;
 463         efx_qword_t *rxd;
 464
 465         rxd = efx_rx_desc(rx_queue, index);
 466         rx_buf = efx_rx_buffer(rx_queue, index);
 467         EFX_POPULATE_QWORD_3(*rxd,
 468                              FSF_AZ_RX_KER_BUF_SIZE,
 469                              rx_buf->len -
 470                              rx_queue->efx->type->rx_buffer_padding,
 471                              FSF_AZ_RX_KER_BUF_REGION, 0,
 472                              FSF_AZ_RX_KER_BUF_ADDR, rx_buf->dma_addr);
 473 }
 474
 475 /* This writes to the RX_DESC_WPTR register for the specified receive
 476  * descriptor ring.
 477  */
 478 void efx_farch_rx_write(struct efx_rx_queue *rx_queue)
 479 {
 480         struct efx_nic *efx = rx_queue->efx;
 481         efx_dword_t reg;
 482         unsigned write_ptr;
 483
 484         while (rx_queue->notified_count != rx_queue->added_count) {
 485                 efx_farch_build_rx_desc(
 486                         rx_queue,
 487                         rx_queue->notified_count & rx_queue->ptr_mask);
 488                 ++rx_queue->notified_count;
 489         }
 490
 491         wmb();
 492         write_ptr = rx_queue->added_count & rx_queue->ptr_mask;
 493         EFX_POPULATE_DWORD_1(reg, FRF_AZ_RX_DESC_WPTR_DWORD, write_ptr);
 494         efx_writed_page(efx, &reg, FR_AZ_RX_DESC_UPD_DWORD_P0,
 495                         efx_rx_queue_index(rx_queue));
 496 }
 497
 498 int efx_farch_rx_probe(struct efx_rx_queue *rx_queue)
 499 {
 500         struct efx_nic *efx = rx_queue->efx;
 501         unsigned entries;
 502
 503         entries = rx_queue->ptr_mask + 1;
 504         return efx_alloc_special_buffer(efx, &rx_queue->rxd,
 505                                         entries * sizeof(efx_qword_t));
 506 }
 507
 508 void efx_farch_rx_init(struct efx_rx_queue *rx_queue)
 509 {
 510         efx_oword_t rx_desc_ptr;
 511         struct efx_nic *efx = rx_queue->efx;
 512         bool jumbo_en;
 513
 514         /* For kernel-mode queues in Siena, the JUMBO flag enables scatter. */
 515         jumbo_en = efx->rx_scatter;
 516
 517         netif_dbg(efx, hw, efx->net_dev,
 518                   "RX queue %d ring in special buffers %d-%d\n",
 519                   efx_rx_queue_index(rx_queue), rx_queue->rxd.index,
 520                   rx_queue->rxd.index + rx_queue->rxd.entries - 1);
 521
 522         rx_queue->scatter_n = 0;
 523
 524         /* Pin RX descriptor ring */
 525         efx_init_special_buffer(efx, &rx_queue->rxd);
 526
 527         /* Push RX descriptor ring to card */
 528         EFX_POPULATE_OWORD_10(rx_desc_ptr,
 529                               FRF_AZ_RX_ISCSI_DDIG_EN, true,
 530                               FRF_AZ_RX_ISCSI_HDIG_EN, true,
 531                               FRF_AZ_RX_DESCQ_BUF_BASE_ID, rx_queue->rxd.index,
 532                               FRF_AZ_RX_DESCQ_EVQ_ID,
 533                               efx_rx_queue_channel(rx_queue)->channel,
 534                               FRF_AZ_RX_DESCQ_OWNER_ID, 0,
 535                               FRF_AZ_RX_DESCQ_LABEL,
 536                               efx_rx_queue_index(rx_queue),
 537                               FRF_AZ_RX_DESCQ_SIZE,
 538                               __ffs(rx_queue->rxd.entries),
 539                               FRF_AZ_RX_DESCQ_TYPE, 0 /* kernel queue */ ,
 540                               FRF_AZ_RX_DESCQ_JUMBO, jumbo_en,
 541                               FRF_AZ_RX_DESCQ_EN, 1);
 542         efx_writeo_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
 543                          efx_rx_queue_index(rx_queue));
 544 }
 545
 546 static void efx_farch_flush_rx_queue(struct efx_rx_queue *rx_queue)
 547 {
 548         struct efx_nic *efx = rx_queue->efx;
 549         efx_oword_t rx_flush_descq;
 550
 551         EFX_POPULATE_OWORD_2(rx_flush_descq,
 552                              FRF_AZ_RX_FLUSH_DESCQ_CMD, 1,
 553                              FRF_AZ_RX_FLUSH_DESCQ,
 554                              efx_rx_queue_index(rx_queue));
 555         efx_writeo(efx, &rx_flush_descq, FR_AZ_RX_FLUSH_DESCQ);
 556 }
 557
 558 void efx_farch_rx_fini(struct efx_rx_queue *rx_queue)
 559 {
 560         efx_oword_t rx_desc_ptr;
 561         struct efx_nic *efx = rx_queue->efx;
 562
 563         /* Remove RX descriptor ring from card */
 564         EFX_ZERO_OWORD(rx_desc_ptr);
 565         efx_writeo_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
 566                          efx_rx_queue_index(rx_queue));
 567
 568         /* Unpin RX descriptor ring */
 569         efx_fini_special_buffer(efx, &rx_queue->rxd);
 570 }
 571
 572 /* Free buffers backing RX queue */
 573 void efx_farch_rx_remove(struct efx_rx_queue *rx_queue)
 574 {
 575         efx_free_special_buffer(rx_queue->efx, &rx_queue->rxd);
 576 }
 577
 578 /**************************************************************************
 579  *
 580  * Flush handling
 581  *
 582  **************************************************************************/
 583
 584 /* efx_farch_flush_queues() must be woken up when all flushes are completed,
 585  * or more RX flushes can be kicked off.
 586  */
 587 static bool efx_farch_flush_wake(struct efx_nic *efx)
 588 {
 589         /* Ensure that all updates are visible to efx_farch_flush_queues() */
 590         smp_mb();
 591
 592         return (atomic_read(&efx->active_queues) == 0 ||
 593                 (atomic_read(&efx->rxq_flush_outstanding) < EFX_RX_FLUSH_COUNT
 594                  && atomic_read(&efx->rxq_flush_pending) > 0));
 595 }
 596
 597 static bool efx_check_tx_flush_complete(struct efx_nic *efx)
 598 {
 599         bool i = true;
 600         efx_oword_t txd_ptr_tbl;
 601         struct efx_channel *channel;
 602         struct efx_tx_queue *tx_queue;
 603
 604         efx_for_each_channel(channel, efx) {
 605                 efx_for_each_channel_tx_queue(tx_queue, channel) {
 606                         efx_reado_table(efx, &txd_ptr_tbl,
 607                                         FR_BZ_TX_DESC_PTR_TBL, tx_queue->queue);
 608                         if (EFX_OWORD_FIELD(txd_ptr_tbl,
 609                                             FRF_AZ_TX_DESCQ_FLUSH) ||
 610                             EFX_OWORD_FIELD(txd_ptr_tbl,
 611                                             FRF_AZ_TX_DESCQ_EN)) {
 612                                 netif_dbg(efx, hw, efx->net_dev,
 613                                           "flush did not complete on TXQ %d\n",
 614                                           tx_queue->queue);
 615                                 i = false;
 616                         } else if (atomic_cmpxchg(&tx_queue->flush_outstanding,
 617                                                   1, 0)) {
 618                                 /* The flush is complete, but we didn't
 619                                  * receive a flush completion event
 620                                  */
 621                                 netif_dbg(efx, hw, efx->net_dev,
 622                                           "flush complete on TXQ %d, so drain "
 623                                           "the queue\n", tx_queue->queue);
 624                                 /* Don't need to increment active_queues as it
 625                                  * has already been incremented for the queues
 626                                  * which did not drain
 627                                  */
 628                                 efx_farch_magic_event(channel,
 629                                                       EFX_CHANNEL_MAGIC_TX_DRAIN(
 630                                                               tx_queue));
 631                         }
 632                 }
 633         }
 634
 635         return i;
 636 }
 637
 638 /* Flush all the transmit queues, and continue flushing receive queues until
 639  * they're all flushed. Wait for the DRAIN events to be received so that there
 640  * are no more RX and TX events left on any channel. */
 641 static int efx_farch_do_flush(struct efx_nic *efx)
 642 {
 643         unsigned timeout = msecs_to_jiffies(5000); /* 5s for all flushes and drains */
 644         struct efx_channel *channel;
 645         struct efx_rx_queue *rx_queue;
 646         struct efx_tx_queue *tx_queue;
 647         int rc = 0;
 648
 649         efx_for_each_channel(channel, efx) {
 650                 efx_for_each_channel_tx_queue(tx_queue, channel) {
 651                         efx_farch_flush_tx_queue(tx_queue);
 652                 }
 653                 efx_for_each_channel_rx_queue(rx_queue, channel) {
 654                         rx_queue->flush_pending = true;
 655                         atomic_inc(&efx->rxq_flush_pending);
 656                 }
 657         }
 658
 659         while (timeout && atomic_read(&efx->active_queues) > 0) {
 660                 /* If SRIOV is enabled, then offload receive queue flushing to
 661                  * the firmware (though we will still have to poll for
 662                  * completion). If that fails, fall back to the old scheme.
 663                  */
 664                 if (efx_siena_sriov_enabled(efx)) {
 665                         rc = efx_mcdi_flush_rxqs(efx);
 666                         if (!rc)
 667                                 goto wait;
 668                 }
 669
 670                 /* The hardware supports four concurrent rx flushes, each of
 671                  * which may need to be retried if there is an outstanding
 672                  * descriptor fetch
 673                  */
 674                 efx_for_each_channel(channel, efx) {
 675                         efx_for_each_channel_rx_queue(rx_queue, channel) {
 676                                 if (atomic_read(&efx->rxq_flush_outstanding) >=
 677                                     EFX_RX_FLUSH_COUNT)
 678                                         break;
 679
 680                                 if (rx_queue->flush_pending) {
 681                                         rx_queue->flush_pending = false;
 682                                         atomic_dec(&efx->rxq_flush_pending);
 683                                         atomic_inc(&efx->rxq_flush_outstanding);
 684                                         efx_farch_flush_rx_queue(rx_queue);
 685                                 }
 686                         }
 687                 }
 688
 689         wait:
 690                 timeout = wait_event_timeout(efx->flush_wq,
 691                                              efx_farch_flush_wake(efx),
 692                                              timeout);
 693         }
 694
 695         if (atomic_read(&efx->active_queues) &&
 696             !efx_check_tx_flush_complete(efx)) {
 697                 netif_err(efx, hw, efx->net_dev, "failed to flush %d queues "
 698                           "(rx %d+%d)\n", atomic_read(&efx->active_queues),
 699                           atomic_read(&efx->rxq_flush_outstanding),
 700                           atomic_read(&efx->rxq_flush_pending));
 701                 rc = -ETIMEDOUT;
 702
 703                 atomic_set(&efx->active_queues, 0);
 704                 atomic_set(&efx->rxq_flush_pending, 0);
 705                 atomic_set(&efx->rxq_flush_outstanding, 0);
 706         }
 707
 708         return rc;
 709 }
 710
 711 int efx_farch_fini_dmaq(struct efx_nic *efx)
 712 {
 713         struct efx_channel *channel;
 714         struct efx_tx_queue *tx_queue;
 715         struct efx_rx_queue *rx_queue;
 716         int rc = 0;
 717
 718         /* Do not attempt to write to the NIC during EEH recovery */
 719         if (efx->state != STATE_RECOVERY) {
 720                 /* Only perform flush if DMA is enabled */
 721                 if (efx->pci_dev->is_busmaster) {
 722                         efx->type->prepare_flush(efx);
 723                         rc = efx_farch_do_flush(efx);
 724                         efx->type->finish_flush(efx);
 725                 }
 726
 727                 efx_for_each_channel(channel, efx) {
 728                         efx_for_each_channel_rx_queue(rx_queue, channel)
 729                                 efx_farch_rx_fini(rx_queue);
 730                         efx_for_each_channel_tx_queue(tx_queue, channel)
 731                                 efx_farch_tx_fini(tx_queue);
 732                 }
 733         }
 734
 735         return rc;
 736 }
 737
 738 /* Reset queue and flush accounting after FLR
 739  *
 740  * One possible cause of FLR recovery is that DMA may be failing (eg. if bus
 741  * mastering was disabled), in which case we don't receive (RXQ) flush
 742  * completion events.  This means that efx->rxq_flush_outstanding remained at 4
 743  * after the FLR; also, efx->active_queues was non-zero (as no flush completion
 744  * events were received, and we didn't go through efx_check_tx_flush_complete())
 745  * If we don't fix this up, on the next call to efx_realloc_channels() we won't
 746  * flush any RX queues because efx->rxq_flush_outstanding is at the limit of 4
 747  * for batched flush requests; and the efx->active_queues gets messed up because
 748  * we keep incrementing for the newly initialised queues, but it never went to
 749  * zero previously.  Then we get a timeout every time we try to restart the
 750  * queues, as it doesn't go back to zero when we should be flushing the queues.
 751  */
 752 void efx_farch_finish_flr(struct efx_nic *efx)
 753 {
 754         atomic_set(&efx->rxq_flush_pending, 0);
 755         atomic_set(&efx->rxq_flush_outstanding, 0);
 756         atomic_set(&efx->active_queues, 0);
 757 }
 758
 759
 760 /**************************************************************************
 761  *
 762  * Event queue processing
 763  * Event queues are processed by per-channel tasklets.
 764  *
 765  **************************************************************************/
 766
 767 /* Update a channel's event queue's read pointer (RPTR) register
 768  *
 769  * This writes the EVQ_RPTR_REG register for the specified channel's
 770  * event queue.
 771  */
 772 void efx_farch_ev_read_ack(struct efx_channel *channel)
 773 {
 774         efx_dword_t reg;
 775         struct efx_nic *efx = channel->efx;
 776
 777         EFX_POPULATE_DWORD_1(reg, FRF_AZ_EVQ_RPTR,
 778                              channel->eventq_read_ptr & channel->eventq_mask);
 779
 780         /* For Falcon A1, EVQ_RPTR_KER is documented as having a step size
 781          * of 4 bytes, but it is really 16 bytes just like later revisions.
 782          */
 783         efx_writed(efx, &reg,
 784                    efx->type->evq_rptr_tbl_base +
 785                    FR_BZ_EVQ_RPTR_STEP * channel->channel);
 786 }
 787
 788 /* Use HW to insert a SW defined event */
 789 void efx_farch_generate_event(struct efx_nic *efx, unsigned int evq,
 790                               efx_qword_t *event)
 791 {
 792         efx_oword_t drv_ev_reg;
 793
 794         BUILD_BUG_ON(FRF_AZ_DRV_EV_DATA_LBN != 0 ||
 795                      FRF_AZ_DRV_EV_DATA_WIDTH != 64);
 796         drv_ev_reg.u32[0] = event->u32[0];
 797         drv_ev_reg.u32[1] = event->u32[1];
 798         drv_ev_reg.u32[2] = 0;
 799         drv_ev_reg.u32[3] = 0;
 800         EFX_SET_OWORD_FIELD(drv_ev_reg, FRF_AZ_DRV_EV_QID, evq);
 801         efx_writeo(efx, &drv_ev_reg, FR_AZ_DRV_EV);
 802 }
 803
 804 static void efx_farch_magic_event(struct efx_channel *channel, u32 magic)
 805 {
 806         efx_qword_t event;
 807
 808         EFX_POPULATE_QWORD_2(event, FSF_AZ_EV_CODE,
 809                              FSE_AZ_EV_CODE_DRV_GEN_EV,
 810                              FSF_AZ_DRV_GEN_EV_MAGIC, magic);
 811         efx_farch_generate_event(channel->efx, channel->channel, &event);
 812 }
 813
 814 /* Handle a transmit completion event
 815  *
 816  * The NIC batches TX completion events; the message we receive is of
 817  * the form "complete all TX events up to this index".
 818  */
 819 static void
 820 efx_farch_handle_tx_event(struct efx_channel *channel, efx_qword_t *event)
 821 {
 822         unsigned int tx_ev_desc_ptr;
 823         unsigned int tx_ev_q_label;
 824         struct efx_tx_queue *tx_queue;
 825         struct efx_nic *efx = channel->efx;
 826
 827         if (unlikely(READ_ONCE(efx->reset_pending)))
 828                 return;
 829
 830         if (likely(EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_COMP))) {
 831                 /* Transmit completion */
 832                 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_DESC_PTR);
 833                 tx_ev_q_label = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_Q_LABEL);
 834                 tx_queue = efx_channel_get_tx_queue(
 835                         channel, tx_ev_q_label % EFX_TXQ_TYPES);
 836                 efx_xmit_done(tx_queue, tx_ev_desc_ptr);
 837         } else if (EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_WQ_FF_FULL)) {
 838                 /* Rewrite the FIFO write pointer */
 839                 tx_ev_q_label = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_Q_LABEL);
 840                 tx_queue = efx_channel_get_tx_queue(
 841                         channel, tx_ev_q_label % EFX_TXQ_TYPES);
 842
 843                 netif_tx_lock(efx->net_dev);
 844                 efx_farch_notify_tx_desc(tx_queue);
 845                 netif_tx_unlock(efx->net_dev);
 846         } else if (EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_PKT_ERR)) {
 847                 efx_schedule_reset(efx, RESET_TYPE_DMA_ERROR);
 848         } else {
 849                 netif_err(efx, tx_err, efx->net_dev,
 850                           "channel %d unexpected TX event "
 851                           EFX_QWORD_FMT"\n", channel->channel,
 852                           EFX_QWORD_VAL(*event));
 853         }
 854 }
 855
 856 /* Detect errors included in the rx_evt_pkt_ok bit. */
 857 static u16 efx_farch_handle_rx_not_ok(struct efx_rx_queue *rx_queue,
 858                                       const efx_qword_t *event)
 859 {
 860         struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
 861         struct efx_nic *efx = rx_queue->efx;
 862         bool rx_ev_buf_owner_id_err, rx_ev_ip_hdr_chksum_err;
 863         bool rx_ev_tcp_udp_chksum_err, rx_ev_eth_crc_err;
 864         bool rx_ev_frm_trunc, rx_ev_tobe_disc;
 865         bool rx_ev_other_err, rx_ev_pause_frm;
 866
 867         rx_ev_tobe_disc = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_TOBE_DISC);
 868         rx_ev_buf_owner_id_err = EFX_QWORD_FIELD(*event,
 869                                                  FSF_AZ_RX_EV_BUF_OWNER_ID_ERR);
 870         rx_ev_ip_hdr_chksum_err = EFX_QWORD_FIELD(*event,
 871                                                   FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR);
 872         rx_ev_tcp_udp_chksum_err = EFX_QWORD_FIELD(*event,
 873                                                    FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR);
 874         rx_ev_eth_crc_err = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_ETH_CRC_ERR);
 875         rx_ev_frm_trunc = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_FRM_TRUNC);
 876         rx_ev_pause_frm = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PAUSE_FRM_ERR);
 877
 878         /* Every error apart from tobe_disc and pause_frm */
 879         rx_ev_other_err = (rx_ev_tcp_udp_chksum_err |
 880                            rx_ev_buf_owner_id_err | rx_ev_eth_crc_err |
 881                            rx_ev_frm_trunc | rx_ev_ip_hdr_chksum_err);
 882
 883         /* Count errors that are not in MAC stats.  Ignore expected
 884          * checksum errors during self-test. */
 885         if (rx_ev_frm_trunc)
 886                 ++channel->n_rx_frm_trunc;
 887         else if (rx_ev_tobe_disc)
 888                 ++channel->n_rx_tobe_disc;
 889         else if (!efx->loopback_selftest) {
 890                 if (rx_ev_ip_hdr_chksum_err)
 891                         ++channel->n_rx_ip_hdr_chksum_err;
 892                 else if (rx_ev_tcp_udp_chksum_err)
 893                         ++channel->n_rx_tcp_udp_chksum_err;
 894         }
 895
 896         /* TOBE_DISC is expected on unicast mismatches; don't print out an
 897          * error message.  FRM_TRUNC indicates RXDP dropped the packet due
 898          * to a FIFO overflow.
 899          */
 900 #ifdef DEBUG
 901         if (rx_ev_other_err && net_ratelimit()) {
 902                 netif_dbg(efx, rx_err, efx->net_dev,
 903                           " RX queue %d unexpected RX event "
 904                           EFX_QWORD_FMT "%s%s%s%s%s%s%s\n",
 905                           efx_rx_queue_index(rx_queue), EFX_QWORD_VAL(*event),
 906                           rx_ev_buf_owner_id_err ? " [OWNER_ID_ERR]" : "",
 907                           rx_ev_ip_hdr_chksum_err ?
 908                           " [IP_HDR_CHKSUM_ERR]" : "",
 909                           rx_ev_tcp_udp_chksum_err ?
 910                           " [TCP_UDP_CHKSUM_ERR]" : "",
 911                           rx_ev_eth_crc_err ? " [ETH_CRC_ERR]" : "",
 912                           rx_ev_frm_trunc ? " [FRM_TRUNC]" : "",
 913                           rx_ev_tobe_disc ? " [TOBE_DISC]" : "",
 914                           rx_ev_pause_frm ? " [PAUSE]" : "");
 915         }
 916 #else
 917         (void) rx_ev_other_err;
 918 #endif
 919
 920         if (efx->net_dev->features & NETIF_F_RXALL)
 921                 /* don't discard frame for CRC error */
 922                 rx_ev_eth_crc_err = false;
 923
 924         /* The frame must be discarded if any of these are true. */
 925         return (rx_ev_eth_crc_err | rx_ev_frm_trunc |
 926                 rx_ev_tobe_disc | rx_ev_pause_frm) ?
 927                 EFX_RX_PKT_DISCARD : 0;
 928 }
 929
 930 /* Handle receive events that are not in-order. Return true if this
 931  * can be handled as a partial packet discard, false if it's more
 932  * serious.
 933  */
 934 static bool
 935 efx_farch_handle_rx_bad_index(struct efx_rx_queue *rx_queue, unsigned index)
 936 {
 937         struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
 938         struct efx_nic *efx = rx_queue->efx;
 939         unsigned expected, dropped;
 940
 941         if (rx_queue->scatter_n &&
 942             index == ((rx_queue->removed_count + rx_queue->scatter_n - 1) &
 943                       rx_queue->ptr_mask)) {
 944                 ++channel->n_rx_nodesc_trunc;
 945                 return true;
 946         }
 947
 948         expected = rx_queue->removed_count & rx_queue->ptr_mask;
 949         dropped = (index - expected) & rx_queue->ptr_mask;
 950         netif_info(efx, rx_err, efx->net_dev,
 951                    "dropped %d events (index=%d expected=%d)\n",
 952                    dropped, index, expected);
 953
 954         efx_schedule_reset(efx, RESET_TYPE_DISABLE);
 955         return false;
 956 }
 957
 958 /* Handle a packet received event
 959  *
 960  * The NIC gives a "discard" flag if it's a unicast packet with the
 961  * wrong destination address
 962  * Also "is multicast" and "matches multicast filter" flags can be used to
 963  * discard non-matching multicast packets.
 964  */
 965 static void
 966 efx_farch_handle_rx_event(struct efx_channel *channel, const efx_qword_t *event)
 967 {
 968         unsigned int rx_ev_desc_ptr, rx_ev_byte_cnt;
 969         unsigned int rx_ev_hdr_type, rx_ev_mcast_pkt;
 970         unsigned expected_ptr;
 971         bool rx_ev_pkt_ok, rx_ev_sop, rx_ev_cont;
 972         u16 flags;
 973         struct efx_rx_queue *rx_queue;
 974         struct efx_nic *efx = channel->efx;
 975
 976         if (unlikely(READ_ONCE(efx->reset_pending)))
 977                 return;
 978
 979         rx_ev_cont = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_JUMBO_CONT);
 980         rx_ev_sop = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_SOP);
 981         WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_Q_LABEL) !=
 982                 channel->channel);
 983
 984         rx_queue = efx_channel_get_rx_queue(channel);
 985
 986         rx_ev_desc_ptr = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_DESC_PTR);
 987         expected_ptr = ((rx_queue->removed_count + rx_queue->scatter_n) &
 988                         rx_queue->ptr_mask);
 989
 990         /* Check for partial drops and other errors */
 991         if (unlikely(rx_ev_desc_ptr != expected_ptr) ||
 992             unlikely(rx_ev_sop != (rx_queue->scatter_n == 0))) {
 993                 if (rx_ev_desc_ptr != expected_ptr &&
 994                     !efx_farch_handle_rx_bad_index(rx_queue, rx_ev_desc_ptr))
 995                         return;
 996
 997                 /* Discard all pending fragments */
 998                 if (rx_queue->scatter_n) {
 999                         efx_rx_packet(
1000                                 rx_queue,
1001                                 rx_queue->removed_count & rx_queue->ptr_mask,
1002                                 rx_queue->scatter_n, 0, EFX_RX_PKT_DISCARD);
1003                         rx_queue->removed_count += rx_queue->scatter_n;
1004                         rx_queue->scatter_n = 0;
1005                 }
1006
1007                 /* Return if there is no new fragment */
1008                 if (rx_ev_desc_ptr != expected_ptr)
1009                         return;
1010
1011                 /* Discard new fragment if not SOP */
1012                 if (!rx_ev_sop) {
1013                         efx_rx_packet(
1014                                 rx_queue,
1015                                 rx_queue->removed_count & rx_queue->ptr_mask,
1016                                 1, 0, EFX_RX_PKT_DISCARD);
1017                         ++rx_queue->removed_count;
1018                         return;
1019                 }
1020         }
1021
1022         ++rx_queue->scatter_n;
1023         if (rx_ev_cont)
1024                 return;
1025
1026         rx_ev_byte_cnt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_BYTE_CNT);
1027         rx_ev_pkt_ok = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PKT_OK);
1028         rx_ev_hdr_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_HDR_TYPE);
1029
1030         if (likely(rx_ev_pkt_ok)) {
1031                 /* If packet is marked as OK then we can rely on the
1032                  * hardware checksum and classification.
1033                  */
1034                 flags = 0;
1035                 switch (rx_ev_hdr_type) {
1036                 case FSE_CZ_RX_EV_HDR_TYPE_IPV4V6_TCP:
1037                         flags |= EFX_RX_PKT_TCP;
1038                         fallthrough;
1039                 case FSE_CZ_RX_EV_HDR_TYPE_IPV4V6_UDP:
1040                         flags |= EFX_RX_PKT_CSUMMED;
1041                         fallthrough;
1042                 case FSE_CZ_RX_EV_HDR_TYPE_IPV4V6_OTHER:
1043                 case FSE_AZ_RX_EV_HDR_TYPE_OTHER:
1044                         break;
1045                 }
1046         } else {
1047                 flags = efx_farch_handle_rx_not_ok(rx_queue, event);
1048         }
1049
1050         /* Detect multicast packets that didn't match the filter */
1051         rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_PKT);
1052         if (rx_ev_mcast_pkt) {
1053                 unsigned int rx_ev_mcast_hash_match =
1054                         EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_HASH_MATCH);
1055
1056                 if (unlikely(!rx_ev_mcast_hash_match)) {
1057                         ++channel->n_rx_mcast_mismatch;
1058                         flags |= EFX_RX_PKT_DISCARD;
1059                 }
1060         }
1061
1062         channel->irq_mod_score += 2;
1063
1064         /* Handle received packet */
1065         efx_rx_packet(rx_queue,
1066                       rx_queue->removed_count & rx_queue->ptr_mask,
1067                       rx_queue->scatter_n, rx_ev_byte_cnt, flags);
1068         rx_queue->removed_count += rx_queue->scatter_n;
1069         rx_queue->scatter_n = 0;
1070 }
1071
1072 /* If this flush done event corresponds to a &struct efx_tx_queue, then
1073  * send an %EFX_CHANNEL_MAGIC_TX_DRAIN event to drain the event queue
1074  * of all transmit completions.
1075  */
1076 static void
1077 efx_farch_handle_tx_flush_done(struct efx_nic *efx, efx_qword_t *event)
1078 {
1079         struct efx_tx_queue *tx_queue;
1080         int qid;
1081
1082         qid = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBDATA);
1083         if (qid < EFX_TXQ_TYPES * (efx->n_tx_channels + efx->n_extra_tx_channels)) {
1084                 tx_queue = efx_get_tx_queue(efx, qid / EFX_TXQ_TYPES,
1085                                             qid % EFX_TXQ_TYPES);
1086                 if (atomic_cmpxchg(&tx_queue->flush_outstanding, 1, 0)) {
1087                         efx_farch_magic_event(tx_queue->channel,
1088                                               EFX_CHANNEL_MAGIC_TX_DRAIN(tx_queue));
1089                 }
1090         }
1091 }
1092
1093 /* If this flush done event corresponds to a &struct efx_rx_queue: If the flush
1094  * was successful then send an %EFX_CHANNEL_MAGIC_RX_DRAIN, otherwise add
1095  * the RX queue back to the mask of RX queues in need of flushing.
1096  */
1097 static void
1098 efx_farch_handle_rx_flush_done(struct efx_nic *efx, efx_qword_t *event)
1099 {
1100         struct efx_channel *channel;
1101         struct efx_rx_queue *rx_queue;
1102         int qid;
1103         bool failed;
1104
1105         qid = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_RX_DESCQ_ID);
1106         failed = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL);
1107         if (qid >= efx->n_channels)
1108                 return;
1109         channel = efx_get_channel(efx, qid);
1110         if (!efx_channel_has_rx_queue(channel))
1111                 return;
1112         rx_queue = efx_channel_get_rx_queue(channel);
1113
1114         if (failed) {
1115                 netif_info(efx, hw, efx->net_dev,
1116                            "RXQ %d flush retry\n", qid);
1117                 rx_queue->flush_pending = true;
1118                 atomic_inc(&efx->rxq_flush_pending);
1119         } else {
1120                 efx_farch_magic_event(efx_rx_queue_channel(rx_queue),
1121                                       EFX_CHANNEL_MAGIC_RX_DRAIN(rx_queue));
1122         }
1123         atomic_dec(&efx->rxq_flush_outstanding);
1124         if (efx_farch_flush_wake(efx))
1125                 wake_up(&efx->flush_wq);
1126 }
1127
1128 static void
1129 efx_farch_handle_drain_event(struct efx_channel *channel)
1130 {
1131         struct efx_nic *efx = channel->efx;
1132
1133         WARN_ON(atomic_read(&efx->active_queues) == 0);
1134         atomic_dec(&efx->active_queues);
1135         if (efx_farch_flush_wake(efx))
1136                 wake_up(&efx->flush_wq);
1137 }
1138
1139 static void efx_farch_handle_generated_event(struct efx_channel *channel,
1140                                              efx_qword_t *event)
1141 {
1142         struct efx_nic *efx = channel->efx;
1143         struct efx_rx_queue *rx_queue =
1144                 efx_channel_has_rx_queue(channel) ?
1145                 efx_channel_get_rx_queue(channel) : NULL;
1146         unsigned magic, code;
1147
1148         magic = EFX_QWORD_FIELD(*event, FSF_AZ_DRV_GEN_EV_MAGIC);
1149         code = _EFX_CHANNEL_MAGIC_CODE(magic);
1150
1151         if (magic == EFX_CHANNEL_MAGIC_TEST(channel)) {
1152                 channel->event_test_cpu = raw_smp_processor_id();
1153         } else if (rx_queue && magic == EFX_CHANNEL_MAGIC_FILL(rx_queue)) {
1154                 /* The queue must be empty, so we won't receive any rx
1155                  * events, so efx_process_channel() won't refill the
1156                  * queue. Refill it here */
1157                 efx_fast_push_rx_descriptors(rx_queue, true);
1158         } else if (rx_queue && magic == EFX_CHANNEL_MAGIC_RX_DRAIN(rx_queue)) {
1159                 efx_farch_handle_drain_event(channel);
1160         } else if (code == _EFX_CHANNEL_MAGIC_TX_DRAIN) {
1161                 efx_farch_handle_drain_event(channel);
1162         } else {
1163                 netif_dbg(efx, hw, efx->net_dev, "channel %d received "
1164                           "generated event "EFX_QWORD_FMT"\n",
1165                           channel->channel, EFX_QWORD_VAL(*event));
1166         }
1167 }
1168
1169 static void
1170 efx_farch_handle_driver_event(struct efx_channel *channel, efx_qword_t *event)
1171 {
1172         struct efx_nic *efx = channel->efx;
1173         unsigned int ev_sub_code;
1174         unsigned int ev_sub_data;
1175
1176         ev_sub_code = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBCODE);
1177         ev_sub_data = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBDATA);
1178
1179         switch (ev_sub_code) {
1180         case FSE_AZ_TX_DESCQ_FLS_DONE_EV:
1181                 netif_vdbg(efx, hw, efx->net_dev, "channel %d TXQ %d flushed\n",
1182                            channel->channel, ev_sub_data);
1183                 efx_farch_handle_tx_flush_done(efx, event);
1184 #ifdef CONFIG_SFC_SRIOV
1185                 efx_siena_sriov_tx_flush_done(efx, event);
1186 #endif
1187                 break;
1188         case FSE_AZ_RX_DESCQ_FLS_DONE_EV:
1189                 netif_vdbg(efx, hw, efx->net_dev, "channel %d RXQ %d flushed\n",
1190                            channel->channel, ev_sub_data);
1191                 efx_farch_handle_rx_flush_done(efx, event);
1192 #ifdef CONFIG_SFC_SRIOV
1193                 efx_siena_sriov_rx_flush_done(efx, event);
1194 #endif
1195                 break;
1196         case FSE_AZ_EVQ_INIT_DONE_EV:
1197                 netif_dbg(efx, hw, efx->net_dev,
1198                           "channel %d EVQ %d initialised\n",
1199                           channel->channel, ev_sub_data);
1200                 break;
1201         case FSE_AZ_SRM_UPD_DONE_EV:
1202                 netif_vdbg(efx, hw, efx->net_dev,
1203                            "channel %d SRAM update done\n", channel->channel);
1204                 break;
1205         case FSE_AZ_WAKE_UP_EV:
1206                 netif_vdbg(efx, hw, efx->net_dev,
1207                            "channel %d RXQ %d wakeup event\n",
1208                            channel->channel, ev_sub_data);
1209                 break;
1210         case FSE_AZ_TIMER_EV:
1211                 netif_vdbg(efx, hw, efx->net_dev,
1212                            "channel %d RX queue %d timer expired\n",
1213                            channel->channel, ev_sub_data);
1214                 break;
1215         case FSE_AA_RX_RECOVER_EV:
1216                 netif_err(efx, rx_err, efx->net_dev,
1217                           "channel %d seen DRIVER RX_RESET event. "
1218                         "Resetting.\n", channel->channel);
1219                 atomic_inc(&efx->rx_reset);
1220                 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
1221                 break;
1222         case FSE_BZ_RX_DSC_ERROR_EV:
1223                 if (ev_sub_data < EFX_VI_BASE) {
1224                         netif_err(efx, rx_err, efx->net_dev,
1225                                   "RX DMA Q %d reports descriptor fetch error."
1226                                   " RX Q %d is disabled.\n", ev_sub_data,
1227                                   ev_sub_data);
1228                         efx_schedule_reset(efx, RESET_TYPE_DMA_ERROR);
1229                 }
1230 #ifdef CONFIG_SFC_SRIOV
1231                 else
1232                         efx_siena_sriov_desc_fetch_err(efx, ev_sub_data);
1233 #endif
1234                 break;
1235         case FSE_BZ_TX_DSC_ERROR_EV:
1236                 if (ev_sub_data < EFX_VI_BASE) {
1237                         netif_err(efx, tx_err, efx->net_dev,
1238                                   "TX DMA Q %d reports descriptor fetch error."
1239                                   " TX Q %d is disabled.\n", ev_sub_data,
1240                                   ev_sub_data);
1241                         efx_schedule_reset(efx, RESET_TYPE_DMA_ERROR);
1242                 }
1243 #ifdef CONFIG_SFC_SRIOV
1244                 else
1245                         efx_siena_sriov_desc_fetch_err(efx, ev_sub_data);
1246 #endif
1247                 break;
1248         default:
1249                 netif_vdbg(efx, hw, efx->net_dev,
1250                            "channel %d unknown driver event code %d "
1251                            "data %04x\n", channel->channel, ev_sub_code,
1252                            ev_sub_data);
1253                 break;
1254         }
1255 }
1256
1257 int efx_farch_ev_process(struct efx_channel *channel, int budget)
1258 {
1259         struct efx_nic *efx = channel->efx;
1260         unsigned int read_ptr;
1261         efx_qword_t event, *p_event;
1262         int ev_code;
1263         int spent = 0;
1264
1265         if (budget <= 0)
1266                 return spent;
1267
1268         read_ptr = channel->eventq_read_ptr;
1269
1270         for (;;) {
1271                 p_event = efx_event(channel, read_ptr);
1272                 event = *p_event;
1273
1274                 if (!efx_event_present(&event))
1275                         /* End of events */
1276                         break;
1277
1278                 netif_vdbg(channel->efx, intr, channel->efx->net_dev,
1279                            "channel %d event is "EFX_QWORD_FMT"\n",
1280                            channel->channel, EFX_QWORD_VAL(event));
1281
1282                 /* Clear this event by marking it all ones */
1283                 EFX_SET_QWORD(*p_event);
1284
1285                 ++read_ptr;
1286
1287                 ev_code = EFX_QWORD_FIELD(event, FSF_AZ_EV_CODE);
1288
1289                 switch (ev_code) {
1290                 case FSE_AZ_EV_CODE_RX_EV:
1291                         efx_farch_handle_rx_event(channel, &event);
1292                         if (++spent == budget)
1293                                 goto out;
1294                         break;
1295                 case FSE_AZ_EV_CODE_TX_EV:
1296                         efx_farch_handle_tx_event(channel, &event);
1297                         break;
1298                 case FSE_AZ_EV_CODE_DRV_GEN_EV:
1299                         efx_farch_handle_generated_event(channel, &event);
1300                         break;
1301                 case FSE_AZ_EV_CODE_DRIVER_EV:
1302                         efx_farch_handle_driver_event(channel, &event);
1303                         break;
1304 #ifdef CONFIG_SFC_SRIOV
1305                 case FSE_CZ_EV_CODE_USER_EV:
1306                         efx_siena_sriov_event(channel, &event);
1307                         break;
1308 #endif
1309                 case FSE_CZ_EV_CODE_MCDI_EV:
1310                         efx_mcdi_process_event(channel, &event);
1311                         break;
1312                 case FSE_AZ_EV_CODE_GLOBAL_EV:
1313                         if (efx->type->handle_global_event &&
1314                             efx->type->handle_global_event(channel, &event))
1315                                 break;
1316                         fallthrough;
1317                 default:
1318                         netif_err(channel->efx, hw, channel->efx->net_dev,
1319                                   "channel %d unknown event type %d (data "
1320                                   EFX_QWORD_FMT ")\n", channel->channel,
1321                                   ev_code, EFX_QWORD_VAL(event));
1322                 }
1323         }
1324
1325 out:
1326         channel->eventq_read_ptr = read_ptr;
1327         return spent;
1328 }
1329
1330 /* Allocate buffer table entries for event queue */
1331 int efx_farch_ev_probe(struct efx_channel *channel)
1332 {
1333         struct efx_nic *efx = channel->efx;
1334         unsigned entries;
1335
1336         entries = channel->eventq_mask + 1;
1337         return efx_alloc_special_buffer(efx, &channel->eventq,
1338                                         entries * sizeof(efx_qword_t));
1339 }
1340
1341 int efx_farch_ev_init(struct efx_channel *channel)
1342 {
1343         efx_oword_t reg;
1344         struct efx_nic *efx = channel->efx;
1345
1346         netif_dbg(efx, hw, efx->net_dev,
1347                   "channel %d event queue in special buffers %d-%d\n",
1348                   channel->channel, channel->eventq.index,
1349                   channel->eventq.index + channel->eventq.entries - 1);
1350
1351         EFX_POPULATE_OWORD_3(reg,
1352                              FRF_CZ_TIMER_Q_EN, 1,
1353                              FRF_CZ_HOST_NOTIFY_MODE, 0,
1354                              FRF_CZ_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS);
1355         efx_writeo_table(efx, &reg, FR_BZ_TIMER_TBL, channel->channel);
1356
1357         /* Pin event queue buffer */
1358         efx_init_special_buffer(efx, &channel->eventq);
1359
1360         /* Fill event queue with all ones (i.e. empty events) */
1361         memset(channel->eventq.buf.addr, 0xff, channel->eventq.buf.len);
1362
1363         /* Push event queue to card */
1364         EFX_POPULATE_OWORD_3(reg,
1365                              FRF_AZ_EVQ_EN, 1,
1366                              FRF_AZ_EVQ_SIZE, __ffs(channel->eventq.entries),
1367                              FRF_AZ_EVQ_BUF_BASE_ID, channel->eventq.index);
1368         efx_writeo_table(efx, &reg, efx->type->evq_ptr_tbl_base,
1369                          channel->channel);
1370
1371         return 0;
1372 }
1373
1374 void efx_farch_ev_fini(struct efx_channel *channel)
1375 {
1376         efx_oword_t reg;
1377         struct efx_nic *efx = channel->efx;
1378
1379         /* Remove event queue from card */
1380         EFX_ZERO_OWORD(reg);
1381         efx_writeo_table(efx, &reg, efx->type->evq_ptr_tbl_base,
1382                          channel->channel);
1383         efx_writeo_table(efx, &reg, FR_BZ_TIMER_TBL, channel->channel);
1384
1385         /* Unpin event queue */
1386         efx_fini_special_buffer(efx, &channel->eventq);
1387 }
1388
1389 /* Free buffers backing event queue */
1390 void efx_farch_ev_remove(struct efx_channel *channel)
1391 {
1392         efx_free_special_buffer(channel->efx, &channel->eventq);
1393 }
1394
1395
1396 void efx_farch_ev_test_generate(struct efx_channel *channel)
1397 {
1398         efx_farch_magic_event(channel, EFX_CHANNEL_MAGIC_TEST(channel));
1399 }
1400
1401 void efx_farch_rx_defer_refill(struct efx_rx_queue *rx_queue)
1402 {
1403         efx_farch_magic_event(efx_rx_queue_channel(rx_queue),
1404                               EFX_CHANNEL_MAGIC_FILL(rx_queue));
1405 }
1406
1407 /**************************************************************************
1408  *
1409  * Hardware interrupts
1410  * The hardware interrupt handler does very little work; all the event
1411  * queue processing is carried out by per-channel tasklets.
1412  *
1413  **************************************************************************/
1414
1415 /* Enable/disable/generate interrupts */
1416 static inline void efx_farch_interrupts(struct efx_nic *efx,
1417                                       bool enabled, bool force)
1418 {
1419         efx_oword_t int_en_reg_ker;
1420
1421         EFX_POPULATE_OWORD_3(int_en_reg_ker,
1422                              FRF_AZ_KER_INT_LEVE_SEL, efx->irq_level,
1423                              FRF_AZ_KER_INT_KER, force,
1424                              FRF_AZ_DRV_INT_EN_KER, enabled);
1425         efx_writeo(efx, &int_en_reg_ker, FR_AZ_INT_EN_KER);
1426 }
1427
1428 void efx_farch_irq_enable_master(struct efx_nic *efx)
1429 {
1430         EFX_ZERO_OWORD(*((efx_oword_t *) efx->irq_status.addr));
1431         wmb(); /* Ensure interrupt vector is clear before interrupts enabled */
1432
1433         efx_farch_interrupts(efx, true, false);
1434 }
1435
1436 void efx_farch_irq_disable_master(struct efx_nic *efx)
1437 {
1438         /* Disable interrupts */
1439         efx_farch_interrupts(efx, false, false);
1440 }
1441
1442 /* Generate a test interrupt
1443  * Interrupt must already have been enabled, otherwise nasty things
1444  * may happen.
1445  */
1446 int efx_farch_irq_test_generate(struct efx_nic *efx)
1447 {
1448         efx_farch_interrupts(efx, true, true);
1449         return 0;
1450 }
1451
1452 /* Process a fatal interrupt
1453  * Disable bus mastering ASAP and schedule a reset
1454  */
1455 irqreturn_t efx_farch_fatal_interrupt(struct efx_nic *efx)
1456 {
1457         efx_oword_t *int_ker = efx->irq_status.addr;
1458         efx_oword_t fatal_intr;
1459         int error, mem_perr;
1460
1461         efx_reado(efx, &fatal_intr, FR_AZ_FATAL_INTR_KER);
1462         error = EFX_OWORD_FIELD(fatal_intr, FRF_AZ_FATAL_INTR);
1463
1464         netif_err(efx, hw, efx->net_dev, "SYSTEM ERROR "EFX_OWORD_FMT" status "
1465                   EFX_OWORD_FMT ": %s\n", EFX_OWORD_VAL(*int_ker),
1466                   EFX_OWORD_VAL(fatal_intr),
1467                   error ? "disabling bus mastering" : "no recognised error");
1468
1469         /* If this is a memory parity error dump which blocks are offending */
1470         mem_perr = (EFX_OWORD_FIELD(fatal_intr, FRF_AZ_MEM_PERR_INT_KER) ||
1471                     EFX_OWORD_FIELD(fatal_intr, FRF_AZ_SRM_PERR_INT_KER));
1472         if (mem_perr) {
1473                 efx_oword_t reg;
1474                 efx_reado(efx, &reg, FR_AZ_MEM_STAT);
1475                 netif_err(efx, hw, efx->net_dev,
1476                           "SYSTEM ERROR: memory parity error "EFX_OWORD_FMT"\n",
1477                           EFX_OWORD_VAL(reg));
1478         }
1479
1480         /* Disable both devices */
1481         pci_clear_master(efx->pci_dev);
1482         efx_farch_irq_disable_master(efx);
1483
1484         /* Count errors and reset or disable the NIC accordingly */
1485         if (efx->int_error_count == 0 ||
1486             time_after(jiffies, efx->int_error_expire)) {
1487                 efx->int_error_count = 0;
1488                 efx->int_error_expire =
1489                         jiffies + EFX_INT_ERROR_EXPIRE * HZ;
1490         }
1491         if (++efx->int_error_count < EFX_MAX_INT_ERRORS) {
1492                 netif_err(efx, hw, efx->net_dev,
1493                           "SYSTEM ERROR - reset scheduled\n");
1494                 efx_schedule_reset(efx, RESET_TYPE_INT_ERROR);
1495         } else {
1496                 netif_err(efx, hw, efx->net_dev,
1497                           "SYSTEM ERROR - max number of errors seen."
1498                           "NIC will be disabled\n");
1499                 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
1500         }
1501
1502         return IRQ_HANDLED;
1503 }
1504
1505 /* Handle a legacy interrupt
1506  * Acknowledges the interrupt and schedule event queue processing.
1507  */
1508 irqreturn_t efx_farch_legacy_interrupt(int irq, void *dev_id)
1509 {
1510         struct efx_nic *efx = dev_id;
1511         bool soft_enabled = READ_ONCE(efx->irq_soft_enabled);
1512         efx_oword_t *int_ker = efx->irq_status.addr;
1513         irqreturn_t result = IRQ_NONE;
1514         struct efx_channel *channel;
1515         efx_dword_t reg;
1516         u32 queues;
1517         int syserr;
1518
1519         /* Read the ISR which also ACKs the interrupts */
1520         efx_readd(efx, &reg, FR_BZ_INT_ISR0);
1521         queues = EFX_EXTRACT_DWORD(reg, 0, 31);
1522
1523         /* Legacy interrupts are disabled too late by the EEH kernel
1524          * code. Disable them earlier.
1525          * If an EEH error occurred, the read will have returned all ones.
1526          */
1527         if (EFX_DWORD_IS_ALL_ONES(reg) && efx_try_recovery(efx) &&
1528             !efx->eeh_disabled_legacy_irq) {
1529                 disable_irq_nosync(efx->legacy_irq);
1530                 efx->eeh_disabled_legacy_irq = true;
1531         }
1532
1533         /* Handle non-event-queue sources */
1534         if (queues & (1U << efx->irq_level) && soft_enabled) {
1535                 syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT);
1536                 if (unlikely(syserr))
1537                         return efx_farch_fatal_interrupt(efx);
1538                 efx->last_irq_cpu = raw_smp_processor_id();
1539         }
1540
1541         if (queues != 0) {
1542                 efx->irq_zero_count = 0;
1543
1544                 /* Schedule processing of any interrupting queues */
1545                 if (likely(soft_enabled)) {
1546                         efx_for_each_channel(channel, efx) {
1547                                 if (queues & 1)
1548                                         efx_schedule_channel_irq(channel);
1549                                 queues >>= 1;
1550                         }
1551                 }
1552                 result = IRQ_HANDLED;
1553
1554         } else {
1555                 efx_qword_t *event;
1556
1557                 /* Legacy ISR read can return zero once (SF bug 15783) */
1558
1559                 /* We can't return IRQ_HANDLED more than once on seeing ISR=0
1560                  * because this might be a shared interrupt. */
1561                 if (efx->irq_zero_count++ == 0)
1562                         result = IRQ_HANDLED;
1563
1564                 /* Ensure we schedule or rearm all event queues */
1565                 if (likely(soft_enabled)) {
1566                         efx_for_each_channel(channel, efx) {
1567                                 event = efx_event(channel,
1568                                                   channel->eventq_read_ptr);
1569                                 if (efx_event_present(event))
1570                                         efx_schedule_channel_irq(channel);
1571                                 else
1572                                         efx_farch_ev_read_ack(channel);
1573                         }
1574                 }
1575         }
1576
1577         if (result == IRQ_HANDLED)
1578                 netif_vdbg(efx, intr, efx->net_dev,
1579                            "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
1580                            irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
1581
1582         return result;
1583 }
1584
1585 /* Handle an MSI interrupt
1586  *
1587  * Handle an MSI hardware interrupt.  This routine schedules event
1588  * queue processing.  No interrupt acknowledgement cycle is necessary.
1589  * Also, we never need to check that the interrupt is for us, since
1590  * MSI interrupts cannot be shared.
1591  */
1592 irqreturn_t efx_farch_msi_interrupt(int irq, void *dev_id)
1593 {
1594         struct efx_msi_context *context = dev_id;
1595         struct efx_nic *efx = context->efx;
1596         efx_oword_t *int_ker = efx->irq_status.addr;
1597         int syserr;
1598
1599         netif_vdbg(efx, intr, efx->net_dev,
1600                    "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
1601                    irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
1602
1603         if (!likely(READ_ONCE(efx->irq_soft_enabled)))
1604                 return IRQ_HANDLED;
1605
1606         /* Handle non-event-queue sources */
1607         if (context->index == efx->irq_level) {
1608                 syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT);
1609                 if (unlikely(syserr))
1610                         return efx_farch_fatal_interrupt(efx);
1611                 efx->last_irq_cpu = raw_smp_processor_id();
1612         }
1613
1614         /* Schedule processing of the channel */
1615         efx_schedule_channel_irq(efx->channel[context->index]);
1616
1617         return IRQ_HANDLED;
1618 }
1619
1620 /* Setup RSS indirection table.
1621  * This maps from the hash value of the packet to RXQ
1622  */
1623 void efx_farch_rx_push_indir_table(struct efx_nic *efx)
1624 {
1625         size_t i = 0;
1626         efx_dword_t dword;
1627
1628         BUILD_BUG_ON(ARRAY_SIZE(efx->rss_context.rx_indir_table) !=
1629                      FR_BZ_RX_INDIRECTION_TBL_ROWS);
1630
1631         for (i = 0; i < FR_BZ_RX_INDIRECTION_TBL_ROWS; i++) {
1632                 EFX_POPULATE_DWORD_1(dword, FRF_BZ_IT_QUEUE,
1633                                      efx->rss_context.rx_indir_table[i]);
1634                 efx_writed(efx, &dword,
1635                            FR_BZ_RX_INDIRECTION_TBL +
1636                            FR_BZ_RX_INDIRECTION_TBL_STEP * i);
1637         }
1638 }
1639
1640 void efx_farch_rx_pull_indir_table(struct efx_nic *efx)
1641 {
1642         size_t i = 0;
1643         efx_dword_t dword;
1644
1645         BUILD_BUG_ON(ARRAY_SIZE(efx->rss_context.rx_indir_table) !=
1646                      FR_BZ_RX_INDIRECTION_TBL_ROWS);
1647
1648         for (i = 0; i < FR_BZ_RX_INDIRECTION_TBL_ROWS; i++) {
1649                 efx_readd(efx, &dword,
1650                            FR_BZ_RX_INDIRECTION_TBL +
1651                            FR_BZ_RX_INDIRECTION_TBL_STEP * i);
1652                 efx->rss_context.rx_indir_table[i] = EFX_DWORD_FIELD(dword, FRF_BZ_IT_QUEUE);
1653         }
1654 }
1655
1656 /* Looks at available SRAM resources and works out how many queues we
1657  * can support, and where things like descriptor caches should live.
1658  *
1659  * SRAM is split up as follows:
1660  * 0                          buftbl entries for channels
1661  * efx->vf_buftbl_base        buftbl entries for SR-IOV
1662  * efx->rx_dc_base            RX descriptor caches
1663  * efx->tx_dc_base            TX descriptor caches
1664  */
1665 void efx_farch_dimension_resources(struct efx_nic *efx, unsigned sram_lim_qw)
1666 {
1667         unsigned vi_count, buftbl_min, total_tx_channels;
1668
1669 #ifdef CONFIG_SFC_SRIOV
1670         struct siena_nic_data *nic_data = efx->nic_data;
1671 #endif
1672
1673         total_tx_channels = efx->n_tx_channels + efx->n_extra_tx_channels;
1674         /* Account for the buffer table entries backing the datapath channels
1675          * and the descriptor caches for those channels.
1676          */
1677         buftbl_min = ((efx->n_rx_channels * EFX_MAX_DMAQ_SIZE +
1678                        total_tx_channels * EFX_TXQ_TYPES * EFX_MAX_DMAQ_SIZE +
1679                        efx->n_channels * EFX_MAX_EVQ_SIZE)
1680                       * sizeof(efx_qword_t) / EFX_BUF_SIZE);
1681         vi_count = max(efx->n_channels, total_tx_channels * EFX_TXQ_TYPES);
1682
1683 #ifdef CONFIG_SFC_SRIOV
1684         if (efx->type->sriov_wanted) {
1685                 if (efx->type->sriov_wanted(efx)) {
1686                         unsigned vi_dc_entries, buftbl_free;
1687                         unsigned entries_per_vf, vf_limit;
1688
1689                         nic_data->vf_buftbl_base = buftbl_min;
1690
1691                         vi_dc_entries = RX_DC_ENTRIES + TX_DC_ENTRIES;
1692                         vi_count = max(vi_count, EFX_VI_BASE);
1693                         buftbl_free = (sram_lim_qw - buftbl_min -
1694                                        vi_count * vi_dc_entries);
1695
1696                         entries_per_vf = ((vi_dc_entries +
1697                                            EFX_VF_BUFTBL_PER_VI) *
1698                                           efx_vf_size(efx));
1699                         vf_limit = min(buftbl_free / entries_per_vf,
1700                                        (1024U - EFX_VI_BASE) >> efx->vi_scale);
1701
1702                         if (efx->vf_count > vf_limit) {
1703                                 netif_err(efx, probe, efx->net_dev,
1704                                           "Reducing VF count from from %d to %d\n",
1705                                           efx->vf_count, vf_limit);
1706                                 efx->vf_count = vf_limit;
1707                         }
1708                         vi_count += efx->vf_count * efx_vf_size(efx);
1709                 }
1710         }
1711 #endif
1712
1713         efx->tx_dc_base = sram_lim_qw - vi_count * TX_DC_ENTRIES;
1714         efx->rx_dc_base = efx->tx_dc_base - vi_count * RX_DC_ENTRIES;
1715 }
1716
1717 u32 efx_farch_fpga_ver(struct efx_nic *efx)
1718 {
1719         efx_oword_t altera_build;
1720         efx_reado(efx, &altera_build, FR_AZ_ALTERA_BUILD);
1721         return EFX_OWORD_FIELD(altera_build, FRF_AZ_ALTERA_BUILD_VER);
1722 }
1723
1724 void efx_farch_init_common(struct efx_nic *efx)
1725 {
1726         efx_oword_t temp;
1727
1728         /* Set positions of descriptor caches in SRAM. */
1729         EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_TX_DC_BASE_ADR, efx->tx_dc_base);
1730         efx_writeo(efx, &temp, FR_AZ_SRM_TX_DC_CFG);
1731         EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_RX_DC_BASE_ADR, efx->rx_dc_base);
1732         efx_writeo(efx, &temp, FR_AZ_SRM_RX_DC_CFG);
1733
1734         /* Set TX descriptor cache size. */
1735         BUILD_BUG_ON(TX_DC_ENTRIES != (8 << TX_DC_ENTRIES_ORDER));
1736         EFX_POPULATE_OWORD_1(temp, FRF_AZ_TX_DC_SIZE, TX_DC_ENTRIES_ORDER);
1737         efx_writeo(efx, &temp, FR_AZ_TX_DC_CFG);
1738
1739         /* Set RX descriptor cache size.  Set low watermark to size-8, as
1740          * this allows most efficient prefetching.
1741          */
1742         BUILD_BUG_ON(RX_DC_ENTRIES != (8 << RX_DC_ENTRIES_ORDER));
1743         EFX_POPULATE_OWORD_1(temp, FRF_AZ_RX_DC_SIZE, RX_DC_ENTRIES_ORDER);
1744         efx_writeo(efx, &temp, FR_AZ_RX_DC_CFG);
1745         EFX_POPULATE_OWORD_1(temp, FRF_AZ_RX_DC_PF_LWM, RX_DC_ENTRIES - 8);
1746         efx_writeo(efx, &temp, FR_AZ_RX_DC_PF_WM);
1747
1748         /* Program INT_KER address */
1749         EFX_POPULATE_OWORD_2(temp,
1750                              FRF_AZ_NORM_INT_VEC_DIS_KER,
1751                              EFX_INT_MODE_USE_MSI(efx),
1752                              FRF_AZ_INT_ADR_KER, efx->irq_status.dma_addr);
1753         efx_writeo(efx, &temp, FR_AZ_INT_ADR_KER);
1754
1755         if (EFX_WORKAROUND_17213(efx) && !EFX_INT_MODE_USE_MSI(efx))
1756                 /* Use an interrupt level unused by event queues */
1757                 efx->irq_level = 0x1f;
1758         else
1759                 /* Use a valid MSI-X vector */
1760                 efx->irq_level = 0;
1761
1762         /* Enable all the genuinely fatal interrupts.  (They are still
1763          * masked by the overall interrupt mask, controlled by
1764          * falcon_interrupts()).
1765          *
1766          * Note: All other fatal interrupts are enabled
1767          */
1768         EFX_POPULATE_OWORD_3(temp,
1769                              FRF_AZ_ILL_ADR_INT_KER_EN, 1,
1770                              FRF_AZ_RBUF_OWN_INT_KER_EN, 1,
1771                              FRF_AZ_TBUF_OWN_INT_KER_EN, 1);
1772         EFX_SET_OWORD_FIELD(temp, FRF_CZ_SRAM_PERR_INT_P_KER_EN, 1);
1773         EFX_INVERT_OWORD(temp);
1774         efx_writeo(efx, &temp, FR_AZ_FATAL_INTR_KER);
1775
1776         /* Disable the ugly timer-based TX DMA backoff and allow TX DMA to be
1777          * controlled by the RX FIFO fill level. Set arbitration to one pkt/Q.
1778          */
1779         efx_reado(efx, &temp, FR_AZ_TX_RESERVED);
1780         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER, 0xfe);
1781         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER_EN, 1);
1782         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_ONE_PKT_PER_Q, 1);
1783         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PUSH_EN, 1);
1784         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_DIS_NON_IP_EV, 1);
1785         /* Enable SW_EV to inherit in char driver - assume harmless here */
1786         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_SOFT_EVT_EN, 1);
1787         /* Prefetch threshold 2 => fetch when descriptor cache half empty */
1788         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PREF_THRESHOLD, 2);
1789         /* Disable hardware watchdog which can misfire */
1790         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PREF_WD_TMR, 0x3fffff);
1791         /* Squash TX of packets of 16 bytes or less */
1792         EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1);
1793         efx_writeo(efx, &temp, FR_AZ_TX_RESERVED);
1794
1795         EFX_POPULATE_OWORD_4(temp,
1796                              /* Default values */
1797                              FRF_BZ_TX_PACE_SB_NOT_AF, 0x15,
1798                              FRF_BZ_TX_PACE_SB_AF, 0xb,
1799                              FRF_BZ_TX_PACE_FB_BASE, 0,
1800                              /* Allow large pace values in the fast bin. */
1801                              FRF_BZ_TX_PACE_BIN_TH,
1802                              FFE_BZ_TX_PACE_RESERVED);
1803         efx_writeo(efx, &temp, FR_BZ_TX_PACE);
1804 }
1805
1806 /**************************************************************************
1807  *
1808  * Filter tables
1809  *
1810  **************************************************************************
1811  */
1812
1813 /* "Fudge factors" - difference between programmed value and actual depth.
1814  * Due to pipelined implementation we need to program H/W with a value that
1815  * is larger than the hop limit we want.
1816  */
1817 #define EFX_FARCH_FILTER_CTL_SRCH_FUDGE_WILD 3
1818 #define EFX_FARCH_FILTER_CTL_SRCH_FUDGE_FULL 1
1819
1820 /* Hard maximum search limit.  Hardware will time-out beyond 200-something.
1821  * We also need to avoid infinite loops in efx_farch_filter_search() when the
1822  * table is full.
1823  */
1824 #define EFX_FARCH_FILTER_CTL_SRCH_MAX 200
1825
1826 /* Don't try very hard to find space for performance hints, as this is
1827  * counter-productive. */
1828 #define EFX_FARCH_FILTER_CTL_SRCH_HINT_MAX 5
1829
1830 enum efx_farch_filter_type {
1831         EFX_FARCH_FILTER_TCP_FULL = 0,
1832         EFX_FARCH_FILTER_TCP_WILD,
1833         EFX_FARCH_FILTER_UDP_FULL,
1834         EFX_FARCH_FILTER_UDP_WILD,
1835         EFX_FARCH_FILTER_MAC_FULL = 4,
1836         EFX_FARCH_FILTER_MAC_WILD,
1837         EFX_FARCH_FILTER_UC_DEF = 8,
1838         EFX_FARCH_FILTER_MC_DEF,
1839         EFX_FARCH_FILTER_TYPE_COUNT,            /* number of specific types */
1840 };
1841
1842 enum efx_farch_filter_table_id {
1843         EFX_FARCH_FILTER_TABLE_RX_IP = 0,
1844         EFX_FARCH_FILTER_TABLE_RX_MAC,
1845         EFX_FARCH_FILTER_TABLE_RX_DEF,
1846         EFX_FARCH_FILTER_TABLE_TX_MAC,
1847         EFX_FARCH_FILTER_TABLE_COUNT,
1848 };
1849
1850 enum efx_farch_filter_index {
1851         EFX_FARCH_FILTER_INDEX_UC_DEF,
1852         EFX_FARCH_FILTER_INDEX_MC_DEF,
1853         EFX_FARCH_FILTER_SIZE_RX_DEF,
1854 };
1855
1856 struct efx_farch_filter_spec {
1857         u8      type:4;
1858         u8      priority:4;
1859         u8      flags;
1860         u16     dmaq_id;
1861         u32     data[3];
1862 };
1863
1864 struct efx_farch_filter_table {
1865         enum efx_farch_filter_table_id id;
1866         u32             offset;         /* address of table relative to BAR */
1867         unsigned        size;           /* number of entries */
1868         unsigned        step;           /* step between entries */
1869         unsigned        used;           /* number currently used */
1870         unsigned long   *used_bitmap;
1871         struct efx_farch_filter_spec *spec;
1872         unsigned        search_limit[EFX_FARCH_FILTER_TYPE_COUNT];
1873 };
1874
1875 struct efx_farch_filter_state {
1876         struct rw_semaphore lock; /* Protects table contents */
1877         struct efx_farch_filter_table table[EFX_FARCH_FILTER_TABLE_COUNT];
1878 };
1879
1880 static void
1881 efx_farch_filter_table_clear_entry(struct efx_nic *efx,
1882                                    struct efx_farch_filter_table *table,
1883                                    unsigned int filter_idx);
1884
1885 /* The filter hash function is LFSR polynomial x^16 + x^3 + 1 of a 32-bit
1886  * key derived from the n-tuple.  The initial LFSR state is 0xffff. */
1887 static u16 efx_farch_filter_hash(u32 key)
1888 {
1889         u16 tmp;
1890
1891         /* First 16 rounds */
1892         tmp = 0x1fff ^ key >> 16;
1893         tmp = tmp ^ tmp >> 3 ^ tmp >> 6;
1894         tmp = tmp ^ tmp >> 9;
1895         /* Last 16 rounds */
1896         tmp = tmp ^ tmp << 13 ^ key;
1897         tmp = tmp ^ tmp >> 3 ^ tmp >> 6;
1898         return tmp ^ tmp >> 9;
1899 }
1900
1901 /* To allow for hash collisions, filter search continues at these
1902  * increments from the first possible entry selected by the hash. */
1903 static u16 efx_farch_filter_increment(u32 key)
1904 {
1905         return key * 2 - 1;
1906 }
1907
1908 static enum efx_farch_filter_table_id
1909 efx_farch_filter_spec_table_id(const struct efx_farch_filter_spec *spec)
1910 {
1911         BUILD_BUG_ON(EFX_FARCH_FILTER_TABLE_RX_IP !=
1912                      (EFX_FARCH_FILTER_TCP_FULL >> 2));
1913         BUILD_BUG_ON(EFX_FARCH_FILTER_TABLE_RX_IP !=
1914                      (EFX_FARCH_FILTER_TCP_WILD >> 2));
1915         BUILD_BUG_ON(EFX_FARCH_FILTER_TABLE_RX_IP !=
1916                      (EFX_FARCH_FILTER_UDP_FULL >> 2));
1917         BUILD_BUG_ON(EFX_FARCH_FILTER_TABLE_RX_IP !=
1918                      (EFX_FARCH_FILTER_UDP_WILD >> 2));
1919         BUILD_BUG_ON(EFX_FARCH_FILTER_TABLE_RX_MAC !=
1920                      (EFX_FARCH_FILTER_MAC_FULL >> 2));
1921         BUILD_BUG_ON(EFX_FARCH_FILTER_TABLE_RX_MAC !=
1922                      (EFX_FARCH_FILTER_MAC_WILD >> 2));
1923         BUILD_BUG_ON(EFX_FARCH_FILTER_TABLE_TX_MAC !=
1924                      EFX_FARCH_FILTER_TABLE_RX_MAC + 2);
1925         return (spec->type >> 2) + ((spec->flags & EFX_FILTER_FLAG_TX) ? 2 : 0);
1926 }
1927
1928 static void efx_farch_filter_push_rx_config(struct efx_nic *efx)
1929 {
1930         struct efx_farch_filter_state *state = efx->filter_state;
1931         struct efx_farch_filter_table *table;
1932         efx_oword_t filter_ctl;
1933
1934         efx_reado(efx, &filter_ctl, FR_BZ_RX_FILTER_CTL);
1935
1936         table = &state->table[EFX_FARCH_FILTER_TABLE_RX_IP];
1937         EFX_SET_OWORD_FIELD(filter_ctl, FRF_BZ_TCP_FULL_SRCH_LIMIT,
1938                             table->search_limit[EFX_FARCH_FILTER_TCP_FULL] +
1939                             EFX_FARCH_FILTER_CTL_SRCH_FUDGE_FULL);
1940         EFX_SET_OWORD_FIELD(filter_ctl, FRF_BZ_TCP_WILD_SRCH_LIMIT,
1941                             table->search_limit[EFX_FARCH_FILTER_TCP_WILD] +
1942                             EFX_FARCH_FILTER_CTL_SRCH_FUDGE_WILD);
1943         EFX_SET_OWORD_FIELD(filter_ctl, FRF_BZ_UDP_FULL_SRCH_LIMIT,
1944                             table->search_limit[EFX_FARCH_FILTER_UDP_FULL] +
1945                             EFX_FARCH_FILTER_CTL_SRCH_FUDGE_FULL);
1946         EFX_SET_OWORD_FIELD(filter_ctl, FRF_BZ_UDP_WILD_SRCH_LIMIT,
1947                             table->search_limit[EFX_FARCH_FILTER_UDP_WILD] +
1948                             EFX_FARCH_FILTER_CTL_SRCH_FUDGE_WILD);
1949
1950         table = &state->table[EFX_FARCH_FILTER_TABLE_RX_MAC];
1951         if (table->size) {
1952                 EFX_SET_OWORD_FIELD(
1953                         filter_ctl, FRF_CZ_ETHERNET_FULL_SEARCH_LIMIT,
1954                         table->search_limit[EFX_FARCH_FILTER_MAC_FULL] +
1955                         EFX_FARCH_FILTER_CTL_SRCH_FUDGE_FULL);
1956                 EFX_SET_OWORD_FIELD(
1957                         filter_ctl, FRF_CZ_ETHERNET_WILDCARD_SEARCH_LIMIT,
1958                         table->search_limit[EFX_FARCH_FILTER_MAC_WILD] +
1959                         EFX_FARCH_FILTER_CTL_SRCH_FUDGE_WILD);
1960         }
1961
1962         table = &state->table[EFX_FARCH_FILTER_TABLE_RX_DEF];
1963         if (table->size) {
1964                 EFX_SET_OWORD_FIELD(
1965                         filter_ctl, FRF_CZ_UNICAST_NOMATCH_Q_ID,
1966                         table->spec[EFX_FARCH_FILTER_INDEX_UC_DEF].dmaq_id);
1967                 EFX_SET_OWORD_FIELD(
1968                         filter_ctl, FRF_CZ_UNICAST_NOMATCH_RSS_ENABLED,
1969                         !!(table->spec[EFX_FARCH_FILTER_INDEX_UC_DEF].flags &
1970                            EFX_FILTER_FLAG_RX_RSS));
1971                 EFX_SET_OWORD_FIELD(
1972                         filter_ctl, FRF_CZ_MULTICAST_NOMATCH_Q_ID,
1973                         table->spec[EFX_FARCH_FILTER_INDEX_MC_DEF].dmaq_id);
1974                 EFX_SET_OWORD_FIELD(
1975                         filter_ctl, FRF_CZ_MULTICAST_NOMATCH_RSS_ENABLED,
1976                         !!(table->spec[EFX_FARCH_FILTER_INDEX_MC_DEF].flags &
1977                            EFX_FILTER_FLAG_RX_RSS));
1978
1979                 /* There is a single bit to enable RX scatter for all
1980                  * unmatched packets.  Only set it if scatter is
1981                  * enabled in both filter specs.
1982                  */
1983                 EFX_SET_OWORD_FIELD(
1984                         filter_ctl, FRF_BZ_SCATTER_ENBL_NO_MATCH_Q,
1985                         !!(table->spec[EFX_FARCH_FILTER_INDEX_UC_DEF].flags &
1986                            table->spec[EFX_FARCH_FILTER_INDEX_MC_DEF].flags &
1987                            EFX_FILTER_FLAG_RX_SCATTER));
1988         } else {
1989                 /* We don't expose 'default' filters because unmatched
1990                  * packets always go to the queue number found in the
1991                  * RSS table.  But we still need to set the RX scatter
1992                  * bit here.
1993                  */
1994                 EFX_SET_OWORD_FIELD(
1995                         filter_ctl, FRF_BZ_SCATTER_ENBL_NO_MATCH_Q,
1996                         efx->rx_scatter);
1997         }
1998
1999         efx_writeo(efx, &filter_ctl, FR_BZ_RX_FILTER_CTL);
2000 }
2001
2002 static void efx_farch_filter_push_tx_limits(struct efx_nic *efx)
2003 {
2004         struct efx_farch_filter_state *state = efx->filter_state;
2005         struct efx_farch_filter_table *table;
2006         efx_oword_t tx_cfg;
2007
2008         efx_reado(efx, &tx_cfg, FR_AZ_TX_CFG);
2009
2010         table = &state->table[EFX_FARCH_FILTER_TABLE_TX_MAC];
2011         if (table->size) {
2012                 EFX_SET_OWORD_FIELD(
2013                         tx_cfg, FRF_CZ_TX_ETH_FILTER_FULL_SEARCH_RANGE,
2014                         table->search_limit[EFX_FARCH_FILTER_MAC_FULL] +
2015                         EFX_FARCH_FILTER_CTL_SRCH_FUDGE_FULL);
2016                 EFX_SET_OWORD_FIELD(
2017                         tx_cfg, FRF_CZ_TX_ETH_FILTER_WILD_SEARCH_RANGE,
2018                         table->search_limit[EFX_FARCH_FILTER_MAC_WILD] +
2019                         EFX_FARCH_FILTER_CTL_SRCH_FUDGE_WILD);
2020         }
2021
2022         efx_writeo(efx, &tx_cfg, FR_AZ_TX_CFG);
2023 }
2024
2025 static int
2026 efx_farch_filter_from_gen_spec(struct efx_farch_filter_spec *spec,
2027                                const struct efx_filter_spec *gen_spec)
2028 {
2029         bool is_full = false;
2030
2031         if ((gen_spec->flags & EFX_FILTER_FLAG_RX_RSS) && gen_spec->rss_context)
2032                 return -EINVAL;
2033
2034         spec->priority = gen_spec->priority;
2035         spec->flags = gen_spec->flags;
2036         spec->dmaq_id = gen_spec->dmaq_id;
2037
2038         switch (gen_spec->match_flags) {
2039         case (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_IP_PROTO |
2040               EFX_FILTER_MATCH_LOC_HOST | EFX_FILTER_MATCH_LOC_PORT |
2041               EFX_FILTER_MATCH_REM_HOST | EFX_FILTER_MATCH_REM_PORT):
2042                 is_full = true;
2043                 fallthrough;
2044         case (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_IP_PROTO |
2045               EFX_FILTER_MATCH_LOC_HOST | EFX_FILTER_MATCH_LOC_PORT): {
2046                 __be32 rhost, host1, host2;
2047                 __be16 rport, port1, port2;
2048
2049                 EFX_WARN_ON_PARANOID(!(gen_spec->flags & EFX_FILTER_FLAG_RX));
2050
2051                 if (gen_spec->ether_type != htons(ETH_P_IP))
2052                         return -EPROTONOSUPPORT;
2053                 if (gen_spec->loc_port == 0 ||
2054                     (is_full && gen_spec->rem_port == 0))
2055                         return -EADDRNOTAVAIL;
2056                 switch (gen_spec->ip_proto) {
2057                 case IPPROTO_TCP:
2058                         spec->type = (is_full ? EFX_FARCH_FILTER_TCP_FULL :
2059                                       EFX_FARCH_FILTER_TCP_WILD);
2060                         break;
2061                 case IPPROTO_UDP:
2062                         spec->type = (is_full ? EFX_FARCH_FILTER_UDP_FULL :
2063                                       EFX_FARCH_FILTER_UDP_WILD);
2064                         break;
2065                 default:
2066                         return -EPROTONOSUPPORT;
2067                 }
2068
2069                 /* Filter is constructed in terms of source and destination,
2070                  * with the odd wrinkle that the ports are swapped in a UDP
2071                  * wildcard filter.  We need to convert from local and remote
2072                  * (= zero for wildcard) addresses.
2073                  */
2074                 rhost = is_full ? gen_spec->rem_host[0] : 0;
2075                 rport = is_full ? gen_spec->rem_port : 0;
2076                 host1 = rhost;
2077                 host2 = gen_spec->loc_host[0];
2078                 if (!is_full && gen_spec->ip_proto == IPPROTO_UDP) {
2079                         port1 = gen_spec->loc_port;
2080                         port2 = rport;
2081                 } else {
2082                         port1 = rport;
2083                         port2 = gen_spec->loc_port;
2084                 }
2085                 spec->data[0] = ntohl(host1) << 16 | ntohs(port1);
2086                 spec->data[1] = ntohs(port2) << 16 | ntohl(host1) >> 16;
2087                 spec->data[2] = ntohl(host2);
2088
2089                 break;
2090         }
2091
2092         case EFX_FILTER_MATCH_LOC_MAC | EFX_FILTER_MATCH_OUTER_VID:
2093                 is_full = true;
2094                 fallthrough;
2095         case EFX_FILTER_MATCH_LOC_MAC:
2096                 spec->type = (is_full ? EFX_FARCH_FILTER_MAC_FULL :
2097                               EFX_FARCH_FILTER_MAC_WILD);
2098                 spec->data[0] = is_full ? ntohs(gen_spec->outer_vid) : 0;
2099                 spec->data[1] = (gen_spec->loc_mac[2] << 24 |
2100                                  gen_spec->loc_mac[3] << 16 |
2101                                  gen_spec->loc_mac[4] << 8 |
2102                                  gen_spec->loc_mac[5]);
2103                 spec->data[2] = (gen_spec->loc_mac[0] << 8 |
2104                                  gen_spec->loc_mac[1]);
2105                 break;
2106
2107         case EFX_FILTER_MATCH_LOC_MAC_IG:
2108                 spec->type = (is_multicast_ether_addr(gen_spec->loc_mac) ?
2109                               EFX_FARCH_FILTER_MC_DEF :
2110                               EFX_FARCH_FILTER_UC_DEF);
2111                 memset(spec->data, 0, sizeof(spec->data)); /* ensure equality */
2112                 break;
2113
2114         default:
2115                 return -EPROTONOSUPPORT;
2116         }
2117
2118         return 0;
2119 }
2120
2121 static void
2122 efx_farch_filter_to_gen_spec(struct efx_filter_spec *gen_spec,
2123                              const struct efx_farch_filter_spec *spec)
2124 {
2125         bool is_full = false;
2126
2127         /* *gen_spec should be completely initialised, to be consistent
2128          * with efx_filter_init_{rx,tx}() and in case we want to copy
2129          * it back to userland.
2130          */
2131         memset(gen_spec, 0, sizeof(*gen_spec));
2132
2133         gen_spec->priority = spec->priority;
2134         gen_spec->flags = spec->flags;
2135         gen_spec->dmaq_id = spec->dmaq_id;
2136
2137         switch (spec->type) {
2138         case EFX_FARCH_FILTER_TCP_FULL:
2139         case EFX_FARCH_FILTER_UDP_FULL:
2140                 is_full = true;
2141                 fallthrough;
2142         case EFX_FARCH_FILTER_TCP_WILD:
2143         case EFX_FARCH_FILTER_UDP_WILD: {
2144                 __be32 host1, host2;
2145                 __be16 port1, port2;
2146
2147                 gen_spec->match_flags =
2148                         EFX_FILTER_MATCH_ETHER_TYPE |
2149                         EFX_FILTER_MATCH_IP_PROTO |
2150                         EFX_FILTER_MATCH_LOC_HOST | EFX_FILTER_MATCH_LOC_PORT;
2151                 if (is_full)
2152                         gen_spec->match_flags |= (EFX_FILTER_MATCH_REM_HOST |
2153                                                   EFX_FILTER_MATCH_REM_PORT);
2154                 gen_spec->ether_type = htons(ETH_P_IP);
2155                 gen_spec->ip_proto =
2156                         (spec->type == EFX_FARCH_FILTER_TCP_FULL ||
2157                          spec->type == EFX_FARCH_FILTER_TCP_WILD) ?
2158                         IPPROTO_TCP : IPPROTO_UDP;
2159
2160                 host1 = htonl(spec->data[0] >> 16 | spec->data[1] << 16);
2161                 port1 = htons(spec->data[0]);
2162                 host2 = htonl(spec->data[2]);
2163                 port2 = htons(spec->data[1] >> 16);
2164                 if (spec->flags & EFX_FILTER_FLAG_TX) {
2165                         gen_spec->loc_host[0] = host1;
2166                         gen_spec->rem_host[0] = host2;
2167                 } else {
2168                         gen_spec->loc_host[0] = host2;
2169                         gen_spec->rem_host[0] = host1;
2170                 }
2171                 if (!!(gen_spec->flags & EFX_FILTER_FLAG_TX) ^
2172                     (!is_full && gen_spec->ip_proto == IPPROTO_UDP)) {
2173                         gen_spec->loc_port = port1;
2174                         gen_spec->rem_port = port2;
2175                 } else {
2176                         gen_spec->loc_port = port2;
2177                         gen_spec->rem_port = port1;
2178                 }
2179
2180                 break;
2181         }
2182
2183         case EFX_FARCH_FILTER_MAC_FULL:
2184                 is_full = true;
2185                 fallthrough;
2186         case EFX_FARCH_FILTER_MAC_WILD:
2187                 gen_spec->match_flags = EFX_FILTER_MATCH_LOC_MAC;
2188                 if (is_full)
2189                         gen_spec->match_flags |= EFX_FILTER_MATCH_OUTER_VID;
2190                 gen_spec->loc_mac[0] = spec->data[2] >> 8;
2191                 gen_spec->loc_mac[1] = spec->data[2];
2192                 gen_spec->loc_mac[2] = spec->data[1] >> 24;
2193                 gen_spec->loc_mac[3] = spec->data[1] >> 16;
2194                 gen_spec->loc_mac[4] = spec->data[1] >> 8;
2195                 gen_spec->loc_mac[5] = spec->data[1];
2196                 gen_spec->outer_vid = htons(spec->data[0]);
2197                 break;
2198
2199         case EFX_FARCH_FILTER_UC_DEF:
2200         case EFX_FARCH_FILTER_MC_DEF:
2201                 gen_spec->match_flags = EFX_FILTER_MATCH_LOC_MAC_IG;
2202                 gen_spec->loc_mac[0] = spec->type == EFX_FARCH_FILTER_MC_DEF;
2203                 break;
2204
2205         default:
2206                 WARN_ON(1);
2207                 break;
2208         }
2209 }
2210
2211 static void
2212 efx_farch_filter_init_rx_auto(struct efx_nic *efx,
2213                               struct efx_farch_filter_spec *spec)
2214 {
2215         /* If there's only one channel then disable RSS for non VF
2216          * traffic, thereby allowing VFs to use RSS when the PF can't.
2217          */
2218         spec->priority = EFX_FILTER_PRI_AUTO;
2219         spec->flags = (EFX_FILTER_FLAG_RX |
2220                        (efx_rss_enabled(efx) ? EFX_FILTER_FLAG_RX_RSS : 0) |
2221                        (efx->rx_scatter ? EFX_FILTER_FLAG_RX_SCATTER : 0));
2222         spec->dmaq_id = 0;
2223 }
2224
2225 /* Build a filter entry and return its n-tuple key. */
2226 static u32 efx_farch_filter_build(efx_oword_t *filter,
2227                                   struct efx_farch_filter_spec *spec)
2228 {
2229         u32 data3;
2230
2231         switch (efx_farch_filter_spec_table_id(spec)) {
2232         case EFX_FARCH_FILTER_TABLE_RX_IP: {
2233                 bool is_udp = (spec->type == EFX_FARCH_FILTER_UDP_FULL ||
2234                                spec->type == EFX_FARCH_FILTER_UDP_WILD);
2235                 EFX_POPULATE_OWORD_7(
2236                         *filter,
2237                         FRF_BZ_RSS_EN,
2238                         !!(spec->flags & EFX_FILTER_FLAG_RX_RSS),
2239                         FRF_BZ_SCATTER_EN,
2240                         !!(spec->flags & EFX_FILTER_FLAG_RX_SCATTER),
2241                         FRF_BZ_TCP_UDP, is_udp,
2242                         FRF_BZ_RXQ_ID, spec->dmaq_id,
2243                         EFX_DWORD_2, spec->data[2],
2244                         EFX_DWORD_1, spec->data[1],
2245                         EFX_DWORD_0, spec->data[0]);
2246                 data3 = is_udp;
2247                 break;
2248         }
2249
2250         case EFX_FARCH_FILTER_TABLE_RX_MAC: {
2251                 bool is_wild = spec->type == EFX_FARCH_FILTER_MAC_WILD;
2252                 EFX_POPULATE_OWORD_7(
2253                         *filter,
2254                         FRF_CZ_RMFT_RSS_EN,
2255                         !!(spec->flags & EFX_FILTER_FLAG_RX_RSS),
2256                         FRF_CZ_RMFT_SCATTER_EN,
2257                         !!(spec->flags & EFX_FILTER_FLAG_RX_SCATTER),
2258                         FRF_CZ_RMFT_RXQ_ID, spec->dmaq_id,
2259                         FRF_CZ_RMFT_WILDCARD_MATCH, is_wild,
2260                         FRF_CZ_RMFT_DEST_MAC_HI, spec->data[2],
2261                         FRF_CZ_RMFT_DEST_MAC_LO, spec->data[1],
2262                         FRF_CZ_RMFT_VLAN_ID, spec->data[0]);
2263                 data3 = is_wild;
2264                 break;
2265         }
2266
2267         case EFX_FARCH_FILTER_TABLE_TX_MAC: {
2268                 bool is_wild = spec->type == EFX_FARCH_FILTER_MAC_WILD;
2269                 EFX_POPULATE_OWORD_5(*filter,
2270                                      FRF_CZ_TMFT_TXQ_ID, spec->dmaq_id,
2271                                      FRF_CZ_TMFT_WILDCARD_MATCH, is_wild,
2272                                      FRF_CZ_TMFT_SRC_MAC_HI, spec->data[2],
2273                                      FRF_CZ_TMFT_SRC_MAC_LO, spec->data[1],
2274                                      FRF_CZ_TMFT_VLAN_ID, spec->data[0]);
2275                 data3 = is_wild | spec->dmaq_id << 1;
2276                 break;
2277         }
2278
2279         default:
2280                 BUG();
2281         }
2282
2283         return spec->data[0] ^ spec->data[1] ^ spec->data[2] ^ data3;
2284 }
2285
2286 static bool efx_farch_filter_equal(const struct efx_farch_filter_spec *left,
2287                                    const struct efx_farch_filter_spec *right)
2288 {
2289         if (left->type != right->type ||
2290             memcmp(left->data, right->data, sizeof(left->data)))
2291                 return false;
2292
2293         if (left->flags & EFX_FILTER_FLAG_TX &&
2294             left->dmaq_id != right->dmaq_id)
2295                 return false;
2296
2297         return true;
2298 }
2299
2300 /*
2301  * Construct/deconstruct external filter IDs.  At least the RX filter
2302  * IDs must be ordered by matching priority, for RX NFC semantics.
2303  *
2304  * Deconstruction needs to be robust against invalid IDs so that
2305  * efx_filter_remove_id_safe() and efx_filter_get_filter_safe() can
2306  * accept user-provided IDs.
2307  */
2308
2309 #define EFX_FARCH_FILTER_MATCH_PRI_COUNT        5
2310
2311 static const u8 efx_farch_filter_type_match_pri[EFX_FARCH_FILTER_TYPE_COUNT] = {
2312         [EFX_FARCH_FILTER_TCP_FULL]     = 0,
2313         [EFX_FARCH_FILTER_UDP_FULL]     = 0,
2314         [EFX_FARCH_FILTER_TCP_WILD]     = 1,
2315         [EFX_FARCH_FILTER_UDP_WILD]     = 1,
2316         [EFX_FARCH_FILTER_MAC_FULL]     = 2,
2317         [EFX_FARCH_FILTER_MAC_WILD]     = 3,
2318         [EFX_FARCH_FILTER_UC_DEF]       = 4,
2319         [EFX_FARCH_FILTER_MC_DEF]       = 4,
2320 };
2321
2322 static const enum efx_farch_filter_table_id efx_farch_filter_range_table[] = {
2323         EFX_FARCH_FILTER_TABLE_RX_IP,   /* RX match pri 0 */
2324         EFX_FARCH_FILTER_TABLE_RX_IP,
2325         EFX_FARCH_FILTER_TABLE_RX_MAC,
2326         EFX_FARCH_FILTER_TABLE_RX_MAC,
2327         EFX_FARCH_FILTER_TABLE_RX_DEF,  /* RX match pri 4 */
2328         EFX_FARCH_FILTER_TABLE_TX_MAC,  /* TX match pri 0 */
2329         EFX_FARCH_FILTER_TABLE_TX_MAC,  /* TX match pri 1 */
2330 };
2331
2332 #define EFX_FARCH_FILTER_INDEX_WIDTH 13
2333 #define EFX_FARCH_FILTER_INDEX_MASK ((1 << EFX_FARCH_FILTER_INDEX_WIDTH) - 1)
2334
2335 static inline u32
2336 efx_farch_filter_make_id(const struct efx_farch_filter_spec *spec,
2337                          unsigned int index)
2338 {
2339         unsigned int range;
2340
2341         range = efx_farch_filter_type_match_pri[spec->type];
2342         if (!(spec->flags & EFX_FILTER_FLAG_RX))
2343                 range += EFX_FARCH_FILTER_MATCH_PRI_COUNT;
2344
2345         return range << EFX_FARCH_FILTER_INDEX_WIDTH | index;
2346 }
2347
2348 static inline enum efx_farch_filter_table_id
2349 efx_farch_filter_id_table_id(u32 id)
2350 {
2351         unsigned int range = id >> EFX_FARCH_FILTER_INDEX_WIDTH;
2352
2353         if (range < ARRAY_SIZE(efx_farch_filter_range_table))
2354                 return efx_farch_filter_range_table[range];
2355         else
2356                 return EFX_FARCH_FILTER_TABLE_COUNT; /* invalid */
2357 }
2358
2359 static inline unsigned int efx_farch_filter_id_index(u32 id)
2360 {
2361         return id & EFX_FARCH_FILTER_INDEX_MASK;
2362 }
2363
2364 u32 efx_farch_filter_get_rx_id_limit(struct efx_nic *efx)
2365 {
2366         struct efx_farch_filter_state *state = efx->filter_state;
2367         unsigned int range = EFX_FARCH_FILTER_MATCH_PRI_COUNT - 1;
2368         enum efx_farch_filter_table_id table_id;
2369
2370         do {
2371                 table_id = efx_farch_filter_range_table[range];
2372                 if (state->table[table_id].size != 0)
2373                         return range << EFX_FARCH_FILTER_INDEX_WIDTH |
2374                                 state->table[table_id].size;
2375         } while (range--);
2376
2377         return 0;
2378 }
2379
2380 s32 efx_farch_filter_insert(struct efx_nic *efx,
2381                             struct efx_filter_spec *gen_spec,
2382                             bool replace_equal)
2383 {
2384         struct efx_farch_filter_state *state = efx->filter_state;
2385         struct efx_farch_filter_table *table;
2386         struct efx_farch_filter_spec spec;
2387         efx_oword_t filter;
2388         int rep_index, ins_index;
2389         unsigned int depth = 0;
2390         int rc;
2391
2392         rc = efx_farch_filter_from_gen_spec(&spec, gen_spec);
2393         if (rc)
2394                 return rc;
2395
2396         down_write(&state->lock);
2397
2398         table = &state->table[efx_farch_filter_spec_table_id(&spec)];
2399         if (table->size == 0) {
2400                 rc = -EINVAL;
2401                 goto out_unlock;
2402         }
2403
2404         netif_vdbg(efx, hw, efx->net_dev,
2405                    "%s: type %d search_limit=%d", __func__, spec.type,
2406                    table->search_limit[spec.type]);
2407
2408         if (table->id == EFX_FARCH_FILTER_TABLE_RX_DEF) {
2409                 /* One filter spec per type */
2410                 BUILD_BUG_ON(EFX_FARCH_FILTER_INDEX_UC_DEF != 0);
2411                 BUILD_BUG_ON(EFX_FARCH_FILTER_INDEX_MC_DEF !=
2412                              EFX_FARCH_FILTER_MC_DEF - EFX_FARCH_FILTER_UC_DEF);
2413                 rep_index = spec.type - EFX_FARCH_FILTER_UC_DEF;
2414                 ins_index = rep_index;
2415         } else {
2416                 /* Search concurrently for
2417                  * (1) a filter to be replaced (rep_index): any filter
2418                  *     with the same match values, up to the current
2419                  *     search depth for this type, and
2420                  * (2) the insertion point (ins_index): (1) or any
2421                  *     free slot before it or up to the maximum search
2422                  *     depth for this priority
2423                  * We fail if we cannot find (2).
2424                  *
2425                  * We can stop once either
2426                  * (a) we find (1), in which case we have definitely
2427                  *     found (2) as well; or
2428                  * (b) we have searched exhaustively for (1), and have
2429                  *     either found (2) or searched exhaustively for it
2430                  */
2431                 u32 key = efx_farch_filter_build(&filter, &spec);
2432                 unsigned int hash = efx_farch_filter_hash(key);
2433                 unsigned int incr = efx_farch_filter_increment(key);
2434                 unsigned int max_rep_depth = table->search_limit[spec.type];
2435                 unsigned int max_ins_depth =
2436                         spec.priority <= EFX_FILTER_PRI_HINT ?
2437                         EFX_FARCH_FILTER_CTL_SRCH_HINT_MAX :
2438                         EFX_FARCH_FILTER_CTL_SRCH_MAX;
2439                 unsigned int i = hash & (table->size - 1);
2440
2441                 ins_index = -1;
2442                 depth = 1;
2443
2444                 for (;;) {
2445                         if (!test_bit(i, table->used_bitmap)) {
2446                                 if (ins_index < 0)
2447                                         ins_index = i;
2448                         } else if (efx_farch_filter_equal(&spec,
2449                                                           &table->spec[i])) {
2450                                 /* Case (a) */
2451                                 if (ins_index < 0)
2452                                         ins_index = i;
2453                                 rep_index = i;
2454                                 break;
2455                         }
2456
2457                         if (depth >= max_rep_depth &&
2458                             (ins_index >= 0 || depth >= max_ins_depth)) {
2459                                 /* Case (b) */
2460                                 if (ins_index < 0) {
2461                                         rc = -EBUSY;
2462                                         goto out_unlock;
2463                                 }
2464                                 rep_index = -1;
2465                                 break;
2466                         }
2467
2468                         i = (i + incr) & (table->size - 1);
2469                         ++depth;
2470                 }
2471         }
2472
2473         /* If we found a filter to be replaced, check whether we
2474          * should do so
2475          */
2476         if (rep_index >= 0) {
2477                 struct efx_farch_filter_spec *saved_spec =
2478                         &table->spec[rep_index];
2479
2480                 if (spec.priority == saved_spec->priority && !replace_equal) {
2481                         rc = -EEXIST;
2482                         goto out_unlock;
2483                 }
2484                 if (spec.priority < saved_spec->priority) {
2485                         rc = -EPERM;
2486                         goto out_unlock;
2487                 }
2488                 if (saved_spec->priority == EFX_FILTER_PRI_AUTO ||
2489                     saved_spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO)
2490                         spec.flags |= EFX_FILTER_FLAG_RX_OVER_AUTO;
2491         }
2492
2493         /* Insert the filter */
2494         if (ins_index != rep_index) {
2495                 __set_bit(ins_index, table->used_bitmap);
2496                 ++table->used;
2497         }
2498         table->spec[ins_index] = spec;
2499
2500         if (table->id == EFX_FARCH_FILTER_TABLE_RX_DEF) {
2501                 efx_farch_filter_push_rx_config(efx);
2502         } else {
2503                 if (table->search_limit[spec.type] < depth) {
2504                         table->search_limit[spec.type] = depth;
2505                         if (spec.flags & EFX_FILTER_FLAG_TX)
2506                                 efx_farch_filter_push_tx_limits(efx);
2507                         else
2508                                 efx_farch_filter_push_rx_config(efx);
2509                 }
2510
2511                 efx_writeo(efx, &filter,
2512                            table->offset + table->step * ins_index);
2513
2514                 /* If we were able to replace a filter by inserting
2515                  * at a lower depth, clear the replaced filter
2516                  */
2517                 if (ins_index != rep_index && rep_index >= 0)
2518                         efx_farch_filter_table_clear_entry(efx, table,
2519                                                            rep_index);
2520         }
2521
2522         netif_vdbg(efx, hw, efx->net_dev,
2523                    "%s: filter type %d index %d rxq %u set",
2524                    __func__, spec.type, ins_index, spec.dmaq_id);
2525         rc = efx_farch_filter_make_id(&spec, ins_index);
2526
2527 out_unlock:
2528         up_write(&state->lock);
2529         return rc;
2530 }
2531
2532 static void
2533 efx_farch_filter_table_clear_entry(struct efx_nic *efx,
2534                                    struct efx_farch_filter_table *table,
2535                                    unsigned int filter_idx)
2536 {
2537         static efx_oword_t filter;
2538
2539         EFX_WARN_ON_PARANOID(!test_bit(filter_idx, table->used_bitmap));
2540         BUG_ON(table->offset == 0); /* can't clear MAC default filters */
2541
2542         __clear_bit(filter_idx, table->used_bitmap);
2543         --table->used;
2544         memset(&table->spec[filter_idx], 0, sizeof(table->spec[0]));
2545
2546         efx_writeo(efx, &filter, table->offset + table->step * filter_idx);
2547
2548         /* If this filter required a greater search depth than
2549          * any other, the search limit for its type can now be
2550          * decreased.  However, it is hard to determine that
2551          * unless the table has become completely empty - in
2552          * which case, all its search limits can be set to 0.
2553          */
2554         if (unlikely(table->used == 0)) {
2555                 memset(table->search_limit, 0, sizeof(table->search_limit));
2556                 if (table->id == EFX_FARCH_FILTER_TABLE_TX_MAC)
2557                         efx_farch_filter_push_tx_limits(efx);
2558                 else
2559                         efx_farch_filter_push_rx_config(efx);
2560         }
2561 }
2562
2563 static int efx_farch_filter_remove(struct efx_nic *efx,
2564                                    struct efx_farch_filter_table *table,
2565                                    unsigned int filter_idx,
2566                                    enum efx_filter_priority priority)
2567 {
2568         struct efx_farch_filter_spec *spec = &table->spec[filter_idx];
2569
2570         if (!test_bit(filter_idx, table->used_bitmap) ||
2571             spec->priority != priority)
2572                 return -ENOENT;
2573
2574         if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO) {
2575                 efx_farch_filter_init_rx_auto(efx, spec);
2576                 efx_farch_filter_push_rx_config(efx);
2577         } else {
2578                 efx_farch_filter_table_clear_entry(efx, table, filter_idx);
2579         }
2580
2581         return 0;
2582 }
2583
2584 int efx_farch_filter_remove_safe(struct efx_nic *efx,
2585                                  enum efx_filter_priority priority,
2586                                  u32 filter_id)
2587 {
2588         struct efx_farch_filter_state *state = efx->filter_state;
2589         enum efx_farch_filter_table_id table_id;
2590         struct efx_farch_filter_table *table;
2591         unsigned int filter_idx;
2592         int rc;
2593
2594         table_id = efx_farch_filter_id_table_id(filter_id);
2595         if ((unsigned int)table_id >= EFX_FARCH_FILTER_TABLE_COUNT)
2596                 return -ENOENT;
2597         table = &state->table[table_id];
2598
2599         filter_idx = efx_farch_filter_id_index(filter_id);
2600         if (filter_idx >= table->size)
2601                 return -ENOENT;
2602         down_write(&state->lock);
2603
2604         rc = efx_farch_filter_remove(efx, table, filter_idx, priority);
2605         up_write(&state->lock);
2606
2607         return rc;
2608 }
2609
2610 int efx_farch_filter_get_safe(struct efx_nic *efx,
2611                               enum efx_filter_priority priority,
2612                               u32 filter_id, struct efx_filter_spec *spec_buf)
2613 {
2614         struct efx_farch_filter_state *state = efx->filter_state;
2615         enum efx_farch_filter_table_id table_id;
2616         struct efx_farch_filter_table *table;
2617         struct efx_farch_filter_spec *spec;
2618         unsigned int filter_idx;
2619         int rc = -ENOENT;
2620
2621         down_read(&state->lock);
2622
2623         table_id = efx_farch_filter_id_table_id(filter_id);
2624         if ((unsigned int)table_id >= EFX_FARCH_FILTER_TABLE_COUNT)
2625                 goto out_unlock;
2626         table = &state->table[table_id];
2627
2628         filter_idx = efx_farch_filter_id_index(filter_id);
2629         if (filter_idx >= table->size)
2630                 goto out_unlock;
2631         spec = &table->spec[filter_idx];
2632
2633         if (test_bit(filter_idx, table->used_bitmap) &&
2634             spec->priority == priority) {
2635                 efx_farch_filter_to_gen_spec(spec_buf, spec);
2636                 rc = 0;
2637         }
2638
2639 out_unlock:
2640         up_read(&state->lock);
2641         return rc;
2642 }
2643
2644 static void
2645 efx_farch_filter_table_clear(struct efx_nic *efx,
2646                              enum efx_farch_filter_table_id table_id,
2647                              enum efx_filter_priority priority)
2648 {
2649         struct efx_farch_filter_state *state = efx->filter_state;
2650         struct efx_farch_filter_table *table = &state->table[table_id];
2651         unsigned int filter_idx;
2652
2653         down_write(&state->lock);
2654         for (filter_idx = 0; filter_idx < table->size; ++filter_idx) {
2655                 if (table->spec[filter_idx].priority != EFX_FILTER_PRI_AUTO)
2656                         efx_farch_filter_remove(efx, table,
2657                                                 filter_idx, priority);
2658         }
2659         up_write(&state->lock);
2660 }
2661
2662 int efx_farch_filter_clear_rx(struct efx_nic *efx,
2663                                enum efx_filter_priority priority)
2664 {
2665         efx_farch_filter_table_clear(efx, EFX_FARCH_FILTER_TABLE_RX_IP,
2666                                      priority);
2667         efx_farch_filter_table_clear(efx, EFX_FARCH_FILTER_TABLE_RX_MAC,
2668                                      priority);
2669         efx_farch_filter_table_clear(efx, EFX_FARCH_FILTER_TABLE_RX_DEF,
2670                                      priority);
2671         return 0;
2672 }
2673
2674 u32 efx_farch_filter_count_rx_used(struct efx_nic *efx,
2675                                    enum efx_filter_priority priority)
2676 {
2677         struct efx_farch_filter_state *state = efx->filter_state;
2678         enum efx_farch_filter_table_id table_id;
2679         struct efx_farch_filter_table *table;
2680         unsigned int filter_idx;
2681         u32 count = 0;
2682
2683         down_read(&state->lock);
2684
2685         for (table_id = EFX_FARCH_FILTER_TABLE_RX_IP;
2686              table_id <= EFX_FARCH_FILTER_TABLE_RX_DEF;
2687              table_id++) {
2688                 table = &state->table[table_id];
2689                 for (filter_idx = 0; filter_idx < table->size; filter_idx++) {
2690                         if (test_bit(filter_idx, table->used_bitmap) &&
2691                             table->spec[filter_idx].priority == priority)
2692                                 ++count;
2693                 }
2694         }
2695
2696         up_read(&state->lock);
2697
2698         return count;
2699 }
2700
2701 s32 efx_farch_filter_get_rx_ids(struct efx_nic *efx,
2702                                 enum efx_filter_priority priority,
2703                                 u32 *buf, u32 size)
2704 {
2705         struct efx_farch_filter_state *state = efx->filter_state;
2706         enum efx_farch_filter_table_id table_id;
2707         struct efx_farch_filter_table *table;
2708         unsigned int filter_idx;
2709         s32 count = 0;
2710
2711         down_read(&state->lock);
2712
2713         for (table_id = EFX_FARCH_FILTER_TABLE_RX_IP;
2714              table_id <= EFX_FARCH_FILTER_TABLE_RX_DEF;
2715              table_id++) {
2716                 table = &state->table[table_id];
2717                 for (filter_idx = 0; filter_idx < table->size; filter_idx++) {
2718                         if (test_bit(filter_idx, table->used_bitmap) &&
2719                             table->spec[filter_idx].priority == priority) {
2720                                 if (count == size) {
2721                                         count = -EMSGSIZE;
2722                                         goto out;
2723                                 }
2724                                 buf[count++] = efx_farch_filter_make_id(
2725                                         &table->spec[filter_idx], filter_idx);
2726                         }
2727                 }
2728         }
2729 out:
2730         up_read(&state->lock);
2731
2732         return count;
2733 }
2734
2735 /* Restore filter stater after reset */
2736 void efx_farch_filter_table_restore(struct efx_nic *efx)
2737 {
2738         struct efx_farch_filter_state *state = efx->filter_state;
2739         enum efx_farch_filter_table_id table_id;
2740         struct efx_farch_filter_table *table;
2741         efx_oword_t filter;
2742         unsigned int filter_idx;
2743
2744         down_write(&state->lock);
2745
2746         for (table_id = 0; table_id < EFX_FARCH_FILTER_TABLE_COUNT; table_id++) {
2747                 table = &state->table[table_id];
2748
2749                 /* Check whether this is a regular register table */
2750                 if (table->step == 0)
2751                         continue;
2752
2753                 for (filter_idx = 0; filter_idx < table->size; filter_idx++) {
2754                         if (!test_bit(filter_idx, table->used_bitmap))
2755                                 continue;
2756                         efx_farch_filter_build(&filter, &table->spec[filter_idx]);
2757                         efx_writeo(efx, &filter,
2758                                    table->offset + table->step * filter_idx);
2759                 }
2760         }
2761
2762         efx_farch_filter_push_rx_config(efx);
2763         efx_farch_filter_push_tx_limits(efx);
2764
2765         up_write(&state->lock);
2766 }
2767
2768 void efx_farch_filter_table_remove(struct efx_nic *efx)
2769 {
2770         struct efx_farch_filter_state *state = efx->filter_state;
2771         enum efx_farch_filter_table_id table_id;
2772
2773         for (table_id = 0; table_id < EFX_FARCH_FILTER_TABLE_COUNT; table_id++) {
2774                 kfree(state->table[table_id].used_bitmap);
2775                 vfree(state->table[table_id].spec);
2776         }
2777         kfree(state);
2778 }
2779
2780 int efx_farch_filter_table_probe(struct efx_nic *efx)
2781 {
2782         struct efx_farch_filter_state *state;
2783         struct efx_farch_filter_table *table;
2784         unsigned table_id;
2785
2786         state = kzalloc(sizeof(struct efx_farch_filter_state), GFP_KERNEL);
2787         if (!state)
2788                 return -ENOMEM;
2789         efx->filter_state = state;
2790         init_rwsem(&state->lock);
2791
2792         table = &state->table[EFX_FARCH_FILTER_TABLE_RX_IP];
2793         table->id = EFX_FARCH_FILTER_TABLE_RX_IP;
2794         table->offset = FR_BZ_RX_FILTER_TBL0;
2795         table->size = FR_BZ_RX_FILTER_TBL0_ROWS;
2796         table->step = FR_BZ_RX_FILTER_TBL0_STEP;
2797
2798         table = &state->table[EFX_FARCH_FILTER_TABLE_RX_MAC];
2799         table->id = EFX_FARCH_FILTER_TABLE_RX_MAC;
2800         table->offset = FR_CZ_RX_MAC_FILTER_TBL0;
2801         table->size = FR_CZ_RX_MAC_FILTER_TBL0_ROWS;
2802         table->step = FR_CZ_RX_MAC_FILTER_TBL0_STEP;
2803
2804         table = &state->table[EFX_FARCH_FILTER_TABLE_RX_DEF];
2805         table->id = EFX_FARCH_FILTER_TABLE_RX_DEF;
2806         table->size = EFX_FARCH_FILTER_SIZE_RX_DEF;
2807
2808         table = &state->table[EFX_FARCH_FILTER_TABLE_TX_MAC];
2809         table->id = EFX_FARCH_FILTER_TABLE_TX_MAC;
2810         table->offset = FR_CZ_TX_MAC_FILTER_TBL0;
2811         table->size = FR_CZ_TX_MAC_FILTER_TBL0_ROWS;
2812         table->step = FR_CZ_TX_MAC_FILTER_TBL0_STEP;
2813
2814         for (table_id = 0; table_id < EFX_FARCH_FILTER_TABLE_COUNT; table_id++) {
2815                 table = &state->table[table_id];
2816                 if (table->size == 0)
2817                         continue;
2818                 table->used_bitmap = kcalloc(BITS_TO_LONGS(table->size),
2819                                              sizeof(unsigned long),
2820                                              GFP_KERNEL);
2821                 if (!table->used_bitmap)
2822                         goto fail;
2823                 table->spec = vzalloc(array_size(sizeof(*table->spec),
2824                                                  table->size));
2825                 if (!table->spec)
2826                         goto fail;
2827         }
2828
2829         table = &state->table[EFX_FARCH_FILTER_TABLE_RX_DEF];
2830         if (table->size) {
2831                 /* RX default filters must always exist */
2832                 struct efx_farch_filter_spec *spec;
2833                 unsigned i;
2834
2835                 for (i = 0; i < EFX_FARCH_FILTER_SIZE_RX_DEF; i++) {
2836                         spec = &table->spec[i];
2837                         spec->type = EFX_FARCH_FILTER_UC_DEF + i;
2838                         efx_farch_filter_init_rx_auto(efx, spec);
2839                         __set_bit(i, table->used_bitmap);
2840                 }
2841         }
2842
2843         efx_farch_filter_push_rx_config(efx);
2844
2845         return 0;
2846
2847 fail:
2848         efx_farch_filter_table_remove(efx);
2849         return -ENOMEM;
2850 }
2851
2852 /* Update scatter enable flags for filters pointing to our own RX queues */
2853 void efx_farch_filter_update_rx_scatter(struct efx_nic *efx)
2854 {
2855         struct efx_farch_filter_state *state = efx->filter_state;
2856         enum efx_farch_filter_table_id table_id;
2857         struct efx_farch_filter_table *table;
2858         efx_oword_t filter;
2859         unsigned int filter_idx;
2860
2861         down_write(&state->lock);
2862
2863         for (table_id = EFX_FARCH_FILTER_TABLE_RX_IP;
2864              table_id <= EFX_FARCH_FILTER_TABLE_RX_DEF;
2865              table_id++) {
2866                 table = &state->table[table_id];
2867
2868                 for (filter_idx = 0; filter_idx < table->size; filter_idx++) {
2869                         if (!test_bit(filter_idx, table->used_bitmap) ||
2870                             table->spec[filter_idx].dmaq_id >=
2871                             efx->n_rx_channels)
2872                                 continue;
2873
2874                         if (efx->rx_scatter)
2875                                 table->spec[filter_idx].flags |=
2876                                         EFX_FILTER_FLAG_RX_SCATTER;
2877                         else
2878                                 table->spec[filter_idx].flags &=
2879                                         ~EFX_FILTER_FLAG_RX_SCATTER;
2880
2881                         if (table_id == EFX_FARCH_FILTER_TABLE_RX_DEF)
2882                                 /* Pushed by efx_farch_filter_push_rx_config() */
2883                                 continue;
2884
2885                         efx_farch_filter_build(&filter, &table->spec[filter_idx]);
2886                         efx_writeo(efx, &filter,
2887                                    table->offset + table->step * filter_idx);
2888                 }
2889         }
2890
2891         efx_farch_filter_push_rx_config(efx);
2892
2893         up_write(&state->lock);
2894 }
2895
2896 #ifdef CONFIG_RFS_ACCEL
2897
2898 bool efx_farch_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id,
2899                                      unsigned int index)
2900 {
2901         struct efx_farch_filter_state *state = efx->filter_state;
2902         struct efx_farch_filter_table *table;
2903         bool ret = false, force = false;
2904         u16 arfs_id;
2905
2906         down_write(&state->lock);
2907         spin_lock_bh(&efx->rps_hash_lock);
2908         table = &state->table[EFX_FARCH_FILTER_TABLE_RX_IP];
2909         if (test_bit(index, table->used_bitmap) &&
2910             table->spec[index].priority == EFX_FILTER_PRI_HINT) {
2911                 struct efx_arfs_rule *rule = NULL;
2912                 struct efx_filter_spec spec;
2913
2914                 efx_farch_filter_to_gen_spec(&spec, &table->spec[index]);
2915                 if (!efx->rps_hash_table) {
2916                         /* In the absence of the table, we always returned 0 to
2917                          * ARFS, so use the same to query it.
2918                          */
2919                         arfs_id = 0;
2920                 } else {
2921                         rule = efx_rps_hash_find(efx, &spec);
2922                         if (!rule) {
2923                                 /* ARFS table doesn't know of this filter, remove it */
2924                                 force = true;
2925                         } else {
2926                                 arfs_id = rule->arfs_id;
2927                                 if (!efx_rps_check_rule(rule, index, &force))
2928                                         goto out_unlock;
2929                         }
2930                 }
2931                 if (force || rps_may_expire_flow(efx->net_dev, spec.dmaq_id,
2932                                                  flow_id, arfs_id)) {
2933                         if (rule)
2934                                 rule->filter_id = EFX_ARFS_FILTER_ID_REMOVING;
2935                         efx_rps_hash_del(efx, &spec);
2936                         efx_farch_filter_table_clear_entry(efx, table, index);
2937                         ret = true;
2938                 }
2939         }
2940 out_unlock:
2941         spin_unlock_bh(&efx->rps_hash_lock);
2942         up_write(&state->lock);
2943         return ret;
2944 }
2945
2946 #endif /* CONFIG_RFS_ACCEL */
2947
2948 void efx_farch_filter_sync_rx_mode(struct efx_nic *efx)
2949 {
2950         struct net_device *net_dev = efx->net_dev;
2951         struct netdev_hw_addr *ha;
2952         union efx_multicast_hash *mc_hash = &efx->multicast_hash;
2953         u32 crc;
2954         int bit;
2955
2956         if (!efx_dev_registered(efx))
2957                 return;
2958
2959         netif_addr_lock_bh(net_dev);
2960
2961         efx->unicast_filter = !(net_dev->flags & IFF_PROMISC);
2962
2963         /* Build multicast hash table */
2964         if (net_dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
2965                 memset(mc_hash, 0xff, sizeof(*mc_hash));
2966         } else {
2967                 memset(mc_hash, 0x00, sizeof(*mc_hash));
2968                 netdev_for_each_mc_addr(ha, net_dev) {
2969                         crc = ether_crc_le(ETH_ALEN, ha->addr);
2970                         bit = crc & (EFX_MCAST_HASH_ENTRIES - 1);
2971                         __set_bit_le(bit, mc_hash);
2972                 }
2973
2974                 /* Broadcast packets go through the multicast hash filter.
2975                  * ether_crc_le() of the broadcast address is 0xbe2612ff
2976                  * so we always add bit 0xff to the mask.
2977                  */
2978                 __set_bit_le(0xff, mc_hash);
2979         }
2980
2981         netif_addr_unlock_bh(net_dev);
2982 }