drivers/net/ethernet/sfc/ef10.c

   1 /****************************************************************************
   2  * Driver for Solarflare network controllers and boards
   3  * Copyright 2012-2013 Solarflare Communications Inc.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published
   7  * by the Free Software Foundation, incorporated herein by reference.
   8  */
   9
  10 #include "net_driver.h"
  11 #include "ef10_regs.h"
  12 #include "io.h"
  13 #include "mcdi.h"
  14 #include "mcdi_pcol.h"
  15 #include "nic.h"
  16 #include "workarounds.h"
  17 #include "selftest.h"
  18 #include "ef10_sriov.h"
  19 #include <linux/in.h>
  20 #include <linux/jhash.h>
  21 #include <linux/wait.h>
  22 #include <linux/workqueue.h>
  23
  24 /* Hardware control for EF10 architecture including 'Huntington'. */
  25
  26 #define EFX_EF10_DRVGEN_EV              7
  27 enum {
  28         EFX_EF10_TEST = 1,
  29         EFX_EF10_REFILL,
  30 };
  31
  32 /* The reserved RSS context value */
  33 #define EFX_EF10_RSS_CONTEXT_INVALID    0xffffffff
  34 /* The maximum size of a shared RSS context */
  35 /* TODO: this should really be from the mcdi protocol export */
  36 #define EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE 64UL
  37
  38 /* The filter table(s) are managed by firmware and we have write-only
  39  * access.  When removing filters we must identify them to the
  40  * firmware by a 64-bit handle, but this is too wide for Linux kernel
  41  * interfaces (32-bit for RX NFC, 16-bit for RFS).  Also, we need to
  42  * be able to tell in advance whether a requested insertion will
  43  * replace an existing filter.  Therefore we maintain a software hash
  44  * table, which should be at least as large as the hardware hash
  45  * table.
  46  *
  47  * Huntington has a single 8K filter table shared between all filter
  48  * types and both ports.
  49  */
  50 #define HUNT_FILTER_TBL_ROWS 8192
  51
  52 #define EFX_EF10_FILTER_ID_INVALID 0xffff
  53
  54 #define EFX_EF10_FILTER_DEV_UC_MAX      32
  55 #define EFX_EF10_FILTER_DEV_MC_MAX      256
  56
  57 /* VLAN list entry */
  58 struct efx_ef10_vlan {
  59         struct list_head list;
  60         u16 vid;
  61 };
  62
  63 enum efx_ef10_default_filters {
  64         EFX_EF10_BCAST,
  65         EFX_EF10_UCDEF,
  66         EFX_EF10_MCDEF,
  67         EFX_EF10_VXLAN4_UCDEF,
  68         EFX_EF10_VXLAN4_MCDEF,
  69         EFX_EF10_VXLAN6_UCDEF,
  70         EFX_EF10_VXLAN6_MCDEF,
  71         EFX_EF10_NVGRE4_UCDEF,
  72         EFX_EF10_NVGRE4_MCDEF,
  73         EFX_EF10_NVGRE6_UCDEF,
  74         EFX_EF10_NVGRE6_MCDEF,
  75         EFX_EF10_GENEVE4_UCDEF,
  76         EFX_EF10_GENEVE4_MCDEF,
  77         EFX_EF10_GENEVE6_UCDEF,
  78         EFX_EF10_GENEVE6_MCDEF,
  79
  80         EFX_EF10_NUM_DEFAULT_FILTERS
  81 };
  82
  83 /* Per-VLAN filters information */
  84 struct efx_ef10_filter_vlan {
  85         struct list_head list;
  86         u16 vid;
  87         u16 uc[EFX_EF10_FILTER_DEV_UC_MAX];
  88         u16 mc[EFX_EF10_FILTER_DEV_MC_MAX];
  89         u16 default_filters[EFX_EF10_NUM_DEFAULT_FILTERS];
  90 };
  91
  92 struct efx_ef10_dev_addr {
  93         u8 addr[ETH_ALEN];
  94 };
  95
  96 struct efx_ef10_filter_table {
  97 /* The MCDI match masks supported by this fw & hw, in order of priority */
  98         u32 rx_match_mcdi_flags[
  99                 MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM * 2];
 100         unsigned int rx_match_count;
 101
 102         struct {
 103                 unsigned long spec;     /* pointer to spec plus flag bits */
 104 /* BUSY flag indicates that an update is in progress.  AUTO_OLD is
 105  * used to mark and sweep MAC filters for the device address lists.
 106  */
 107 #define EFX_EF10_FILTER_FLAG_BUSY       1UL
 108 #define EFX_EF10_FILTER_FLAG_AUTO_OLD   2UL
 109 #define EFX_EF10_FILTER_FLAGS           3UL
 110                 u64 handle;             /* firmware handle */
 111         } *entry;
 112         wait_queue_head_t waitq;
 113 /* Shadow of net_device address lists, guarded by mac_lock */
 114         struct efx_ef10_dev_addr dev_uc_list[EFX_EF10_FILTER_DEV_UC_MAX];
 115         struct efx_ef10_dev_addr dev_mc_list[EFX_EF10_FILTER_DEV_MC_MAX];
 116         int dev_uc_count;
 117         int dev_mc_count;
 118         bool uc_promisc;
 119         bool mc_promisc;
 120 /* Whether in multicast promiscuous mode when last changed */
 121         bool mc_promisc_last;
 122         bool mc_overflow; /* Too many MC addrs; should always imply mc_promisc */
 123         bool vlan_filter;
 124         struct list_head vlan_list;
 125 };
 126
 127 /* An arbitrary search limit for the software hash table */
 128 #define EFX_EF10_FILTER_SEARCH_LIMIT 200
 129
 130 static void efx_ef10_rx_free_indir_table(struct efx_nic *efx);
 131 static void efx_ef10_filter_table_remove(struct efx_nic *efx);
 132 static int efx_ef10_filter_add_vlan(struct efx_nic *efx, u16 vid);
 133 static void efx_ef10_filter_del_vlan_internal(struct efx_nic *efx,
 134                                               struct efx_ef10_filter_vlan *vlan);
 135 static void efx_ef10_filter_del_vlan(struct efx_nic *efx, u16 vid);
 136 static int efx_ef10_set_udp_tnl_ports(struct efx_nic *efx, bool unloading);
 137
 138 static u32 efx_ef10_filter_get_unsafe_id(u32 filter_id)
 139 {
 140         WARN_ON_ONCE(filter_id == EFX_EF10_FILTER_ID_INVALID);
 141         return filter_id & (HUNT_FILTER_TBL_ROWS - 1);
 142 }
 143
 144 static unsigned int efx_ef10_filter_get_unsafe_pri(u32 filter_id)
 145 {
 146         return filter_id / (HUNT_FILTER_TBL_ROWS * 2);
 147 }
 148
 149 static u32 efx_ef10_make_filter_id(unsigned int pri, u16 idx)
 150 {
 151         return pri * HUNT_FILTER_TBL_ROWS * 2 + idx;
 152 }
 153
 154 static int efx_ef10_get_warm_boot_count(struct efx_nic *efx)
 155 {
 156         efx_dword_t reg;
 157
 158         efx_readd(efx, &reg, ER_DZ_BIU_MC_SFT_STATUS);
 159         return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ?
 160                 EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO;
 161 }
 162
 163 /* On all EF10s up to and including SFC9220 (Medford1), all PFs use BAR 0 for
 164  * I/O space and BAR 2(&3) for memory.  On SFC9250 (Medford2), there is no I/O
 165  * bar; PFs use BAR 0/1 for memory.
 166  */
 167 static unsigned int efx_ef10_pf_mem_bar(struct efx_nic *efx)
 168 {
 169         switch (efx->pci_dev->device) {
 170         case 0x0b03: /* SFC9250 PF */
 171                 return 0;
 172         default:
 173                 return 2;
 174         }
 175 }
 176
 177 /* All VFs use BAR 0/1 for memory */
 178 static unsigned int efx_ef10_vf_mem_bar(struct efx_nic *efx)
 179 {
 180         return 0;
 181 }
 182
 183 static unsigned int efx_ef10_mem_map_size(struct efx_nic *efx)
 184 {
 185         int bar;
 186
 187         bar = efx->type->mem_bar(efx);
 188         return resource_size(&efx->pci_dev->resource[bar]);
 189 }
 190
 191 static bool efx_ef10_is_vf(struct efx_nic *efx)
 192 {
 193         return efx->type->is_vf;
 194 }
 195
 196 static int efx_ef10_get_pf_index(struct efx_nic *efx)
 197 {
 198         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN);
 199         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 200         size_t outlen;
 201         int rc;
 202
 203         rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf,
 204                           sizeof(outbuf), &outlen);
 205         if (rc)
 206                 return rc;
 207         if (outlen < sizeof(outbuf))
 208                 return -EIO;
 209
 210         nic_data->pf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_PF);
 211         return 0;
 212 }
 213
 214 #ifdef CONFIG_SFC_SRIOV
 215 static int efx_ef10_get_vf_index(struct efx_nic *efx)
 216 {
 217         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN);
 218         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 219         size_t outlen;
 220         int rc;
 221
 222         rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf,
 223                           sizeof(outbuf), &outlen);
 224         if (rc)
 225                 return rc;
 226         if (outlen < sizeof(outbuf))
 227                 return -EIO;
 228
 229         nic_data->vf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_VF);
 230         return 0;
 231 }
 232 #endif
 233
 234 static int efx_ef10_init_datapath_caps(struct efx_nic *efx)
 235 {
 236         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_V4_OUT_LEN);
 237         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 238         size_t outlen;
 239         int rc;
 240
 241         BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0);
 242
 243         rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0,
 244                           outbuf, sizeof(outbuf), &outlen);
 245         if (rc)
 246                 return rc;
 247         if (outlen < MC_CMD_GET_CAPABILITIES_OUT_LEN) {
 248                 netif_err(efx, drv, efx->net_dev,
 249                           "unable to read datapath firmware capabilities\n");
 250                 return -EIO;
 251         }
 252
 253         nic_data->datapath_caps =
 254                 MCDI_DWORD(outbuf, GET_CAPABILITIES_OUT_FLAGS1);
 255
 256         if (outlen >= MC_CMD_GET_CAPABILITIES_V2_OUT_LEN) {
 257                 nic_data->datapath_caps2 = MCDI_DWORD(outbuf,
 258                                 GET_CAPABILITIES_V2_OUT_FLAGS2);
 259                 nic_data->piobuf_size = MCDI_WORD(outbuf,
 260                                 GET_CAPABILITIES_V2_OUT_SIZE_PIO_BUFF);
 261         } else {
 262                 nic_data->datapath_caps2 = 0;
 263                 nic_data->piobuf_size = ER_DZ_TX_PIOBUF_SIZE;
 264         }
 265
 266         /* record the DPCPU firmware IDs to determine VEB vswitching support.
 267          */
 268         nic_data->rx_dpcpu_fw_id =
 269                 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID);
 270         nic_data->tx_dpcpu_fw_id =
 271                 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID);
 272
 273         if (!(nic_data->datapath_caps &
 274               (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN))) {
 275                 netif_err(efx, probe, efx->net_dev,
 276                           "current firmware does not support an RX prefix\n");
 277                 return -ENODEV;
 278         }
 279
 280         if (outlen >= MC_CMD_GET_CAPABILITIES_V3_OUT_LEN) {
 281                 u8 vi_window_mode = MCDI_BYTE(outbuf,
 282                                 GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE);
 283
 284                 switch (vi_window_mode) {
 285                 case MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_8K:
 286                         efx->vi_stride = 8192;
 287                         break;
 288                 case MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_16K:
 289                         efx->vi_stride = 16384;
 290                         break;
 291                 case MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_64K:
 292                         efx->vi_stride = 65536;
 293                         break;
 294                 default:
 295                         netif_err(efx, probe, efx->net_dev,
 296                                   "Unrecognised VI window mode %d\n",
 297                                   vi_window_mode);
 298                         return -EIO;
 299                 }
 300                 netif_dbg(efx, probe, efx->net_dev, "vi_stride = %u\n",
 301                           efx->vi_stride);
 302         } else {
 303                 /* keep default VI stride */
 304                 netif_dbg(efx, probe, efx->net_dev,
 305                           "firmware did not report VI window mode, assuming vi_stride = %u\n",
 306                           efx->vi_stride);
 307         }
 308
 309         if (outlen >= MC_CMD_GET_CAPABILITIES_V4_OUT_LEN) {
 310                 efx->num_mac_stats = MCDI_WORD(outbuf,
 311                                 GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS);
 312                 netif_dbg(efx, probe, efx->net_dev,
 313                           "firmware reports num_mac_stats = %u\n",
 314                           efx->num_mac_stats);
 315         } else {
 316                 /* leave num_mac_stats as the default value, MC_CMD_MAC_NSTATS */
 317                 netif_dbg(efx, probe, efx->net_dev,
 318                           "firmware did not report num_mac_stats, assuming %u\n",
 319                           efx->num_mac_stats);
 320         }
 321
 322         return 0;
 323 }
 324
 325 static void efx_ef10_read_licensed_features(struct efx_nic *efx)
 326 {
 327         MCDI_DECLARE_BUF(inbuf, MC_CMD_LICENSING_V3_IN_LEN);
 328         MCDI_DECLARE_BUF(outbuf, MC_CMD_LICENSING_V3_OUT_LEN);
 329         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 330         size_t outlen;
 331         int rc;
 332
 333         MCDI_SET_DWORD(inbuf, LICENSING_V3_IN_OP,
 334                        MC_CMD_LICENSING_V3_IN_OP_REPORT_LICENSE);
 335         rc = efx_mcdi_rpc_quiet(efx, MC_CMD_LICENSING_V3, inbuf, sizeof(inbuf),
 336                                 outbuf, sizeof(outbuf), &outlen);
 337         if (rc || (outlen < MC_CMD_LICENSING_V3_OUT_LEN))
 338                 return;
 339
 340         nic_data->licensed_features = MCDI_QWORD(outbuf,
 341                                          LICENSING_V3_OUT_LICENSED_FEATURES);
 342 }
 343
 344 static int efx_ef10_get_sysclk_freq(struct efx_nic *efx)
 345 {
 346         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CLOCK_OUT_LEN);
 347         int rc;
 348
 349         rc = efx_mcdi_rpc(efx, MC_CMD_GET_CLOCK, NULL, 0,
 350                           outbuf, sizeof(outbuf), NULL);
 351         if (rc)
 352                 return rc;
 353         rc = MCDI_DWORD(outbuf, GET_CLOCK_OUT_SYS_FREQ);
 354         return rc > 0 ? rc : -ERANGE;
 355 }
 356
 357 static int efx_ef10_get_timer_workarounds(struct efx_nic *efx)
 358 {
 359         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 360         unsigned int implemented;
 361         unsigned int enabled;
 362         int rc;
 363
 364         nic_data->workaround_35388 = false;
 365         nic_data->workaround_61265 = false;
 366
 367         rc = efx_mcdi_get_workarounds(efx, &implemented, &enabled);
 368
 369         if (rc == -ENOSYS) {
 370                 /* Firmware without GET_WORKAROUNDS - not a problem. */
 371                 rc = 0;
 372         } else if (rc == 0) {
 373                 /* Bug61265 workaround is always enabled if implemented. */
 374                 if (enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG61265)
 375                         nic_data->workaround_61265 = true;
 376
 377                 if (enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG35388) {
 378                         nic_data->workaround_35388 = true;
 379                 } else if (implemented & MC_CMD_GET_WORKAROUNDS_OUT_BUG35388) {
 380                         /* Workaround is implemented but not enabled.
 381                          * Try to enable it.
 382                          */
 383                         rc = efx_mcdi_set_workaround(efx,
 384                                                      MC_CMD_WORKAROUND_BUG35388,
 385                                                      true, NULL);
 386                         if (rc == 0)
 387                                 nic_data->workaround_35388 = true;
 388                         /* If we failed to set the workaround just carry on. */
 389                         rc = 0;
 390                 }
 391         }
 392
 393         netif_dbg(efx, probe, efx->net_dev,
 394                   "workaround for bug 35388 is %sabled\n",
 395                   nic_data->workaround_35388 ? "en" : "dis");
 396         netif_dbg(efx, probe, efx->net_dev,
 397                   "workaround for bug 61265 is %sabled\n",
 398                   nic_data->workaround_61265 ? "en" : "dis");
 399
 400         return rc;
 401 }
 402
 403 static void efx_ef10_process_timer_config(struct efx_nic *efx,
 404                                           const efx_dword_t *data)
 405 {
 406         unsigned int max_count;
 407
 408         if (EFX_EF10_WORKAROUND_61265(efx)) {
 409                 efx->timer_quantum_ns = MCDI_DWORD(data,
 410                         GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_STEP_NS);
 411                 efx->timer_max_ns = MCDI_DWORD(data,
 412                         GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_MAX_NS);
 413         } else if (EFX_EF10_WORKAROUND_35388(efx)) {
 414                 efx->timer_quantum_ns = MCDI_DWORD(data,
 415                         GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_NS_PER_COUNT);
 416                 max_count = MCDI_DWORD(data,
 417                         GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_MAX_COUNT);
 418                 efx->timer_max_ns = max_count * efx->timer_quantum_ns;
 419         } else {
 420                 efx->timer_quantum_ns = MCDI_DWORD(data,
 421                         GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_NS_PER_COUNT);
 422                 max_count = MCDI_DWORD(data,
 423                         GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_MAX_COUNT);
 424                 efx->timer_max_ns = max_count * efx->timer_quantum_ns;
 425         }
 426
 427         netif_dbg(efx, probe, efx->net_dev,
 428                   "got timer properties from MC: quantum %u ns; max %u ns\n",
 429                   efx->timer_quantum_ns, efx->timer_max_ns);
 430 }
 431
 432 static int efx_ef10_get_timer_config(struct efx_nic *efx)
 433 {
 434         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN);
 435         int rc;
 436
 437         rc = efx_ef10_get_timer_workarounds(efx);
 438         if (rc)
 439                 return rc;
 440
 441         rc = efx_mcdi_rpc_quiet(efx, MC_CMD_GET_EVQ_TMR_PROPERTIES, NULL, 0,
 442                                 outbuf, sizeof(outbuf), NULL);
 443
 444         if (rc == 0) {
 445                 efx_ef10_process_timer_config(efx, outbuf);
 446         } else if (rc == -ENOSYS || rc == -EPERM) {
 447                 /* Not available - fall back to Huntington defaults. */
 448                 unsigned int quantum;
 449
 450                 rc = efx_ef10_get_sysclk_freq(efx);
 451                 if (rc < 0)
 452                         return rc;
 453
 454                 quantum = 1536000 / rc; /* 1536 cycles */
 455                 efx->timer_quantum_ns = quantum;
 456                 efx->timer_max_ns = efx->type->timer_period_max * quantum;
 457                 rc = 0;
 458         } else {
 459                 efx_mcdi_display_error(efx, MC_CMD_GET_EVQ_TMR_PROPERTIES,
 460                                        MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN,
 461                                        NULL, 0, rc);
 462         }
 463
 464         return rc;
 465 }
 466
 467 static int efx_ef10_get_mac_address_pf(struct efx_nic *efx, u8 *mac_address)
 468 {
 469         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN);
 470         size_t outlen;
 471         int rc;
 472
 473         BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0);
 474
 475         rc = efx_mcdi_rpc(efx, MC_CMD_GET_MAC_ADDRESSES, NULL, 0,
 476                           outbuf, sizeof(outbuf), &outlen);
 477         if (rc)
 478                 return rc;
 479         if (outlen < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN)
 480                 return -EIO;
 481
 482         ether_addr_copy(mac_address,
 483                         MCDI_PTR(outbuf, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE));
 484         return 0;
 485 }
 486
 487 static int efx_ef10_get_mac_address_vf(struct efx_nic *efx, u8 *mac_address)
 488 {
 489         MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN);
 490         MCDI_DECLARE_BUF(outbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX);
 491         size_t outlen;
 492         int num_addrs, rc;
 493
 494         MCDI_SET_DWORD(inbuf, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID,
 495                        EVB_PORT_ID_ASSIGNED);
 496         rc = efx_mcdi_rpc(efx, MC_CMD_VPORT_GET_MAC_ADDRESSES, inbuf,
 497                           sizeof(inbuf), outbuf, sizeof(outbuf), &outlen);
 498
 499         if (rc)
 500                 return rc;
 501         if (outlen < MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN)
 502                 return -EIO;
 503
 504         num_addrs = MCDI_DWORD(outbuf,
 505                                VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT);
 506
 507         WARN_ON(num_addrs != 1);
 508
 509         ether_addr_copy(mac_address,
 510                         MCDI_PTR(outbuf, VPORT_GET_MAC_ADDRESSES_OUT_MACADDR));
 511
 512         return 0;
 513 }
 514
 515 static ssize_t efx_ef10_show_link_control_flag(struct device *dev,
 516                                                struct device_attribute *attr,
 517                                                char *buf)
 518 {
 519         struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
 520
 521         return sprintf(buf, "%d\n",
 522                        ((efx->mcdi->fn_flags) &
 523                         (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL))
 524                        ? 1 : 0);
 525 }
 526
 527 static ssize_t efx_ef10_show_primary_flag(struct device *dev,
 528                                           struct device_attribute *attr,
 529                                           char *buf)
 530 {
 531         struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
 532
 533         return sprintf(buf, "%d\n",
 534                        ((efx->mcdi->fn_flags) &
 535                         (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY))
 536                        ? 1 : 0);
 537 }
 538
 539 static struct efx_ef10_vlan *efx_ef10_find_vlan(struct efx_nic *efx, u16 vid)
 540 {
 541         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 542         struct efx_ef10_vlan *vlan;
 543
 544         WARN_ON(!mutex_is_locked(&nic_data->vlan_lock));
 545
 546         list_for_each_entry(vlan, &nic_data->vlan_list, list) {
 547                 if (vlan->vid == vid)
 548                         return vlan;
 549         }
 550
 551         return NULL;
 552 }
 553
 554 static int efx_ef10_add_vlan(struct efx_nic *efx, u16 vid)
 555 {
 556         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 557         struct efx_ef10_vlan *vlan;
 558         int rc;
 559
 560         mutex_lock(&nic_data->vlan_lock);
 561
 562         vlan = efx_ef10_find_vlan(efx, vid);
 563         if (vlan) {
 564                 /* We add VID 0 on init. 8021q adds it on module init
 565                  * for all interfaces with VLAN filtring feature.
 566                  */
 567                 if (vid == 0)
 568                         goto done_unlock;
 569                 netif_warn(efx, drv, efx->net_dev,
 570                            "VLAN %u already added\n", vid);
 571                 rc = -EALREADY;
 572                 goto fail_exist;
 573         }
 574
 575         rc = -ENOMEM;
 576         vlan = kzalloc(sizeof(*vlan), GFP_KERNEL);
 577         if (!vlan)
 578                 goto fail_alloc;
 579
 580         vlan->vid = vid;
 581
 582         list_add_tail(&vlan->list, &nic_data->vlan_list);
 583
 584         if (efx->filter_state) {
 585                 mutex_lock(&efx->mac_lock);
 586                 down_write(&efx->filter_sem);
 587                 rc = efx_ef10_filter_add_vlan(efx, vlan->vid);
 588                 up_write(&efx->filter_sem);
 589                 mutex_unlock(&efx->mac_lock);
 590                 if (rc)
 591                         goto fail_filter_add_vlan;
 592         }
 593
 594 done_unlock:
 595         mutex_unlock(&nic_data->vlan_lock);
 596         return 0;
 597
 598 fail_filter_add_vlan:
 599         list_del(&vlan->list);
 600         kfree(vlan);
 601 fail_alloc:
 602 fail_exist:
 603         mutex_unlock(&nic_data->vlan_lock);
 604         return rc;
 605 }
 606
 607 static void efx_ef10_del_vlan_internal(struct efx_nic *efx,
 608                                        struct efx_ef10_vlan *vlan)
 609 {
 610         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 611
 612         WARN_ON(!mutex_is_locked(&nic_data->vlan_lock));
 613
 614         if (efx->filter_state) {
 615                 down_write(&efx->filter_sem);
 616                 efx_ef10_filter_del_vlan(efx, vlan->vid);
 617                 up_write(&efx->filter_sem);
 618         }
 619
 620         list_del(&vlan->list);
 621         kfree(vlan);
 622 }
 623
 624 static int efx_ef10_del_vlan(struct efx_nic *efx, u16 vid)
 625 {
 626         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 627         struct efx_ef10_vlan *vlan;
 628         int rc = 0;
 629
 630         /* 8021q removes VID 0 on module unload for all interfaces
 631          * with VLAN filtering feature. We need to keep it to receive
 632          * untagged traffic.
 633          */
 634         if (vid == 0)
 635                 return 0;
 636
 637         mutex_lock(&nic_data->vlan_lock);
 638
 639         vlan = efx_ef10_find_vlan(efx, vid);
 640         if (!vlan) {
 641                 netif_err(efx, drv, efx->net_dev,
 642                           "VLAN %u to be deleted not found\n", vid);
 643                 rc = -ENOENT;
 644         } else {
 645                 efx_ef10_del_vlan_internal(efx, vlan);
 646         }
 647
 648         mutex_unlock(&nic_data->vlan_lock);
 649
 650         return rc;
 651 }
 652
 653 static void efx_ef10_cleanup_vlans(struct efx_nic *efx)
 654 {
 655         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 656         struct efx_ef10_vlan *vlan, *next_vlan;
 657
 658         mutex_lock(&nic_data->vlan_lock);
 659         list_for_each_entry_safe(vlan, next_vlan, &nic_data->vlan_list, list)
 660                 efx_ef10_del_vlan_internal(efx, vlan);
 661         mutex_unlock(&nic_data->vlan_lock);
 662 }
 663
 664 static DEVICE_ATTR(link_control_flag, 0444, efx_ef10_show_link_control_flag,
 665                    NULL);
 666 static DEVICE_ATTR(primary_flag, 0444, efx_ef10_show_primary_flag, NULL);
 667
 668 static int efx_ef10_probe(struct efx_nic *efx)
 669 {
 670         struct efx_ef10_nic_data *nic_data;
 671         int i, rc;
 672
 673         nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
 674         if (!nic_data)
 675                 return -ENOMEM;
 676         efx->nic_data = nic_data;
 677
 678         /* we assume later that we can copy from this buffer in dwords */
 679         BUILD_BUG_ON(MCDI_CTL_SDU_LEN_MAX_V2 % 4);
 680
 681         rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf,
 682                                   8 + MCDI_CTL_SDU_LEN_MAX_V2, GFP_KERNEL);
 683         if (rc)
 684                 goto fail1;
 685
 686         /* Get the MC's warm boot count.  In case it's rebooting right
 687          * now, be prepared to retry.
 688          */
 689         i = 0;
 690         for (;;) {
 691                 rc = efx_ef10_get_warm_boot_count(efx);
 692                 if (rc >= 0)
 693                         break;
 694                 if (++i == 5)
 695                         goto fail2;
 696                 ssleep(1);
 697         }
 698         nic_data->warm_boot_count = rc;
 699
 700         nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
 701
 702         nic_data->vport_id = EVB_PORT_ID_ASSIGNED;
 703
 704         /* In case we're recovering from a crash (kexec), we want to
 705          * cancel any outstanding request by the previous user of this
 706          * function.  We send a special message using the least
 707          * significant bits of the 'high' (doorbell) register.
 708          */
 709         _efx_writed(efx, cpu_to_le32(1), ER_DZ_MC_DB_HWRD);
 710
 711         rc = efx_mcdi_init(efx);
 712         if (rc)
 713                 goto fail2;
 714
 715         mutex_init(&nic_data->udp_tunnels_lock);
 716
 717         /* Reset (most) configuration for this function */
 718         rc = efx_mcdi_reset(efx, RESET_TYPE_ALL);
 719         if (rc)
 720                 goto fail3;
 721
 722         /* Enable event logging */
 723         rc = efx_mcdi_log_ctrl(efx, true, false, 0);
 724         if (rc)
 725                 goto fail3;
 726
 727         rc = device_create_file(&efx->pci_dev->dev,
 728                                 &dev_attr_link_control_flag);
 729         if (rc)
 730                 goto fail3;
 731
 732         rc = device_create_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
 733         if (rc)
 734                 goto fail4;
 735
 736         rc = efx_ef10_get_pf_index(efx);
 737         if (rc)
 738                 goto fail5;
 739
 740         rc = efx_ef10_init_datapath_caps(efx);
 741         if (rc < 0)
 742                 goto fail5;
 743
 744         efx_ef10_read_licensed_features(efx);
 745
 746         /* We can have one VI for each vi_stride-byte region.
 747          * However, until we use TX option descriptors we need two TX queues
 748          * per channel.
 749          */
 750         efx->max_channels = min_t(unsigned int,
 751                                   EFX_MAX_CHANNELS,
 752                                   efx_ef10_mem_map_size(efx) /
 753                                   (efx->vi_stride * EFX_TXQ_TYPES));
 754         efx->max_tx_channels = efx->max_channels;
 755         if (WARN_ON(efx->max_channels == 0)) {
 756                 rc = -EIO;
 757                 goto fail5;
 758         }
 759
 760         efx->rx_packet_len_offset =
 761                 ES_DZ_RX_PREFIX_PKTLEN_OFST - ES_DZ_RX_PREFIX_SIZE;
 762
 763         if (nic_data->datapath_caps &
 764             (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_LBN))
 765                 efx->net_dev->hw_features |= NETIF_F_RXFCS;
 766
 767         rc = efx_mcdi_port_get_number(efx);
 768         if (rc < 0)
 769                 goto fail5;
 770         efx->port_num = rc;
 771
 772         rc = efx->type->get_mac_address(efx, efx->net_dev->perm_addr);
 773         if (rc)
 774                 goto fail5;
 775
 776         rc = efx_ef10_get_timer_config(efx);
 777         if (rc < 0)
 778                 goto fail5;
 779
 780         rc = efx_mcdi_mon_probe(efx);
 781         if (rc && rc != -EPERM)
 782                 goto fail5;
 783
 784         efx_ptp_defer_probe_with_channel(efx);
 785
 786 #ifdef CONFIG_SFC_SRIOV
 787         if ((efx->pci_dev->physfn) && (!efx->pci_dev->is_physfn)) {
 788                 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn;
 789                 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
 790
 791                 efx_pf->type->get_mac_address(efx_pf, nic_data->port_id);
 792         } else
 793 #endif
 794                 ether_addr_copy(nic_data->port_id, efx->net_dev->perm_addr);
 795
 796         INIT_LIST_HEAD(&nic_data->vlan_list);
 797         mutex_init(&nic_data->vlan_lock);
 798
 799         /* Add unspecified VID to support VLAN filtering being disabled */
 800         rc = efx_ef10_add_vlan(efx, EFX_FILTER_VID_UNSPEC);
 801         if (rc)
 802                 goto fail_add_vid_unspec;
 803
 804         /* If VLAN filtering is enabled, we need VID 0 to get untagged
 805          * traffic.  It is added automatically if 8021q module is loaded,
 806          * but we can't rely on it since module may be not loaded.
 807          */
 808         rc = efx_ef10_add_vlan(efx, 0);
 809         if (rc)
 810                 goto fail_add_vid_0;
 811
 812         return 0;
 813
 814 fail_add_vid_0:
 815         efx_ef10_cleanup_vlans(efx);
 816 fail_add_vid_unspec:
 817         mutex_destroy(&nic_data->vlan_lock);
 818         efx_ptp_remove(efx);
 819         efx_mcdi_mon_remove(efx);
 820 fail5:
 821         device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
 822 fail4:
 823         device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag);
 824 fail3:
 825         efx_mcdi_detach(efx);
 826
 827         mutex_lock(&nic_data->udp_tunnels_lock);
 828         memset(nic_data->udp_tunnels, 0, sizeof(nic_data->udp_tunnels));
 829         (void)efx_ef10_set_udp_tnl_ports(efx, true);
 830         mutex_unlock(&nic_data->udp_tunnels_lock);
 831         mutex_destroy(&nic_data->udp_tunnels_lock);
 832
 833         efx_mcdi_fini(efx);
 834 fail2:
 835         efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
 836 fail1:
 837         kfree(nic_data);
 838         efx->nic_data = NULL;
 839         return rc;
 840 }
 841
 842 static int efx_ef10_free_vis(struct efx_nic *efx)
 843 {
 844         MCDI_DECLARE_BUF_ERR(outbuf);
 845         size_t outlen;
 846         int rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FREE_VIS, NULL, 0,
 847                                     outbuf, sizeof(outbuf), &outlen);
 848
 849         /* -EALREADY means nothing to free, so ignore */
 850         if (rc == -EALREADY)
 851                 rc = 0;
 852         if (rc)
 853                 efx_mcdi_display_error(efx, MC_CMD_FREE_VIS, 0, outbuf, outlen,
 854                                        rc);
 855         return rc;
 856 }
 857
 858 #ifdef EFX_USE_PIO
 859
 860 static void efx_ef10_free_piobufs(struct efx_nic *efx)
 861 {
 862         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 863         MCDI_DECLARE_BUF(inbuf, MC_CMD_FREE_PIOBUF_IN_LEN);
 864         unsigned int i;
 865         int rc;
 866
 867         BUILD_BUG_ON(MC_CMD_FREE_PIOBUF_OUT_LEN != 0);
 868
 869         for (i = 0; i < nic_data->n_piobufs; i++) {
 870                 MCDI_SET_DWORD(inbuf, FREE_PIOBUF_IN_PIOBUF_HANDLE,
 871                                nic_data->piobuf_handle[i]);
 872                 rc = efx_mcdi_rpc(efx, MC_CMD_FREE_PIOBUF, inbuf, sizeof(inbuf),
 873                                   NULL, 0, NULL);
 874                 WARN_ON(rc);
 875         }
 876
 877         nic_data->n_piobufs = 0;
 878 }
 879
 880 static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
 881 {
 882         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 883         MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_PIOBUF_OUT_LEN);
 884         unsigned int i;
 885         size_t outlen;
 886         int rc = 0;
 887
 888         BUILD_BUG_ON(MC_CMD_ALLOC_PIOBUF_IN_LEN != 0);
 889
 890         for (i = 0; i < n; i++) {
 891                 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_ALLOC_PIOBUF, NULL, 0,
 892                                         outbuf, sizeof(outbuf), &outlen);
 893                 if (rc) {
 894                         /* Don't display the MC error if we didn't have space
 895                          * for a VF.
 896                          */
 897                         if (!(efx_ef10_is_vf(efx) && rc == -ENOSPC))
 898                                 efx_mcdi_display_error(efx, MC_CMD_ALLOC_PIOBUF,
 899                                                        0, outbuf, outlen, rc);
 900                         break;
 901                 }
 902                 if (outlen < MC_CMD_ALLOC_PIOBUF_OUT_LEN) {
 903                         rc = -EIO;
 904                         break;
 905                 }
 906                 nic_data->piobuf_handle[i] =
 907                         MCDI_DWORD(outbuf, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE);
 908                 netif_dbg(efx, probe, efx->net_dev,
 909                           "allocated PIO buffer %u handle %x\n", i,
 910                           nic_data->piobuf_handle[i]);
 911         }
 912
 913         nic_data->n_piobufs = i;
 914         if (rc)
 915                 efx_ef10_free_piobufs(efx);
 916         return rc;
 917 }
 918
 919 static int efx_ef10_link_piobufs(struct efx_nic *efx)
 920 {
 921         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 922         MCDI_DECLARE_BUF(inbuf, MC_CMD_LINK_PIOBUF_IN_LEN);
 923         struct efx_channel *channel;
 924         struct efx_tx_queue *tx_queue;
 925         unsigned int offset, index;
 926         int rc;
 927
 928         BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_OUT_LEN != 0);
 929         BUILD_BUG_ON(MC_CMD_UNLINK_PIOBUF_OUT_LEN != 0);
 930
 931         /* Link a buffer to each VI in the write-combining mapping */
 932         for (index = 0; index < nic_data->n_piobufs; ++index) {
 933                 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_PIOBUF_HANDLE,
 934                                nic_data->piobuf_handle[index]);
 935                 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_TXQ_INSTANCE,
 936                                nic_data->pio_write_vi_base + index);
 937                 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
 938                                   inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
 939                                   NULL, 0, NULL);
 940                 if (rc) {
 941                         netif_err(efx, drv, efx->net_dev,
 942                                   "failed to link VI %u to PIO buffer %u (%d)\n",
 943                                   nic_data->pio_write_vi_base + index, index,
 944                                   rc);
 945                         goto fail;
 946                 }
 947                 netif_dbg(efx, probe, efx->net_dev,
 948                           "linked VI %u to PIO buffer %u\n",
 949                           nic_data->pio_write_vi_base + index, index);
 950         }
 951
 952         /* Link a buffer to each TX queue */
 953         efx_for_each_channel(channel, efx) {
 954                 efx_for_each_channel_tx_queue(tx_queue, channel) {
 955                         /* We assign the PIO buffers to queues in
 956                          * reverse order to allow for the following
 957                          * special case.
 958                          */
 959                         offset = ((efx->tx_channel_offset + efx->n_tx_channels -
 960                                    tx_queue->channel->channel - 1) *
 961                                   efx_piobuf_size);
 962                         index = offset / nic_data->piobuf_size;
 963                         offset = offset % nic_data->piobuf_size;
 964
 965                         /* When the host page size is 4K, the first
 966                          * host page in the WC mapping may be within
 967                          * the same VI page as the last TX queue.  We
 968                          * can only link one buffer to each VI.
 969                          */
 970                         if (tx_queue->queue == nic_data->pio_write_vi_base) {
 971                                 BUG_ON(index != 0);
 972                                 rc = 0;
 973                         } else {
 974                                 MCDI_SET_DWORD(inbuf,
 975                                                LINK_PIOBUF_IN_PIOBUF_HANDLE,
 976                                                nic_data->piobuf_handle[index]);
 977                                 MCDI_SET_DWORD(inbuf,
 978                                                LINK_PIOBUF_IN_TXQ_INSTANCE,
 979                                                tx_queue->queue);
 980                                 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
 981                                                   inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
 982                                                   NULL, 0, NULL);
 983                         }
 984
 985                         if (rc) {
 986                                 /* This is non-fatal; the TX path just
 987                                  * won't use PIO for this queue
 988                                  */
 989                                 netif_err(efx, drv, efx->net_dev,
 990                                           "failed to link VI %u to PIO buffer %u (%d)\n",
 991                                           tx_queue->queue, index, rc);
 992                                 tx_queue->piobuf = NULL;
 993                         } else {
 994                                 tx_queue->piobuf =
 995                                         nic_data->pio_write_base +
 996                                         index * efx->vi_stride + offset;
 997                                 tx_queue->piobuf_offset = offset;
 998                                 netif_dbg(efx, probe, efx->net_dev,
 999                                           "linked VI %u to PIO buffer %u offset %x addr %p\n",
1000                                           tx_queue->queue, index,
1001                                           tx_queue->piobuf_offset,
1002                                           tx_queue->piobuf);
1003                         }
1004                 }
1005         }
1006
1007         return 0;
1008
1009 fail:
1010         /* inbuf was defined for MC_CMD_LINK_PIOBUF.  We can use the same
1011          * buffer for MC_CMD_UNLINK_PIOBUF because it's shorter.
1012          */
1013         BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_IN_LEN < MC_CMD_UNLINK_PIOBUF_IN_LEN);
1014         while (index--) {
1015                 MCDI_SET_DWORD(inbuf, UNLINK_PIOBUF_IN_TXQ_INSTANCE,
1016                                nic_data->pio_write_vi_base + index);
1017                 efx_mcdi_rpc(efx, MC_CMD_UNLINK_PIOBUF,
1018                              inbuf, MC_CMD_UNLINK_PIOBUF_IN_LEN,
1019                              NULL, 0, NULL);
1020         }
1021         return rc;
1022 }
1023
1024 static void efx_ef10_forget_old_piobufs(struct efx_nic *efx)
1025 {
1026         struct efx_channel *channel;
1027         struct efx_tx_queue *tx_queue;
1028
1029         /* All our existing PIO buffers went away */
1030         efx_for_each_channel(channel, efx)
1031                 efx_for_each_channel_tx_queue(tx_queue, channel)
1032                         tx_queue->piobuf = NULL;
1033 }
1034
1035 #else /* !EFX_USE_PIO */
1036
1037 static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
1038 {
1039         return n == 0 ? 0 : -ENOBUFS;
1040 }
1041
1042 static int efx_ef10_link_piobufs(struct efx_nic *efx)
1043 {
1044         return 0;
1045 }
1046
1047 static void efx_ef10_free_piobufs(struct efx_nic *efx)
1048 {
1049 }
1050
1051 static void efx_ef10_forget_old_piobufs(struct efx_nic *efx)
1052 {
1053 }
1054
1055 #endif /* EFX_USE_PIO */
1056
1057 static void efx_ef10_remove(struct efx_nic *efx)
1058 {
1059         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1060         int rc;
1061
1062 #ifdef CONFIG_SFC_SRIOV
1063         struct efx_ef10_nic_data *nic_data_pf;
1064         struct pci_dev *pci_dev_pf;
1065         struct efx_nic *efx_pf;
1066         struct ef10_vf *vf;
1067
1068         if (efx->pci_dev->is_virtfn) {
1069                 pci_dev_pf = efx->pci_dev->physfn;
1070                 if (pci_dev_pf) {
1071                         efx_pf = pci_get_drvdata(pci_dev_pf);
1072                         nic_data_pf = efx_pf->nic_data;
1073                         vf = nic_data_pf->vf + nic_data->vf_index;
1074                         vf->efx = NULL;
1075                 } else
1076                         netif_info(efx, drv, efx->net_dev,
1077                                    "Could not get the PF id from VF\n");
1078         }
1079 #endif
1080
1081         efx_ef10_cleanup_vlans(efx);
1082         mutex_destroy(&nic_data->vlan_lock);
1083
1084         efx_ptp_remove(efx);
1085
1086         efx_mcdi_mon_remove(efx);
1087
1088         efx_ef10_rx_free_indir_table(efx);
1089
1090         if (nic_data->wc_membase)
1091                 iounmap(nic_data->wc_membase);
1092
1093         rc = efx_ef10_free_vis(efx);
1094         WARN_ON(rc != 0);
1095
1096         if (!nic_data->must_restore_piobufs)
1097                 efx_ef10_free_piobufs(efx);
1098
1099         device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
1100         device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag);
1101
1102         efx_mcdi_detach(efx);
1103
1104         memset(nic_data->udp_tunnels, 0, sizeof(nic_data->udp_tunnels));
1105         mutex_lock(&nic_data->udp_tunnels_lock);
1106         (void)efx_ef10_set_udp_tnl_ports(efx, true);
1107         mutex_unlock(&nic_data->udp_tunnels_lock);
1108
1109         mutex_destroy(&nic_data->udp_tunnels_lock);
1110
1111         efx_mcdi_fini(efx);
1112         efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
1113         kfree(nic_data);
1114 }
1115
1116 static int efx_ef10_probe_pf(struct efx_nic *efx)
1117 {
1118         return efx_ef10_probe(efx);
1119 }
1120
1121 int efx_ef10_vadaptor_query(struct efx_nic *efx, unsigned int port_id,
1122                             u32 *port_flags, u32 *vadaptor_flags,
1123                             unsigned int *vlan_tags)
1124 {
1125         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1126         MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_QUERY_IN_LEN);
1127         MCDI_DECLARE_BUF(outbuf, MC_CMD_VADAPTOR_QUERY_OUT_LEN);
1128         size_t outlen;
1129         int rc;
1130
1131         if (nic_data->datapath_caps &
1132             (1 << MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_LBN)) {
1133                 MCDI_SET_DWORD(inbuf, VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID,
1134                                port_id);
1135
1136                 rc = efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_QUERY, inbuf, sizeof(inbuf),
1137                                   outbuf, sizeof(outbuf), &outlen);
1138                 if (rc)
1139                         return rc;
1140
1141                 if (outlen < sizeof(outbuf)) {
1142                         rc = -EIO;
1143                         return rc;
1144                 }
1145         }
1146
1147         if (port_flags)
1148                 *port_flags = MCDI_DWORD(outbuf, VADAPTOR_QUERY_OUT_PORT_FLAGS);
1149         if (vadaptor_flags)
1150                 *vadaptor_flags =
1151                         MCDI_DWORD(outbuf, VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS);
1152         if (vlan_tags)
1153                 *vlan_tags =
1154                         MCDI_DWORD(outbuf,
1155                                    VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS);
1156
1157         return 0;
1158 }
1159
1160 int efx_ef10_vadaptor_alloc(struct efx_nic *efx, unsigned int port_id)
1161 {
1162         MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_ALLOC_IN_LEN);
1163
1164         MCDI_SET_DWORD(inbuf, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID, port_id);
1165         return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_ALLOC, inbuf, sizeof(inbuf),
1166                             NULL, 0, NULL);
1167 }
1168
1169 int efx_ef10_vadaptor_free(struct efx_nic *efx, unsigned int port_id)
1170 {
1171         MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_FREE_IN_LEN);
1172
1173         MCDI_SET_DWORD(inbuf, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID, port_id);
1174         return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_FREE, inbuf, sizeof(inbuf),
1175                             NULL, 0, NULL);
1176 }
1177
1178 int efx_ef10_vport_add_mac(struct efx_nic *efx,
1179                            unsigned int port_id, u8 *mac)
1180 {
1181         MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN);
1182
1183         MCDI_SET_DWORD(inbuf, VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID, port_id);
1184         ether_addr_copy(MCDI_PTR(inbuf, VPORT_ADD_MAC_ADDRESS_IN_MACADDR), mac);
1185
1186         return efx_mcdi_rpc(efx, MC_CMD_VPORT_ADD_MAC_ADDRESS, inbuf,
1187                             sizeof(inbuf), NULL, 0, NULL);
1188 }
1189
1190 int efx_ef10_vport_del_mac(struct efx_nic *efx,
1191                            unsigned int port_id, u8 *mac)
1192 {
1193         MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN);
1194
1195         MCDI_SET_DWORD(inbuf, VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID, port_id);
1196         ether_addr_copy(MCDI_PTR(inbuf, VPORT_DEL_MAC_ADDRESS_IN_MACADDR), mac);
1197
1198         return efx_mcdi_rpc(efx, MC_CMD_VPORT_DEL_MAC_ADDRESS, inbuf,
1199                             sizeof(inbuf), NULL, 0, NULL);
1200 }
1201
1202 #ifdef CONFIG_SFC_SRIOV
1203 static int efx_ef10_probe_vf(struct efx_nic *efx)
1204 {
1205         int rc;
1206         struct pci_dev *pci_dev_pf;
1207
1208         /* If the parent PF has no VF data structure, it doesn't know about this
1209          * VF so fail probe.  The VF needs to be re-created.  This can happen
1210          * if the PF driver is unloaded while the VF is assigned to a guest.
1211          */
1212         pci_dev_pf = efx->pci_dev->physfn;
1213         if (pci_dev_pf) {
1214                 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
1215                 struct efx_ef10_nic_data *nic_data_pf = efx_pf->nic_data;
1216
1217                 if (!nic_data_pf->vf) {
1218                         netif_info(efx, drv, efx->net_dev,
1219                                    "The VF cannot link to its parent PF; "
1220                                    "please destroy and re-create the VF\n");
1221                         return -EBUSY;
1222                 }
1223         }
1224
1225         rc = efx_ef10_probe(efx);
1226         if (rc)
1227                 return rc;
1228
1229         rc = efx_ef10_get_vf_index(efx);
1230         if (rc)
1231                 goto fail;
1232
1233         if (efx->pci_dev->is_virtfn) {
1234                 if (efx->pci_dev->physfn) {
1235                         struct efx_nic *efx_pf =
1236                                 pci_get_drvdata(efx->pci_dev->physfn);
1237                         struct efx_ef10_nic_data *nic_data_p = efx_pf->nic_data;
1238                         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1239
1240                         nic_data_p->vf[nic_data->vf_index].efx = efx;
1241                         nic_data_p->vf[nic_data->vf_index].pci_dev =
1242                                 efx->pci_dev;
1243                 } else
1244                         netif_info(efx, drv, efx->net_dev,
1245                                    "Could not get the PF id from VF\n");
1246         }
1247
1248         return 0;
1249
1250 fail:
1251         efx_ef10_remove(efx);
1252         return rc;
1253 }
1254 #else
1255 static int efx_ef10_probe_vf(struct efx_nic *efx __attribute__ ((unused)))
1256 {
1257         return 0;
1258 }
1259 #endif
1260
1261 static int efx_ef10_alloc_vis(struct efx_nic *efx,
1262                               unsigned int min_vis, unsigned int max_vis)
1263 {
1264         MCDI_DECLARE_BUF(inbuf, MC_CMD_ALLOC_VIS_IN_LEN);
1265         MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_VIS_OUT_LEN);
1266         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1267         size_t outlen;
1268         int rc;
1269
1270         MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MIN_VI_COUNT, min_vis);
1271         MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MAX_VI_COUNT, max_vis);
1272         rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_VIS, inbuf, sizeof(inbuf),
1273                           outbuf, sizeof(outbuf), &outlen);
1274         if (rc != 0)
1275                 return rc;
1276
1277         if (outlen < MC_CMD_ALLOC_VIS_OUT_LEN)
1278                 return -EIO;
1279
1280         netif_dbg(efx, drv, efx->net_dev, "base VI is A0x%03x\n",
1281                   MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE));
1282
1283         nic_data->vi_base = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE);
1284         nic_data->n_allocated_vis = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_COUNT);
1285         return 0;
1286 }
1287
1288 /* Note that the failure path of this function does not free
1289  * resources, as this will be done by efx_ef10_remove().
1290  */
1291 static int efx_ef10_dimension_resources(struct efx_nic *efx)
1292 {
1293         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1294         unsigned int uc_mem_map_size, wc_mem_map_size;
1295         unsigned int min_vis = max(EFX_TXQ_TYPES,
1296                                    efx_separate_tx_channels ? 2 : 1);
1297         unsigned int channel_vis, pio_write_vi_base, max_vis;
1298         void __iomem *membase;
1299         int rc;
1300
1301         channel_vis = max(efx->n_channels, efx->n_tx_channels * EFX_TXQ_TYPES);
1302
1303 #ifdef EFX_USE_PIO
1304         /* Try to allocate PIO buffers if wanted and if the full
1305          * number of PIO buffers would be sufficient to allocate one
1306          * copy-buffer per TX channel.  Failure is non-fatal, as there
1307          * are only a small number of PIO buffers shared between all
1308          * functions of the controller.
1309          */
1310         if (efx_piobuf_size != 0 &&
1311             nic_data->piobuf_size / efx_piobuf_size * EF10_TX_PIOBUF_COUNT >=
1312             efx->n_tx_channels) {
1313                 unsigned int n_piobufs =
1314                         DIV_ROUND_UP(efx->n_tx_channels,
1315                                      nic_data->piobuf_size / efx_piobuf_size);
1316
1317                 rc = efx_ef10_alloc_piobufs(efx, n_piobufs);
1318                 if (rc == -ENOSPC)
1319                         netif_dbg(efx, probe, efx->net_dev,
1320                                   "out of PIO buffers; cannot allocate more\n");
1321                 else if (rc == -EPERM)
1322                         netif_dbg(efx, probe, efx->net_dev,
1323                                   "not permitted to allocate PIO buffers\n");
1324                 else if (rc)
1325                         netif_err(efx, probe, efx->net_dev,
1326                                   "failed to allocate PIO buffers (%d)\n", rc);
1327                 else
1328                         netif_dbg(efx, probe, efx->net_dev,
1329                                   "allocated %u PIO buffers\n", n_piobufs);
1330         }
1331 #else
1332         nic_data->n_piobufs = 0;
1333 #endif
1334
1335         /* PIO buffers should be mapped with write-combining enabled,
1336          * and we want to make single UC and WC mappings rather than
1337          * several of each (in fact that's the only option if host
1338          * page size is >4K).  So we may allocate some extra VIs just
1339          * for writing PIO buffers through.
1340          *
1341          * The UC mapping contains (channel_vis - 1) complete VIs and the
1342          * first 4K of the next VI.  Then the WC mapping begins with
1343          * the remainder of this last VI.
1344          */
1345         uc_mem_map_size = PAGE_ALIGN((channel_vis - 1) * efx->vi_stride +
1346                                      ER_DZ_TX_PIOBUF);
1347         if (nic_data->n_piobufs) {
1348                 /* pio_write_vi_base rounds down to give the number of complete
1349                  * VIs inside the UC mapping.
1350                  */
1351                 pio_write_vi_base = uc_mem_map_size / efx->vi_stride;
1352                 wc_mem_map_size = (PAGE_ALIGN((pio_write_vi_base +
1353                                                nic_data->n_piobufs) *
1354                                               efx->vi_stride) -
1355                                    uc_mem_map_size);
1356                 max_vis = pio_write_vi_base + nic_data->n_piobufs;
1357         } else {
1358                 pio_write_vi_base = 0;
1359                 wc_mem_map_size = 0;
1360                 max_vis = channel_vis;
1361         }
1362
1363         /* In case the last attached driver failed to free VIs, do it now */
1364         rc = efx_ef10_free_vis(efx);
1365         if (rc != 0)
1366                 return rc;
1367
1368         rc = efx_ef10_alloc_vis(efx, min_vis, max_vis);
1369         if (rc != 0)
1370                 return rc;
1371
1372         if (nic_data->n_allocated_vis < channel_vis) {
1373                 netif_info(efx, drv, efx->net_dev,
1374                            "Could not allocate enough VIs to satisfy RSS"
1375                            " requirements. Performance may not be optimal.\n");
1376                 /* We didn't get the VIs to populate our channels.
1377                  * We could keep what we got but then we'd have more
1378                  * interrupts than we need.
1379                  * Instead calculate new max_channels and restart
1380                  */
1381                 efx->max_channels = nic_data->n_allocated_vis;
1382                 efx->max_tx_channels =
1383                         nic_data->n_allocated_vis / EFX_TXQ_TYPES;
1384
1385                 efx_ef10_free_vis(efx);
1386                 return -EAGAIN;
1387         }
1388
1389         /* If we didn't get enough VIs to map all the PIO buffers, free the
1390          * PIO buffers
1391          */
1392         if (nic_data->n_piobufs &&
1393             nic_data->n_allocated_vis <
1394             pio_write_vi_base + nic_data->n_piobufs) {
1395                 netif_dbg(efx, probe, efx->net_dev,
1396                           "%u VIs are not sufficient to map %u PIO buffers\n",
1397                           nic_data->n_allocated_vis, nic_data->n_piobufs);
1398                 efx_ef10_free_piobufs(efx);
1399         }
1400
1401         /* Shrink the original UC mapping of the memory BAR */
1402         membase = ioremap_nocache(efx->membase_phys, uc_mem_map_size);
1403         if (!membase) {
1404                 netif_err(efx, probe, efx->net_dev,
1405                           "could not shrink memory BAR to %x\n",
1406                           uc_mem_map_size);
1407                 return -ENOMEM;
1408         }
1409         iounmap(efx->membase);
1410         efx->membase = membase;
1411
1412         /* Set up the WC mapping if needed */
1413         if (wc_mem_map_size) {
1414                 nic_data->wc_membase = ioremap_wc(efx->membase_phys +
1415                                                   uc_mem_map_size,
1416                                                   wc_mem_map_size);
1417                 if (!nic_data->wc_membase) {
1418                         netif_err(efx, probe, efx->net_dev,
1419                                   "could not allocate WC mapping of size %x\n",
1420                                   wc_mem_map_size);
1421                         return -ENOMEM;
1422                 }
1423                 nic_data->pio_write_vi_base = pio_write_vi_base;
1424                 nic_data->pio_write_base =
1425                         nic_data->wc_membase +
1426                         (pio_write_vi_base * efx->vi_stride + ER_DZ_TX_PIOBUF -
1427                          uc_mem_map_size);
1428
1429                 rc = efx_ef10_link_piobufs(efx);
1430                 if (rc)
1431                         efx_ef10_free_piobufs(efx);
1432         }
1433
1434         netif_dbg(efx, probe, efx->net_dev,
1435                   "memory BAR at %pa (virtual %p+%x UC, %p+%x WC)\n",
1436                   &efx->membase_phys, efx->membase, uc_mem_map_size,
1437                   nic_data->wc_membase, wc_mem_map_size);
1438
1439         return 0;
1440 }
1441
1442 static int efx_ef10_init_nic(struct efx_nic *efx)
1443 {
1444         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1445         int rc;
1446
1447         if (nic_data->must_check_datapath_caps) {
1448                 rc = efx_ef10_init_datapath_caps(efx);
1449                 if (rc)
1450                         return rc;
1451                 nic_data->must_check_datapath_caps = false;
1452         }
1453
1454         if (nic_data->must_realloc_vis) {
1455                 /* We cannot let the number of VIs change now */
1456                 rc = efx_ef10_alloc_vis(efx, nic_data->n_allocated_vis,
1457                                         nic_data->n_allocated_vis);
1458                 if (rc)
1459                         return rc;
1460                 nic_data->must_realloc_vis = false;
1461         }
1462
1463         if (nic_data->must_restore_piobufs && nic_data->n_piobufs) {
1464                 rc = efx_ef10_alloc_piobufs(efx, nic_data->n_piobufs);
1465                 if (rc == 0) {
1466                         rc = efx_ef10_link_piobufs(efx);
1467                         if (rc)
1468                                 efx_ef10_free_piobufs(efx);
1469                 }
1470
1471                 /* Log an error on failure, but this is non-fatal.
1472                  * Permission errors are less important - we've presumably
1473                  * had the PIO buffer licence removed.
1474                  */
1475                 if (rc == -EPERM)
1476                         netif_dbg(efx, drv, efx->net_dev,
1477                                   "not permitted to restore PIO buffers\n");
1478                 else if (rc)
1479                         netif_err(efx, drv, efx->net_dev,
1480                                   "failed to restore PIO buffers (%d)\n", rc);
1481                 nic_data->must_restore_piobufs = false;
1482         }
1483
1484         /* don't fail init if RSS setup doesn't work */
1485         rc = efx->type->rx_push_rss_config(efx, false, efx->rx_indir_table, NULL);
1486         efx->rss_active = (rc == 0);
1487
1488         return 0;
1489 }
1490
1491 static void efx_ef10_reset_mc_allocations(struct efx_nic *efx)
1492 {
1493         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1494 #ifdef CONFIG_SFC_SRIOV
1495         unsigned int i;
1496 #endif
1497
1498         /* All our allocations have been reset */
1499         nic_data->must_realloc_vis = true;
1500         nic_data->must_restore_filters = true;
1501         nic_data->must_restore_piobufs = true;
1502         efx_ef10_forget_old_piobufs(efx);
1503         nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
1504
1505         /* Driver-created vswitches and vports must be re-created */
1506         nic_data->must_probe_vswitching = true;
1507         nic_data->vport_id = EVB_PORT_ID_ASSIGNED;
1508 #ifdef CONFIG_SFC_SRIOV
1509         if (nic_data->vf)
1510                 for (i = 0; i < efx->vf_count; i++)
1511                         nic_data->vf[i].vport_id = 0;
1512 #endif
1513 }
1514
1515 static enum reset_type efx_ef10_map_reset_reason(enum reset_type reason)
1516 {
1517         if (reason == RESET_TYPE_MC_FAILURE)
1518                 return RESET_TYPE_DATAPATH;
1519
1520         return efx_mcdi_map_reset_reason(reason);
1521 }
1522
1523 static int efx_ef10_map_reset_flags(u32 *flags)
1524 {
1525         enum {
1526                 EF10_RESET_PORT = ((ETH_RESET_MAC | ETH_RESET_PHY) <<
1527                                    ETH_RESET_SHARED_SHIFT),
1528                 EF10_RESET_MC = ((ETH_RESET_DMA | ETH_RESET_FILTER |
1529                                   ETH_RESET_OFFLOAD | ETH_RESET_MAC |
1530                                   ETH_RESET_PHY | ETH_RESET_MGMT) <<
1531                                  ETH_RESET_SHARED_SHIFT)
1532         };
1533
1534         /* We assume for now that our PCI function is permitted to
1535          * reset everything.
1536          */
1537
1538         if ((*flags & EF10_RESET_MC) == EF10_RESET_MC) {
1539                 *flags &= ~EF10_RESET_MC;
1540                 return RESET_TYPE_WORLD;
1541         }
1542
1543         if ((*flags & EF10_RESET_PORT) == EF10_RESET_PORT) {
1544                 *flags &= ~EF10_RESET_PORT;
1545                 return RESET_TYPE_ALL;
1546         }
1547
1548         /* no invisible reset implemented */
1549
1550         return -EINVAL;
1551 }
1552
1553 static int efx_ef10_reset(struct efx_nic *efx, enum reset_type reset_type)
1554 {
1555         int rc = efx_mcdi_reset(efx, reset_type);
1556
1557         /* Unprivileged functions return -EPERM, but need to return success
1558          * here so that the datapath is brought back up.
1559          */
1560         if (reset_type == RESET_TYPE_WORLD && rc == -EPERM)
1561                 rc = 0;
1562
1563         /* If it was a port reset, trigger reallocation of MC resources.
1564          * Note that on an MC reset nothing needs to be done now because we'll
1565          * detect the MC reset later and handle it then.
1566          * For an FLR, we never get an MC reset event, but the MC has reset all
1567          * resources assigned to us, so we have to trigger reallocation now.
1568          */
1569         if ((reset_type == RESET_TYPE_ALL ||
1570              reset_type == RESET_TYPE_MCDI_TIMEOUT) && !rc)
1571                 efx_ef10_reset_mc_allocations(efx);
1572         return rc;
1573 }
1574
1575 #define EF10_DMA_STAT(ext_name, mcdi_name)                      \
1576         [EF10_STAT_ ## ext_name] =                              \
1577         { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
1578 #define EF10_DMA_INVIS_STAT(int_name, mcdi_name)                \
1579         [EF10_STAT_ ## int_name] =                              \
1580         { NULL, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
1581 #define EF10_OTHER_STAT(ext_name)                               \
1582         [EF10_STAT_ ## ext_name] = { #ext_name, 0, 0 }
1583 #define GENERIC_SW_STAT(ext_name)                               \
1584         [GENERIC_STAT_ ## ext_name] = { #ext_name, 0, 0 }
1585
1586 static const struct efx_hw_stat_desc efx_ef10_stat_desc[EF10_STAT_COUNT] = {
1587         EF10_DMA_STAT(port_tx_bytes, TX_BYTES),
1588         EF10_DMA_STAT(port_tx_packets, TX_PKTS),
1589         EF10_DMA_STAT(port_tx_pause, TX_PAUSE_PKTS),
1590         EF10_DMA_STAT(port_tx_control, TX_CONTROL_PKTS),
1591         EF10_DMA_STAT(port_tx_unicast, TX_UNICAST_PKTS),
1592         EF10_DMA_STAT(port_tx_multicast, TX_MULTICAST_PKTS),
1593         EF10_DMA_STAT(port_tx_broadcast, TX_BROADCAST_PKTS),
1594         EF10_DMA_STAT(port_tx_lt64, TX_LT64_PKTS),
1595         EF10_DMA_STAT(port_tx_64, TX_64_PKTS),
1596         EF10_DMA_STAT(port_tx_65_to_127, TX_65_TO_127_PKTS),
1597         EF10_DMA_STAT(port_tx_128_to_255, TX_128_TO_255_PKTS),
1598         EF10_DMA_STAT(port_tx_256_to_511, TX_256_TO_511_PKTS),
1599         EF10_DMA_STAT(port_tx_512_to_1023, TX_512_TO_1023_PKTS),
1600         EF10_DMA_STAT(port_tx_1024_to_15xx, TX_1024_TO_15XX_PKTS),
1601         EF10_DMA_STAT(port_tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS),
1602         EF10_DMA_STAT(port_rx_bytes, RX_BYTES),
1603         EF10_DMA_INVIS_STAT(port_rx_bytes_minus_good_bytes, RX_BAD_BYTES),
1604         EF10_OTHER_STAT(port_rx_good_bytes),
1605         EF10_OTHER_STAT(port_rx_bad_bytes),
1606         EF10_DMA_STAT(port_rx_packets, RX_PKTS),
1607         EF10_DMA_STAT(port_rx_good, RX_GOOD_PKTS),
1608         EF10_DMA_STAT(port_rx_bad, RX_BAD_FCS_PKTS),
1609         EF10_DMA_STAT(port_rx_pause, RX_PAUSE_PKTS),
1610         EF10_DMA_STAT(port_rx_control, RX_CONTROL_PKTS),
1611         EF10_DMA_STAT(port_rx_unicast, RX_UNICAST_PKTS),
1612         EF10_DMA_STAT(port_rx_multicast, RX_MULTICAST_PKTS),
1613         EF10_DMA_STAT(port_rx_broadcast, RX_BROADCAST_PKTS),
1614         EF10_DMA_STAT(port_rx_lt64, RX_UNDERSIZE_PKTS),
1615         EF10_DMA_STAT(port_rx_64, RX_64_PKTS),
1616         EF10_DMA_STAT(port_rx_65_to_127, RX_65_TO_127_PKTS),
1617         EF10_DMA_STAT(port_rx_128_to_255, RX_128_TO_255_PKTS),
1618         EF10_DMA_STAT(port_rx_256_to_511, RX_256_TO_511_PKTS),
1619         EF10_DMA_STAT(port_rx_512_to_1023, RX_512_TO_1023_PKTS),
1620         EF10_DMA_STAT(port_rx_1024_to_15xx, RX_1024_TO_15XX_PKTS),
1621         EF10_DMA_STAT(port_rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS),
1622         EF10_DMA_STAT(port_rx_gtjumbo, RX_GTJUMBO_PKTS),
1623         EF10_DMA_STAT(port_rx_bad_gtjumbo, RX_JABBER_PKTS),
1624         EF10_DMA_STAT(port_rx_overflow, RX_OVERFLOW_PKTS),
1625         EF10_DMA_STAT(port_rx_align_error, RX_ALIGN_ERROR_PKTS),
1626         EF10_DMA_STAT(port_rx_length_error, RX_LENGTH_ERROR_PKTS),
1627         EF10_DMA_STAT(port_rx_nodesc_drops, RX_NODESC_DROPS),
1628         GENERIC_SW_STAT(rx_nodesc_trunc),
1629         GENERIC_SW_STAT(rx_noskb_drops),
1630         EF10_DMA_STAT(port_rx_pm_trunc_bb_overflow, PM_TRUNC_BB_OVERFLOW),
1631         EF10_DMA_STAT(port_rx_pm_discard_bb_overflow, PM_DISCARD_BB_OVERFLOW),
1632         EF10_DMA_STAT(port_rx_pm_trunc_vfifo_full, PM_TRUNC_VFIFO_FULL),
1633         EF10_DMA_STAT(port_rx_pm_discard_vfifo_full, PM_DISCARD_VFIFO_FULL),
1634         EF10_DMA_STAT(port_rx_pm_trunc_qbb, PM_TRUNC_QBB),
1635         EF10_DMA_STAT(port_rx_pm_discard_qbb, PM_DISCARD_QBB),
1636         EF10_DMA_STAT(port_rx_pm_discard_mapping, PM_DISCARD_MAPPING),
1637         EF10_DMA_STAT(port_rx_dp_q_disabled_packets, RXDP_Q_DISABLED_PKTS),
1638         EF10_DMA_STAT(port_rx_dp_di_dropped_packets, RXDP_DI_DROPPED_PKTS),
1639         EF10_DMA_STAT(port_rx_dp_streaming_packets, RXDP_STREAMING_PKTS),
1640         EF10_DMA_STAT(port_rx_dp_hlb_fetch, RXDP_HLB_FETCH_CONDITIONS),
1641         EF10_DMA_STAT(port_rx_dp_hlb_wait, RXDP_HLB_WAIT_CONDITIONS),
1642         EF10_DMA_STAT(rx_unicast, VADAPTER_RX_UNICAST_PACKETS),
1643         EF10_DMA_STAT(rx_unicast_bytes, VADAPTER_RX_UNICAST_BYTES),
1644         EF10_DMA_STAT(rx_multicast, VADAPTER_RX_MULTICAST_PACKETS),
1645         EF10_DMA_STAT(rx_multicast_bytes, VADAPTER_RX_MULTICAST_BYTES),
1646         EF10_DMA_STAT(rx_broadcast, VADAPTER_RX_BROADCAST_PACKETS),
1647         EF10_DMA_STAT(rx_broadcast_bytes, VADAPTER_RX_BROADCAST_BYTES),
1648         EF10_DMA_STAT(rx_bad, VADAPTER_RX_BAD_PACKETS),
1649         EF10_DMA_STAT(rx_bad_bytes, VADAPTER_RX_BAD_BYTES),
1650         EF10_DMA_STAT(rx_overflow, VADAPTER_RX_OVERFLOW),
1651         EF10_DMA_STAT(tx_unicast, VADAPTER_TX_UNICAST_PACKETS),
1652         EF10_DMA_STAT(tx_unicast_bytes, VADAPTER_TX_UNICAST_BYTES),
1653         EF10_DMA_STAT(tx_multicast, VADAPTER_TX_MULTICAST_PACKETS),
1654         EF10_DMA_STAT(tx_multicast_bytes, VADAPTER_TX_MULTICAST_BYTES),
1655         EF10_DMA_STAT(tx_broadcast, VADAPTER_TX_BROADCAST_PACKETS),
1656         EF10_DMA_STAT(tx_broadcast_bytes, VADAPTER_TX_BROADCAST_BYTES),
1657         EF10_DMA_STAT(tx_bad, VADAPTER_TX_BAD_PACKETS),
1658         EF10_DMA_STAT(tx_bad_bytes, VADAPTER_TX_BAD_BYTES),
1659         EF10_DMA_STAT(tx_overflow, VADAPTER_TX_OVERFLOW),
1660         EF10_DMA_STAT(fec_uncorrected_errors, FEC_UNCORRECTED_ERRORS),
1661         EF10_DMA_STAT(fec_corrected_errors, FEC_CORRECTED_ERRORS),
1662         EF10_DMA_STAT(fec_corrected_symbols_lane0, FEC_CORRECTED_SYMBOLS_LANE0),
1663         EF10_DMA_STAT(fec_corrected_symbols_lane1, FEC_CORRECTED_SYMBOLS_LANE1),
1664         EF10_DMA_STAT(fec_corrected_symbols_lane2, FEC_CORRECTED_SYMBOLS_LANE2),
1665         EF10_DMA_STAT(fec_corrected_symbols_lane3, FEC_CORRECTED_SYMBOLS_LANE3),
1666         EF10_DMA_STAT(ctpio_dmabuf_start, CTPIO_DMABUF_START),
1667         EF10_DMA_STAT(ctpio_vi_busy_fallback, CTPIO_VI_BUSY_FALLBACK),
1668         EF10_DMA_STAT(ctpio_long_write_success, CTPIO_LONG_WRITE_SUCCESS),
1669         EF10_DMA_STAT(ctpio_missing_dbell_fail, CTPIO_MISSING_DBELL_FAIL),
1670         EF10_DMA_STAT(ctpio_overflow_fail, CTPIO_OVERFLOW_FAIL),
1671         EF10_DMA_STAT(ctpio_underflow_fail, CTPIO_UNDERFLOW_FAIL),
1672         EF10_DMA_STAT(ctpio_timeout_fail, CTPIO_TIMEOUT_FAIL),
1673         EF10_DMA_STAT(ctpio_noncontig_wr_fail, CTPIO_NONCONTIG_WR_FAIL),
1674         EF10_DMA_STAT(ctpio_frm_clobber_fail, CTPIO_FRM_CLOBBER_FAIL),
1675         EF10_DMA_STAT(ctpio_invalid_wr_fail, CTPIO_INVALID_WR_FAIL),
1676         EF10_DMA_STAT(ctpio_vi_clobber_fallback, CTPIO_VI_CLOBBER_FALLBACK),
1677         EF10_DMA_STAT(ctpio_unqualified_fallback, CTPIO_UNQUALIFIED_FALLBACK),
1678         EF10_DMA_STAT(ctpio_runt_fallback, CTPIO_RUNT_FALLBACK),
1679         EF10_DMA_STAT(ctpio_success, CTPIO_SUCCESS),
1680         EF10_DMA_STAT(ctpio_fallback, CTPIO_FALLBACK),
1681         EF10_DMA_STAT(ctpio_poison, CTPIO_POISON),
1682         EF10_DMA_STAT(ctpio_erase, CTPIO_ERASE),
1683 };
1684
1685 #define HUNT_COMMON_STAT_MASK ((1ULL << EF10_STAT_port_tx_bytes) |      \
1686                                (1ULL << EF10_STAT_port_tx_packets) |    \
1687                                (1ULL << EF10_STAT_port_tx_pause) |      \
1688                                (1ULL << EF10_STAT_port_tx_unicast) |    \
1689                                (1ULL << EF10_STAT_port_tx_multicast) |  \
1690                                (1ULL << EF10_STAT_port_tx_broadcast) |  \
1691                                (1ULL << EF10_STAT_port_rx_bytes) |      \
1692                                (1ULL <<                                 \
1693                                 EF10_STAT_port_rx_bytes_minus_good_bytes) | \
1694                                (1ULL << EF10_STAT_port_rx_good_bytes) | \
1695                                (1ULL << EF10_STAT_port_rx_bad_bytes) |  \
1696                                (1ULL << EF10_STAT_port_rx_packets) |    \
1697                                (1ULL << EF10_STAT_port_rx_good) |       \
1698                                (1ULL << EF10_STAT_port_rx_bad) |        \
1699                                (1ULL << EF10_STAT_port_rx_pause) |      \
1700                                (1ULL << EF10_STAT_port_rx_control) |    \
1701                                (1ULL << EF10_STAT_port_rx_unicast) |    \
1702                                (1ULL << EF10_STAT_port_rx_multicast) |  \
1703                                (1ULL << EF10_STAT_port_rx_broadcast) |  \
1704                                (1ULL << EF10_STAT_port_rx_lt64) |       \
1705                                (1ULL << EF10_STAT_port_rx_64) |         \
1706                                (1ULL << EF10_STAT_port_rx_65_to_127) |  \
1707                                (1ULL << EF10_STAT_port_rx_128_to_255) | \
1708                                (1ULL << EF10_STAT_port_rx_256_to_511) | \
1709                                (1ULL << EF10_STAT_port_rx_512_to_1023) |\
1710                                (1ULL << EF10_STAT_port_rx_1024_to_15xx) |\
1711                                (1ULL << EF10_STAT_port_rx_15xx_to_jumbo) |\
1712                                (1ULL << EF10_STAT_port_rx_gtjumbo) |    \
1713                                (1ULL << EF10_STAT_port_rx_bad_gtjumbo) |\
1714                                (1ULL << EF10_STAT_port_rx_overflow) |   \
1715                                (1ULL << EF10_STAT_port_rx_nodesc_drops) |\
1716                                (1ULL << GENERIC_STAT_rx_nodesc_trunc) | \
1717                                (1ULL << GENERIC_STAT_rx_noskb_drops))
1718
1719 /* On 7000 series NICs, these statistics are only provided by the 10G MAC.
1720  * For a 10G/40G switchable port we do not expose these because they might
1721  * not include all the packets they should.
1722  * On 8000 series NICs these statistics are always provided.
1723  */
1724 #define HUNT_10G_ONLY_STAT_MASK ((1ULL << EF10_STAT_port_tx_control) |  \
1725                                  (1ULL << EF10_STAT_port_tx_lt64) |     \
1726                                  (1ULL << EF10_STAT_port_tx_64) |       \
1727                                  (1ULL << EF10_STAT_port_tx_65_to_127) |\
1728                                  (1ULL << EF10_STAT_port_tx_128_to_255) |\
1729                                  (1ULL << EF10_STAT_port_tx_256_to_511) |\
1730                                  (1ULL << EF10_STAT_port_tx_512_to_1023) |\
1731                                  (1ULL << EF10_STAT_port_tx_1024_to_15xx) |\
1732                                  (1ULL << EF10_STAT_port_tx_15xx_to_jumbo))
1733
1734 /* These statistics are only provided by the 40G MAC.  For a 10G/40G
1735  * switchable port we do expose these because the errors will otherwise
1736  * be silent.
1737  */
1738 #define HUNT_40G_EXTRA_STAT_MASK ((1ULL << EF10_STAT_port_rx_align_error) |\
1739                                   (1ULL << EF10_STAT_port_rx_length_error))
1740
1741 /* These statistics are only provided if the firmware supports the
1742  * capability PM_AND_RXDP_COUNTERS.
1743  */
1744 #define HUNT_PM_AND_RXDP_STAT_MASK (                                    \
1745         (1ULL << EF10_STAT_port_rx_pm_trunc_bb_overflow) |              \
1746         (1ULL << EF10_STAT_port_rx_pm_discard_bb_overflow) |            \
1747         (1ULL << EF10_STAT_port_rx_pm_trunc_vfifo_full) |               \
1748         (1ULL << EF10_STAT_port_rx_pm_discard_vfifo_full) |             \
1749         (1ULL << EF10_STAT_port_rx_pm_trunc_qbb) |                      \
1750         (1ULL << EF10_STAT_port_rx_pm_discard_qbb) |                    \
1751         (1ULL << EF10_STAT_port_rx_pm_discard_mapping) |                \
1752         (1ULL << EF10_STAT_port_rx_dp_q_disabled_packets) |             \
1753         (1ULL << EF10_STAT_port_rx_dp_di_dropped_packets) |             \
1754         (1ULL << EF10_STAT_port_rx_dp_streaming_packets) |              \
1755         (1ULL << EF10_STAT_port_rx_dp_hlb_fetch) |                      \
1756         (1ULL << EF10_STAT_port_rx_dp_hlb_wait))
1757
1758 /* These statistics are only provided if the NIC supports MC_CMD_MAC_STATS_V2,
1759  * indicated by returning a value >= MC_CMD_MAC_NSTATS_V2 in
1760  * MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS.
1761  * These bits are in the second u64 of the raw mask.
1762  */
1763 #define EF10_FEC_STAT_MASK (                                            \
1764         (1ULL << (EF10_STAT_fec_uncorrected_errors - 64)) |             \
1765         (1ULL << (EF10_STAT_fec_corrected_errors - 64)) |               \
1766         (1ULL << (EF10_STAT_fec_corrected_symbols_lane0 - 64)) |        \
1767         (1ULL << (EF10_STAT_fec_corrected_symbols_lane1 - 64)) |        \
1768         (1ULL << (EF10_STAT_fec_corrected_symbols_lane2 - 64)) |        \
1769         (1ULL << (EF10_STAT_fec_corrected_symbols_lane3 - 64)))
1770
1771 /* These statistics are only provided if the NIC supports MC_CMD_MAC_STATS_V3,
1772  * indicated by returning a value >= MC_CMD_MAC_NSTATS_V3 in
1773  * MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS.
1774  * These bits are in the second u64 of the raw mask.
1775  */
1776 #define EF10_CTPIO_STAT_MASK (                                          \
1777         (1ULL << (EF10_STAT_ctpio_dmabuf_start - 64)) |                 \
1778         (1ULL << (EF10_STAT_ctpio_vi_busy_fallback - 64)) |             \
1779         (1ULL << (EF10_STAT_ctpio_long_write_success - 64)) |           \
1780         (1ULL << (EF10_STAT_ctpio_missing_dbell_fail - 64)) |           \
1781         (1ULL << (EF10_STAT_ctpio_overflow_fail - 64)) |                \
1782         (1ULL << (EF10_STAT_ctpio_underflow_fail - 64)) |               \
1783         (1ULL << (EF10_STAT_ctpio_timeout_fail - 64)) |                 \
1784         (1ULL << (EF10_STAT_ctpio_noncontig_wr_fail - 64)) |            \
1785         (1ULL << (EF10_STAT_ctpio_frm_clobber_fail - 64)) |             \
1786         (1ULL << (EF10_STAT_ctpio_invalid_wr_fail - 64)) |              \
1787         (1ULL << (EF10_STAT_ctpio_vi_clobber_fallback - 64)) |          \
1788         (1ULL << (EF10_STAT_ctpio_unqualified_fallback - 64)) |         \
1789         (1ULL << (EF10_STAT_ctpio_runt_fallback - 64)) |                \
1790         (1ULL << (EF10_STAT_ctpio_success - 64)) |                      \
1791         (1ULL << (EF10_STAT_ctpio_fallback - 64)) |                     \
1792         (1ULL << (EF10_STAT_ctpio_poison - 64)) |                       \
1793         (1ULL << (EF10_STAT_ctpio_erase - 64)))
1794
1795 static u64 efx_ef10_raw_stat_mask(struct efx_nic *efx)
1796 {
1797         u64 raw_mask = HUNT_COMMON_STAT_MASK;
1798         u32 port_caps = efx_mcdi_phy_get_caps(efx);
1799         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1800
1801         if (!(efx->mcdi->fn_flags &
1802               1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL))
1803                 return 0;
1804
1805         if (port_caps & (1 << MC_CMD_PHY_CAP_40000FDX_LBN)) {
1806                 raw_mask |= HUNT_40G_EXTRA_STAT_MASK;
1807                 /* 8000 series have everything even at 40G */
1808                 if (nic_data->datapath_caps2 &
1809                     (1 << MC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN))
1810                         raw_mask |= HUNT_10G_ONLY_STAT_MASK;
1811         } else {
1812                 raw_mask |= HUNT_10G_ONLY_STAT_MASK;
1813         }
1814
1815         if (nic_data->datapath_caps &
1816             (1 << MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN))
1817                 raw_mask |= HUNT_PM_AND_RXDP_STAT_MASK;
1818
1819         return raw_mask;
1820 }
1821
1822 static void efx_ef10_get_stat_mask(struct efx_nic *efx, unsigned long *mask)
1823 {
1824         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1825         u64 raw_mask[2];
1826
1827         raw_mask[0] = efx_ef10_raw_stat_mask(efx);
1828
1829         /* Only show vadaptor stats when EVB capability is present */
1830         if (nic_data->datapath_caps &
1831             (1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN)) {
1832                 raw_mask[0] |= ~((1ULL << EF10_STAT_rx_unicast) - 1);
1833                 raw_mask[1] = (1ULL << (EF10_STAT_V1_COUNT - 64)) - 1;
1834         } else {
1835                 raw_mask[1] = 0;
1836         }
1837         /* Only show FEC stats when NIC supports MC_CMD_MAC_STATS_V2 */
1838         if (efx->num_mac_stats >= MC_CMD_MAC_NSTATS_V2)
1839                 raw_mask[1] |= EF10_FEC_STAT_MASK;
1840
1841         /* CTPIO stats appear in V3. Only show them on devices that actually
1842          * support CTPIO. Although this driver doesn't use CTPIO others might,
1843          * and we may be reporting the stats for the underlying port.
1844          */
1845         if (efx->num_mac_stats >= MC_CMD_MAC_NSTATS_V3 &&
1846             (nic_data->datapath_caps2 &
1847              (1 << MC_CMD_GET_CAPABILITIES_V4_OUT_CTPIO_LBN)))
1848                 raw_mask[1] |= EF10_CTPIO_STAT_MASK;
1849
1850 #if BITS_PER_LONG == 64
1851         BUILD_BUG_ON(BITS_TO_LONGS(EF10_STAT_COUNT) != 2);
1852         mask[0] = raw_mask[0];
1853         mask[1] = raw_mask[1];
1854 #else
1855         BUILD_BUG_ON(BITS_TO_LONGS(EF10_STAT_COUNT) != 3);
1856         mask[0] = raw_mask[0] & 0xffffffff;
1857         mask[1] = raw_mask[0] >> 32;
1858         mask[2] = raw_mask[1] & 0xffffffff;
1859 #endif
1860 }
1861
1862 static size_t efx_ef10_describe_stats(struct efx_nic *efx, u8 *names)
1863 {
1864         DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1865
1866         efx_ef10_get_stat_mask(efx, mask);
1867         return efx_nic_describe_stats(efx_ef10_stat_desc, EF10_STAT_COUNT,
1868                                       mask, names);
1869 }
1870
1871 static size_t efx_ef10_update_stats_common(struct efx_nic *efx, u64 *full_stats,
1872                                            struct rtnl_link_stats64 *core_stats)
1873 {
1874         DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1875         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1876         u64 *stats = nic_data->stats;
1877         size_t stats_count = 0, index;
1878
1879         efx_ef10_get_stat_mask(efx, mask);
1880
1881         if (full_stats) {
1882                 for_each_set_bit(index, mask, EF10_STAT_COUNT) {
1883                         if (efx_ef10_stat_desc[index].name) {
1884                                 *full_stats++ = stats[index];
1885                                 ++stats_count;
1886                         }
1887                 }
1888         }
1889
1890         if (!core_stats)
1891                 return stats_count;
1892
1893         if (nic_data->datapath_caps &
1894                         1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN) {
1895                 /* Use vadaptor stats. */
1896                 core_stats->rx_packets = stats[EF10_STAT_rx_unicast] +
1897                                          stats[EF10_STAT_rx_multicast] +
1898                                          stats[EF10_STAT_rx_broadcast];
1899                 core_stats->tx_packets = stats[EF10_STAT_tx_unicast] +
1900                                          stats[EF10_STAT_tx_multicast] +
1901                                          stats[EF10_STAT_tx_broadcast];
1902                 core_stats->rx_bytes = stats[EF10_STAT_rx_unicast_bytes] +
1903                                        stats[EF10_STAT_rx_multicast_bytes] +
1904                                        stats[EF10_STAT_rx_broadcast_bytes];
1905                 core_stats->tx_bytes = stats[EF10_STAT_tx_unicast_bytes] +
1906                                        stats[EF10_STAT_tx_multicast_bytes] +
1907                                        stats[EF10_STAT_tx_broadcast_bytes];
1908                 core_stats->rx_dropped = stats[GENERIC_STAT_rx_nodesc_trunc] +
1909                                          stats[GENERIC_STAT_rx_noskb_drops];
1910                 core_stats->multicast = stats[EF10_STAT_rx_multicast];
1911                 core_stats->rx_crc_errors = stats[EF10_STAT_rx_bad];
1912                 core_stats->rx_fifo_errors = stats[EF10_STAT_rx_overflow];
1913                 core_stats->rx_errors = core_stats->rx_crc_errors;
1914                 core_stats->tx_errors = stats[EF10_STAT_tx_bad];
1915         } else {
1916                 /* Use port stats. */
1917                 core_stats->rx_packets = stats[EF10_STAT_port_rx_packets];
1918                 core_stats->tx_packets = stats[EF10_STAT_port_tx_packets];
1919                 core_stats->rx_bytes = stats[EF10_STAT_port_rx_bytes];
1920                 core_stats->tx_bytes = stats[EF10_STAT_port_tx_bytes];
1921                 core_stats->rx_dropped = stats[EF10_STAT_port_rx_nodesc_drops] +
1922                                          stats[GENERIC_STAT_rx_nodesc_trunc] +
1923                                          stats[GENERIC_STAT_rx_noskb_drops];
1924                 core_stats->multicast = stats[EF10_STAT_port_rx_multicast];
1925                 core_stats->rx_length_errors =
1926                                 stats[EF10_STAT_port_rx_gtjumbo] +
1927                                 stats[EF10_STAT_port_rx_length_error];
1928                 core_stats->rx_crc_errors = stats[EF10_STAT_port_rx_bad];
1929                 core_stats->rx_frame_errors =
1930                                 stats[EF10_STAT_port_rx_align_error];
1931                 core_stats->rx_fifo_errors = stats[EF10_STAT_port_rx_overflow];
1932                 core_stats->rx_errors = (core_stats->rx_length_errors +
1933                                          core_stats->rx_crc_errors +
1934                                          core_stats->rx_frame_errors);
1935         }
1936
1937         return stats_count;
1938 }
1939
1940 static int efx_ef10_try_update_nic_stats_pf(struct efx_nic *efx)
1941 {
1942         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1943         DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1944         __le64 generation_start, generation_end;
1945         u64 *stats = nic_data->stats;
1946         __le64 *dma_stats;
1947
1948         efx_ef10_get_stat_mask(efx, mask);
1949
1950         dma_stats = efx->stats_buffer.addr;
1951
1952         generation_end = dma_stats[efx->num_mac_stats - 1];
1953         if (generation_end == EFX_MC_STATS_GENERATION_INVALID)
1954                 return 0;
1955         rmb();
1956         efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask,
1957                              stats, efx->stats_buffer.addr, false);
1958         rmb();
1959         generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
1960         if (generation_end != generation_start)
1961                 return -EAGAIN;
1962
1963         /* Update derived statistics */
1964         efx_nic_fix_nodesc_drop_stat(efx,
1965                                      &stats[EF10_STAT_port_rx_nodesc_drops]);
1966         stats[EF10_STAT_port_rx_good_bytes] =
1967                 stats[EF10_STAT_port_rx_bytes] -
1968                 stats[EF10_STAT_port_rx_bytes_minus_good_bytes];
1969         efx_update_diff_stat(&stats[EF10_STAT_port_rx_bad_bytes],
1970                              stats[EF10_STAT_port_rx_bytes_minus_good_bytes]);
1971         efx_update_sw_stats(efx, stats);
1972         return 0;
1973 }
1974
1975
1976 static size_t efx_ef10_update_stats_pf(struct efx_nic *efx, u64 *full_stats,
1977                                        struct rtnl_link_stats64 *core_stats)
1978 {
1979         int retry;
1980
1981         /* If we're unlucky enough to read statistics during the DMA, wait
1982          * up to 10ms for it to finish (typically takes <500us)
1983          */
1984         for (retry = 0; retry < 100; ++retry) {
1985                 if (efx_ef10_try_update_nic_stats_pf(efx) == 0)
1986                         break;
1987                 udelay(100);
1988         }
1989
1990         return efx_ef10_update_stats_common(efx, full_stats, core_stats);
1991 }
1992
1993 static int efx_ef10_try_update_nic_stats_vf(struct efx_nic *efx)
1994 {
1995         MCDI_DECLARE_BUF(inbuf, MC_CMD_MAC_STATS_IN_LEN);
1996         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1997         DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1998         __le64 generation_start, generation_end;
1999         u64 *stats = nic_data->stats;
2000         u32 dma_len = efx->num_mac_stats * sizeof(u64);
2001         struct efx_buffer stats_buf;
2002         __le64 *dma_stats;
2003         int rc;
2004
2005         spin_unlock_bh(&efx->stats_lock);
2006
2007         if (in_interrupt()) {
2008                 /* If in atomic context, cannot update stats.  Just update the
2009                  * software stats and return so the caller can continue.
2010                  */
2011                 spin_lock_bh(&efx->stats_lock);
2012                 efx_update_sw_stats(efx, stats);
2013                 return 0;
2014         }
2015
2016         efx_ef10_get_stat_mask(efx, mask);
2017
2018         rc = efx_nic_alloc_buffer(efx, &stats_buf, dma_len, GFP_ATOMIC);
2019         if (rc) {
2020                 spin_lock_bh(&efx->stats_lock);
2021                 return rc;
2022         }
2023
2024         dma_stats = stats_buf.addr;
2025         dma_stats[efx->num_mac_stats - 1] = EFX_MC_STATS_GENERATION_INVALID;
2026
2027         MCDI_SET_QWORD(inbuf, MAC_STATS_IN_DMA_ADDR, stats_buf.dma_addr);
2028         MCDI_POPULATE_DWORD_1(inbuf, MAC_STATS_IN_CMD,
2029                               MAC_STATS_IN_DMA, 1);
2030         MCDI_SET_DWORD(inbuf, MAC_STATS_IN_DMA_LEN, dma_len);
2031         MCDI_SET_DWORD(inbuf, MAC_STATS_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
2032
2033         rc = efx_mcdi_rpc_quiet(efx, MC_CMD_MAC_STATS, inbuf, sizeof(inbuf),
2034                                 NULL, 0, NULL);
2035         spin_lock_bh(&efx->stats_lock);
2036         if (rc) {
2037                 /* Expect ENOENT if DMA queues have not been set up */
2038                 if (rc != -ENOENT || atomic_read(&efx->active_queues))
2039                         efx_mcdi_display_error(efx, MC_CMD_MAC_STATS,
2040                                                sizeof(inbuf), NULL, 0, rc);
2041                 goto out;
2042         }
2043
2044         generation_end = dma_stats[efx->num_mac_stats - 1];
2045         if (generation_end == EFX_MC_STATS_GENERATION_INVALID) {
2046                 WARN_ON_ONCE(1);
2047                 goto out;
2048         }
2049         rmb();
2050         efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask,
2051                              stats, stats_buf.addr, false);
2052         rmb();
2053         generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
2054         if (generation_end != generation_start) {
2055                 rc = -EAGAIN;
2056                 goto out;
2057         }
2058
2059         efx_update_sw_stats(efx, stats);
2060 out:
2061         efx_nic_free_buffer(efx, &stats_buf);
2062         return rc;
2063 }
2064
2065 static size_t efx_ef10_update_stats_vf(struct efx_nic *efx, u64 *full_stats,
2066                                        struct rtnl_link_stats64 *core_stats)
2067 {
2068         if (efx_ef10_try_update_nic_stats_vf(efx))
2069                 return 0;
2070
2071         return efx_ef10_update_stats_common(efx, full_stats, core_stats);
2072 }
2073
2074 static void efx_ef10_push_irq_moderation(struct efx_channel *channel)
2075 {
2076         struct efx_nic *efx = channel->efx;
2077         unsigned int mode, usecs;
2078         efx_dword_t timer_cmd;
2079
2080         if (channel->irq_moderation_us) {
2081                 mode = 3;
2082                 usecs = channel->irq_moderation_us;
2083         } else {
2084                 mode = 0;
2085                 usecs = 0;
2086         }
2087
2088         if (EFX_EF10_WORKAROUND_61265(efx)) {
2089                 MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_EVQ_TMR_IN_LEN);
2090                 unsigned int ns = usecs * 1000;
2091
2092                 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_INSTANCE,
2093                                channel->channel);
2094                 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_LOAD_REQ_NS, ns);
2095                 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_RELOAD_REQ_NS, ns);
2096                 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_MODE, mode);
2097
2098                 efx_mcdi_rpc_async(efx, MC_CMD_SET_EVQ_TMR,
2099                                    inbuf, sizeof(inbuf), 0, NULL, 0);
2100         } else if (EFX_EF10_WORKAROUND_35388(efx)) {
2101                 unsigned int ticks = efx_usecs_to_ticks(efx, usecs);
2102
2103                 EFX_POPULATE_DWORD_3(timer_cmd, ERF_DD_EVQ_IND_TIMER_FLAGS,
2104                                      EFE_DD_EVQ_IND_TIMER_FLAGS,
2105                                      ERF_DD_EVQ_IND_TIMER_MODE, mode,
2106                                      ERF_DD_EVQ_IND_TIMER_VAL, ticks);
2107                 efx_writed_page(efx, &timer_cmd, ER_DD_EVQ_INDIRECT,
2108                                 channel->channel);
2109         } else {
2110                 unsigned int ticks = efx_usecs_to_ticks(efx, usecs);
2111
2112                 EFX_POPULATE_DWORD_3(timer_cmd, ERF_DZ_TC_TIMER_MODE, mode,
2113                                      ERF_DZ_TC_TIMER_VAL, ticks,
2114                                      ERF_FZ_TC_TMR_REL_VAL, ticks);
2115                 efx_writed_page(efx, &timer_cmd, ER_DZ_EVQ_TMR,
2116                                 channel->channel);
2117         }
2118 }
2119
2120 static void efx_ef10_get_wol_vf(struct efx_nic *efx,
2121                                 struct ethtool_wolinfo *wol) {}
2122
2123 static int efx_ef10_set_wol_vf(struct efx_nic *efx, u32 type)
2124 {
2125         return -EOPNOTSUPP;
2126 }
2127
2128 static void efx_ef10_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
2129 {
2130         wol->supported = 0;
2131         wol->wolopts = 0;
2132         memset(&wol->sopass, 0, sizeof(wol->sopass));
2133 }
2134
2135 static int efx_ef10_set_wol(struct efx_nic *efx, u32 type)
2136 {
2137         if (type != 0)
2138                 return -EINVAL;
2139         return 0;
2140 }
2141
2142 static void efx_ef10_mcdi_request(struct efx_nic *efx,
2143                                   const efx_dword_t *hdr, size_t hdr_len,
2144                                   const efx_dword_t *sdu, size_t sdu_len)
2145 {
2146         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2147         u8 *pdu = nic_data->mcdi_buf.addr;
2148
2149         memcpy(pdu, hdr, hdr_len);
2150         memcpy(pdu + hdr_len, sdu, sdu_len);
2151         wmb();
2152
2153         /* The hardware provides 'low' and 'high' (doorbell) registers
2154          * for passing the 64-bit address of an MCDI request to
2155          * firmware.  However the dwords are swapped by firmware.  The
2156          * least significant bits of the doorbell are then 0 for all
2157          * MCDI requests due to alignment.
2158          */
2159         _efx_writed(efx, cpu_to_le32((u64)nic_data->mcdi_buf.dma_addr >> 32),
2160                     ER_DZ_MC_DB_LWRD);
2161         _efx_writed(efx, cpu_to_le32((u32)nic_data->mcdi_buf.dma_addr),
2162                     ER_DZ_MC_DB_HWRD);
2163 }
2164
2165 static bool efx_ef10_mcdi_poll_response(struct efx_nic *efx)
2166 {
2167         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2168         const efx_dword_t hdr = *(const efx_dword_t *)nic_data->mcdi_buf.addr;
2169
2170         rmb();
2171         return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE);
2172 }
2173
2174 static void
2175 efx_ef10_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf,
2176                             size_t offset, size_t outlen)
2177 {
2178         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2179         const u8 *pdu = nic_data->mcdi_buf.addr;
2180
2181         memcpy(outbuf, pdu + offset, outlen);
2182 }
2183
2184 static void efx_ef10_mcdi_reboot_detected(struct efx_nic *efx)
2185 {
2186         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2187
2188         /* All our allocations have been reset */
2189         efx_ef10_reset_mc_allocations(efx);
2190
2191         /* The datapath firmware might have been changed */
2192         nic_data->must_check_datapath_caps = true;
2193
2194         /* MAC statistics have been cleared on the NIC; clear the local
2195          * statistic that we update with efx_update_diff_stat().
2196          */
2197         nic_data->stats[EF10_STAT_port_rx_bad_bytes] = 0;
2198 }
2199
2200 static int efx_ef10_mcdi_poll_reboot(struct efx_nic *efx)
2201 {
2202         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2203         int rc;
2204
2205         rc = efx_ef10_get_warm_boot_count(efx);
2206         if (rc < 0) {
2207                 /* The firmware is presumably in the process of
2208                  * rebooting.  However, we are supposed to report each
2209                  * reboot just once, so we must only do that once we
2210                  * can read and store the updated warm boot count.
2211                  */
2212                 return 0;
2213         }
2214
2215         if (rc == nic_data->warm_boot_count)
2216                 return 0;
2217
2218         nic_data->warm_boot_count = rc;
2219         efx_ef10_mcdi_reboot_detected(efx);
2220
2221         return -EIO;
2222 }
2223
2224 /* Handle an MSI interrupt
2225  *
2226  * Handle an MSI hardware interrupt.  This routine schedules event
2227  * queue processing.  No interrupt acknowledgement cycle is necessary.
2228  * Also, we never need to check that the interrupt is for us, since
2229  * MSI interrupts cannot be shared.
2230  */
2231 static irqreturn_t efx_ef10_msi_interrupt(int irq, void *dev_id)
2232 {
2233         struct efx_msi_context *context = dev_id;
2234         struct efx_nic *efx = context->efx;
2235
2236         netif_vdbg(efx, intr, efx->net_dev,
2237                    "IRQ %d on CPU %d\n", irq, raw_smp_processor_id());
2238
2239         if (likely(READ_ONCE(efx->irq_soft_enabled))) {
2240                 /* Note test interrupts */
2241                 if (context->index == efx->irq_level)
2242                         efx->last_irq_cpu = raw_smp_processor_id();
2243
2244                 /* Schedule processing of the channel */
2245                 efx_schedule_channel_irq(efx->channel[context->index]);
2246         }
2247
2248         return IRQ_HANDLED;
2249 }
2250
2251 static irqreturn_t efx_ef10_legacy_interrupt(int irq, void *dev_id)
2252 {
2253         struct efx_nic *efx = dev_id;
2254         bool soft_enabled = READ_ONCE(efx->irq_soft_enabled);
2255         struct efx_channel *channel;
2256         efx_dword_t reg;
2257         u32 queues;
2258
2259         /* Read the ISR which also ACKs the interrupts */
2260         efx_readd(efx, &reg, ER_DZ_BIU_INT_ISR);
2261         queues = EFX_DWORD_FIELD(reg, ERF_DZ_ISR_REG);
2262
2263         if (queues == 0)
2264                 return IRQ_NONE;
2265
2266         if (likely(soft_enabled)) {
2267                 /* Note test interrupts */
2268                 if (queues & (1U << efx->irq_level))
2269                         efx->last_irq_cpu = raw_smp_processor_id();
2270
2271                 efx_for_each_channel(channel, efx) {
2272                         if (queues & 1)
2273                                 efx_schedule_channel_irq(channel);
2274                         queues >>= 1;
2275                 }
2276         }
2277
2278         netif_vdbg(efx, intr, efx->net_dev,
2279                    "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
2280                    irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
2281
2282         return IRQ_HANDLED;
2283 }
2284
2285 static int efx_ef10_irq_test_generate(struct efx_nic *efx)
2286 {
2287         MCDI_DECLARE_BUF(inbuf, MC_CMD_TRIGGER_INTERRUPT_IN_LEN);
2288
2289         if (efx_mcdi_set_workaround(efx, MC_CMD_WORKAROUND_BUG41750, true,
2290                                     NULL) == 0)
2291                 return -ENOTSUPP;
2292
2293         BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN != 0);
2294
2295         MCDI_SET_DWORD(inbuf, TRIGGER_INTERRUPT_IN_INTR_LEVEL, efx->irq_level);
2296         return efx_mcdi_rpc(efx, MC_CMD_TRIGGER_INTERRUPT,
2297                             inbuf, sizeof(inbuf), NULL, 0, NULL);
2298 }
2299
2300 static int efx_ef10_tx_probe(struct efx_tx_queue *tx_queue)
2301 {
2302         return efx_nic_alloc_buffer(tx_queue->efx, &tx_queue->txd.buf,
2303                                     (tx_queue->ptr_mask + 1) *
2304                                     sizeof(efx_qword_t),
2305                                     GFP_KERNEL);
2306 }
2307
2308 /* This writes to the TX_DESC_WPTR and also pushes data */
2309 static inline void efx_ef10_push_tx_desc(struct efx_tx_queue *tx_queue,
2310                                          const efx_qword_t *txd)
2311 {
2312         unsigned int write_ptr;
2313         efx_oword_t reg;
2314
2315         write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
2316         EFX_POPULATE_OWORD_1(reg, ERF_DZ_TX_DESC_WPTR, write_ptr);
2317         reg.qword[0] = *txd;
2318         efx_writeo_page(tx_queue->efx, &reg,
2319                         ER_DZ_TX_DESC_UPD, tx_queue->queue);
2320 }
2321
2322 /* Add Firmware-Assisted TSO v2 option descriptors to a queue.
2323  */
2324 static int efx_ef10_tx_tso_desc(struct efx_tx_queue *tx_queue,
2325                                 struct sk_buff *skb,
2326                                 bool *data_mapped)
2327 {
2328         struct efx_tx_buffer *buffer;
2329         struct tcphdr *tcp;
2330         struct iphdr *ip;
2331
2332         u16 ipv4_id;
2333         u32 seqnum;
2334         u32 mss;
2335
2336         EFX_WARN_ON_ONCE_PARANOID(tx_queue->tso_version != 2);
2337
2338         mss = skb_shinfo(skb)->gso_size;
2339
2340         if (unlikely(mss < 4)) {
2341                 WARN_ONCE(1, "MSS of %u is too small for TSO v2\n", mss);
2342                 return -EINVAL;
2343         }
2344
2345         ip = ip_hdr(skb);
2346         if (ip->version == 4) {
2347                 /* Modify IPv4 header if needed. */
2348                 ip->tot_len = 0;
2349                 ip->check = 0;
2350                 ipv4_id = ntohs(ip->id);
2351         } else {
2352                 /* Modify IPv6 header if needed. */
2353                 struct ipv6hdr *ipv6 = ipv6_hdr(skb);
2354
2355                 ipv6->payload_len = 0;
2356                 ipv4_id = 0;
2357         }
2358
2359         tcp = tcp_hdr(skb);
2360         seqnum = ntohl(tcp->seq);
2361
2362         buffer = efx_tx_queue_get_insert_buffer(tx_queue);
2363
2364         buffer->flags = EFX_TX_BUF_OPTION;
2365         buffer->len = 0;
2366         buffer->unmap_len = 0;
2367         EFX_POPULATE_QWORD_5(buffer->option,
2368                         ESF_DZ_TX_DESC_IS_OPT, 1,
2369                         ESF_DZ_TX_OPTION_TYPE, ESE_DZ_TX_OPTION_DESC_TSO,
2370                         ESF_DZ_TX_TSO_OPTION_TYPE,
2371                         ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A,
2372                         ESF_DZ_TX_TSO_IP_ID, ipv4_id,
2373                         ESF_DZ_TX_TSO_TCP_SEQNO, seqnum
2374                         );
2375         ++tx_queue->insert_count;
2376
2377         buffer = efx_tx_queue_get_insert_buffer(tx_queue);
2378
2379         buffer->flags = EFX_TX_BUF_OPTION;
2380         buffer->len = 0;
2381         buffer->unmap_len = 0;
2382         EFX_POPULATE_QWORD_4(buffer->option,
2383                         ESF_DZ_TX_DESC_IS_OPT, 1,
2384                         ESF_DZ_TX_OPTION_TYPE, ESE_DZ_TX_OPTION_DESC_TSO,
2385                         ESF_DZ_TX_TSO_OPTION_TYPE,
2386                         ESE_DZ_TX_TSO_OPTION_DESC_FATSO2B,
2387                         ESF_DZ_TX_TSO_TCP_MSS, mss
2388                         );
2389         ++tx_queue->insert_count;
2390
2391         return 0;
2392 }
2393
2394 static u32 efx_ef10_tso_versions(struct efx_nic *efx)
2395 {
2396         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2397         u32 tso_versions = 0;
2398
2399         if (nic_data->datapath_caps &
2400             (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN))
2401                 tso_versions |= BIT(1);
2402         if (nic_data->datapath_caps2 &
2403             (1 << MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_LBN))
2404                 tso_versions |= BIT(2);
2405         return tso_versions;
2406 }
2407
2408 static void efx_ef10_tx_init(struct efx_tx_queue *tx_queue)
2409 {
2410         MCDI_DECLARE_BUF(inbuf, MC_CMD_INIT_TXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
2411                                                        EFX_BUF_SIZE));
2412         bool csum_offload = tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD;
2413         size_t entries = tx_queue->txd.buf.len / EFX_BUF_SIZE;
2414         struct efx_channel *channel = tx_queue->channel;
2415         struct efx_nic *efx = tx_queue->efx;
2416         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2417         bool tso_v2 = false;
2418         size_t inlen;
2419         dma_addr_t dma_addr;
2420         efx_qword_t *txd;
2421         int rc;
2422         int i;
2423         BUILD_BUG_ON(MC_CMD_INIT_TXQ_OUT_LEN != 0);
2424
2425         /* Only attempt to enable TX timestamping if we have the license for it,
2426          * otherwise TXQ init will fail
2427          */
2428         if (!(nic_data->licensed_features &
2429               (1 << LICENSED_V3_FEATURES_TX_TIMESTAMPS_LBN)))
2430                 tx_queue->timestamping = false;
2431
2432         /* TSOv2 is a limited resource that can only be configured on a limited
2433          * number of queues. TSO without checksum offload is not really a thing,
2434          * so we only enable it for those queues.
2435          * TSOv2 cannot be used with Hardware timestamping.
2436          */
2437         if (csum_offload && (nic_data->datapath_caps2 &
2438                         (1 << MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_LBN)) &&
2439             !tx_queue->timestamping) {
2440                 tso_v2 = true;
2441                 netif_dbg(efx, hw, efx->net_dev, "Using TSOv2 for channel %u\n",
2442                                 channel->channel);
2443         }
2444
2445         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_SIZE, tx_queue->ptr_mask + 1);
2446         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_TARGET_EVQ, channel->channel);
2447         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_LABEL, tx_queue->queue);
2448         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_INSTANCE, tx_queue->queue);
2449         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_OWNER_ID, 0);
2450         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_PORT_ID, nic_data->vport_id);
2451
2452         dma_addr = tx_queue->txd.buf.dma_addr;
2453
2454         netif_dbg(efx, hw, efx->net_dev, "pushing TXQ %d. %zu entries (%llx)\n",
2455                   tx_queue->queue, entries, (u64)dma_addr);
2456
2457         for (i = 0; i < entries; ++i) {
2458                 MCDI_SET_ARRAY_QWORD(inbuf, INIT_TXQ_IN_DMA_ADDR, i, dma_addr);
2459                 dma_addr += EFX_BUF_SIZE;
2460         }
2461
2462         inlen = MC_CMD_INIT_TXQ_IN_LEN(entries);
2463
2464         do {
2465                 MCDI_POPULATE_DWORD_4(inbuf, INIT_TXQ_IN_FLAGS,
2466                                 /* This flag was removed from mcdi_pcol.h for
2467                                  * the non-_EXT version of INIT_TXQ.  However,
2468                                  * firmware still honours it.
2469                                  */
2470                                 INIT_TXQ_EXT_IN_FLAG_TSOV2_EN, tso_v2,
2471                                 INIT_TXQ_IN_FLAG_IP_CSUM_DIS, !csum_offload,
2472                                 INIT_TXQ_IN_FLAG_TCP_CSUM_DIS, !csum_offload,
2473                                 INIT_TXQ_EXT_IN_FLAG_TIMESTAMP,
2474                                                 tx_queue->timestamping);
2475
2476                 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_INIT_TXQ, inbuf, inlen,
2477                                         NULL, 0, NULL);
2478                 if (rc == -ENOSPC && tso_v2) {
2479                         /* Retry without TSOv2 if we're short on contexts. */
2480                         tso_v2 = false;
2481                         netif_warn(efx, probe, efx->net_dev,
2482                                    "TSOv2 context not available to segment in hardware. TCP performance may be reduced.\n");
2483                 } else if (rc) {
2484                         efx_mcdi_display_error(efx, MC_CMD_INIT_TXQ,
2485                                                MC_CMD_INIT_TXQ_EXT_IN_LEN,
2486                                                NULL, 0, rc);
2487                         goto fail;
2488                 }
2489         } while (rc);
2490
2491         /* A previous user of this TX queue might have set us up the
2492          * bomb by writing a descriptor to the TX push collector but
2493          * not the doorbell.  (Each collector belongs to a port, not a
2494          * queue or function, so cannot easily be reset.)  We must
2495          * attempt to push a no-op descriptor in its place.
2496          */
2497         tx_queue->buffer[0].flags = EFX_TX_BUF_OPTION;
2498         tx_queue->insert_count = 1;
2499         txd = efx_tx_desc(tx_queue, 0);
2500         EFX_POPULATE_QWORD_5(*txd,
2501                              ESF_DZ_TX_DESC_IS_OPT, true,
2502                              ESF_DZ_TX_OPTION_TYPE,
2503                              ESE_DZ_TX_OPTION_DESC_CRC_CSUM,
2504                              ESF_DZ_TX_OPTION_UDP_TCP_CSUM, csum_offload,
2505                              ESF_DZ_TX_OPTION_IP_CSUM, csum_offload,
2506                              ESF_DZ_TX_TIMESTAMP, tx_queue->timestamping);
2507         tx_queue->write_count = 1;
2508
2509         if (tso_v2) {
2510                 tx_queue->handle_tso = efx_ef10_tx_tso_desc;
2511                 tx_queue->tso_version = 2;
2512         } else if (nic_data->datapath_caps &
2513                         (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN)) {
2514                 tx_queue->tso_version = 1;
2515         }
2516
2517         wmb();
2518         efx_ef10_push_tx_desc(tx_queue, txd);
2519
2520         return;
2521
2522 fail:
2523         netdev_WARN(efx->net_dev, "failed to initialise TXQ %d\n",
2524                     tx_queue->queue);
2525 }
2526
2527 static void efx_ef10_tx_fini(struct efx_tx_queue *tx_queue)
2528 {
2529         MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_TXQ_IN_LEN);
2530         MCDI_DECLARE_BUF_ERR(outbuf);
2531         struct efx_nic *efx = tx_queue->efx;
2532         size_t outlen;
2533         int rc;
2534
2535         MCDI_SET_DWORD(inbuf, FINI_TXQ_IN_INSTANCE,
2536                        tx_queue->queue);
2537
2538         rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_TXQ, inbuf, sizeof(inbuf),
2539                           outbuf, sizeof(outbuf), &outlen);
2540
2541         if (rc && rc != -EALREADY)
2542                 goto fail;
2543
2544         return;
2545
2546 fail:
2547         efx_mcdi_display_error(efx, MC_CMD_FINI_TXQ, MC_CMD_FINI_TXQ_IN_LEN,
2548                                outbuf, outlen, rc);
2549 }
2550
2551 static void efx_ef10_tx_remove(struct efx_tx_queue *tx_queue)
2552 {
2553         efx_nic_free_buffer(tx_queue->efx, &tx_queue->txd.buf);
2554 }
2555
2556 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
2557 static inline void efx_ef10_notify_tx_desc(struct efx_tx_queue *tx_queue)
2558 {
2559         unsigned int write_ptr;
2560         efx_dword_t reg;
2561
2562         write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
2563         EFX_POPULATE_DWORD_1(reg, ERF_DZ_TX_DESC_WPTR_DWORD, write_ptr);
2564         efx_writed_page(tx_queue->efx, &reg,
2565                         ER_DZ_TX_DESC_UPD_DWORD, tx_queue->queue);
2566 }
2567
2568 #define EFX_EF10_MAX_TX_DESCRIPTOR_LEN 0x3fff
2569
2570 static unsigned int efx_ef10_tx_limit_len(struct efx_tx_queue *tx_queue,
2571                                           dma_addr_t dma_addr, unsigned int len)
2572 {
2573         if (len > EFX_EF10_MAX_TX_DESCRIPTOR_LEN) {
2574                 /* If we need to break across multiple descriptors we should
2575                  * stop at a page boundary. This assumes the length limit is
2576                  * greater than the page size.
2577                  */
2578                 dma_addr_t end = dma_addr + EFX_EF10_MAX_TX_DESCRIPTOR_LEN;
2579
2580                 BUILD_BUG_ON(EFX_EF10_MAX_TX_DESCRIPTOR_LEN < EFX_PAGE_SIZE);
2581                 len = (end & (~(EFX_PAGE_SIZE - 1))) - dma_addr;
2582         }
2583
2584         return len;
2585 }
2586
2587 static void efx_ef10_tx_write(struct efx_tx_queue *tx_queue)
2588 {
2589         unsigned int old_write_count = tx_queue->write_count;
2590         struct efx_tx_buffer *buffer;
2591         unsigned int write_ptr;
2592         efx_qword_t *txd;
2593
2594         tx_queue->xmit_more_available = false;
2595         if (unlikely(tx_queue->write_count == tx_queue->insert_count))
2596                 return;
2597
2598         do {
2599                 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
2600                 buffer = &tx_queue->buffer[write_ptr];
2601                 txd = efx_tx_desc(tx_queue, write_ptr);
2602                 ++tx_queue->write_count;
2603
2604                 /* Create TX descriptor ring entry */
2605                 if (buffer->flags & EFX_TX_BUF_OPTION) {
2606                         *txd = buffer->option;
2607                         if (EFX_QWORD_FIELD(*txd, ESF_DZ_TX_OPTION_TYPE) == 1)
2608                                 /* PIO descriptor */
2609                                 tx_queue->packet_write_count = tx_queue->write_count;
2610                 } else {
2611                         tx_queue->packet_write_count = tx_queue->write_count;
2612                         BUILD_BUG_ON(EFX_TX_BUF_CONT != 1);
2613                         EFX_POPULATE_QWORD_3(
2614                                 *txd,
2615                                 ESF_DZ_TX_KER_CONT,
2616                                 buffer->flags & EFX_TX_BUF_CONT,
2617                                 ESF_DZ_TX_KER_BYTE_CNT, buffer->len,
2618                                 ESF_DZ_TX_KER_BUF_ADDR, buffer->dma_addr);
2619                 }
2620         } while (tx_queue->write_count != tx_queue->insert_count);
2621
2622         wmb(); /* Ensure descriptors are written before they are fetched */
2623
2624         if (efx_nic_may_push_tx_desc(tx_queue, old_write_count)) {
2625                 txd = efx_tx_desc(tx_queue,
2626                                   old_write_count & tx_queue->ptr_mask);
2627                 efx_ef10_push_tx_desc(tx_queue, txd);
2628                 ++tx_queue->pushes;
2629         } else {
2630                 efx_ef10_notify_tx_desc(tx_queue);
2631         }
2632 }
2633
2634 #define RSS_MODE_HASH_ADDRS     (1 << RSS_MODE_HASH_SRC_ADDR_LBN |\
2635                                  1 << RSS_MODE_HASH_DST_ADDR_LBN)
2636 #define RSS_MODE_HASH_PORTS     (1 << RSS_MODE_HASH_SRC_PORT_LBN |\
2637                                  1 << RSS_MODE_HASH_DST_PORT_LBN)
2638 #define RSS_CONTEXT_FLAGS_DEFAULT       (1 << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_LBN |\
2639                                          1 << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_LBN |\
2640                                          1 << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_LBN |\
2641                                          1 << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_LBN |\
2642                                          (RSS_MODE_HASH_ADDRS | RSS_MODE_HASH_PORTS) << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_LBN |\
2643                                          RSS_MODE_HASH_ADDRS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_LBN |\
2644                                          RSS_MODE_HASH_ADDRS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_LBN |\
2645                                          (RSS_MODE_HASH_ADDRS | RSS_MODE_HASH_PORTS) << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_LBN |\
2646                                          RSS_MODE_HASH_ADDRS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_LBN |\
2647                                          RSS_MODE_HASH_ADDRS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_LBN)
2648
2649 static int efx_ef10_get_rss_flags(struct efx_nic *efx, u32 context, u32 *flags)
2650 {
2651         /* Firmware had a bug (sfc bug 61952) where it would not actually
2652          * fill in the flags field in the response to MC_CMD_RSS_CONTEXT_GET_FLAGS.
2653          * This meant that it would always contain whatever was previously
2654          * in the MCDI buffer.  Fortunately, all firmware versions with
2655          * this bug have the same default flags value for a newly-allocated
2656          * RSS context, and the only time we want to get the flags is just
2657          * after allocating.  Moreover, the response has a 32-bit hole
2658          * where the context ID would be in the request, so we can use an
2659          * overlength buffer in the request and pre-fill the flags field
2660          * with what we believe the default to be.  Thus if the firmware
2661          * has the bug, it will leave our pre-filled value in the flags
2662          * field of the response, and we will get the right answer.
2663          *
2664          * However, this does mean that this function should NOT be used if
2665          * the RSS context flags might not be their defaults - it is ONLY
2666          * reliably correct for a newly-allocated RSS context.
2667          */
2668         MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN);
2669         MCDI_DECLARE_BUF(outbuf, MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN);
2670         size_t outlen;
2671         int rc;
2672
2673         /* Check we have a hole for the context ID */
2674         BUILD_BUG_ON(MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_LEN != MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_FLAGS_OFST);
2675         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_GET_FLAGS_IN_RSS_CONTEXT_ID, context);
2676         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_GET_FLAGS_OUT_FLAGS,
2677                        RSS_CONTEXT_FLAGS_DEFAULT);
2678         rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_GET_FLAGS, inbuf,
2679                           sizeof(inbuf), outbuf, sizeof(outbuf), &outlen);
2680         if (rc == 0) {
2681                 if (outlen < MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN)
2682                         rc = -EIO;
2683                 else
2684                         *flags = MCDI_DWORD(outbuf, RSS_CONTEXT_GET_FLAGS_OUT_FLAGS);
2685         }
2686         return rc;
2687 }
2688
2689 /* Attempt to enable 4-tuple UDP hashing on the specified RSS context.
2690  * If we fail, we just leave the RSS context at its default hash settings,
2691  * which is safe but may slightly reduce performance.
2692  * Defaults are 4-tuple for TCP and 2-tuple for UDP and other-IP, so we
2693  * just need to set the UDP ports flags (for both IP versions).
2694  */
2695 static void efx_ef10_set_rss_flags(struct efx_nic *efx, u32 context)
2696 {
2697         MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_LEN);
2698         u32 flags;
2699
2700         BUILD_BUG_ON(MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT_LEN != 0);
2701
2702         if (efx_ef10_get_rss_flags(efx, context, &flags) != 0)
2703                 return;
2704         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID, context);
2705         flags |= RSS_MODE_HASH_PORTS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_LBN;
2706         flags |= RSS_MODE_HASH_PORTS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_LBN;
2707         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_SET_FLAGS_IN_FLAGS, flags);
2708         if (!efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_FLAGS, inbuf, sizeof(inbuf),
2709                           NULL, 0, NULL))
2710                 /* Succeeded, so UDP 4-tuple is now enabled */
2711                 efx->rx_hash_udp_4tuple = true;
2712 }
2713
2714 static int efx_ef10_alloc_rss_context(struct efx_nic *efx, u32 *context,
2715                                       bool exclusive, unsigned *context_size)
2716 {
2717         MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN);
2718         MCDI_DECLARE_BUF(outbuf, MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN);
2719         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2720         size_t outlen;
2721         int rc;
2722         u32 alloc_type = exclusive ?
2723                                 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE :
2724                                 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED;
2725         unsigned rss_spread = exclusive ?
2726                                 efx->rss_spread :
2727                                 min(rounddown_pow_of_two(efx->rss_spread),
2728                                     EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE);
2729
2730         if (!exclusive && rss_spread == 1) {
2731                 *context = EFX_EF10_RSS_CONTEXT_INVALID;
2732                 if (context_size)
2733                         *context_size = 1;
2734                 return 0;
2735         }
2736
2737         if (nic_data->datapath_caps &
2738             1 << MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_LBN)
2739                 return -EOPNOTSUPP;
2740
2741         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID,
2742                        nic_data->vport_id);
2743         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_TYPE, alloc_type);
2744         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_NUM_QUEUES, rss_spread);
2745
2746         rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_ALLOC, inbuf, sizeof(inbuf),
2747                 outbuf, sizeof(outbuf), &outlen);
2748         if (rc != 0)
2749                 return rc;
2750
2751         if (outlen < MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN)
2752                 return -EIO;
2753
2754         *context = MCDI_DWORD(outbuf, RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID);
2755
2756         if (context_size)
2757                 *context_size = rss_spread;
2758
2759         if (nic_data->datapath_caps &
2760             1 << MC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_LBN)
2761                 efx_ef10_set_rss_flags(efx, *context);
2762
2763         return 0;
2764 }
2765
2766 static void efx_ef10_free_rss_context(struct efx_nic *efx, u32 context)
2767 {
2768         MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_FREE_IN_LEN);
2769         int rc;
2770
2771         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID,
2772                        context);
2773
2774         rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_FREE, inbuf, sizeof(inbuf),
2775                             NULL, 0, NULL);
2776         WARN_ON(rc != 0);
2777 }
2778
2779 static int efx_ef10_populate_rss_table(struct efx_nic *efx, u32 context,
2780                                        const u32 *rx_indir_table, const u8 *key)
2781 {
2782         MCDI_DECLARE_BUF(tablebuf, MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN);
2783         MCDI_DECLARE_BUF(keybuf, MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN);
2784         int i, rc;
2785
2786         MCDI_SET_DWORD(tablebuf, RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID,
2787                        context);
2788         BUILD_BUG_ON(ARRAY_SIZE(efx->rx_indir_table) !=
2789                      MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN);
2790
2791         /* This iterates over the length of efx->rx_indir_table, but copies
2792          * bytes from rx_indir_table.  That's because the latter is a pointer
2793          * rather than an array, but should have the same length.
2794          * The efx->rx_hash_key loop below is similar.
2795          */
2796         for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); ++i)
2797                 MCDI_PTR(tablebuf,
2798                          RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE)[i] =
2799                                 (u8) rx_indir_table[i];
2800
2801         rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_TABLE, tablebuf,
2802                           sizeof(tablebuf), NULL, 0, NULL);
2803         if (rc != 0)
2804                 return rc;
2805
2806         MCDI_SET_DWORD(keybuf, RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID,
2807                        context);
2808         BUILD_BUG_ON(ARRAY_SIZE(efx->rx_hash_key) !=
2809                      MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN);
2810         for (i = 0; i < ARRAY_SIZE(efx->rx_hash_key); ++i)
2811                 MCDI_PTR(keybuf, RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY)[i] = key[i];
2812
2813         return efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_KEY, keybuf,
2814                             sizeof(keybuf), NULL, 0, NULL);
2815 }
2816
2817 static void efx_ef10_rx_free_indir_table(struct efx_nic *efx)
2818 {
2819         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2820
2821         if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID)
2822                 efx_ef10_free_rss_context(efx, nic_data->rx_rss_context);
2823         nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
2824 }
2825
2826 static int efx_ef10_rx_push_shared_rss_config(struct efx_nic *efx,
2827                                               unsigned *context_size)
2828 {
2829         u32 new_rx_rss_context;
2830         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2831         int rc = efx_ef10_alloc_rss_context(efx, &new_rx_rss_context,
2832                                             false, context_size);
2833
2834         if (rc != 0)
2835                 return rc;
2836
2837         nic_data->rx_rss_context = new_rx_rss_context;
2838         nic_data->rx_rss_context_exclusive = false;
2839         efx_set_default_rx_indir_table(efx);
2840         return 0;
2841 }
2842
2843 static int efx_ef10_rx_push_exclusive_rss_config(struct efx_nic *efx,
2844                                                  const u32 *rx_indir_table,
2845                                                  const u8 *key)
2846 {
2847         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2848         int rc;
2849         u32 new_rx_rss_context;
2850
2851         if (nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID ||
2852             !nic_data->rx_rss_context_exclusive) {
2853                 rc = efx_ef10_alloc_rss_context(efx, &new_rx_rss_context,
2854                                                 true, NULL);
2855                 if (rc == -EOPNOTSUPP)
2856                         return rc;
2857                 else if (rc != 0)
2858                         goto fail1;
2859         } else {
2860                 new_rx_rss_context = nic_data->rx_rss_context;
2861         }
2862
2863         rc = efx_ef10_populate_rss_table(efx, new_rx_rss_context,
2864                                          rx_indir_table, key);
2865         if (rc != 0)
2866                 goto fail2;
2867
2868         if (nic_data->rx_rss_context != new_rx_rss_context)
2869                 efx_ef10_rx_free_indir_table(efx);
2870         nic_data->rx_rss_context = new_rx_rss_context;
2871         nic_data->rx_rss_context_exclusive = true;
2872         if (rx_indir_table != efx->rx_indir_table)
2873                 memcpy(efx->rx_indir_table, rx_indir_table,
2874                        sizeof(efx->rx_indir_table));
2875         if (key != efx->rx_hash_key)
2876                 memcpy(efx->rx_hash_key, key, efx->type->rx_hash_key_size);
2877
2878         return 0;
2879
2880 fail2:
2881         if (new_rx_rss_context != nic_data->rx_rss_context)
2882                 efx_ef10_free_rss_context(efx, new_rx_rss_context);
2883 fail1:
2884         netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
2885         return rc;
2886 }
2887
2888 static int efx_ef10_rx_pull_rss_config(struct efx_nic *efx)
2889 {
2890         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2891         MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_GET_TABLE_IN_LEN);
2892         MCDI_DECLARE_BUF(tablebuf, MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_LEN);
2893         MCDI_DECLARE_BUF(keybuf, MC_CMD_RSS_CONTEXT_GET_KEY_OUT_LEN);
2894         size_t outlen;
2895         int rc, i;
2896
2897         BUILD_BUG_ON(MC_CMD_RSS_CONTEXT_GET_TABLE_IN_LEN !=
2898                      MC_CMD_RSS_CONTEXT_GET_KEY_IN_LEN);
2899
2900         if (nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID)
2901                 return -ENOENT;
2902
2903         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_GET_TABLE_IN_RSS_CONTEXT_ID,
2904                        nic_data->rx_rss_context);
2905         BUILD_BUG_ON(ARRAY_SIZE(efx->rx_indir_table) !=
2906                      MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_LEN);
2907         rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_GET_TABLE, inbuf, sizeof(inbuf),
2908                           tablebuf, sizeof(tablebuf), &outlen);
2909         if (rc != 0)
2910                 return rc;
2911
2912         if (WARN_ON(outlen != MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_LEN))
2913                 return -EIO;
2914
2915         for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); i++)
2916                 efx->rx_indir_table[i] = MCDI_PTR(tablebuf,
2917                                 RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE)[i];
2918
2919         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_GET_KEY_IN_RSS_CONTEXT_ID,
2920                        nic_data->rx_rss_context);
2921         BUILD_BUG_ON(ARRAY_SIZE(efx->rx_hash_key) !=
2922                      MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN);
2923         rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_GET_KEY, inbuf, sizeof(inbuf),
2924                           keybuf, sizeof(keybuf), &outlen);
2925         if (rc != 0)
2926                 return rc;
2927
2928         if (WARN_ON(outlen != MC_CMD_RSS_CONTEXT_GET_KEY_OUT_LEN))
2929                 return -EIO;
2930
2931         for (i = 0; i < ARRAY_SIZE(efx->rx_hash_key); ++i)
2932                 efx->rx_hash_key[i] = MCDI_PTR(
2933                                 keybuf, RSS_CONTEXT_GET_KEY_OUT_TOEPLITZ_KEY)[i];
2934
2935         return 0;
2936 }
2937
2938 static int efx_ef10_pf_rx_push_rss_config(struct efx_nic *efx, bool user,
2939                                           const u32 *rx_indir_table,
2940                                           const u8 *key)
2941 {
2942         int rc;
2943
2944         if (efx->rss_spread == 1)
2945                 return 0;
2946
2947         if (!key)
2948                 key = efx->rx_hash_key;
2949
2950         rc = efx_ef10_rx_push_exclusive_rss_config(efx, rx_indir_table, key);
2951
2952         if (rc == -ENOBUFS && !user) {
2953                 unsigned context_size;
2954                 bool mismatch = false;
2955                 size_t i;
2956
2957                 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table) && !mismatch;
2958                      i++)
2959                         mismatch = rx_indir_table[i] !=
2960                                 ethtool_rxfh_indir_default(i, efx->rss_spread);
2961
2962                 rc = efx_ef10_rx_push_shared_rss_config(efx, &context_size);
2963                 if (rc == 0) {
2964                         if (context_size != efx->rss_spread)
2965                                 netif_warn(efx, probe, efx->net_dev,
2966                                            "Could not allocate an exclusive RSS"
2967                                            " context; allocated a shared one of"
2968                                            " different size."
2969                                            " Wanted %u, got %u.\n",
2970                                            efx->rss_spread, context_size);
2971                         else if (mismatch)
2972                                 netif_warn(efx, probe, efx->net_dev,
2973                                            "Could not allocate an exclusive RSS"
2974                                            " context; allocated a shared one but"
2975                                            " could not apply custom"
2976                                            " indirection.\n");
2977                         else
2978                                 netif_info(efx, probe, efx->net_dev,
2979                                            "Could not allocate an exclusive RSS"
2980                                            " context; allocated a shared one.\n");
2981                 }
2982         }
2983         return rc;
2984 }
2985
2986 static int efx_ef10_vf_rx_push_rss_config(struct efx_nic *efx, bool user,
2987                                           const u32 *rx_indir_table
2988                                           __attribute__ ((unused)),
2989                                           const u8 *key
2990                                           __attribute__ ((unused)))
2991 {
2992         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2993
2994         if (user)
2995                 return -EOPNOTSUPP;
2996         if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID)
2997                 return 0;
2998         return efx_ef10_rx_push_shared_rss_config(efx, NULL);
2999 }
3000
3001 static int efx_ef10_rx_probe(struct efx_rx_queue *rx_queue)
3002 {
3003         return efx_nic_alloc_buffer(rx_queue->efx, &rx_queue->rxd.buf,
3004                                     (rx_queue->ptr_mask + 1) *
3005                                     sizeof(efx_qword_t),
3006                                     GFP_KERNEL);
3007 }
3008
3009 static void efx_ef10_rx_init(struct efx_rx_queue *rx_queue)
3010 {
3011         MCDI_DECLARE_BUF(inbuf,
3012                          MC_CMD_INIT_RXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
3013                                                 EFX_BUF_SIZE));
3014         struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
3015         size_t entries = rx_queue->rxd.buf.len / EFX_BUF_SIZE;
3016         struct efx_nic *efx = rx_queue->efx;
3017         struct efx_ef10_nic_data *nic_data = efx->nic_data;
3018         size_t inlen;
3019         dma_addr_t dma_addr;
3020         int rc;
3021         int i;
3022         BUILD_BUG_ON(MC_CMD_INIT_RXQ_OUT_LEN != 0);
3023
3024         rx_queue->scatter_n = 0;
3025         rx_queue->scatter_len = 0;
3026
3027         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_SIZE, rx_queue->ptr_mask + 1);
3028         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_TARGET_EVQ, channel->channel);
3029         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_LABEL, efx_rx_queue_index(rx_queue));
3030         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_INSTANCE,
3031                        efx_rx_queue_index(rx_queue));
3032         MCDI_POPULATE_DWORD_2(inbuf, INIT_RXQ_IN_FLAGS,
3033                               INIT_RXQ_IN_FLAG_PREFIX, 1,
3034                               INIT_RXQ_IN_FLAG_TIMESTAMP, 1);
3035         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_OWNER_ID, 0);
3036         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_PORT_ID, nic_data->vport_id);
3037
3038         dma_addr = rx_queue->rxd.buf.dma_addr;
3039
3040         netif_dbg(efx, hw, efx->net_dev, "pushing RXQ %d. %zu entries (%llx)\n",
3041                   efx_rx_queue_index(rx_queue), entries, (u64)dma_addr);
3042
3043         for (i = 0; i < entries; ++i) {
3044                 MCDI_SET_ARRAY_QWORD(inbuf, INIT_RXQ_IN_DMA_ADDR, i, dma_addr);
3045                 dma_addr += EFX_BUF_SIZE;
3046         }
3047
3048         inlen = MC_CMD_INIT_RXQ_IN_LEN(entries);
3049
3050         rc = efx_mcdi_rpc(efx, MC_CMD_INIT_RXQ, inbuf, inlen,
3051                           NULL, 0, NULL);
3052         if (rc)
3053                 netdev_WARN(efx->net_dev, "failed to initialise RXQ %d\n",
3054                             efx_rx_queue_index(rx_queue));
3055 }
3056
3057 static void efx_ef10_rx_fini(struct efx_rx_queue *rx_queue)
3058 {
3059         MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_RXQ_IN_LEN);
3060         MCDI_DECLARE_BUF_ERR(outbuf);
3061         struct efx_nic *efx = rx_queue->efx;
3062         size_t outlen;
3063         int rc;
3064
3065         MCDI_SET_DWORD(inbuf, FINI_RXQ_IN_INSTANCE,
3066                        efx_rx_queue_index(rx_queue));
3067
3068         rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_RXQ, inbuf, sizeof(inbuf),
3069                           outbuf, sizeof(outbuf), &outlen);
3070
3071         if (rc && rc != -EALREADY)
3072                 goto fail;
3073
3074         return;
3075
3076 fail:
3077         efx_mcdi_display_error(efx, MC_CMD_FINI_RXQ, MC_CMD_FINI_RXQ_IN_LEN,
3078                                outbuf, outlen, rc);
3079 }
3080
3081 static void efx_ef10_rx_remove(struct efx_rx_queue *rx_queue)
3082 {
3083         efx_nic_free_buffer(rx_queue->efx, &rx_queue->rxd.buf);
3084 }
3085
3086 /* This creates an entry in the RX descriptor queue */
3087 static inline void
3088 efx_ef10_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index)
3089 {
3090         struct efx_rx_buffer *rx_buf;
3091         efx_qword_t *rxd;
3092
3093         rxd = efx_rx_desc(rx_queue, index);
3094         rx_buf = efx_rx_buffer(rx_queue, index);
3095         EFX_POPULATE_QWORD_2(*rxd,
3096                              ESF_DZ_RX_KER_BYTE_CNT, rx_buf->len,
3097                              ESF_DZ_RX_KER_BUF_ADDR, rx_buf->dma_addr);
3098 }
3099
3100 static void efx_ef10_rx_write(struct efx_rx_queue *rx_queue)
3101 {
3102         struct efx_nic *efx = rx_queue->efx;
3103         unsigned int write_count;
3104         efx_dword_t reg;
3105
3106         /* Firmware requires that RX_DESC_WPTR be a multiple of 8 */
3107         write_count = rx_queue->added_count & ~7;
3108         if (rx_queue->notified_count == write_count)
3109                 return;
3110
3111         do
3112                 efx_ef10_build_rx_desc(
3113                         rx_queue,
3114                         rx_queue->notified_count & rx_queue->ptr_mask);
3115         while (++rx_queue->notified_count != write_count);
3116
3117         wmb();
3118         EFX_POPULATE_DWORD_1(reg, ERF_DZ_RX_DESC_WPTR,
3119                              write_count & rx_queue->ptr_mask);
3120         efx_writed_page(efx, &reg, ER_DZ_RX_DESC_UPD,
3121                         efx_rx_queue_index(rx_queue));
3122 }
3123
3124 static efx_mcdi_async_completer efx_ef10_rx_defer_refill_complete;
3125
3126 static void efx_ef10_rx_defer_refill(struct efx_rx_queue *rx_queue)
3127 {
3128         struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
3129         MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
3130         efx_qword_t event;
3131
3132         EFX_POPULATE_QWORD_2(event,
3133                              ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
3134                              ESF_DZ_EV_DATA, EFX_EF10_REFILL);
3135
3136         MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
3137
3138         /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
3139          * already swapped the data to little-endian order.
3140          */
3141         memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
3142                sizeof(efx_qword_t));
3143
3144         efx_mcdi_rpc_async(channel->efx, MC_CMD_DRIVER_EVENT,
3145                            inbuf, sizeof(inbuf), 0,
3146                            efx_ef10_rx_defer_refill_complete, 0);
3147 }
3148
3149 static void
3150 efx_ef10_rx_defer_refill_complete(struct efx_nic *efx, unsigned long cookie,
3151                                   int rc, efx_dword_t *outbuf,
3152                                   size_t outlen_actual)
3153 {
3154         /* nothing to do */
3155 }
3156
3157 static int efx_ef10_ev_probe(struct efx_channel *channel)
3158 {
3159         return efx_nic_alloc_buffer(channel->efx, &channel->eventq.buf,
3160                                     (channel->eventq_mask + 1) *
3161                                     sizeof(efx_qword_t),
3162                                     GFP_KERNEL);
3163 }
3164
3165 static void efx_ef10_ev_fini(struct efx_channel *channel)
3166 {
3167         MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_EVQ_IN_LEN);
3168         MCDI_DECLARE_BUF_ERR(outbuf);
3169         struct efx_nic *efx = channel->efx;
3170         size_t outlen;
3171         int rc;
3172
3173         MCDI_SET_DWORD(inbuf, FINI_EVQ_IN_INSTANCE, channel->channel);
3174
3175         rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_EVQ, inbuf, sizeof(inbuf),
3176                           outbuf, sizeof(outbuf), &outlen);
3177
3178         if (rc && rc != -EALREADY)
3179                 goto fail;
3180
3181         return;
3182
3183 fail:
3184         efx_mcdi_display_error(efx, MC_CMD_FINI_EVQ, MC_CMD_FINI_EVQ_IN_LEN,
3185                                outbuf, outlen, rc);
3186 }
3187
3188 static int efx_ef10_ev_init(struct efx_channel *channel)
3189 {
3190         MCDI_DECLARE_BUF(inbuf,
3191                          MC_CMD_INIT_EVQ_V2_IN_LEN(EFX_MAX_EVQ_SIZE * 8 /
3192                                                    EFX_BUF_SIZE));
3193         MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_EVQ_V2_OUT_LEN);
3194         size_t entries = channel->eventq.buf.len / EFX_BUF_SIZE;
3195         struct efx_nic *efx = channel->efx;
3196         struct efx_ef10_nic_data *nic_data;
3197         size_t inlen, outlen;
3198         unsigned int enabled, implemented;
3199         dma_addr_t dma_addr;
3200         int rc;
3201         int i;
3202
3203         nic_data = efx->nic_data;
3204
3205         /* Fill event queue with all ones (i.e. empty events) */
3206         memset(channel->eventq.buf.addr, 0xff, channel->eventq.buf.len);
3207
3208         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_SIZE, channel->eventq_mask + 1);
3209         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_INSTANCE, channel->channel);
3210         /* INIT_EVQ expects index in vector table, not absolute */
3211         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_IRQ_NUM, channel->channel);
3212         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_MODE,
3213                        MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS);
3214         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_LOAD, 0);
3215         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_RELOAD, 0);
3216         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_MODE,
3217                        MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS);
3218         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_THRSHLD, 0);
3219
3220         if (nic_data->datapath_caps2 &
3221             1 << MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_LBN) {
3222                 /* Use the new generic approach to specifying event queue
3223                  * configuration, requesting lower latency or higher throughput.
3224                  * The options that actually get used appear in the output.
3225                  */
3226                 MCDI_POPULATE_DWORD_2(inbuf, INIT_EVQ_V2_IN_FLAGS,
3227                                       INIT_EVQ_V2_IN_FLAG_INTERRUPTING, 1,
3228                                       INIT_EVQ_V2_IN_FLAG_TYPE,
3229                                       MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_AUTO);
3230         } else {
3231                 bool cut_thru = !(nic_data->datapath_caps &
3232                         1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN);
3233
3234                 MCDI_POPULATE_DWORD_4(inbuf, INIT_EVQ_IN_FLAGS,
3235                                       INIT_EVQ_IN_FLAG_INTERRUPTING, 1,
3236                                       INIT_EVQ_IN_FLAG_RX_MERGE, 1,
3237                                       INIT_EVQ_IN_FLAG_TX_MERGE, 1,
3238                                       INIT_EVQ_IN_FLAG_CUT_THRU, cut_thru);
3239         }
3240
3241         dma_addr = channel->eventq.buf.dma_addr;
3242         for (i = 0; i < entries; ++i) {
3243                 MCDI_SET_ARRAY_QWORD(inbuf, INIT_EVQ_IN_DMA_ADDR, i, dma_addr);
3244                 dma_addr += EFX_BUF_SIZE;
3245         }
3246
3247         inlen = MC_CMD_INIT_EVQ_IN_LEN(entries);
3248
3249         rc = efx_mcdi_rpc(efx, MC_CMD_INIT_EVQ, inbuf, inlen,
3250                           outbuf, sizeof(outbuf), &outlen);
3251
3252         if (outlen >= MC_CMD_INIT_EVQ_V2_OUT_LEN)
3253                 netif_dbg(efx, drv, efx->net_dev,
3254                           "Channel %d using event queue flags %08x\n",
3255                           channel->channel,
3256                           MCDI_DWORD(outbuf, INIT_EVQ_V2_OUT_FLAGS));
3257
3258         /* IRQ return is ignored */
3259         if (channel->channel || rc)
3260                 return rc;
3261
3262         /* Successfully created event queue on channel 0 */
3263         rc = efx_mcdi_get_workarounds(efx, &implemented, &enabled);
3264         if (rc == -ENOSYS) {
3265                 /* GET_WORKAROUNDS was implemented before this workaround,
3266                  * thus it must be unavailable in this firmware.
3267                  */
3268                 nic_data->workaround_26807 = false;
3269                 rc = 0;
3270         } else if (rc) {
3271                 goto fail;
3272         } else {
3273                 nic_data->workaround_26807 =
3274                         !!(enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807);
3275
3276                 if (implemented & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807 &&
3277                     !nic_data->workaround_26807) {
3278                         unsigned int flags;
3279
3280                         rc = efx_mcdi_set_workaround(efx,
3281                                                      MC_CMD_WORKAROUND_BUG26807,
3282                                                      true, &flags);
3283
3284                         if (!rc) {
3285                                 if (flags &
3286                                     1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN) {
3287                                         netif_info(efx, drv, efx->net_dev,
3288                                                    "other functions on NIC have been reset\n");
3289
3290                                         /* With MCFW v4.6.x and earlier, the
3291                                          * boot count will have incremented,
3292                                          * so re-read the warm_boot_count
3293                                          * value now to ensure this function
3294                                          * doesn't think it has changed next
3295                                          * time it checks.
3296                                          */
3297                                         rc = efx_ef10_get_warm_boot_count(efx);
3298                                         if (rc >= 0) {
3299                                                 nic_data->warm_boot_count = rc;
3300                                                 rc = 0;
3301                                         }
3302                                 }
3303                                 nic_data->workaround_26807 = true;
3304                         } else if (rc == -EPERM) {
3305                                 rc = 0;
3306                         }
3307                 }
3308         }
3309
3310         if (!rc)
3311                 return 0;
3312
3313 fail:
3314         efx_ef10_ev_fini(channel);
3315         return rc;
3316 }
3317
3318 static void efx_ef10_ev_remove(struct efx_channel *channel)
3319 {
3320         efx_nic_free_buffer(channel->efx, &channel->eventq.buf);
3321 }
3322
3323 static void efx_ef10_handle_rx_wrong_queue(struct efx_rx_queue *rx_queue,
3324                                            unsigned int rx_queue_label)
3325 {
3326         struct efx_nic *efx = rx_queue->efx;
3327
3328         netif_info(efx, hw, efx->net_dev,
3329                    "rx event arrived on queue %d labeled as queue %u\n",
3330                    efx_rx_queue_index(rx_queue), rx_queue_label);
3331
3332         efx_schedule_reset(efx, RESET_TYPE_DISABLE);
3333 }
3334
3335 static void
3336 efx_ef10_handle_rx_bad_lbits(struct efx_rx_queue *rx_queue,
3337                              unsigned int actual, unsigned int expected)
3338 {
3339         unsigned int dropped = (actual - expected) & rx_queue->ptr_mask;
3340         struct efx_nic *efx = rx_queue->efx;
3341
3342         netif_info(efx, hw, efx->net_dev,
3343                    "dropped %d events (index=%d expected=%d)\n",
3344                    dropped, actual, expected);
3345
3346         efx_schedule_reset(efx, RESET_TYPE_DISABLE);
3347 }
3348
3349 /* partially received RX was aborted. clean up. */
3350 static void efx_ef10_handle_rx_abort(struct efx_rx_queue *rx_queue)
3351 {
3352         unsigned int rx_desc_ptr;
3353
3354         netif_dbg(rx_queue->efx, hw, rx_queue->efx->net_dev,
3355                   "scattered RX aborted (dropping %u buffers)\n",
3356                   rx_queue->scatter_n);
3357
3358         rx_desc_ptr = rx_queue->removed_count & rx_queue->ptr_mask;
3359
3360         efx_rx_packet(rx_queue, rx_desc_ptr, rx_queue->scatter_n,
3361                       0, EFX_RX_PKT_DISCARD);
3362
3363         rx_queue->removed_count += rx_queue->scatter_n;
3364         rx_queue->scatter_n = 0;
3365         rx_queue->scatter_len = 0;
3366         ++efx_rx_queue_channel(rx_queue)->n_rx_nodesc_trunc;
3367 }
3368
3369 static u16 efx_ef10_handle_rx_event_errors(struct efx_channel *channel,
3370                                            unsigned int n_packets,
3371                                            unsigned int rx_encap_hdr,
3372                                            unsigned int rx_l3_class,
3373                                            unsigned int rx_l4_class,
3374                                            const efx_qword_t *event)
3375 {
3376         struct efx_nic *efx = channel->efx;
3377         bool handled = false;
3378
3379         if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_ECRC_ERR)) {
3380                 if (!(efx->net_dev->features & NETIF_F_RXALL)) {
3381                         if (!efx->loopback_selftest)
3382                                 channel->n_rx_eth_crc_err += n_packets;
3383                         return EFX_RX_PKT_DISCARD;
3384                 }
3385                 handled = true;
3386         }
3387         if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_IPCKSUM_ERR)) {
3388                 if (unlikely(rx_encap_hdr != ESE_EZ_ENCAP_HDR_VXLAN &&
3389                              rx_l3_class != ESE_DZ_L3_CLASS_IP4 &&
3390                              rx_l3_class != ESE_DZ_L3_CLASS_IP4_FRAG &&
3391                              rx_l3_class != ESE_DZ_L3_CLASS_IP6 &&
3392                              rx_l3_class != ESE_DZ_L3_CLASS_IP6_FRAG))
3393                         netdev_WARN(efx->net_dev,
3394                                     "invalid class for RX_IPCKSUM_ERR: event="
3395                                     EFX_QWORD_FMT "\n",
3396                                     EFX_QWORD_VAL(*event));
3397                 if (!efx->loopback_selftest)
3398                         *(rx_encap_hdr ?
3399                           &channel->n_rx_outer_ip_hdr_chksum_err :
3400                           &channel->n_rx_ip_hdr_chksum_err) += n_packets;
3401                 return 0;
3402         }
3403         if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_TCPUDP_CKSUM_ERR)) {
3404                 if (unlikely(rx_encap_hdr != ESE_EZ_ENCAP_HDR_VXLAN &&
3405                              ((rx_l3_class != ESE_DZ_L3_CLASS_IP4 &&
3406                                rx_l3_class != ESE_DZ_L3_CLASS_IP6) ||
3407                               (rx_l4_class != ESE_FZ_L4_CLASS_TCP &&
3408                                rx_l4_class != ESE_FZ_L4_CLASS_UDP))))
3409                         netdev_WARN(efx->net_dev,
3410                                     "invalid class for RX_TCPUDP_CKSUM_ERR: event="
3411                                     EFX_QWORD_FMT "\n",
3412                                     EFX_QWORD_VAL(*event));
3413                 if (!efx->loopback_selftest)
3414                         *(rx_encap_hdr ?
3415                           &channel->n_rx_outer_tcp_udp_chksum_err :
3416                           &channel->n_rx_tcp_udp_chksum_err) += n_packets;
3417                 return 0;
3418         }
3419         if (EFX_QWORD_FIELD(*event, ESF_EZ_RX_IP_INNER_CHKSUM_ERR)) {
3420                 if (unlikely(!rx_encap_hdr))
3421                         netdev_WARN(efx->net_dev,
3422                                     "invalid encapsulation type for RX_IP_INNER_CHKSUM_ERR: event="
3423                                     EFX_QWORD_FMT "\n",
3424                                     EFX_QWORD_VAL(*event));
3425                 else if (unlikely(rx_l3_class != ESE_DZ_L3_CLASS_IP4 &&
3426                                   rx_l3_class != ESE_DZ_L3_CLASS_IP4_FRAG &&
3427                                   rx_l3_class != ESE_DZ_L3_CLASS_IP6 &&
3428                                   rx_l3_class != ESE_DZ_L3_CLASS_IP6_FRAG))
3429                         netdev_WARN(efx->net_dev,
3430                                     "invalid class for RX_IP_INNER_CHKSUM_ERR: event="
3431                                     EFX_QWORD_FMT "\n",
3432                                     EFX_QWORD_VAL(*event));
3433                 if (!efx->loopback_selftest)
3434                         channel->n_rx_inner_ip_hdr_chksum_err += n_packets;
3435                 return 0;
3436         }
3437         if (EFX_QWORD_FIELD(*event, ESF_EZ_RX_TCP_UDP_INNER_CHKSUM_ERR)) {
3438                 if (unlikely(!rx_encap_hdr))
3439                         netdev_WARN(efx->net_dev,
3440                                     "invalid encapsulation type for RX_TCP_UDP_INNER_CHKSUM_ERR: event="
3441                                     EFX_QWORD_FMT "\n",
3442                                     EFX_QWORD_VAL(*event));
3443                 else if (unlikely((rx_l3_class != ESE_DZ_L3_CLASS_IP4 &&
3444                                    rx_l3_class != ESE_DZ_L3_CLASS_IP6) ||
3445                                   (rx_l4_class != ESE_FZ_L4_CLASS_TCP &&
3446                                    rx_l4_class != ESE_FZ_L4_CLASS_UDP)))
3447                         netdev_WARN(efx->net_dev,
3448                                     "invalid class for RX_TCP_UDP_INNER_CHKSUM_ERR: event="
3449                                     EFX_QWORD_FMT "\n",
3450                                     EFX_QWORD_VAL(*event));
3451                 if (!efx->loopback_selftest)
3452                         channel->n_rx_inner_tcp_udp_chksum_err += n_packets;
3453                 return 0;
3454         }
3455
3456         WARN_ON(!handled); /* No error bits were recognised */
3457         return 0;
3458 }
3459
3460 static int efx_ef10_handle_rx_event(struct efx_channel *channel,
3461                                     const efx_qword_t *event)
3462 {
3463         unsigned int rx_bytes, next_ptr_lbits, rx_queue_label;
3464         unsigned int rx_l3_class, rx_l4_class, rx_encap_hdr;
3465         unsigned int n_descs, n_packets, i;
3466         struct efx_nic *efx = channel->efx;
3467         struct efx_ef10_nic_data *nic_data = efx->nic_data;
3468         struct efx_rx_queue *rx_queue;
3469         efx_qword_t errors;
3470         bool rx_cont;
3471         u16 flags = 0;
3472
3473         if (unlikely(READ_ONCE(efx->reset_pending)))
3474                 return 0;
3475
3476         /* Basic packet information */
3477         rx_bytes = EFX_QWORD_FIELD(*event, ESF_DZ_RX_BYTES);
3478         next_ptr_lbits = EFX_QWORD_FIELD(*event, ESF_DZ_RX_DSC_PTR_LBITS);
3479         rx_queue_label = EFX_QWORD_FIELD(*event, ESF_DZ_RX_QLABEL);
3480         rx_l3_class = EFX_QWORD_FIELD(*event, ESF_DZ_RX_L3_CLASS);
3481         rx_l4_class = EFX_QWORD_FIELD(*event, ESF_FZ_RX_L4_CLASS);
3482         rx_cont = EFX_QWORD_FIELD(*event, ESF_DZ_RX_CONT);
3483         rx_encap_hdr =
3484                 nic_data->datapath_caps &
3485                         (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN) ?
3486                 EFX_QWORD_FIELD(*event, ESF_EZ_RX_ENCAP_HDR) :
3487                 ESE_EZ_ENCAP_HDR_NONE;
3488
3489         if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_DROP_EVENT))
3490                 netdev_WARN(efx->net_dev, "saw RX_DROP_EVENT: event="
3491                             EFX_QWORD_FMT "\n",
3492                             EFX_QWORD_VAL(*event));
3493
3494         rx_queue = efx_channel_get_rx_queue(channel);
3495
3496         if (unlikely(rx_queue_label != efx_rx_queue_index(rx_queue)))
3497                 efx_ef10_handle_rx_wrong_queue(rx_queue, rx_queue_label);
3498
3499         n_descs = ((next_ptr_lbits - rx_queue->removed_count) &
3500                    ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
3501
3502         if (n_descs != rx_queue->scatter_n + 1) {
3503                 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3504
3505                 /* detect rx abort */
3506                 if (unlikely(n_descs == rx_queue->scatter_n)) {
3507                         if (rx_queue->scatter_n == 0 || rx_bytes != 0)
3508                                 netdev_WARN(efx->net_dev,
3509                                             "invalid RX abort: scatter_n=%u event="
3510                                             EFX_QWORD_FMT "\n",
3511                                             rx_queue->scatter_n,
3512                                             EFX_QWORD_VAL(*event));
3513                         efx_ef10_handle_rx_abort(rx_queue);
3514                         return 0;
3515                 }
3516
3517                 /* Check that RX completion merging is valid, i.e.
3518                  * the current firmware supports it and this is a
3519                  * non-scattered packet.
3520                  */
3521                 if (!(nic_data->datapath_caps &
3522                       (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN)) ||
3523                     rx_queue->scatter_n != 0 || rx_cont) {
3524                         efx_ef10_handle_rx_bad_lbits(
3525                                 rx_queue, next_ptr_lbits,
3526                                 (rx_queue->removed_count +
3527                                  rx_queue->scatter_n + 1) &
3528                                 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
3529                         return 0;
3530                 }
3531
3532                 /* Merged completion for multiple non-scattered packets */
3533                 rx_queue->scatter_n = 1;
3534                 rx_queue->scatter_len = 0;
3535                 n_packets = n_descs;
3536                 ++channel->n_rx_merge_events;
3537                 channel->n_rx_merge_packets += n_packets;
3538                 flags |= EFX_RX_PKT_PREFIX_LEN;
3539         } else {
3540                 ++rx_queue->scatter_n;
3541                 rx_queue->scatter_len += rx_bytes;
3542                 if (rx_cont)
3543                         return 0;
3544                 n_packets = 1;
3545         }
3546
3547         EFX_POPULATE_QWORD_5(errors, ESF_DZ_RX_ECRC_ERR, 1,
3548                                      ESF_DZ_RX_IPCKSUM_ERR, 1,
3549                                      ESF_DZ_RX_TCPUDP_CKSUM_ERR, 1,
3550                                      ESF_EZ_RX_IP_INNER_CHKSUM_ERR, 1,
3551                                      ESF_EZ_RX_TCP_UDP_INNER_CHKSUM_ERR, 1);
3552         EFX_AND_QWORD(errors, *event, errors);
3553         if (unlikely(!EFX_QWORD_IS_ZERO(errors))) {
3554                 flags |= efx_ef10_handle_rx_event_errors(channel, n_packets,
3555                                                          rx_encap_hdr,
3556                                                          rx_l3_class, rx_l4_class,
3557                                                          event);
3558         } else {
3559                 bool tcpudp = rx_l4_class == ESE_FZ_L4_CLASS_TCP ||
3560                               rx_l4_class == ESE_FZ_L4_CLASS_UDP;
3561
3562                 switch (rx_encap_hdr) {
3563                 case ESE_EZ_ENCAP_HDR_VXLAN: /* VxLAN or GENEVE */
3564                         flags |= EFX_RX_PKT_CSUMMED; /* outer UDP csum */
3565                         if (tcpudp)
3566                                 flags |= EFX_RX_PKT_CSUM_LEVEL; /* inner L4 */
3567                         break;
3568                 case ESE_EZ_ENCAP_HDR_GRE:
3569                 case ESE_EZ_ENCAP_HDR_NONE:
3570                         if (tcpudp)
3571                                 flags |= EFX_RX_PKT_CSUMMED;
3572                         break;
3573                 default:
3574                         netdev_WARN(efx->net_dev,
3575                                     "unknown encapsulation type: event="
3576                                     EFX_QWORD_FMT "\n",
3577                                     EFX_QWORD_VAL(*event));
3578                 }
3579         }
3580
3581         if (rx_l4_class == ESE_FZ_L4_CLASS_TCP)
3582                 flags |= EFX_RX_PKT_TCP;
3583
3584         channel->irq_mod_score += 2 * n_packets;
3585
3586         /* Handle received packet(s) */
3587         for (i = 0; i < n_packets; i++) {
3588                 efx_rx_packet(rx_queue,
3589                               rx_queue->removed_count & rx_queue->ptr_mask,
3590                               rx_queue->scatter_n, rx_queue->scatter_len,
3591                               flags);
3592                 rx_queue->removed_count += rx_queue->scatter_n;
3593         }
3594
3595         rx_queue->scatter_n = 0;
3596         rx_queue->scatter_len = 0;
3597
3598         return n_packets;
3599 }
3600
3601 static u32 efx_ef10_extract_event_ts(efx_qword_t *event)
3602 {
3603         u32 tstamp;
3604
3605         tstamp = EFX_QWORD_FIELD(*event, TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI);
3606         tstamp <<= 16;
3607         tstamp |= EFX_QWORD_FIELD(*event, TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO);
3608
3609         return tstamp;
3610 }
3611
3612 static void
3613 efx_ef10_handle_tx_event(struct efx_channel *channel, efx_qword_t *event)
3614 {
3615         struct efx_nic *efx = channel->efx;
3616         struct efx_tx_queue *tx_queue;
3617         unsigned int tx_ev_desc_ptr;
3618         unsigned int tx_ev_q_label;
3619         unsigned int tx_ev_type;
3620         u64 ts_part;
3621
3622         if (unlikely(READ_ONCE(efx->reset_pending)))
3623                 return;
3624
3625         if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_TX_DROP_EVENT)))
3626                 return;
3627
3628         /* Get the transmit queue */
3629         tx_ev_q_label = EFX_QWORD_FIELD(*event, ESF_DZ_TX_QLABEL);
3630         tx_queue = efx_channel_get_tx_queue(channel,
3631                                             tx_ev_q_label % EFX_TXQ_TYPES);
3632
3633         if (!tx_queue->timestamping) {
3634                 /* Transmit completion */
3635                 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, ESF_DZ_TX_DESCR_INDX);
3636                 efx_xmit_done(tx_queue, tx_ev_desc_ptr & tx_queue->ptr_mask);
3637                 return;
3638         }
3639
3640         /* Transmit timestamps are only available for 8XXX series. They result
3641          * in three events per packet. These occur in order, and are:
3642          *  - the normal completion event
3643          *  - the low part of the timestamp
3644          *  - the high part of the timestamp
3645          *
3646          * Each part of the timestamp is itself split across two 16 bit
3647          * fields in the event.
3648          */
3649         tx_ev_type = EFX_QWORD_FIELD(*event, ESF_EZ_TX_SOFT1);
3650
3651         switch (tx_ev_type) {
3652         case TX_TIMESTAMP_EVENT_TX_EV_COMPLETION:
3653                 /* In case of Queue flush or FLR, we might have received
3654                  * the previous TX completion event but not the Timestamp
3655                  * events.
3656                  */
3657                 if (tx_queue->completed_desc_ptr != tx_queue->ptr_mask)
3658                         efx_xmit_done(tx_queue, tx_queue->completed_desc_ptr);
3659
3660                 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event,
3661                                                  ESF_DZ_TX_DESCR_INDX);
3662                 tx_queue->completed_desc_ptr =
3663                                         tx_ev_desc_ptr & tx_queue->ptr_mask;
3664                 break;
3665
3666         case TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_LO:
3667                 ts_part = efx_ef10_extract_event_ts(event);
3668                 tx_queue->completed_timestamp_minor = ts_part;
3669                 break;
3670
3671         case TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_HI:
3672                 ts_part = efx_ef10_extract_event_ts(event);
3673                 tx_queue->completed_timestamp_major = ts_part;
3674
3675                 efx_xmit_done(tx_queue, tx_queue->completed_desc_ptr);
3676                 tx_queue->completed_desc_ptr = tx_queue->ptr_mask;
3677                 break;
3678
3679         default:
3680                 netif_err(efx, hw, efx->net_dev,
3681                           "channel %d unknown tx event type %d (data "
3682                           EFX_QWORD_FMT ")\n",
3683                           channel->channel, tx_ev_type,
3684                           EFX_QWORD_VAL(*event));
3685                 break;
3686         }
3687 }
3688
3689 static void
3690 efx_ef10_handle_driver_event(struct efx_channel *channel, efx_qword_t *event)
3691 {
3692         struct efx_nic *efx = channel->efx;
3693         int subcode;
3694
3695         subcode = EFX_QWORD_FIELD(*event, ESF_DZ_DRV_SUB_CODE);
3696
3697         switch (subcode) {
3698         case ESE_DZ_DRV_TIMER_EV:
3699         case ESE_DZ_DRV_WAKE_UP_EV:
3700                 break;
3701         case ESE_DZ_DRV_START_UP_EV:
3702                 /* event queue init complete. ok. */
3703                 break;
3704         default:
3705                 netif_err(efx, hw, efx->net_dev,
3706                           "channel %d unknown driver event type %d"
3707                           " (data " EFX_QWORD_FMT ")\n",
3708                           channel->channel, subcode,
3709                           EFX_QWORD_VAL(*event));
3710
3711         }
3712 }
3713
3714 static void efx_ef10_handle_driver_generated_event(struct efx_channel *channel,
3715                                                    efx_qword_t *event)
3716 {
3717         struct efx_nic *efx = channel->efx;
3718         u32 subcode;
3719
3720         subcode = EFX_QWORD_FIELD(*event, EFX_DWORD_0);
3721
3722         switch (subcode) {
3723         case EFX_EF10_TEST:
3724                 channel->event_test_cpu = raw_smp_processor_id();
3725                 break;
3726         case EFX_EF10_REFILL:
3727                 /* The queue must be empty, so we won't receive any rx
3728                  * events, so efx_process_channel() won't refill the
3729                  * queue. Refill it here
3730                  */
3731                 efx_fast_push_rx_descriptors(&channel->rx_queue, true);
3732                 break;
3733         default:
3734                 netif_err(efx, hw, efx->net_dev,
3735                           "channel %d unknown driver event type %u"
3736                           " (data " EFX_QWORD_FMT ")\n",
3737                           channel->channel, (unsigned) subcode,
3738                           EFX_QWORD_VAL(*event));
3739         }
3740 }
3741
3742 static int efx_ef10_ev_process(struct efx_channel *channel, int quota)
3743 {
3744         struct efx_nic *efx = channel->efx;
3745         efx_qword_t event, *p_event;
3746         unsigned int read_ptr;
3747         int ev_code;
3748         int spent = 0;
3749
3750         if (quota <= 0)
3751                 return spent;
3752
3753         read_ptr = channel->eventq_read_ptr;
3754
3755         for (;;) {
3756                 p_event = efx_event(channel, read_ptr);
3757                 event = *p_event;
3758
3759                 if (!efx_event_present(&event))
3760                         break;
3761
3762                 EFX_SET_QWORD(*p_event);
3763
3764                 ++read_ptr;
3765
3766                 ev_code = EFX_QWORD_FIELD(event, ESF_DZ_EV_CODE);
3767
3768                 netif_vdbg(efx, drv, efx->net_dev,
3769                            "processing event on %d " EFX_QWORD_FMT "\n",
3770                            channel->channel, EFX_QWORD_VAL(event));
3771
3772                 switch (ev_code) {
3773                 case ESE_DZ_EV_CODE_MCDI_EV:
3774                         efx_mcdi_process_event(channel, &event);
3775                         break;
3776                 case ESE_DZ_EV_CODE_RX_EV:
3777                         spent += efx_ef10_handle_rx_event(channel, &event);
3778                         if (spent >= quota) {
3779                                 /* XXX can we split a merged event to
3780                                  * avoid going over-quota?
3781                                  */
3782                                 spent = quota;
3783                                 goto out;
3784                         }
3785                         break;
3786                 case ESE_DZ_EV_CODE_TX_EV:
3787                         efx_ef10_handle_tx_event(channel, &event);
3788                         break;
3789                 case ESE_DZ_EV_CODE_DRIVER_EV:
3790                         efx_ef10_handle_driver_event(channel, &event);
3791                         if (++spent == quota)
3792                                 goto out;
3793                         break;
3794                 case EFX_EF10_DRVGEN_EV:
3795                         efx_ef10_handle_driver_generated_event(channel, &event);
3796                         break;
3797                 default:
3798                         netif_err(efx, hw, efx->net_dev,
3799                                   "channel %d unknown event type %d"
3800                                   " (data " EFX_QWORD_FMT ")\n",
3801                                   channel->channel, ev_code,
3802                                   EFX_QWORD_VAL(event));
3803                 }
3804         }
3805
3806 out:
3807         channel->eventq_read_ptr = read_ptr;
3808         return spent;
3809 }
3810
3811 static void efx_ef10_ev_read_ack(struct efx_channel *channel)
3812 {
3813         struct efx_nic *efx = channel->efx;
3814         efx_dword_t rptr;
3815
3816         if (EFX_EF10_WORKAROUND_35388(efx)) {
3817                 BUILD_BUG_ON(EFX_MIN_EVQ_SIZE <
3818                              (1 << ERF_DD_EVQ_IND_RPTR_WIDTH));
3819                 BUILD_BUG_ON(EFX_MAX_EVQ_SIZE >
3820                              (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH));
3821
3822                 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
3823                                      EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH,
3824                                      ERF_DD_EVQ_IND_RPTR,
3825                                      (channel->eventq_read_ptr &
3826                                       channel->eventq_mask) >>
3827                                      ERF_DD_EVQ_IND_RPTR_WIDTH);
3828                 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
3829                                 channel->channel);
3830                 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
3831                                      EFE_DD_EVQ_IND_RPTR_FLAGS_LOW,
3832                                      ERF_DD_EVQ_IND_RPTR,
3833                                      channel->eventq_read_ptr &
3834                                      ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1));
3835                 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
3836                                 channel->channel);
3837         } else {
3838                 EFX_POPULATE_DWORD_1(rptr, ERF_DZ_EVQ_RPTR,
3839                                      channel->eventq_read_ptr &
3840                                      channel->eventq_mask);
3841                 efx_writed_page(efx, &rptr, ER_DZ_EVQ_RPTR, channel->channel);
3842         }
3843 }
3844
3845 static void efx_ef10_ev_test_generate(struct efx_channel *channel)
3846 {
3847         MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
3848         struct efx_nic *efx = channel->efx;
3849         efx_qword_t event;
3850         int rc;
3851
3852         EFX_POPULATE_QWORD_2(event,
3853                              ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
3854                              ESF_DZ_EV_DATA, EFX_EF10_TEST);
3855
3856         MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
3857
3858         /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
3859          * already swapped the data to little-endian order.
3860          */
3861         memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
3862                sizeof(efx_qword_t));
3863
3864         rc = efx_mcdi_rpc(efx, MC_CMD_DRIVER_EVENT, inbuf, sizeof(inbuf),
3865                           NULL, 0, NULL);
3866         if (rc != 0)
3867                 goto fail;
3868
3869         return;
3870
3871 fail:
3872         WARN_ON(true);
3873         netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
3874 }
3875
3876 void efx_ef10_handle_drain_event(struct efx_nic *efx)
3877 {
3878         if (atomic_dec_and_test(&efx->active_queues))
3879                 wake_up(&efx->flush_wq);
3880
3881         WARN_ON(atomic_read(&efx->active_queues) < 0);
3882 }
3883
3884 static int efx_ef10_fini_dmaq(struct efx_nic *efx)
3885 {
3886         struct efx_ef10_nic_data *nic_data = efx->nic_data;
3887         struct efx_channel *channel;
3888         struct efx_tx_queue *tx_queue;
3889         struct efx_rx_queue *rx_queue;
3890         int pending;
3891
3892         /* If the MC has just rebooted, the TX/RX queues will have already been
3893          * torn down, but efx->active_queues needs to be set to zero.
3894          */
3895         if (nic_data->must_realloc_vis) {
3896                 atomic_set(&efx->active_queues, 0);
3897                 return 0;
3898         }
3899
3900         /* Do not attempt to write to the NIC during EEH recovery */
3901         if (efx->state != STATE_RECOVERY) {
3902                 efx_for_each_channel(channel, efx) {
3903                         efx_for_each_channel_rx_queue(rx_queue, channel)
3904                                 efx_ef10_rx_fini(rx_queue);
3905                         efx_for_each_channel_tx_queue(tx_queue, channel)
3906                                 efx_ef10_tx_fini(tx_queue);
3907                 }
3908
3909                 wait_event_timeout(efx->flush_wq,
3910                                    atomic_read(&efx->active_queues) == 0,
3911                                    msecs_to_jiffies(EFX_MAX_FLUSH_TIME));
3912                 pending = atomic_read(&efx->active_queues);
3913                 if (pending) {
3914                         netif_err(efx, hw, efx->net_dev, "failed to flush %d queues\n",
3915                                   pending);
3916                         return -ETIMEDOUT;
3917                 }
3918         }
3919
3920         return 0;
3921 }
3922
3923 static void efx_ef10_prepare_flr(struct efx_nic *efx)
3924 {
3925         atomic_set(&efx->active_queues, 0);
3926 }
3927
3928 static bool efx_ef10_filter_equal(const struct efx_filter_spec *left,
3929                                   const struct efx_filter_spec *right)
3930 {
3931         if ((left->match_flags ^ right->match_flags) |
3932             ((left->flags ^ right->flags) &
3933              (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)))
3934                 return false;
3935
3936         return memcmp(&left->outer_vid, &right->outer_vid,
3937                       sizeof(struct efx_filter_spec) -
3938                       offsetof(struct efx_filter_spec, outer_vid)) == 0;
3939 }
3940
3941 static unsigned int efx_ef10_filter_hash(const struct efx_filter_spec *spec)
3942 {
3943         BUILD_BUG_ON(offsetof(struct efx_filter_spec, outer_vid) & 3);
3944         return jhash2((const u32 *)&spec->outer_vid,
3945                       (sizeof(struct efx_filter_spec) -
3946                        offsetof(struct efx_filter_spec, outer_vid)) / 4,
3947                       0);
3948         /* XXX should we randomise the initval? */
3949 }
3950
3951 /* Decide whether a filter should be exclusive or else should allow
3952  * delivery to additional recipients.  Currently we decide that
3953  * filters for specific local unicast MAC and IP addresses are
3954  * exclusive.
3955  */
3956 static bool efx_ef10_filter_is_exclusive(const struct efx_filter_spec *spec)
3957 {
3958         if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC &&
3959             !is_multicast_ether_addr(spec->loc_mac))
3960                 return true;
3961
3962         if ((spec->match_flags &
3963              (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) ==
3964             (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) {
3965                 if (spec->ether_type == htons(ETH_P_IP) &&
3966                     !ipv4_is_multicast(spec->loc_host[0]))
3967                         return true;
3968                 if (spec->ether_type == htons(ETH_P_IPV6) &&
3969                     ((const u8 *)spec->loc_host)[0] != 0xff)
3970                         return true;
3971         }
3972
3973         return false;
3974 }
3975
3976 static struct efx_filter_spec *
3977 efx_ef10_filter_entry_spec(const struct efx_ef10_filter_table *table,
3978                            unsigned int filter_idx)
3979 {
3980         return (struct efx_filter_spec *)(table->entry[filter_idx].spec &
3981                                           ~EFX_EF10_FILTER_FLAGS);
3982 }
3983
3984 static unsigned int
3985 efx_ef10_filter_entry_flags(const struct efx_ef10_filter_table *table,
3986                            unsigned int filter_idx)
3987 {
3988         return table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAGS;
3989 }
3990
3991 static void
3992 efx_ef10_filter_set_entry(struct efx_ef10_filter_table *table,
3993                           unsigned int filter_idx,
3994                           const struct efx_filter_spec *spec,
3995                           unsigned int flags)
3996 {
3997         table->entry[filter_idx].spec = (unsigned long)spec | flags;
3998 }
3999
4000 static void
4001 efx_ef10_filter_push_prep_set_match_fields(struct efx_nic *efx,
4002                                            const struct efx_filter_spec *spec,
4003                                            efx_dword_t *inbuf)
4004 {
4005         enum efx_encap_type encap_type = efx_filter_get_encap_type(spec);
4006         u32 match_fields = 0, uc_match, mc_match;
4007
4008         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
4009                        efx_ef10_filter_is_exclusive(spec) ?
4010                        MC_CMD_FILTER_OP_IN_OP_INSERT :
4011                        MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE);
4012
4013         /* Convert match flags and values.  Unlike almost
4014          * everything else in MCDI, these fields are in
4015          * network byte order.
4016          */
4017 #define COPY_VALUE(value, mcdi_field)                                        \
4018         do {                                                         \
4019                 match_fields |=                                      \
4020                         1 << MC_CMD_FILTER_OP_IN_MATCH_ ##           \
4021                         mcdi_field ## _LBN;                          \
4022                 BUILD_BUG_ON(                                        \
4023                         MC_CMD_FILTER_OP_IN_ ## mcdi_field ## _LEN < \
4024                         sizeof(value));                              \
4025                 memcpy(MCDI_PTR(inbuf, FILTER_OP_IN_ ## mcdi_field), \
4026                        &value, sizeof(value));                       \
4027         } while (0)
4028 #define COPY_FIELD(gen_flag, gen_field, mcdi_field)                          \
4029         if (spec->match_flags & EFX_FILTER_MATCH_ ## gen_flag) {     \
4030                 COPY_VALUE(spec->gen_field, mcdi_field);             \
4031         }
4032         /* Handle encap filters first.  They will always be mismatch
4033          * (unknown UC or MC) filters
4034          */
4035         if (encap_type) {
4036                 /* ether_type and outer_ip_proto need to be variables
4037                  * because COPY_VALUE wants to memcpy them
4038                  */
4039                 __be16 ether_type =
4040                         htons(encap_type & EFX_ENCAP_FLAG_IPV6 ?
4041                               ETH_P_IPV6 : ETH_P_IP);
4042                 u8 vni_type = MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_GENEVE;
4043                 u8 outer_ip_proto;
4044
4045                 switch (encap_type & EFX_ENCAP_TYPES_MASK) {
4046                 case EFX_ENCAP_TYPE_VXLAN:
4047                         vni_type = MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_VXLAN;
4048                         /* fallthrough */
4049                 case EFX_ENCAP_TYPE_GENEVE:
4050                         COPY_VALUE(ether_type, ETHER_TYPE);
4051                         outer_ip_proto = IPPROTO_UDP;
4052                         COPY_VALUE(outer_ip_proto, IP_PROTO);
4053                         /* We always need to set the type field, even
4054                          * though we're not matching on the TNI.
4055                          */
4056                         MCDI_POPULATE_DWORD_1(inbuf,
4057                                 FILTER_OP_EXT_IN_VNI_OR_VSID,
4058                                 FILTER_OP_EXT_IN_VNI_TYPE,
4059                                 vni_type);
4060                         break;
4061                 case EFX_ENCAP_TYPE_NVGRE:
4062                         COPY_VALUE(ether_type, ETHER_TYPE);
4063                         outer_ip_proto = IPPROTO_GRE;
4064                         COPY_VALUE(outer_ip_proto, IP_PROTO);
4065                         break;
4066                 default:
4067                         WARN_ON(1);
4068                 }
4069
4070                 uc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_LBN;
4071                 mc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_LBN;
4072         } else {
4073                 uc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_LBN;
4074                 mc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_LBN;
4075         }
4076
4077         if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC_IG)
4078                 match_fields |=
4079                         is_multicast_ether_addr(spec->loc_mac) ?
4080                         1 << mc_match :
4081                         1 << uc_match;
4082         COPY_FIELD(REM_HOST, rem_host, SRC_IP);
4083         COPY_FIELD(LOC_HOST, loc_host, DST_IP);
4084         COPY_FIELD(REM_MAC, rem_mac, SRC_MAC);
4085         COPY_FIELD(REM_PORT, rem_port, SRC_PORT);
4086         COPY_FIELD(LOC_MAC, loc_mac, DST_MAC);
4087         COPY_FIELD(LOC_PORT, loc_port, DST_PORT);
4088         COPY_FIELD(ETHER_TYPE, ether_type, ETHER_TYPE);
4089         COPY_FIELD(INNER_VID, inner_vid, INNER_VLAN);
4090         COPY_FIELD(OUTER_VID, outer_vid, OUTER_VLAN);
4091         COPY_FIELD(IP_PROTO, ip_proto, IP_PROTO);
4092 #undef COPY_FIELD
4093 #undef COPY_VALUE
4094         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_MATCH_FIELDS,
4095                        match_fields);
4096 }
4097
4098 static void efx_ef10_filter_push_prep(struct efx_nic *efx,
4099                                       const struct efx_filter_spec *spec,
4100                                       efx_dword_t *inbuf, u64 handle,
4101                                       bool replacing)
4102 {
4103         struct efx_ef10_nic_data *nic_data = efx->nic_data;
4104         u32 flags = spec->flags;
4105
4106         memset(inbuf, 0, MC_CMD_FILTER_OP_EXT_IN_LEN);
4107
4108         /* Remove RSS flag if we don't have an RSS context. */
4109         if (flags & EFX_FILTER_FLAG_RX_RSS &&
4110             spec->rss_context == EFX_FILTER_RSS_CONTEXT_DEFAULT &&
4111             nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID)
4112                 flags &= ~EFX_FILTER_FLAG_RX_RSS;
4113
4114         if (replacing) {
4115                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
4116                                MC_CMD_FILTER_OP_IN_OP_REPLACE);
4117                 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, handle);
4118         } else {
4119                 efx_ef10_filter_push_prep_set_match_fields(efx, spec, inbuf);
4120         }
4121
4122         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_PORT_ID, nic_data->vport_id);
4123         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_DEST,
4124                        spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
4125                        MC_CMD_FILTER_OP_IN_RX_DEST_DROP :
4126                        MC_CMD_FILTER_OP_IN_RX_DEST_HOST);
4127         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DOMAIN, 0);
4128         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DEST,
4129                        MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT);
4130         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_QUEUE,
4131                        spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
4132                        0 : spec->dmaq_id);
4133         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_MODE,
4134                        (flags & EFX_FILTER_FLAG_RX_RSS) ?
4135                        MC_CMD_FILTER_OP_IN_RX_MODE_RSS :
4136                        MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE);
4137         if (flags & EFX_FILTER_FLAG_RX_RSS)
4138                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_CONTEXT,
4139                                spec->rss_context !=
4140                                EFX_FILTER_RSS_CONTEXT_DEFAULT ?
4141                                spec->rss_context : nic_data->rx_rss_context);
4142 }
4143
4144 static int efx_ef10_filter_push(struct efx_nic *efx,
4145                                 const struct efx_filter_spec *spec,
4146                                 u64 *handle, bool replacing)
4147 {
4148         MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_EXT_IN_LEN);
4149         MCDI_DECLARE_BUF(outbuf, MC_CMD_FILTER_OP_EXT_OUT_LEN);
4150         int rc;
4151
4152         efx_ef10_filter_push_prep(efx, spec, inbuf, *handle, replacing);
4153         rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
4154                           outbuf, sizeof(outbuf), NULL);
4155         if (rc == 0)
4156                 *handle = MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
4157         if (rc == -ENOSPC)
4158                 rc = -EBUSY; /* to match efx_farch_filter_insert() */
4159         return rc;
4160 }
4161
4162 static u32 efx_ef10_filter_mcdi_flags_from_spec(const struct efx_filter_spec *spec)
4163 {
4164         enum efx_encap_type encap_type = efx_filter_get_encap_type(spec);
4165         unsigned int match_flags = spec->match_flags;
4166         unsigned int uc_match, mc_match;
4167         u32 mcdi_flags = 0;
4168
4169 #define MAP_FILTER_TO_MCDI_FLAG(gen_flag, mcdi_field, encap) {          \
4170                 unsigned int  old_match_flags = match_flags;            \
4171                 match_flags &= ~EFX_FILTER_MATCH_ ## gen_flag;          \
4172                 if (match_flags != old_match_flags)                     \
4173                         mcdi_flags |=                                   \
4174                                 (1 << ((encap) ?                        \
4175                                        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_ ## \
4176                                        mcdi_field ## _LBN :             \
4177                                        MC_CMD_FILTER_OP_EXT_IN_MATCH_ ##\
4178                                        mcdi_field ## _LBN));            \
4179         }
4180         /* inner or outer based on encap type */
4181         MAP_FILTER_TO_MCDI_FLAG(REM_HOST, SRC_IP, encap_type);
4182         MAP_FILTER_TO_MCDI_FLAG(LOC_HOST, DST_IP, encap_type);
4183         MAP_FILTER_TO_MCDI_FLAG(REM_MAC, SRC_MAC, encap_type);
4184         MAP_FILTER_TO_MCDI_FLAG(REM_PORT, SRC_PORT, encap_type);
4185         MAP_FILTER_TO_MCDI_FLAG(LOC_MAC, DST_MAC, encap_type);
4186         MAP_FILTER_TO_MCDI_FLAG(LOC_PORT, DST_PORT, encap_type);
4187         MAP_FILTER_TO_MCDI_FLAG(ETHER_TYPE, ETHER_TYPE, encap_type);
4188         MAP_FILTER_TO_MCDI_FLAG(IP_PROTO, IP_PROTO, encap_type);
4189         /* always outer */
4190         MAP_FILTER_TO_MCDI_FLAG(INNER_VID, INNER_VLAN, false);
4191         MAP_FILTER_TO_MCDI_FLAG(OUTER_VID, OUTER_VLAN, false);
4192 #undef MAP_FILTER_TO_MCDI_FLAG
4193
4194         /* special handling for encap type, and mismatch */
4195         if (encap_type) {
4196                 match_flags &= ~EFX_FILTER_MATCH_ENCAP_TYPE;
4197                 mcdi_flags |=
4198                         (1 << MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_LBN);
4199                 mcdi_flags |= (1 << MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_LBN);
4200
4201                 uc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_LBN;
4202                 mc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_LBN;
4203         } else {
4204                 uc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_LBN;
4205                 mc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_LBN;
4206         }
4207
4208         if (match_flags & EFX_FILTER_MATCH_LOC_MAC_IG) {
4209                 match_flags &= ~EFX_FILTER_MATCH_LOC_MAC_IG;
4210                 mcdi_flags |=
4211                         is_multicast_ether_addr(spec->loc_mac) ?
4212                         1 << mc_match :
4213                         1 << uc_match;
4214         }
4215
4216         /* Did we map them all? */
4217         WARN_ON_ONCE(match_flags);
4218
4219         return mcdi_flags;
4220 }
4221
4222 static int efx_ef10_filter_pri(struct efx_ef10_filter_table *table,
4223                                const struct efx_filter_spec *spec)
4224 {
4225         u32 mcdi_flags = efx_ef10_filter_mcdi_flags_from_spec(spec);
4226         unsigned int match_pri;
4227
4228         for (match_pri = 0;
4229              match_pri < table->rx_match_count;
4230              match_pri++)
4231                 if (table->rx_match_mcdi_flags[match_pri] == mcdi_flags)
4232                         return match_pri;
4233
4234         return -EPROTONOSUPPORT;
4235 }
4236
4237 static s32 efx_ef10_filter_insert(struct efx_nic *efx,
4238                                   struct efx_filter_spec *spec,
4239                                   bool replace_equal)
4240 {
4241         struct efx_ef10_filter_table *table = efx->filter_state;
4242         DECLARE_BITMAP(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
4243         struct efx_filter_spec *saved_spec;
4244         unsigned int match_pri, hash;
4245         unsigned int priv_flags;
4246         bool replacing = false;
4247         int ins_index = -1;
4248         DEFINE_WAIT(wait);
4249         bool is_mc_recip;
4250         s32 rc;
4251
4252         /* For now, only support RX filters */
4253         if ((spec->flags & (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)) !=
4254             EFX_FILTER_FLAG_RX)
4255                 return -EINVAL;
4256
4257         rc = efx_ef10_filter_pri(table, spec);
4258         if (rc < 0)
4259                 return rc;
4260         match_pri = rc;
4261
4262         hash = efx_ef10_filter_hash(spec);
4263         is_mc_recip = efx_filter_is_mc_recipient(spec);
4264         if (is_mc_recip)
4265                 bitmap_zero(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
4266
4267         /* Find any existing filters with the same match tuple or
4268          * else a free slot to insert at.  If any of them are busy,
4269          * we have to wait and retry.
4270          */
4271         for (;;) {
4272                 unsigned int depth = 1;
4273                 unsigned int i;
4274
4275                 spin_lock_bh(&efx->filter_lock);
4276
4277                 for (;;) {
4278                         i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
4279                         saved_spec = efx_ef10_filter_entry_spec(table, i);
4280
4281                         if (!saved_spec) {
4282                                 if (ins_index < 0)
4283                                         ins_index = i;
4284                         } else if (efx_ef10_filter_equal(spec, saved_spec)) {
4285                                 if (table->entry[i].spec &
4286                                     EFX_EF10_FILTER_FLAG_BUSY)
4287                                         break;
4288                                 if (spec->priority < saved_spec->priority &&
4289                                     spec->priority != EFX_FILTER_PRI_AUTO) {
4290                                         rc = -EPERM;
4291                                         goto out_unlock;
4292                                 }
4293                                 if (!is_mc_recip) {
4294                                         /* This is the only one */
4295                                         if (spec->priority ==
4296                                             saved_spec->priority &&
4297                                             !replace_equal) {
4298                                                 rc = -EEXIST;
4299                                                 goto out_unlock;
4300                                         }
4301                                         ins_index = i;
4302                                         goto found;
4303                                 } else if (spec->priority >
4304                                            saved_spec->priority ||
4305                                            (spec->priority ==
4306                                             saved_spec->priority &&
4307                                             replace_equal)) {
4308                                         if (ins_index < 0)
4309                                                 ins_index = i;
4310                                         else
4311                                                 __set_bit(depth, mc_rem_map);
4312                                 }
4313                         }
4314
4315                         /* Once we reach the maximum search depth, use
4316                          * the first suitable slot or return -EBUSY if
4317                          * there was none
4318                          */
4319                         if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
4320                                 if (ins_index < 0) {
4321                                         rc = -EBUSY;
4322                                         goto out_unlock;
4323                                 }
4324                                 goto found;
4325                         }
4326
4327                         ++depth;
4328                 }
4329
4330                 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
4331                 spin_unlock_bh(&efx->filter_lock);
4332                 schedule();
4333         }
4334
4335 found:
4336         /* Create a software table entry if necessary, and mark it
4337          * busy.  We might yet fail to insert, but any attempt to
4338          * insert a conflicting filter while we're waiting for the
4339          * firmware must find the busy entry.
4340          */
4341         saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
4342         if (saved_spec) {
4343                 if (spec->priority == EFX_FILTER_PRI_AUTO &&
4344                     saved_spec->priority >= EFX_FILTER_PRI_AUTO) {
4345                         /* Just make sure it won't be removed */
4346                         if (saved_spec->priority > EFX_FILTER_PRI_AUTO)
4347                                 saved_spec->flags |= EFX_FILTER_FLAG_RX_OVER_AUTO;
4348                         table->entry[ins_index].spec &=
4349                                 ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
4350                         rc = ins_index;
4351                         goto out_unlock;
4352                 }
4353                 replacing = true;
4354                 priv_flags = efx_ef10_filter_entry_flags(table, ins_index);
4355         } else {
4356                 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
4357                 if (!saved_spec) {
4358                         rc = -ENOMEM;
4359                         goto out_unlock;
4360                 }
4361                 *saved_spec = *spec;
4362                 priv_flags = 0;
4363         }
4364         efx_ef10_filter_set_entry(table, ins_index, saved_spec,
4365                                   priv_flags | EFX_EF10_FILTER_FLAG_BUSY);
4366
4367         /* Mark lower-priority multicast recipients busy prior to removal */
4368         if (is_mc_recip) {
4369                 unsigned int depth, i;
4370
4371                 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
4372                         i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
4373                         if (test_bit(depth, mc_rem_map))
4374                                 table->entry[i].spec |=
4375                                         EFX_EF10_FILTER_FLAG_BUSY;
4376                 }
4377         }
4378
4379         spin_unlock_bh(&efx->filter_lock);
4380
4381         rc = efx_ef10_filter_push(efx, spec, &table->entry[ins_index].handle,
4382                                   replacing);
4383
4384         /* Finalise the software table entry */
4385         spin_lock_bh(&efx->filter_lock);
4386         if (rc == 0) {
4387                 if (replacing) {
4388                         /* Update the fields that may differ */
4389                         if (saved_spec->priority == EFX_FILTER_PRI_AUTO)
4390                                 saved_spec->flags |=
4391                                         EFX_FILTER_FLAG_RX_OVER_AUTO;
4392                         saved_spec->priority = spec->priority;
4393                         saved_spec->flags &= EFX_FILTER_FLAG_RX_OVER_AUTO;
4394                         saved_spec->flags |= spec->flags;
4395                         saved_spec->rss_context = spec->rss_context;
4396                         saved_spec->dmaq_id = spec->dmaq_id;
4397                 }
4398         } else if (!replacing) {
4399                 kfree(saved_spec);
4400                 saved_spec = NULL;
4401         }
4402         efx_ef10_filter_set_entry(table, ins_index, saved_spec, priv_flags);
4403
4404         /* Remove and finalise entries for lower-priority multicast
4405          * recipients
4406          */
4407         if (is_mc_recip) {
4408                 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_EXT_IN_LEN);
4409                 unsigned int depth, i;
4410
4411                 memset(inbuf, 0, sizeof(inbuf));
4412
4413                 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
4414                         if (!test_bit(depth, mc_rem_map))
4415                                 continue;
4416
4417                         i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
4418                         saved_spec = efx_ef10_filter_entry_spec(table, i);
4419                         priv_flags = efx_ef10_filter_entry_flags(table, i);
4420
4421                         if (rc == 0) {
4422                                 spin_unlock_bh(&efx->filter_lock);
4423                                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
4424                                                MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
4425                                 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
4426                                                table->entry[i].handle);
4427                                 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
4428                                                   inbuf, sizeof(inbuf),
4429                                                   NULL, 0, NULL);
4430                                 spin_lock_bh(&efx->filter_lock);
4431                         }
4432
4433                         if (rc == 0) {
4434                                 kfree(saved_spec);
4435                                 saved_spec = NULL;
4436                                 priv_flags = 0;
4437                         } else {
4438                                 priv_flags &= ~EFX_EF10_FILTER_FLAG_BUSY;
4439                         }
4440                         efx_ef10_filter_set_entry(table, i, saved_spec,
4441                                                   priv_flags);
4442                 }
4443         }
4444
4445         /* If successful, return the inserted filter ID */
4446         if (rc == 0)
4447                 rc = efx_ef10_make_filter_id(match_pri, ins_index);
4448
4449         wake_up_all(&table->waitq);
4450 out_unlock:
4451         spin_unlock_bh(&efx->filter_lock);
4452         finish_wait(&table->waitq, &wait);
4453         return rc;
4454 }
4455
4456 static void efx_ef10_filter_update_rx_scatter(struct efx_nic *efx)
4457 {
4458         /* no need to do anything here on EF10 */
4459 }
4460
4461 /* Remove a filter.
4462  * If !by_index, remove by ID
4463  * If by_index, remove by index
4464  * Filter ID may come from userland and must be range-checked.
4465  */
4466 static int efx_ef10_filter_remove_internal(struct efx_nic *efx,
4467                                            unsigned int priority_mask,
4468                                            u32 filter_id, bool by_index)
4469 {
4470         unsigned int filter_idx = efx_ef10_filter_get_unsafe_id(filter_id);
4471         struct efx_ef10_filter_table *table = efx->filter_state;
4472         MCDI_DECLARE_BUF(inbuf,
4473                          MC_CMD_FILTER_OP_IN_HANDLE_OFST +
4474                          MC_CMD_FILTER_OP_IN_HANDLE_LEN);
4475         struct efx_filter_spec *spec;
4476         DEFINE_WAIT(wait);
4477         int rc;
4478
4479         /* Find the software table entry and mark it busy.  Don't
4480          * remove it yet; any attempt to update while we're waiting
4481          * for the firmware must find the busy entry.
4482          */
4483         for (;;) {
4484                 spin_lock_bh(&efx->filter_lock);
4485                 if (!(table->entry[filter_idx].spec &
4486                       EFX_EF10_FILTER_FLAG_BUSY))
4487                         break;
4488                 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
4489                 spin_unlock_bh(&efx->filter_lock);
4490                 schedule();
4491         }
4492
4493         spec = efx_ef10_filter_entry_spec(table, filter_idx);
4494         if (!spec ||
4495             (!by_index &&
4496              efx_ef10_filter_pri(table, spec) !=
4497              efx_ef10_filter_get_unsafe_pri(filter_id))) {
4498                 rc = -ENOENT;
4499                 goto out_unlock;
4500         }
4501
4502         if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO &&
4503             priority_mask == (1U << EFX_FILTER_PRI_AUTO)) {
4504                 /* Just remove flags */
4505                 spec->flags &= ~EFX_FILTER_FLAG_RX_OVER_AUTO;
4506                 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
4507                 rc = 0;
4508                 goto out_unlock;
4509         }
4510
4511         if (!(priority_mask & (1U << spec->priority))) {
4512                 rc = -ENOENT;
4513                 goto out_unlock;
4514         }
4515
4516         table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
4517         spin_unlock_bh(&efx->filter_lock);
4518
4519         if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO) {
4520                 /* Reset to an automatic filter */
4521
4522                 struct efx_filter_spec new_spec = *spec;
4523
4524                 new_spec.priority = EFX_FILTER_PRI_AUTO;
4525                 new_spec.flags = (EFX_FILTER_FLAG_RX |
4526                                   (efx_rss_enabled(efx) ?
4527                                    EFX_FILTER_FLAG_RX_RSS : 0));
4528                 new_spec.dmaq_id = 0;
4529                 new_spec.rss_context = EFX_FILTER_RSS_CONTEXT_DEFAULT;
4530                 rc = efx_ef10_filter_push(efx, &new_spec,
4531                                           &table->entry[filter_idx].handle,
4532                                           true);
4533
4534                 spin_lock_bh(&efx->filter_lock);
4535                 if (rc == 0)
4536                         *spec = new_spec;
4537         } else {
4538                 /* Really remove the filter */
4539
4540                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
4541                                efx_ef10_filter_is_exclusive(spec) ?
4542                                MC_CMD_FILTER_OP_IN_OP_REMOVE :
4543                                MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
4544                 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
4545                                table->entry[filter_idx].handle);
4546                 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FILTER_OP,
4547                                         inbuf, sizeof(inbuf), NULL, 0, NULL);
4548
4549                 spin_lock_bh(&efx->filter_lock);
4550                 if ((rc == 0) || (rc == -ENOENT)) {
4551                         /* Filter removed OK or didn't actually exist */
4552                         kfree(spec);
4553                         efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
4554                 } else {
4555                         efx_mcdi_display_error(efx, MC_CMD_FILTER_OP,
4556                                                MC_CMD_FILTER_OP_EXT_IN_LEN,
4557                                                NULL, 0, rc);
4558                 }
4559         }
4560
4561         table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
4562         wake_up_all(&table->waitq);
4563 out_unlock:
4564         spin_unlock_bh(&efx->filter_lock);
4565         finish_wait(&table->waitq, &wait);
4566         return rc;
4567 }
4568
4569 static int efx_ef10_filter_remove_safe(struct efx_nic *efx,
4570                                        enum efx_filter_priority priority,
4571                                        u32 filter_id)
4572 {
4573         return efx_ef10_filter_remove_internal(efx, 1U << priority,
4574                                                filter_id, false);
4575 }
4576
4577 static void efx_ef10_filter_remove_unsafe(struct efx_nic *efx,
4578                                           enum efx_filter_priority priority,
4579                                           u32 filter_id)
4580 {
4581         if (filter_id == EFX_EF10_FILTER_ID_INVALID)
4582                 return;
4583         efx_ef10_filter_remove_internal(efx, 1U << priority, filter_id, true);
4584 }
4585
4586 static int efx_ef10_filter_get_safe(struct efx_nic *efx,
4587                                     enum efx_filter_priority priority,
4588                                     u32 filter_id, struct efx_filter_spec *spec)
4589 {
4590         unsigned int filter_idx = efx_ef10_filter_get_unsafe_id(filter_id);
4591         struct efx_ef10_filter_table *table = efx->filter_state;
4592         const struct efx_filter_spec *saved_spec;
4593         int rc;
4594
4595         spin_lock_bh(&efx->filter_lock);
4596         saved_spec = efx_ef10_filter_entry_spec(table, filter_idx);
4597         if (saved_spec && saved_spec->priority == priority &&
4598             efx_ef10_filter_pri(table, saved_spec) ==
4599             efx_ef10_filter_get_unsafe_pri(filter_id)) {
4600                 *spec = *saved_spec;
4601                 rc = 0;
4602         } else {
4603                 rc = -ENOENT;
4604         }
4605         spin_unlock_bh(&efx->filter_lock);
4606         return rc;
4607 }
4608
4609 static int efx_ef10_filter_clear_rx(struct efx_nic *efx,
4610                                      enum efx_filter_priority priority)
4611 {
4612         unsigned int priority_mask;
4613         unsigned int i;
4614         int rc;
4615
4616         priority_mask = (((1U << (priority + 1)) - 1) &
4617                          ~(1U << EFX_FILTER_PRI_AUTO));
4618
4619         for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
4620                 rc = efx_ef10_filter_remove_internal(efx, priority_mask,
4621                                                      i, true);
4622                 if (rc && rc != -ENOENT)
4623                         return rc;
4624         }
4625
4626         return 0;
4627 }
4628
4629 static u32 efx_ef10_filter_count_rx_used(struct efx_nic *efx,
4630                                          enum efx_filter_priority priority)
4631 {
4632         struct efx_ef10_filter_table *table = efx->filter_state;
4633         unsigned int filter_idx;
4634         s32 count = 0;
4635
4636         spin_lock_bh(&efx->filter_lock);
4637         for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
4638                 if (table->entry[filter_idx].spec &&
4639                     efx_ef10_filter_entry_spec(table, filter_idx)->priority ==
4640                     priority)
4641                         ++count;
4642         }
4643         spin_unlock_bh(&efx->filter_lock);
4644         return count;
4645 }
4646
4647 static u32 efx_ef10_filter_get_rx_id_limit(struct efx_nic *efx)
4648 {
4649         struct efx_ef10_filter_table *table = efx->filter_state;
4650
4651         return table->rx_match_count * HUNT_FILTER_TBL_ROWS * 2;
4652 }
4653
4654 static s32 efx_ef10_filter_get_rx_ids(struct efx_nic *efx,
4655                                       enum efx_filter_priority priority,
4656                                       u32 *buf, u32 size)
4657 {
4658         struct efx_ef10_filter_table *table = efx->filter_state;
4659         struct efx_filter_spec *spec;
4660         unsigned int filter_idx;
4661         s32 count = 0;
4662
4663         spin_lock_bh(&efx->filter_lock);
4664         for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
4665                 spec = efx_ef10_filter_entry_spec(table, filter_idx);
4666                 if (spec && spec->priority == priority) {
4667                         if (count == size) {
4668                                 count = -EMSGSIZE;
4669                                 break;
4670                         }
4671                         buf[count++] =
4672                                 efx_ef10_make_filter_id(
4673                                         efx_ef10_filter_pri(table, spec),
4674                                         filter_idx);
4675                 }
4676         }
4677         spin_unlock_bh(&efx->filter_lock);
4678         return count;
4679 }
4680
4681 #ifdef CONFIG_RFS_ACCEL
4682
4683 static efx_mcdi_async_completer efx_ef10_filter_rfs_insert_complete;
4684
4685 static s32 efx_ef10_filter_rfs_insert(struct efx_nic *efx,
4686                                       struct efx_filter_spec *spec)
4687 {
4688         struct efx_ef10_filter_table *table = efx->filter_state;
4689         MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_EXT_IN_LEN);
4690         struct efx_filter_spec *saved_spec;
4691         unsigned int hash, i, depth = 1;
4692         bool replacing = false;
4693         int ins_index = -1;
4694         u64 cookie;
4695         s32 rc;
4696
4697         /* Must be an RX filter without RSS and not for a multicast
4698          * destination address (RFS only works for connected sockets).
4699          * These restrictions allow us to pass only a tiny amount of
4700          * data through to the completion function.
4701          */
4702         EFX_WARN_ON_PARANOID(spec->flags !=
4703                              (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_RX_SCATTER));
4704         EFX_WARN_ON_PARANOID(spec->priority != EFX_FILTER_PRI_HINT);
4705         EFX_WARN_ON_PARANOID(efx_filter_is_mc_recipient(spec));
4706
4707         hash = efx_ef10_filter_hash(spec);
4708
4709         spin_lock_bh(&efx->filter_lock);
4710
4711         /* Find any existing filter with the same match tuple or else
4712          * a free slot to insert at.  If an existing filter is busy,
4713          * we have to give up.
4714          */
4715         for (;;) {
4716                 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
4717                 saved_spec = efx_ef10_filter_entry_spec(table, i);
4718
4719                 if (!saved_spec) {
4720                         if (ins_index < 0)
4721                                 ins_index = i;
4722                 } else if (efx_ef10_filter_equal(spec, saved_spec)) {
4723                         if (table->entry[i].spec & EFX_EF10_FILTER_FLAG_BUSY) {
4724                                 rc = -EBUSY;
4725                                 goto fail_unlock;
4726                         }
4727                         if (spec->priority < saved_spec->priority) {
4728                                 rc = -EPERM;
4729                                 goto fail_unlock;
4730                         }
4731                         ins_index = i;
4732                         break;
4733                 }
4734
4735                 /* Once we reach the maximum search depth, use the
4736                  * first suitable slot or return -EBUSY if there was
4737                  * none
4738                  */
4739                 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
4740                         if (ins_index < 0) {
4741                                 rc = -EBUSY;
4742                                 goto fail_unlock;
4743                         }
4744                         break;
4745                 }
4746
4747                 ++depth;
4748         }
4749
4750         /* Create a software table entry if necessary, and mark it
4751          * busy.  We might yet fail to insert, but any attempt to
4752          * insert a conflicting filter while we're waiting for the
4753          * firmware must find the busy entry.
4754          */
4755         saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
4756         if (saved_spec) {
4757                 replacing = true;
4758         } else {
4759                 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
4760                 if (!saved_spec) {
4761                         rc = -ENOMEM;
4762                         goto fail_unlock;
4763                 }
4764                 *saved_spec = *spec;
4765         }
4766         efx_ef10_filter_set_entry(table, ins_index, saved_spec,
4767                                   EFX_EF10_FILTER_FLAG_BUSY);
4768
4769         spin_unlock_bh(&efx->filter_lock);
4770
4771         /* Pack up the variables needed on completion */
4772         cookie = replacing << 31 | ins_index << 16 | spec->dmaq_id;
4773
4774         efx_ef10_filter_push_prep(efx, spec, inbuf,
4775                                   table->entry[ins_index].handle, replacing);
4776         efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
4777                            MC_CMD_FILTER_OP_OUT_LEN,
4778                            efx_ef10_filter_rfs_insert_complete, cookie);
4779
4780         return ins_index;
4781
4782 fail_unlock:
4783         spin_unlock_bh(&efx->filter_lock);
4784         return rc;
4785 }
4786
4787 static void
4788 efx_ef10_filter_rfs_insert_complete(struct efx_nic *efx, unsigned long cookie,
4789                                     int rc, efx_dword_t *outbuf,
4790                                     size_t outlen_actual)
4791 {
4792         struct efx_ef10_filter_table *table = efx->filter_state;
4793         unsigned int ins_index, dmaq_id;
4794         struct efx_filter_spec *spec;
4795         bool replacing;
4796
4797         /* Unpack the cookie */
4798         replacing = cookie >> 31;
4799         ins_index = (cookie >> 16) & (HUNT_FILTER_TBL_ROWS - 1);
4800         dmaq_id = cookie & 0xffff;
4801
4802         spin_lock_bh(&efx->filter_lock);
4803         spec = efx_ef10_filter_entry_spec(table, ins_index);
4804         if (rc == 0) {
4805                 table->entry[ins_index].handle =
4806                         MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
4807                 if (replacing)
4808                         spec->dmaq_id = dmaq_id;
4809         } else if (!replacing) {
4810                 kfree(spec);
4811                 spec = NULL;
4812         }
4813         efx_ef10_filter_set_entry(table, ins_index, spec, 0);
4814         spin_unlock_bh(&efx->filter_lock);
4815
4816         wake_up_all(&table->waitq);
4817 }
4818
4819 static void
4820 efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
4821                                     unsigned long filter_idx,
4822                                     int rc, efx_dword_t *outbuf,
4823                                     size_t outlen_actual);
4824
4825 static bool efx_ef10_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id,
4826                                            unsigned int filter_idx)
4827 {
4828         struct efx_ef10_filter_table *table = efx->filter_state;
4829         struct efx_filter_spec *spec =
4830                 efx_ef10_filter_entry_spec(table, filter_idx);
4831         MCDI_DECLARE_BUF(inbuf,
4832                          MC_CMD_FILTER_OP_IN_HANDLE_OFST +
4833                          MC_CMD_FILTER_OP_IN_HANDLE_LEN);
4834
4835         if (!spec ||
4836             (table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAG_BUSY) ||
4837             spec->priority != EFX_FILTER_PRI_HINT ||
4838             !rps_may_expire_flow(efx->net_dev, spec->dmaq_id,
4839                                  flow_id, filter_idx))
4840                 return false;
4841
4842         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
4843                        MC_CMD_FILTER_OP_IN_OP_REMOVE);
4844         MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
4845                        table->entry[filter_idx].handle);
4846         if (efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), 0,
4847                                efx_ef10_filter_rfs_expire_complete, filter_idx))
4848                 return false;
4849
4850         table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
4851         return true;
4852 }
4853
4854 static void
4855 efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
4856                                     unsigned long filter_idx,
4857                                     int rc, efx_dword_t *outbuf,
4858                                     size_t outlen_actual)
4859 {
4860         struct efx_ef10_filter_table *table = efx->filter_state;
4861         struct efx_filter_spec *spec =
4862                 efx_ef10_filter_entry_spec(table, filter_idx);
4863
4864         spin_lock_bh(&efx->filter_lock);
4865         if (rc == 0) {
4866                 kfree(spec);
4867                 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
4868         }
4869         table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
4870         wake_up_all(&table->waitq);
4871         spin_unlock_bh(&efx->filter_lock);
4872 }
4873
4874 #endif /* CONFIG_RFS_ACCEL */
4875
4876 static int efx_ef10_filter_match_flags_from_mcdi(bool encap, u32 mcdi_flags)
4877 {
4878         int match_flags = 0;
4879
4880 #define MAP_FLAG(gen_flag, mcdi_field) do {                             \
4881                 u32 old_mcdi_flags = mcdi_flags;                        \
4882                 mcdi_flags &= ~(1 << MC_CMD_FILTER_OP_EXT_IN_MATCH_ ##  \
4883                                      mcdi_field ## _LBN);               \
4884                 if (mcdi_flags != old_mcdi_flags)                       \
4885                         match_flags |= EFX_FILTER_MATCH_ ## gen_flag;   \
4886         } while (0)
4887
4888         if (encap) {
4889                 /* encap filters must specify encap type */
4890                 match_flags |= EFX_FILTER_MATCH_ENCAP_TYPE;
4891                 /* and imply ethertype and ip proto */
4892                 mcdi_flags &=
4893                         ~(1 << MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_LBN);
4894                 mcdi_flags &=
4895                         ~(1 << MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_LBN);
4896                 /* VLAN tags refer to the outer packet */
4897                 MAP_FLAG(INNER_VID, INNER_VLAN);
4898                 MAP_FLAG(OUTER_VID, OUTER_VLAN);
4899                 /* everything else refers to the inner packet */
4900                 MAP_FLAG(LOC_MAC_IG, IFRM_UNKNOWN_UCAST_DST);
4901                 MAP_FLAG(LOC_MAC_IG, IFRM_UNKNOWN_MCAST_DST);
4902                 MAP_FLAG(REM_HOST, IFRM_SRC_IP);
4903                 MAP_FLAG(LOC_HOST, IFRM_DST_IP);
4904                 MAP_FLAG(REM_MAC, IFRM_SRC_MAC);
4905                 MAP_FLAG(REM_PORT, IFRM_SRC_PORT);
4906                 MAP_FLAG(LOC_MAC, IFRM_DST_MAC);
4907                 MAP_FLAG(LOC_PORT, IFRM_DST_PORT);
4908                 MAP_FLAG(ETHER_TYPE, IFRM_ETHER_TYPE);
4909                 MAP_FLAG(IP_PROTO, IFRM_IP_PROTO);
4910         } else {
4911                 MAP_FLAG(LOC_MAC_IG, UNKNOWN_UCAST_DST);
4912                 MAP_FLAG(LOC_MAC_IG, UNKNOWN_MCAST_DST);
4913                 MAP_FLAG(REM_HOST, SRC_IP);
4914                 MAP_FLAG(LOC_HOST, DST_IP);
4915                 MAP_FLAG(REM_MAC, SRC_MAC);
4916                 MAP_FLAG(REM_PORT, SRC_PORT);
4917                 MAP_FLAG(LOC_MAC, DST_MAC);
4918                 MAP_FLAG(LOC_PORT, DST_PORT);
4919                 MAP_FLAG(ETHER_TYPE, ETHER_TYPE);
4920                 MAP_FLAG(INNER_VID, INNER_VLAN);
4921                 MAP_FLAG(OUTER_VID, OUTER_VLAN);
4922                 MAP_FLAG(IP_PROTO, IP_PROTO);
4923         }
4924 #undef MAP_FLAG
4925
4926         /* Did we map them all? */
4927         if (mcdi_flags)
4928                 return -EINVAL;
4929
4930         return match_flags;
4931 }
4932
4933 static void efx_ef10_filter_cleanup_vlans(struct efx_nic *efx)
4934 {
4935         struct efx_ef10_filter_table *table = efx->filter_state;
4936         struct efx_ef10_filter_vlan *vlan, *next_vlan;
4937
4938         /* See comment in efx_ef10_filter_table_remove() */
4939         if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
4940                 return;
4941
4942         if (!table)
4943                 return;
4944
4945         list_for_each_entry_safe(vlan, next_vlan, &table->vlan_list, list)
4946                 efx_ef10_filter_del_vlan_internal(efx, vlan);
4947 }
4948
4949 static bool efx_ef10_filter_match_supported(struct efx_ef10_filter_table *table,
4950                                             bool encap,
4951                                             enum efx_filter_match_flags match_flags)
4952 {
4953         unsigned int match_pri;
4954         int mf;
4955
4956         for (match_pri = 0;
4957              match_pri < table->rx_match_count;
4958              match_pri++) {
4959                 mf = efx_ef10_filter_match_flags_from_mcdi(encap,
4960                                 table->rx_match_mcdi_flags[match_pri]);
4961                 if (mf == match_flags)
4962                         return true;
4963         }
4964
4965         return false;
4966 }
4967
4968 static int
4969 efx_ef10_filter_table_probe_matches(struct efx_nic *efx,
4970                                     struct efx_ef10_filter_table *table,
4971                                     bool encap)
4972 {
4973         MCDI_DECLARE_BUF(inbuf, MC_CMD_GET_PARSER_DISP_INFO_IN_LEN);
4974         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX);
4975         unsigned int pd_match_pri, pd_match_count;
4976         size_t outlen;
4977         int rc;
4978
4979         /* Find out which RX filter types are supported, and their priorities */
4980         MCDI_SET_DWORD(inbuf, GET_PARSER_DISP_INFO_IN_OP,
4981                        encap ?
4982                        MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_ENCAP_RX_MATCHES :
4983                        MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES);
4984         rc = efx_mcdi_rpc(efx, MC_CMD_GET_PARSER_DISP_INFO,
4985                           inbuf, sizeof(inbuf), outbuf, sizeof(outbuf),
4986                           &outlen);
4987         if (rc)
4988                 return rc;
4989
4990         pd_match_count = MCDI_VAR_ARRAY_LEN(
4991                 outlen, GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES);
4992
4993         for (pd_match_pri = 0; pd_match_pri < pd_match_count; pd_match_pri++) {
4994                 u32 mcdi_flags =
4995                         MCDI_ARRAY_DWORD(
4996                                 outbuf,
4997                                 GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES,
4998                                 pd_match_pri);
4999                 rc = efx_ef10_filter_match_flags_from_mcdi(encap, mcdi_flags);
5000                 if (rc < 0) {
5001                         netif_dbg(efx, probe, efx->net_dev,
5002                                   "%s: fw flags %#x pri %u not supported in driver\n",
5003                                   __func__, mcdi_flags, pd_match_pri);
5004                 } else {
5005                         netif_dbg(efx, probe, efx->net_dev,
5006                                   "%s: fw flags %#x pri %u supported as driver flags %#x pri %u\n",
5007                                   __func__, mcdi_flags, pd_match_pri,
5008                                   rc, table->rx_match_count);
5009                         table->rx_match_mcdi_flags[table->rx_match_count] = mcdi_flags;
5010                         table->rx_match_count++;
5011                 }
5012         }
5013
5014         return 0;
5015 }
5016
5017 static int efx_ef10_filter_table_probe(struct efx_nic *efx)
5018 {
5019         struct efx_ef10_nic_data *nic_data = efx->nic_data;
5020         struct net_device *net_dev = efx->net_dev;
5021         struct efx_ef10_filter_table *table;
5022         struct efx_ef10_vlan *vlan;
5023         int rc;
5024
5025         if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
5026                 return -EINVAL;
5027
5028         if (efx->filter_state) /* already probed */
5029                 return 0;
5030
5031         table = kzalloc(sizeof(*table), GFP_KERNEL);
5032         if (!table)
5033                 return -ENOMEM;
5034
5035         table->rx_match_count = 0;
5036         rc = efx_ef10_filter_table_probe_matches(efx, table, false);
5037         if (rc)
5038                 goto fail;
5039         if (nic_data->datapath_caps &
5040                    (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN))
5041                 rc = efx_ef10_filter_table_probe_matches(efx, table, true);
5042         if (rc)
5043                 goto fail;
5044         if ((efx_supported_features(efx) & NETIF_F_HW_VLAN_CTAG_FILTER) &&
5045             !(efx_ef10_filter_match_supported(table, false,
5046                 (EFX_FILTER_MATCH_OUTER_VID | EFX_FILTER_MATCH_LOC_MAC)) &&
5047               efx_ef10_filter_match_supported(table, false,
5048                 (EFX_FILTER_MATCH_OUTER_VID | EFX_FILTER_MATCH_LOC_MAC_IG)))) {
5049                 netif_info(efx, probe, net_dev,
5050                            "VLAN filters are not supported in this firmware variant\n");
5051                 net_dev->features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
5052                 efx->fixed_features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
5053                 net_dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
5054         }
5055
5056         table->entry = vzalloc(HUNT_FILTER_TBL_ROWS * sizeof(*table->entry));
5057         if (!table->entry) {
5058                 rc = -ENOMEM;
5059                 goto fail;
5060         }
5061
5062         table->mc_promisc_last = false;
5063         table->vlan_filter =
5064                 !!(efx->net_dev->features & NETIF_F_HW_VLAN_CTAG_FILTER);
5065         INIT_LIST_HEAD(&table->vlan_list);
5066
5067         efx->filter_state = table;
5068         init_waitqueue_head(&table->waitq);
5069
5070         list_for_each_entry(vlan, &nic_data->vlan_list, list) {
5071                 rc = efx_ef10_filter_add_vlan(efx, vlan->vid);
5072                 if (rc)
5073                         goto fail_add_vlan;
5074         }
5075
5076         return 0;
5077
5078 fail_add_vlan:
5079         efx_ef10_filter_cleanup_vlans(efx);
5080         efx->filter_state = NULL;
5081 fail:
5082         kfree(table);
5083         return rc;
5084 }
5085
5086 /* Caller must hold efx->filter_sem for read if race against
5087  * efx_ef10_filter_table_remove() is possible
5088  */
5089 static void efx_ef10_filter_table_restore(struct efx_nic *efx)
5090 {
5091         struct efx_ef10_filter_table *table = efx->filter_state;
5092         struct efx_ef10_nic_data *nic_data = efx->nic_data;
5093         unsigned int invalid_filters = 0, failed = 0;
5094         struct efx_ef10_filter_vlan *vlan;
5095         struct efx_filter_spec *spec;
5096         unsigned int filter_idx;
5097         u32 mcdi_flags;
5098         int match_pri;
5099         int rc, i;
5100
5101         WARN_ON(!rwsem_is_locked(&efx->filter_sem));
5102
5103         if (!nic_data->must_restore_filters)
5104                 return;
5105
5106         if (!table)
5107                 return;
5108
5109         spin_lock_bh(&efx->filter_lock);
5110
5111         for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
5112                 spec = efx_ef10_filter_entry_spec(table, filter_idx);
5113                 if (!spec)
5114                         continue;
5115
5116                 mcdi_flags = efx_ef10_filter_mcdi_flags_from_spec(spec);
5117                 match_pri = 0;
5118                 while (match_pri < table->rx_match_count &&
5119                        table->rx_match_mcdi_flags[match_pri] != mcdi_flags)
5120                         ++match_pri;
5121                 if (match_pri >= table->rx_match_count) {
5122                         invalid_filters++;
5123                         goto not_restored;
5124                 }
5125                 if (spec->rss_context != EFX_FILTER_RSS_CONTEXT_DEFAULT &&
5126                     spec->rss_context != nic_data->rx_rss_context)
5127                         netif_warn(efx, drv, efx->net_dev,
5128                                    "Warning: unable to restore a filter with specific RSS context.\n");
5129
5130                 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
5131                 spin_unlock_bh(&efx->filter_lock);
5132
5133                 rc = efx_ef10_filter_push(efx, spec,
5134                                           &table->entry[filter_idx].handle,
5135                                           false);
5136                 if (rc)
5137                         failed++;
5138                 spin_lock_bh(&efx->filter_lock);
5139
5140                 if (rc) {
5141 not_restored:
5142                         list_for_each_entry(vlan, &table->vlan_list, list)
5143                                 for (i = 0; i < EFX_EF10_NUM_DEFAULT_FILTERS; ++i)
5144                                         if (vlan->default_filters[i] == filter_idx)
5145                                                 vlan->default_filters[i] =
5146                                                         EFX_EF10_FILTER_ID_INVALID;
5147
5148                         kfree(spec);
5149                         efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
5150                 } else {
5151                         table->entry[filter_idx].spec &=
5152                                 ~EFX_EF10_FILTER_FLAG_BUSY;
5153                 }
5154         }
5155
5156         spin_unlock_bh(&efx->filter_lock);
5157
5158         /* This can happen validly if the MC's capabilities have changed, so
5159          * is not an error.
5160          */
5161         if (invalid_filters)
5162                 netif_dbg(efx, drv, efx->net_dev,
5163                           "Did not restore %u filters that are now unsupported.\n",
5164                           invalid_filters);
5165
5166         if (failed)
5167                 netif_err(efx, hw, efx->net_dev,
5168                           "unable to restore %u filters\n", failed);
5169         else
5170                 nic_data->must_restore_filters = false;
5171 }
5172
5173 static void efx_ef10_filter_table_remove(struct efx_nic *efx)
5174 {
5175         struct efx_ef10_filter_table *table = efx->filter_state;
5176         MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_EXT_IN_LEN);
5177         struct efx_filter_spec *spec;
5178         unsigned int filter_idx;
5179         int rc;
5180
5181         efx_ef10_filter_cleanup_vlans(efx);
5182         efx->filter_state = NULL;
5183         /* If we were called without locking, then it's not safe to free
5184          * the table as others might be using it.  So we just WARN, leak
5185          * the memory, and potentially get an inconsistent filter table
5186          * state.
5187          * This should never actually happen.
5188          */
5189         if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
5190                 return;
5191
5192         if (!table)
5193                 return;
5194
5195         for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
5196                 spec = efx_ef10_filter_entry_spec(table, filter_idx);
5197                 if (!spec)
5198                         continue;
5199
5200                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
5201                                efx_ef10_filter_is_exclusive(spec) ?
5202                                MC_CMD_FILTER_OP_IN_OP_REMOVE :
5203                                MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
5204                 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
5205                                table->entry[filter_idx].handle);
5206                 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FILTER_OP, inbuf,
5207                                         sizeof(inbuf), NULL, 0, NULL);
5208                 if (rc)
5209                         netif_info(efx, drv, efx->net_dev,
5210                                    "%s: filter %04x remove failed\n",
5211                                    __func__, filter_idx);
5212                 kfree(spec);
5213         }
5214
5215         vfree(table->entry);
5216         kfree(table);
5217 }
5218
5219 static void efx_ef10_filter_mark_one_old(struct efx_nic *efx, uint16_t *id)
5220 {
5221         struct efx_ef10_filter_table *table = efx->filter_state;
5222         unsigned int filter_idx;
5223
5224         if (*id != EFX_EF10_FILTER_ID_INVALID) {
5225                 filter_idx = efx_ef10_filter_get_unsafe_id(*id);
5226                 if (!table->entry[filter_idx].spec)
5227                         netif_dbg(efx, drv, efx->net_dev,
5228                                   "marked null spec old %04x:%04x\n", *id,
5229                                   filter_idx);
5230                 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_AUTO_OLD;
5231                 *id = EFX_EF10_FILTER_ID_INVALID;
5232         }
5233 }
5234
5235 /* Mark old per-VLAN filters that may need to be removed */
5236 static void _efx_ef10_filter_vlan_mark_old(struct efx_nic *efx,
5237                                            struct efx_ef10_filter_vlan *vlan)
5238 {
5239         struct efx_ef10_filter_table *table = efx->filter_state;
5240         unsigned int i;
5241
5242         for (i = 0; i < table->dev_uc_count; i++)
5243                 efx_ef10_filter_mark_one_old(efx, &vlan->uc[i]);
5244         for (i = 0; i < table->dev_mc_count; i++)
5245                 efx_ef10_filter_mark_one_old(efx, &vlan->mc[i]);
5246         for (i = 0; i < EFX_EF10_NUM_DEFAULT_FILTERS; i++)
5247                 efx_ef10_filter_mark_one_old(efx, &vlan->default_filters[i]);
5248 }
5249
5250 /* Mark old filters that may need to be removed.
5251  * Caller must hold efx->filter_sem for read if race against
5252  * efx_ef10_filter_table_remove() is possible
5253  */
5254 static void efx_ef10_filter_mark_old(struct efx_nic *efx)
5255 {
5256         struct efx_ef10_filter_table *table = efx->filter_state;
5257         struct efx_ef10_filter_vlan *vlan;
5258
5259         spin_lock_bh(&efx->filter_lock);
5260         list_for_each_entry(vlan, &table->vlan_list, list)
5261                 _efx_ef10_filter_vlan_mark_old(efx, vlan);
5262         spin_unlock_bh(&efx->filter_lock);
5263 }
5264
5265 static void efx_ef10_filter_uc_addr_list(struct efx_nic *efx)
5266 {
5267         struct efx_ef10_filter_table *table = efx->filter_state;
5268         struct net_device *net_dev = efx->net_dev;
5269         struct netdev_hw_addr *uc;
5270         unsigned int i;
5271
5272         table->uc_promisc = !!(net_dev->flags & IFF_PROMISC);
5273         ether_addr_copy(table->dev_uc_list[0].addr, net_dev->dev_addr);
5274         i = 1;
5275         netdev_for_each_uc_addr(uc, net_dev) {
5276                 if (i >= EFX_EF10_FILTER_DEV_UC_MAX) {
5277                         table->uc_promisc = true;
5278                         break;
5279                 }
5280                 ether_addr_copy(table->dev_uc_list[i].addr, uc->addr);
5281                 i++;
5282         }
5283
5284         table->dev_uc_count = i;
5285 }
5286
5287 static void efx_ef10_filter_mc_addr_list(struct efx_nic *efx)
5288 {
5289         struct efx_ef10_filter_table *table = efx->filter_state;
5290         struct net_device *net_dev = efx->net_dev;
5291         struct netdev_hw_addr *mc;
5292         unsigned int i;
5293
5294         table->mc_overflow = false;
5295         table->mc_promisc = !!(net_dev->flags & (IFF_PROMISC | IFF_ALLMULTI));
5296
5297         i = 0;
5298         netdev_for_each_mc_addr(mc, net_dev) {
5299                 if (i >= EFX_EF10_FILTER_DEV_MC_MAX) {
5300                         table->mc_promisc = true;
5301                         table->mc_overflow = true;
5302                         break;
5303                 }
5304                 ether_addr_copy(table->dev_mc_list[i].addr, mc->addr);
5305                 i++;
5306         }
5307
5308         table->dev_mc_count = i;
5309 }
5310
5311 static int efx_ef10_filter_insert_addr_list(struct efx_nic *efx,
5312                                             struct efx_ef10_filter_vlan *vlan,
5313                                             bool multicast, bool rollback)
5314 {
5315         struct efx_ef10_filter_table *table = efx->filter_state;
5316         struct efx_ef10_dev_addr *addr_list;
5317         enum efx_filter_flags filter_flags;
5318         struct efx_filter_spec spec;
5319         u8 baddr[ETH_ALEN];
5320         unsigned int i, j;
5321         int addr_count;
5322         u16 *ids;
5323         int rc;
5324
5325         if (multicast) {
5326                 addr_list = table->dev_mc_list;
5327                 addr_count = table->dev_mc_count;
5328                 ids = vlan->mc;
5329         } else {
5330                 addr_list = table->dev_uc_list;
5331                 addr_count = table->dev_uc_count;
5332                 ids = vlan->uc;
5333         }
5334
5335         filter_flags = efx_rss_enabled(efx) ? EFX_FILTER_FLAG_RX_RSS : 0;
5336
5337         /* Insert/renew filters */
5338         for (i = 0; i < addr_count; i++) {
5339                 EFX_WARN_ON_PARANOID(ids[i] != EFX_EF10_FILTER_ID_INVALID);
5340                 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0);
5341                 efx_filter_set_eth_local(&spec, vlan->vid, addr_list[i].addr);
5342                 rc = efx_ef10_filter_insert(efx, &spec, true);
5343                 if (rc < 0) {
5344                         if (rollback) {
5345                                 netif_info(efx, drv, efx->net_dev,
5346                                            "efx_ef10_filter_insert failed rc=%d\n",
5347                                            rc);
5348                                 /* Fall back to promiscuous */
5349                                 for (j = 0; j < i; j++) {
5350                                         efx_ef10_filter_remove_unsafe(
5351                                                 efx, EFX_FILTER_PRI_AUTO,
5352                                                 ids[j]);
5353                                         ids[j] = EFX_EF10_FILTER_ID_INVALID;
5354                                 }
5355                                 return rc;
5356                         } else {
5357                                 /* keep invalid ID, and carry on */
5358                         }
5359                 } else {
5360                         ids[i] = efx_ef10_filter_get_unsafe_id(rc);
5361                 }
5362         }
5363
5364         if (multicast && rollback) {
5365                 /* Also need an Ethernet broadcast filter */
5366                 EFX_WARN_ON_PARANOID(vlan->default_filters[EFX_EF10_BCAST] !=
5367                                      EFX_EF10_FILTER_ID_INVALID);
5368                 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0);
5369                 eth_broadcast_addr(baddr);
5370                 efx_filter_set_eth_local(&spec, vlan->vid, baddr);
5371                 rc = efx_ef10_filter_insert(efx, &spec, true);
5372                 if (rc < 0) {
5373                         netif_warn(efx, drv, efx->net_dev,
5374                                    "Broadcast filter insert failed rc=%d\n", rc);
5375                         /* Fall back to promiscuous */
5376                         for (j = 0; j < i; j++) {
5377                                 efx_ef10_filter_remove_unsafe(
5378                                         efx, EFX_FILTER_PRI_AUTO,
5379                                         ids[j]);
5380                                 ids[j] = EFX_EF10_FILTER_ID_INVALID;
5381                         }
5382                         return rc;
5383                 } else {
5384                         vlan->default_filters[EFX_EF10_BCAST] =
5385                                 efx_ef10_filter_get_unsafe_id(rc);
5386                 }
5387         }
5388
5389         return 0;
5390 }
5391
5392 static int efx_ef10_filter_insert_def(struct efx_nic *efx,
5393                                       struct efx_ef10_filter_vlan *vlan,
5394                                       enum efx_encap_type encap_type,
5395                                       bool multicast, bool rollback)
5396 {
5397         struct efx_ef10_nic_data *nic_data = efx->nic_data;
5398         enum efx_filter_flags filter_flags;
5399         struct efx_filter_spec spec;
5400         u8 baddr[ETH_ALEN];
5401         int rc;
5402         u16 *id;
5403
5404         filter_flags = efx_rss_enabled(efx) ? EFX_FILTER_FLAG_RX_RSS : 0;
5405
5406         efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0);
5407
5408         if (multicast)
5409                 efx_filter_set_mc_def(&spec);
5410         else
5411                 efx_filter_set_uc_def(&spec);
5412
5413         if (encap_type) {
5414                 if (nic_data->datapath_caps &
5415                     (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN))
5416                         efx_filter_set_encap_type(&spec, encap_type);
5417                 else
5418                         /* don't insert encap filters on non-supporting
5419                          * platforms. ID will be left as INVALID.
5420                          */
5421                         return 0;
5422         }
5423
5424         if (vlan->vid != EFX_FILTER_VID_UNSPEC)
5425                 efx_filter_set_eth_local(&spec, vlan->vid, NULL);
5426
5427         rc = efx_ef10_filter_insert(efx, &spec, true);
5428         if (rc < 0) {
5429                 const char *um = multicast ? "Multicast" : "Unicast";
5430                 const char *encap_name = "";
5431                 const char *encap_ipv = "";
5432
5433                 if ((encap_type & EFX_ENCAP_TYPES_MASK) ==
5434                     EFX_ENCAP_TYPE_VXLAN)
5435                         encap_name = "VXLAN ";
5436                 else if ((encap_type & EFX_ENCAP_TYPES_MASK) ==
5437                          EFX_ENCAP_TYPE_NVGRE)
5438                         encap_name = "NVGRE ";
5439                 else if ((encap_type & EFX_ENCAP_TYPES_MASK) ==
5440                          EFX_ENCAP_TYPE_GENEVE)
5441                         encap_name = "GENEVE ";
5442                 if (encap_type & EFX_ENCAP_FLAG_IPV6)
5443                         encap_ipv = "IPv6 ";
5444                 else if (encap_type)
5445                         encap_ipv = "IPv4 ";
5446
5447                 /* unprivileged functions can't insert mismatch filters
5448                  * for encapsulated or unicast traffic, so downgrade
5449                  * those warnings to debug.
5450                  */
5451                 netif_cond_dbg(efx, drv, efx->net_dev,
5452                                rc == -EPERM && (encap_type || !multicast), warn,
5453                                "%s%s%s mismatch filter insert failed rc=%d\n",
5454                                encap_name, encap_ipv, um, rc);
5455         } else if (multicast) {
5456                 /* mapping from encap types to default filter IDs (multicast) */
5457                 static enum efx_ef10_default_filters map[] = {
5458                         [EFX_ENCAP_TYPE_NONE] = EFX_EF10_MCDEF,
5459                         [EFX_ENCAP_TYPE_VXLAN] = EFX_EF10_VXLAN4_MCDEF,
5460                         [EFX_ENCAP_TYPE_NVGRE] = EFX_EF10_NVGRE4_MCDEF,
5461                         [EFX_ENCAP_TYPE_GENEVE] = EFX_EF10_GENEVE4_MCDEF,
5462                         [EFX_ENCAP_TYPE_VXLAN | EFX_ENCAP_FLAG_IPV6] =
5463                                 EFX_EF10_VXLAN6_MCDEF,
5464                         [EFX_ENCAP_TYPE_NVGRE | EFX_ENCAP_FLAG_IPV6] =
5465                                 EFX_EF10_NVGRE6_MCDEF,
5466                         [EFX_ENCAP_TYPE_GENEVE | EFX_ENCAP_FLAG_IPV6] =
5467                                 EFX_EF10_GENEVE6_MCDEF,
5468                 };
5469
5470                 /* quick bounds check (BCAST result impossible) */
5471                 BUILD_BUG_ON(EFX_EF10_BCAST != 0);
5472                 if (encap_type >= ARRAY_SIZE(map) || map[encap_type] == 0) {
5473                         WARN_ON(1);
5474                         return -EINVAL;
5475                 }
5476                 /* then follow map */
5477                 id = &vlan->default_filters[map[encap_type]];
5478
5479                 EFX_WARN_ON_PARANOID(*id != EFX_EF10_FILTER_ID_INVALID);
5480                 *id = efx_ef10_filter_get_unsafe_id(rc);
5481                 if (!nic_data->workaround_26807 && !encap_type) {
5482                         /* Also need an Ethernet broadcast filter */
5483                         efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
5484                                            filter_flags, 0);
5485                         eth_broadcast_addr(baddr);
5486                         efx_filter_set_eth_local(&spec, vlan->vid, baddr);
5487                         rc = efx_ef10_filter_insert(efx, &spec, true);
5488                         if (rc < 0) {
5489                                 netif_warn(efx, drv, efx->net_dev,
5490                                            "Broadcast filter insert failed rc=%d\n",
5491                                            rc);
5492                                 if (rollback) {
5493                                         /* Roll back the mc_def filter */
5494                                         efx_ef10_filter_remove_unsafe(
5495                                                         efx, EFX_FILTER_PRI_AUTO,
5496                                                         *id);
5497                                         *id = EFX_EF10_FILTER_ID_INVALID;
5498                                         return rc;
5499                                 }
5500                         } else {
5501                                 EFX_WARN_ON_PARANOID(
5502                                         vlan->default_filters[EFX_EF10_BCAST] !=
5503                                         EFX_EF10_FILTER_ID_INVALID);
5504                                 vlan->default_filters[EFX_EF10_BCAST] =
5505                                         efx_ef10_filter_get_unsafe_id(rc);
5506                         }
5507                 }
5508                 rc = 0;
5509         } else {
5510                 /* mapping from encap types to default filter IDs (unicast) */
5511                 static enum efx_ef10_default_filters map[] = {
5512                         [EFX_ENCAP_TYPE_NONE] = EFX_EF10_UCDEF,
5513                         [EFX_ENCAP_TYPE_VXLAN] = EFX_EF10_VXLAN4_UCDEF,
5514                         [EFX_ENCAP_TYPE_NVGRE] = EFX_EF10_NVGRE4_UCDEF,
5515                         [EFX_ENCAP_TYPE_GENEVE] = EFX_EF10_GENEVE4_UCDEF,
5516                         [EFX_ENCAP_TYPE_VXLAN | EFX_ENCAP_FLAG_IPV6] =
5517                                 EFX_EF10_VXLAN6_UCDEF,
5518                         [EFX_ENCAP_TYPE_NVGRE | EFX_ENCAP_FLAG_IPV6] =
5519                                 EFX_EF10_NVGRE6_UCDEF,
5520                         [EFX_ENCAP_TYPE_GENEVE | EFX_ENCAP_FLAG_IPV6] =
5521                                 EFX_EF10_GENEVE6_UCDEF,
5522                 };
5523
5524                 /* quick bounds check (BCAST result impossible) */
5525                 BUILD_BUG_ON(EFX_EF10_BCAST != 0);
5526                 if (encap_type >= ARRAY_SIZE(map) || map[encap_type] == 0) {
5527                         WARN_ON(1);
5528                         return -EINVAL;
5529                 }
5530                 /* then follow map */
5531                 id = &vlan->default_filters[map[encap_type]];
5532                 EFX_WARN_ON_PARANOID(*id != EFX_EF10_FILTER_ID_INVALID);
5533                 *id = rc;
5534                 rc = 0;
5535         }
5536         return rc;
5537 }
5538
5539 /* Remove filters that weren't renewed.  Since nothing else changes the AUTO_OLD
5540  * flag or removes these filters, we don't need to hold the filter_lock while
5541  * scanning for these filters.
5542  */
5543 static void efx_ef10_filter_remove_old(struct efx_nic *efx)
5544 {
5545         struct efx_ef10_filter_table *table = efx->filter_state;
5546         int remove_failed = 0;
5547         int remove_noent = 0;
5548         int rc;
5549         int i;
5550
5551         for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
5552                 if (READ_ONCE(table->entry[i].spec) &
5553                     EFX_EF10_FILTER_FLAG_AUTO_OLD) {
5554                         rc = efx_ef10_filter_remove_internal(efx,
5555                                         1U << EFX_FILTER_PRI_AUTO, i, true);
5556                         if (rc == -ENOENT)
5557                                 remove_noent++;
5558                         else if (rc)
5559                                 remove_failed++;
5560                 }
5561         }
5562
5563         if (remove_failed)
5564                 netif_info(efx, drv, efx->net_dev,
5565                            "%s: failed to remove %d filters\n",
5566                            __func__, remove_failed);
5567         if (remove_noent)
5568                 netif_info(efx, drv, efx->net_dev,
5569                            "%s: failed to remove %d non-existent filters\n",
5570                            __func__, remove_noent);
5571 }
5572
5573 static int efx_ef10_vport_set_mac_address(struct efx_nic *efx)
5574 {
5575         struct efx_ef10_nic_data *nic_data = efx->nic_data;
5576         u8 mac_old[ETH_ALEN];
5577         int rc, rc2;
5578
5579         /* Only reconfigure a PF-created vport */
5580         if (is_zero_ether_addr(nic_data->vport_mac))
5581                 return 0;
5582
5583         efx_device_detach_sync(efx);
5584         efx_net_stop(efx->net_dev);
5585         down_write(&efx->filter_sem);
5586         efx_ef10_filter_table_remove(efx);
5587         up_write(&efx->filter_sem);
5588
5589         rc = efx_ef10_vadaptor_free(efx, nic_data->vport_id);
5590         if (rc)
5591                 goto restore_filters;
5592
5593         ether_addr_copy(mac_old, nic_data->vport_mac);
5594         rc = efx_ef10_vport_del_mac(efx, nic_data->vport_id,
5595                                     nic_data->vport_mac);
5596         if (rc)
5597                 goto restore_vadaptor;
5598
5599         rc = efx_ef10_vport_add_mac(efx, nic_data->vport_id,
5600                                     efx->net_dev->dev_addr);
5601         if (!rc) {
5602                 ether_addr_copy(nic_data->vport_mac, efx->net_dev->dev_addr);
5603         } else {
5604                 rc2 = efx_ef10_vport_add_mac(efx, nic_data->vport_id, mac_old);
5605                 if (rc2) {
5606                         /* Failed to add original MAC, so clear vport_mac */
5607                         eth_zero_addr(nic_data->vport_mac);
5608                         goto reset_nic;
5609                 }
5610         }
5611
5612 restore_vadaptor:
5613         rc2 = efx_ef10_vadaptor_alloc(efx, nic_data->vport_id);
5614         if (rc2)
5615                 goto reset_nic;
5616 restore_filters:
5617         down_write(&efx->filter_sem);
5618         rc2 = efx_ef10_filter_table_probe(efx);
5619         up_write(&efx->filter_sem);
5620         if (rc2)
5621                 goto reset_nic;
5622
5623         rc2 = efx_net_open(efx->net_dev);
5624         if (rc2)
5625                 goto reset_nic;
5626
5627         efx_device_attach_if_not_resetting(efx);
5628
5629         return rc;
5630
5631 reset_nic:
5632         netif_err(efx, drv, efx->net_dev,
5633                   "Failed to restore when changing MAC address - scheduling reset\n");
5634         efx_schedule_reset(efx, RESET_TYPE_DATAPATH);
5635
5636         return rc ? rc : rc2;
5637 }
5638
5639 /* Caller must hold efx->filter_sem for read if race against
5640  * efx_ef10_filter_table_remove() is possible
5641  */
5642 static void efx_ef10_filter_vlan_sync_rx_mode(struct efx_nic *efx,
5643                                               struct efx_ef10_filter_vlan *vlan)
5644 {
5645         struct efx_ef10_filter_table *table = efx->filter_state;
5646         struct efx_ef10_nic_data *nic_data = efx->nic_data;
5647
5648         /* Do not install unspecified VID if VLAN filtering is enabled.
5649          * Do not install all specified VIDs if VLAN filtering is disabled.
5650          */
5651         if ((vlan->vid == EFX_FILTER_VID_UNSPEC) == table->vlan_filter)
5652                 return;
5653
5654         /* Insert/renew unicast filters */
5655         if (table->uc_promisc) {
5656                 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_NONE,
5657                                            false, false);
5658                 efx_ef10_filter_insert_addr_list(efx, vlan, false, false);
5659         } else {
5660                 /* If any of the filters failed to insert, fall back to
5661                  * promiscuous mode - add in the uc_def filter.  But keep
5662                  * our individual unicast filters.
5663                  */
5664                 if (efx_ef10_filter_insert_addr_list(efx, vlan, false, false))
5665                         efx_ef10_filter_insert_def(efx, vlan,
5666                                                    EFX_ENCAP_TYPE_NONE,
5667                                                    false, false);
5668         }
5669         efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_VXLAN,
5670                                    false, false);
5671         efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_VXLAN |
5672                                               EFX_ENCAP_FLAG_IPV6,
5673                                    false, false);
5674         efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_NVGRE,
5675                                    false, false);
5676         efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_NVGRE |
5677                                               EFX_ENCAP_FLAG_IPV6,
5678                                    false, false);
5679         efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_GENEVE,
5680                                    false, false);
5681         efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_GENEVE |
5682                                               EFX_ENCAP_FLAG_IPV6,
5683                                    false, false);
5684
5685         /* Insert/renew multicast filters */
5686         /* If changing promiscuous state with cascaded multicast filters, remove
5687          * old filters first, so that packets are dropped rather than duplicated
5688          */
5689         if (nic_data->workaround_26807 &&
5690             table->mc_promisc_last != table->mc_promisc)
5691                 efx_ef10_filter_remove_old(efx);
5692         if (table->mc_promisc) {
5693                 if (nic_data->workaround_26807) {
5694                         /* If we failed to insert promiscuous filters, rollback
5695                          * and fall back to individual multicast filters
5696                          */
5697                         if (efx_ef10_filter_insert_def(efx, vlan,
5698                                                        EFX_ENCAP_TYPE_NONE,
5699                                                        true, true)) {
5700                                 /* Changing promisc state, so remove old filters */
5701                                 efx_ef10_filter_remove_old(efx);
5702                                 efx_ef10_filter_insert_addr_list(efx, vlan,
5703                                                                  true, false);
5704                         }
5705                 } else {
5706                         /* If we failed to insert promiscuous filters, don't
5707                          * rollback.  Regardless, also insert the mc_list,
5708                          * unless it's incomplete due to overflow
5709                          */
5710                         efx_ef10_filter_insert_def(efx, vlan,
5711                                                    EFX_ENCAP_TYPE_NONE,
5712                                                    true, false);
5713                         if (!table->mc_overflow)
5714                                 efx_ef10_filter_insert_addr_list(efx, vlan,
5715                                                                  true, false);
5716                 }
5717         } else {
5718                 /* If any filters failed to insert, rollback and fall back to
5719                  * promiscuous mode - mc_def filter and maybe broadcast.  If
5720                  * that fails, roll back again and insert as many of our
5721                  * individual multicast filters as we can.
5722                  */
5723                 if (efx_ef10_filter_insert_addr_list(efx, vlan, true, true)) {
5724                         /* Changing promisc state, so remove old filters */
5725                         if (nic_data->workaround_26807)
5726                                 efx_ef10_filter_remove_old(efx);
5727                         if (efx_ef10_filter_insert_def(efx, vlan,
5728                                                        EFX_ENCAP_TYPE_NONE,
5729                                                        true, true))
5730                                 efx_ef10_filter_insert_addr_list(efx, vlan,
5731                                                                  true, false);
5732                 }
5733         }
5734         efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_VXLAN,
5735                                    true, false);
5736         efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_VXLAN |
5737                                               EFX_ENCAP_FLAG_IPV6,
5738                                    true, false);
5739         efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_NVGRE,
5740                                    true, false);
5741         efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_NVGRE |
5742                                               EFX_ENCAP_FLAG_IPV6,
5743                                    true, false);
5744         efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_GENEVE,
5745                                    true, false);
5746         efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_GENEVE |
5747                                               EFX_ENCAP_FLAG_IPV6,
5748                                    true, false);
5749 }
5750
5751 /* Caller must hold efx->filter_sem for read if race against
5752  * efx_ef10_filter_table_remove() is possible
5753  */
5754 static void efx_ef10_filter_sync_rx_mode(struct efx_nic *efx)
5755 {
5756         struct efx_ef10_filter_table *table = efx->filter_state;
5757         struct net_device *net_dev = efx->net_dev;
5758         struct efx_ef10_filter_vlan *vlan;
5759         bool vlan_filter;
5760
5761         if (!efx_dev_registered(efx))
5762                 return;
5763
5764         if (!table)
5765                 return;
5766
5767         efx_ef10_filter_mark_old(efx);
5768
5769         /* Copy/convert the address lists; add the primary station
5770          * address and broadcast address
5771          */
5772         netif_addr_lock_bh(net_dev);
5773         efx_ef10_filter_uc_addr_list(efx);
5774         efx_ef10_filter_mc_addr_list(efx);
5775         netif_addr_unlock_bh(net_dev);
5776
5777         /* If VLAN filtering changes, all old filters are finally removed.
5778          * Do it in advance to avoid conflicts for unicast untagged and
5779          * VLAN 0 tagged filters.
5780          */
5781         vlan_filter = !!(net_dev->features & NETIF_F_HW_VLAN_CTAG_FILTER);
5782         if (table->vlan_filter != vlan_filter) {
5783                 table->vlan_filter = vlan_filter;
5784                 efx_ef10_filter_remove_old(efx);
5785         }
5786
5787         list_for_each_entry(vlan, &table->vlan_list, list)
5788                 efx_ef10_filter_vlan_sync_rx_mode(efx, vlan);
5789
5790         efx_ef10_filter_remove_old(efx);
5791         table->mc_promisc_last = table->mc_promisc;
5792 }
5793
5794 static struct efx_ef10_filter_vlan *efx_ef10_filter_find_vlan(struct efx_nic *efx, u16 vid)
5795 {
5796         struct efx_ef10_filter_table *table = efx->filter_state;
5797         struct efx_ef10_filter_vlan *vlan;
5798
5799         WARN_ON(!rwsem_is_locked(&efx->filter_sem));
5800
5801         list_for_each_entry(vlan, &table->vlan_list, list) {
5802                 if (vlan->vid == vid)
5803                         return vlan;
5804         }
5805
5806         return NULL;
5807 }
5808
5809 static int efx_ef10_filter_add_vlan(struct efx_nic *efx, u16 vid)
5810 {
5811         struct efx_ef10_filter_table *table = efx->filter_state;
5812         struct efx_ef10_filter_vlan *vlan;
5813         unsigned int i;
5814
5815         if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
5816                 return -EINVAL;
5817
5818         vlan = efx_ef10_filter_find_vlan(efx, vid);
5819         if (WARN_ON(vlan)) {
5820                 netif_err(efx, drv, efx->net_dev,
5821                           "VLAN %u already added\n", vid);
5822                 return -EALREADY;
5823         }
5824
5825         vlan = kzalloc(sizeof(*vlan), GFP_KERNEL);
5826         if (!vlan)
5827                 return -ENOMEM;
5828
5829         vlan->vid = vid;
5830
5831         for (i = 0; i < ARRAY_SIZE(vlan->uc); i++)
5832                 vlan->uc[i] = EFX_EF10_FILTER_ID_INVALID;
5833         for (i = 0; i < ARRAY_SIZE(vlan->mc); i++)
5834                 vlan->mc[i] = EFX_EF10_FILTER_ID_INVALID;
5835         for (i = 0; i < EFX_EF10_NUM_DEFAULT_FILTERS; i++)
5836                 vlan->default_filters[i] = EFX_EF10_FILTER_ID_INVALID;
5837
5838         list_add_tail(&vlan->list, &table->vlan_list);
5839
5840         if (efx_dev_registered(efx))
5841                 efx_ef10_filter_vlan_sync_rx_mode(efx, vlan);
5842
5843         return 0;
5844 }
5845
5846 static void efx_ef10_filter_del_vlan_internal(struct efx_nic *efx,
5847                                               struct efx_ef10_filter_vlan *vlan)
5848 {
5849         unsigned int i;
5850
5851         /* See comment in efx_ef10_filter_table_remove() */
5852         if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
5853                 return;
5854
5855         list_del(&vlan->list);
5856
5857         for (i = 0; i < ARRAY_SIZE(vlan->uc); i++)
5858                 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO,
5859                                               vlan->uc[i]);
5860         for (i = 0; i < ARRAY_SIZE(vlan->mc); i++)
5861                 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO,
5862                                               vlan->mc[i]);
5863         for (i = 0; i < EFX_EF10_NUM_DEFAULT_FILTERS; i++)
5864                 if (vlan->default_filters[i] != EFX_EF10_FILTER_ID_INVALID)
5865                         efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO,
5866                                                       vlan->default_filters[i]);
5867
5868         kfree(vlan);
5869 }
5870
5871 static void efx_ef10_filter_del_vlan(struct efx_nic *efx, u16 vid)
5872 {
5873         struct efx_ef10_filter_vlan *vlan;
5874
5875         /* See comment in efx_ef10_filter_table_remove() */
5876         if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
5877                 return;
5878
5879         vlan = efx_ef10_filter_find_vlan(efx, vid);
5880         if (!vlan) {
5881                 netif_err(efx, drv, efx->net_dev,
5882                           "VLAN %u not found in filter state\n", vid);
5883                 return;
5884         }
5885
5886         efx_ef10_filter_del_vlan_internal(efx, vlan);
5887 }
5888
5889 static int efx_ef10_set_mac_address(struct efx_nic *efx)
5890 {
5891         MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_SET_MAC_IN_LEN);
5892         struct efx_ef10_nic_data *nic_data = efx->nic_data;
5893         bool was_enabled = efx->port_enabled;
5894         int rc;
5895
5896         efx_device_detach_sync(efx);
5897         efx_net_stop(efx->net_dev);
5898
5899         mutex_lock(&efx->mac_lock);
5900         down_write(&efx->filter_sem);
5901         efx_ef10_filter_table_remove(efx);
5902
5903         ether_addr_copy(MCDI_PTR(inbuf, VADAPTOR_SET_MAC_IN_MACADDR),
5904                         efx->net_dev->dev_addr);
5905         MCDI_SET_DWORD(inbuf, VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID,
5906                        nic_data->vport_id);
5907         rc = efx_mcdi_rpc_quiet(efx, MC_CMD_VADAPTOR_SET_MAC, inbuf,
5908                                 sizeof(inbuf), NULL, 0, NULL);
5909
5910         efx_ef10_filter_table_probe(efx);
5911         up_write(&efx->filter_sem);
5912         mutex_unlock(&efx->mac_lock);
5913
5914         if (was_enabled)
5915                 efx_net_open(efx->net_dev);
5916         efx_device_attach_if_not_resetting(efx);
5917
5918 #ifdef CONFIG_SFC_SRIOV
5919         if (efx->pci_dev->is_virtfn && efx->pci_dev->physfn) {
5920                 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn;
5921
5922                 if (rc == -EPERM) {
5923                         struct efx_nic *efx_pf;
5924
5925                         /* Switch to PF and change MAC address on vport */
5926                         efx_pf = pci_get_drvdata(pci_dev_pf);
5927
5928                         rc = efx_ef10_sriov_set_vf_mac(efx_pf,
5929                                                        nic_data->vf_index,
5930                                                        efx->net_dev->dev_addr);
5931                 } else if (!rc) {
5932                         struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
5933                         struct efx_ef10_nic_data *nic_data = efx_pf->nic_data;
5934                         unsigned int i;
5935
5936                         /* MAC address successfully changed by VF (with MAC
5937                          * spoofing) so update the parent PF if possible.
5938                          */
5939                         for (i = 0; i < efx_pf->vf_count; ++i) {
5940                                 struct ef10_vf *vf = nic_data->vf + i;
5941
5942                                 if (vf->efx == efx) {
5943                                         ether_addr_copy(vf->mac,
5944                                                         efx->net_dev->dev_addr);
5945                                         return 0;
5946                                 }
5947                         }
5948                 }
5949         } else
5950 #endif
5951         if (rc == -EPERM) {
5952                 netif_err(efx, drv, efx->net_dev,
5953                           "Cannot change MAC address; use sfboot to enable"
5954                           " mac-spoofing on this interface\n");
5955         } else if (rc == -ENOSYS && !efx_ef10_is_vf(efx)) {
5956                 /* If the active MCFW does not support MC_CMD_VADAPTOR_SET_MAC
5957                  * fall-back to the method of changing the MAC address on the
5958                  * vport.  This only applies to PFs because such versions of
5959                  * MCFW do not support VFs.
5960                  */
5961                 rc = efx_ef10_vport_set_mac_address(efx);
5962         } else if (rc) {
5963                 efx_mcdi_display_error(efx, MC_CMD_VADAPTOR_SET_MAC,
5964                                        sizeof(inbuf), NULL, 0, rc);
5965         }
5966
5967         return rc;
5968 }
5969
5970 static int efx_ef10_mac_reconfigure(struct efx_nic *efx)
5971 {
5972         efx_ef10_filter_sync_rx_mode(efx);
5973
5974         return efx_mcdi_set_mac(efx);
5975 }
5976
5977 static int efx_ef10_mac_reconfigure_vf(struct efx_nic *efx)
5978 {
5979         efx_ef10_filter_sync_rx_mode(efx);
5980
5981         return 0;
5982 }
5983
5984 static int efx_ef10_start_bist(struct efx_nic *efx, u32 bist_type)
5985 {
5986         MCDI_DECLARE_BUF(inbuf, MC_CMD_START_BIST_IN_LEN);
5987
5988         MCDI_SET_DWORD(inbuf, START_BIST_IN_TYPE, bist_type);
5989         return efx_mcdi_rpc(efx, MC_CMD_START_BIST, inbuf, sizeof(inbuf),
5990                             NULL, 0, NULL);
5991 }
5992
5993 /* MC BISTs follow a different poll mechanism to phy BISTs.
5994  * The BIST is done in the poll handler on the MC, and the MCDI command
5995  * will block until the BIST is done.
5996  */
5997 static int efx_ef10_poll_bist(struct efx_nic *efx)
5998 {
5999         int rc;
6000         MCDI_DECLARE_BUF(outbuf, MC_CMD_POLL_BIST_OUT_LEN);
6001         size_t outlen;
6002         u32 result;
6003
6004         rc = efx_mcdi_rpc(efx, MC_CMD_POLL_BIST, NULL, 0,
6005                            outbuf, sizeof(outbuf), &outlen);
6006         if (rc != 0)
6007                 return rc;
6008
6009         if (outlen < MC_CMD_POLL_BIST_OUT_LEN)
6010                 return -EIO;
6011
6012         result = MCDI_DWORD(outbuf, POLL_BIST_OUT_RESULT);
6013         switch (result) {
6014         case MC_CMD_POLL_BIST_PASSED:
6015                 netif_dbg(efx, hw, efx->net_dev, "BIST passed.\n");
6016                 return 0;
6017         case MC_CMD_POLL_BIST_TIMEOUT:
6018                 netif_err(efx, hw, efx->net_dev, "BIST timed out\n");
6019                 return -EIO;
6020         case MC_CMD_POLL_BIST_FAILED:
6021                 netif_err(efx, hw, efx->net_dev, "BIST failed.\n");
6022                 return -EIO;
6023         default:
6024                 netif_err(efx, hw, efx->net_dev,
6025                           "BIST returned unknown result %u", result);
6026                 return -EIO;
6027         }
6028 }
6029
6030 static int efx_ef10_run_bist(struct efx_nic *efx, u32 bist_type)
6031 {
6032         int rc;
6033
6034         netif_dbg(efx, drv, efx->net_dev, "starting BIST type %u\n", bist_type);
6035
6036         rc = efx_ef10_start_bist(efx, bist_type);
6037         if (rc != 0)
6038                 return rc;
6039
6040         return efx_ef10_poll_bist(efx);
6041 }
6042
6043 static int
6044 efx_ef10_test_chip(struct efx_nic *efx, struct efx_self_tests *tests)
6045 {
6046         int rc, rc2;
6047
6048         efx_reset_down(efx, RESET_TYPE_WORLD);
6049
6050         rc = efx_mcdi_rpc(efx, MC_CMD_ENABLE_OFFLINE_BIST,
6051                           NULL, 0, NULL, 0, NULL);
6052         if (rc != 0)
6053                 goto out;
6054
6055         tests->memory = efx_ef10_run_bist(efx, MC_CMD_MC_MEM_BIST) ? -1 : 1;
6056         tests->registers = efx_ef10_run_bist(efx, MC_CMD_REG_BIST) ? -1 : 1;
6057
6058         rc = efx_mcdi_reset(efx, RESET_TYPE_WORLD);
6059
6060 out:
6061         if (rc == -EPERM)
6062                 rc = 0;
6063         rc2 = efx_reset_up(efx, RESET_TYPE_WORLD, rc == 0);
6064         return rc ? rc : rc2;
6065 }
6066
6067 #ifdef CONFIG_SFC_MTD
6068
6069 struct efx_ef10_nvram_type_info {
6070         u16 type, type_mask;
6071         u8 port;
6072         const char *name;
6073 };
6074
6075 static const struct efx_ef10_nvram_type_info efx_ef10_nvram_types[] = {
6076         { NVRAM_PARTITION_TYPE_MC_FIRMWARE,        0,    0, "sfc_mcfw" },
6077         { NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 0,    0, "sfc_mcfw_backup" },
6078         { NVRAM_PARTITION_TYPE_EXPANSION_ROM,      0,    0, "sfc_exp_rom" },
6079         { NVRAM_PARTITION_TYPE_STATIC_CONFIG,      0,    0, "sfc_static_cfg" },
6080         { NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG,     0,    0, "sfc_dynamic_cfg" },
6081         { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 0,   0, "sfc_exp_rom_cfg" },
6082         { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1, 0,   1, "sfc_exp_rom_cfg" },
6083         { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2, 0,   2, "sfc_exp_rom_cfg" },
6084         { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3, 0,   3, "sfc_exp_rom_cfg" },
6085         { NVRAM_PARTITION_TYPE_LICENSE,            0,    0, "sfc_license" },
6086         { NVRAM_PARTITION_TYPE_PHY_MIN,            0xff, 0, "sfc_phy_fw" },
6087 };
6088
6089 static int efx_ef10_mtd_probe_partition(struct efx_nic *efx,
6090                                         struct efx_mcdi_mtd_partition *part,
6091                                         unsigned int type)
6092 {
6093         MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_METADATA_IN_LEN);
6094         MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_METADATA_OUT_LENMAX);
6095         const struct efx_ef10_nvram_type_info *info;
6096         size_t size, erase_size, outlen;
6097         bool protected;
6098         int rc;
6099
6100         for (info = efx_ef10_nvram_types; ; info++) {
6101                 if (info ==
6102                     efx_ef10_nvram_types + ARRAY_SIZE(efx_ef10_nvram_types))
6103                         return -ENODEV;
6104                 if ((type & ~info->type_mask) == info->type)
6105                         break;
6106         }
6107         if (info->port != efx_port_num(efx))
6108                 return -ENODEV;
6109
6110         rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected);
6111         if (rc)
6112                 return rc;
6113         if (protected)
6114                 return -ENODEV; /* hide it */
6115
6116         part->nvram_type = type;
6117
6118         MCDI_SET_DWORD(inbuf, NVRAM_METADATA_IN_TYPE, type);
6119         rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_METADATA, inbuf, sizeof(inbuf),
6120                           outbuf, sizeof(outbuf), &outlen);
6121         if (rc)
6122                 return rc;
6123         if (outlen < MC_CMD_NVRAM_METADATA_OUT_LENMIN)
6124                 return -EIO;
6125         if (MCDI_DWORD(outbuf, NVRAM_METADATA_OUT_FLAGS) &
6126             (1 << MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN))
6127                 part->fw_subtype = MCDI_DWORD(outbuf,
6128                                               NVRAM_METADATA_OUT_SUBTYPE);
6129
6130         part->common.dev_type_name = "EF10 NVRAM manager";
6131         part->common.type_name = info->name;
6132
6133         part->common.mtd.type = MTD_NORFLASH;
6134         part->common.mtd.flags = MTD_CAP_NORFLASH;
6135         part->common.mtd.size = size;
6136         part->common.mtd.erasesize = erase_size;
6137
6138         return 0;
6139 }
6140
6141 static int efx_ef10_mtd_probe(struct efx_nic *efx)
6142 {
6143         MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX);
6144         struct efx_mcdi_mtd_partition *parts;
6145         size_t outlen, n_parts_total, i, n_parts;
6146         unsigned int type;
6147         int rc;
6148
6149         ASSERT_RTNL();
6150
6151         BUILD_BUG_ON(MC_CMD_NVRAM_PARTITIONS_IN_LEN != 0);
6152         rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_PARTITIONS, NULL, 0,
6153                           outbuf, sizeof(outbuf), &outlen);
6154         if (rc)
6155                 return rc;
6156         if (outlen < MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN)
6157                 return -EIO;
6158
6159         n_parts_total = MCDI_DWORD(outbuf, NVRAM_PARTITIONS_OUT_NUM_PARTITIONS);
6160         if (n_parts_total >
6161             MCDI_VAR_ARRAY_LEN(outlen, NVRAM_PARTITIONS_OUT_TYPE_ID))
6162                 return -EIO;
6163
6164         parts = kcalloc(n_parts_total, sizeof(*parts), GFP_KERNEL);
6165         if (!parts)
6166                 return -ENOMEM;
6167
6168         n_parts = 0;
6169         for (i = 0; i < n_parts_total; i++) {
6170                 type = MCDI_ARRAY_DWORD(outbuf, NVRAM_PARTITIONS_OUT_TYPE_ID,
6171                                         i);
6172                 rc = efx_ef10_mtd_probe_partition(efx, &parts[n_parts], type);
6173                 if (rc == 0)
6174                         n_parts++;
6175                 else if (rc != -ENODEV)
6176                         goto fail;
6177         }
6178
6179         rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts));
6180 fail:
6181         if (rc)
6182                 kfree(parts);
6183         return rc;
6184 }
6185
6186 #endif /* CONFIG_SFC_MTD */
6187
6188 static void efx_ef10_ptp_write_host_time(struct efx_nic *efx, u32 host_time)
6189 {
6190         _efx_writed(efx, cpu_to_le32(host_time), ER_DZ_MC_DB_LWRD);
6191 }
6192
6193 static void efx_ef10_ptp_write_host_time_vf(struct efx_nic *efx,
6194                                             u32 host_time) {}
6195
6196 static int efx_ef10_rx_enable_timestamping(struct efx_channel *channel,
6197                                            bool temp)
6198 {
6199         MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN);
6200         int rc;
6201
6202         if (channel->sync_events_state == SYNC_EVENTS_REQUESTED ||
6203             channel->sync_events_state == SYNC_EVENTS_VALID ||
6204             (temp && channel->sync_events_state == SYNC_EVENTS_DISABLED))
6205                 return 0;
6206         channel->sync_events_state = SYNC_EVENTS_REQUESTED;
6207
6208         MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE);
6209         MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
6210         MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE,
6211                        channel->channel);
6212
6213         rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
6214                           inbuf, sizeof(inbuf), NULL, 0, NULL);
6215
6216         if (rc != 0)
6217                 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
6218                                                     SYNC_EVENTS_DISABLED;
6219
6220         return rc;
6221 }
6222
6223 static int efx_ef10_rx_disable_timestamping(struct efx_channel *channel,
6224                                             bool temp)
6225 {
6226         MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN);
6227         int rc;
6228
6229         if (channel->sync_events_state == SYNC_EVENTS_DISABLED ||
6230             (temp && channel->sync_events_state == SYNC_EVENTS_QUIESCENT))
6231                 return 0;
6232         if (channel->sync_events_state == SYNC_EVENTS_QUIESCENT) {
6233                 channel->sync_events_state = SYNC_EVENTS_DISABLED;
6234                 return 0;
6235         }
6236         channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
6237                                             SYNC_EVENTS_DISABLED;
6238
6239         MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE);
6240         MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
6241         MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL,
6242                        MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE);
6243         MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE,
6244                        channel->channel);
6245
6246         rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
6247                           inbuf, sizeof(inbuf), NULL, 0, NULL);
6248
6249         return rc;
6250 }
6251
6252 static int efx_ef10_ptp_set_ts_sync_events(struct efx_nic *efx, bool en,
6253                                            bool temp)
6254 {
6255         int (*set)(struct efx_channel *channel, bool temp);
6256         struct efx_channel *channel;
6257
6258         set = en ?
6259               efx_ef10_rx_enable_timestamping :
6260               efx_ef10_rx_disable_timestamping;
6261
6262         efx_for_each_channel(channel, efx) {
6263                 int rc = set(channel, temp);
6264                 if (en && rc != 0) {
6265                         efx_ef10_ptp_set_ts_sync_events(efx, false, temp);
6266                         return rc;
6267                 }
6268         }
6269
6270         return 0;
6271 }
6272
6273 static int efx_ef10_ptp_set_ts_config_vf(struct efx_nic *efx,
6274                                          struct hwtstamp_config *init)
6275 {
6276         return -EOPNOTSUPP;
6277 }
6278
6279 static int efx_ef10_ptp_set_ts_config(struct efx_nic *efx,
6280                                       struct hwtstamp_config *init)
6281 {
6282         int rc;
6283
6284         switch (init->rx_filter) {
6285         case HWTSTAMP_FILTER_NONE:
6286                 efx_ef10_ptp_set_ts_sync_events(efx, false, false);
6287                 /* if TX timestamping is still requested then leave PTP on */
6288                 return efx_ptp_change_mode(efx,
6289                                            init->tx_type != HWTSTAMP_TX_OFF, 0);
6290         case HWTSTAMP_FILTER_ALL:
6291         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
6292         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
6293         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
6294         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
6295         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
6296         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
6297         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
6298         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
6299         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
6300         case HWTSTAMP_FILTER_PTP_V2_EVENT:
6301         case HWTSTAMP_FILTER_PTP_V2_SYNC:
6302         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
6303         case HWTSTAMP_FILTER_NTP_ALL:
6304                 init->rx_filter = HWTSTAMP_FILTER_ALL;
6305                 rc = efx_ptp_change_mode(efx, true, 0);
6306                 if (!rc)
6307                         rc = efx_ef10_ptp_set_ts_sync_events(efx, true, false);
6308                 if (rc)
6309                         efx_ptp_change_mode(efx, false, 0);
6310                 return rc;
6311         default:
6312                 return -ERANGE;
6313         }
6314 }
6315
6316 static int efx_ef10_get_phys_port_id(struct efx_nic *efx,
6317                                      struct netdev_phys_item_id *ppid)
6318 {
6319         struct efx_ef10_nic_data *nic_data = efx->nic_data;
6320
6321         if (!is_valid_ether_addr(nic_data->port_id))
6322                 return -EOPNOTSUPP;
6323
6324         ppid->id_len = ETH_ALEN;
6325         memcpy(ppid->id, nic_data->port_id, ppid->id_len);
6326
6327         return 0;
6328 }
6329
6330 static int efx_ef10_vlan_rx_add_vid(struct efx_nic *efx, __be16 proto, u16 vid)
6331 {
6332         if (proto != htons(ETH_P_8021Q))
6333                 return -EINVAL;
6334
6335         return efx_ef10_add_vlan(efx, vid);
6336 }
6337
6338 static int efx_ef10_vlan_rx_kill_vid(struct efx_nic *efx, __be16 proto, u16 vid)
6339 {
6340         if (proto != htons(ETH_P_8021Q))
6341                 return -EINVAL;
6342
6343         return efx_ef10_del_vlan(efx, vid);
6344 }
6345
6346 /* We rely on the MCDI wiping out our TX rings if it made any changes to the
6347  * ports table, ensuring that any TSO descriptors that were made on a now-
6348  * removed tunnel port will be blown away and won't break things when we try
6349  * to transmit them using the new ports table.
6350  */
6351 static int efx_ef10_set_udp_tnl_ports(struct efx_nic *efx, bool unloading)
6352 {
6353         struct efx_ef10_nic_data *nic_data = efx->nic_data;
6354         MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LENMAX);
6355         MCDI_DECLARE_BUF(outbuf, MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_LEN);
6356         bool will_reset = false;
6357         size_t num_entries = 0;
6358         size_t inlen, outlen;
6359         size_t i;
6360         int rc;
6361         efx_dword_t flags_and_num_entries;
6362
6363         WARN_ON(!mutex_is_locked(&nic_data->udp_tunnels_lock));
6364
6365         nic_data->udp_tunnels_dirty = false;
6366
6367         if (!(nic_data->datapath_caps &
6368             (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN))) {
6369                 efx_device_attach_if_not_resetting(efx);
6370                 return 0;
6371         }
6372
6373         BUILD_BUG_ON(ARRAY_SIZE(nic_data->udp_tunnels) >
6374                      MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MAXNUM);
6375
6376         for (i = 0; i < ARRAY_SIZE(nic_data->udp_tunnels); ++i) {
6377                 if (nic_data->udp_tunnels[i].count &&
6378                     nic_data->udp_tunnels[i].port) {
6379                         efx_dword_t entry;
6380
6381                         EFX_POPULATE_DWORD_2(entry,
6382                                 TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT,
6383                                         ntohs(nic_data->udp_tunnels[i].port),
6384                                 TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL,
6385                                         nic_data->udp_tunnels[i].type);
6386                         *_MCDI_ARRAY_DWORD(inbuf,
6387                                 SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES,
6388                                 num_entries++) = entry;
6389                 }
6390         }
6391
6392         BUILD_BUG_ON((MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_OFST -
6393                       MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS_OFST) * 8 !=
6394                      EFX_WORD_1_LBN);
6395         BUILD_BUG_ON(MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_LEN * 8 !=
6396                      EFX_WORD_1_WIDTH);
6397         EFX_POPULATE_DWORD_2(flags_and_num_entries,
6398                              MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING,
6399                                 !!unloading,
6400                              EFX_WORD_1, num_entries);
6401         *_MCDI_DWORD(inbuf, SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS) =
6402                 flags_and_num_entries;
6403
6404         inlen = MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LEN(num_entries);
6405
6406         rc = efx_mcdi_rpc_quiet(efx, MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS,
6407                                 inbuf, inlen, outbuf, sizeof(outbuf), &outlen);
6408         if (rc == -EIO) {
6409                 /* Most likely the MC rebooted due to another function also
6410                  * setting its tunnel port list. Mark the tunnel port list as
6411                  * dirty, so it will be pushed upon coming up from the reboot.
6412                  */
6413                 nic_data->udp_tunnels_dirty = true;
6414                 return 0;
6415         }
6416
6417         if (rc) {
6418                 /* expected not available on unprivileged functions */
6419                 if (rc != -EPERM)
6420                         netif_warn(efx, drv, efx->net_dev,
6421                                    "Unable to set UDP tunnel ports; rc=%d.\n", rc);
6422         } else if (MCDI_DWORD(outbuf, SET_TUNNEL_ENCAP_UDP_PORTS_OUT_FLAGS) &
6423                    (1 << MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_LBN)) {
6424                 netif_info(efx, drv, efx->net_dev,
6425                            "Rebooting MC due to UDP tunnel port list change\n");
6426                 will_reset = true;
6427                 if (unloading)
6428                         /* Delay for the MC reset to complete. This will make
6429                          * unloading other functions a bit smoother. This is a
6430                          * race, but the other unload will work whichever way
6431                          * it goes, this just avoids an unnecessary error
6432                          * message.
6433                          */
6434                         msleep(100);
6435         }
6436         if (!will_reset && !unloading) {
6437                 /* The caller will have detached, relying on the MC reset to
6438                  * trigger a re-attach.  Since there won't be an MC reset, we
6439                  * have to do the attach ourselves.
6440                  */
6441                 efx_device_attach_if_not_resetting(efx);
6442         }
6443
6444         return rc;
6445 }
6446
6447 static int efx_ef10_udp_tnl_push_ports(struct efx_nic *efx)
6448 {
6449         struct efx_ef10_nic_data *nic_data = efx->nic_data;
6450         int rc = 0;
6451
6452         mutex_lock(&nic_data->udp_tunnels_lock);
6453         if (nic_data->udp_tunnels_dirty) {
6454                 /* Make sure all TX are stopped while we modify the table, else
6455                  * we might race against an efx_features_check().
6456                  */
6457                 efx_device_detach_sync(efx);
6458                 rc = efx_ef10_set_udp_tnl_ports(efx, false);
6459         }
6460         mutex_unlock(&nic_data->udp_tunnels_lock);
6461         return rc;
6462 }
6463
6464 static struct efx_udp_tunnel *__efx_ef10_udp_tnl_lookup_port(struct efx_nic *efx,
6465                                                              __be16 port)
6466 {
6467         struct efx_ef10_nic_data *nic_data = efx->nic_data;
6468         size_t i;
6469
6470         for (i = 0; i < ARRAY_SIZE(nic_data->udp_tunnels); ++i) {
6471                 if (!nic_data->udp_tunnels[i].count)
6472                         continue;
6473                 if (nic_data->udp_tunnels[i].port == port)
6474                         return &nic_data->udp_tunnels[i];
6475         }
6476         return NULL;
6477 }
6478
6479 static int efx_ef10_udp_tnl_add_port(struct efx_nic *efx,
6480                                      struct efx_udp_tunnel tnl)
6481 {
6482         struct efx_ef10_nic_data *nic_data = efx->nic_data;
6483         struct efx_udp_tunnel *match;
6484         char typebuf[8];
6485         size_t i;
6486         int rc;
6487
6488         if (!(nic_data->datapath_caps &
6489               (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN)))
6490                 return 0;
6491
6492         efx_get_udp_tunnel_type_name(tnl.type, typebuf, sizeof(typebuf));
6493         netif_dbg(efx, drv, efx->net_dev, "Adding UDP tunnel (%s) port %d\n",
6494                   typebuf, ntohs(tnl.port));
6495
6496         mutex_lock(&nic_data->udp_tunnels_lock);
6497         /* Make sure all TX are stopped while we add to the table, else we
6498          * might race against an efx_features_check().
6499          */
6500         efx_device_detach_sync(efx);
6501
6502         match = __efx_ef10_udp_tnl_lookup_port(efx, tnl.port);
6503         if (match != NULL) {
6504                 if (match->type == tnl.type) {
6505                         netif_dbg(efx, drv, efx->net_dev,
6506                                   "Referencing existing tunnel entry\n");
6507                         match->count++;
6508                         /* No need to cause an MCDI update */
6509                         rc = 0;
6510                         goto unlock_out;
6511                 }
6512                 efx_get_udp_tunnel_type_name(match->type,
6513                                              typebuf, sizeof(typebuf));
6514                 netif_dbg(efx, drv, efx->net_dev,
6515                           "UDP port %d is already in use by %s\n",
6516                           ntohs(tnl.port), typebuf);
6517                 rc = -EEXIST;
6518                 goto unlock_out;
6519         }
6520
6521         for (i = 0; i < ARRAY_SIZE(nic_data->udp_tunnels); ++i)
6522                 if (!nic_data->udp_tunnels[i].count) {
6523                         nic_data->udp_tunnels[i] = tnl;
6524                         nic_data->udp_tunnels[i].count = 1;
6525                         rc = efx_ef10_set_udp_tnl_ports(efx, false);
6526                         goto unlock_out;
6527                 }
6528
6529         netif_dbg(efx, drv, efx->net_dev,
6530                   "Unable to add UDP tunnel (%s) port %d; insufficient resources.\n",
6531                   typebuf, ntohs(tnl.port));
6532
6533         rc = -ENOMEM;
6534
6535 unlock_out:
6536         mutex_unlock(&nic_data->udp_tunnels_lock);
6537         return rc;
6538 }
6539
6540 /* Called under the TX lock with the TX queue running, hence no-one can be
6541  * in the middle of updating the UDP tunnels table.  However, they could
6542  * have tried and failed the MCDI, in which case they'll have set the dirty
6543  * flag before dropping their locks.
6544  */
6545 static bool efx_ef10_udp_tnl_has_port(struct efx_nic *efx, __be16 port)
6546 {
6547         struct efx_ef10_nic_data *nic_data = efx->nic_data;
6548
6549         if (!(nic_data->datapath_caps &
6550               (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN)))
6551                 return false;
6552
6553         if (nic_data->udp_tunnels_dirty)
6554                 /* SW table may not match HW state, so just assume we can't
6555                  * use any UDP tunnel offloads.
6556                  */
6557                 return false;
6558
6559         return __efx_ef10_udp_tnl_lookup_port(efx, port) != NULL;
6560 }
6561
6562 static int efx_ef10_udp_tnl_del_port(struct efx_nic *efx,
6563                                      struct efx_udp_tunnel tnl)
6564 {
6565         struct efx_ef10_nic_data *nic_data = efx->nic_data;
6566         struct efx_udp_tunnel *match;
6567         char typebuf[8];
6568         int rc;
6569
6570         if (!(nic_data->datapath_caps &
6571               (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN)))
6572                 return 0;
6573
6574         efx_get_udp_tunnel_type_name(tnl.type, typebuf, sizeof(typebuf));
6575         netif_dbg(efx, drv, efx->net_dev, "Removing UDP tunnel (%s) port %d\n",
6576                   typebuf, ntohs(tnl.port));
6577
6578         mutex_lock(&nic_data->udp_tunnels_lock);
6579         /* Make sure all TX are stopped while we remove from the table, else we
6580          * might race against an efx_features_check().
6581          */
6582         efx_device_detach_sync(efx);
6583
6584         match = __efx_ef10_udp_tnl_lookup_port(efx, tnl.port);
6585         if (match != NULL) {
6586                 if (match->type == tnl.type) {
6587                         if (--match->count) {
6588                                 /* Port is still in use, so nothing to do */
6589                                 netif_dbg(efx, drv, efx->net_dev,
6590                                           "UDP tunnel port %d remains active\n",
6591                                           ntohs(tnl.port));
6592                                 rc = 0;
6593                                 goto out_unlock;
6594                         }
6595                         rc = efx_ef10_set_udp_tnl_ports(efx, false);
6596                         goto out_unlock;
6597                 }
6598                 efx_get_udp_tunnel_type_name(match->type,
6599                                              typebuf, sizeof(typebuf));
6600                 netif_warn(efx, drv, efx->net_dev,
6601                            "UDP port %d is actually in use by %s, not removing\n",
6602                            ntohs(tnl.port), typebuf);
6603         }
6604         rc = -ENOENT;
6605
6606 out_unlock:
6607         mutex_unlock(&nic_data->udp_tunnels_lock);
6608         return rc;
6609 }
6610
6611 #define EF10_OFFLOAD_FEATURES           \
6612         (NETIF_F_IP_CSUM |              \
6613          NETIF_F_HW_VLAN_CTAG_FILTER |  \
6614          NETIF_F_IPV6_CSUM |            \
6615          NETIF_F_RXHASH |               \
6616          NETIF_F_NTUPLE)
6617
6618 const struct efx_nic_type efx_hunt_a0_vf_nic_type = {
6619         .is_vf = true,
6620         .mem_bar = efx_ef10_vf_mem_bar,
6621         .mem_map_size = efx_ef10_mem_map_size,
6622         .probe = efx_ef10_probe_vf,
6623         .remove = efx_ef10_remove,
6624         .dimension_resources = efx_ef10_dimension_resources,
6625         .init = efx_ef10_init_nic,
6626         .fini = efx_port_dummy_op_void,
6627         .map_reset_reason = efx_ef10_map_reset_reason,
6628         .map_reset_flags = efx_ef10_map_reset_flags,
6629         .reset = efx_ef10_reset,
6630         .probe_port = efx_mcdi_port_probe,
6631         .remove_port = efx_mcdi_port_remove,
6632         .fini_dmaq = efx_ef10_fini_dmaq,
6633         .prepare_flr = efx_ef10_prepare_flr,
6634         .finish_flr = efx_port_dummy_op_void,
6635         .describe_stats = efx_ef10_describe_stats,
6636         .update_stats = efx_ef10_update_stats_vf,
6637         .start_stats = efx_port_dummy_op_void,
6638         .pull_stats = efx_port_dummy_op_void,
6639         .stop_stats = efx_port_dummy_op_void,
6640         .set_id_led = efx_mcdi_set_id_led,
6641         .push_irq_moderation = efx_ef10_push_irq_moderation,
6642         .reconfigure_mac = efx_ef10_mac_reconfigure_vf,
6643         .check_mac_fault = efx_mcdi_mac_check_fault,
6644         .reconfigure_port = efx_mcdi_port_reconfigure,
6645         .get_wol = efx_ef10_get_wol_vf,
6646         .set_wol = efx_ef10_set_wol_vf,
6647         .resume_wol = efx_port_dummy_op_void,
6648         .mcdi_request = efx_ef10_mcdi_request,
6649         .mcdi_poll_response = efx_ef10_mcdi_poll_response,
6650         .mcdi_read_response = efx_ef10_mcdi_read_response,
6651         .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
6652         .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected,
6653         .irq_enable_master = efx_port_dummy_op_void,
6654         .irq_test_generate = efx_ef10_irq_test_generate,
6655         .irq_disable_non_ev = efx_port_dummy_op_void,
6656         .irq_handle_msi = efx_ef10_msi_interrupt,
6657         .irq_handle_legacy = efx_ef10_legacy_interrupt,
6658         .tx_probe = efx_ef10_tx_probe,
6659         .tx_init = efx_ef10_tx_init,
6660         .tx_remove = efx_ef10_tx_remove,
6661         .tx_write = efx_ef10_tx_write,
6662         .tx_limit_len = efx_ef10_tx_limit_len,
6663         .rx_push_rss_config = efx_ef10_vf_rx_push_rss_config,
6664         .rx_pull_rss_config = efx_ef10_rx_pull_rss_config,
6665         .rx_probe = efx_ef10_rx_probe,
6666         .rx_init = efx_ef10_rx_init,
6667         .rx_remove = efx_ef10_rx_remove,
6668         .rx_write = efx_ef10_rx_write,
6669         .rx_defer_refill = efx_ef10_rx_defer_refill,
6670         .ev_probe = efx_ef10_ev_probe,
6671         .ev_init = efx_ef10_ev_init,
6672         .ev_fini = efx_ef10_ev_fini,
6673         .ev_remove = efx_ef10_ev_remove,
6674         .ev_process = efx_ef10_ev_process,
6675         .ev_read_ack = efx_ef10_ev_read_ack,
6676         .ev_test_generate = efx_ef10_ev_test_generate,
6677         .filter_table_probe = efx_ef10_filter_table_probe,
6678         .filter_table_restore = efx_ef10_filter_table_restore,
6679         .filter_table_remove = efx_ef10_filter_table_remove,
6680         .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
6681         .filter_insert = efx_ef10_filter_insert,
6682         .filter_remove_safe = efx_ef10_filter_remove_safe,
6683         .filter_get_safe = efx_ef10_filter_get_safe,
6684         .filter_clear_rx = efx_ef10_filter_clear_rx,
6685         .filter_count_rx_used = efx_ef10_filter_count_rx_used,
6686         .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
6687         .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
6688 #ifdef CONFIG_RFS_ACCEL
6689         .filter_rfs_insert = efx_ef10_filter_rfs_insert,
6690         .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
6691 #endif
6692 #ifdef CONFIG_SFC_MTD
6693         .mtd_probe = efx_port_dummy_op_int,
6694 #endif
6695         .ptp_write_host_time = efx_ef10_ptp_write_host_time_vf,
6696         .ptp_set_ts_config = efx_ef10_ptp_set_ts_config_vf,
6697         .vlan_rx_add_vid = efx_ef10_vlan_rx_add_vid,
6698         .vlan_rx_kill_vid = efx_ef10_vlan_rx_kill_vid,
6699 #ifdef CONFIG_SFC_SRIOV
6700         .vswitching_probe = efx_ef10_vswitching_probe_vf,
6701         .vswitching_restore = efx_ef10_vswitching_restore_vf,
6702         .vswitching_remove = efx_ef10_vswitching_remove_vf,
6703 #endif
6704         .get_mac_address = efx_ef10_get_mac_address_vf,
6705         .set_mac_address = efx_ef10_set_mac_address,
6706
6707         .get_phys_port_id = efx_ef10_get_phys_port_id,
6708         .revision = EFX_REV_HUNT_A0,
6709         .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
6710         .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
6711         .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
6712         .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
6713         .can_rx_scatter = true,
6714         .always_rx_scatter = true,
6715         .min_interrupt_mode = EFX_INT_MODE_MSIX,
6716         .max_interrupt_mode = EFX_INT_MODE_MSIX,
6717         .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
6718         .offload_features = EF10_OFFLOAD_FEATURES,
6719         .mcdi_max_ver = 2,
6720         .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,
6721         .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
6722                             1 << HWTSTAMP_FILTER_ALL,
6723         .rx_hash_key_size = 40,
6724 };
6725
6726 const struct efx_nic_type efx_hunt_a0_nic_type = {
6727         .is_vf = false,
6728         .mem_bar = efx_ef10_pf_mem_bar,
6729         .mem_map_size = efx_ef10_mem_map_size,
6730         .probe = efx_ef10_probe_pf,
6731         .remove = efx_ef10_remove,
6732         .dimension_resources = efx_ef10_dimension_resources,
6733         .init = efx_ef10_init_nic,
6734         .fini = efx_port_dummy_op_void,
6735         .map_reset_reason = efx_ef10_map_reset_reason,
6736         .map_reset_flags = efx_ef10_map_reset_flags,
6737         .reset = efx_ef10_reset,
6738         .probe_port = efx_mcdi_port_probe,
6739         .remove_port = efx_mcdi_port_remove,
6740         .fini_dmaq = efx_ef10_fini_dmaq,
6741         .prepare_flr = efx_ef10_prepare_flr,
6742         .finish_flr = efx_port_dummy_op_void,
6743         .describe_stats = efx_ef10_describe_stats,
6744         .update_stats = efx_ef10_update_stats_pf,
6745         .start_stats = efx_mcdi_mac_start_stats,
6746         .pull_stats = efx_mcdi_mac_pull_stats,
6747         .stop_stats = efx_mcdi_mac_stop_stats,
6748         .set_id_led = efx_mcdi_set_id_led,
6749         .push_irq_moderation = efx_ef10_push_irq_moderation,
6750         .reconfigure_mac = efx_ef10_mac_reconfigure,
6751         .check_mac_fault = efx_mcdi_mac_check_fault,
6752         .reconfigure_port = efx_mcdi_port_reconfigure,
6753         .get_wol = efx_ef10_get_wol,
6754         .set_wol = efx_ef10_set_wol,
6755         .resume_wol = efx_port_dummy_op_void,
6756         .test_chip = efx_ef10_test_chip,
6757         .test_nvram = efx_mcdi_nvram_test_all,
6758         .mcdi_request = efx_ef10_mcdi_request,
6759         .mcdi_poll_response = efx_ef10_mcdi_poll_response,
6760         .mcdi_read_response = efx_ef10_mcdi_read_response,
6761         .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
6762         .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected,
6763         .irq_enable_master = efx_port_dummy_op_void,
6764         .irq_test_generate = efx_ef10_irq_test_generate,
6765         .irq_disable_non_ev = efx_port_dummy_op_void,
6766         .irq_handle_msi = efx_ef10_msi_interrupt,
6767         .irq_handle_legacy = efx_ef10_legacy_interrupt,
6768         .tx_probe = efx_ef10_tx_probe,
6769         .tx_init = efx_ef10_tx_init,
6770         .tx_remove = efx_ef10_tx_remove,
6771         .tx_write = efx_ef10_tx_write,
6772         .tx_limit_len = efx_ef10_tx_limit_len,
6773         .rx_push_rss_config = efx_ef10_pf_rx_push_rss_config,
6774         .rx_pull_rss_config = efx_ef10_rx_pull_rss_config,
6775         .rx_probe = efx_ef10_rx_probe,
6776         .rx_init = efx_ef10_rx_init,
6777         .rx_remove = efx_ef10_rx_remove,
6778         .rx_write = efx_ef10_rx_write,
6779         .rx_defer_refill = efx_ef10_rx_defer_refill,
6780         .ev_probe = efx_ef10_ev_probe,
6781         .ev_init = efx_ef10_ev_init,
6782         .ev_fini = efx_ef10_ev_fini,
6783         .ev_remove = efx_ef10_ev_remove,
6784         .ev_process = efx_ef10_ev_process,
6785         .ev_read_ack = efx_ef10_ev_read_ack,
6786         .ev_test_generate = efx_ef10_ev_test_generate,
6787         .filter_table_probe = efx_ef10_filter_table_probe,
6788         .filter_table_restore = efx_ef10_filter_table_restore,
6789         .filter_table_remove = efx_ef10_filter_table_remove,
6790         .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
6791         .filter_insert = efx_ef10_filter_insert,
6792         .filter_remove_safe = efx_ef10_filter_remove_safe,
6793         .filter_get_safe = efx_ef10_filter_get_safe,
6794         .filter_clear_rx = efx_ef10_filter_clear_rx,
6795         .filter_count_rx_used = efx_ef10_filter_count_rx_used,
6796         .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
6797         .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
6798 #ifdef CONFIG_RFS_ACCEL
6799         .filter_rfs_insert = efx_ef10_filter_rfs_insert,
6800         .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
6801 #endif
6802 #ifdef CONFIG_SFC_MTD
6803         .mtd_probe = efx_ef10_mtd_probe,
6804         .mtd_rename = efx_mcdi_mtd_rename,
6805         .mtd_read = efx_mcdi_mtd_read,
6806         .mtd_erase = efx_mcdi_mtd_erase,
6807         .mtd_write = efx_mcdi_mtd_write,
6808         .mtd_sync = efx_mcdi_mtd_sync,
6809 #endif
6810         .ptp_write_host_time = efx_ef10_ptp_write_host_time,
6811         .ptp_set_ts_sync_events = efx_ef10_ptp_set_ts_sync_events,
6812         .ptp_set_ts_config = efx_ef10_ptp_set_ts_config,
6813         .vlan_rx_add_vid = efx_ef10_vlan_rx_add_vid,
6814         .vlan_rx_kill_vid = efx_ef10_vlan_rx_kill_vid,
6815         .udp_tnl_push_ports = efx_ef10_udp_tnl_push_ports,
6816         .udp_tnl_add_port = efx_ef10_udp_tnl_add_port,
6817         .udp_tnl_has_port = efx_ef10_udp_tnl_has_port,
6818         .udp_tnl_del_port = efx_ef10_udp_tnl_del_port,
6819 #ifdef CONFIG_SFC_SRIOV
6820         .sriov_configure = efx_ef10_sriov_configure,
6821         .sriov_init = efx_ef10_sriov_init,
6822         .sriov_fini = efx_ef10_sriov_fini,
6823         .sriov_wanted = efx_ef10_sriov_wanted,
6824         .sriov_reset = efx_ef10_sriov_reset,
6825         .sriov_flr = efx_ef10_sriov_flr,
6826         .sriov_set_vf_mac = efx_ef10_sriov_set_vf_mac,
6827         .sriov_set_vf_vlan = efx_ef10_sriov_set_vf_vlan,
6828         .sriov_set_vf_spoofchk = efx_ef10_sriov_set_vf_spoofchk,
6829         .sriov_get_vf_config = efx_ef10_sriov_get_vf_config,
6830         .sriov_set_vf_link_state = efx_ef10_sriov_set_vf_link_state,
6831         .vswitching_probe = efx_ef10_vswitching_probe_pf,
6832         .vswitching_restore = efx_ef10_vswitching_restore_pf,
6833         .vswitching_remove = efx_ef10_vswitching_remove_pf,
6834 #endif
6835         .get_mac_address = efx_ef10_get_mac_address_pf,
6836         .set_mac_address = efx_ef10_set_mac_address,
6837         .tso_versions = efx_ef10_tso_versions,
6838
6839         .get_phys_port_id = efx_ef10_get_phys_port_id,
6840         .revision = EFX_REV_HUNT_A0,
6841         .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
6842         .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
6843         .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
6844         .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
6845         .can_rx_scatter = true,
6846         .always_rx_scatter = true,
6847         .option_descriptors = true,
6848         .min_interrupt_mode = EFX_INT_MODE_LEGACY,
6849         .max_interrupt_mode = EFX_INT_MODE_MSIX,
6850         .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
6851         .offload_features = EF10_OFFLOAD_FEATURES,
6852         .mcdi_max_ver = 2,
6853         .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,
6854         .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
6855                             1 << HWTSTAMP_FILTER_ALL,
6856         .rx_hash_key_size = 40,
6857 };