drivers/net/ethernet/sfc/ef10.c

   1 /****************************************************************************
   2  * Driver for Solarflare network controllers and boards
   3  * Copyright 2012-2013 Solarflare Communications Inc.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published
   7  * by the Free Software Foundation, incorporated herein by reference.
   8  */
   9
  10 #include "net_driver.h"
  11 #include "ef10_regs.h"
  12 #include "io.h"
  13 #include "mcdi.h"
  14 #include "mcdi_pcol.h"
  15 #include "nic.h"
  16 #include "workarounds.h"
  17 #include "selftest.h"
  18 #include "ef10_sriov.h"
  19 #include <linux/in.h>
  20 #include <linux/jhash.h>
  21 #include <linux/wait.h>
  22 #include <linux/workqueue.h>
  23
  24 /* Hardware control for EF10 architecture including 'Huntington'. */
  25
  26 #define EFX_EF10_DRVGEN_EV              7
  27 enum {
  28         EFX_EF10_TEST = 1,
  29         EFX_EF10_REFILL,
  30 };
  31
  32 /* The reserved RSS context value */
  33 #define EFX_EF10_RSS_CONTEXT_INVALID    0xffffffff
  34 /* The maximum size of a shared RSS context */
  35 /* TODO: this should really be from the mcdi protocol export */
  36 #define EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE 64UL
  37
  38 /* The filter table(s) are managed by firmware and we have write-only
  39  * access.  When removing filters we must identify them to the
  40  * firmware by a 64-bit handle, but this is too wide for Linux kernel
  41  * interfaces (32-bit for RX NFC, 16-bit for RFS).  Also, we need to
  42  * be able to tell in advance whether a requested insertion will
  43  * replace an existing filter.  Therefore we maintain a software hash
  44  * table, which should be at least as large as the hardware hash
  45  * table.
  46  *
  47  * Huntington has a single 8K filter table shared between all filter
  48  * types and both ports.
  49  */
  50 #define HUNT_FILTER_TBL_ROWS 8192
  51
  52 #define EFX_EF10_FILTER_ID_INVALID 0xffff
  53
  54 #define EFX_EF10_FILTER_DEV_UC_MAX      32
  55 #define EFX_EF10_FILTER_DEV_MC_MAX      256
  56
  57 /* VLAN list entry */
  58 struct efx_ef10_vlan {
  59         struct list_head list;
  60         u16 vid;
  61 };
  62
  63 enum efx_ef10_default_filters {
  64         EFX_EF10_BCAST,
  65         EFX_EF10_UCDEF,
  66         EFX_EF10_MCDEF,
  67         EFX_EF10_VXLAN4_UCDEF,
  68         EFX_EF10_VXLAN4_MCDEF,
  69         EFX_EF10_VXLAN6_UCDEF,
  70         EFX_EF10_VXLAN6_MCDEF,
  71         EFX_EF10_NVGRE4_UCDEF,
  72         EFX_EF10_NVGRE4_MCDEF,
  73         EFX_EF10_NVGRE6_UCDEF,
  74         EFX_EF10_NVGRE6_MCDEF,
  75         EFX_EF10_GENEVE4_UCDEF,
  76         EFX_EF10_GENEVE4_MCDEF,
  77         EFX_EF10_GENEVE6_UCDEF,
  78         EFX_EF10_GENEVE6_MCDEF,
  79
  80         EFX_EF10_NUM_DEFAULT_FILTERS
  81 };
  82
  83 /* Per-VLAN filters information */
  84 struct efx_ef10_filter_vlan {
  85         struct list_head list;
  86         u16 vid;
  87         u16 uc[EFX_EF10_FILTER_DEV_UC_MAX];
  88         u16 mc[EFX_EF10_FILTER_DEV_MC_MAX];
  89         u16 default_filters[EFX_EF10_NUM_DEFAULT_FILTERS];
  90 };
  91
  92 struct efx_ef10_dev_addr {
  93         u8 addr[ETH_ALEN];
  94 };
  95
  96 struct efx_ef10_filter_table {
  97 /* The MCDI match masks supported by this fw & hw, in order of priority */
  98         u32 rx_match_mcdi_flags[
  99                 MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM * 2];
 100         unsigned int rx_match_count;
 101
 102         struct {
 103                 unsigned long spec;     /* pointer to spec plus flag bits */
 104 /* BUSY flag indicates that an update is in progress.  AUTO_OLD is
 105  * used to mark and sweep MAC filters for the device address lists.
 106  */
 107 #define EFX_EF10_FILTER_FLAG_BUSY       1UL
 108 #define EFX_EF10_FILTER_FLAG_AUTO_OLD   2UL
 109 #define EFX_EF10_FILTER_FLAGS           3UL
 110                 u64 handle;             /* firmware handle */
 111         } *entry;
 112         wait_queue_head_t waitq;
 113 /* Shadow of net_device address lists, guarded by mac_lock */
 114         struct efx_ef10_dev_addr dev_uc_list[EFX_EF10_FILTER_DEV_UC_MAX];
 115         struct efx_ef10_dev_addr dev_mc_list[EFX_EF10_FILTER_DEV_MC_MAX];
 116         int dev_uc_count;
 117         int dev_mc_count;
 118         bool uc_promisc;
 119         bool mc_promisc;
 120 /* Whether in multicast promiscuous mode when last changed */
 121         bool mc_promisc_last;
 122         bool mc_overflow; /* Too many MC addrs; should always imply mc_promisc */
 123         bool vlan_filter;
 124         struct list_head vlan_list;
 125 };
 126
 127 /* An arbitrary search limit for the software hash table */
 128 #define EFX_EF10_FILTER_SEARCH_LIMIT 200
 129
 130 static void efx_ef10_rx_free_indir_table(struct efx_nic *efx);
 131 static void efx_ef10_filter_table_remove(struct efx_nic *efx);
 132 static int efx_ef10_filter_add_vlan(struct efx_nic *efx, u16 vid);
 133 static void efx_ef10_filter_del_vlan_internal(struct efx_nic *efx,
 134                                               struct efx_ef10_filter_vlan *vlan);
 135 static void efx_ef10_filter_del_vlan(struct efx_nic *efx, u16 vid);
 136 static int efx_ef10_set_udp_tnl_ports(struct efx_nic *efx, bool unloading);
 137
 138 static u32 efx_ef10_filter_get_unsafe_id(u32 filter_id)
 139 {
 140         WARN_ON_ONCE(filter_id == EFX_EF10_FILTER_ID_INVALID);
 141         return filter_id & (HUNT_FILTER_TBL_ROWS - 1);
 142 }
 143
 144 static unsigned int efx_ef10_filter_get_unsafe_pri(u32 filter_id)
 145 {
 146         return filter_id / (HUNT_FILTER_TBL_ROWS * 2);
 147 }
 148
 149 static u32 efx_ef10_make_filter_id(unsigned int pri, u16 idx)
 150 {
 151         return pri * HUNT_FILTER_TBL_ROWS * 2 + idx;
 152 }
 153
 154 static int efx_ef10_get_warm_boot_count(struct efx_nic *efx)
 155 {
 156         efx_dword_t reg;
 157
 158         efx_readd(efx, &reg, ER_DZ_BIU_MC_SFT_STATUS);
 159         return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ?
 160                 EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO;
 161 }
 162
 163 /* On all EF10s up to and including SFC9220 (Medford1), all PFs use BAR 0 for
 164  * I/O space and BAR 2(&3) for memory.  On SFC9250 (Medford2), there is no I/O
 165  * bar; PFs use BAR 0/1 for memory.
 166  */
 167 static unsigned int efx_ef10_pf_mem_bar(struct efx_nic *efx)
 168 {
 169         switch (efx->pci_dev->device) {
 170         case 0x0b03: /* SFC9250 PF */
 171                 return 0;
 172         default:
 173                 return 2;
 174         }
 175 }
 176
 177 /* All VFs use BAR 0/1 for memory */
 178 static unsigned int efx_ef10_vf_mem_bar(struct efx_nic *efx)
 179 {
 180         return 0;
 181 }
 182
 183 static unsigned int efx_ef10_mem_map_size(struct efx_nic *efx)
 184 {
 185         int bar;
 186
 187         bar = efx->type->mem_bar(efx);
 188         return resource_size(&efx->pci_dev->resource[bar]);
 189 }
 190
 191 static bool efx_ef10_is_vf(struct efx_nic *efx)
 192 {
 193         return efx->type->is_vf;
 194 }
 195
 196 static int efx_ef10_get_pf_index(struct efx_nic *efx)
 197 {
 198         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN);
 199         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 200         size_t outlen;
 201         int rc;
 202
 203         rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf,
 204                           sizeof(outbuf), &outlen);
 205         if (rc)
 206                 return rc;
 207         if (outlen < sizeof(outbuf))
 208                 return -EIO;
 209
 210         nic_data->pf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_PF);
 211         return 0;
 212 }
 213
 214 #ifdef CONFIG_SFC_SRIOV
 215 static int efx_ef10_get_vf_index(struct efx_nic *efx)
 216 {
 217         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN);
 218         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 219         size_t outlen;
 220         int rc;
 221
 222         rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf,
 223                           sizeof(outbuf), &outlen);
 224         if (rc)
 225                 return rc;
 226         if (outlen < sizeof(outbuf))
 227                 return -EIO;
 228
 229         nic_data->vf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_VF);
 230         return 0;
 231 }
 232 #endif
 233
 234 static int efx_ef10_init_datapath_caps(struct efx_nic *efx)
 235 {
 236         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_V3_OUT_LEN);
 237         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 238         size_t outlen;
 239         int rc;
 240
 241         BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0);
 242
 243         rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0,
 244                           outbuf, sizeof(outbuf), &outlen);
 245         if (rc)
 246                 return rc;
 247         if (outlen < MC_CMD_GET_CAPABILITIES_OUT_LEN) {
 248                 netif_err(efx, drv, efx->net_dev,
 249                           "unable to read datapath firmware capabilities\n");
 250                 return -EIO;
 251         }
 252
 253         nic_data->datapath_caps =
 254                 MCDI_DWORD(outbuf, GET_CAPABILITIES_OUT_FLAGS1);
 255
 256         if (outlen >= MC_CMD_GET_CAPABILITIES_V2_OUT_LEN) {
 257                 nic_data->datapath_caps2 = MCDI_DWORD(outbuf,
 258                                 GET_CAPABILITIES_V2_OUT_FLAGS2);
 259                 nic_data->piobuf_size = MCDI_WORD(outbuf,
 260                                 GET_CAPABILITIES_V2_OUT_SIZE_PIO_BUFF);
 261         } else {
 262                 nic_data->datapath_caps2 = 0;
 263                 nic_data->piobuf_size = ER_DZ_TX_PIOBUF_SIZE;
 264         }
 265
 266         /* record the DPCPU firmware IDs to determine VEB vswitching support.
 267          */
 268         nic_data->rx_dpcpu_fw_id =
 269                 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID);
 270         nic_data->tx_dpcpu_fw_id =
 271                 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID);
 272
 273         if (!(nic_data->datapath_caps &
 274               (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN))) {
 275                 netif_err(efx, probe, efx->net_dev,
 276                           "current firmware does not support an RX prefix\n");
 277                 return -ENODEV;
 278         }
 279
 280         if (outlen >= MC_CMD_GET_CAPABILITIES_V3_OUT_LEN) {
 281                 u8 vi_window_mode = MCDI_BYTE(outbuf,
 282                                 GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE);
 283
 284                 switch (vi_window_mode) {
 285                 case MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_8K:
 286                         efx->vi_stride = 8192;
 287                         break;
 288                 case MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_16K:
 289                         efx->vi_stride = 16384;
 290                         break;
 291                 case MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_64K:
 292                         efx->vi_stride = 65536;
 293                         break;
 294                 default:
 295                         netif_err(efx, probe, efx->net_dev,
 296                                   "Unrecognised VI window mode %d\n",
 297                                   vi_window_mode);
 298                         return -EIO;
 299                 }
 300                 netif_dbg(efx, probe, efx->net_dev, "vi_stride = %u\n",
 301                           efx->vi_stride);
 302         } else {
 303                 /* keep default VI stride */
 304                 netif_dbg(efx, probe, efx->net_dev,
 305                           "firmware did not report VI window mode, assuming vi_stride = %u\n",
 306                           efx->vi_stride);
 307         }
 308
 309         return 0;
 310 }
 311
 312 static int efx_ef10_get_sysclk_freq(struct efx_nic *efx)
 313 {
 314         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CLOCK_OUT_LEN);
 315         int rc;
 316
 317         rc = efx_mcdi_rpc(efx, MC_CMD_GET_CLOCK, NULL, 0,
 318                           outbuf, sizeof(outbuf), NULL);
 319         if (rc)
 320                 return rc;
 321         rc = MCDI_DWORD(outbuf, GET_CLOCK_OUT_SYS_FREQ);
 322         return rc > 0 ? rc : -ERANGE;
 323 }
 324
 325 static int efx_ef10_get_timer_workarounds(struct efx_nic *efx)
 326 {
 327         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 328         unsigned int implemented;
 329         unsigned int enabled;
 330         int rc;
 331
 332         nic_data->workaround_35388 = false;
 333         nic_data->workaround_61265 = false;
 334
 335         rc = efx_mcdi_get_workarounds(efx, &implemented, &enabled);
 336
 337         if (rc == -ENOSYS) {
 338                 /* Firmware without GET_WORKAROUNDS - not a problem. */
 339                 rc = 0;
 340         } else if (rc == 0) {
 341                 /* Bug61265 workaround is always enabled if implemented. */
 342                 if (enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG61265)
 343                         nic_data->workaround_61265 = true;
 344
 345                 if (enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG35388) {
 346                         nic_data->workaround_35388 = true;
 347                 } else if (implemented & MC_CMD_GET_WORKAROUNDS_OUT_BUG35388) {
 348                         /* Workaround is implemented but not enabled.
 349                          * Try to enable it.
 350                          */
 351                         rc = efx_mcdi_set_workaround(efx,
 352                                                      MC_CMD_WORKAROUND_BUG35388,
 353                                                      true, NULL);
 354                         if (rc == 0)
 355                                 nic_data->workaround_35388 = true;
 356                         /* If we failed to set the workaround just carry on. */
 357                         rc = 0;
 358                 }
 359         }
 360
 361         netif_dbg(efx, probe, efx->net_dev,
 362                   "workaround for bug 35388 is %sabled\n",
 363                   nic_data->workaround_35388 ? "en" : "dis");
 364         netif_dbg(efx, probe, efx->net_dev,
 365                   "workaround for bug 61265 is %sabled\n",
 366                   nic_data->workaround_61265 ? "en" : "dis");
 367
 368         return rc;
 369 }
 370
 371 static void efx_ef10_process_timer_config(struct efx_nic *efx,
 372                                           const efx_dword_t *data)
 373 {
 374         unsigned int max_count;
 375
 376         if (EFX_EF10_WORKAROUND_61265(efx)) {
 377                 efx->timer_quantum_ns = MCDI_DWORD(data,
 378                         GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_STEP_NS);
 379                 efx->timer_max_ns = MCDI_DWORD(data,
 380                         GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_MAX_NS);
 381         } else if (EFX_EF10_WORKAROUND_35388(efx)) {
 382                 efx->timer_quantum_ns = MCDI_DWORD(data,
 383                         GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_NS_PER_COUNT);
 384                 max_count = MCDI_DWORD(data,
 385                         GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_MAX_COUNT);
 386                 efx->timer_max_ns = max_count * efx->timer_quantum_ns;
 387         } else {
 388                 efx->timer_quantum_ns = MCDI_DWORD(data,
 389                         GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_NS_PER_COUNT);
 390                 max_count = MCDI_DWORD(data,
 391                         GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_MAX_COUNT);
 392                 efx->timer_max_ns = max_count * efx->timer_quantum_ns;
 393         }
 394
 395         netif_dbg(efx, probe, efx->net_dev,
 396                   "got timer properties from MC: quantum %u ns; max %u ns\n",
 397                   efx->timer_quantum_ns, efx->timer_max_ns);
 398 }
 399
 400 static int efx_ef10_get_timer_config(struct efx_nic *efx)
 401 {
 402         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN);
 403         int rc;
 404
 405         rc = efx_ef10_get_timer_workarounds(efx);
 406         if (rc)
 407                 return rc;
 408
 409         rc = efx_mcdi_rpc_quiet(efx, MC_CMD_GET_EVQ_TMR_PROPERTIES, NULL, 0,
 410                                 outbuf, sizeof(outbuf), NULL);
 411
 412         if (rc == 0) {
 413                 efx_ef10_process_timer_config(efx, outbuf);
 414         } else if (rc == -ENOSYS || rc == -EPERM) {
 415                 /* Not available - fall back to Huntington defaults. */
 416                 unsigned int quantum;
 417
 418                 rc = efx_ef10_get_sysclk_freq(efx);
 419                 if (rc < 0)
 420                         return rc;
 421
 422                 quantum = 1536000 / rc; /* 1536 cycles */
 423                 efx->timer_quantum_ns = quantum;
 424                 efx->timer_max_ns = efx->type->timer_period_max * quantum;
 425                 rc = 0;
 426         } else {
 427                 efx_mcdi_display_error(efx, MC_CMD_GET_EVQ_TMR_PROPERTIES,
 428                                        MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN,
 429                                        NULL, 0, rc);
 430         }
 431
 432         return rc;
 433 }
 434
 435 static int efx_ef10_get_mac_address_pf(struct efx_nic *efx, u8 *mac_address)
 436 {
 437         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN);
 438         size_t outlen;
 439         int rc;
 440
 441         BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0);
 442
 443         rc = efx_mcdi_rpc(efx, MC_CMD_GET_MAC_ADDRESSES, NULL, 0,
 444                           outbuf, sizeof(outbuf), &outlen);
 445         if (rc)
 446                 return rc;
 447         if (outlen < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN)
 448                 return -EIO;
 449
 450         ether_addr_copy(mac_address,
 451                         MCDI_PTR(outbuf, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE));
 452         return 0;
 453 }
 454
 455 static int efx_ef10_get_mac_address_vf(struct efx_nic *efx, u8 *mac_address)
 456 {
 457         MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN);
 458         MCDI_DECLARE_BUF(outbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX);
 459         size_t outlen;
 460         int num_addrs, rc;
 461
 462         MCDI_SET_DWORD(inbuf, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID,
 463                        EVB_PORT_ID_ASSIGNED);
 464         rc = efx_mcdi_rpc(efx, MC_CMD_VPORT_GET_MAC_ADDRESSES, inbuf,
 465                           sizeof(inbuf), outbuf, sizeof(outbuf), &outlen);
 466
 467         if (rc)
 468                 return rc;
 469         if (outlen < MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN)
 470                 return -EIO;
 471
 472         num_addrs = MCDI_DWORD(outbuf,
 473                                VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT);
 474
 475         WARN_ON(num_addrs != 1);
 476
 477         ether_addr_copy(mac_address,
 478                         MCDI_PTR(outbuf, VPORT_GET_MAC_ADDRESSES_OUT_MACADDR));
 479
 480         return 0;
 481 }
 482
 483 static ssize_t efx_ef10_show_link_control_flag(struct device *dev,
 484                                                struct device_attribute *attr,
 485                                                char *buf)
 486 {
 487         struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
 488
 489         return sprintf(buf, "%d\n",
 490                        ((efx->mcdi->fn_flags) &
 491                         (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL))
 492                        ? 1 : 0);
 493 }
 494
 495 static ssize_t efx_ef10_show_primary_flag(struct device *dev,
 496                                           struct device_attribute *attr,
 497                                           char *buf)
 498 {
 499         struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
 500
 501         return sprintf(buf, "%d\n",
 502                        ((efx->mcdi->fn_flags) &
 503                         (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY))
 504                        ? 1 : 0);
 505 }
 506
 507 static struct efx_ef10_vlan *efx_ef10_find_vlan(struct efx_nic *efx, u16 vid)
 508 {
 509         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 510         struct efx_ef10_vlan *vlan;
 511
 512         WARN_ON(!mutex_is_locked(&nic_data->vlan_lock));
 513
 514         list_for_each_entry(vlan, &nic_data->vlan_list, list) {
 515                 if (vlan->vid == vid)
 516                         return vlan;
 517         }
 518
 519         return NULL;
 520 }
 521
 522 static int efx_ef10_add_vlan(struct efx_nic *efx, u16 vid)
 523 {
 524         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 525         struct efx_ef10_vlan *vlan;
 526         int rc;
 527
 528         mutex_lock(&nic_data->vlan_lock);
 529
 530         vlan = efx_ef10_find_vlan(efx, vid);
 531         if (vlan) {
 532                 /* We add VID 0 on init. 8021q adds it on module init
 533                  * for all interfaces with VLAN filtring feature.
 534                  */
 535                 if (vid == 0)
 536                         goto done_unlock;
 537                 netif_warn(efx, drv, efx->net_dev,
 538                            "VLAN %u already added\n", vid);
 539                 rc = -EALREADY;
 540                 goto fail_exist;
 541         }
 542
 543         rc = -ENOMEM;
 544         vlan = kzalloc(sizeof(*vlan), GFP_KERNEL);
 545         if (!vlan)
 546                 goto fail_alloc;
 547
 548         vlan->vid = vid;
 549
 550         list_add_tail(&vlan->list, &nic_data->vlan_list);
 551
 552         if (efx->filter_state) {
 553                 mutex_lock(&efx->mac_lock);
 554                 down_write(&efx->filter_sem);
 555                 rc = efx_ef10_filter_add_vlan(efx, vlan->vid);
 556                 up_write(&efx->filter_sem);
 557                 mutex_unlock(&efx->mac_lock);
 558                 if (rc)
 559                         goto fail_filter_add_vlan;
 560         }
 561
 562 done_unlock:
 563         mutex_unlock(&nic_data->vlan_lock);
 564         return 0;
 565
 566 fail_filter_add_vlan:
 567         list_del(&vlan->list);
 568         kfree(vlan);
 569 fail_alloc:
 570 fail_exist:
 571         mutex_unlock(&nic_data->vlan_lock);
 572         return rc;
 573 }
 574
 575 static void efx_ef10_del_vlan_internal(struct efx_nic *efx,
 576                                        struct efx_ef10_vlan *vlan)
 577 {
 578         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 579
 580         WARN_ON(!mutex_is_locked(&nic_data->vlan_lock));
 581
 582         if (efx->filter_state) {
 583                 down_write(&efx->filter_sem);
 584                 efx_ef10_filter_del_vlan(efx, vlan->vid);
 585                 up_write(&efx->filter_sem);
 586         }
 587
 588         list_del(&vlan->list);
 589         kfree(vlan);
 590 }
 591
 592 static int efx_ef10_del_vlan(struct efx_nic *efx, u16 vid)
 593 {
 594         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 595         struct efx_ef10_vlan *vlan;
 596         int rc = 0;
 597
 598         /* 8021q removes VID 0 on module unload for all interfaces
 599          * with VLAN filtering feature. We need to keep it to receive
 600          * untagged traffic.
 601          */
 602         if (vid == 0)
 603                 return 0;
 604
 605         mutex_lock(&nic_data->vlan_lock);
 606
 607         vlan = efx_ef10_find_vlan(efx, vid);
 608         if (!vlan) {
 609                 netif_err(efx, drv, efx->net_dev,
 610                           "VLAN %u to be deleted not found\n", vid);
 611                 rc = -ENOENT;
 612         } else {
 613                 efx_ef10_del_vlan_internal(efx, vlan);
 614         }
 615
 616         mutex_unlock(&nic_data->vlan_lock);
 617
 618         return rc;
 619 }
 620
 621 static void efx_ef10_cleanup_vlans(struct efx_nic *efx)
 622 {
 623         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 624         struct efx_ef10_vlan *vlan, *next_vlan;
 625
 626         mutex_lock(&nic_data->vlan_lock);
 627         list_for_each_entry_safe(vlan, next_vlan, &nic_data->vlan_list, list)
 628                 efx_ef10_del_vlan_internal(efx, vlan);
 629         mutex_unlock(&nic_data->vlan_lock);
 630 }
 631
 632 static DEVICE_ATTR(link_control_flag, 0444, efx_ef10_show_link_control_flag,
 633                    NULL);
 634 static DEVICE_ATTR(primary_flag, 0444, efx_ef10_show_primary_flag, NULL);
 635
 636 static int efx_ef10_probe(struct efx_nic *efx)
 637 {
 638         struct efx_ef10_nic_data *nic_data;
 639         int i, rc;
 640
 641         nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
 642         if (!nic_data)
 643                 return -ENOMEM;
 644         efx->nic_data = nic_data;
 645
 646         /* we assume later that we can copy from this buffer in dwords */
 647         BUILD_BUG_ON(MCDI_CTL_SDU_LEN_MAX_V2 % 4);
 648
 649         rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf,
 650                                   8 + MCDI_CTL_SDU_LEN_MAX_V2, GFP_KERNEL);
 651         if (rc)
 652                 goto fail1;
 653
 654         /* Get the MC's warm boot count.  In case it's rebooting right
 655          * now, be prepared to retry.
 656          */
 657         i = 0;
 658         for (;;) {
 659                 rc = efx_ef10_get_warm_boot_count(efx);
 660                 if (rc >= 0)
 661                         break;
 662                 if (++i == 5)
 663                         goto fail2;
 664                 ssleep(1);
 665         }
 666         nic_data->warm_boot_count = rc;
 667
 668         nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
 669
 670         nic_data->vport_id = EVB_PORT_ID_ASSIGNED;
 671
 672         /* In case we're recovering from a crash (kexec), we want to
 673          * cancel any outstanding request by the previous user of this
 674          * function.  We send a special message using the least
 675          * significant bits of the 'high' (doorbell) register.
 676          */
 677         _efx_writed(efx, cpu_to_le32(1), ER_DZ_MC_DB_HWRD);
 678
 679         rc = efx_mcdi_init(efx);
 680         if (rc)
 681                 goto fail2;
 682
 683         mutex_init(&nic_data->udp_tunnels_lock);
 684
 685         /* Reset (most) configuration for this function */
 686         rc = efx_mcdi_reset(efx, RESET_TYPE_ALL);
 687         if (rc)
 688                 goto fail3;
 689
 690         /* Enable event logging */
 691         rc = efx_mcdi_log_ctrl(efx, true, false, 0);
 692         if (rc)
 693                 goto fail3;
 694
 695         rc = device_create_file(&efx->pci_dev->dev,
 696                                 &dev_attr_link_control_flag);
 697         if (rc)
 698                 goto fail3;
 699
 700         rc = device_create_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
 701         if (rc)
 702                 goto fail4;
 703
 704         rc = efx_ef10_get_pf_index(efx);
 705         if (rc)
 706                 goto fail5;
 707
 708         rc = efx_ef10_init_datapath_caps(efx);
 709         if (rc < 0)
 710                 goto fail5;
 711
 712         /* We can have one VI for each vi_stride-byte region.
 713          * However, until we use TX option descriptors we need two TX queues
 714          * per channel.
 715          */
 716         efx->max_channels = min_t(unsigned int,
 717                                   EFX_MAX_CHANNELS,
 718                                   efx_ef10_mem_map_size(efx) /
 719                                   (efx->vi_stride * EFX_TXQ_TYPES));
 720         efx->max_tx_channels = efx->max_channels;
 721         if (WARN_ON(efx->max_channels == 0)) {
 722                 rc = -EIO;
 723                 goto fail5;
 724         }
 725
 726         efx->rx_packet_len_offset =
 727                 ES_DZ_RX_PREFIX_PKTLEN_OFST - ES_DZ_RX_PREFIX_SIZE;
 728
 729         if (nic_data->datapath_caps &
 730             (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_LBN))
 731                 efx->net_dev->hw_features |= NETIF_F_RXFCS;
 732
 733         rc = efx_mcdi_port_get_number(efx);
 734         if (rc < 0)
 735                 goto fail5;
 736         efx->port_num = rc;
 737
 738         rc = efx->type->get_mac_address(efx, efx->net_dev->perm_addr);
 739         if (rc)
 740                 goto fail5;
 741
 742         rc = efx_ef10_get_timer_config(efx);
 743         if (rc < 0)
 744                 goto fail5;
 745
 746         rc = efx_mcdi_mon_probe(efx);
 747         if (rc && rc != -EPERM)
 748                 goto fail5;
 749
 750         efx_ptp_probe(efx, NULL);
 751
 752 #ifdef CONFIG_SFC_SRIOV
 753         if ((efx->pci_dev->physfn) && (!efx->pci_dev->is_physfn)) {
 754                 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn;
 755                 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
 756
 757                 efx_pf->type->get_mac_address(efx_pf, nic_data->port_id);
 758         } else
 759 #endif
 760                 ether_addr_copy(nic_data->port_id, efx->net_dev->perm_addr);
 761
 762         INIT_LIST_HEAD(&nic_data->vlan_list);
 763         mutex_init(&nic_data->vlan_lock);
 764
 765         /* Add unspecified VID to support VLAN filtering being disabled */
 766         rc = efx_ef10_add_vlan(efx, EFX_FILTER_VID_UNSPEC);
 767         if (rc)
 768                 goto fail_add_vid_unspec;
 769
 770         /* If VLAN filtering is enabled, we need VID 0 to get untagged
 771          * traffic.  It is added automatically if 8021q module is loaded,
 772          * but we can't rely on it since module may be not loaded.
 773          */
 774         rc = efx_ef10_add_vlan(efx, 0);
 775         if (rc)
 776                 goto fail_add_vid_0;
 777
 778         return 0;
 779
 780 fail_add_vid_0:
 781         efx_ef10_cleanup_vlans(efx);
 782 fail_add_vid_unspec:
 783         mutex_destroy(&nic_data->vlan_lock);
 784         efx_ptp_remove(efx);
 785         efx_mcdi_mon_remove(efx);
 786 fail5:
 787         device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
 788 fail4:
 789         device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag);
 790 fail3:
 791         efx_mcdi_detach(efx);
 792
 793         mutex_lock(&nic_data->udp_tunnels_lock);
 794         memset(nic_data->udp_tunnels, 0, sizeof(nic_data->udp_tunnels));
 795         (void)efx_ef10_set_udp_tnl_ports(efx, true);
 796         mutex_unlock(&nic_data->udp_tunnels_lock);
 797         mutex_destroy(&nic_data->udp_tunnels_lock);
 798
 799         efx_mcdi_fini(efx);
 800 fail2:
 801         efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
 802 fail1:
 803         kfree(nic_data);
 804         efx->nic_data = NULL;
 805         return rc;
 806 }
 807
 808 static int efx_ef10_free_vis(struct efx_nic *efx)
 809 {
 810         MCDI_DECLARE_BUF_ERR(outbuf);
 811         size_t outlen;
 812         int rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FREE_VIS, NULL, 0,
 813                                     outbuf, sizeof(outbuf), &outlen);
 814
 815         /* -EALREADY means nothing to free, so ignore */
 816         if (rc == -EALREADY)
 817                 rc = 0;
 818         if (rc)
 819                 efx_mcdi_display_error(efx, MC_CMD_FREE_VIS, 0, outbuf, outlen,
 820                                        rc);
 821         return rc;
 822 }
 823
 824 #ifdef EFX_USE_PIO
 825
 826 static void efx_ef10_free_piobufs(struct efx_nic *efx)
 827 {
 828         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 829         MCDI_DECLARE_BUF(inbuf, MC_CMD_FREE_PIOBUF_IN_LEN);
 830         unsigned int i;
 831         int rc;
 832
 833         BUILD_BUG_ON(MC_CMD_FREE_PIOBUF_OUT_LEN != 0);
 834
 835         for (i = 0; i < nic_data->n_piobufs; i++) {
 836                 MCDI_SET_DWORD(inbuf, FREE_PIOBUF_IN_PIOBUF_HANDLE,
 837                                nic_data->piobuf_handle[i]);
 838                 rc = efx_mcdi_rpc(efx, MC_CMD_FREE_PIOBUF, inbuf, sizeof(inbuf),
 839                                   NULL, 0, NULL);
 840                 WARN_ON(rc);
 841         }
 842
 843         nic_data->n_piobufs = 0;
 844 }
 845
 846 static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
 847 {
 848         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 849         MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_PIOBUF_OUT_LEN);
 850         unsigned int i;
 851         size_t outlen;
 852         int rc = 0;
 853
 854         BUILD_BUG_ON(MC_CMD_ALLOC_PIOBUF_IN_LEN != 0);
 855
 856         for (i = 0; i < n; i++) {
 857                 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_ALLOC_PIOBUF, NULL, 0,
 858                                         outbuf, sizeof(outbuf), &outlen);
 859                 if (rc) {
 860                         /* Don't display the MC error if we didn't have space
 861                          * for a VF.
 862                          */
 863                         if (!(efx_ef10_is_vf(efx) && rc == -ENOSPC))
 864                                 efx_mcdi_display_error(efx, MC_CMD_ALLOC_PIOBUF,
 865                                                        0, outbuf, outlen, rc);
 866                         break;
 867                 }
 868                 if (outlen < MC_CMD_ALLOC_PIOBUF_OUT_LEN) {
 869                         rc = -EIO;
 870                         break;
 871                 }
 872                 nic_data->piobuf_handle[i] =
 873                         MCDI_DWORD(outbuf, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE);
 874                 netif_dbg(efx, probe, efx->net_dev,
 875                           "allocated PIO buffer %u handle %x\n", i,
 876                           nic_data->piobuf_handle[i]);
 877         }
 878
 879         nic_data->n_piobufs = i;
 880         if (rc)
 881                 efx_ef10_free_piobufs(efx);
 882         return rc;
 883 }
 884
 885 static int efx_ef10_link_piobufs(struct efx_nic *efx)
 886 {
 887         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 888         MCDI_DECLARE_BUF(inbuf, MC_CMD_LINK_PIOBUF_IN_LEN);
 889         struct efx_channel *channel;
 890         struct efx_tx_queue *tx_queue;
 891         unsigned int offset, index;
 892         int rc;
 893
 894         BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_OUT_LEN != 0);
 895         BUILD_BUG_ON(MC_CMD_UNLINK_PIOBUF_OUT_LEN != 0);
 896
 897         /* Link a buffer to each VI in the write-combining mapping */
 898         for (index = 0; index < nic_data->n_piobufs; ++index) {
 899                 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_PIOBUF_HANDLE,
 900                                nic_data->piobuf_handle[index]);
 901                 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_TXQ_INSTANCE,
 902                                nic_data->pio_write_vi_base + index);
 903                 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
 904                                   inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
 905                                   NULL, 0, NULL);
 906                 if (rc) {
 907                         netif_err(efx, drv, efx->net_dev,
 908                                   "failed to link VI %u to PIO buffer %u (%d)\n",
 909                                   nic_data->pio_write_vi_base + index, index,
 910                                   rc);
 911                         goto fail;
 912                 }
 913                 netif_dbg(efx, probe, efx->net_dev,
 914                           "linked VI %u to PIO buffer %u\n",
 915                           nic_data->pio_write_vi_base + index, index);
 916         }
 917
 918         /* Link a buffer to each TX queue */
 919         efx_for_each_channel(channel, efx) {
 920                 efx_for_each_channel_tx_queue(tx_queue, channel) {
 921                         /* We assign the PIO buffers to queues in
 922                          * reverse order to allow for the following
 923                          * special case.
 924                          */
 925                         offset = ((efx->tx_channel_offset + efx->n_tx_channels -
 926                                    tx_queue->channel->channel - 1) *
 927                                   efx_piobuf_size);
 928                         index = offset / nic_data->piobuf_size;
 929                         offset = offset % nic_data->piobuf_size;
 930
 931                         /* When the host page size is 4K, the first
 932                          * host page in the WC mapping may be within
 933                          * the same VI page as the last TX queue.  We
 934                          * can only link one buffer to each VI.
 935                          */
 936                         if (tx_queue->queue == nic_data->pio_write_vi_base) {
 937                                 BUG_ON(index != 0);
 938                                 rc = 0;
 939                         } else {
 940                                 MCDI_SET_DWORD(inbuf,
 941                                                LINK_PIOBUF_IN_PIOBUF_HANDLE,
 942                                                nic_data->piobuf_handle[index]);
 943                                 MCDI_SET_DWORD(inbuf,
 944                                                LINK_PIOBUF_IN_TXQ_INSTANCE,
 945                                                tx_queue->queue);
 946                                 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
 947                                                   inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
 948                                                   NULL, 0, NULL);
 949                         }
 950
 951                         if (rc) {
 952                                 /* This is non-fatal; the TX path just
 953                                  * won't use PIO for this queue
 954                                  */
 955                                 netif_err(efx, drv, efx->net_dev,
 956                                           "failed to link VI %u to PIO buffer %u (%d)\n",
 957                                           tx_queue->queue, index, rc);
 958                                 tx_queue->piobuf = NULL;
 959                         } else {
 960                                 tx_queue->piobuf =
 961                                         nic_data->pio_write_base +
 962                                         index * efx->vi_stride + offset;
 963                                 tx_queue->piobuf_offset = offset;
 964                                 netif_dbg(efx, probe, efx->net_dev,
 965                                           "linked VI %u to PIO buffer %u offset %x addr %p\n",
 966                                           tx_queue->queue, index,
 967                                           tx_queue->piobuf_offset,
 968                                           tx_queue->piobuf);
 969                         }
 970                 }
 971         }
 972
 973         return 0;
 974
 975 fail:
 976         /* inbuf was defined for MC_CMD_LINK_PIOBUF.  We can use the same
 977          * buffer for MC_CMD_UNLINK_PIOBUF because it's shorter.
 978          */
 979         BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_IN_LEN < MC_CMD_UNLINK_PIOBUF_IN_LEN);
 980         while (index--) {
 981                 MCDI_SET_DWORD(inbuf, UNLINK_PIOBUF_IN_TXQ_INSTANCE,
 982                                nic_data->pio_write_vi_base + index);
 983                 efx_mcdi_rpc(efx, MC_CMD_UNLINK_PIOBUF,
 984                              inbuf, MC_CMD_UNLINK_PIOBUF_IN_LEN,
 985                              NULL, 0, NULL);
 986         }
 987         return rc;
 988 }
 989
 990 static void efx_ef10_forget_old_piobufs(struct efx_nic *efx)
 991 {
 992         struct efx_channel *channel;
 993         struct efx_tx_queue *tx_queue;
 994
 995         /* All our existing PIO buffers went away */
 996         efx_for_each_channel(channel, efx)
 997                 efx_for_each_channel_tx_queue(tx_queue, channel)
 998                         tx_queue->piobuf = NULL;
 999 }
1000
1001 #else /* !EFX_USE_PIO */
1002
1003 static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
1004 {
1005         return n == 0 ? 0 : -ENOBUFS;
1006 }
1007
1008 static int efx_ef10_link_piobufs(struct efx_nic *efx)
1009 {
1010         return 0;
1011 }
1012
1013 static void efx_ef10_free_piobufs(struct efx_nic *efx)
1014 {
1015 }
1016
1017 static void efx_ef10_forget_old_piobufs(struct efx_nic *efx)
1018 {
1019 }
1020
1021 #endif /* EFX_USE_PIO */
1022
1023 static void efx_ef10_remove(struct efx_nic *efx)
1024 {
1025         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1026         int rc;
1027
1028 #ifdef CONFIG_SFC_SRIOV
1029         struct efx_ef10_nic_data *nic_data_pf;
1030         struct pci_dev *pci_dev_pf;
1031         struct efx_nic *efx_pf;
1032         struct ef10_vf *vf;
1033
1034         if (efx->pci_dev->is_virtfn) {
1035                 pci_dev_pf = efx->pci_dev->physfn;
1036                 if (pci_dev_pf) {
1037                         efx_pf = pci_get_drvdata(pci_dev_pf);
1038                         nic_data_pf = efx_pf->nic_data;
1039                         vf = nic_data_pf->vf + nic_data->vf_index;
1040                         vf->efx = NULL;
1041                 } else
1042                         netif_info(efx, drv, efx->net_dev,
1043                                    "Could not get the PF id from VF\n");
1044         }
1045 #endif
1046
1047         efx_ef10_cleanup_vlans(efx);
1048         mutex_destroy(&nic_data->vlan_lock);
1049
1050         efx_ptp_remove(efx);
1051
1052         efx_mcdi_mon_remove(efx);
1053
1054         efx_ef10_rx_free_indir_table(efx);
1055
1056         if (nic_data->wc_membase)
1057                 iounmap(nic_data->wc_membase);
1058
1059         rc = efx_ef10_free_vis(efx);
1060         WARN_ON(rc != 0);
1061
1062         if (!nic_data->must_restore_piobufs)
1063                 efx_ef10_free_piobufs(efx);
1064
1065         device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
1066         device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag);
1067
1068         efx_mcdi_detach(efx);
1069
1070         memset(nic_data->udp_tunnels, 0, sizeof(nic_data->udp_tunnels));
1071         mutex_lock(&nic_data->udp_tunnels_lock);
1072         (void)efx_ef10_set_udp_tnl_ports(efx, true);
1073         mutex_unlock(&nic_data->udp_tunnels_lock);
1074
1075         mutex_destroy(&nic_data->udp_tunnels_lock);
1076
1077         efx_mcdi_fini(efx);
1078         efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
1079         kfree(nic_data);
1080 }
1081
1082 static int efx_ef10_probe_pf(struct efx_nic *efx)
1083 {
1084         return efx_ef10_probe(efx);
1085 }
1086
1087 int efx_ef10_vadaptor_query(struct efx_nic *efx, unsigned int port_id,
1088                             u32 *port_flags, u32 *vadaptor_flags,
1089                             unsigned int *vlan_tags)
1090 {
1091         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1092         MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_QUERY_IN_LEN);
1093         MCDI_DECLARE_BUF(outbuf, MC_CMD_VADAPTOR_QUERY_OUT_LEN);
1094         size_t outlen;
1095         int rc;
1096
1097         if (nic_data->datapath_caps &
1098             (1 << MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_LBN)) {
1099                 MCDI_SET_DWORD(inbuf, VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID,
1100                                port_id);
1101
1102                 rc = efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_QUERY, inbuf, sizeof(inbuf),
1103                                   outbuf, sizeof(outbuf), &outlen);
1104                 if (rc)
1105                         return rc;
1106
1107                 if (outlen < sizeof(outbuf)) {
1108                         rc = -EIO;
1109                         return rc;
1110                 }
1111         }
1112
1113         if (port_flags)
1114                 *port_flags = MCDI_DWORD(outbuf, VADAPTOR_QUERY_OUT_PORT_FLAGS);
1115         if (vadaptor_flags)
1116                 *vadaptor_flags =
1117                         MCDI_DWORD(outbuf, VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS);
1118         if (vlan_tags)
1119                 *vlan_tags =
1120                         MCDI_DWORD(outbuf,
1121                                    VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS);
1122
1123         return 0;
1124 }
1125
1126 int efx_ef10_vadaptor_alloc(struct efx_nic *efx, unsigned int port_id)
1127 {
1128         MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_ALLOC_IN_LEN);
1129
1130         MCDI_SET_DWORD(inbuf, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID, port_id);
1131         return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_ALLOC, inbuf, sizeof(inbuf),
1132                             NULL, 0, NULL);
1133 }
1134
1135 int efx_ef10_vadaptor_free(struct efx_nic *efx, unsigned int port_id)
1136 {
1137         MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_FREE_IN_LEN);
1138
1139         MCDI_SET_DWORD(inbuf, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID, port_id);
1140         return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_FREE, inbuf, sizeof(inbuf),
1141                             NULL, 0, NULL);
1142 }
1143
1144 int efx_ef10_vport_add_mac(struct efx_nic *efx,
1145                            unsigned int port_id, u8 *mac)
1146 {
1147         MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN);
1148
1149         MCDI_SET_DWORD(inbuf, VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID, port_id);
1150         ether_addr_copy(MCDI_PTR(inbuf, VPORT_ADD_MAC_ADDRESS_IN_MACADDR), mac);
1151
1152         return efx_mcdi_rpc(efx, MC_CMD_VPORT_ADD_MAC_ADDRESS, inbuf,
1153                             sizeof(inbuf), NULL, 0, NULL);
1154 }
1155
1156 int efx_ef10_vport_del_mac(struct efx_nic *efx,
1157                            unsigned int port_id, u8 *mac)
1158 {
1159         MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN);
1160
1161         MCDI_SET_DWORD(inbuf, VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID, port_id);
1162         ether_addr_copy(MCDI_PTR(inbuf, VPORT_DEL_MAC_ADDRESS_IN_MACADDR), mac);
1163
1164         return efx_mcdi_rpc(efx, MC_CMD_VPORT_DEL_MAC_ADDRESS, inbuf,
1165                             sizeof(inbuf), NULL, 0, NULL);
1166 }
1167
1168 #ifdef CONFIG_SFC_SRIOV
1169 static int efx_ef10_probe_vf(struct efx_nic *efx)
1170 {
1171         int rc;
1172         struct pci_dev *pci_dev_pf;
1173
1174         /* If the parent PF has no VF data structure, it doesn't know about this
1175          * VF so fail probe.  The VF needs to be re-created.  This can happen
1176          * if the PF driver is unloaded while the VF is assigned to a guest.
1177          */
1178         pci_dev_pf = efx->pci_dev->physfn;
1179         if (pci_dev_pf) {
1180                 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
1181                 struct efx_ef10_nic_data *nic_data_pf = efx_pf->nic_data;
1182
1183                 if (!nic_data_pf->vf) {
1184                         netif_info(efx, drv, efx->net_dev,
1185                                    "The VF cannot link to its parent PF; "
1186                                    "please destroy and re-create the VF\n");
1187                         return -EBUSY;
1188                 }
1189         }
1190
1191         rc = efx_ef10_probe(efx);
1192         if (rc)
1193                 return rc;
1194
1195         rc = efx_ef10_get_vf_index(efx);
1196         if (rc)
1197                 goto fail;
1198
1199         if (efx->pci_dev->is_virtfn) {
1200                 if (efx->pci_dev->physfn) {
1201                         struct efx_nic *efx_pf =
1202                                 pci_get_drvdata(efx->pci_dev->physfn);
1203                         struct efx_ef10_nic_data *nic_data_p = efx_pf->nic_data;
1204                         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1205
1206                         nic_data_p->vf[nic_data->vf_index].efx = efx;
1207                         nic_data_p->vf[nic_data->vf_index].pci_dev =
1208                                 efx->pci_dev;
1209                 } else
1210                         netif_info(efx, drv, efx->net_dev,
1211                                    "Could not get the PF id from VF\n");
1212         }
1213
1214         return 0;
1215
1216 fail:
1217         efx_ef10_remove(efx);
1218         return rc;
1219 }
1220 #else
1221 static int efx_ef10_probe_vf(struct efx_nic *efx __attribute__ ((unused)))
1222 {
1223         return 0;
1224 }
1225 #endif
1226
1227 static int efx_ef10_alloc_vis(struct efx_nic *efx,
1228                               unsigned int min_vis, unsigned int max_vis)
1229 {
1230         MCDI_DECLARE_BUF(inbuf, MC_CMD_ALLOC_VIS_IN_LEN);
1231         MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_VIS_OUT_LEN);
1232         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1233         size_t outlen;
1234         int rc;
1235
1236         MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MIN_VI_COUNT, min_vis);
1237         MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MAX_VI_COUNT, max_vis);
1238         rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_VIS, inbuf, sizeof(inbuf),
1239                           outbuf, sizeof(outbuf), &outlen);
1240         if (rc != 0)
1241                 return rc;
1242
1243         if (outlen < MC_CMD_ALLOC_VIS_OUT_LEN)
1244                 return -EIO;
1245
1246         netif_dbg(efx, drv, efx->net_dev, "base VI is A0x%03x\n",
1247                   MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE));
1248
1249         nic_data->vi_base = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE);
1250         nic_data->n_allocated_vis = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_COUNT);
1251         return 0;
1252 }
1253
1254 /* Note that the failure path of this function does not free
1255  * resources, as this will be done by efx_ef10_remove().
1256  */
1257 static int efx_ef10_dimension_resources(struct efx_nic *efx)
1258 {
1259         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1260         unsigned int uc_mem_map_size, wc_mem_map_size;
1261         unsigned int min_vis = max(EFX_TXQ_TYPES,
1262                                    efx_separate_tx_channels ? 2 : 1);
1263         unsigned int channel_vis, pio_write_vi_base, max_vis;
1264         void __iomem *membase;
1265         int rc;
1266
1267         channel_vis = max(efx->n_channels, efx->n_tx_channels * EFX_TXQ_TYPES);
1268
1269 #ifdef EFX_USE_PIO
1270         /* Try to allocate PIO buffers if wanted and if the full
1271          * number of PIO buffers would be sufficient to allocate one
1272          * copy-buffer per TX channel.  Failure is non-fatal, as there
1273          * are only a small number of PIO buffers shared between all
1274          * functions of the controller.
1275          */
1276         if (efx_piobuf_size != 0 &&
1277             nic_data->piobuf_size / efx_piobuf_size * EF10_TX_PIOBUF_COUNT >=
1278             efx->n_tx_channels) {
1279                 unsigned int n_piobufs =
1280                         DIV_ROUND_UP(efx->n_tx_channels,
1281                                      nic_data->piobuf_size / efx_piobuf_size);
1282
1283                 rc = efx_ef10_alloc_piobufs(efx, n_piobufs);
1284                 if (rc == -ENOSPC)
1285                         netif_dbg(efx, probe, efx->net_dev,
1286                                   "out of PIO buffers; cannot allocate more\n");
1287                 else if (rc == -EPERM)
1288                         netif_dbg(efx, probe, efx->net_dev,
1289                                   "not permitted to allocate PIO buffers\n");
1290                 else if (rc)
1291                         netif_err(efx, probe, efx->net_dev,
1292                                   "failed to allocate PIO buffers (%d)\n", rc);
1293                 else
1294                         netif_dbg(efx, probe, efx->net_dev,
1295                                   "allocated %u PIO buffers\n", n_piobufs);
1296         }
1297 #else
1298         nic_data->n_piobufs = 0;
1299 #endif
1300
1301         /* PIO buffers should be mapped with write-combining enabled,
1302          * and we want to make single UC and WC mappings rather than
1303          * several of each (in fact that's the only option if host
1304          * page size is >4K).  So we may allocate some extra VIs just
1305          * for writing PIO buffers through.
1306          *
1307          * The UC mapping contains (channel_vis - 1) complete VIs and the
1308          * first 4K of the next VI.  Then the WC mapping begins with
1309          * the remainder of this last VI.
1310          */
1311         uc_mem_map_size = PAGE_ALIGN((channel_vis - 1) * efx->vi_stride +
1312                                      ER_DZ_TX_PIOBUF);
1313         if (nic_data->n_piobufs) {
1314                 /* pio_write_vi_base rounds down to give the number of complete
1315                  * VIs inside the UC mapping.
1316                  */
1317                 pio_write_vi_base = uc_mem_map_size / efx->vi_stride;
1318                 wc_mem_map_size = (PAGE_ALIGN((pio_write_vi_base +
1319                                                nic_data->n_piobufs) *
1320                                               efx->vi_stride) -
1321                                    uc_mem_map_size);
1322                 max_vis = pio_write_vi_base + nic_data->n_piobufs;
1323         } else {
1324                 pio_write_vi_base = 0;
1325                 wc_mem_map_size = 0;
1326                 max_vis = channel_vis;
1327         }
1328
1329         /* In case the last attached driver failed to free VIs, do it now */
1330         rc = efx_ef10_free_vis(efx);
1331         if (rc != 0)
1332                 return rc;
1333
1334         rc = efx_ef10_alloc_vis(efx, min_vis, max_vis);
1335         if (rc != 0)
1336                 return rc;
1337
1338         if (nic_data->n_allocated_vis < channel_vis) {
1339                 netif_info(efx, drv, efx->net_dev,
1340                            "Could not allocate enough VIs to satisfy RSS"
1341                            " requirements. Performance may not be optimal.\n");
1342                 /* We didn't get the VIs to populate our channels.
1343                  * We could keep what we got but then we'd have more
1344                  * interrupts than we need.
1345                  * Instead calculate new max_channels and restart
1346                  */
1347                 efx->max_channels = nic_data->n_allocated_vis;
1348                 efx->max_tx_channels =
1349                         nic_data->n_allocated_vis / EFX_TXQ_TYPES;
1350
1351                 efx_ef10_free_vis(efx);
1352                 return -EAGAIN;
1353         }
1354
1355         /* If we didn't get enough VIs to map all the PIO buffers, free the
1356          * PIO buffers
1357          */
1358         if (nic_data->n_piobufs &&
1359             nic_data->n_allocated_vis <
1360             pio_write_vi_base + nic_data->n_piobufs) {
1361                 netif_dbg(efx, probe, efx->net_dev,
1362                           "%u VIs are not sufficient to map %u PIO buffers\n",
1363                           nic_data->n_allocated_vis, nic_data->n_piobufs);
1364                 efx_ef10_free_piobufs(efx);
1365         }
1366
1367         /* Shrink the original UC mapping of the memory BAR */
1368         membase = ioremap_nocache(efx->membase_phys, uc_mem_map_size);
1369         if (!membase) {
1370                 netif_err(efx, probe, efx->net_dev,
1371                           "could not shrink memory BAR to %x\n",
1372                           uc_mem_map_size);
1373                 return -ENOMEM;
1374         }
1375         iounmap(efx->membase);
1376         efx->membase = membase;
1377
1378         /* Set up the WC mapping if needed */
1379         if (wc_mem_map_size) {
1380                 nic_data->wc_membase = ioremap_wc(efx->membase_phys +
1381                                                   uc_mem_map_size,
1382                                                   wc_mem_map_size);
1383                 if (!nic_data->wc_membase) {
1384                         netif_err(efx, probe, efx->net_dev,
1385                                   "could not allocate WC mapping of size %x\n",
1386                                   wc_mem_map_size);
1387                         return -ENOMEM;
1388                 }
1389                 nic_data->pio_write_vi_base = pio_write_vi_base;
1390                 nic_data->pio_write_base =
1391                         nic_data->wc_membase +
1392                         (pio_write_vi_base * efx->vi_stride + ER_DZ_TX_PIOBUF -
1393                          uc_mem_map_size);
1394
1395                 rc = efx_ef10_link_piobufs(efx);
1396                 if (rc)
1397                         efx_ef10_free_piobufs(efx);
1398         }
1399
1400         netif_dbg(efx, probe, efx->net_dev,
1401                   "memory BAR at %pa (virtual %p+%x UC, %p+%x WC)\n",
1402                   &efx->membase_phys, efx->membase, uc_mem_map_size,
1403                   nic_data->wc_membase, wc_mem_map_size);
1404
1405         return 0;
1406 }
1407
1408 static int efx_ef10_init_nic(struct efx_nic *efx)
1409 {
1410         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1411         int rc;
1412
1413         if (nic_data->must_check_datapath_caps) {
1414                 rc = efx_ef10_init_datapath_caps(efx);
1415                 if (rc)
1416                         return rc;
1417                 nic_data->must_check_datapath_caps = false;
1418         }
1419
1420         if (nic_data->must_realloc_vis) {
1421                 /* We cannot let the number of VIs change now */
1422                 rc = efx_ef10_alloc_vis(efx, nic_data->n_allocated_vis,
1423                                         nic_data->n_allocated_vis);
1424                 if (rc)
1425                         return rc;
1426                 nic_data->must_realloc_vis = false;
1427         }
1428
1429         if (nic_data->must_restore_piobufs && nic_data->n_piobufs) {
1430                 rc = efx_ef10_alloc_piobufs(efx, nic_data->n_piobufs);
1431                 if (rc == 0) {
1432                         rc = efx_ef10_link_piobufs(efx);
1433                         if (rc)
1434                                 efx_ef10_free_piobufs(efx);
1435                 }
1436
1437                 /* Log an error on failure, but this is non-fatal.
1438                  * Permission errors are less important - we've presumably
1439                  * had the PIO buffer licence removed.
1440                  */
1441                 if (rc == -EPERM)
1442                         netif_dbg(efx, drv, efx->net_dev,
1443                                   "not permitted to restore PIO buffers\n");
1444                 else if (rc)
1445                         netif_err(efx, drv, efx->net_dev,
1446                                   "failed to restore PIO buffers (%d)\n", rc);
1447                 nic_data->must_restore_piobufs = false;
1448         }
1449
1450         /* don't fail init if RSS setup doesn't work */
1451         rc = efx->type->rx_push_rss_config(efx, false, efx->rx_indir_table, NULL);
1452         efx->rss_active = (rc == 0);
1453
1454         return 0;
1455 }
1456
1457 static void efx_ef10_reset_mc_allocations(struct efx_nic *efx)
1458 {
1459         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1460 #ifdef CONFIG_SFC_SRIOV
1461         unsigned int i;
1462 #endif
1463
1464         /* All our allocations have been reset */
1465         nic_data->must_realloc_vis = true;
1466         nic_data->must_restore_filters = true;
1467         nic_data->must_restore_piobufs = true;
1468         efx_ef10_forget_old_piobufs(efx);
1469         nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
1470
1471         /* Driver-created vswitches and vports must be re-created */
1472         nic_data->must_probe_vswitching = true;
1473         nic_data->vport_id = EVB_PORT_ID_ASSIGNED;
1474 #ifdef CONFIG_SFC_SRIOV
1475         if (nic_data->vf)
1476                 for (i = 0; i < efx->vf_count; i++)
1477                         nic_data->vf[i].vport_id = 0;
1478 #endif
1479 }
1480
1481 static enum reset_type efx_ef10_map_reset_reason(enum reset_type reason)
1482 {
1483         if (reason == RESET_TYPE_MC_FAILURE)
1484                 return RESET_TYPE_DATAPATH;
1485
1486         return efx_mcdi_map_reset_reason(reason);
1487 }
1488
1489 static int efx_ef10_map_reset_flags(u32 *flags)
1490 {
1491         enum {
1492                 EF10_RESET_PORT = ((ETH_RESET_MAC | ETH_RESET_PHY) <<
1493                                    ETH_RESET_SHARED_SHIFT),
1494                 EF10_RESET_MC = ((ETH_RESET_DMA | ETH_RESET_FILTER |
1495                                   ETH_RESET_OFFLOAD | ETH_RESET_MAC |
1496                                   ETH_RESET_PHY | ETH_RESET_MGMT) <<
1497                                  ETH_RESET_SHARED_SHIFT)
1498         };
1499
1500         /* We assume for now that our PCI function is permitted to
1501          * reset everything.
1502          */
1503
1504         if ((*flags & EF10_RESET_MC) == EF10_RESET_MC) {
1505                 *flags &= ~EF10_RESET_MC;
1506                 return RESET_TYPE_WORLD;
1507         }
1508
1509         if ((*flags & EF10_RESET_PORT) == EF10_RESET_PORT) {
1510                 *flags &= ~EF10_RESET_PORT;
1511                 return RESET_TYPE_ALL;
1512         }
1513
1514         /* no invisible reset implemented */
1515
1516         return -EINVAL;
1517 }
1518
1519 static int efx_ef10_reset(struct efx_nic *efx, enum reset_type reset_type)
1520 {
1521         int rc = efx_mcdi_reset(efx, reset_type);
1522
1523         /* Unprivileged functions return -EPERM, but need to return success
1524          * here so that the datapath is brought back up.
1525          */
1526         if (reset_type == RESET_TYPE_WORLD && rc == -EPERM)
1527                 rc = 0;
1528
1529         /* If it was a port reset, trigger reallocation of MC resources.
1530          * Note that on an MC reset nothing needs to be done now because we'll
1531          * detect the MC reset later and handle it then.
1532          * For an FLR, we never get an MC reset event, but the MC has reset all
1533          * resources assigned to us, so we have to trigger reallocation now.
1534          */
1535         if ((reset_type == RESET_TYPE_ALL ||
1536              reset_type == RESET_TYPE_MCDI_TIMEOUT) && !rc)
1537                 efx_ef10_reset_mc_allocations(efx);
1538         return rc;
1539 }
1540
1541 #define EF10_DMA_STAT(ext_name, mcdi_name)                      \
1542         [EF10_STAT_ ## ext_name] =                              \
1543         { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
1544 #define EF10_DMA_INVIS_STAT(int_name, mcdi_name)                \
1545         [EF10_STAT_ ## int_name] =                              \
1546         { NULL, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
1547 #define EF10_OTHER_STAT(ext_name)                               \
1548         [EF10_STAT_ ## ext_name] = { #ext_name, 0, 0 }
1549 #define GENERIC_SW_STAT(ext_name)                               \
1550         [GENERIC_STAT_ ## ext_name] = { #ext_name, 0, 0 }
1551
1552 static const struct efx_hw_stat_desc efx_ef10_stat_desc[EF10_STAT_COUNT] = {
1553         EF10_DMA_STAT(port_tx_bytes, TX_BYTES),
1554         EF10_DMA_STAT(port_tx_packets, TX_PKTS),
1555         EF10_DMA_STAT(port_tx_pause, TX_PAUSE_PKTS),
1556         EF10_DMA_STAT(port_tx_control, TX_CONTROL_PKTS),
1557         EF10_DMA_STAT(port_tx_unicast, TX_UNICAST_PKTS),
1558         EF10_DMA_STAT(port_tx_multicast, TX_MULTICAST_PKTS),
1559         EF10_DMA_STAT(port_tx_broadcast, TX_BROADCAST_PKTS),
1560         EF10_DMA_STAT(port_tx_lt64, TX_LT64_PKTS),
1561         EF10_DMA_STAT(port_tx_64, TX_64_PKTS),
1562         EF10_DMA_STAT(port_tx_65_to_127, TX_65_TO_127_PKTS),
1563         EF10_DMA_STAT(port_tx_128_to_255, TX_128_TO_255_PKTS),
1564         EF10_DMA_STAT(port_tx_256_to_511, TX_256_TO_511_PKTS),
1565         EF10_DMA_STAT(port_tx_512_to_1023, TX_512_TO_1023_PKTS),
1566         EF10_DMA_STAT(port_tx_1024_to_15xx, TX_1024_TO_15XX_PKTS),
1567         EF10_DMA_STAT(port_tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS),
1568         EF10_DMA_STAT(port_rx_bytes, RX_BYTES),
1569         EF10_DMA_INVIS_STAT(port_rx_bytes_minus_good_bytes, RX_BAD_BYTES),
1570         EF10_OTHER_STAT(port_rx_good_bytes),
1571         EF10_OTHER_STAT(port_rx_bad_bytes),
1572         EF10_DMA_STAT(port_rx_packets, RX_PKTS),
1573         EF10_DMA_STAT(port_rx_good, RX_GOOD_PKTS),
1574         EF10_DMA_STAT(port_rx_bad, RX_BAD_FCS_PKTS),
1575         EF10_DMA_STAT(port_rx_pause, RX_PAUSE_PKTS),
1576         EF10_DMA_STAT(port_rx_control, RX_CONTROL_PKTS),
1577         EF10_DMA_STAT(port_rx_unicast, RX_UNICAST_PKTS),
1578         EF10_DMA_STAT(port_rx_multicast, RX_MULTICAST_PKTS),
1579         EF10_DMA_STAT(port_rx_broadcast, RX_BROADCAST_PKTS),
1580         EF10_DMA_STAT(port_rx_lt64, RX_UNDERSIZE_PKTS),
1581         EF10_DMA_STAT(port_rx_64, RX_64_PKTS),
1582         EF10_DMA_STAT(port_rx_65_to_127, RX_65_TO_127_PKTS),
1583         EF10_DMA_STAT(port_rx_128_to_255, RX_128_TO_255_PKTS),
1584         EF10_DMA_STAT(port_rx_256_to_511, RX_256_TO_511_PKTS),
1585         EF10_DMA_STAT(port_rx_512_to_1023, RX_512_TO_1023_PKTS),
1586         EF10_DMA_STAT(port_rx_1024_to_15xx, RX_1024_TO_15XX_PKTS),
1587         EF10_DMA_STAT(port_rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS),
1588         EF10_DMA_STAT(port_rx_gtjumbo, RX_GTJUMBO_PKTS),
1589         EF10_DMA_STAT(port_rx_bad_gtjumbo, RX_JABBER_PKTS),
1590         EF10_DMA_STAT(port_rx_overflow, RX_OVERFLOW_PKTS),
1591         EF10_DMA_STAT(port_rx_align_error, RX_ALIGN_ERROR_PKTS),
1592         EF10_DMA_STAT(port_rx_length_error, RX_LENGTH_ERROR_PKTS),
1593         EF10_DMA_STAT(port_rx_nodesc_drops, RX_NODESC_DROPS),
1594         GENERIC_SW_STAT(rx_nodesc_trunc),
1595         GENERIC_SW_STAT(rx_noskb_drops),
1596         EF10_DMA_STAT(port_rx_pm_trunc_bb_overflow, PM_TRUNC_BB_OVERFLOW),
1597         EF10_DMA_STAT(port_rx_pm_discard_bb_overflow, PM_DISCARD_BB_OVERFLOW),
1598         EF10_DMA_STAT(port_rx_pm_trunc_vfifo_full, PM_TRUNC_VFIFO_FULL),
1599         EF10_DMA_STAT(port_rx_pm_discard_vfifo_full, PM_DISCARD_VFIFO_FULL),
1600         EF10_DMA_STAT(port_rx_pm_trunc_qbb, PM_TRUNC_QBB),
1601         EF10_DMA_STAT(port_rx_pm_discard_qbb, PM_DISCARD_QBB),
1602         EF10_DMA_STAT(port_rx_pm_discard_mapping, PM_DISCARD_MAPPING),
1603         EF10_DMA_STAT(port_rx_dp_q_disabled_packets, RXDP_Q_DISABLED_PKTS),
1604         EF10_DMA_STAT(port_rx_dp_di_dropped_packets, RXDP_DI_DROPPED_PKTS),
1605         EF10_DMA_STAT(port_rx_dp_streaming_packets, RXDP_STREAMING_PKTS),
1606         EF10_DMA_STAT(port_rx_dp_hlb_fetch, RXDP_HLB_FETCH_CONDITIONS),
1607         EF10_DMA_STAT(port_rx_dp_hlb_wait, RXDP_HLB_WAIT_CONDITIONS),
1608         EF10_DMA_STAT(rx_unicast, VADAPTER_RX_UNICAST_PACKETS),
1609         EF10_DMA_STAT(rx_unicast_bytes, VADAPTER_RX_UNICAST_BYTES),
1610         EF10_DMA_STAT(rx_multicast, VADAPTER_RX_MULTICAST_PACKETS),
1611         EF10_DMA_STAT(rx_multicast_bytes, VADAPTER_RX_MULTICAST_BYTES),
1612         EF10_DMA_STAT(rx_broadcast, VADAPTER_RX_BROADCAST_PACKETS),
1613         EF10_DMA_STAT(rx_broadcast_bytes, VADAPTER_RX_BROADCAST_BYTES),
1614         EF10_DMA_STAT(rx_bad, VADAPTER_RX_BAD_PACKETS),
1615         EF10_DMA_STAT(rx_bad_bytes, VADAPTER_RX_BAD_BYTES),
1616         EF10_DMA_STAT(rx_overflow, VADAPTER_RX_OVERFLOW),
1617         EF10_DMA_STAT(tx_unicast, VADAPTER_TX_UNICAST_PACKETS),
1618         EF10_DMA_STAT(tx_unicast_bytes, VADAPTER_TX_UNICAST_BYTES),
1619         EF10_DMA_STAT(tx_multicast, VADAPTER_TX_MULTICAST_PACKETS),
1620         EF10_DMA_STAT(tx_multicast_bytes, VADAPTER_TX_MULTICAST_BYTES),
1621         EF10_DMA_STAT(tx_broadcast, VADAPTER_TX_BROADCAST_PACKETS),
1622         EF10_DMA_STAT(tx_broadcast_bytes, VADAPTER_TX_BROADCAST_BYTES),
1623         EF10_DMA_STAT(tx_bad, VADAPTER_TX_BAD_PACKETS),
1624         EF10_DMA_STAT(tx_bad_bytes, VADAPTER_TX_BAD_BYTES),
1625         EF10_DMA_STAT(tx_overflow, VADAPTER_TX_OVERFLOW),
1626 };
1627
1628 #define HUNT_COMMON_STAT_MASK ((1ULL << EF10_STAT_port_tx_bytes) |      \
1629                                (1ULL << EF10_STAT_port_tx_packets) |    \
1630                                (1ULL << EF10_STAT_port_tx_pause) |      \
1631                                (1ULL << EF10_STAT_port_tx_unicast) |    \
1632                                (1ULL << EF10_STAT_port_tx_multicast) |  \
1633                                (1ULL << EF10_STAT_port_tx_broadcast) |  \
1634                                (1ULL << EF10_STAT_port_rx_bytes) |      \
1635                                (1ULL <<                                 \
1636                                 EF10_STAT_port_rx_bytes_minus_good_bytes) | \
1637                                (1ULL << EF10_STAT_port_rx_good_bytes) | \
1638                                (1ULL << EF10_STAT_port_rx_bad_bytes) |  \
1639                                (1ULL << EF10_STAT_port_rx_packets) |    \
1640                                (1ULL << EF10_STAT_port_rx_good) |       \
1641                                (1ULL << EF10_STAT_port_rx_bad) |        \
1642                                (1ULL << EF10_STAT_port_rx_pause) |      \
1643                                (1ULL << EF10_STAT_port_rx_control) |    \
1644                                (1ULL << EF10_STAT_port_rx_unicast) |    \
1645                                (1ULL << EF10_STAT_port_rx_multicast) |  \
1646                                (1ULL << EF10_STAT_port_rx_broadcast) |  \
1647                                (1ULL << EF10_STAT_port_rx_lt64) |       \
1648                                (1ULL << EF10_STAT_port_rx_64) |         \
1649                                (1ULL << EF10_STAT_port_rx_65_to_127) |  \
1650                                (1ULL << EF10_STAT_port_rx_128_to_255) | \
1651                                (1ULL << EF10_STAT_port_rx_256_to_511) | \
1652                                (1ULL << EF10_STAT_port_rx_512_to_1023) |\
1653                                (1ULL << EF10_STAT_port_rx_1024_to_15xx) |\
1654                                (1ULL << EF10_STAT_port_rx_15xx_to_jumbo) |\
1655                                (1ULL << EF10_STAT_port_rx_gtjumbo) |    \
1656                                (1ULL << EF10_STAT_port_rx_bad_gtjumbo) |\
1657                                (1ULL << EF10_STAT_port_rx_overflow) |   \
1658                                (1ULL << EF10_STAT_port_rx_nodesc_drops) |\
1659                                (1ULL << GENERIC_STAT_rx_nodesc_trunc) | \
1660                                (1ULL << GENERIC_STAT_rx_noskb_drops))
1661
1662 /* On 7000 series NICs, these statistics are only provided by the 10G MAC.
1663  * For a 10G/40G switchable port we do not expose these because they might
1664  * not include all the packets they should.
1665  * On 8000 series NICs these statistics are always provided.
1666  */
1667 #define HUNT_10G_ONLY_STAT_MASK ((1ULL << EF10_STAT_port_tx_control) |  \
1668                                  (1ULL << EF10_STAT_port_tx_lt64) |     \
1669                                  (1ULL << EF10_STAT_port_tx_64) |       \
1670                                  (1ULL << EF10_STAT_port_tx_65_to_127) |\
1671                                  (1ULL << EF10_STAT_port_tx_128_to_255) |\
1672                                  (1ULL << EF10_STAT_port_tx_256_to_511) |\
1673                                  (1ULL << EF10_STAT_port_tx_512_to_1023) |\
1674                                  (1ULL << EF10_STAT_port_tx_1024_to_15xx) |\
1675                                  (1ULL << EF10_STAT_port_tx_15xx_to_jumbo))
1676
1677 /* These statistics are only provided by the 40G MAC.  For a 10G/40G
1678  * switchable port we do expose these because the errors will otherwise
1679  * be silent.
1680  */
1681 #define HUNT_40G_EXTRA_STAT_MASK ((1ULL << EF10_STAT_port_rx_align_error) |\
1682                                   (1ULL << EF10_STAT_port_rx_length_error))
1683
1684 /* These statistics are only provided if the firmware supports the
1685  * capability PM_AND_RXDP_COUNTERS.
1686  */
1687 #define HUNT_PM_AND_RXDP_STAT_MASK (                                    \
1688         (1ULL << EF10_STAT_port_rx_pm_trunc_bb_overflow) |              \
1689         (1ULL << EF10_STAT_port_rx_pm_discard_bb_overflow) |            \
1690         (1ULL << EF10_STAT_port_rx_pm_trunc_vfifo_full) |               \
1691         (1ULL << EF10_STAT_port_rx_pm_discard_vfifo_full) |             \
1692         (1ULL << EF10_STAT_port_rx_pm_trunc_qbb) |                      \
1693         (1ULL << EF10_STAT_port_rx_pm_discard_qbb) |                    \
1694         (1ULL << EF10_STAT_port_rx_pm_discard_mapping) |                \
1695         (1ULL << EF10_STAT_port_rx_dp_q_disabled_packets) |             \
1696         (1ULL << EF10_STAT_port_rx_dp_di_dropped_packets) |             \
1697         (1ULL << EF10_STAT_port_rx_dp_streaming_packets) |              \
1698         (1ULL << EF10_STAT_port_rx_dp_hlb_fetch) |                      \
1699         (1ULL << EF10_STAT_port_rx_dp_hlb_wait))
1700
1701 static u64 efx_ef10_raw_stat_mask(struct efx_nic *efx)
1702 {
1703         u64 raw_mask = HUNT_COMMON_STAT_MASK;
1704         u32 port_caps = efx_mcdi_phy_get_caps(efx);
1705         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1706
1707         if (!(efx->mcdi->fn_flags &
1708               1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL))
1709                 return 0;
1710
1711         if (port_caps & (1 << MC_CMD_PHY_CAP_40000FDX_LBN)) {
1712                 raw_mask |= HUNT_40G_EXTRA_STAT_MASK;
1713                 /* 8000 series have everything even at 40G */
1714                 if (nic_data->datapath_caps2 &
1715                     (1 << MC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN))
1716                         raw_mask |= HUNT_10G_ONLY_STAT_MASK;
1717         } else {
1718                 raw_mask |= HUNT_10G_ONLY_STAT_MASK;
1719         }
1720
1721         if (nic_data->datapath_caps &
1722             (1 << MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN))
1723                 raw_mask |= HUNT_PM_AND_RXDP_STAT_MASK;
1724
1725         return raw_mask;
1726 }
1727
1728 static void efx_ef10_get_stat_mask(struct efx_nic *efx, unsigned long *mask)
1729 {
1730         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1731         u64 raw_mask[2];
1732
1733         raw_mask[0] = efx_ef10_raw_stat_mask(efx);
1734
1735         /* Only show vadaptor stats when EVB capability is present */
1736         if (nic_data->datapath_caps &
1737             (1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN)) {
1738                 raw_mask[0] |= ~((1ULL << EF10_STAT_rx_unicast) - 1);
1739                 raw_mask[1] = (1ULL << (EF10_STAT_COUNT - 63)) - 1;
1740         } else {
1741                 raw_mask[1] = 0;
1742         }
1743
1744 #if BITS_PER_LONG == 64
1745         BUILD_BUG_ON(BITS_TO_LONGS(EF10_STAT_COUNT) != 2);
1746         mask[0] = raw_mask[0];
1747         mask[1] = raw_mask[1];
1748 #else
1749         BUILD_BUG_ON(BITS_TO_LONGS(EF10_STAT_COUNT) != 3);
1750         mask[0] = raw_mask[0] & 0xffffffff;
1751         mask[1] = raw_mask[0] >> 32;
1752         mask[2] = raw_mask[1] & 0xffffffff;
1753 #endif
1754 }
1755
1756 static size_t efx_ef10_describe_stats(struct efx_nic *efx, u8 *names)
1757 {
1758         DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1759
1760         efx_ef10_get_stat_mask(efx, mask);
1761         return efx_nic_describe_stats(efx_ef10_stat_desc, EF10_STAT_COUNT,
1762                                       mask, names);
1763 }
1764
1765 static size_t efx_ef10_update_stats_common(struct efx_nic *efx, u64 *full_stats,
1766                                            struct rtnl_link_stats64 *core_stats)
1767 {
1768         DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1769         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1770         u64 *stats = nic_data->stats;
1771         size_t stats_count = 0, index;
1772
1773         efx_ef10_get_stat_mask(efx, mask);
1774
1775         if (full_stats) {
1776                 for_each_set_bit(index, mask, EF10_STAT_COUNT) {
1777                         if (efx_ef10_stat_desc[index].name) {
1778                                 *full_stats++ = stats[index];
1779                                 ++stats_count;
1780                         }
1781                 }
1782         }
1783
1784         if (!core_stats)
1785                 return stats_count;
1786
1787         if (nic_data->datapath_caps &
1788                         1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN) {
1789                 /* Use vadaptor stats. */
1790                 core_stats->rx_packets = stats[EF10_STAT_rx_unicast] +
1791                                          stats[EF10_STAT_rx_multicast] +
1792                                          stats[EF10_STAT_rx_broadcast];
1793                 core_stats->tx_packets = stats[EF10_STAT_tx_unicast] +
1794                                          stats[EF10_STAT_tx_multicast] +
1795                                          stats[EF10_STAT_tx_broadcast];
1796                 core_stats->rx_bytes = stats[EF10_STAT_rx_unicast_bytes] +
1797                                        stats[EF10_STAT_rx_multicast_bytes] +
1798                                        stats[EF10_STAT_rx_broadcast_bytes];
1799                 core_stats->tx_bytes = stats[EF10_STAT_tx_unicast_bytes] +
1800                                        stats[EF10_STAT_tx_multicast_bytes] +
1801                                        stats[EF10_STAT_tx_broadcast_bytes];
1802                 core_stats->rx_dropped = stats[GENERIC_STAT_rx_nodesc_trunc] +
1803                                          stats[GENERIC_STAT_rx_noskb_drops];
1804                 core_stats->multicast = stats[EF10_STAT_rx_multicast];
1805                 core_stats->rx_crc_errors = stats[EF10_STAT_rx_bad];
1806                 core_stats->rx_fifo_errors = stats[EF10_STAT_rx_overflow];
1807                 core_stats->rx_errors = core_stats->rx_crc_errors;
1808                 core_stats->tx_errors = stats[EF10_STAT_tx_bad];
1809         } else {
1810                 /* Use port stats. */
1811                 core_stats->rx_packets = stats[EF10_STAT_port_rx_packets];
1812                 core_stats->tx_packets = stats[EF10_STAT_port_tx_packets];
1813                 core_stats->rx_bytes = stats[EF10_STAT_port_rx_bytes];
1814                 core_stats->tx_bytes = stats[EF10_STAT_port_tx_bytes];
1815                 core_stats->rx_dropped = stats[EF10_STAT_port_rx_nodesc_drops] +
1816                                          stats[GENERIC_STAT_rx_nodesc_trunc] +
1817                                          stats[GENERIC_STAT_rx_noskb_drops];
1818                 core_stats->multicast = stats[EF10_STAT_port_rx_multicast];
1819                 core_stats->rx_length_errors =
1820                                 stats[EF10_STAT_port_rx_gtjumbo] +
1821                                 stats[EF10_STAT_port_rx_length_error];
1822                 core_stats->rx_crc_errors = stats[EF10_STAT_port_rx_bad];
1823                 core_stats->rx_frame_errors =
1824                                 stats[EF10_STAT_port_rx_align_error];
1825                 core_stats->rx_fifo_errors = stats[EF10_STAT_port_rx_overflow];
1826                 core_stats->rx_errors = (core_stats->rx_length_errors +
1827                                          core_stats->rx_crc_errors +
1828                                          core_stats->rx_frame_errors);
1829         }
1830
1831         return stats_count;
1832 }
1833
1834 static int efx_ef10_try_update_nic_stats_pf(struct efx_nic *efx)
1835 {
1836         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1837         DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1838         __le64 generation_start, generation_end;
1839         u64 *stats = nic_data->stats;
1840         __le64 *dma_stats;
1841
1842         efx_ef10_get_stat_mask(efx, mask);
1843
1844         dma_stats = efx->stats_buffer.addr;
1845
1846         generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
1847         if (generation_end == EFX_MC_STATS_GENERATION_INVALID)
1848                 return 0;
1849         rmb();
1850         efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask,
1851                              stats, efx->stats_buffer.addr, false);
1852         rmb();
1853         generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
1854         if (generation_end != generation_start)
1855                 return -EAGAIN;
1856
1857         /* Update derived statistics */
1858         efx_nic_fix_nodesc_drop_stat(efx,
1859                                      &stats[EF10_STAT_port_rx_nodesc_drops]);
1860         stats[EF10_STAT_port_rx_good_bytes] =
1861                 stats[EF10_STAT_port_rx_bytes] -
1862                 stats[EF10_STAT_port_rx_bytes_minus_good_bytes];
1863         efx_update_diff_stat(&stats[EF10_STAT_port_rx_bad_bytes],
1864                              stats[EF10_STAT_port_rx_bytes_minus_good_bytes]);
1865         efx_update_sw_stats(efx, stats);
1866         return 0;
1867 }
1868
1869
1870 static size_t efx_ef10_update_stats_pf(struct efx_nic *efx, u64 *full_stats,
1871                                        struct rtnl_link_stats64 *core_stats)
1872 {
1873         int retry;
1874
1875         /* If we're unlucky enough to read statistics during the DMA, wait
1876          * up to 10ms for it to finish (typically takes <500us)
1877          */
1878         for (retry = 0; retry < 100; ++retry) {
1879                 if (efx_ef10_try_update_nic_stats_pf(efx) == 0)
1880                         break;
1881                 udelay(100);
1882         }
1883
1884         return efx_ef10_update_stats_common(efx, full_stats, core_stats);
1885 }
1886
1887 static int efx_ef10_try_update_nic_stats_vf(struct efx_nic *efx)
1888 {
1889         MCDI_DECLARE_BUF(inbuf, MC_CMD_MAC_STATS_IN_LEN);
1890         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1891         DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1892         __le64 generation_start, generation_end;
1893         u64 *stats = nic_data->stats;
1894         u32 dma_len = MC_CMD_MAC_NSTATS * sizeof(u64);
1895         struct efx_buffer stats_buf;
1896         __le64 *dma_stats;
1897         int rc;
1898
1899         spin_unlock_bh(&efx->stats_lock);
1900
1901         if (in_interrupt()) {
1902                 /* If in atomic context, cannot update stats.  Just update the
1903                  * software stats and return so the caller can continue.
1904                  */
1905                 spin_lock_bh(&efx->stats_lock);
1906                 efx_update_sw_stats(efx, stats);
1907                 return 0;
1908         }
1909
1910         efx_ef10_get_stat_mask(efx, mask);
1911
1912         rc = efx_nic_alloc_buffer(efx, &stats_buf, dma_len, GFP_ATOMIC);
1913         if (rc) {
1914                 spin_lock_bh(&efx->stats_lock);
1915                 return rc;
1916         }
1917
1918         dma_stats = stats_buf.addr;
1919         dma_stats[MC_CMD_MAC_GENERATION_END] = EFX_MC_STATS_GENERATION_INVALID;
1920
1921         MCDI_SET_QWORD(inbuf, MAC_STATS_IN_DMA_ADDR, stats_buf.dma_addr);
1922         MCDI_POPULATE_DWORD_1(inbuf, MAC_STATS_IN_CMD,
1923                               MAC_STATS_IN_DMA, 1);
1924         MCDI_SET_DWORD(inbuf, MAC_STATS_IN_DMA_LEN, dma_len);
1925         MCDI_SET_DWORD(inbuf, MAC_STATS_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
1926
1927         rc = efx_mcdi_rpc_quiet(efx, MC_CMD_MAC_STATS, inbuf, sizeof(inbuf),
1928                                 NULL, 0, NULL);
1929         spin_lock_bh(&efx->stats_lock);
1930         if (rc) {
1931                 /* Expect ENOENT if DMA queues have not been set up */
1932                 if (rc != -ENOENT || atomic_read(&efx->active_queues))
1933                         efx_mcdi_display_error(efx, MC_CMD_MAC_STATS,
1934                                                sizeof(inbuf), NULL, 0, rc);
1935                 goto out;
1936         }
1937
1938         generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
1939         if (generation_end == EFX_MC_STATS_GENERATION_INVALID) {
1940                 WARN_ON_ONCE(1);
1941                 goto out;
1942         }
1943         rmb();
1944         efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask,
1945                              stats, stats_buf.addr, false);
1946         rmb();
1947         generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
1948         if (generation_end != generation_start) {
1949                 rc = -EAGAIN;
1950                 goto out;
1951         }
1952
1953         efx_update_sw_stats(efx, stats);
1954 out:
1955         efx_nic_free_buffer(efx, &stats_buf);
1956         return rc;
1957 }
1958
1959 static size_t efx_ef10_update_stats_vf(struct efx_nic *efx, u64 *full_stats,
1960                                        struct rtnl_link_stats64 *core_stats)
1961 {
1962         if (efx_ef10_try_update_nic_stats_vf(efx))
1963                 return 0;
1964
1965         return efx_ef10_update_stats_common(efx, full_stats, core_stats);
1966 }
1967
1968 static void efx_ef10_push_irq_moderation(struct efx_channel *channel)
1969 {
1970         struct efx_nic *efx = channel->efx;
1971         unsigned int mode, usecs;
1972         efx_dword_t timer_cmd;
1973
1974         if (channel->irq_moderation_us) {
1975                 mode = 3;
1976                 usecs = channel->irq_moderation_us;
1977         } else {
1978                 mode = 0;
1979                 usecs = 0;
1980         }
1981
1982         if (EFX_EF10_WORKAROUND_61265(efx)) {
1983                 MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_EVQ_TMR_IN_LEN);
1984                 unsigned int ns = usecs * 1000;
1985
1986                 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_INSTANCE,
1987                                channel->channel);
1988                 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_LOAD_REQ_NS, ns);
1989                 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_RELOAD_REQ_NS, ns);
1990                 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_MODE, mode);
1991
1992                 efx_mcdi_rpc_async(efx, MC_CMD_SET_EVQ_TMR,
1993                                    inbuf, sizeof(inbuf), 0, NULL, 0);
1994         } else if (EFX_EF10_WORKAROUND_35388(efx)) {
1995                 unsigned int ticks = efx_usecs_to_ticks(efx, usecs);
1996
1997                 EFX_POPULATE_DWORD_3(timer_cmd, ERF_DD_EVQ_IND_TIMER_FLAGS,
1998                                      EFE_DD_EVQ_IND_TIMER_FLAGS,
1999                                      ERF_DD_EVQ_IND_TIMER_MODE, mode,
2000                                      ERF_DD_EVQ_IND_TIMER_VAL, ticks);
2001                 efx_writed_page(efx, &timer_cmd, ER_DD_EVQ_INDIRECT,
2002                                 channel->channel);
2003         } else {
2004                 unsigned int ticks = efx_usecs_to_ticks(efx, usecs);
2005
2006                 EFX_POPULATE_DWORD_2(timer_cmd, ERF_DZ_TC_TIMER_MODE, mode,
2007                                      ERF_DZ_TC_TIMER_VAL, ticks);
2008                 efx_writed_page(efx, &timer_cmd, ER_DZ_EVQ_TMR,
2009                                 channel->channel);
2010         }
2011 }
2012
2013 static void efx_ef10_get_wol_vf(struct efx_nic *efx,
2014                                 struct ethtool_wolinfo *wol) {}
2015
2016 static int efx_ef10_set_wol_vf(struct efx_nic *efx, u32 type)
2017 {
2018         return -EOPNOTSUPP;
2019 }
2020
2021 static void efx_ef10_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
2022 {
2023         wol->supported = 0;
2024         wol->wolopts = 0;
2025         memset(&wol->sopass, 0, sizeof(wol->sopass));
2026 }
2027
2028 static int efx_ef10_set_wol(struct efx_nic *efx, u32 type)
2029 {
2030         if (type != 0)
2031                 return -EINVAL;
2032         return 0;
2033 }
2034
2035 static void efx_ef10_mcdi_request(struct efx_nic *efx,
2036                                   const efx_dword_t *hdr, size_t hdr_len,
2037                                   const efx_dword_t *sdu, size_t sdu_len)
2038 {
2039         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2040         u8 *pdu = nic_data->mcdi_buf.addr;
2041
2042         memcpy(pdu, hdr, hdr_len);
2043         memcpy(pdu + hdr_len, sdu, sdu_len);
2044         wmb();
2045
2046         /* The hardware provides 'low' and 'high' (doorbell) registers
2047          * for passing the 64-bit address of an MCDI request to
2048          * firmware.  However the dwords are swapped by firmware.  The
2049          * least significant bits of the doorbell are then 0 for all
2050          * MCDI requests due to alignment.
2051          */
2052         _efx_writed(efx, cpu_to_le32((u64)nic_data->mcdi_buf.dma_addr >> 32),
2053                     ER_DZ_MC_DB_LWRD);
2054         _efx_writed(efx, cpu_to_le32((u32)nic_data->mcdi_buf.dma_addr),
2055                     ER_DZ_MC_DB_HWRD);
2056 }
2057
2058 static bool efx_ef10_mcdi_poll_response(struct efx_nic *efx)
2059 {
2060         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2061         const efx_dword_t hdr = *(const efx_dword_t *)nic_data->mcdi_buf.addr;
2062
2063         rmb();
2064         return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE);
2065 }
2066
2067 static void
2068 efx_ef10_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf,
2069                             size_t offset, size_t outlen)
2070 {
2071         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2072         const u8 *pdu = nic_data->mcdi_buf.addr;
2073
2074         memcpy(outbuf, pdu + offset, outlen);
2075 }
2076
2077 static void efx_ef10_mcdi_reboot_detected(struct efx_nic *efx)
2078 {
2079         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2080
2081         /* All our allocations have been reset */
2082         efx_ef10_reset_mc_allocations(efx);
2083
2084         /* The datapath firmware might have been changed */
2085         nic_data->must_check_datapath_caps = true;
2086
2087         /* MAC statistics have been cleared on the NIC; clear the local
2088          * statistic that we update with efx_update_diff_stat().
2089          */
2090         nic_data->stats[EF10_STAT_port_rx_bad_bytes] = 0;
2091 }
2092
2093 static int efx_ef10_mcdi_poll_reboot(struct efx_nic *efx)
2094 {
2095         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2096         int rc;
2097
2098         rc = efx_ef10_get_warm_boot_count(efx);
2099         if (rc < 0) {
2100                 /* The firmware is presumably in the process of
2101                  * rebooting.  However, we are supposed to report each
2102                  * reboot just once, so we must only do that once we
2103                  * can read and store the updated warm boot count.
2104                  */
2105                 return 0;
2106         }
2107
2108         if (rc == nic_data->warm_boot_count)
2109                 return 0;
2110
2111         nic_data->warm_boot_count = rc;
2112         efx_ef10_mcdi_reboot_detected(efx);
2113
2114         return -EIO;
2115 }
2116
2117 /* Handle an MSI interrupt
2118  *
2119  * Handle an MSI hardware interrupt.  This routine schedules event
2120  * queue processing.  No interrupt acknowledgement cycle is necessary.
2121  * Also, we never need to check that the interrupt is for us, since
2122  * MSI interrupts cannot be shared.
2123  */
2124 static irqreturn_t efx_ef10_msi_interrupt(int irq, void *dev_id)
2125 {
2126         struct efx_msi_context *context = dev_id;
2127         struct efx_nic *efx = context->efx;
2128
2129         netif_vdbg(efx, intr, efx->net_dev,
2130                    "IRQ %d on CPU %d\n", irq, raw_smp_processor_id());
2131
2132         if (likely(READ_ONCE(efx->irq_soft_enabled))) {
2133                 /* Note test interrupts */
2134                 if (context->index == efx->irq_level)
2135                         efx->last_irq_cpu = raw_smp_processor_id();
2136
2137                 /* Schedule processing of the channel */
2138                 efx_schedule_channel_irq(efx->channel[context->index]);
2139         }
2140
2141         return IRQ_HANDLED;
2142 }
2143
2144 static irqreturn_t efx_ef10_legacy_interrupt(int irq, void *dev_id)
2145 {
2146         struct efx_nic *efx = dev_id;
2147         bool soft_enabled = READ_ONCE(efx->irq_soft_enabled);
2148         struct efx_channel *channel;
2149         efx_dword_t reg;
2150         u32 queues;
2151
2152         /* Read the ISR which also ACKs the interrupts */
2153         efx_readd(efx, &reg, ER_DZ_BIU_INT_ISR);
2154         queues = EFX_DWORD_FIELD(reg, ERF_DZ_ISR_REG);
2155
2156         if (queues == 0)
2157                 return IRQ_NONE;
2158
2159         if (likely(soft_enabled)) {
2160                 /* Note test interrupts */
2161                 if (queues & (1U << efx->irq_level))
2162                         efx->last_irq_cpu = raw_smp_processor_id();
2163
2164                 efx_for_each_channel(channel, efx) {
2165                         if (queues & 1)
2166                                 efx_schedule_channel_irq(channel);
2167                         queues >>= 1;
2168                 }
2169         }
2170
2171         netif_vdbg(efx, intr, efx->net_dev,
2172                    "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
2173                    irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
2174
2175         return IRQ_HANDLED;
2176 }
2177
2178 static int efx_ef10_irq_test_generate(struct efx_nic *efx)
2179 {
2180         MCDI_DECLARE_BUF(inbuf, MC_CMD_TRIGGER_INTERRUPT_IN_LEN);
2181
2182         if (efx_mcdi_set_workaround(efx, MC_CMD_WORKAROUND_BUG41750, true,
2183                                     NULL) == 0)
2184                 return -ENOTSUPP;
2185
2186         BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN != 0);
2187
2188         MCDI_SET_DWORD(inbuf, TRIGGER_INTERRUPT_IN_INTR_LEVEL, efx->irq_level);
2189         return efx_mcdi_rpc(efx, MC_CMD_TRIGGER_INTERRUPT,
2190                             inbuf, sizeof(inbuf), NULL, 0, NULL);
2191 }
2192
2193 static int efx_ef10_tx_probe(struct efx_tx_queue *tx_queue)
2194 {
2195         return efx_nic_alloc_buffer(tx_queue->efx, &tx_queue->txd.buf,
2196                                     (tx_queue->ptr_mask + 1) *
2197                                     sizeof(efx_qword_t),
2198                                     GFP_KERNEL);
2199 }
2200
2201 /* This writes to the TX_DESC_WPTR and also pushes data */
2202 static inline void efx_ef10_push_tx_desc(struct efx_tx_queue *tx_queue,
2203                                          const efx_qword_t *txd)
2204 {
2205         unsigned int write_ptr;
2206         efx_oword_t reg;
2207
2208         write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
2209         EFX_POPULATE_OWORD_1(reg, ERF_DZ_TX_DESC_WPTR, write_ptr);
2210         reg.qword[0] = *txd;
2211         efx_writeo_page(tx_queue->efx, &reg,
2212                         ER_DZ_TX_DESC_UPD, tx_queue->queue);
2213 }
2214
2215 /* Add Firmware-Assisted TSO v2 option descriptors to a queue.
2216  */
2217 static int efx_ef10_tx_tso_desc(struct efx_tx_queue *tx_queue,
2218                                 struct sk_buff *skb,
2219                                 bool *data_mapped)
2220 {
2221         struct efx_tx_buffer *buffer;
2222         struct tcphdr *tcp;
2223         struct iphdr *ip;
2224
2225         u16 ipv4_id;
2226         u32 seqnum;
2227         u32 mss;
2228
2229         EFX_WARN_ON_ONCE_PARANOID(tx_queue->tso_version != 2);
2230
2231         mss = skb_shinfo(skb)->gso_size;
2232
2233         if (unlikely(mss < 4)) {
2234                 WARN_ONCE(1, "MSS of %u is too small for TSO v2\n", mss);
2235                 return -EINVAL;
2236         }
2237
2238         ip = ip_hdr(skb);
2239         if (ip->version == 4) {
2240                 /* Modify IPv4 header if needed. */
2241                 ip->tot_len = 0;
2242                 ip->check = 0;
2243                 ipv4_id = ntohs(ip->id);
2244         } else {
2245                 /* Modify IPv6 header if needed. */
2246                 struct ipv6hdr *ipv6 = ipv6_hdr(skb);
2247
2248                 ipv6->payload_len = 0;
2249                 ipv4_id = 0;
2250         }
2251
2252         tcp = tcp_hdr(skb);
2253         seqnum = ntohl(tcp->seq);
2254
2255         buffer = efx_tx_queue_get_insert_buffer(tx_queue);
2256
2257         buffer->flags = EFX_TX_BUF_OPTION;
2258         buffer->len = 0;
2259         buffer->unmap_len = 0;
2260         EFX_POPULATE_QWORD_5(buffer->option,
2261                         ESF_DZ_TX_DESC_IS_OPT, 1,
2262                         ESF_DZ_TX_OPTION_TYPE, ESE_DZ_TX_OPTION_DESC_TSO,
2263                         ESF_DZ_TX_TSO_OPTION_TYPE,
2264                         ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A,
2265                         ESF_DZ_TX_TSO_IP_ID, ipv4_id,
2266                         ESF_DZ_TX_TSO_TCP_SEQNO, seqnum
2267                         );
2268         ++tx_queue->insert_count;
2269
2270         buffer = efx_tx_queue_get_insert_buffer(tx_queue);
2271
2272         buffer->flags = EFX_TX_BUF_OPTION;
2273         buffer->len = 0;
2274         buffer->unmap_len = 0;
2275         EFX_POPULATE_QWORD_4(buffer->option,
2276                         ESF_DZ_TX_DESC_IS_OPT, 1,
2277                         ESF_DZ_TX_OPTION_TYPE, ESE_DZ_TX_OPTION_DESC_TSO,
2278                         ESF_DZ_TX_TSO_OPTION_TYPE,
2279                         ESE_DZ_TX_TSO_OPTION_DESC_FATSO2B,
2280                         ESF_DZ_TX_TSO_TCP_MSS, mss
2281                         );
2282         ++tx_queue->insert_count;
2283
2284         return 0;
2285 }
2286
2287 static u32 efx_ef10_tso_versions(struct efx_nic *efx)
2288 {
2289         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2290         u32 tso_versions = 0;
2291
2292         if (nic_data->datapath_caps &
2293             (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN))
2294                 tso_versions |= BIT(1);
2295         if (nic_data->datapath_caps2 &
2296             (1 << MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_LBN))
2297                 tso_versions |= BIT(2);
2298         return tso_versions;
2299 }
2300
2301 static void efx_ef10_tx_init(struct efx_tx_queue *tx_queue)
2302 {
2303         MCDI_DECLARE_BUF(inbuf, MC_CMD_INIT_TXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
2304                                                        EFX_BUF_SIZE));
2305         bool csum_offload = tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD;
2306         size_t entries = tx_queue->txd.buf.len / EFX_BUF_SIZE;
2307         struct efx_channel *channel = tx_queue->channel;
2308         struct efx_nic *efx = tx_queue->efx;
2309         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2310         bool tso_v2 = false;
2311         size_t inlen;
2312         dma_addr_t dma_addr;
2313         efx_qword_t *txd;
2314         int rc;
2315         int i;
2316         BUILD_BUG_ON(MC_CMD_INIT_TXQ_OUT_LEN != 0);
2317
2318         /* TSOv2 is a limited resource that can only be configured on a limited
2319          * number of queues. TSO without checksum offload is not really a thing,
2320          * so we only enable it for those queues.
2321          */
2322         if (csum_offload && (nic_data->datapath_caps2 &
2323                         (1 << MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_LBN))) {
2324                 tso_v2 = true;
2325                 netif_dbg(efx, hw, efx->net_dev, "Using TSOv2 for channel %u\n",
2326                                 channel->channel);
2327         }
2328
2329         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_SIZE, tx_queue->ptr_mask + 1);
2330         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_TARGET_EVQ, channel->channel);
2331         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_LABEL, tx_queue->queue);
2332         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_INSTANCE, tx_queue->queue);
2333         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_OWNER_ID, 0);
2334         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_PORT_ID, nic_data->vport_id);
2335
2336         dma_addr = tx_queue->txd.buf.dma_addr;
2337
2338         netif_dbg(efx, hw, efx->net_dev, "pushing TXQ %d. %zu entries (%llx)\n",
2339                   tx_queue->queue, entries, (u64)dma_addr);
2340
2341         for (i = 0; i < entries; ++i) {
2342                 MCDI_SET_ARRAY_QWORD(inbuf, INIT_TXQ_IN_DMA_ADDR, i, dma_addr);
2343                 dma_addr += EFX_BUF_SIZE;
2344         }
2345
2346         inlen = MC_CMD_INIT_TXQ_IN_LEN(entries);
2347
2348         do {
2349                 MCDI_POPULATE_DWORD_3(inbuf, INIT_TXQ_IN_FLAGS,
2350                                 /* This flag was removed from mcdi_pcol.h for
2351                                  * the non-_EXT version of INIT_TXQ.  However,
2352                                  * firmware still honours it.
2353                                  */
2354                                 INIT_TXQ_EXT_IN_FLAG_TSOV2_EN, tso_v2,
2355                                 INIT_TXQ_IN_FLAG_IP_CSUM_DIS, !csum_offload,
2356                                 INIT_TXQ_IN_FLAG_TCP_CSUM_DIS, !csum_offload);
2357
2358                 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_INIT_TXQ, inbuf, inlen,
2359                                         NULL, 0, NULL);
2360                 if (rc == -ENOSPC && tso_v2) {
2361                         /* Retry without TSOv2 if we're short on contexts. */
2362                         tso_v2 = false;
2363                         netif_warn(efx, probe, efx->net_dev,
2364                                    "TSOv2 context not available to segment in hardware. TCP performance may be reduced.\n");
2365                 } else if (rc) {
2366                         efx_mcdi_display_error(efx, MC_CMD_INIT_TXQ,
2367                                                MC_CMD_INIT_TXQ_EXT_IN_LEN,
2368                                                NULL, 0, rc);
2369                         goto fail;
2370                 }
2371         } while (rc);
2372
2373         /* A previous user of this TX queue might have set us up the
2374          * bomb by writing a descriptor to the TX push collector but
2375          * not the doorbell.  (Each collector belongs to a port, not a
2376          * queue or function, so cannot easily be reset.)  We must
2377          * attempt to push a no-op descriptor in its place.
2378          */
2379         tx_queue->buffer[0].flags = EFX_TX_BUF_OPTION;
2380         tx_queue->insert_count = 1;
2381         txd = efx_tx_desc(tx_queue, 0);
2382         EFX_POPULATE_QWORD_4(*txd,
2383                              ESF_DZ_TX_DESC_IS_OPT, true,
2384                              ESF_DZ_TX_OPTION_TYPE,
2385                              ESE_DZ_TX_OPTION_DESC_CRC_CSUM,
2386                              ESF_DZ_TX_OPTION_UDP_TCP_CSUM, csum_offload,
2387                              ESF_DZ_TX_OPTION_IP_CSUM, csum_offload);
2388         tx_queue->write_count = 1;
2389
2390         if (tso_v2) {
2391                 tx_queue->handle_tso = efx_ef10_tx_tso_desc;
2392                 tx_queue->tso_version = 2;
2393         } else if (nic_data->datapath_caps &
2394                         (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN)) {
2395                 tx_queue->tso_version = 1;
2396         }
2397
2398         wmb();
2399         efx_ef10_push_tx_desc(tx_queue, txd);
2400
2401         return;
2402
2403 fail:
2404         netdev_WARN(efx->net_dev, "failed to initialise TXQ %d\n",
2405                     tx_queue->queue);
2406 }
2407
2408 static void efx_ef10_tx_fini(struct efx_tx_queue *tx_queue)
2409 {
2410         MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_TXQ_IN_LEN);
2411         MCDI_DECLARE_BUF_ERR(outbuf);
2412         struct efx_nic *efx = tx_queue->efx;
2413         size_t outlen;
2414         int rc;
2415
2416         MCDI_SET_DWORD(inbuf, FINI_TXQ_IN_INSTANCE,
2417                        tx_queue->queue);
2418
2419         rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_TXQ, inbuf, sizeof(inbuf),
2420                           outbuf, sizeof(outbuf), &outlen);
2421
2422         if (rc && rc != -EALREADY)
2423                 goto fail;
2424
2425         return;
2426
2427 fail:
2428         efx_mcdi_display_error(efx, MC_CMD_FINI_TXQ, MC_CMD_FINI_TXQ_IN_LEN,
2429                                outbuf, outlen, rc);
2430 }
2431
2432 static void efx_ef10_tx_remove(struct efx_tx_queue *tx_queue)
2433 {
2434         efx_nic_free_buffer(tx_queue->efx, &tx_queue->txd.buf);
2435 }
2436
2437 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
2438 static inline void efx_ef10_notify_tx_desc(struct efx_tx_queue *tx_queue)
2439 {
2440         unsigned int write_ptr;
2441         efx_dword_t reg;
2442
2443         write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
2444         EFX_POPULATE_DWORD_1(reg, ERF_DZ_TX_DESC_WPTR_DWORD, write_ptr);
2445         efx_writed_page(tx_queue->efx, &reg,
2446                         ER_DZ_TX_DESC_UPD_DWORD, tx_queue->queue);
2447 }
2448
2449 #define EFX_EF10_MAX_TX_DESCRIPTOR_LEN 0x3fff
2450
2451 static unsigned int efx_ef10_tx_limit_len(struct efx_tx_queue *tx_queue,
2452                                           dma_addr_t dma_addr, unsigned int len)
2453 {
2454         if (len > EFX_EF10_MAX_TX_DESCRIPTOR_LEN) {
2455                 /* If we need to break across multiple descriptors we should
2456                  * stop at a page boundary. This assumes the length limit is
2457                  * greater than the page size.
2458                  */
2459                 dma_addr_t end = dma_addr + EFX_EF10_MAX_TX_DESCRIPTOR_LEN;
2460
2461                 BUILD_BUG_ON(EFX_EF10_MAX_TX_DESCRIPTOR_LEN < EFX_PAGE_SIZE);
2462                 len = (end & (~(EFX_PAGE_SIZE - 1))) - dma_addr;
2463         }
2464
2465         return len;
2466 }
2467
2468 static void efx_ef10_tx_write(struct efx_tx_queue *tx_queue)
2469 {
2470         unsigned int old_write_count = tx_queue->write_count;
2471         struct efx_tx_buffer *buffer;
2472         unsigned int write_ptr;
2473         efx_qword_t *txd;
2474
2475         tx_queue->xmit_more_available = false;
2476         if (unlikely(tx_queue->write_count == tx_queue->insert_count))
2477                 return;
2478
2479         do {
2480                 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
2481                 buffer = &tx_queue->buffer[write_ptr];
2482                 txd = efx_tx_desc(tx_queue, write_ptr);
2483                 ++tx_queue->write_count;
2484
2485                 /* Create TX descriptor ring entry */
2486                 if (buffer->flags & EFX_TX_BUF_OPTION) {
2487                         *txd = buffer->option;
2488                         if (EFX_QWORD_FIELD(*txd, ESF_DZ_TX_OPTION_TYPE) == 1)
2489                                 /* PIO descriptor */
2490                                 tx_queue->packet_write_count = tx_queue->write_count;
2491                 } else {
2492                         tx_queue->packet_write_count = tx_queue->write_count;
2493                         BUILD_BUG_ON(EFX_TX_BUF_CONT != 1);
2494                         EFX_POPULATE_QWORD_3(
2495                                 *txd,
2496                                 ESF_DZ_TX_KER_CONT,
2497                                 buffer->flags & EFX_TX_BUF_CONT,
2498                                 ESF_DZ_TX_KER_BYTE_CNT, buffer->len,
2499                                 ESF_DZ_TX_KER_BUF_ADDR, buffer->dma_addr);
2500                 }
2501         } while (tx_queue->write_count != tx_queue->insert_count);
2502
2503         wmb(); /* Ensure descriptors are written before they are fetched */
2504
2505         if (efx_nic_may_push_tx_desc(tx_queue, old_write_count)) {
2506                 txd = efx_tx_desc(tx_queue,
2507                                   old_write_count & tx_queue->ptr_mask);
2508                 efx_ef10_push_tx_desc(tx_queue, txd);
2509                 ++tx_queue->pushes;
2510         } else {
2511                 efx_ef10_notify_tx_desc(tx_queue);
2512         }
2513 }
2514
2515 #define RSS_MODE_HASH_ADDRS     (1 << RSS_MODE_HASH_SRC_ADDR_LBN |\
2516                                  1 << RSS_MODE_HASH_DST_ADDR_LBN)
2517 #define RSS_MODE_HASH_PORTS     (1 << RSS_MODE_HASH_SRC_PORT_LBN |\
2518                                  1 << RSS_MODE_HASH_DST_PORT_LBN)
2519 #define RSS_CONTEXT_FLAGS_DEFAULT       (1 << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_LBN |\
2520                                          1 << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_LBN |\
2521                                          1 << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_LBN |\
2522                                          1 << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_LBN |\
2523                                          (RSS_MODE_HASH_ADDRS | RSS_MODE_HASH_PORTS) << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_LBN |\
2524                                          RSS_MODE_HASH_ADDRS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_LBN |\
2525                                          RSS_MODE_HASH_ADDRS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_LBN |\
2526                                          (RSS_MODE_HASH_ADDRS | RSS_MODE_HASH_PORTS) << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_LBN |\
2527                                          RSS_MODE_HASH_ADDRS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_LBN |\
2528                                          RSS_MODE_HASH_ADDRS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_LBN)
2529
2530 static int efx_ef10_get_rss_flags(struct efx_nic *efx, u32 context, u32 *flags)
2531 {
2532         /* Firmware had a bug (sfc bug 61952) where it would not actually
2533          * fill in the flags field in the response to MC_CMD_RSS_CONTEXT_GET_FLAGS.
2534          * This meant that it would always contain whatever was previously
2535          * in the MCDI buffer.  Fortunately, all firmware versions with
2536          * this bug have the same default flags value for a newly-allocated
2537          * RSS context, and the only time we want to get the flags is just
2538          * after allocating.  Moreover, the response has a 32-bit hole
2539          * where the context ID would be in the request, so we can use an
2540          * overlength buffer in the request and pre-fill the flags field
2541          * with what we believe the default to be.  Thus if the firmware
2542          * has the bug, it will leave our pre-filled value in the flags
2543          * field of the response, and we will get the right answer.
2544          *
2545          * However, this does mean that this function should NOT be used if
2546          * the RSS context flags might not be their defaults - it is ONLY
2547          * reliably correct for a newly-allocated RSS context.
2548          */
2549         MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN);
2550         MCDI_DECLARE_BUF(outbuf, MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN);
2551         size_t outlen;
2552         int rc;
2553
2554         /* Check we have a hole for the context ID */
2555         BUILD_BUG_ON(MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_LEN != MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_FLAGS_OFST);
2556         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_GET_FLAGS_IN_RSS_CONTEXT_ID, context);
2557         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_GET_FLAGS_OUT_FLAGS,
2558                        RSS_CONTEXT_FLAGS_DEFAULT);
2559         rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_GET_FLAGS, inbuf,
2560                           sizeof(inbuf), outbuf, sizeof(outbuf), &outlen);
2561         if (rc == 0) {
2562                 if (outlen < MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN)
2563                         rc = -EIO;
2564                 else
2565                         *flags = MCDI_DWORD(outbuf, RSS_CONTEXT_GET_FLAGS_OUT_FLAGS);
2566         }
2567         return rc;
2568 }
2569
2570 /* Attempt to enable 4-tuple UDP hashing on the specified RSS context.
2571  * If we fail, we just leave the RSS context at its default hash settings,
2572  * which is safe but may slightly reduce performance.
2573  * Defaults are 4-tuple for TCP and 2-tuple for UDP and other-IP, so we
2574  * just need to set the UDP ports flags (for both IP versions).
2575  */
2576 static void efx_ef10_set_rss_flags(struct efx_nic *efx, u32 context)
2577 {
2578         MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_LEN);
2579         u32 flags;
2580
2581         BUILD_BUG_ON(MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT_LEN != 0);
2582
2583         if (efx_ef10_get_rss_flags(efx, context, &flags) != 0)
2584                 return;
2585         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID, context);
2586         flags |= RSS_MODE_HASH_PORTS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_LBN;
2587         flags |= RSS_MODE_HASH_PORTS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_LBN;
2588         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_SET_FLAGS_IN_FLAGS, flags);
2589         if (!efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_FLAGS, inbuf, sizeof(inbuf),
2590                           NULL, 0, NULL))
2591                 /* Succeeded, so UDP 4-tuple is now enabled */
2592                 efx->rx_hash_udp_4tuple = true;
2593 }
2594
2595 static int efx_ef10_alloc_rss_context(struct efx_nic *efx, u32 *context,
2596                                       bool exclusive, unsigned *context_size)
2597 {
2598         MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN);
2599         MCDI_DECLARE_BUF(outbuf, MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN);
2600         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2601         size_t outlen;
2602         int rc;
2603         u32 alloc_type = exclusive ?
2604                                 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE :
2605                                 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED;
2606         unsigned rss_spread = exclusive ?
2607                                 efx->rss_spread :
2608                                 min(rounddown_pow_of_two(efx->rss_spread),
2609                                     EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE);
2610
2611         if (!exclusive && rss_spread == 1) {
2612                 *context = EFX_EF10_RSS_CONTEXT_INVALID;
2613                 if (context_size)
2614                         *context_size = 1;
2615                 return 0;
2616         }
2617
2618         if (nic_data->datapath_caps &
2619             1 << MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_LBN)
2620                 return -EOPNOTSUPP;
2621
2622         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID,
2623                        nic_data->vport_id);
2624         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_TYPE, alloc_type);
2625         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_NUM_QUEUES, rss_spread);
2626
2627         rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_ALLOC, inbuf, sizeof(inbuf),
2628                 outbuf, sizeof(outbuf), &outlen);
2629         if (rc != 0)
2630                 return rc;
2631
2632         if (outlen < MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN)
2633                 return -EIO;
2634
2635         *context = MCDI_DWORD(outbuf, RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID);
2636
2637         if (context_size)
2638                 *context_size = rss_spread;
2639
2640         if (nic_data->datapath_caps &
2641             1 << MC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_LBN)
2642                 efx_ef10_set_rss_flags(efx, *context);
2643
2644         return 0;
2645 }
2646
2647 static void efx_ef10_free_rss_context(struct efx_nic *efx, u32 context)
2648 {
2649         MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_FREE_IN_LEN);
2650         int rc;
2651
2652         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID,
2653                        context);
2654
2655         rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_FREE, inbuf, sizeof(inbuf),
2656                             NULL, 0, NULL);
2657         WARN_ON(rc != 0);
2658 }
2659
2660 static int efx_ef10_populate_rss_table(struct efx_nic *efx, u32 context,
2661                                        const u32 *rx_indir_table, const u8 *key)
2662 {
2663         MCDI_DECLARE_BUF(tablebuf, MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN);
2664         MCDI_DECLARE_BUF(keybuf, MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN);
2665         int i, rc;
2666
2667         MCDI_SET_DWORD(tablebuf, RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID,
2668                        context);
2669         BUILD_BUG_ON(ARRAY_SIZE(efx->rx_indir_table) !=
2670                      MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN);
2671
2672         /* This iterates over the length of efx->rx_indir_table, but copies
2673          * bytes from rx_indir_table.  That's because the latter is a pointer
2674          * rather than an array, but should have the same length.
2675          * The efx->rx_hash_key loop below is similar.
2676          */
2677         for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); ++i)
2678                 MCDI_PTR(tablebuf,
2679                          RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE)[i] =
2680                                 (u8) rx_indir_table[i];
2681
2682         rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_TABLE, tablebuf,
2683                           sizeof(tablebuf), NULL, 0, NULL);
2684         if (rc != 0)
2685                 return rc;
2686
2687         MCDI_SET_DWORD(keybuf, RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID,
2688                        context);
2689         BUILD_BUG_ON(ARRAY_SIZE(efx->rx_hash_key) !=
2690                      MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN);
2691         for (i = 0; i < ARRAY_SIZE(efx->rx_hash_key); ++i)
2692                 MCDI_PTR(keybuf, RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY)[i] = key[i];
2693
2694         return efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_KEY, keybuf,
2695                             sizeof(keybuf), NULL, 0, NULL);
2696 }
2697
2698 static void efx_ef10_rx_free_indir_table(struct efx_nic *efx)
2699 {
2700         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2701
2702         if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID)
2703                 efx_ef10_free_rss_context(efx, nic_data->rx_rss_context);
2704         nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
2705 }
2706
2707 static int efx_ef10_rx_push_shared_rss_config(struct efx_nic *efx,
2708                                               unsigned *context_size)
2709 {
2710         u32 new_rx_rss_context;
2711         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2712         int rc = efx_ef10_alloc_rss_context(efx, &new_rx_rss_context,
2713                                             false, context_size);
2714
2715         if (rc != 0)
2716                 return rc;
2717
2718         nic_data->rx_rss_context = new_rx_rss_context;
2719         nic_data->rx_rss_context_exclusive = false;
2720         efx_set_default_rx_indir_table(efx);
2721         return 0;
2722 }
2723
2724 static int efx_ef10_rx_push_exclusive_rss_config(struct efx_nic *efx,
2725                                                  const u32 *rx_indir_table,
2726                                                  const u8 *key)
2727 {
2728         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2729         int rc;
2730         u32 new_rx_rss_context;
2731
2732         if (nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID ||
2733             !nic_data->rx_rss_context_exclusive) {
2734                 rc = efx_ef10_alloc_rss_context(efx, &new_rx_rss_context,
2735                                                 true, NULL);
2736                 if (rc == -EOPNOTSUPP)
2737                         return rc;
2738                 else if (rc != 0)
2739                         goto fail1;
2740         } else {
2741                 new_rx_rss_context = nic_data->rx_rss_context;
2742         }
2743
2744         rc = efx_ef10_populate_rss_table(efx, new_rx_rss_context,
2745                                          rx_indir_table, key);
2746         if (rc != 0)
2747                 goto fail2;
2748
2749         if (nic_data->rx_rss_context != new_rx_rss_context)
2750                 efx_ef10_rx_free_indir_table(efx);
2751         nic_data->rx_rss_context = new_rx_rss_context;
2752         nic_data->rx_rss_context_exclusive = true;
2753         if (rx_indir_table != efx->rx_indir_table)
2754                 memcpy(efx->rx_indir_table, rx_indir_table,
2755                        sizeof(efx->rx_indir_table));
2756         if (key != efx->rx_hash_key)
2757                 memcpy(efx->rx_hash_key, key, efx->type->rx_hash_key_size);
2758
2759         return 0;
2760
2761 fail2:
2762         if (new_rx_rss_context != nic_data->rx_rss_context)
2763                 efx_ef10_free_rss_context(efx, new_rx_rss_context);
2764 fail1:
2765         netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
2766         return rc;
2767 }
2768
2769 static int efx_ef10_rx_pull_rss_config(struct efx_nic *efx)
2770 {
2771         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2772         MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_GET_TABLE_IN_LEN);
2773         MCDI_DECLARE_BUF(tablebuf, MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_LEN);
2774         MCDI_DECLARE_BUF(keybuf, MC_CMD_RSS_CONTEXT_GET_KEY_OUT_LEN);
2775         size_t outlen;
2776         int rc, i;
2777
2778         BUILD_BUG_ON(MC_CMD_RSS_CONTEXT_GET_TABLE_IN_LEN !=
2779                      MC_CMD_RSS_CONTEXT_GET_KEY_IN_LEN);
2780
2781         if (nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID)
2782                 return -ENOENT;
2783
2784         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_GET_TABLE_IN_RSS_CONTEXT_ID,
2785                        nic_data->rx_rss_context);
2786         BUILD_BUG_ON(ARRAY_SIZE(efx->rx_indir_table) !=
2787                      MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_LEN);
2788         rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_GET_TABLE, inbuf, sizeof(inbuf),
2789                           tablebuf, sizeof(tablebuf), &outlen);
2790         if (rc != 0)
2791                 return rc;
2792
2793         if (WARN_ON(outlen != MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_LEN))
2794                 return -EIO;
2795
2796         for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); i++)
2797                 efx->rx_indir_table[i] = MCDI_PTR(tablebuf,
2798                                 RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE)[i];
2799
2800         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_GET_KEY_IN_RSS_CONTEXT_ID,
2801                        nic_data->rx_rss_context);
2802         BUILD_BUG_ON(ARRAY_SIZE(efx->rx_hash_key) !=
2803                      MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN);
2804         rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_GET_KEY, inbuf, sizeof(inbuf),
2805                           keybuf, sizeof(keybuf), &outlen);
2806         if (rc != 0)
2807                 return rc;
2808
2809         if (WARN_ON(outlen != MC_CMD_RSS_CONTEXT_GET_KEY_OUT_LEN))
2810                 return -EIO;
2811
2812         for (i = 0; i < ARRAY_SIZE(efx->rx_hash_key); ++i)
2813                 efx->rx_hash_key[i] = MCDI_PTR(
2814                                 keybuf, RSS_CONTEXT_GET_KEY_OUT_TOEPLITZ_KEY)[i];
2815
2816         return 0;
2817 }
2818
2819 static int efx_ef10_pf_rx_push_rss_config(struct efx_nic *efx, bool user,
2820                                           const u32 *rx_indir_table,
2821                                           const u8 *key)
2822 {
2823         int rc;
2824
2825         if (efx->rss_spread == 1)
2826                 return 0;
2827
2828         if (!key)
2829                 key = efx->rx_hash_key;
2830
2831         rc = efx_ef10_rx_push_exclusive_rss_config(efx, rx_indir_table, key);
2832
2833         if (rc == -ENOBUFS && !user) {
2834                 unsigned context_size;
2835                 bool mismatch = false;
2836                 size_t i;
2837
2838                 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table) && !mismatch;
2839                      i++)
2840                         mismatch = rx_indir_table[i] !=
2841                                 ethtool_rxfh_indir_default(i, efx->rss_spread);
2842
2843                 rc = efx_ef10_rx_push_shared_rss_config(efx, &context_size);
2844                 if (rc == 0) {
2845                         if (context_size != efx->rss_spread)
2846                                 netif_warn(efx, probe, efx->net_dev,
2847                                            "Could not allocate an exclusive RSS"
2848                                            " context; allocated a shared one of"
2849                                            " different size."
2850                                            " Wanted %u, got %u.\n",
2851                                            efx->rss_spread, context_size);
2852                         else if (mismatch)
2853                                 netif_warn(efx, probe, efx->net_dev,
2854                                            "Could not allocate an exclusive RSS"
2855                                            " context; allocated a shared one but"
2856                                            " could not apply custom"
2857                                            " indirection.\n");
2858                         else
2859                                 netif_info(efx, probe, efx->net_dev,
2860                                            "Could not allocate an exclusive RSS"
2861                                            " context; allocated a shared one.\n");
2862                 }
2863         }
2864         return rc;
2865 }
2866
2867 static int efx_ef10_vf_rx_push_rss_config(struct efx_nic *efx, bool user,
2868                                           const u32 *rx_indir_table
2869                                           __attribute__ ((unused)),
2870                                           const u8 *key
2871                                           __attribute__ ((unused)))
2872 {
2873         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2874
2875         if (user)
2876                 return -EOPNOTSUPP;
2877         if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID)
2878                 return 0;
2879         return efx_ef10_rx_push_shared_rss_config(efx, NULL);
2880 }
2881
2882 static int efx_ef10_rx_probe(struct efx_rx_queue *rx_queue)
2883 {
2884         return efx_nic_alloc_buffer(rx_queue->efx, &rx_queue->rxd.buf,
2885                                     (rx_queue->ptr_mask + 1) *
2886                                     sizeof(efx_qword_t),
2887                                     GFP_KERNEL);
2888 }
2889
2890 static void efx_ef10_rx_init(struct efx_rx_queue *rx_queue)
2891 {
2892         MCDI_DECLARE_BUF(inbuf,
2893                          MC_CMD_INIT_RXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
2894                                                 EFX_BUF_SIZE));
2895         struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
2896         size_t entries = rx_queue->rxd.buf.len / EFX_BUF_SIZE;
2897         struct efx_nic *efx = rx_queue->efx;
2898         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2899         size_t inlen;
2900         dma_addr_t dma_addr;
2901         int rc;
2902         int i;
2903         BUILD_BUG_ON(MC_CMD_INIT_RXQ_OUT_LEN != 0);
2904
2905         rx_queue->scatter_n = 0;
2906         rx_queue->scatter_len = 0;
2907
2908         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_SIZE, rx_queue->ptr_mask + 1);
2909         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_TARGET_EVQ, channel->channel);
2910         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_LABEL, efx_rx_queue_index(rx_queue));
2911         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_INSTANCE,
2912                        efx_rx_queue_index(rx_queue));
2913         MCDI_POPULATE_DWORD_2(inbuf, INIT_RXQ_IN_FLAGS,
2914                               INIT_RXQ_IN_FLAG_PREFIX, 1,
2915                               INIT_RXQ_IN_FLAG_TIMESTAMP, 1);
2916         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_OWNER_ID, 0);
2917         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_PORT_ID, nic_data->vport_id);
2918
2919         dma_addr = rx_queue->rxd.buf.dma_addr;
2920
2921         netif_dbg(efx, hw, efx->net_dev, "pushing RXQ %d. %zu entries (%llx)\n",
2922                   efx_rx_queue_index(rx_queue), entries, (u64)dma_addr);
2923
2924         for (i = 0; i < entries; ++i) {
2925                 MCDI_SET_ARRAY_QWORD(inbuf, INIT_RXQ_IN_DMA_ADDR, i, dma_addr);
2926                 dma_addr += EFX_BUF_SIZE;
2927         }
2928
2929         inlen = MC_CMD_INIT_RXQ_IN_LEN(entries);
2930
2931         rc = efx_mcdi_rpc(efx, MC_CMD_INIT_RXQ, inbuf, inlen,
2932                           NULL, 0, NULL);
2933         if (rc)
2934                 netdev_WARN(efx->net_dev, "failed to initialise RXQ %d\n",
2935                             efx_rx_queue_index(rx_queue));
2936 }
2937
2938 static void efx_ef10_rx_fini(struct efx_rx_queue *rx_queue)
2939 {
2940         MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_RXQ_IN_LEN);
2941         MCDI_DECLARE_BUF_ERR(outbuf);
2942         struct efx_nic *efx = rx_queue->efx;
2943         size_t outlen;
2944         int rc;
2945
2946         MCDI_SET_DWORD(inbuf, FINI_RXQ_IN_INSTANCE,
2947                        efx_rx_queue_index(rx_queue));
2948
2949         rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_RXQ, inbuf, sizeof(inbuf),
2950                           outbuf, sizeof(outbuf), &outlen);
2951
2952         if (rc && rc != -EALREADY)
2953                 goto fail;
2954
2955         return;
2956
2957 fail:
2958         efx_mcdi_display_error(efx, MC_CMD_FINI_RXQ, MC_CMD_FINI_RXQ_IN_LEN,
2959                                outbuf, outlen, rc);
2960 }
2961
2962 static void efx_ef10_rx_remove(struct efx_rx_queue *rx_queue)
2963 {
2964         efx_nic_free_buffer(rx_queue->efx, &rx_queue->rxd.buf);
2965 }
2966
2967 /* This creates an entry in the RX descriptor queue */
2968 static inline void
2969 efx_ef10_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index)
2970 {
2971         struct efx_rx_buffer *rx_buf;
2972         efx_qword_t *rxd;
2973
2974         rxd = efx_rx_desc(rx_queue, index);
2975         rx_buf = efx_rx_buffer(rx_queue, index);
2976         EFX_POPULATE_QWORD_2(*rxd,
2977                              ESF_DZ_RX_KER_BYTE_CNT, rx_buf->len,
2978                              ESF_DZ_RX_KER_BUF_ADDR, rx_buf->dma_addr);
2979 }
2980
2981 static void efx_ef10_rx_write(struct efx_rx_queue *rx_queue)
2982 {
2983         struct efx_nic *efx = rx_queue->efx;
2984         unsigned int write_count;
2985         efx_dword_t reg;
2986
2987         /* Firmware requires that RX_DESC_WPTR be a multiple of 8 */
2988         write_count = rx_queue->added_count & ~7;
2989         if (rx_queue->notified_count == write_count)
2990                 return;
2991
2992         do
2993                 efx_ef10_build_rx_desc(
2994                         rx_queue,
2995                         rx_queue->notified_count & rx_queue->ptr_mask);
2996         while (++rx_queue->notified_count != write_count);
2997
2998         wmb();
2999         EFX_POPULATE_DWORD_1(reg, ERF_DZ_RX_DESC_WPTR,
3000                              write_count & rx_queue->ptr_mask);
3001         efx_writed_page(efx, &reg, ER_DZ_RX_DESC_UPD,
3002                         efx_rx_queue_index(rx_queue));
3003 }
3004
3005 static efx_mcdi_async_completer efx_ef10_rx_defer_refill_complete;
3006
3007 static void efx_ef10_rx_defer_refill(struct efx_rx_queue *rx_queue)
3008 {
3009         struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
3010         MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
3011         efx_qword_t event;
3012
3013         EFX_POPULATE_QWORD_2(event,
3014                              ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
3015                              ESF_DZ_EV_DATA, EFX_EF10_REFILL);
3016
3017         MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
3018
3019         /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
3020          * already swapped the data to little-endian order.
3021          */
3022         memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
3023                sizeof(efx_qword_t));
3024
3025         efx_mcdi_rpc_async(channel->efx, MC_CMD_DRIVER_EVENT,
3026                            inbuf, sizeof(inbuf), 0,
3027                            efx_ef10_rx_defer_refill_complete, 0);
3028 }
3029
3030 static void
3031 efx_ef10_rx_defer_refill_complete(struct efx_nic *efx, unsigned long cookie,
3032                                   int rc, efx_dword_t *outbuf,
3033                                   size_t outlen_actual)
3034 {
3035         /* nothing to do */
3036 }
3037
3038 static int efx_ef10_ev_probe(struct efx_channel *channel)
3039 {
3040         return efx_nic_alloc_buffer(channel->efx, &channel->eventq.buf,
3041                                     (channel->eventq_mask + 1) *
3042                                     sizeof(efx_qword_t),
3043                                     GFP_KERNEL);
3044 }
3045
3046 static void efx_ef10_ev_fini(struct efx_channel *channel)
3047 {
3048         MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_EVQ_IN_LEN);
3049         MCDI_DECLARE_BUF_ERR(outbuf);
3050         struct efx_nic *efx = channel->efx;
3051         size_t outlen;
3052         int rc;
3053
3054         MCDI_SET_DWORD(inbuf, FINI_EVQ_IN_INSTANCE, channel->channel);
3055
3056         rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_EVQ, inbuf, sizeof(inbuf),
3057                           outbuf, sizeof(outbuf), &outlen);
3058
3059         if (rc && rc != -EALREADY)
3060                 goto fail;
3061
3062         return;
3063
3064 fail:
3065         efx_mcdi_display_error(efx, MC_CMD_FINI_EVQ, MC_CMD_FINI_EVQ_IN_LEN,
3066                                outbuf, outlen, rc);
3067 }
3068
3069 static int efx_ef10_ev_init(struct efx_channel *channel)
3070 {
3071         MCDI_DECLARE_BUF(inbuf,
3072                          MC_CMD_INIT_EVQ_V2_IN_LEN(EFX_MAX_EVQ_SIZE * 8 /
3073                                                    EFX_BUF_SIZE));
3074         MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_EVQ_V2_OUT_LEN);
3075         size_t entries = channel->eventq.buf.len / EFX_BUF_SIZE;
3076         struct efx_nic *efx = channel->efx;
3077         struct efx_ef10_nic_data *nic_data;
3078         size_t inlen, outlen;
3079         unsigned int enabled, implemented;
3080         dma_addr_t dma_addr;
3081         int rc;
3082         int i;
3083
3084         nic_data = efx->nic_data;
3085
3086         /* Fill event queue with all ones (i.e. empty events) */
3087         memset(channel->eventq.buf.addr, 0xff, channel->eventq.buf.len);
3088
3089         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_SIZE, channel->eventq_mask + 1);
3090         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_INSTANCE, channel->channel);
3091         /* INIT_EVQ expects index in vector table, not absolute */
3092         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_IRQ_NUM, channel->channel);
3093         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_MODE,
3094                        MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS);
3095         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_LOAD, 0);
3096         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_RELOAD, 0);
3097         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_MODE,
3098                        MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS);
3099         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_THRSHLD, 0);
3100
3101         if (nic_data->datapath_caps2 &
3102             1 << MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_LBN) {
3103                 /* Use the new generic approach to specifying event queue
3104                  * configuration, requesting lower latency or higher throughput.
3105                  * The options that actually get used appear in the output.
3106                  */
3107                 MCDI_POPULATE_DWORD_2(inbuf, INIT_EVQ_V2_IN_FLAGS,
3108                                       INIT_EVQ_V2_IN_FLAG_INTERRUPTING, 1,
3109                                       INIT_EVQ_V2_IN_FLAG_TYPE,
3110                                       MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_AUTO);
3111         } else {
3112                 bool cut_thru = !(nic_data->datapath_caps &
3113                         1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN);
3114
3115                 MCDI_POPULATE_DWORD_4(inbuf, INIT_EVQ_IN_FLAGS,
3116                                       INIT_EVQ_IN_FLAG_INTERRUPTING, 1,
3117                                       INIT_EVQ_IN_FLAG_RX_MERGE, 1,
3118                                       INIT_EVQ_IN_FLAG_TX_MERGE, 1,
3119                                       INIT_EVQ_IN_FLAG_CUT_THRU, cut_thru);
3120         }
3121
3122         dma_addr = channel->eventq.buf.dma_addr;
3123         for (i = 0; i < entries; ++i) {
3124                 MCDI_SET_ARRAY_QWORD(inbuf, INIT_EVQ_IN_DMA_ADDR, i, dma_addr);
3125                 dma_addr += EFX_BUF_SIZE;
3126         }
3127
3128         inlen = MC_CMD_INIT_EVQ_IN_LEN(entries);
3129
3130         rc = efx_mcdi_rpc(efx, MC_CMD_INIT_EVQ, inbuf, inlen,
3131                           outbuf, sizeof(outbuf), &outlen);
3132
3133         if (outlen >= MC_CMD_INIT_EVQ_V2_OUT_LEN)
3134                 netif_dbg(efx, drv, efx->net_dev,
3135                           "Channel %d using event queue flags %08x\n",
3136                           channel->channel,
3137                           MCDI_DWORD(outbuf, INIT_EVQ_V2_OUT_FLAGS));
3138
3139         /* IRQ return is ignored */
3140         if (channel->channel || rc)
3141                 return rc;
3142
3143         /* Successfully created event queue on channel 0 */
3144         rc = efx_mcdi_get_workarounds(efx, &implemented, &enabled);
3145         if (rc == -ENOSYS) {
3146                 /* GET_WORKAROUNDS was implemented before this workaround,
3147                  * thus it must be unavailable in this firmware.
3148                  */
3149                 nic_data->workaround_26807 = false;
3150                 rc = 0;
3151         } else if (rc) {
3152                 goto fail;
3153         } else {
3154                 nic_data->workaround_26807 =
3155                         !!(enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807);
3156
3157                 if (implemented & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807 &&
3158                     !nic_data->workaround_26807) {
3159                         unsigned int flags;
3160
3161                         rc = efx_mcdi_set_workaround(efx,
3162                                                      MC_CMD_WORKAROUND_BUG26807,
3163                                                      true, &flags);
3164
3165                         if (!rc) {
3166                                 if (flags &
3167                                     1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN) {
3168                                         netif_info(efx, drv, efx->net_dev,
3169                                                    "other functions on NIC have been reset\n");
3170
3171                                         /* With MCFW v4.6.x and earlier, the
3172                                          * boot count will have incremented,
3173                                          * so re-read the warm_boot_count
3174                                          * value now to ensure this function
3175                                          * doesn't think it has changed next
3176                                          * time it checks.
3177                                          */
3178                                         rc = efx_ef10_get_warm_boot_count(efx);
3179                                         if (rc >= 0) {
3180                                                 nic_data->warm_boot_count = rc;
3181                                                 rc = 0;
3182                                         }
3183                                 }
3184                                 nic_data->workaround_26807 = true;
3185                         } else if (rc == -EPERM) {
3186                                 rc = 0;
3187                         }
3188                 }
3189         }
3190
3191         if (!rc)
3192                 return 0;
3193
3194 fail:
3195         efx_ef10_ev_fini(channel);
3196         return rc;
3197 }
3198
3199 static void efx_ef10_ev_remove(struct efx_channel *channel)
3200 {
3201         efx_nic_free_buffer(channel->efx, &channel->eventq.buf);
3202 }
3203
3204 static void efx_ef10_handle_rx_wrong_queue(struct efx_rx_queue *rx_queue,
3205                                            unsigned int rx_queue_label)
3206 {
3207         struct efx_nic *efx = rx_queue->efx;
3208
3209         netif_info(efx, hw, efx->net_dev,
3210                    "rx event arrived on queue %d labeled as queue %u\n",
3211                    efx_rx_queue_index(rx_queue), rx_queue_label);
3212
3213         efx_schedule_reset(efx, RESET_TYPE_DISABLE);
3214 }
3215
3216 static void
3217 efx_ef10_handle_rx_bad_lbits(struct efx_rx_queue *rx_queue,
3218                              unsigned int actual, unsigned int expected)
3219 {
3220         unsigned int dropped = (actual - expected) & rx_queue->ptr_mask;
3221         struct efx_nic *efx = rx_queue->efx;
3222
3223         netif_info(efx, hw, efx->net_dev,
3224                    "dropped %d events (index=%d expected=%d)\n",
3225                    dropped, actual, expected);
3226
3227         efx_schedule_reset(efx, RESET_TYPE_DISABLE);
3228 }
3229
3230 /* partially received RX was aborted. clean up. */
3231 static void efx_ef10_handle_rx_abort(struct efx_rx_queue *rx_queue)
3232 {
3233         unsigned int rx_desc_ptr;
3234
3235         netif_dbg(rx_queue->efx, hw, rx_queue->efx->net_dev,
3236                   "scattered RX aborted (dropping %u buffers)\n",
3237                   rx_queue->scatter_n);
3238
3239         rx_desc_ptr = rx_queue->removed_count & rx_queue->ptr_mask;
3240
3241         efx_rx_packet(rx_queue, rx_desc_ptr, rx_queue->scatter_n,
3242                       0, EFX_RX_PKT_DISCARD);
3243
3244         rx_queue->removed_count += rx_queue->scatter_n;
3245         rx_queue->scatter_n = 0;
3246         rx_queue->scatter_len = 0;
3247         ++efx_rx_queue_channel(rx_queue)->n_rx_nodesc_trunc;
3248 }
3249
3250 static u16 efx_ef10_handle_rx_event_errors(struct efx_channel *channel,
3251                                            unsigned int n_packets,
3252                                            unsigned int rx_encap_hdr,
3253                                            unsigned int rx_l3_class,
3254                                            unsigned int rx_l4_class,
3255                                            const efx_qword_t *event)
3256 {
3257         struct efx_nic *efx = channel->efx;
3258         bool handled = false;
3259
3260         if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_ECRC_ERR)) {
3261                 if (!(efx->net_dev->features & NETIF_F_RXALL)) {
3262                         if (!efx->loopback_selftest)
3263                                 channel->n_rx_eth_crc_err += n_packets;
3264                         return EFX_RX_PKT_DISCARD;
3265                 }
3266                 handled = true;
3267         }
3268         if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_IPCKSUM_ERR)) {
3269                 if (unlikely(rx_encap_hdr != ESE_EZ_ENCAP_HDR_VXLAN &&
3270                              rx_l3_class != ESE_DZ_L3_CLASS_IP4 &&
3271                              rx_l3_class != ESE_DZ_L3_CLASS_IP4_FRAG &&
3272                              rx_l3_class != ESE_DZ_L3_CLASS_IP6 &&
3273                              rx_l3_class != ESE_DZ_L3_CLASS_IP6_FRAG))
3274                         netdev_WARN(efx->net_dev,
3275                                     "invalid class for RX_IPCKSUM_ERR: event="
3276                                     EFX_QWORD_FMT "\n",
3277                                     EFX_QWORD_VAL(*event));
3278                 if (!efx->loopback_selftest)
3279                         *(rx_encap_hdr ?
3280                           &channel->n_rx_outer_ip_hdr_chksum_err :
3281                           &channel->n_rx_ip_hdr_chksum_err) += n_packets;
3282                 return 0;
3283         }
3284         if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_TCPUDP_CKSUM_ERR)) {
3285                 if (unlikely(rx_encap_hdr != ESE_EZ_ENCAP_HDR_VXLAN &&
3286                              ((rx_l3_class != ESE_DZ_L3_CLASS_IP4 &&
3287                                rx_l3_class != ESE_DZ_L3_CLASS_IP6) ||
3288                               (rx_l4_class != ESE_DZ_L4_CLASS_TCP &&
3289                                rx_l4_class != ESE_DZ_L4_CLASS_UDP))))
3290                         netdev_WARN(efx->net_dev,
3291                                     "invalid class for RX_TCPUDP_CKSUM_ERR: event="
3292                                     EFX_QWORD_FMT "\n",
3293                                     EFX_QWORD_VAL(*event));
3294                 if (!efx->loopback_selftest)
3295                         *(rx_encap_hdr ?
3296                           &channel->n_rx_outer_tcp_udp_chksum_err :
3297                           &channel->n_rx_tcp_udp_chksum_err) += n_packets;
3298                 return 0;
3299         }
3300         if (EFX_QWORD_FIELD(*event, ESF_EZ_RX_IP_INNER_CHKSUM_ERR)) {
3301                 if (unlikely(!rx_encap_hdr))
3302                         netdev_WARN(efx->net_dev,
3303                                     "invalid encapsulation type for RX_IP_INNER_CHKSUM_ERR: event="
3304                                     EFX_QWORD_FMT "\n",
3305                                     EFX_QWORD_VAL(*event));
3306                 else if (unlikely(rx_l3_class != ESE_DZ_L3_CLASS_IP4 &&
3307                                   rx_l3_class != ESE_DZ_L3_CLASS_IP4_FRAG &&
3308                                   rx_l3_class != ESE_DZ_L3_CLASS_IP6 &&
3309                                   rx_l3_class != ESE_DZ_L3_CLASS_IP6_FRAG))
3310                         netdev_WARN(efx->net_dev,
3311                                     "invalid class for RX_IP_INNER_CHKSUM_ERR: event="
3312                                     EFX_QWORD_FMT "\n",
3313                                     EFX_QWORD_VAL(*event));
3314                 if (!efx->loopback_selftest)
3315                         channel->n_rx_inner_ip_hdr_chksum_err += n_packets;
3316                 return 0;
3317         }
3318         if (EFX_QWORD_FIELD(*event, ESF_EZ_RX_TCP_UDP_INNER_CHKSUM_ERR)) {
3319                 if (unlikely(!rx_encap_hdr))
3320                         netdev_WARN(efx->net_dev,
3321                                     "invalid encapsulation type for RX_TCP_UDP_INNER_CHKSUM_ERR: event="
3322                                     EFX_QWORD_FMT "\n",
3323                                     EFX_QWORD_VAL(*event));
3324                 else if (unlikely((rx_l3_class != ESE_DZ_L3_CLASS_IP4 &&
3325                                    rx_l3_class != ESE_DZ_L3_CLASS_IP6) ||
3326                                   (rx_l4_class != ESE_DZ_L4_CLASS_TCP &&
3327                                    rx_l4_class != ESE_DZ_L4_CLASS_UDP)))
3328                         netdev_WARN(efx->net_dev,
3329                                     "invalid class for RX_TCP_UDP_INNER_CHKSUM_ERR: event="
3330                                     EFX_QWORD_FMT "\n",
3331                                     EFX_QWORD_VAL(*event));
3332                 if (!efx->loopback_selftest)
3333                         channel->n_rx_inner_tcp_udp_chksum_err += n_packets;
3334                 return 0;
3335         }
3336
3337         WARN_ON(!handled); /* No error bits were recognised */
3338         return 0;
3339 }
3340
3341 static int efx_ef10_handle_rx_event(struct efx_channel *channel,
3342                                     const efx_qword_t *event)
3343 {
3344         unsigned int rx_bytes, next_ptr_lbits, rx_queue_label;
3345         unsigned int rx_l3_class, rx_l4_class, rx_encap_hdr;
3346         unsigned int n_descs, n_packets, i;
3347         struct efx_nic *efx = channel->efx;
3348         struct efx_ef10_nic_data *nic_data = efx->nic_data;
3349         struct efx_rx_queue *rx_queue;
3350         efx_qword_t errors;
3351         bool rx_cont;
3352         u16 flags = 0;
3353
3354         if (unlikely(READ_ONCE(efx->reset_pending)))
3355                 return 0;
3356
3357         /* Basic packet information */
3358         rx_bytes = EFX_QWORD_FIELD(*event, ESF_DZ_RX_BYTES);
3359         next_ptr_lbits = EFX_QWORD_FIELD(*event, ESF_DZ_RX_DSC_PTR_LBITS);
3360         rx_queue_label = EFX_QWORD_FIELD(*event, ESF_DZ_RX_QLABEL);
3361         rx_l3_class = EFX_QWORD_FIELD(*event, ESF_DZ_RX_L3_CLASS);
3362         rx_l4_class = EFX_QWORD_FIELD(*event, ESF_DZ_RX_L4_CLASS);
3363         rx_cont = EFX_QWORD_FIELD(*event, ESF_DZ_RX_CONT);
3364         rx_encap_hdr =
3365                 nic_data->datapath_caps &
3366                         (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN) ?
3367                 EFX_QWORD_FIELD(*event, ESF_EZ_RX_ENCAP_HDR) :
3368                 ESE_EZ_ENCAP_HDR_NONE;
3369
3370         if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_DROP_EVENT))
3371                 netdev_WARN(efx->net_dev, "saw RX_DROP_EVENT: event="
3372                             EFX_QWORD_FMT "\n",
3373                             EFX_QWORD_VAL(*event));
3374
3375         rx_queue = efx_channel_get_rx_queue(channel);
3376
3377         if (unlikely(rx_queue_label != efx_rx_queue_index(rx_queue)))
3378                 efx_ef10_handle_rx_wrong_queue(rx_queue, rx_queue_label);
3379
3380         n_descs = ((next_ptr_lbits - rx_queue->removed_count) &
3381                    ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
3382
3383         if (n_descs != rx_queue->scatter_n + 1) {
3384                 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3385
3386                 /* detect rx abort */
3387                 if (unlikely(n_descs == rx_queue->scatter_n)) {
3388                         if (rx_queue->scatter_n == 0 || rx_bytes != 0)
3389                                 netdev_WARN(efx->net_dev,
3390                                             "invalid RX abort: scatter_n=%u event="
3391                                             EFX_QWORD_FMT "\n",
3392                                             rx_queue->scatter_n,
3393                                             EFX_QWORD_VAL(*event));
3394                         efx_ef10_handle_rx_abort(rx_queue);
3395                         return 0;
3396                 }
3397
3398                 /* Check that RX completion merging is valid, i.e.
3399                  * the current firmware supports it and this is a
3400                  * non-scattered packet.
3401                  */
3402                 if (!(nic_data->datapath_caps &
3403                       (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN)) ||
3404                     rx_queue->scatter_n != 0 || rx_cont) {
3405                         efx_ef10_handle_rx_bad_lbits(
3406                                 rx_queue, next_ptr_lbits,
3407                                 (rx_queue->removed_count +
3408                                  rx_queue->scatter_n + 1) &
3409                                 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
3410                         return 0;
3411                 }
3412
3413                 /* Merged completion for multiple non-scattered packets */
3414                 rx_queue->scatter_n = 1;
3415                 rx_queue->scatter_len = 0;
3416                 n_packets = n_descs;
3417                 ++channel->n_rx_merge_events;
3418                 channel->n_rx_merge_packets += n_packets;
3419                 flags |= EFX_RX_PKT_PREFIX_LEN;
3420         } else {
3421                 ++rx_queue->scatter_n;
3422                 rx_queue->scatter_len += rx_bytes;
3423                 if (rx_cont)
3424                         return 0;
3425                 n_packets = 1;
3426         }
3427
3428         EFX_POPULATE_QWORD_5(errors, ESF_DZ_RX_ECRC_ERR, 1,
3429                                      ESF_DZ_RX_IPCKSUM_ERR, 1,
3430                                      ESF_DZ_RX_TCPUDP_CKSUM_ERR, 1,
3431                                      ESF_EZ_RX_IP_INNER_CHKSUM_ERR, 1,
3432                                      ESF_EZ_RX_TCP_UDP_INNER_CHKSUM_ERR, 1);
3433         EFX_AND_QWORD(errors, *event, errors);
3434         if (unlikely(!EFX_QWORD_IS_ZERO(errors))) {
3435                 flags |= efx_ef10_handle_rx_event_errors(channel, n_packets,
3436                                                          rx_encap_hdr,
3437                                                          rx_l3_class, rx_l4_class,
3438                                                          event);
3439         } else {
3440                 bool tcpudp = rx_l4_class == ESE_DZ_L4_CLASS_TCP ||
3441                               rx_l4_class == ESE_DZ_L4_CLASS_UDP;
3442
3443                 switch (rx_encap_hdr) {
3444                 case ESE_EZ_ENCAP_HDR_VXLAN: /* VxLAN or GENEVE */
3445                         flags |= EFX_RX_PKT_CSUMMED; /* outer UDP csum */
3446                         if (tcpudp)
3447                                 flags |= EFX_RX_PKT_CSUM_LEVEL; /* inner L4 */
3448                         break;
3449                 case ESE_EZ_ENCAP_HDR_GRE:
3450                 case ESE_EZ_ENCAP_HDR_NONE:
3451                         if (tcpudp)
3452                                 flags |= EFX_RX_PKT_CSUMMED;
3453                         break;
3454                 default:
3455                         netdev_WARN(efx->net_dev,
3456                                     "unknown encapsulation type: event="
3457                                     EFX_QWORD_FMT "\n",
3458                                     EFX_QWORD_VAL(*event));
3459                 }
3460         }
3461
3462         if (rx_l4_class == ESE_DZ_L4_CLASS_TCP)
3463                 flags |= EFX_RX_PKT_TCP;
3464
3465         channel->irq_mod_score += 2 * n_packets;
3466
3467         /* Handle received packet(s) */
3468         for (i = 0; i < n_packets; i++) {
3469                 efx_rx_packet(rx_queue,
3470                               rx_queue->removed_count & rx_queue->ptr_mask,
3471                               rx_queue->scatter_n, rx_queue->scatter_len,
3472                               flags);
3473                 rx_queue->removed_count += rx_queue->scatter_n;
3474         }
3475
3476         rx_queue->scatter_n = 0;
3477         rx_queue->scatter_len = 0;
3478
3479         return n_packets;
3480 }
3481
3482 static int
3483 efx_ef10_handle_tx_event(struct efx_channel *channel, efx_qword_t *event)
3484 {
3485         struct efx_nic *efx = channel->efx;
3486         struct efx_tx_queue *tx_queue;
3487         unsigned int tx_ev_desc_ptr;
3488         unsigned int tx_ev_q_label;
3489         int tx_descs = 0;
3490
3491         if (unlikely(READ_ONCE(efx->reset_pending)))
3492                 return 0;
3493
3494         if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_TX_DROP_EVENT)))
3495                 return 0;
3496
3497         /* Transmit completion */
3498         tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, ESF_DZ_TX_DESCR_INDX);
3499         tx_ev_q_label = EFX_QWORD_FIELD(*event, ESF_DZ_TX_QLABEL);
3500         tx_queue = efx_channel_get_tx_queue(channel,
3501                                             tx_ev_q_label % EFX_TXQ_TYPES);
3502         tx_descs = ((tx_ev_desc_ptr + 1 - tx_queue->read_count) &
3503                     tx_queue->ptr_mask);
3504         efx_xmit_done(tx_queue, tx_ev_desc_ptr & tx_queue->ptr_mask);
3505
3506         return tx_descs;
3507 }
3508
3509 static void
3510 efx_ef10_handle_driver_event(struct efx_channel *channel, efx_qword_t *event)
3511 {
3512         struct efx_nic *efx = channel->efx;
3513         int subcode;
3514
3515         subcode = EFX_QWORD_FIELD(*event, ESF_DZ_DRV_SUB_CODE);
3516
3517         switch (subcode) {
3518         case ESE_DZ_DRV_TIMER_EV:
3519         case ESE_DZ_DRV_WAKE_UP_EV:
3520                 break;
3521         case ESE_DZ_DRV_START_UP_EV:
3522                 /* event queue init complete. ok. */
3523                 break;
3524         default:
3525                 netif_err(efx, hw, efx->net_dev,
3526                           "channel %d unknown driver event type %d"
3527                           " (data " EFX_QWORD_FMT ")\n",
3528                           channel->channel, subcode,
3529                           EFX_QWORD_VAL(*event));
3530
3531         }
3532 }
3533
3534 static void efx_ef10_handle_driver_generated_event(struct efx_channel *channel,
3535                                                    efx_qword_t *event)
3536 {
3537         struct efx_nic *efx = channel->efx;
3538         u32 subcode;
3539
3540         subcode = EFX_QWORD_FIELD(*event, EFX_DWORD_0);
3541
3542         switch (subcode) {
3543         case EFX_EF10_TEST:
3544                 channel->event_test_cpu = raw_smp_processor_id();
3545                 break;
3546         case EFX_EF10_REFILL:
3547                 /* The queue must be empty, so we won't receive any rx
3548                  * events, so efx_process_channel() won't refill the
3549                  * queue. Refill it here
3550                  */
3551                 efx_fast_push_rx_descriptors(&channel->rx_queue, true);
3552                 break;
3553         default:
3554                 netif_err(efx, hw, efx->net_dev,
3555                           "channel %d unknown driver event type %u"
3556                           " (data " EFX_QWORD_FMT ")\n",
3557                           channel->channel, (unsigned) subcode,
3558                           EFX_QWORD_VAL(*event));
3559         }
3560 }
3561
3562 static int efx_ef10_ev_process(struct efx_channel *channel, int quota)
3563 {
3564         struct efx_nic *efx = channel->efx;
3565         efx_qword_t event, *p_event;
3566         unsigned int read_ptr;
3567         int ev_code;
3568         int tx_descs = 0;
3569         int spent = 0;
3570
3571         if (quota <= 0)
3572                 return spent;
3573
3574         read_ptr = channel->eventq_read_ptr;
3575
3576         for (;;) {
3577                 p_event = efx_event(channel, read_ptr);
3578                 event = *p_event;
3579
3580                 if (!efx_event_present(&event))
3581                         break;
3582
3583                 EFX_SET_QWORD(*p_event);
3584
3585                 ++read_ptr;
3586
3587                 ev_code = EFX_QWORD_FIELD(event, ESF_DZ_EV_CODE);
3588
3589                 netif_vdbg(efx, drv, efx->net_dev,
3590                            "processing event on %d " EFX_QWORD_FMT "\n",
3591                            channel->channel, EFX_QWORD_VAL(event));
3592
3593                 switch (ev_code) {
3594                 case ESE_DZ_EV_CODE_MCDI_EV:
3595                         efx_mcdi_process_event(channel, &event);
3596                         break;
3597                 case ESE_DZ_EV_CODE_RX_EV:
3598                         spent += efx_ef10_handle_rx_event(channel, &event);
3599                         if (spent >= quota) {
3600                                 /* XXX can we split a merged event to
3601                                  * avoid going over-quota?
3602                                  */
3603                                 spent = quota;
3604                                 goto out;
3605                         }
3606                         break;
3607                 case ESE_DZ_EV_CODE_TX_EV:
3608                         tx_descs += efx_ef10_handle_tx_event(channel, &event);
3609                         if (tx_descs > efx->txq_entries) {
3610                                 spent = quota;
3611                                 goto out;
3612                         } else if (++spent == quota) {
3613                                 goto out;
3614                         }
3615                         break;
3616                 case ESE_DZ_EV_CODE_DRIVER_EV:
3617                         efx_ef10_handle_driver_event(channel, &event);
3618                         if (++spent == quota)
3619                                 goto out;
3620                         break;
3621                 case EFX_EF10_DRVGEN_EV:
3622                         efx_ef10_handle_driver_generated_event(channel, &event);
3623                         break;
3624                 default:
3625                         netif_err(efx, hw, efx->net_dev,
3626                                   "channel %d unknown event type %d"
3627                                   " (data " EFX_QWORD_FMT ")\n",
3628                                   channel->channel, ev_code,
3629                                   EFX_QWORD_VAL(event));
3630                 }
3631         }
3632
3633 out:
3634         channel->eventq_read_ptr = read_ptr;
3635         return spent;
3636 }
3637
3638 static void efx_ef10_ev_read_ack(struct efx_channel *channel)
3639 {
3640         struct efx_nic *efx = channel->efx;
3641         efx_dword_t rptr;
3642
3643         if (EFX_EF10_WORKAROUND_35388(efx)) {
3644                 BUILD_BUG_ON(EFX_MIN_EVQ_SIZE <
3645                              (1 << ERF_DD_EVQ_IND_RPTR_WIDTH));
3646                 BUILD_BUG_ON(EFX_MAX_EVQ_SIZE >
3647                              (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH));
3648
3649                 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
3650                                      EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH,
3651                                      ERF_DD_EVQ_IND_RPTR,
3652                                      (channel->eventq_read_ptr &
3653                                       channel->eventq_mask) >>
3654                                      ERF_DD_EVQ_IND_RPTR_WIDTH);
3655                 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
3656                                 channel->channel);
3657                 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
3658                                      EFE_DD_EVQ_IND_RPTR_FLAGS_LOW,
3659                                      ERF_DD_EVQ_IND_RPTR,
3660                                      channel->eventq_read_ptr &
3661                                      ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1));
3662                 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
3663                                 channel->channel);
3664         } else {
3665                 EFX_POPULATE_DWORD_1(rptr, ERF_DZ_EVQ_RPTR,
3666                                      channel->eventq_read_ptr &
3667                                      channel->eventq_mask);
3668                 efx_writed_page(efx, &rptr, ER_DZ_EVQ_RPTR, channel->channel);
3669         }
3670 }
3671
3672 static void efx_ef10_ev_test_generate(struct efx_channel *channel)
3673 {
3674         MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
3675         struct efx_nic *efx = channel->efx;
3676         efx_qword_t event;
3677         int rc;
3678
3679         EFX_POPULATE_QWORD_2(event,
3680                              ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
3681                              ESF_DZ_EV_DATA, EFX_EF10_TEST);
3682
3683         MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
3684
3685         /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
3686          * already swapped the data to little-endian order.
3687          */
3688         memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
3689                sizeof(efx_qword_t));
3690
3691         rc = efx_mcdi_rpc(efx, MC_CMD_DRIVER_EVENT, inbuf, sizeof(inbuf),
3692                           NULL, 0, NULL);
3693         if (rc != 0)
3694                 goto fail;
3695
3696         return;
3697
3698 fail:
3699         WARN_ON(true);
3700         netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
3701 }
3702
3703 void efx_ef10_handle_drain_event(struct efx_nic *efx)
3704 {
3705         if (atomic_dec_and_test(&efx->active_queues))
3706                 wake_up(&efx->flush_wq);
3707
3708         WARN_ON(atomic_read(&efx->active_queues) < 0);
3709 }
3710
3711 static int efx_ef10_fini_dmaq(struct efx_nic *efx)
3712 {
3713         struct efx_ef10_nic_data *nic_data = efx->nic_data;
3714         struct efx_channel *channel;
3715         struct efx_tx_queue *tx_queue;
3716         struct efx_rx_queue *rx_queue;
3717         int pending;
3718
3719         /* If the MC has just rebooted, the TX/RX queues will have already been
3720          * torn down, but efx->active_queues needs to be set to zero.
3721          */
3722         if (nic_data->must_realloc_vis) {
3723                 atomic_set(&efx->active_queues, 0);
3724                 return 0;
3725         }
3726
3727         /* Do not attempt to write to the NIC during EEH recovery */
3728         if (efx->state != STATE_RECOVERY) {
3729                 efx_for_each_channel(channel, efx) {
3730                         efx_for_each_channel_rx_queue(rx_queue, channel)
3731                                 efx_ef10_rx_fini(rx_queue);
3732                         efx_for_each_channel_tx_queue(tx_queue, channel)
3733                                 efx_ef10_tx_fini(tx_queue);
3734                 }
3735
3736                 wait_event_timeout(efx->flush_wq,
3737                                    atomic_read(&efx->active_queues) == 0,
3738                                    msecs_to_jiffies(EFX_MAX_FLUSH_TIME));
3739                 pending = atomic_read(&efx->active_queues);
3740                 if (pending) {
3741                         netif_err(efx, hw, efx->net_dev, "failed to flush %d queues\n",
3742                                   pending);
3743                         return -ETIMEDOUT;
3744                 }
3745         }
3746
3747         return 0;
3748 }
3749
3750 static void efx_ef10_prepare_flr(struct efx_nic *efx)
3751 {
3752         atomic_set(&efx->active_queues, 0);
3753 }
3754
3755 static bool efx_ef10_filter_equal(const struct efx_filter_spec *left,
3756                                   const struct efx_filter_spec *right)
3757 {
3758         if ((left->match_flags ^ right->match_flags) |
3759             ((left->flags ^ right->flags) &
3760              (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)))
3761                 return false;
3762
3763         return memcmp(&left->outer_vid, &right->outer_vid,
3764                       sizeof(struct efx_filter_spec) -
3765                       offsetof(struct efx_filter_spec, outer_vid)) == 0;
3766 }
3767
3768 static unsigned int efx_ef10_filter_hash(const struct efx_filter_spec *spec)
3769 {
3770         BUILD_BUG_ON(offsetof(struct efx_filter_spec, outer_vid) & 3);
3771         return jhash2((const u32 *)&spec->outer_vid,
3772                       (sizeof(struct efx_filter_spec) -
3773                        offsetof(struct efx_filter_spec, outer_vid)) / 4,
3774                       0);
3775         /* XXX should we randomise the initval? */
3776 }
3777
3778 /* Decide whether a filter should be exclusive or else should allow
3779  * delivery to additional recipients.  Currently we decide that
3780  * filters for specific local unicast MAC and IP addresses are
3781  * exclusive.
3782  */
3783 static bool efx_ef10_filter_is_exclusive(const struct efx_filter_spec *spec)
3784 {
3785         if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC &&
3786             !is_multicast_ether_addr(spec->loc_mac))
3787                 return true;
3788
3789         if ((spec->match_flags &
3790              (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) ==
3791             (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) {
3792                 if (spec->ether_type == htons(ETH_P_IP) &&
3793                     !ipv4_is_multicast(spec->loc_host[0]))
3794                         return true;
3795                 if (spec->ether_type == htons(ETH_P_IPV6) &&
3796                     ((const u8 *)spec->loc_host)[0] != 0xff)
3797                         return true;
3798         }
3799
3800         return false;
3801 }
3802
3803 static struct efx_filter_spec *
3804 efx_ef10_filter_entry_spec(const struct efx_ef10_filter_table *table,
3805                            unsigned int filter_idx)
3806 {
3807         return (struct efx_filter_spec *)(table->entry[filter_idx].spec &
3808                                           ~EFX_EF10_FILTER_FLAGS);
3809 }
3810
3811 static unsigned int
3812 efx_ef10_filter_entry_flags(const struct efx_ef10_filter_table *table,
3813                            unsigned int filter_idx)
3814 {
3815         return table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAGS;
3816 }
3817
3818 static void
3819 efx_ef10_filter_set_entry(struct efx_ef10_filter_table *table,
3820                           unsigned int filter_idx,
3821                           const struct efx_filter_spec *spec,
3822                           unsigned int flags)
3823 {
3824         table->entry[filter_idx].spec = (unsigned long)spec | flags;
3825 }
3826
3827 static void
3828 efx_ef10_filter_push_prep_set_match_fields(struct efx_nic *efx,
3829                                            const struct efx_filter_spec *spec,
3830                                            efx_dword_t *inbuf)
3831 {
3832         enum efx_encap_type encap_type = efx_filter_get_encap_type(spec);
3833         u32 match_fields = 0, uc_match, mc_match;
3834
3835         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3836                        efx_ef10_filter_is_exclusive(spec) ?
3837                        MC_CMD_FILTER_OP_IN_OP_INSERT :
3838                        MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE);
3839
3840         /* Convert match flags and values.  Unlike almost
3841          * everything else in MCDI, these fields are in
3842          * network byte order.
3843          */
3844 #define COPY_VALUE(value, mcdi_field)                                        \
3845         do {                                                         \
3846                 match_fields |=                                      \
3847                         1 << MC_CMD_FILTER_OP_IN_MATCH_ ##           \
3848                         mcdi_field ## _LBN;                          \
3849                 BUILD_BUG_ON(                                        \
3850                         MC_CMD_FILTER_OP_IN_ ## mcdi_field ## _LEN < \
3851                         sizeof(value));                              \
3852                 memcpy(MCDI_PTR(inbuf, FILTER_OP_IN_ ## mcdi_field), \
3853                        &value, sizeof(value));                       \
3854         } while (0)
3855 #define COPY_FIELD(gen_flag, gen_field, mcdi_field)                          \
3856         if (spec->match_flags & EFX_FILTER_MATCH_ ## gen_flag) {     \
3857                 COPY_VALUE(spec->gen_field, mcdi_field);             \
3858         }
3859         /* Handle encap filters first.  They will always be mismatch
3860          * (unknown UC or MC) filters
3861          */
3862         if (encap_type) {
3863                 /* ether_type and outer_ip_proto need to be variables
3864                  * because COPY_VALUE wants to memcpy them
3865                  */
3866                 __be16 ether_type =
3867                         htons(encap_type & EFX_ENCAP_FLAG_IPV6 ?
3868                               ETH_P_IPV6 : ETH_P_IP);
3869                 u8 vni_type = MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_GENEVE;
3870                 u8 outer_ip_proto;
3871
3872                 switch (encap_type & EFX_ENCAP_TYPES_MASK) {
3873                 case EFX_ENCAP_TYPE_VXLAN:
3874                         vni_type = MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_VXLAN;
3875                         /* fallthrough */
3876                 case EFX_ENCAP_TYPE_GENEVE:
3877                         COPY_VALUE(ether_type, ETHER_TYPE);
3878                         outer_ip_proto = IPPROTO_UDP;
3879                         COPY_VALUE(outer_ip_proto, IP_PROTO);
3880                         /* We always need to set the type field, even
3881                          * though we're not matching on the TNI.
3882                          */
3883                         MCDI_POPULATE_DWORD_1(inbuf,
3884                                 FILTER_OP_EXT_IN_VNI_OR_VSID,
3885                                 FILTER_OP_EXT_IN_VNI_TYPE,
3886                                 vni_type);
3887                         break;
3888                 case EFX_ENCAP_TYPE_NVGRE:
3889                         COPY_VALUE(ether_type, ETHER_TYPE);
3890                         outer_ip_proto = IPPROTO_GRE;
3891                         COPY_VALUE(outer_ip_proto, IP_PROTO);
3892                         break;
3893                 default:
3894                         WARN_ON(1);
3895                 }
3896
3897                 uc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_LBN;
3898                 mc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_LBN;
3899         } else {
3900                 uc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_LBN;
3901                 mc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_LBN;
3902         }
3903
3904         if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC_IG)
3905                 match_fields |=
3906                         is_multicast_ether_addr(spec->loc_mac) ?
3907                         1 << mc_match :
3908                         1 << uc_match;
3909         COPY_FIELD(REM_HOST, rem_host, SRC_IP);
3910         COPY_FIELD(LOC_HOST, loc_host, DST_IP);
3911         COPY_FIELD(REM_MAC, rem_mac, SRC_MAC);
3912         COPY_FIELD(REM_PORT, rem_port, SRC_PORT);
3913         COPY_FIELD(LOC_MAC, loc_mac, DST_MAC);
3914         COPY_FIELD(LOC_PORT, loc_port, DST_PORT);
3915         COPY_FIELD(ETHER_TYPE, ether_type, ETHER_TYPE);
3916         COPY_FIELD(INNER_VID, inner_vid, INNER_VLAN);
3917         COPY_FIELD(OUTER_VID, outer_vid, OUTER_VLAN);
3918         COPY_FIELD(IP_PROTO, ip_proto, IP_PROTO);
3919 #undef COPY_FIELD
3920 #undef COPY_VALUE
3921         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_MATCH_FIELDS,
3922                        match_fields);
3923 }
3924
3925 static void efx_ef10_filter_push_prep(struct efx_nic *efx,
3926                                       const struct efx_filter_spec *spec,
3927                                       efx_dword_t *inbuf, u64 handle,
3928                                       bool replacing)
3929 {
3930         struct efx_ef10_nic_data *nic_data = efx->nic_data;
3931         u32 flags = spec->flags;
3932
3933         memset(inbuf, 0, MC_CMD_FILTER_OP_EXT_IN_LEN);
3934
3935         /* Remove RSS flag if we don't have an RSS context. */
3936         if (flags & EFX_FILTER_FLAG_RX_RSS &&
3937             spec->rss_context == EFX_FILTER_RSS_CONTEXT_DEFAULT &&
3938             nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID)
3939                 flags &= ~EFX_FILTER_FLAG_RX_RSS;
3940
3941         if (replacing) {
3942                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3943                                MC_CMD_FILTER_OP_IN_OP_REPLACE);
3944                 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, handle);
3945         } else {
3946                 efx_ef10_filter_push_prep_set_match_fields(efx, spec, inbuf);
3947         }
3948
3949         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_PORT_ID, nic_data->vport_id);
3950         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_DEST,
3951                        spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
3952                        MC_CMD_FILTER_OP_IN_RX_DEST_DROP :
3953                        MC_CMD_FILTER_OP_IN_RX_DEST_HOST);
3954         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DOMAIN, 0);
3955         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DEST,
3956                        MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT);
3957         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_QUEUE,
3958                        spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
3959                        0 : spec->dmaq_id);
3960         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_MODE,
3961                        (flags & EFX_FILTER_FLAG_RX_RSS) ?
3962                        MC_CMD_FILTER_OP_IN_RX_MODE_RSS :
3963                        MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE);
3964         if (flags & EFX_FILTER_FLAG_RX_RSS)
3965                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_CONTEXT,
3966                                spec->rss_context !=
3967                                EFX_FILTER_RSS_CONTEXT_DEFAULT ?
3968                                spec->rss_context : nic_data->rx_rss_context);
3969 }
3970
3971 static int efx_ef10_filter_push(struct efx_nic *efx,
3972                                 const struct efx_filter_spec *spec,
3973                                 u64 *handle, bool replacing)
3974 {
3975         MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_EXT_IN_LEN);
3976         MCDI_DECLARE_BUF(outbuf, MC_CMD_FILTER_OP_EXT_OUT_LEN);
3977         int rc;
3978
3979         efx_ef10_filter_push_prep(efx, spec, inbuf, *handle, replacing);
3980         rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
3981                           outbuf, sizeof(outbuf), NULL);
3982         if (rc == 0)
3983                 *handle = MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
3984         if (rc == -ENOSPC)
3985                 rc = -EBUSY; /* to match efx_farch_filter_insert() */
3986         return rc;
3987 }
3988
3989 static u32 efx_ef10_filter_mcdi_flags_from_spec(const struct efx_filter_spec *spec)
3990 {
3991         enum efx_encap_type encap_type = efx_filter_get_encap_type(spec);
3992         unsigned int match_flags = spec->match_flags;
3993         unsigned int uc_match, mc_match;
3994         u32 mcdi_flags = 0;
3995
3996 #define MAP_FILTER_TO_MCDI_FLAG(gen_flag, mcdi_field, encap) {          \
3997                 unsigned int  old_match_flags = match_flags;            \
3998                 match_flags &= ~EFX_FILTER_MATCH_ ## gen_flag;          \
3999                 if (match_flags != old_match_flags)                     \
4000                         mcdi_flags |=                                   \
4001                                 (1 << ((encap) ?                        \
4002                                        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_ ## \
4003                                        mcdi_field ## _LBN :             \
4004                                        MC_CMD_FILTER_OP_EXT_IN_MATCH_ ##\
4005                                        mcdi_field ## _LBN));            \
4006         }
4007         /* inner or outer based on encap type */
4008         MAP_FILTER_TO_MCDI_FLAG(REM_HOST, SRC_IP, encap_type);
4009         MAP_FILTER_TO_MCDI_FLAG(LOC_HOST, DST_IP, encap_type);
4010         MAP_FILTER_TO_MCDI_FLAG(REM_MAC, SRC_MAC, encap_type);
4011         MAP_FILTER_TO_MCDI_FLAG(REM_PORT, SRC_PORT, encap_type);
4012         MAP_FILTER_TO_MCDI_FLAG(LOC_MAC, DST_MAC, encap_type);
4013         MAP_FILTER_TO_MCDI_FLAG(LOC_PORT, DST_PORT, encap_type);
4014         MAP_FILTER_TO_MCDI_FLAG(ETHER_TYPE, ETHER_TYPE, encap_type);
4015         MAP_FILTER_TO_MCDI_FLAG(IP_PROTO, IP_PROTO, encap_type);
4016         /* always outer */
4017         MAP_FILTER_TO_MCDI_FLAG(INNER_VID, INNER_VLAN, false);
4018         MAP_FILTER_TO_MCDI_FLAG(OUTER_VID, OUTER_VLAN, false);
4019 #undef MAP_FILTER_TO_MCDI_FLAG
4020
4021         /* special handling for encap type, and mismatch */
4022         if (encap_type) {
4023                 match_flags &= ~EFX_FILTER_MATCH_ENCAP_TYPE;
4024                 mcdi_flags |=
4025                         (1 << MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_LBN);
4026                 mcdi_flags |= (1 << MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_LBN);
4027
4028                 uc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_LBN;
4029                 mc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_LBN;
4030         } else {
4031                 uc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_LBN;
4032                 mc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_LBN;
4033         }
4034
4035         if (match_flags & EFX_FILTER_MATCH_LOC_MAC_IG) {
4036                 match_flags &= ~EFX_FILTER_MATCH_LOC_MAC_IG;
4037                 mcdi_flags |=
4038                         is_multicast_ether_addr(spec->loc_mac) ?
4039                         1 << mc_match :
4040                         1 << uc_match;
4041         }
4042
4043         /* Did we map them all? */
4044         WARN_ON_ONCE(match_flags);
4045
4046         return mcdi_flags;
4047 }
4048
4049 static int efx_ef10_filter_pri(struct efx_ef10_filter_table *table,
4050                                const struct efx_filter_spec *spec)
4051 {
4052         u32 mcdi_flags = efx_ef10_filter_mcdi_flags_from_spec(spec);
4053         unsigned int match_pri;
4054
4055         for (match_pri = 0;
4056              match_pri < table->rx_match_count;
4057              match_pri++)
4058                 if (table->rx_match_mcdi_flags[match_pri] == mcdi_flags)
4059                         return match_pri;
4060
4061         return -EPROTONOSUPPORT;
4062 }
4063
4064 static s32 efx_ef10_filter_insert(struct efx_nic *efx,
4065                                   struct efx_filter_spec *spec,
4066                                   bool replace_equal)
4067 {
4068         struct efx_ef10_filter_table *table = efx->filter_state;
4069         DECLARE_BITMAP(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
4070         struct efx_filter_spec *saved_spec;
4071         unsigned int match_pri, hash;
4072         unsigned int priv_flags;
4073         bool replacing = false;
4074         int ins_index = -1;
4075         DEFINE_WAIT(wait);
4076         bool is_mc_recip;
4077         s32 rc;
4078
4079         /* For now, only support RX filters */
4080         if ((spec->flags & (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)) !=
4081             EFX_FILTER_FLAG_RX)
4082                 return -EINVAL;
4083
4084         rc = efx_ef10_filter_pri(table, spec);
4085         if (rc < 0)
4086                 return rc;
4087         match_pri = rc;
4088
4089         hash = efx_ef10_filter_hash(spec);
4090         is_mc_recip = efx_filter_is_mc_recipient(spec);
4091         if (is_mc_recip)
4092                 bitmap_zero(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
4093
4094         /* Find any existing filters with the same match tuple or
4095          * else a free slot to insert at.  If any of them are busy,
4096          * we have to wait and retry.
4097          */
4098         for (;;) {
4099                 unsigned int depth = 1;
4100                 unsigned int i;
4101
4102                 spin_lock_bh(&efx->filter_lock);
4103
4104                 for (;;) {
4105                         i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
4106                         saved_spec = efx_ef10_filter_entry_spec(table, i);
4107
4108                         if (!saved_spec) {
4109                                 if (ins_index < 0)
4110                                         ins_index = i;
4111                         } else if (efx_ef10_filter_equal(spec, saved_spec)) {
4112                                 if (table->entry[i].spec &
4113                                     EFX_EF10_FILTER_FLAG_BUSY)
4114                                         break;
4115                                 if (spec->priority < saved_spec->priority &&
4116                                     spec->priority != EFX_FILTER_PRI_AUTO) {
4117                                         rc = -EPERM;
4118                                         goto out_unlock;
4119                                 }
4120                                 if (!is_mc_recip) {
4121                                         /* This is the only one */
4122                                         if (spec->priority ==
4123                                             saved_spec->priority &&
4124                                             !replace_equal) {
4125                                                 rc = -EEXIST;
4126                                                 goto out_unlock;
4127                                         }
4128                                         ins_index = i;
4129                                         goto found;
4130                                 } else if (spec->priority >
4131                                            saved_spec->priority ||
4132                                            (spec->priority ==
4133                                             saved_spec->priority &&
4134                                             replace_equal)) {
4135                                         if (ins_index < 0)
4136                                                 ins_index = i;
4137                                         else
4138                                                 __set_bit(depth, mc_rem_map);
4139                                 }
4140                         }
4141
4142                         /* Once we reach the maximum search depth, use
4143                          * the first suitable slot or return -EBUSY if
4144                          * there was none
4145                          */
4146                         if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
4147                                 if (ins_index < 0) {
4148                                         rc = -EBUSY;
4149                                         goto out_unlock;
4150                                 }
4151                                 goto found;
4152                         }
4153
4154                         ++depth;
4155                 }
4156
4157                 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
4158                 spin_unlock_bh(&efx->filter_lock);
4159                 schedule();
4160         }
4161
4162 found:
4163         /* Create a software table entry if necessary, and mark it
4164          * busy.  We might yet fail to insert, but any attempt to
4165          * insert a conflicting filter while we're waiting for the
4166          * firmware must find the busy entry.
4167          */
4168         saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
4169         if (saved_spec) {
4170                 if (spec->priority == EFX_FILTER_PRI_AUTO &&
4171                     saved_spec->priority >= EFX_FILTER_PRI_AUTO) {
4172                         /* Just make sure it won't be removed */
4173                         if (saved_spec->priority > EFX_FILTER_PRI_AUTO)
4174                                 saved_spec->flags |= EFX_FILTER_FLAG_RX_OVER_AUTO;
4175                         table->entry[ins_index].spec &=
4176                                 ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
4177                         rc = ins_index;
4178                         goto out_unlock;
4179                 }
4180                 replacing = true;
4181                 priv_flags = efx_ef10_filter_entry_flags(table, ins_index);
4182         } else {
4183                 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
4184                 if (!saved_spec) {
4185                         rc = -ENOMEM;
4186                         goto out_unlock;
4187                 }
4188                 *saved_spec = *spec;
4189                 priv_flags = 0;
4190         }
4191         efx_ef10_filter_set_entry(table, ins_index, saved_spec,
4192                                   priv_flags | EFX_EF10_FILTER_FLAG_BUSY);
4193
4194         /* Mark lower-priority multicast recipients busy prior to removal */
4195         if (is_mc_recip) {
4196                 unsigned int depth, i;
4197
4198                 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
4199                         i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
4200                         if (test_bit(depth, mc_rem_map))
4201                                 table->entry[i].spec |=
4202                                         EFX_EF10_FILTER_FLAG_BUSY;
4203                 }
4204         }
4205
4206         spin_unlock_bh(&efx->filter_lock);
4207
4208         rc = efx_ef10_filter_push(efx, spec, &table->entry[ins_index].handle,
4209                                   replacing);
4210
4211         /* Finalise the software table entry */
4212         spin_lock_bh(&efx->filter_lock);
4213         if (rc == 0) {
4214                 if (replacing) {
4215                         /* Update the fields that may differ */
4216                         if (saved_spec->priority == EFX_FILTER_PRI_AUTO)
4217                                 saved_spec->flags |=
4218                                         EFX_FILTER_FLAG_RX_OVER_AUTO;
4219                         saved_spec->priority = spec->priority;
4220                         saved_spec->flags &= EFX_FILTER_FLAG_RX_OVER_AUTO;
4221                         saved_spec->flags |= spec->flags;
4222                         saved_spec->rss_context = spec->rss_context;
4223                         saved_spec->dmaq_id = spec->dmaq_id;
4224                 }
4225         } else if (!replacing) {
4226                 kfree(saved_spec);
4227                 saved_spec = NULL;
4228         }
4229         efx_ef10_filter_set_entry(table, ins_index, saved_spec, priv_flags);
4230
4231         /* Remove and finalise entries for lower-priority multicast
4232          * recipients
4233          */
4234         if (is_mc_recip) {
4235                 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_EXT_IN_LEN);
4236                 unsigned int depth, i;
4237
4238                 memset(inbuf, 0, sizeof(inbuf));
4239
4240                 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
4241                         if (!test_bit(depth, mc_rem_map))
4242                                 continue;
4243
4244                         i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
4245                         saved_spec = efx_ef10_filter_entry_spec(table, i);
4246                         priv_flags = efx_ef10_filter_entry_flags(table, i);
4247
4248                         if (rc == 0) {
4249                                 spin_unlock_bh(&efx->filter_lock);
4250                                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
4251                                                MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
4252                                 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
4253                                                table->entry[i].handle);
4254                                 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
4255                                                   inbuf, sizeof(inbuf),
4256                                                   NULL, 0, NULL);
4257                                 spin_lock_bh(&efx->filter_lock);
4258                         }
4259
4260                         if (rc == 0) {
4261                                 kfree(saved_spec);
4262                                 saved_spec = NULL;
4263                                 priv_flags = 0;
4264                         } else {
4265                                 priv_flags &= ~EFX_EF10_FILTER_FLAG_BUSY;
4266                         }
4267                         efx_ef10_filter_set_entry(table, i, saved_spec,
4268                                                   priv_flags);
4269                 }
4270         }
4271
4272         /* If successful, return the inserted filter ID */
4273         if (rc == 0)
4274                 rc = efx_ef10_make_filter_id(match_pri, ins_index);
4275
4276         wake_up_all(&table->waitq);
4277 out_unlock:
4278         spin_unlock_bh(&efx->filter_lock);
4279         finish_wait(&table->waitq, &wait);
4280         return rc;
4281 }
4282
4283 static void efx_ef10_filter_update_rx_scatter(struct efx_nic *efx)
4284 {
4285         /* no need to do anything here on EF10 */
4286 }
4287
4288 /* Remove a filter.
4289  * If !by_index, remove by ID
4290  * If by_index, remove by index
4291  * Filter ID may come from userland and must be range-checked.
4292  */
4293 static int efx_ef10_filter_remove_internal(struct efx_nic *efx,
4294                                            unsigned int priority_mask,
4295                                            u32 filter_id, bool by_index)
4296 {
4297         unsigned int filter_idx = efx_ef10_filter_get_unsafe_id(filter_id);
4298         struct efx_ef10_filter_table *table = efx->filter_state;
4299         MCDI_DECLARE_BUF(inbuf,
4300                          MC_CMD_FILTER_OP_IN_HANDLE_OFST +
4301                          MC_CMD_FILTER_OP_IN_HANDLE_LEN);
4302         struct efx_filter_spec *spec;
4303         DEFINE_WAIT(wait);
4304         int rc;
4305
4306         /* Find the software table entry and mark it busy.  Don't
4307          * remove it yet; any attempt to update while we're waiting
4308          * for the firmware must find the busy entry.
4309          */
4310         for (;;) {
4311                 spin_lock_bh(&efx->filter_lock);
4312                 if (!(table->entry[filter_idx].spec &
4313                       EFX_EF10_FILTER_FLAG_BUSY))
4314                         break;
4315                 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
4316                 spin_unlock_bh(&efx->filter_lock);
4317                 schedule();
4318         }
4319
4320         spec = efx_ef10_filter_entry_spec(table, filter_idx);
4321         if (!spec ||
4322             (!by_index &&
4323              efx_ef10_filter_pri(table, spec) !=
4324              efx_ef10_filter_get_unsafe_pri(filter_id))) {
4325                 rc = -ENOENT;
4326                 goto out_unlock;
4327         }
4328
4329         if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO &&
4330             priority_mask == (1U << EFX_FILTER_PRI_AUTO)) {
4331                 /* Just remove flags */
4332                 spec->flags &= ~EFX_FILTER_FLAG_RX_OVER_AUTO;
4333                 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
4334                 rc = 0;
4335                 goto out_unlock;
4336         }
4337
4338         if (!(priority_mask & (1U << spec->priority))) {
4339                 rc = -ENOENT;
4340                 goto out_unlock;
4341         }
4342
4343         table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
4344         spin_unlock_bh(&efx->filter_lock);
4345
4346         if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO) {
4347                 /* Reset to an automatic filter */
4348
4349                 struct efx_filter_spec new_spec = *spec;
4350
4351                 new_spec.priority = EFX_FILTER_PRI_AUTO;
4352                 new_spec.flags = (EFX_FILTER_FLAG_RX |
4353                                   (efx_rss_enabled(efx) ?
4354                                    EFX_FILTER_FLAG_RX_RSS : 0));
4355                 new_spec.dmaq_id = 0;
4356                 new_spec.rss_context = EFX_FILTER_RSS_CONTEXT_DEFAULT;
4357                 rc = efx_ef10_filter_push(efx, &new_spec,
4358                                           &table->entry[filter_idx].handle,
4359                                           true);
4360
4361                 spin_lock_bh(&efx->filter_lock);
4362                 if (rc == 0)
4363                         *spec = new_spec;
4364         } else {
4365                 /* Really remove the filter */
4366
4367                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
4368                                efx_ef10_filter_is_exclusive(spec) ?
4369                                MC_CMD_FILTER_OP_IN_OP_REMOVE :
4370                                MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
4371                 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
4372                                table->entry[filter_idx].handle);
4373                 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FILTER_OP,
4374                                         inbuf, sizeof(inbuf), NULL, 0, NULL);
4375
4376                 spin_lock_bh(&efx->filter_lock);
4377                 if ((rc == 0) || (rc == -ENOENT)) {
4378                         /* Filter removed OK or didn't actually exist */
4379                         kfree(spec);
4380                         efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
4381                 } else {
4382                         efx_mcdi_display_error(efx, MC_CMD_FILTER_OP,
4383                                                MC_CMD_FILTER_OP_EXT_IN_LEN,
4384                                                NULL, 0, rc);
4385                 }
4386         }
4387
4388         table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
4389         wake_up_all(&table->waitq);
4390 out_unlock:
4391         spin_unlock_bh(&efx->filter_lock);
4392         finish_wait(&table->waitq, &wait);
4393         return rc;
4394 }
4395
4396 static int efx_ef10_filter_remove_safe(struct efx_nic *efx,
4397                                        enum efx_filter_priority priority,
4398                                        u32 filter_id)
4399 {
4400         return efx_ef10_filter_remove_internal(efx, 1U << priority,
4401                                                filter_id, false);
4402 }
4403
4404 static void efx_ef10_filter_remove_unsafe(struct efx_nic *efx,
4405                                           enum efx_filter_priority priority,
4406                                           u32 filter_id)
4407 {
4408         if (filter_id == EFX_EF10_FILTER_ID_INVALID)
4409                 return;
4410         efx_ef10_filter_remove_internal(efx, 1U << priority, filter_id, true);
4411 }
4412
4413 static int efx_ef10_filter_get_safe(struct efx_nic *efx,
4414                                     enum efx_filter_priority priority,
4415                                     u32 filter_id, struct efx_filter_spec *spec)
4416 {
4417         unsigned int filter_idx = efx_ef10_filter_get_unsafe_id(filter_id);
4418         struct efx_ef10_filter_table *table = efx->filter_state;
4419         const struct efx_filter_spec *saved_spec;
4420         int rc;
4421
4422         spin_lock_bh(&efx->filter_lock);
4423         saved_spec = efx_ef10_filter_entry_spec(table, filter_idx);
4424         if (saved_spec && saved_spec->priority == priority &&
4425             efx_ef10_filter_pri(table, saved_spec) ==
4426             efx_ef10_filter_get_unsafe_pri(filter_id)) {
4427                 *spec = *saved_spec;
4428                 rc = 0;
4429         } else {
4430                 rc = -ENOENT;
4431         }
4432         spin_unlock_bh(&efx->filter_lock);
4433         return rc;
4434 }
4435
4436 static int efx_ef10_filter_clear_rx(struct efx_nic *efx,
4437                                      enum efx_filter_priority priority)
4438 {
4439         unsigned int priority_mask;
4440         unsigned int i;
4441         int rc;
4442
4443         priority_mask = (((1U << (priority + 1)) - 1) &
4444                          ~(1U << EFX_FILTER_PRI_AUTO));
4445
4446         for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
4447                 rc = efx_ef10_filter_remove_internal(efx, priority_mask,
4448                                                      i, true);
4449                 if (rc && rc != -ENOENT)
4450                         return rc;
4451         }
4452
4453         return 0;
4454 }
4455
4456 static u32 efx_ef10_filter_count_rx_used(struct efx_nic *efx,
4457                                          enum efx_filter_priority priority)
4458 {
4459         struct efx_ef10_filter_table *table = efx->filter_state;
4460         unsigned int filter_idx;
4461         s32 count = 0;
4462
4463         spin_lock_bh(&efx->filter_lock);
4464         for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
4465                 if (table->entry[filter_idx].spec &&
4466                     efx_ef10_filter_entry_spec(table, filter_idx)->priority ==
4467                     priority)
4468                         ++count;
4469         }
4470         spin_unlock_bh(&efx->filter_lock);
4471         return count;
4472 }
4473
4474 static u32 efx_ef10_filter_get_rx_id_limit(struct efx_nic *efx)
4475 {
4476         struct efx_ef10_filter_table *table = efx->filter_state;
4477
4478         return table->rx_match_count * HUNT_FILTER_TBL_ROWS * 2;
4479 }
4480
4481 static s32 efx_ef10_filter_get_rx_ids(struct efx_nic *efx,
4482                                       enum efx_filter_priority priority,
4483                                       u32 *buf, u32 size)
4484 {
4485         struct efx_ef10_filter_table *table = efx->filter_state;
4486         struct efx_filter_spec *spec;
4487         unsigned int filter_idx;
4488         s32 count = 0;
4489
4490         spin_lock_bh(&efx->filter_lock);
4491         for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
4492                 spec = efx_ef10_filter_entry_spec(table, filter_idx);
4493                 if (spec && spec->priority == priority) {
4494                         if (count == size) {
4495                                 count = -EMSGSIZE;
4496                                 break;
4497                         }
4498                         buf[count++] =
4499                                 efx_ef10_make_filter_id(
4500                                         efx_ef10_filter_pri(table, spec),
4501                                         filter_idx);
4502                 }
4503         }
4504         spin_unlock_bh(&efx->filter_lock);
4505         return count;
4506 }
4507
4508 #ifdef CONFIG_RFS_ACCEL
4509
4510 static efx_mcdi_async_completer efx_ef10_filter_rfs_insert_complete;
4511
4512 static s32 efx_ef10_filter_rfs_insert(struct efx_nic *efx,
4513                                       struct efx_filter_spec *spec)
4514 {
4515         struct efx_ef10_filter_table *table = efx->filter_state;
4516         MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_EXT_IN_LEN);
4517         struct efx_filter_spec *saved_spec;
4518         unsigned int hash, i, depth = 1;
4519         bool replacing = false;
4520         int ins_index = -1;
4521         u64 cookie;
4522         s32 rc;
4523
4524         /* Must be an RX filter without RSS and not for a multicast
4525          * destination address (RFS only works for connected sockets).
4526          * These restrictions allow us to pass only a tiny amount of
4527          * data through to the completion function.
4528          */
4529         EFX_WARN_ON_PARANOID(spec->flags !=
4530                              (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_RX_SCATTER));
4531         EFX_WARN_ON_PARANOID(spec->priority != EFX_FILTER_PRI_HINT);
4532         EFX_WARN_ON_PARANOID(efx_filter_is_mc_recipient(spec));
4533
4534         hash = efx_ef10_filter_hash(spec);
4535
4536         spin_lock_bh(&efx->filter_lock);
4537
4538         /* Find any existing filter with the same match tuple or else
4539          * a free slot to insert at.  If an existing filter is busy,
4540          * we have to give up.
4541          */
4542         for (;;) {
4543                 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
4544                 saved_spec = efx_ef10_filter_entry_spec(table, i);
4545
4546                 if (!saved_spec) {
4547                         if (ins_index < 0)
4548                                 ins_index = i;
4549                 } else if (efx_ef10_filter_equal(spec, saved_spec)) {
4550                         if (table->entry[i].spec & EFX_EF10_FILTER_FLAG_BUSY) {
4551                                 rc = -EBUSY;
4552                                 goto fail_unlock;
4553                         }
4554                         if (spec->priority < saved_spec->priority) {
4555                                 rc = -EPERM;
4556                                 goto fail_unlock;
4557                         }
4558                         ins_index = i;
4559                         break;
4560                 }
4561
4562                 /* Once we reach the maximum search depth, use the
4563                  * first suitable slot or return -EBUSY if there was
4564                  * none
4565                  */
4566                 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
4567                         if (ins_index < 0) {
4568                                 rc = -EBUSY;
4569                                 goto fail_unlock;
4570                         }
4571                         break;
4572                 }
4573
4574                 ++depth;
4575         }
4576
4577         /* Create a software table entry if necessary, and mark it
4578          * busy.  We might yet fail to insert, but any attempt to
4579          * insert a conflicting filter while we're waiting for the
4580          * firmware must find the busy entry.
4581          */
4582         saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
4583         if (saved_spec) {
4584                 replacing = true;
4585         } else {
4586                 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
4587                 if (!saved_spec) {
4588                         rc = -ENOMEM;
4589                         goto fail_unlock;
4590                 }
4591                 *saved_spec = *spec;
4592         }
4593         efx_ef10_filter_set_entry(table, ins_index, saved_spec,
4594                                   EFX_EF10_FILTER_FLAG_BUSY);
4595
4596         spin_unlock_bh(&efx->filter_lock);
4597
4598         /* Pack up the variables needed on completion */
4599         cookie = replacing << 31 | ins_index << 16 | spec->dmaq_id;
4600
4601         efx_ef10_filter_push_prep(efx, spec, inbuf,
4602                                   table->entry[ins_index].handle, replacing);
4603         efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
4604                            MC_CMD_FILTER_OP_OUT_LEN,
4605                            efx_ef10_filter_rfs_insert_complete, cookie);
4606
4607         return ins_index;
4608
4609 fail_unlock:
4610         spin_unlock_bh(&efx->filter_lock);
4611         return rc;
4612 }
4613
4614 static void
4615 efx_ef10_filter_rfs_insert_complete(struct efx_nic *efx, unsigned long cookie,
4616                                     int rc, efx_dword_t *outbuf,
4617                                     size_t outlen_actual)
4618 {
4619         struct efx_ef10_filter_table *table = efx->filter_state;
4620         unsigned int ins_index, dmaq_id;
4621         struct efx_filter_spec *spec;
4622         bool replacing;
4623
4624         /* Unpack the cookie */
4625         replacing = cookie >> 31;
4626         ins_index = (cookie >> 16) & (HUNT_FILTER_TBL_ROWS - 1);
4627         dmaq_id = cookie & 0xffff;
4628
4629         spin_lock_bh(&efx->filter_lock);
4630         spec = efx_ef10_filter_entry_spec(table, ins_index);
4631         if (rc == 0) {
4632                 table->entry[ins_index].handle =
4633                         MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
4634                 if (replacing)
4635                         spec->dmaq_id = dmaq_id;
4636         } else if (!replacing) {
4637                 kfree(spec);
4638                 spec = NULL;
4639         }
4640         efx_ef10_filter_set_entry(table, ins_index, spec, 0);
4641         spin_unlock_bh(&efx->filter_lock);
4642
4643         wake_up_all(&table->waitq);
4644 }
4645
4646 static void
4647 efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
4648                                     unsigned long filter_idx,
4649                                     int rc, efx_dword_t *outbuf,
4650                                     size_t outlen_actual);
4651
4652 static bool efx_ef10_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id,
4653                                            unsigned int filter_idx)
4654 {
4655         struct efx_ef10_filter_table *table = efx->filter_state;
4656         struct efx_filter_spec *spec =
4657                 efx_ef10_filter_entry_spec(table, filter_idx);
4658         MCDI_DECLARE_BUF(inbuf,
4659                          MC_CMD_FILTER_OP_IN_HANDLE_OFST +
4660                          MC_CMD_FILTER_OP_IN_HANDLE_LEN);
4661
4662         if (!spec ||
4663             (table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAG_BUSY) ||
4664             spec->priority != EFX_FILTER_PRI_HINT ||
4665             !rps_may_expire_flow(efx->net_dev, spec->dmaq_id,
4666                                  flow_id, filter_idx))
4667                 return false;
4668
4669         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
4670                        MC_CMD_FILTER_OP_IN_OP_REMOVE);
4671         MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
4672                        table->entry[filter_idx].handle);
4673         if (efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), 0,
4674                                efx_ef10_filter_rfs_expire_complete, filter_idx))
4675                 return false;
4676
4677         table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
4678         return true;
4679 }
4680
4681 static void
4682 efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
4683                                     unsigned long filter_idx,
4684                                     int rc, efx_dword_t *outbuf,
4685                                     size_t outlen_actual)
4686 {
4687         struct efx_ef10_filter_table *table = efx->filter_state;
4688         struct efx_filter_spec *spec =
4689                 efx_ef10_filter_entry_spec(table, filter_idx);
4690
4691         spin_lock_bh(&efx->filter_lock);
4692         if (rc == 0) {
4693                 kfree(spec);
4694                 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
4695         }
4696         table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
4697         wake_up_all(&table->waitq);
4698         spin_unlock_bh(&efx->filter_lock);
4699 }
4700
4701 #endif /* CONFIG_RFS_ACCEL */
4702
4703 static int efx_ef10_filter_match_flags_from_mcdi(bool encap, u32 mcdi_flags)
4704 {
4705         int match_flags = 0;
4706
4707 #define MAP_FLAG(gen_flag, mcdi_field) do {                             \
4708                 u32 old_mcdi_flags = mcdi_flags;                        \
4709                 mcdi_flags &= ~(1 << MC_CMD_FILTER_OP_EXT_IN_MATCH_ ##  \
4710                                      mcdi_field ## _LBN);               \
4711                 if (mcdi_flags != old_mcdi_flags)                       \
4712                         match_flags |= EFX_FILTER_MATCH_ ## gen_flag;   \
4713         } while (0)
4714
4715         if (encap) {
4716                 /* encap filters must specify encap type */
4717                 match_flags |= EFX_FILTER_MATCH_ENCAP_TYPE;
4718                 /* and imply ethertype and ip proto */
4719                 mcdi_flags &=
4720                         ~(1 << MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_LBN);
4721                 mcdi_flags &=
4722                         ~(1 << MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_LBN);
4723                 /* VLAN tags refer to the outer packet */
4724                 MAP_FLAG(INNER_VID, INNER_VLAN);
4725                 MAP_FLAG(OUTER_VID, OUTER_VLAN);
4726                 /* everything else refers to the inner packet */
4727                 MAP_FLAG(LOC_MAC_IG, IFRM_UNKNOWN_UCAST_DST);
4728                 MAP_FLAG(LOC_MAC_IG, IFRM_UNKNOWN_MCAST_DST);
4729                 MAP_FLAG(REM_HOST, IFRM_SRC_IP);
4730                 MAP_FLAG(LOC_HOST, IFRM_DST_IP);
4731                 MAP_FLAG(REM_MAC, IFRM_SRC_MAC);
4732                 MAP_FLAG(REM_PORT, IFRM_SRC_PORT);
4733                 MAP_FLAG(LOC_MAC, IFRM_DST_MAC);
4734                 MAP_FLAG(LOC_PORT, IFRM_DST_PORT);
4735                 MAP_FLAG(ETHER_TYPE, IFRM_ETHER_TYPE);
4736                 MAP_FLAG(IP_PROTO, IFRM_IP_PROTO);
4737         } else {
4738                 MAP_FLAG(LOC_MAC_IG, UNKNOWN_UCAST_DST);
4739                 MAP_FLAG(LOC_MAC_IG, UNKNOWN_MCAST_DST);
4740                 MAP_FLAG(REM_HOST, SRC_IP);
4741                 MAP_FLAG(LOC_HOST, DST_IP);
4742                 MAP_FLAG(REM_MAC, SRC_MAC);
4743                 MAP_FLAG(REM_PORT, SRC_PORT);
4744                 MAP_FLAG(LOC_MAC, DST_MAC);
4745                 MAP_FLAG(LOC_PORT, DST_PORT);
4746                 MAP_FLAG(ETHER_TYPE, ETHER_TYPE);
4747                 MAP_FLAG(INNER_VID, INNER_VLAN);
4748                 MAP_FLAG(OUTER_VID, OUTER_VLAN);
4749                 MAP_FLAG(IP_PROTO, IP_PROTO);
4750         }
4751 #undef MAP_FLAG
4752
4753         /* Did we map them all? */
4754         if (mcdi_flags)
4755                 return -EINVAL;
4756
4757         return match_flags;
4758 }
4759
4760 static void efx_ef10_filter_cleanup_vlans(struct efx_nic *efx)
4761 {
4762         struct efx_ef10_filter_table *table = efx->filter_state;
4763         struct efx_ef10_filter_vlan *vlan, *next_vlan;
4764
4765         /* See comment in efx_ef10_filter_table_remove() */
4766         if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
4767                 return;
4768
4769         if (!table)
4770                 return;
4771
4772         list_for_each_entry_safe(vlan, next_vlan, &table->vlan_list, list)
4773                 efx_ef10_filter_del_vlan_internal(efx, vlan);
4774 }
4775
4776 static bool efx_ef10_filter_match_supported(struct efx_ef10_filter_table *table,
4777                                             bool encap,
4778                                             enum efx_filter_match_flags match_flags)
4779 {
4780         unsigned int match_pri;
4781         int mf;
4782
4783         for (match_pri = 0;
4784              match_pri < table->rx_match_count;
4785              match_pri++) {
4786                 mf = efx_ef10_filter_match_flags_from_mcdi(encap,
4787                                 table->rx_match_mcdi_flags[match_pri]);
4788                 if (mf == match_flags)
4789                         return true;
4790         }
4791
4792         return false;
4793 }
4794
4795 static int
4796 efx_ef10_filter_table_probe_matches(struct efx_nic *efx,
4797                                     struct efx_ef10_filter_table *table,
4798                                     bool encap)
4799 {
4800         MCDI_DECLARE_BUF(inbuf, MC_CMD_GET_PARSER_DISP_INFO_IN_LEN);
4801         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX);
4802         unsigned int pd_match_pri, pd_match_count;
4803         size_t outlen;
4804         int rc;
4805
4806         /* Find out which RX filter types are supported, and their priorities */
4807         MCDI_SET_DWORD(inbuf, GET_PARSER_DISP_INFO_IN_OP,
4808                        encap ?
4809                        MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_ENCAP_RX_MATCHES :
4810                        MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES);
4811         rc = efx_mcdi_rpc(efx, MC_CMD_GET_PARSER_DISP_INFO,
4812                           inbuf, sizeof(inbuf), outbuf, sizeof(outbuf),
4813                           &outlen);
4814         if (rc)
4815                 return rc;
4816
4817         pd_match_count = MCDI_VAR_ARRAY_LEN(
4818                 outlen, GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES);
4819
4820         for (pd_match_pri = 0; pd_match_pri < pd_match_count; pd_match_pri++) {
4821                 u32 mcdi_flags =
4822                         MCDI_ARRAY_DWORD(
4823                                 outbuf,
4824                                 GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES,
4825                                 pd_match_pri);
4826                 rc = efx_ef10_filter_match_flags_from_mcdi(encap, mcdi_flags);
4827                 if (rc < 0) {
4828                         netif_dbg(efx, probe, efx->net_dev,
4829                                   "%s: fw flags %#x pri %u not supported in driver\n",
4830                                   __func__, mcdi_flags, pd_match_pri);
4831                 } else {
4832                         netif_dbg(efx, probe, efx->net_dev,
4833                                   "%s: fw flags %#x pri %u supported as driver flags %#x pri %u\n",
4834                                   __func__, mcdi_flags, pd_match_pri,
4835                                   rc, table->rx_match_count);
4836                         table->rx_match_mcdi_flags[table->rx_match_count] = mcdi_flags;
4837                         table->rx_match_count++;
4838                 }
4839         }
4840
4841         return 0;
4842 }
4843
4844 static int efx_ef10_filter_table_probe(struct efx_nic *efx)
4845 {
4846         struct efx_ef10_nic_data *nic_data = efx->nic_data;
4847         struct net_device *net_dev = efx->net_dev;
4848         struct efx_ef10_filter_table *table;
4849         struct efx_ef10_vlan *vlan;
4850         int rc;
4851
4852         if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
4853                 return -EINVAL;
4854
4855         if (efx->filter_state) /* already probed */
4856                 return 0;
4857
4858         table = kzalloc(sizeof(*table), GFP_KERNEL);
4859         if (!table)
4860                 return -ENOMEM;
4861
4862         table->rx_match_count = 0;
4863         rc = efx_ef10_filter_table_probe_matches(efx, table, false);
4864         if (rc)
4865                 goto fail;
4866         if (nic_data->datapath_caps &
4867                    (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN))
4868                 rc = efx_ef10_filter_table_probe_matches(efx, table, true);
4869         if (rc)
4870                 goto fail;
4871         if ((efx_supported_features(efx) & NETIF_F_HW_VLAN_CTAG_FILTER) &&
4872             !(efx_ef10_filter_match_supported(table, false,
4873                 (EFX_FILTER_MATCH_OUTER_VID | EFX_FILTER_MATCH_LOC_MAC)) &&
4874               efx_ef10_filter_match_supported(table, false,
4875                 (EFX_FILTER_MATCH_OUTER_VID | EFX_FILTER_MATCH_LOC_MAC_IG)))) {
4876                 netif_info(efx, probe, net_dev,
4877                            "VLAN filters are not supported in this firmware variant\n");
4878                 net_dev->features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
4879                 efx->fixed_features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
4880                 net_dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
4881         }
4882
4883         table->entry = vzalloc(HUNT_FILTER_TBL_ROWS * sizeof(*table->entry));
4884         if (!table->entry) {
4885                 rc = -ENOMEM;
4886                 goto fail;
4887         }
4888
4889         table->mc_promisc_last = false;
4890         table->vlan_filter =
4891                 !!(efx->net_dev->features & NETIF_F_HW_VLAN_CTAG_FILTER);
4892         INIT_LIST_HEAD(&table->vlan_list);
4893
4894         efx->filter_state = table;
4895         init_waitqueue_head(&table->waitq);
4896
4897         list_for_each_entry(vlan, &nic_data->vlan_list, list) {
4898                 rc = efx_ef10_filter_add_vlan(efx, vlan->vid);
4899                 if (rc)
4900                         goto fail_add_vlan;
4901         }
4902
4903         return 0;
4904
4905 fail_add_vlan:
4906         efx_ef10_filter_cleanup_vlans(efx);
4907         efx->filter_state = NULL;
4908 fail:
4909         kfree(table);
4910         return rc;
4911 }
4912
4913 /* Caller must hold efx->filter_sem for read if race against
4914  * efx_ef10_filter_table_remove() is possible
4915  */
4916 static void efx_ef10_filter_table_restore(struct efx_nic *efx)
4917 {
4918         struct efx_ef10_filter_table *table = efx->filter_state;
4919         struct efx_ef10_nic_data *nic_data = efx->nic_data;
4920         unsigned int invalid_filters = 0, failed = 0;
4921         struct efx_ef10_filter_vlan *vlan;
4922         struct efx_filter_spec *spec;
4923         unsigned int filter_idx;
4924         u32 mcdi_flags;
4925         int match_pri;
4926         int rc, i;
4927
4928         WARN_ON(!rwsem_is_locked(&efx->filter_sem));
4929
4930         if (!nic_data->must_restore_filters)
4931                 return;
4932
4933         if (!table)
4934                 return;
4935
4936         spin_lock_bh(&efx->filter_lock);
4937
4938         for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
4939                 spec = efx_ef10_filter_entry_spec(table, filter_idx);
4940                 if (!spec)
4941                         continue;
4942
4943                 mcdi_flags = efx_ef10_filter_mcdi_flags_from_spec(spec);
4944                 match_pri = 0;
4945                 while (match_pri < table->rx_match_count &&
4946                        table->rx_match_mcdi_flags[match_pri] != mcdi_flags)
4947                         ++match_pri;
4948                 if (match_pri >= table->rx_match_count) {
4949                         invalid_filters++;
4950                         goto not_restored;
4951                 }
4952                 if (spec->rss_context != EFX_FILTER_RSS_CONTEXT_DEFAULT &&
4953                     spec->rss_context != nic_data->rx_rss_context)
4954                         netif_warn(efx, drv, efx->net_dev,
4955                                    "Warning: unable to restore a filter with specific RSS context.\n");
4956
4957                 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
4958                 spin_unlock_bh(&efx->filter_lock);
4959
4960                 rc = efx_ef10_filter_push(efx, spec,
4961                                           &table->entry[filter_idx].handle,
4962                                           false);
4963                 if (rc)
4964                         failed++;
4965                 spin_lock_bh(&efx->filter_lock);
4966
4967                 if (rc) {
4968 not_restored:
4969                         list_for_each_entry(vlan, &table->vlan_list, list)
4970                                 for (i = 0; i < EFX_EF10_NUM_DEFAULT_FILTERS; ++i)
4971                                         if (vlan->default_filters[i] == filter_idx)
4972                                                 vlan->default_filters[i] =
4973                                                         EFX_EF10_FILTER_ID_INVALID;
4974
4975                         kfree(spec);
4976                         efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
4977                 } else {
4978                         table->entry[filter_idx].spec &=
4979                                 ~EFX_EF10_FILTER_FLAG_BUSY;
4980                 }
4981         }
4982
4983         spin_unlock_bh(&efx->filter_lock);
4984
4985         /* This can happen validly if the MC's capabilities have changed, so
4986          * is not an error.
4987          */
4988         if (invalid_filters)
4989                 netif_dbg(efx, drv, efx->net_dev,
4990                           "Did not restore %u filters that are now unsupported.\n",
4991                           invalid_filters);
4992
4993         if (failed)
4994                 netif_err(efx, hw, efx->net_dev,
4995                           "unable to restore %u filters\n", failed);
4996         else
4997                 nic_data->must_restore_filters = false;
4998 }
4999
5000 static void efx_ef10_filter_table_remove(struct efx_nic *efx)
5001 {
5002         struct efx_ef10_filter_table *table = efx->filter_state;
5003         MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_EXT_IN_LEN);
5004         struct efx_filter_spec *spec;
5005         unsigned int filter_idx;
5006         int rc;
5007
5008         efx_ef10_filter_cleanup_vlans(efx);
5009         efx->filter_state = NULL;
5010         /* If we were called without locking, then it's not safe to free
5011          * the table as others might be using it.  So we just WARN, leak
5012          * the memory, and potentially get an inconsistent filter table
5013          * state.
5014          * This should never actually happen.
5015          */
5016         if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
5017                 return;
5018
5019         if (!table)
5020                 return;
5021
5022         for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
5023                 spec = efx_ef10_filter_entry_spec(table, filter_idx);
5024                 if (!spec)
5025                         continue;
5026
5027                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
5028                                efx_ef10_filter_is_exclusive(spec) ?
5029                                MC_CMD_FILTER_OP_IN_OP_REMOVE :
5030                                MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
5031                 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
5032                                table->entry[filter_idx].handle);
5033                 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FILTER_OP, inbuf,
5034                                         sizeof(inbuf), NULL, 0, NULL);
5035                 if (rc)
5036                         netif_info(efx, drv, efx->net_dev,
5037                                    "%s: filter %04x remove failed\n",
5038                                    __func__, filter_idx);
5039                 kfree(spec);
5040         }
5041
5042         vfree(table->entry);
5043         kfree(table);
5044 }
5045
5046 static void efx_ef10_filter_mark_one_old(struct efx_nic *efx, uint16_t *id)
5047 {
5048         struct efx_ef10_filter_table *table = efx->filter_state;
5049         unsigned int filter_idx;
5050
5051         if (*id != EFX_EF10_FILTER_ID_INVALID) {
5052                 filter_idx = efx_ef10_filter_get_unsafe_id(*id);
5053                 if (!table->entry[filter_idx].spec)
5054                         netif_dbg(efx, drv, efx->net_dev,
5055                                   "marked null spec old %04x:%04x\n", *id,
5056                                   filter_idx);
5057                 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_AUTO_OLD;
5058                 *id = EFX_EF10_FILTER_ID_INVALID;
5059         }
5060 }
5061
5062 /* Mark old per-VLAN filters that may need to be removed */
5063 static void _efx_ef10_filter_vlan_mark_old(struct efx_nic *efx,
5064                                            struct efx_ef10_filter_vlan *vlan)
5065 {
5066         struct efx_ef10_filter_table *table = efx->filter_state;
5067         unsigned int i;
5068
5069         for (i = 0; i < table->dev_uc_count; i++)
5070                 efx_ef10_filter_mark_one_old(efx, &vlan->uc[i]);
5071         for (i = 0; i < table->dev_mc_count; i++)
5072                 efx_ef10_filter_mark_one_old(efx, &vlan->mc[i]);
5073         for (i = 0; i < EFX_EF10_NUM_DEFAULT_FILTERS; i++)
5074                 efx_ef10_filter_mark_one_old(efx, &vlan->default_filters[i]);
5075 }
5076
5077 /* Mark old filters that may need to be removed.
5078  * Caller must hold efx->filter_sem for read if race against
5079  * efx_ef10_filter_table_remove() is possible
5080  */
5081 static void efx_ef10_filter_mark_old(struct efx_nic *efx)
5082 {
5083         struct efx_ef10_filter_table *table = efx->filter_state;
5084         struct efx_ef10_filter_vlan *vlan;
5085
5086         spin_lock_bh(&efx->filter_lock);
5087         list_for_each_entry(vlan, &table->vlan_list, list)
5088                 _efx_ef10_filter_vlan_mark_old(efx, vlan);
5089         spin_unlock_bh(&efx->filter_lock);
5090 }
5091
5092 static void efx_ef10_filter_uc_addr_list(struct efx_nic *efx)
5093 {
5094         struct efx_ef10_filter_table *table = efx->filter_state;
5095         struct net_device *net_dev = efx->net_dev;
5096         struct netdev_hw_addr *uc;
5097         unsigned int i;
5098
5099         table->uc_promisc = !!(net_dev->flags & IFF_PROMISC);
5100         ether_addr_copy(table->dev_uc_list[0].addr, net_dev->dev_addr);
5101         i = 1;
5102         netdev_for_each_uc_addr(uc, net_dev) {
5103                 if (i >= EFX_EF10_FILTER_DEV_UC_MAX) {
5104                         table->uc_promisc = true;
5105                         break;
5106                 }
5107                 ether_addr_copy(table->dev_uc_list[i].addr, uc->addr);
5108                 i++;
5109         }
5110
5111         table->dev_uc_count = i;
5112 }
5113
5114 static void efx_ef10_filter_mc_addr_list(struct efx_nic *efx)
5115 {
5116         struct efx_ef10_filter_table *table = efx->filter_state;
5117         struct net_device *net_dev = efx->net_dev;
5118         struct netdev_hw_addr *mc;
5119         unsigned int i;
5120
5121         table->mc_overflow = false;
5122         table->mc_promisc = !!(net_dev->flags & (IFF_PROMISC | IFF_ALLMULTI));
5123
5124         i = 0;
5125         netdev_for_each_mc_addr(mc, net_dev) {
5126                 if (i >= EFX_EF10_FILTER_DEV_MC_MAX) {
5127                         table->mc_promisc = true;
5128                         table->mc_overflow = true;
5129                         break;
5130                 }
5131                 ether_addr_copy(table->dev_mc_list[i].addr, mc->addr);
5132                 i++;
5133         }
5134
5135         table->dev_mc_count = i;
5136 }
5137
5138 static int efx_ef10_filter_insert_addr_list(struct efx_nic *efx,
5139                                             struct efx_ef10_filter_vlan *vlan,
5140                                             bool multicast, bool rollback)
5141 {
5142         struct efx_ef10_filter_table *table = efx->filter_state;
5143         struct efx_ef10_dev_addr *addr_list;
5144         enum efx_filter_flags filter_flags;
5145         struct efx_filter_spec spec;
5146         u8 baddr[ETH_ALEN];
5147         unsigned int i, j;
5148         int addr_count;
5149         u16 *ids;
5150         int rc;
5151
5152         if (multicast) {
5153                 addr_list = table->dev_mc_list;
5154                 addr_count = table->dev_mc_count;
5155                 ids = vlan->mc;
5156         } else {
5157                 addr_list = table->dev_uc_list;
5158                 addr_count = table->dev_uc_count;
5159                 ids = vlan->uc;
5160         }
5161
5162         filter_flags = efx_rss_enabled(efx) ? EFX_FILTER_FLAG_RX_RSS : 0;
5163
5164         /* Insert/renew filters */
5165         for (i = 0; i < addr_count; i++) {
5166                 EFX_WARN_ON_PARANOID(ids[i] != EFX_EF10_FILTER_ID_INVALID);
5167                 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0);
5168                 efx_filter_set_eth_local(&spec, vlan->vid, addr_list[i].addr);
5169                 rc = efx_ef10_filter_insert(efx, &spec, true);
5170                 if (rc < 0) {
5171                         if (rollback) {
5172                                 netif_info(efx, drv, efx->net_dev,
5173                                            "efx_ef10_filter_insert failed rc=%d\n",
5174                                            rc);
5175                                 /* Fall back to promiscuous */
5176                                 for (j = 0; j < i; j++) {
5177                                         efx_ef10_filter_remove_unsafe(
5178                                                 efx, EFX_FILTER_PRI_AUTO,
5179                                                 ids[j]);
5180                                         ids[j] = EFX_EF10_FILTER_ID_INVALID;
5181                                 }
5182                                 return rc;
5183                         } else {
5184                                 /* keep invalid ID, and carry on */
5185                         }
5186                 } else {
5187                         ids[i] = efx_ef10_filter_get_unsafe_id(rc);
5188                 }
5189         }
5190
5191         if (multicast && rollback) {
5192                 /* Also need an Ethernet broadcast filter */
5193                 EFX_WARN_ON_PARANOID(vlan->default_filters[EFX_EF10_BCAST] !=
5194                                      EFX_EF10_FILTER_ID_INVALID);
5195                 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0);
5196                 eth_broadcast_addr(baddr);
5197                 efx_filter_set_eth_local(&spec, vlan->vid, baddr);
5198                 rc = efx_ef10_filter_insert(efx, &spec, true);
5199                 if (rc < 0) {
5200                         netif_warn(efx, drv, efx->net_dev,
5201                                    "Broadcast filter insert failed rc=%d\n", rc);
5202                         /* Fall back to promiscuous */
5203                         for (j = 0; j < i; j++) {
5204                                 efx_ef10_filter_remove_unsafe(
5205                                         efx, EFX_FILTER_PRI_AUTO,
5206                                         ids[j]);
5207                                 ids[j] = EFX_EF10_FILTER_ID_INVALID;
5208                         }
5209                         return rc;
5210                 } else {
5211                         vlan->default_filters[EFX_EF10_BCAST] =
5212                                 efx_ef10_filter_get_unsafe_id(rc);
5213                 }
5214         }
5215
5216         return 0;
5217 }
5218
5219 static int efx_ef10_filter_insert_def(struct efx_nic *efx,
5220                                       struct efx_ef10_filter_vlan *vlan,
5221                                       enum efx_encap_type encap_type,
5222                                       bool multicast, bool rollback)
5223 {
5224         struct efx_ef10_nic_data *nic_data = efx->nic_data;
5225         enum efx_filter_flags filter_flags;
5226         struct efx_filter_spec spec;
5227         u8 baddr[ETH_ALEN];
5228         int rc;
5229         u16 *id;
5230
5231         filter_flags = efx_rss_enabled(efx) ? EFX_FILTER_FLAG_RX_RSS : 0;
5232
5233         efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0);
5234
5235         if (multicast)
5236                 efx_filter_set_mc_def(&spec);
5237         else
5238                 efx_filter_set_uc_def(&spec);
5239
5240         if (encap_type) {
5241                 if (nic_data->datapath_caps &
5242                     (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN))
5243                         efx_filter_set_encap_type(&spec, encap_type);
5244                 else
5245                         /* don't insert encap filters on non-supporting
5246                          * platforms. ID will be left as INVALID.
5247                          */
5248                         return 0;
5249         }
5250
5251         if (vlan->vid != EFX_FILTER_VID_UNSPEC)
5252                 efx_filter_set_eth_local(&spec, vlan->vid, NULL);
5253
5254         rc = efx_ef10_filter_insert(efx, &spec, true);
5255         if (rc < 0) {
5256                 const char *um = multicast ? "Multicast" : "Unicast";
5257                 const char *encap_name = "";
5258                 const char *encap_ipv = "";
5259
5260                 if ((encap_type & EFX_ENCAP_TYPES_MASK) ==
5261                     EFX_ENCAP_TYPE_VXLAN)
5262                         encap_name = "VXLAN ";
5263                 else if ((encap_type & EFX_ENCAP_TYPES_MASK) ==
5264                          EFX_ENCAP_TYPE_NVGRE)
5265                         encap_name = "NVGRE ";
5266                 else if ((encap_type & EFX_ENCAP_TYPES_MASK) ==
5267                          EFX_ENCAP_TYPE_GENEVE)
5268                         encap_name = "GENEVE ";
5269                 if (encap_type & EFX_ENCAP_FLAG_IPV6)
5270                         encap_ipv = "IPv6 ";
5271                 else if (encap_type)
5272                         encap_ipv = "IPv4 ";
5273
5274                 /* unprivileged functions can't insert mismatch filters
5275                  * for encapsulated or unicast traffic, so downgrade
5276                  * those warnings to debug.
5277                  */
5278                 netif_cond_dbg(efx, drv, efx->net_dev,
5279                                rc == -EPERM && (encap_type || !multicast), warn,
5280                                "%s%s%s mismatch filter insert failed rc=%d\n",
5281                                encap_name, encap_ipv, um, rc);
5282         } else if (multicast) {
5283                 /* mapping from encap types to default filter IDs (multicast) */
5284                 static enum efx_ef10_default_filters map[] = {
5285                         [EFX_ENCAP_TYPE_NONE] = EFX_EF10_MCDEF,
5286                         [EFX_ENCAP_TYPE_VXLAN] = EFX_EF10_VXLAN4_MCDEF,
5287                         [EFX_ENCAP_TYPE_NVGRE] = EFX_EF10_NVGRE4_MCDEF,
5288                         [EFX_ENCAP_TYPE_GENEVE] = EFX_EF10_GENEVE4_MCDEF,
5289                         [EFX_ENCAP_TYPE_VXLAN | EFX_ENCAP_FLAG_IPV6] =
5290                                 EFX_EF10_VXLAN6_MCDEF,
5291                         [EFX_ENCAP_TYPE_NVGRE | EFX_ENCAP_FLAG_IPV6] =
5292                                 EFX_EF10_NVGRE6_MCDEF,
5293                         [EFX_ENCAP_TYPE_GENEVE | EFX_ENCAP_FLAG_IPV6] =
5294                                 EFX_EF10_GENEVE6_MCDEF,
5295                 };
5296
5297                 /* quick bounds check (BCAST result impossible) */
5298                 BUILD_BUG_ON(EFX_EF10_BCAST != 0);
5299                 if (encap_type >= ARRAY_SIZE(map) || map[encap_type] == 0) {
5300                         WARN_ON(1);
5301                         return -EINVAL;
5302                 }
5303                 /* then follow map */
5304                 id = &vlan->default_filters[map[encap_type]];
5305
5306                 EFX_WARN_ON_PARANOID(*id != EFX_EF10_FILTER_ID_INVALID);
5307                 *id = efx_ef10_filter_get_unsafe_id(rc);
5308                 if (!nic_data->workaround_26807 && !encap_type) {
5309                         /* Also need an Ethernet broadcast filter */
5310                         efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
5311                                            filter_flags, 0);
5312                         eth_broadcast_addr(baddr);
5313                         efx_filter_set_eth_local(&spec, vlan->vid, baddr);
5314                         rc = efx_ef10_filter_insert(efx, &spec, true);
5315                         if (rc < 0) {
5316                                 netif_warn(efx, drv, efx->net_dev,
5317                                            "Broadcast filter insert failed rc=%d\n",
5318                                            rc);
5319                                 if (rollback) {
5320                                         /* Roll back the mc_def filter */
5321                                         efx_ef10_filter_remove_unsafe(
5322                                                         efx, EFX_FILTER_PRI_AUTO,
5323                                                         *id);
5324                                         *id = EFX_EF10_FILTER_ID_INVALID;
5325                                         return rc;
5326                                 }
5327                         } else {
5328                                 EFX_WARN_ON_PARANOID(
5329                                         vlan->default_filters[EFX_EF10_BCAST] !=
5330                                         EFX_EF10_FILTER_ID_INVALID);
5331                                 vlan->default_filters[EFX_EF10_BCAST] =
5332                                         efx_ef10_filter_get_unsafe_id(rc);
5333                         }
5334                 }
5335                 rc = 0;
5336         } else {
5337                 /* mapping from encap types to default filter IDs (unicast) */
5338                 static enum efx_ef10_default_filters map[] = {
5339                         [EFX_ENCAP_TYPE_NONE] = EFX_EF10_UCDEF,
5340                         [EFX_ENCAP_TYPE_VXLAN] = EFX_EF10_VXLAN4_UCDEF,
5341                         [EFX_ENCAP_TYPE_NVGRE] = EFX_EF10_NVGRE4_UCDEF,
5342                         [EFX_ENCAP_TYPE_GENEVE] = EFX_EF10_GENEVE4_UCDEF,
5343                         [EFX_ENCAP_TYPE_VXLAN | EFX_ENCAP_FLAG_IPV6] =
5344                                 EFX_EF10_VXLAN6_UCDEF,
5345                         [EFX_ENCAP_TYPE_NVGRE | EFX_ENCAP_FLAG_IPV6] =
5346                                 EFX_EF10_NVGRE6_UCDEF,
5347                         [EFX_ENCAP_TYPE_GENEVE | EFX_ENCAP_FLAG_IPV6] =
5348                                 EFX_EF10_GENEVE6_UCDEF,
5349                 };
5350
5351                 /* quick bounds check (BCAST result impossible) */
5352                 BUILD_BUG_ON(EFX_EF10_BCAST != 0);
5353                 if (encap_type >= ARRAY_SIZE(map) || map[encap_type] == 0) {
5354                         WARN_ON(1);
5355                         return -EINVAL;
5356                 }
5357                 /* then follow map */
5358                 id = &vlan->default_filters[map[encap_type]];
5359                 EFX_WARN_ON_PARANOID(*id != EFX_EF10_FILTER_ID_INVALID);
5360                 *id = rc;
5361                 rc = 0;
5362         }
5363         return rc;
5364 }
5365
5366 /* Remove filters that weren't renewed.  Since nothing else changes the AUTO_OLD
5367  * flag or removes these filters, we don't need to hold the filter_lock while
5368  * scanning for these filters.
5369  */
5370 static void efx_ef10_filter_remove_old(struct efx_nic *efx)
5371 {
5372         struct efx_ef10_filter_table *table = efx->filter_state;
5373         int remove_failed = 0;
5374         int remove_noent = 0;
5375         int rc;
5376         int i;
5377
5378         for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
5379                 if (READ_ONCE(table->entry[i].spec) &
5380                     EFX_EF10_FILTER_FLAG_AUTO_OLD) {
5381                         rc = efx_ef10_filter_remove_internal(efx,
5382                                         1U << EFX_FILTER_PRI_AUTO, i, true);
5383                         if (rc == -ENOENT)
5384                                 remove_noent++;
5385                         else if (rc)
5386                                 remove_failed++;
5387                 }
5388         }
5389
5390         if (remove_failed)
5391                 netif_info(efx, drv, efx->net_dev,
5392                            "%s: failed to remove %d filters\n",
5393                            __func__, remove_failed);
5394         if (remove_noent)
5395                 netif_info(efx, drv, efx->net_dev,
5396                            "%s: failed to remove %d non-existent filters\n",
5397                            __func__, remove_noent);
5398 }
5399
5400 static int efx_ef10_vport_set_mac_address(struct efx_nic *efx)
5401 {
5402         struct efx_ef10_nic_data *nic_data = efx->nic_data;
5403         u8 mac_old[ETH_ALEN];
5404         int rc, rc2;
5405
5406         /* Only reconfigure a PF-created vport */
5407         if (is_zero_ether_addr(nic_data->vport_mac))
5408                 return 0;
5409
5410         efx_device_detach_sync(efx);
5411         efx_net_stop(efx->net_dev);
5412         down_write(&efx->filter_sem);
5413         efx_ef10_filter_table_remove(efx);
5414         up_write(&efx->filter_sem);
5415
5416         rc = efx_ef10_vadaptor_free(efx, nic_data->vport_id);
5417         if (rc)
5418                 goto restore_filters;
5419
5420         ether_addr_copy(mac_old, nic_data->vport_mac);
5421         rc = efx_ef10_vport_del_mac(efx, nic_data->vport_id,
5422                                     nic_data->vport_mac);
5423         if (rc)
5424                 goto restore_vadaptor;
5425
5426         rc = efx_ef10_vport_add_mac(efx, nic_data->vport_id,
5427                                     efx->net_dev->dev_addr);
5428         if (!rc) {
5429                 ether_addr_copy(nic_data->vport_mac, efx->net_dev->dev_addr);
5430         } else {
5431                 rc2 = efx_ef10_vport_add_mac(efx, nic_data->vport_id, mac_old);
5432                 if (rc2) {
5433                         /* Failed to add original MAC, so clear vport_mac */
5434                         eth_zero_addr(nic_data->vport_mac);
5435                         goto reset_nic;
5436                 }
5437         }
5438
5439 restore_vadaptor:
5440         rc2 = efx_ef10_vadaptor_alloc(efx, nic_data->vport_id);
5441         if (rc2)
5442                 goto reset_nic;
5443 restore_filters:
5444         down_write(&efx->filter_sem);
5445         rc2 = efx_ef10_filter_table_probe(efx);
5446         up_write(&efx->filter_sem);
5447         if (rc2)
5448                 goto reset_nic;
5449
5450         rc2 = efx_net_open(efx->net_dev);
5451         if (rc2)
5452                 goto reset_nic;
5453
5454         efx_device_attach_if_not_resetting(efx);
5455
5456         return rc;
5457
5458 reset_nic:
5459         netif_err(efx, drv, efx->net_dev,
5460                   "Failed to restore when changing MAC address - scheduling reset\n");
5461         efx_schedule_reset(efx, RESET_TYPE_DATAPATH);
5462
5463         return rc ? rc : rc2;
5464 }
5465
5466 /* Caller must hold efx->filter_sem for read if race against
5467  * efx_ef10_filter_table_remove() is possible
5468  */
5469 static void efx_ef10_filter_vlan_sync_rx_mode(struct efx_nic *efx,
5470                                               struct efx_ef10_filter_vlan *vlan)
5471 {
5472         struct efx_ef10_filter_table *table = efx->filter_state;
5473         struct efx_ef10_nic_data *nic_data = efx->nic_data;
5474
5475         /* Do not install unspecified VID if VLAN filtering is enabled.
5476          * Do not install all specified VIDs if VLAN filtering is disabled.
5477          */
5478         if ((vlan->vid == EFX_FILTER_VID_UNSPEC) == table->vlan_filter)
5479                 return;
5480
5481         /* Insert/renew unicast filters */
5482         if (table->uc_promisc) {
5483                 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_NONE,
5484                                            false, false);
5485                 efx_ef10_filter_insert_addr_list(efx, vlan, false, false);
5486         } else {
5487                 /* If any of the filters failed to insert, fall back to
5488                  * promiscuous mode - add in the uc_def filter.  But keep
5489                  * our individual unicast filters.
5490                  */
5491                 if (efx_ef10_filter_insert_addr_list(efx, vlan, false, false))
5492                         efx_ef10_filter_insert_def(efx, vlan,
5493                                                    EFX_ENCAP_TYPE_NONE,
5494                                                    false, false);
5495         }
5496         efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_VXLAN,
5497                                    false, false);
5498         efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_VXLAN |
5499                                               EFX_ENCAP_FLAG_IPV6,
5500                                    false, false);
5501         efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_NVGRE,
5502                                    false, false);
5503         efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_NVGRE |
5504                                               EFX_ENCAP_FLAG_IPV6,
5505                                    false, false);
5506         efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_GENEVE,
5507                                    false, false);
5508         efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_GENEVE |
5509                                               EFX_ENCAP_FLAG_IPV6,
5510                                    false, false);
5511
5512         /* Insert/renew multicast filters */
5513         /* If changing promiscuous state with cascaded multicast filters, remove
5514          * old filters first, so that packets are dropped rather than duplicated
5515          */
5516         if (nic_data->workaround_26807 &&
5517             table->mc_promisc_last != table->mc_promisc)
5518                 efx_ef10_filter_remove_old(efx);
5519         if (table->mc_promisc) {
5520                 if (nic_data->workaround_26807) {
5521                         /* If we failed to insert promiscuous filters, rollback
5522                          * and fall back to individual multicast filters
5523                          */
5524                         if (efx_ef10_filter_insert_def(efx, vlan,
5525                                                        EFX_ENCAP_TYPE_NONE,
5526                                                        true, true)) {
5527                                 /* Changing promisc state, so remove old filters */
5528                                 efx_ef10_filter_remove_old(efx);
5529                                 efx_ef10_filter_insert_addr_list(efx, vlan,
5530                                                                  true, false);
5531                         }
5532                 } else {
5533                         /* If we failed to insert promiscuous filters, don't
5534                          * rollback.  Regardless, also insert the mc_list,
5535                          * unless it's incomplete due to overflow
5536                          */
5537                         efx_ef10_filter_insert_def(efx, vlan,
5538                                                    EFX_ENCAP_TYPE_NONE,
5539                                                    true, false);
5540                         if (!table->mc_overflow)
5541                                 efx_ef10_filter_insert_addr_list(efx, vlan,
5542                                                                  true, false);
5543                 }
5544         } else {
5545                 /* If any filters failed to insert, rollback and fall back to
5546                  * promiscuous mode - mc_def filter and maybe broadcast.  If
5547                  * that fails, roll back again and insert as many of our
5548                  * individual multicast filters as we can.
5549                  */
5550                 if (efx_ef10_filter_insert_addr_list(efx, vlan, true, true)) {
5551                         /* Changing promisc state, so remove old filters */
5552                         if (nic_data->workaround_26807)
5553                                 efx_ef10_filter_remove_old(efx);
5554                         if (efx_ef10_filter_insert_def(efx, vlan,
5555                                                        EFX_ENCAP_TYPE_NONE,
5556                                                        true, true))
5557                                 efx_ef10_filter_insert_addr_list(efx, vlan,
5558                                                                  true, false);
5559                 }
5560         }
5561         efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_VXLAN,
5562                                    true, false);
5563         efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_VXLAN |
5564                                               EFX_ENCAP_FLAG_IPV6,
5565                                    true, false);
5566         efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_NVGRE,
5567                                    true, false);
5568         efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_NVGRE |
5569                                               EFX_ENCAP_FLAG_IPV6,
5570                                    true, false);
5571         efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_GENEVE,
5572                                    true, false);
5573         efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_GENEVE |
5574                                               EFX_ENCAP_FLAG_IPV6,
5575                                    true, false);
5576 }
5577
5578 /* Caller must hold efx->filter_sem for read if race against
5579  * efx_ef10_filter_table_remove() is possible
5580  */
5581 static void efx_ef10_filter_sync_rx_mode(struct efx_nic *efx)
5582 {
5583         struct efx_ef10_filter_table *table = efx->filter_state;
5584         struct net_device *net_dev = efx->net_dev;
5585         struct efx_ef10_filter_vlan *vlan;
5586         bool vlan_filter;
5587
5588         if (!efx_dev_registered(efx))
5589                 return;
5590
5591         if (!table)
5592                 return;
5593
5594         efx_ef10_filter_mark_old(efx);
5595
5596         /* Copy/convert the address lists; add the primary station
5597          * address and broadcast address
5598          */
5599         netif_addr_lock_bh(net_dev);
5600         efx_ef10_filter_uc_addr_list(efx);
5601         efx_ef10_filter_mc_addr_list(efx);
5602         netif_addr_unlock_bh(net_dev);
5603
5604         /* If VLAN filtering changes, all old filters are finally removed.
5605          * Do it in advance to avoid conflicts for unicast untagged and
5606          * VLAN 0 tagged filters.
5607          */
5608         vlan_filter = !!(net_dev->features & NETIF_F_HW_VLAN_CTAG_FILTER);
5609         if (table->vlan_filter != vlan_filter) {
5610                 table->vlan_filter = vlan_filter;
5611                 efx_ef10_filter_remove_old(efx);
5612         }
5613
5614         list_for_each_entry(vlan, &table->vlan_list, list)
5615                 efx_ef10_filter_vlan_sync_rx_mode(efx, vlan);
5616
5617         efx_ef10_filter_remove_old(efx);
5618         table->mc_promisc_last = table->mc_promisc;
5619 }
5620
5621 static struct efx_ef10_filter_vlan *efx_ef10_filter_find_vlan(struct efx_nic *efx, u16 vid)
5622 {
5623         struct efx_ef10_filter_table *table = efx->filter_state;
5624         struct efx_ef10_filter_vlan *vlan;
5625
5626         WARN_ON(!rwsem_is_locked(&efx->filter_sem));
5627
5628         list_for_each_entry(vlan, &table->vlan_list, list) {
5629                 if (vlan->vid == vid)
5630                         return vlan;
5631         }
5632
5633         return NULL;
5634 }
5635
5636 static int efx_ef10_filter_add_vlan(struct efx_nic *efx, u16 vid)
5637 {
5638         struct efx_ef10_filter_table *table = efx->filter_state;
5639         struct efx_ef10_filter_vlan *vlan;
5640         unsigned int i;
5641
5642         if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
5643                 return -EINVAL;
5644
5645         vlan = efx_ef10_filter_find_vlan(efx, vid);
5646         if (WARN_ON(vlan)) {
5647                 netif_err(efx, drv, efx->net_dev,
5648                           "VLAN %u already added\n", vid);
5649                 return -EALREADY;
5650         }
5651
5652         vlan = kzalloc(sizeof(*vlan), GFP_KERNEL);
5653         if (!vlan)
5654                 return -ENOMEM;
5655
5656         vlan->vid = vid;
5657
5658         for (i = 0; i < ARRAY_SIZE(vlan->uc); i++)
5659                 vlan->uc[i] = EFX_EF10_FILTER_ID_INVALID;
5660         for (i = 0; i < ARRAY_SIZE(vlan->mc); i++)
5661                 vlan->mc[i] = EFX_EF10_FILTER_ID_INVALID;
5662         for (i = 0; i < EFX_EF10_NUM_DEFAULT_FILTERS; i++)
5663                 vlan->default_filters[i] = EFX_EF10_FILTER_ID_INVALID;
5664
5665         list_add_tail(&vlan->list, &table->vlan_list);
5666
5667         if (efx_dev_registered(efx))
5668                 efx_ef10_filter_vlan_sync_rx_mode(efx, vlan);
5669
5670         return 0;
5671 }
5672
5673 static void efx_ef10_filter_del_vlan_internal(struct efx_nic *efx,
5674                                               struct efx_ef10_filter_vlan *vlan)
5675 {
5676         unsigned int i;
5677
5678         /* See comment in efx_ef10_filter_table_remove() */
5679         if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
5680                 return;
5681
5682         list_del(&vlan->list);
5683
5684         for (i = 0; i < ARRAY_SIZE(vlan->uc); i++)
5685                 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO,
5686                                               vlan->uc[i]);
5687         for (i = 0; i < ARRAY_SIZE(vlan->mc); i++)
5688                 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO,
5689                                               vlan->mc[i]);
5690         for (i = 0; i < EFX_EF10_NUM_DEFAULT_FILTERS; i++)
5691                 if (vlan->default_filters[i] != EFX_EF10_FILTER_ID_INVALID)
5692                         efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO,
5693                                                       vlan->default_filters[i]);
5694
5695         kfree(vlan);
5696 }
5697
5698 static void efx_ef10_filter_del_vlan(struct efx_nic *efx, u16 vid)
5699 {
5700         struct efx_ef10_filter_vlan *vlan;
5701
5702         /* See comment in efx_ef10_filter_table_remove() */
5703         if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
5704                 return;
5705
5706         vlan = efx_ef10_filter_find_vlan(efx, vid);
5707         if (!vlan) {
5708                 netif_err(efx, drv, efx->net_dev,
5709                           "VLAN %u not found in filter state\n", vid);
5710                 return;
5711         }
5712
5713         efx_ef10_filter_del_vlan_internal(efx, vlan);
5714 }
5715
5716 static int efx_ef10_set_mac_address(struct efx_nic *efx)
5717 {
5718         MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_SET_MAC_IN_LEN);
5719         struct efx_ef10_nic_data *nic_data = efx->nic_data;
5720         bool was_enabled = efx->port_enabled;
5721         int rc;
5722
5723         efx_device_detach_sync(efx);
5724         efx_net_stop(efx->net_dev);
5725
5726         mutex_lock(&efx->mac_lock);
5727         down_write(&efx->filter_sem);
5728         efx_ef10_filter_table_remove(efx);
5729
5730         ether_addr_copy(MCDI_PTR(inbuf, VADAPTOR_SET_MAC_IN_MACADDR),
5731                         efx->net_dev->dev_addr);
5732         MCDI_SET_DWORD(inbuf, VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID,
5733                        nic_data->vport_id);
5734         rc = efx_mcdi_rpc_quiet(efx, MC_CMD_VADAPTOR_SET_MAC, inbuf,
5735                                 sizeof(inbuf), NULL, 0, NULL);
5736
5737         efx_ef10_filter_table_probe(efx);
5738         up_write(&efx->filter_sem);
5739         mutex_unlock(&efx->mac_lock);
5740
5741         if (was_enabled)
5742                 efx_net_open(efx->net_dev);
5743         efx_device_attach_if_not_resetting(efx);
5744
5745 #ifdef CONFIG_SFC_SRIOV
5746         if (efx->pci_dev->is_virtfn && efx->pci_dev->physfn) {
5747                 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn;
5748
5749                 if (rc == -EPERM) {
5750                         struct efx_nic *efx_pf;
5751
5752                         /* Switch to PF and change MAC address on vport */
5753                         efx_pf = pci_get_drvdata(pci_dev_pf);
5754
5755                         rc = efx_ef10_sriov_set_vf_mac(efx_pf,
5756                                                        nic_data->vf_index,
5757                                                        efx->net_dev->dev_addr);
5758                 } else if (!rc) {
5759                         struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
5760                         struct efx_ef10_nic_data *nic_data = efx_pf->nic_data;
5761                         unsigned int i;
5762
5763                         /* MAC address successfully changed by VF (with MAC
5764                          * spoofing) so update the parent PF if possible.
5765                          */
5766                         for (i = 0; i < efx_pf->vf_count; ++i) {
5767                                 struct ef10_vf *vf = nic_data->vf + i;
5768
5769                                 if (vf->efx == efx) {
5770                                         ether_addr_copy(vf->mac,
5771                                                         efx->net_dev->dev_addr);
5772                                         return 0;
5773                                 }
5774                         }
5775                 }
5776         } else
5777 #endif
5778         if (rc == -EPERM) {
5779                 netif_err(efx, drv, efx->net_dev,
5780                           "Cannot change MAC address; use sfboot to enable"
5781                           " mac-spoofing on this interface\n");
5782         } else if (rc == -ENOSYS && !efx_ef10_is_vf(efx)) {
5783                 /* If the active MCFW does not support MC_CMD_VADAPTOR_SET_MAC
5784                  * fall-back to the method of changing the MAC address on the
5785                  * vport.  This only applies to PFs because such versions of
5786                  * MCFW do not support VFs.
5787                  */
5788                 rc = efx_ef10_vport_set_mac_address(efx);
5789         } else if (rc) {
5790                 efx_mcdi_display_error(efx, MC_CMD_VADAPTOR_SET_MAC,
5791                                        sizeof(inbuf), NULL, 0, rc);
5792         }
5793
5794         return rc;
5795 }
5796
5797 static int efx_ef10_mac_reconfigure(struct efx_nic *efx)
5798 {
5799         efx_ef10_filter_sync_rx_mode(efx);
5800
5801         return efx_mcdi_set_mac(efx);
5802 }
5803
5804 static int efx_ef10_mac_reconfigure_vf(struct efx_nic *efx)
5805 {
5806         efx_ef10_filter_sync_rx_mode(efx);
5807
5808         return 0;
5809 }
5810
5811 static int efx_ef10_start_bist(struct efx_nic *efx, u32 bist_type)
5812 {
5813         MCDI_DECLARE_BUF(inbuf, MC_CMD_START_BIST_IN_LEN);
5814
5815         MCDI_SET_DWORD(inbuf, START_BIST_IN_TYPE, bist_type);
5816         return efx_mcdi_rpc(efx, MC_CMD_START_BIST, inbuf, sizeof(inbuf),
5817                             NULL, 0, NULL);
5818 }
5819
5820 /* MC BISTs follow a different poll mechanism to phy BISTs.
5821  * The BIST is done in the poll handler on the MC, and the MCDI command
5822  * will block until the BIST is done.
5823  */
5824 static int efx_ef10_poll_bist(struct efx_nic *efx)
5825 {
5826         int rc;
5827         MCDI_DECLARE_BUF(outbuf, MC_CMD_POLL_BIST_OUT_LEN);
5828         size_t outlen;
5829         u32 result;
5830
5831         rc = efx_mcdi_rpc(efx, MC_CMD_POLL_BIST, NULL, 0,
5832                            outbuf, sizeof(outbuf), &outlen);
5833         if (rc != 0)
5834                 return rc;
5835
5836         if (outlen < MC_CMD_POLL_BIST_OUT_LEN)
5837                 return -EIO;
5838
5839         result = MCDI_DWORD(outbuf, POLL_BIST_OUT_RESULT);
5840         switch (result) {
5841         case MC_CMD_POLL_BIST_PASSED:
5842                 netif_dbg(efx, hw, efx->net_dev, "BIST passed.\n");
5843                 return 0;
5844         case MC_CMD_POLL_BIST_TIMEOUT:
5845                 netif_err(efx, hw, efx->net_dev, "BIST timed out\n");
5846                 return -EIO;
5847         case MC_CMD_POLL_BIST_FAILED:
5848                 netif_err(efx, hw, efx->net_dev, "BIST failed.\n");
5849                 return -EIO;
5850         default:
5851                 netif_err(efx, hw, efx->net_dev,
5852                           "BIST returned unknown result %u", result);
5853                 return -EIO;
5854         }
5855 }
5856
5857 static int efx_ef10_run_bist(struct efx_nic *efx, u32 bist_type)
5858 {
5859         int rc;
5860
5861         netif_dbg(efx, drv, efx->net_dev, "starting BIST type %u\n", bist_type);
5862
5863         rc = efx_ef10_start_bist(efx, bist_type);
5864         if (rc != 0)
5865                 return rc;
5866
5867         return efx_ef10_poll_bist(efx);
5868 }
5869
5870 static int
5871 efx_ef10_test_chip(struct efx_nic *efx, struct efx_self_tests *tests)
5872 {
5873         int rc, rc2;
5874
5875         efx_reset_down(efx, RESET_TYPE_WORLD);
5876
5877         rc = efx_mcdi_rpc(efx, MC_CMD_ENABLE_OFFLINE_BIST,
5878                           NULL, 0, NULL, 0, NULL);
5879         if (rc != 0)
5880                 goto out;
5881
5882         tests->memory = efx_ef10_run_bist(efx, MC_CMD_MC_MEM_BIST) ? -1 : 1;
5883         tests->registers = efx_ef10_run_bist(efx, MC_CMD_REG_BIST) ? -1 : 1;
5884
5885         rc = efx_mcdi_reset(efx, RESET_TYPE_WORLD);
5886
5887 out:
5888         if (rc == -EPERM)
5889                 rc = 0;
5890         rc2 = efx_reset_up(efx, RESET_TYPE_WORLD, rc == 0);
5891         return rc ? rc : rc2;
5892 }
5893
5894 #ifdef CONFIG_SFC_MTD
5895
5896 struct efx_ef10_nvram_type_info {
5897         u16 type, type_mask;
5898         u8 port;
5899         const char *name;
5900 };
5901
5902 static const struct efx_ef10_nvram_type_info efx_ef10_nvram_types[] = {
5903         { NVRAM_PARTITION_TYPE_MC_FIRMWARE,        0,    0, "sfc_mcfw" },
5904         { NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 0,    0, "sfc_mcfw_backup" },
5905         { NVRAM_PARTITION_TYPE_EXPANSION_ROM,      0,    0, "sfc_exp_rom" },
5906         { NVRAM_PARTITION_TYPE_STATIC_CONFIG,      0,    0, "sfc_static_cfg" },
5907         { NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG,     0,    0, "sfc_dynamic_cfg" },
5908         { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 0,   0, "sfc_exp_rom_cfg" },
5909         { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1, 0,   1, "sfc_exp_rom_cfg" },
5910         { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2, 0,   2, "sfc_exp_rom_cfg" },
5911         { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3, 0,   3, "sfc_exp_rom_cfg" },
5912         { NVRAM_PARTITION_TYPE_LICENSE,            0,    0, "sfc_license" },
5913         { NVRAM_PARTITION_TYPE_PHY_MIN,            0xff, 0, "sfc_phy_fw" },
5914 };
5915
5916 static int efx_ef10_mtd_probe_partition(struct efx_nic *efx,
5917                                         struct efx_mcdi_mtd_partition *part,
5918                                         unsigned int type)
5919 {
5920         MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_METADATA_IN_LEN);
5921         MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_METADATA_OUT_LENMAX);
5922         const struct efx_ef10_nvram_type_info *info;
5923         size_t size, erase_size, outlen;
5924         bool protected;
5925         int rc;
5926
5927         for (info = efx_ef10_nvram_types; ; info++) {
5928                 if (info ==
5929                     efx_ef10_nvram_types + ARRAY_SIZE(efx_ef10_nvram_types))
5930                         return -ENODEV;
5931                 if ((type & ~info->type_mask) == info->type)
5932                         break;
5933         }
5934         if (info->port != efx_port_num(efx))
5935                 return -ENODEV;
5936
5937         rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected);
5938         if (rc)
5939                 return rc;
5940         if (protected)
5941                 return -ENODEV; /* hide it */
5942
5943         part->nvram_type = type;
5944
5945         MCDI_SET_DWORD(inbuf, NVRAM_METADATA_IN_TYPE, type);
5946         rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_METADATA, inbuf, sizeof(inbuf),
5947                           outbuf, sizeof(outbuf), &outlen);
5948         if (rc)
5949                 return rc;
5950         if (outlen < MC_CMD_NVRAM_METADATA_OUT_LENMIN)
5951                 return -EIO;
5952         if (MCDI_DWORD(outbuf, NVRAM_METADATA_OUT_FLAGS) &
5953             (1 << MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN))
5954                 part->fw_subtype = MCDI_DWORD(outbuf,
5955                                               NVRAM_METADATA_OUT_SUBTYPE);
5956
5957         part->common.dev_type_name = "EF10 NVRAM manager";
5958         part->common.type_name = info->name;
5959
5960         part->common.mtd.type = MTD_NORFLASH;
5961         part->common.mtd.flags = MTD_CAP_NORFLASH;
5962         part->common.mtd.size = size;
5963         part->common.mtd.erasesize = erase_size;
5964
5965         return 0;
5966 }
5967
5968 static int efx_ef10_mtd_probe(struct efx_nic *efx)
5969 {
5970         MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX);
5971         struct efx_mcdi_mtd_partition *parts;
5972         size_t outlen, n_parts_total, i, n_parts;
5973         unsigned int type;
5974         int rc;
5975
5976         ASSERT_RTNL();
5977
5978         BUILD_BUG_ON(MC_CMD_NVRAM_PARTITIONS_IN_LEN != 0);
5979         rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_PARTITIONS, NULL, 0,
5980                           outbuf, sizeof(outbuf), &outlen);
5981         if (rc)
5982                 return rc;
5983         if (outlen < MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN)
5984                 return -EIO;
5985
5986         n_parts_total = MCDI_DWORD(outbuf, NVRAM_PARTITIONS_OUT_NUM_PARTITIONS);
5987         if (n_parts_total >
5988             MCDI_VAR_ARRAY_LEN(outlen, NVRAM_PARTITIONS_OUT_TYPE_ID))
5989                 return -EIO;
5990
5991         parts = kcalloc(n_parts_total, sizeof(*parts), GFP_KERNEL);
5992         if (!parts)
5993                 return -ENOMEM;
5994
5995         n_parts = 0;
5996         for (i = 0; i < n_parts_total; i++) {
5997                 type = MCDI_ARRAY_DWORD(outbuf, NVRAM_PARTITIONS_OUT_TYPE_ID,
5998                                         i);
5999                 rc = efx_ef10_mtd_probe_partition(efx, &parts[n_parts], type);
6000                 if (rc == 0)
6001                         n_parts++;
6002                 else if (rc != -ENODEV)
6003                         goto fail;
6004         }
6005
6006         rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts));
6007 fail:
6008         if (rc)
6009                 kfree(parts);
6010         return rc;
6011 }
6012
6013 #endif /* CONFIG_SFC_MTD */
6014
6015 static void efx_ef10_ptp_write_host_time(struct efx_nic *efx, u32 host_time)
6016 {
6017         _efx_writed(efx, cpu_to_le32(host_time), ER_DZ_MC_DB_LWRD);
6018 }
6019
6020 static void efx_ef10_ptp_write_host_time_vf(struct efx_nic *efx,
6021                                             u32 host_time) {}
6022
6023 static int efx_ef10_rx_enable_timestamping(struct efx_channel *channel,
6024                                            bool temp)
6025 {
6026         MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN);
6027         int rc;
6028
6029         if (channel->sync_events_state == SYNC_EVENTS_REQUESTED ||
6030             channel->sync_events_state == SYNC_EVENTS_VALID ||
6031             (temp && channel->sync_events_state == SYNC_EVENTS_DISABLED))
6032                 return 0;
6033         channel->sync_events_state = SYNC_EVENTS_REQUESTED;
6034
6035         MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE);
6036         MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
6037         MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE,
6038                        channel->channel);
6039
6040         rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
6041                           inbuf, sizeof(inbuf), NULL, 0, NULL);
6042
6043         if (rc != 0)
6044                 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
6045                                                     SYNC_EVENTS_DISABLED;
6046
6047         return rc;
6048 }
6049
6050 static int efx_ef10_rx_disable_timestamping(struct efx_channel *channel,
6051                                             bool temp)
6052 {
6053         MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN);
6054         int rc;
6055
6056         if (channel->sync_events_state == SYNC_EVENTS_DISABLED ||
6057             (temp && channel->sync_events_state == SYNC_EVENTS_QUIESCENT))
6058                 return 0;
6059         if (channel->sync_events_state == SYNC_EVENTS_QUIESCENT) {
6060                 channel->sync_events_state = SYNC_EVENTS_DISABLED;
6061                 return 0;
6062         }
6063         channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
6064                                             SYNC_EVENTS_DISABLED;
6065
6066         MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE);
6067         MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
6068         MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL,
6069                        MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE);
6070         MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE,
6071                        channel->channel);
6072
6073         rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
6074                           inbuf, sizeof(inbuf), NULL, 0, NULL);
6075
6076         return rc;
6077 }
6078
6079 static int efx_ef10_ptp_set_ts_sync_events(struct efx_nic *efx, bool en,
6080                                            bool temp)
6081 {
6082         int (*set)(struct efx_channel *channel, bool temp);
6083         struct efx_channel *channel;
6084
6085         set = en ?
6086               efx_ef10_rx_enable_timestamping :
6087               efx_ef10_rx_disable_timestamping;
6088
6089         efx_for_each_channel(channel, efx) {
6090                 int rc = set(channel, temp);
6091                 if (en && rc != 0) {
6092                         efx_ef10_ptp_set_ts_sync_events(efx, false, temp);
6093                         return rc;
6094                 }
6095         }
6096
6097         return 0;
6098 }
6099
6100 static int efx_ef10_ptp_set_ts_config_vf(struct efx_nic *efx,
6101                                          struct hwtstamp_config *init)
6102 {
6103         return -EOPNOTSUPP;
6104 }
6105
6106 static int efx_ef10_ptp_set_ts_config(struct efx_nic *efx,
6107                                       struct hwtstamp_config *init)
6108 {
6109         int rc;
6110
6111         switch (init->rx_filter) {
6112         case HWTSTAMP_FILTER_NONE:
6113                 efx_ef10_ptp_set_ts_sync_events(efx, false, false);
6114                 /* if TX timestamping is still requested then leave PTP on */
6115                 return efx_ptp_change_mode(efx,
6116                                            init->tx_type != HWTSTAMP_TX_OFF, 0);
6117         case HWTSTAMP_FILTER_ALL:
6118         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
6119         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
6120         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
6121         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
6122         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
6123         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
6124         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
6125         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
6126         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
6127         case HWTSTAMP_FILTER_PTP_V2_EVENT:
6128         case HWTSTAMP_FILTER_PTP_V2_SYNC:
6129         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
6130         case HWTSTAMP_FILTER_NTP_ALL:
6131                 init->rx_filter = HWTSTAMP_FILTER_ALL;
6132                 rc = efx_ptp_change_mode(efx, true, 0);
6133                 if (!rc)
6134                         rc = efx_ef10_ptp_set_ts_sync_events(efx, true, false);
6135                 if (rc)
6136                         efx_ptp_change_mode(efx, false, 0);
6137                 return rc;
6138         default:
6139                 return -ERANGE;
6140         }
6141 }
6142
6143 static int efx_ef10_get_phys_port_id(struct efx_nic *efx,
6144                                      struct netdev_phys_item_id *ppid)
6145 {
6146         struct efx_ef10_nic_data *nic_data = efx->nic_data;
6147
6148         if (!is_valid_ether_addr(nic_data->port_id))
6149                 return -EOPNOTSUPP;
6150
6151         ppid->id_len = ETH_ALEN;
6152         memcpy(ppid->id, nic_data->port_id, ppid->id_len);
6153
6154         return 0;
6155 }
6156
6157 static int efx_ef10_vlan_rx_add_vid(struct efx_nic *efx, __be16 proto, u16 vid)
6158 {
6159         if (proto != htons(ETH_P_8021Q))
6160                 return -EINVAL;
6161
6162         return efx_ef10_add_vlan(efx, vid);
6163 }
6164
6165 static int efx_ef10_vlan_rx_kill_vid(struct efx_nic *efx, __be16 proto, u16 vid)
6166 {
6167         if (proto != htons(ETH_P_8021Q))
6168                 return -EINVAL;
6169
6170         return efx_ef10_del_vlan(efx, vid);
6171 }
6172
6173 /* We rely on the MCDI wiping out our TX rings if it made any changes to the
6174  * ports table, ensuring that any TSO descriptors that were made on a now-
6175  * removed tunnel port will be blown away and won't break things when we try
6176  * to transmit them using the new ports table.
6177  */
6178 static int efx_ef10_set_udp_tnl_ports(struct efx_nic *efx, bool unloading)
6179 {
6180         struct efx_ef10_nic_data *nic_data = efx->nic_data;
6181         MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LENMAX);
6182         MCDI_DECLARE_BUF(outbuf, MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_LEN);
6183         bool will_reset = false;
6184         size_t num_entries = 0;
6185         size_t inlen, outlen;
6186         size_t i;
6187         int rc;
6188         efx_dword_t flags_and_num_entries;
6189
6190         WARN_ON(!mutex_is_locked(&nic_data->udp_tunnels_lock));
6191
6192         nic_data->udp_tunnels_dirty = false;
6193
6194         if (!(nic_data->datapath_caps &
6195             (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN))) {
6196                 efx_device_attach_if_not_resetting(efx);
6197                 return 0;
6198         }
6199
6200         BUILD_BUG_ON(ARRAY_SIZE(nic_data->udp_tunnels) >
6201                      MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MAXNUM);
6202
6203         for (i = 0; i < ARRAY_SIZE(nic_data->udp_tunnels); ++i) {
6204                 if (nic_data->udp_tunnels[i].count &&
6205                     nic_data->udp_tunnels[i].port) {
6206                         efx_dword_t entry;
6207
6208                         EFX_POPULATE_DWORD_2(entry,
6209                                 TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT,
6210                                         ntohs(nic_data->udp_tunnels[i].port),
6211                                 TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL,
6212                                         nic_data->udp_tunnels[i].type);
6213                         *_MCDI_ARRAY_DWORD(inbuf,
6214                                 SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES,
6215                                 num_entries++) = entry;
6216                 }
6217         }
6218
6219         BUILD_BUG_ON((MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_OFST -
6220                       MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS_OFST) * 8 !=
6221                      EFX_WORD_1_LBN);
6222         BUILD_BUG_ON(MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_LEN * 8 !=
6223                      EFX_WORD_1_WIDTH);
6224         EFX_POPULATE_DWORD_2(flags_and_num_entries,
6225                              MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING,
6226                                 !!unloading,
6227                              EFX_WORD_1, num_entries);
6228         *_MCDI_DWORD(inbuf, SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS) =
6229                 flags_and_num_entries;
6230
6231         inlen = MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LEN(num_entries);
6232
6233         rc = efx_mcdi_rpc_quiet(efx, MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS,
6234                                 inbuf, inlen, outbuf, sizeof(outbuf), &outlen);
6235         if (rc == -EIO) {
6236                 /* Most likely the MC rebooted due to another function also
6237                  * setting its tunnel port list. Mark the tunnel port list as
6238                  * dirty, so it will be pushed upon coming up from the reboot.
6239                  */
6240                 nic_data->udp_tunnels_dirty = true;
6241                 return 0;
6242         }
6243
6244         if (rc) {
6245                 /* expected not available on unprivileged functions */
6246                 if (rc != -EPERM)
6247                         netif_warn(efx, drv, efx->net_dev,
6248                                    "Unable to set UDP tunnel ports; rc=%d.\n", rc);
6249         } else if (MCDI_DWORD(outbuf, SET_TUNNEL_ENCAP_UDP_PORTS_OUT_FLAGS) &
6250                    (1 << MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_LBN)) {
6251                 netif_info(efx, drv, efx->net_dev,
6252                            "Rebooting MC due to UDP tunnel port list change\n");
6253                 will_reset = true;
6254                 if (unloading)
6255                         /* Delay for the MC reset to complete. This will make
6256                          * unloading other functions a bit smoother. This is a
6257                          * race, but the other unload will work whichever way
6258                          * it goes, this just avoids an unnecessary error
6259                          * message.
6260                          */
6261                         msleep(100);
6262         }
6263         if (!will_reset && !unloading) {
6264                 /* The caller will have detached, relying on the MC reset to
6265                  * trigger a re-attach.  Since there won't be an MC reset, we
6266                  * have to do the attach ourselves.
6267                  */
6268                 efx_device_attach_if_not_resetting(efx);
6269         }
6270
6271         return rc;
6272 }
6273
6274 static int efx_ef10_udp_tnl_push_ports(struct efx_nic *efx)
6275 {
6276         struct efx_ef10_nic_data *nic_data = efx->nic_data;
6277         int rc = 0;
6278
6279         mutex_lock(&nic_data->udp_tunnels_lock);
6280         if (nic_data->udp_tunnels_dirty) {
6281                 /* Make sure all TX are stopped while we modify the table, else
6282                  * we might race against an efx_features_check().
6283                  */
6284                 efx_device_detach_sync(efx);
6285                 rc = efx_ef10_set_udp_tnl_ports(efx, false);
6286         }
6287         mutex_unlock(&nic_data->udp_tunnels_lock);
6288         return rc;
6289 }
6290
6291 static struct efx_udp_tunnel *__efx_ef10_udp_tnl_lookup_port(struct efx_nic *efx,
6292                                                              __be16 port)
6293 {
6294         struct efx_ef10_nic_data *nic_data = efx->nic_data;
6295         size_t i;
6296
6297         for (i = 0; i < ARRAY_SIZE(nic_data->udp_tunnels); ++i) {
6298                 if (!nic_data->udp_tunnels[i].count)
6299                         continue;
6300                 if (nic_data->udp_tunnels[i].port == port)
6301                         return &nic_data->udp_tunnels[i];
6302         }
6303         return NULL;
6304 }
6305
6306 static int efx_ef10_udp_tnl_add_port(struct efx_nic *efx,
6307                                      struct efx_udp_tunnel tnl)
6308 {
6309         struct efx_ef10_nic_data *nic_data = efx->nic_data;
6310         struct efx_udp_tunnel *match;
6311         char typebuf[8];
6312         size_t i;
6313         int rc;
6314
6315         if (!(nic_data->datapath_caps &
6316               (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN)))
6317                 return 0;
6318
6319         efx_get_udp_tunnel_type_name(tnl.type, typebuf, sizeof(typebuf));
6320         netif_dbg(efx, drv, efx->net_dev, "Adding UDP tunnel (%s) port %d\n",
6321                   typebuf, ntohs(tnl.port));
6322
6323         mutex_lock(&nic_data->udp_tunnels_lock);
6324         /* Make sure all TX are stopped while we add to the table, else we
6325          * might race against an efx_features_check().
6326          */
6327         efx_device_detach_sync(efx);
6328
6329         match = __efx_ef10_udp_tnl_lookup_port(efx, tnl.port);
6330         if (match != NULL) {
6331                 if (match->type == tnl.type) {
6332                         netif_dbg(efx, drv, efx->net_dev,
6333                                   "Referencing existing tunnel entry\n");
6334                         match->count++;
6335                         /* No need to cause an MCDI update */
6336                         rc = 0;
6337                         goto unlock_out;
6338                 }
6339                 efx_get_udp_tunnel_type_name(match->type,
6340                                              typebuf, sizeof(typebuf));
6341                 netif_dbg(efx, drv, efx->net_dev,
6342                           "UDP port %d is already in use by %s\n",
6343                           ntohs(tnl.port), typebuf);
6344                 rc = -EEXIST;
6345                 goto unlock_out;
6346         }
6347
6348         for (i = 0; i < ARRAY_SIZE(nic_data->udp_tunnels); ++i)
6349                 if (!nic_data->udp_tunnels[i].count) {
6350                         nic_data->udp_tunnels[i] = tnl;
6351                         nic_data->udp_tunnels[i].count = 1;
6352                         rc = efx_ef10_set_udp_tnl_ports(efx, false);
6353                         goto unlock_out;
6354                 }
6355
6356         netif_dbg(efx, drv, efx->net_dev,
6357                   "Unable to add UDP tunnel (%s) port %d; insufficient resources.\n",
6358                   typebuf, ntohs(tnl.port));
6359
6360         rc = -ENOMEM;
6361
6362 unlock_out:
6363         mutex_unlock(&nic_data->udp_tunnels_lock);
6364         return rc;
6365 }
6366
6367 /* Called under the TX lock with the TX queue running, hence no-one can be
6368  * in the middle of updating the UDP tunnels table.  However, they could
6369  * have tried and failed the MCDI, in which case they'll have set the dirty
6370  * flag before dropping their locks.
6371  */
6372 static bool efx_ef10_udp_tnl_has_port(struct efx_nic *efx, __be16 port)
6373 {
6374         struct efx_ef10_nic_data *nic_data = efx->nic_data;
6375
6376         if (!(nic_data->datapath_caps &
6377               (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN)))
6378                 return false;
6379
6380         if (nic_data->udp_tunnels_dirty)
6381                 /* SW table may not match HW state, so just assume we can't
6382                  * use any UDP tunnel offloads.
6383                  */
6384                 return false;
6385
6386         return __efx_ef10_udp_tnl_lookup_port(efx, port) != NULL;
6387 }
6388
6389 static int efx_ef10_udp_tnl_del_port(struct efx_nic *efx,
6390                                      struct efx_udp_tunnel tnl)
6391 {
6392         struct efx_ef10_nic_data *nic_data = efx->nic_data;
6393         struct efx_udp_tunnel *match;
6394         char typebuf[8];
6395         int rc;
6396
6397         if (!(nic_data->datapath_caps &
6398               (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN)))
6399                 return 0;
6400
6401         efx_get_udp_tunnel_type_name(tnl.type, typebuf, sizeof(typebuf));
6402         netif_dbg(efx, drv, efx->net_dev, "Removing UDP tunnel (%s) port %d\n",
6403                   typebuf, ntohs(tnl.port));
6404
6405         mutex_lock(&nic_data->udp_tunnels_lock);
6406         /* Make sure all TX are stopped while we remove from the table, else we
6407          * might race against an efx_features_check().
6408          */
6409         efx_device_detach_sync(efx);
6410
6411         match = __efx_ef10_udp_tnl_lookup_port(efx, tnl.port);
6412         if (match != NULL) {
6413                 if (match->type == tnl.type) {
6414                         if (--match->count) {
6415                                 /* Port is still in use, so nothing to do */
6416                                 netif_dbg(efx, drv, efx->net_dev,
6417                                           "UDP tunnel port %d remains active\n",
6418                                           ntohs(tnl.port));
6419                                 rc = 0;
6420                                 goto out_unlock;
6421                         }
6422                         rc = efx_ef10_set_udp_tnl_ports(efx, false);
6423                         goto out_unlock;
6424                 }
6425                 efx_get_udp_tunnel_type_name(match->type,
6426                                              typebuf, sizeof(typebuf));
6427                 netif_warn(efx, drv, efx->net_dev,
6428                            "UDP port %d is actually in use by %s, not removing\n",
6429                            ntohs(tnl.port), typebuf);
6430         }
6431         rc = -ENOENT;
6432
6433 out_unlock:
6434         mutex_unlock(&nic_data->udp_tunnels_lock);
6435         return rc;
6436 }
6437
6438 #define EF10_OFFLOAD_FEATURES           \
6439         (NETIF_F_IP_CSUM |              \
6440          NETIF_F_HW_VLAN_CTAG_FILTER |  \
6441          NETIF_F_IPV6_CSUM |            \
6442          NETIF_F_RXHASH |               \
6443          NETIF_F_NTUPLE)
6444
6445 const struct efx_nic_type efx_hunt_a0_vf_nic_type = {
6446         .is_vf = true,
6447         .mem_bar = efx_ef10_vf_mem_bar,
6448         .mem_map_size = efx_ef10_mem_map_size,
6449         .probe = efx_ef10_probe_vf,
6450         .remove = efx_ef10_remove,
6451         .dimension_resources = efx_ef10_dimension_resources,
6452         .init = efx_ef10_init_nic,
6453         .fini = efx_port_dummy_op_void,
6454         .map_reset_reason = efx_ef10_map_reset_reason,
6455         .map_reset_flags = efx_ef10_map_reset_flags,
6456         .reset = efx_ef10_reset,
6457         .probe_port = efx_mcdi_port_probe,
6458         .remove_port = efx_mcdi_port_remove,
6459         .fini_dmaq = efx_ef10_fini_dmaq,
6460         .prepare_flr = efx_ef10_prepare_flr,
6461         .finish_flr = efx_port_dummy_op_void,
6462         .describe_stats = efx_ef10_describe_stats,
6463         .update_stats = efx_ef10_update_stats_vf,
6464         .start_stats = efx_port_dummy_op_void,
6465         .pull_stats = efx_port_dummy_op_void,
6466         .stop_stats = efx_port_dummy_op_void,
6467         .set_id_led = efx_mcdi_set_id_led,
6468         .push_irq_moderation = efx_ef10_push_irq_moderation,
6469         .reconfigure_mac = efx_ef10_mac_reconfigure_vf,
6470         .check_mac_fault = efx_mcdi_mac_check_fault,
6471         .reconfigure_port = efx_mcdi_port_reconfigure,
6472         .get_wol = efx_ef10_get_wol_vf,
6473         .set_wol = efx_ef10_set_wol_vf,
6474         .resume_wol = efx_port_dummy_op_void,
6475         .mcdi_request = efx_ef10_mcdi_request,
6476         .mcdi_poll_response = efx_ef10_mcdi_poll_response,
6477         .mcdi_read_response = efx_ef10_mcdi_read_response,
6478         .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
6479         .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected,
6480         .irq_enable_master = efx_port_dummy_op_void,
6481         .irq_test_generate = efx_ef10_irq_test_generate,
6482         .irq_disable_non_ev = efx_port_dummy_op_void,
6483         .irq_handle_msi = efx_ef10_msi_interrupt,
6484         .irq_handle_legacy = efx_ef10_legacy_interrupt,
6485         .tx_probe = efx_ef10_tx_probe,
6486         .tx_init = efx_ef10_tx_init,
6487         .tx_remove = efx_ef10_tx_remove,
6488         .tx_write = efx_ef10_tx_write,
6489         .tx_limit_len = efx_ef10_tx_limit_len,
6490         .rx_push_rss_config = efx_ef10_vf_rx_push_rss_config,
6491         .rx_pull_rss_config = efx_ef10_rx_pull_rss_config,
6492         .rx_probe = efx_ef10_rx_probe,
6493         .rx_init = efx_ef10_rx_init,
6494         .rx_remove = efx_ef10_rx_remove,
6495         .rx_write = efx_ef10_rx_write,
6496         .rx_defer_refill = efx_ef10_rx_defer_refill,
6497         .ev_probe = efx_ef10_ev_probe,
6498         .ev_init = efx_ef10_ev_init,
6499         .ev_fini = efx_ef10_ev_fini,
6500         .ev_remove = efx_ef10_ev_remove,
6501         .ev_process = efx_ef10_ev_process,
6502         .ev_read_ack = efx_ef10_ev_read_ack,
6503         .ev_test_generate = efx_ef10_ev_test_generate,
6504         .filter_table_probe = efx_ef10_filter_table_probe,
6505         .filter_table_restore = efx_ef10_filter_table_restore,
6506         .filter_table_remove = efx_ef10_filter_table_remove,
6507         .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
6508         .filter_insert = efx_ef10_filter_insert,
6509         .filter_remove_safe = efx_ef10_filter_remove_safe,
6510         .filter_get_safe = efx_ef10_filter_get_safe,
6511         .filter_clear_rx = efx_ef10_filter_clear_rx,
6512         .filter_count_rx_used = efx_ef10_filter_count_rx_used,
6513         .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
6514         .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
6515 #ifdef CONFIG_RFS_ACCEL
6516         .filter_rfs_insert = efx_ef10_filter_rfs_insert,
6517         .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
6518 #endif
6519 #ifdef CONFIG_SFC_MTD
6520         .mtd_probe = efx_port_dummy_op_int,
6521 #endif
6522         .ptp_write_host_time = efx_ef10_ptp_write_host_time_vf,
6523         .ptp_set_ts_config = efx_ef10_ptp_set_ts_config_vf,
6524         .vlan_rx_add_vid = efx_ef10_vlan_rx_add_vid,
6525         .vlan_rx_kill_vid = efx_ef10_vlan_rx_kill_vid,
6526 #ifdef CONFIG_SFC_SRIOV
6527         .vswitching_probe = efx_ef10_vswitching_probe_vf,
6528         .vswitching_restore = efx_ef10_vswitching_restore_vf,
6529         .vswitching_remove = efx_ef10_vswitching_remove_vf,
6530 #endif
6531         .get_mac_address = efx_ef10_get_mac_address_vf,
6532         .set_mac_address = efx_ef10_set_mac_address,
6533
6534         .get_phys_port_id = efx_ef10_get_phys_port_id,
6535         .revision = EFX_REV_HUNT_A0,
6536         .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
6537         .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
6538         .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
6539         .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
6540         .can_rx_scatter = true,
6541         .always_rx_scatter = true,
6542         .min_interrupt_mode = EFX_INT_MODE_MSIX,
6543         .max_interrupt_mode = EFX_INT_MODE_MSIX,
6544         .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
6545         .offload_features = EF10_OFFLOAD_FEATURES,
6546         .mcdi_max_ver = 2,
6547         .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,
6548         .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
6549                             1 << HWTSTAMP_FILTER_ALL,
6550         .rx_hash_key_size = 40,
6551 };
6552
6553 const struct efx_nic_type efx_hunt_a0_nic_type = {
6554         .is_vf = false,
6555         .mem_bar = efx_ef10_pf_mem_bar,
6556         .mem_map_size = efx_ef10_mem_map_size,
6557         .probe = efx_ef10_probe_pf,
6558         .remove = efx_ef10_remove,
6559         .dimension_resources = efx_ef10_dimension_resources,
6560         .init = efx_ef10_init_nic,
6561         .fini = efx_port_dummy_op_void,
6562         .map_reset_reason = efx_ef10_map_reset_reason,
6563         .map_reset_flags = efx_ef10_map_reset_flags,
6564         .reset = efx_ef10_reset,
6565         .probe_port = efx_mcdi_port_probe,
6566         .remove_port = efx_mcdi_port_remove,
6567         .fini_dmaq = efx_ef10_fini_dmaq,
6568         .prepare_flr = efx_ef10_prepare_flr,
6569         .finish_flr = efx_port_dummy_op_void,
6570         .describe_stats = efx_ef10_describe_stats,
6571         .update_stats = efx_ef10_update_stats_pf,
6572         .start_stats = efx_mcdi_mac_start_stats,
6573         .pull_stats = efx_mcdi_mac_pull_stats,
6574         .stop_stats = efx_mcdi_mac_stop_stats,
6575         .set_id_led = efx_mcdi_set_id_led,
6576         .push_irq_moderation = efx_ef10_push_irq_moderation,
6577         .reconfigure_mac = efx_ef10_mac_reconfigure,
6578         .check_mac_fault = efx_mcdi_mac_check_fault,
6579         .reconfigure_port = efx_mcdi_port_reconfigure,
6580         .get_wol = efx_ef10_get_wol,
6581         .set_wol = efx_ef10_set_wol,
6582         .resume_wol = efx_port_dummy_op_void,
6583         .test_chip = efx_ef10_test_chip,
6584         .test_nvram = efx_mcdi_nvram_test_all,
6585         .mcdi_request = efx_ef10_mcdi_request,
6586         .mcdi_poll_response = efx_ef10_mcdi_poll_response,
6587         .mcdi_read_response = efx_ef10_mcdi_read_response,
6588         .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
6589         .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected,
6590         .irq_enable_master = efx_port_dummy_op_void,
6591         .irq_test_generate = efx_ef10_irq_test_generate,
6592         .irq_disable_non_ev = efx_port_dummy_op_void,
6593         .irq_handle_msi = efx_ef10_msi_interrupt,
6594         .irq_handle_legacy = efx_ef10_legacy_interrupt,
6595         .tx_probe = efx_ef10_tx_probe,
6596         .tx_init = efx_ef10_tx_init,
6597         .tx_remove = efx_ef10_tx_remove,
6598         .tx_write = efx_ef10_tx_write,
6599         .tx_limit_len = efx_ef10_tx_limit_len,
6600         .rx_push_rss_config = efx_ef10_pf_rx_push_rss_config,
6601         .rx_pull_rss_config = efx_ef10_rx_pull_rss_config,
6602         .rx_probe = efx_ef10_rx_probe,
6603         .rx_init = efx_ef10_rx_init,
6604         .rx_remove = efx_ef10_rx_remove,
6605         .rx_write = efx_ef10_rx_write,
6606         .rx_defer_refill = efx_ef10_rx_defer_refill,
6607         .ev_probe = efx_ef10_ev_probe,
6608         .ev_init = efx_ef10_ev_init,
6609         .ev_fini = efx_ef10_ev_fini,
6610         .ev_remove = efx_ef10_ev_remove,
6611         .ev_process = efx_ef10_ev_process,
6612         .ev_read_ack = efx_ef10_ev_read_ack,
6613         .ev_test_generate = efx_ef10_ev_test_generate,
6614         .filter_table_probe = efx_ef10_filter_table_probe,
6615         .filter_table_restore = efx_ef10_filter_table_restore,
6616         .filter_table_remove = efx_ef10_filter_table_remove,
6617         .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
6618         .filter_insert = efx_ef10_filter_insert,
6619         .filter_remove_safe = efx_ef10_filter_remove_safe,
6620         .filter_get_safe = efx_ef10_filter_get_safe,
6621         .filter_clear_rx = efx_ef10_filter_clear_rx,
6622         .filter_count_rx_used = efx_ef10_filter_count_rx_used,
6623         .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
6624         .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
6625 #ifdef CONFIG_RFS_ACCEL
6626         .filter_rfs_insert = efx_ef10_filter_rfs_insert,
6627         .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
6628 #endif
6629 #ifdef CONFIG_SFC_MTD
6630         .mtd_probe = efx_ef10_mtd_probe,
6631         .mtd_rename = efx_mcdi_mtd_rename,
6632         .mtd_read = efx_mcdi_mtd_read,
6633         .mtd_erase = efx_mcdi_mtd_erase,
6634         .mtd_write = efx_mcdi_mtd_write,
6635         .mtd_sync = efx_mcdi_mtd_sync,
6636 #endif
6637         .ptp_write_host_time = efx_ef10_ptp_write_host_time,
6638         .ptp_set_ts_sync_events = efx_ef10_ptp_set_ts_sync_events,
6639         .ptp_set_ts_config = efx_ef10_ptp_set_ts_config,
6640         .vlan_rx_add_vid = efx_ef10_vlan_rx_add_vid,
6641         .vlan_rx_kill_vid = efx_ef10_vlan_rx_kill_vid,
6642         .udp_tnl_push_ports = efx_ef10_udp_tnl_push_ports,
6643         .udp_tnl_add_port = efx_ef10_udp_tnl_add_port,
6644         .udp_tnl_has_port = efx_ef10_udp_tnl_has_port,
6645         .udp_tnl_del_port = efx_ef10_udp_tnl_del_port,
6646 #ifdef CONFIG_SFC_SRIOV
6647         .sriov_configure = efx_ef10_sriov_configure,
6648         .sriov_init = efx_ef10_sriov_init,
6649         .sriov_fini = efx_ef10_sriov_fini,
6650         .sriov_wanted = efx_ef10_sriov_wanted,
6651         .sriov_reset = efx_ef10_sriov_reset,
6652         .sriov_flr = efx_ef10_sriov_flr,
6653         .sriov_set_vf_mac = efx_ef10_sriov_set_vf_mac,
6654         .sriov_set_vf_vlan = efx_ef10_sriov_set_vf_vlan,
6655         .sriov_set_vf_spoofchk = efx_ef10_sriov_set_vf_spoofchk,
6656         .sriov_get_vf_config = efx_ef10_sriov_get_vf_config,
6657         .sriov_set_vf_link_state = efx_ef10_sriov_set_vf_link_state,
6658         .vswitching_probe = efx_ef10_vswitching_probe_pf,
6659         .vswitching_restore = efx_ef10_vswitching_restore_pf,
6660         .vswitching_remove = efx_ef10_vswitching_remove_pf,
6661 #endif
6662         .get_mac_address = efx_ef10_get_mac_address_pf,
6663         .set_mac_address = efx_ef10_set_mac_address,
6664         .tso_versions = efx_ef10_tso_versions,
6665
6666         .get_phys_port_id = efx_ef10_get_phys_port_id,
6667         .revision = EFX_REV_HUNT_A0,
6668         .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
6669         .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
6670         .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
6671         .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
6672         .can_rx_scatter = true,
6673         .always_rx_scatter = true,
6674         .option_descriptors = true,
6675         .min_interrupt_mode = EFX_INT_MODE_LEGACY,
6676         .max_interrupt_mode = EFX_INT_MODE_MSIX,
6677         .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
6678         .offload_features = EF10_OFFLOAD_FEATURES,
6679         .mcdi_max_ver = 2,
6680         .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,
6681         .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
6682                             1 << HWTSTAMP_FILTER_ALL,
6683         .rx_hash_key_size = 40,
6684 };