1 /****************************************************************************
2 * Driver for Solarflare network controllers and boards
3 * Copyright 2012-2013 Solarflare Communications Inc.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published
7 * by the Free Software Foundation, incorporated herein by reference.
10 #include "net_driver.h"
11 #include "ef10_regs.h"
14 #include "mcdi_pcol.h"
16 #include "workarounds.h"
18 #include "ef10_sriov.h"
20 #include <linux/jhash.h>
21 #include <linux/wait.h>
22 #include <linux/workqueue.h>
24 /* Hardware control for EF10 architecture including 'Huntington'. */
26 #define EFX_EF10_DRVGEN_EV 7
31 /* The maximum size of a shared RSS context */
32 /* TODO: this should really be from the mcdi protocol export */
33 #define EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE 64UL
35 /* The filter table(s) are managed by firmware and we have write-only
36 * access. When removing filters we must identify them to the
37 * firmware by a 64-bit handle, but this is too wide for Linux kernel
38 * interfaces (32-bit for RX NFC, 16-bit for RFS). Also, we need to
39 * be able to tell in advance whether a requested insertion will
40 * replace an existing filter. Therefore we maintain a software hash
41 * table, which should be at least as large as the hardware hash
44 * Huntington has a single 8K filter table shared between all filter
45 * types and both ports.
47 #define HUNT_FILTER_TBL_ROWS 8192
49 #define EFX_EF10_FILTER_ID_INVALID 0xffff
51 #define EFX_EF10_FILTER_DEV_UC_MAX 32
52 #define EFX_EF10_FILTER_DEV_MC_MAX 256
55 struct efx_ef10_vlan {
56 struct list_head list;
60 enum efx_ef10_default_filters {
64 EFX_EF10_VXLAN4_UCDEF,
65 EFX_EF10_VXLAN4_MCDEF,
66 EFX_EF10_VXLAN6_UCDEF,
67 EFX_EF10_VXLAN6_MCDEF,
68 EFX_EF10_NVGRE4_UCDEF,
69 EFX_EF10_NVGRE4_MCDEF,
70 EFX_EF10_NVGRE6_UCDEF,
71 EFX_EF10_NVGRE6_MCDEF,
72 EFX_EF10_GENEVE4_UCDEF,
73 EFX_EF10_GENEVE4_MCDEF,
74 EFX_EF10_GENEVE6_UCDEF,
75 EFX_EF10_GENEVE6_MCDEF,
77 EFX_EF10_NUM_DEFAULT_FILTERS
80 /* Per-VLAN filters information */
81 struct efx_ef10_filter_vlan {
82 struct list_head list;
84 u16 uc[EFX_EF10_FILTER_DEV_UC_MAX];
85 u16 mc[EFX_EF10_FILTER_DEV_MC_MAX];
86 u16 default_filters[EFX_EF10_NUM_DEFAULT_FILTERS];
89 struct efx_ef10_dev_addr {
93 struct efx_ef10_filter_table {
94 /* The MCDI match masks supported by this fw & hw, in order of priority */
95 u32 rx_match_mcdi_flags[
96 MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM * 2];
97 unsigned int rx_match_count;
99 struct rw_semaphore lock; /* Protects entries */
101 unsigned long spec; /* pointer to spec plus flag bits */
102 /* AUTO_OLD is used to mark and sweep MAC filters for the device address lists. */
103 /* unused flag 1UL */
104 #define EFX_EF10_FILTER_FLAG_AUTO_OLD 2UL
105 #define EFX_EF10_FILTER_FLAGS 3UL
106 u64 handle; /* firmware handle */
108 /* Shadow of net_device address lists, guarded by mac_lock */
109 struct efx_ef10_dev_addr dev_uc_list[EFX_EF10_FILTER_DEV_UC_MAX];
110 struct efx_ef10_dev_addr dev_mc_list[EFX_EF10_FILTER_DEV_MC_MAX];
115 /* Whether in multicast promiscuous mode when last changed */
116 bool mc_promisc_last;
117 bool mc_overflow; /* Too many MC addrs; should always imply mc_promisc */
119 struct list_head vlan_list;
122 /* An arbitrary search limit for the software hash table */
123 #define EFX_EF10_FILTER_SEARCH_LIMIT 200
125 static void efx_ef10_rx_free_indir_table(struct efx_nic *efx);
126 static void efx_ef10_filter_table_remove(struct efx_nic *efx);
127 static int efx_ef10_filter_add_vlan(struct efx_nic *efx, u16 vid);
128 static void efx_ef10_filter_del_vlan_internal(struct efx_nic *efx,
129 struct efx_ef10_filter_vlan *vlan);
130 static void efx_ef10_filter_del_vlan(struct efx_nic *efx, u16 vid);
131 static int efx_ef10_set_udp_tnl_ports(struct efx_nic *efx, bool unloading);
133 static u32 efx_ef10_filter_get_unsafe_id(u32 filter_id)
135 WARN_ON_ONCE(filter_id == EFX_EF10_FILTER_ID_INVALID);
136 return filter_id & (HUNT_FILTER_TBL_ROWS - 1);
139 static unsigned int efx_ef10_filter_get_unsafe_pri(u32 filter_id)
141 return filter_id / (HUNT_FILTER_TBL_ROWS * 2);
144 static u32 efx_ef10_make_filter_id(unsigned int pri, u16 idx)
146 return pri * HUNT_FILTER_TBL_ROWS * 2 + idx;
149 static int efx_ef10_get_warm_boot_count(struct efx_nic *efx)
153 efx_readd(efx, ®, ER_DZ_BIU_MC_SFT_STATUS);
154 return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ?
155 EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO;
158 /* On all EF10s up to and including SFC9220 (Medford1), all PFs use BAR 0 for
159 * I/O space and BAR 2(&3) for memory. On SFC9250 (Medford2), there is no I/O
160 * bar; PFs use BAR 0/1 for memory.
162 static unsigned int efx_ef10_pf_mem_bar(struct efx_nic *efx)
164 switch (efx->pci_dev->device) {
165 case 0x0b03: /* SFC9250 PF */
172 /* All VFs use BAR 0/1 for memory */
173 static unsigned int efx_ef10_vf_mem_bar(struct efx_nic *efx)
178 static unsigned int efx_ef10_mem_map_size(struct efx_nic *efx)
182 bar = efx->type->mem_bar(efx);
183 return resource_size(&efx->pci_dev->resource[bar]);
186 static bool efx_ef10_is_vf(struct efx_nic *efx)
188 return efx->type->is_vf;
191 static int efx_ef10_get_pf_index(struct efx_nic *efx)
193 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN);
194 struct efx_ef10_nic_data *nic_data = efx->nic_data;
198 rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf,
199 sizeof(outbuf), &outlen);
202 if (outlen < sizeof(outbuf))
205 nic_data->pf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_PF);
209 #ifdef CONFIG_SFC_SRIOV
210 static int efx_ef10_get_vf_index(struct efx_nic *efx)
212 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN);
213 struct efx_ef10_nic_data *nic_data = efx->nic_data;
217 rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf,
218 sizeof(outbuf), &outlen);
221 if (outlen < sizeof(outbuf))
224 nic_data->vf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_VF);
229 static int efx_ef10_init_datapath_caps(struct efx_nic *efx)
231 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_V4_OUT_LEN);
232 struct efx_ef10_nic_data *nic_data = efx->nic_data;
236 BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0);
238 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0,
239 outbuf, sizeof(outbuf), &outlen);
242 if (outlen < MC_CMD_GET_CAPABILITIES_OUT_LEN) {
243 netif_err(efx, drv, efx->net_dev,
244 "unable to read datapath firmware capabilities\n");
248 nic_data->datapath_caps =
249 MCDI_DWORD(outbuf, GET_CAPABILITIES_OUT_FLAGS1);
251 if (outlen >= MC_CMD_GET_CAPABILITIES_V2_OUT_LEN) {
252 nic_data->datapath_caps2 = MCDI_DWORD(outbuf,
253 GET_CAPABILITIES_V2_OUT_FLAGS2);
254 nic_data->piobuf_size = MCDI_WORD(outbuf,
255 GET_CAPABILITIES_V2_OUT_SIZE_PIO_BUFF);
257 nic_data->datapath_caps2 = 0;
258 nic_data->piobuf_size = ER_DZ_TX_PIOBUF_SIZE;
261 /* record the DPCPU firmware IDs to determine VEB vswitching support.
263 nic_data->rx_dpcpu_fw_id =
264 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID);
265 nic_data->tx_dpcpu_fw_id =
266 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID);
268 if (!(nic_data->datapath_caps &
269 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN))) {
270 netif_err(efx, probe, efx->net_dev,
271 "current firmware does not support an RX prefix\n");
275 if (outlen >= MC_CMD_GET_CAPABILITIES_V3_OUT_LEN) {
276 u8 vi_window_mode = MCDI_BYTE(outbuf,
277 GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE);
279 switch (vi_window_mode) {
280 case MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_8K:
281 efx->vi_stride = 8192;
283 case MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_16K:
284 efx->vi_stride = 16384;
286 case MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_64K:
287 efx->vi_stride = 65536;
290 netif_err(efx, probe, efx->net_dev,
291 "Unrecognised VI window mode %d\n",
295 netif_dbg(efx, probe, efx->net_dev, "vi_stride = %u\n",
298 /* keep default VI stride */
299 netif_dbg(efx, probe, efx->net_dev,
300 "firmware did not report VI window mode, assuming vi_stride = %u\n",
304 if (outlen >= MC_CMD_GET_CAPABILITIES_V4_OUT_LEN) {
305 efx->num_mac_stats = MCDI_WORD(outbuf,
306 GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS);
307 netif_dbg(efx, probe, efx->net_dev,
308 "firmware reports num_mac_stats = %u\n",
311 /* leave num_mac_stats as the default value, MC_CMD_MAC_NSTATS */
312 netif_dbg(efx, probe, efx->net_dev,
313 "firmware did not report num_mac_stats, assuming %u\n",
320 static void efx_ef10_read_licensed_features(struct efx_nic *efx)
322 MCDI_DECLARE_BUF(inbuf, MC_CMD_LICENSING_V3_IN_LEN);
323 MCDI_DECLARE_BUF(outbuf, MC_CMD_LICENSING_V3_OUT_LEN);
324 struct efx_ef10_nic_data *nic_data = efx->nic_data;
328 MCDI_SET_DWORD(inbuf, LICENSING_V3_IN_OP,
329 MC_CMD_LICENSING_V3_IN_OP_REPORT_LICENSE);
330 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_LICENSING_V3, inbuf, sizeof(inbuf),
331 outbuf, sizeof(outbuf), &outlen);
332 if (rc || (outlen < MC_CMD_LICENSING_V3_OUT_LEN))
335 nic_data->licensed_features = MCDI_QWORD(outbuf,
336 LICENSING_V3_OUT_LICENSED_FEATURES);
339 static int efx_ef10_get_sysclk_freq(struct efx_nic *efx)
341 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CLOCK_OUT_LEN);
344 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CLOCK, NULL, 0,
345 outbuf, sizeof(outbuf), NULL);
348 rc = MCDI_DWORD(outbuf, GET_CLOCK_OUT_SYS_FREQ);
349 return rc > 0 ? rc : -ERANGE;
352 static int efx_ef10_get_timer_workarounds(struct efx_nic *efx)
354 struct efx_ef10_nic_data *nic_data = efx->nic_data;
355 unsigned int implemented;
356 unsigned int enabled;
359 nic_data->workaround_35388 = false;
360 nic_data->workaround_61265 = false;
362 rc = efx_mcdi_get_workarounds(efx, &implemented, &enabled);
365 /* Firmware without GET_WORKAROUNDS - not a problem. */
367 } else if (rc == 0) {
368 /* Bug61265 workaround is always enabled if implemented. */
369 if (enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG61265)
370 nic_data->workaround_61265 = true;
372 if (enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG35388) {
373 nic_data->workaround_35388 = true;
374 } else if (implemented & MC_CMD_GET_WORKAROUNDS_OUT_BUG35388) {
375 /* Workaround is implemented but not enabled.
378 rc = efx_mcdi_set_workaround(efx,
379 MC_CMD_WORKAROUND_BUG35388,
382 nic_data->workaround_35388 = true;
383 /* If we failed to set the workaround just carry on. */
388 netif_dbg(efx, probe, efx->net_dev,
389 "workaround for bug 35388 is %sabled\n",
390 nic_data->workaround_35388 ? "en" : "dis");
391 netif_dbg(efx, probe, efx->net_dev,
392 "workaround for bug 61265 is %sabled\n",
393 nic_data->workaround_61265 ? "en" : "dis");
398 static void efx_ef10_process_timer_config(struct efx_nic *efx,
399 const efx_dword_t *data)
401 unsigned int max_count;
403 if (EFX_EF10_WORKAROUND_61265(efx)) {
404 efx->timer_quantum_ns = MCDI_DWORD(data,
405 GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_STEP_NS);
406 efx->timer_max_ns = MCDI_DWORD(data,
407 GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_MAX_NS);
408 } else if (EFX_EF10_WORKAROUND_35388(efx)) {
409 efx->timer_quantum_ns = MCDI_DWORD(data,
410 GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_NS_PER_COUNT);
411 max_count = MCDI_DWORD(data,
412 GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_MAX_COUNT);
413 efx->timer_max_ns = max_count * efx->timer_quantum_ns;
415 efx->timer_quantum_ns = MCDI_DWORD(data,
416 GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_NS_PER_COUNT);
417 max_count = MCDI_DWORD(data,
418 GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_MAX_COUNT);
419 efx->timer_max_ns = max_count * efx->timer_quantum_ns;
422 netif_dbg(efx, probe, efx->net_dev,
423 "got timer properties from MC: quantum %u ns; max %u ns\n",
424 efx->timer_quantum_ns, efx->timer_max_ns);
427 static int efx_ef10_get_timer_config(struct efx_nic *efx)
429 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN);
432 rc = efx_ef10_get_timer_workarounds(efx);
436 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_GET_EVQ_TMR_PROPERTIES, NULL, 0,
437 outbuf, sizeof(outbuf), NULL);
440 efx_ef10_process_timer_config(efx, outbuf);
441 } else if (rc == -ENOSYS || rc == -EPERM) {
442 /* Not available - fall back to Huntington defaults. */
443 unsigned int quantum;
445 rc = efx_ef10_get_sysclk_freq(efx);
449 quantum = 1536000 / rc; /* 1536 cycles */
450 efx->timer_quantum_ns = quantum;
451 efx->timer_max_ns = efx->type->timer_period_max * quantum;
454 efx_mcdi_display_error(efx, MC_CMD_GET_EVQ_TMR_PROPERTIES,
455 MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN,
462 static int efx_ef10_get_mac_address_pf(struct efx_nic *efx, u8 *mac_address)
464 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN);
468 BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0);
470 rc = efx_mcdi_rpc(efx, MC_CMD_GET_MAC_ADDRESSES, NULL, 0,
471 outbuf, sizeof(outbuf), &outlen);
474 if (outlen < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN)
477 ether_addr_copy(mac_address,
478 MCDI_PTR(outbuf, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE));
482 static int efx_ef10_get_mac_address_vf(struct efx_nic *efx, u8 *mac_address)
484 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN);
485 MCDI_DECLARE_BUF(outbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX);
489 MCDI_SET_DWORD(inbuf, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID,
490 EVB_PORT_ID_ASSIGNED);
491 rc = efx_mcdi_rpc(efx, MC_CMD_VPORT_GET_MAC_ADDRESSES, inbuf,
492 sizeof(inbuf), outbuf, sizeof(outbuf), &outlen);
496 if (outlen < MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN)
499 num_addrs = MCDI_DWORD(outbuf,
500 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT);
502 WARN_ON(num_addrs != 1);
504 ether_addr_copy(mac_address,
505 MCDI_PTR(outbuf, VPORT_GET_MAC_ADDRESSES_OUT_MACADDR));
510 static ssize_t efx_ef10_show_link_control_flag(struct device *dev,
511 struct device_attribute *attr,
514 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
516 return sprintf(buf, "%d\n",
517 ((efx->mcdi->fn_flags) &
518 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL))
522 static ssize_t efx_ef10_show_primary_flag(struct device *dev,
523 struct device_attribute *attr,
526 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
528 return sprintf(buf, "%d\n",
529 ((efx->mcdi->fn_flags) &
530 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY))
534 static struct efx_ef10_vlan *efx_ef10_find_vlan(struct efx_nic *efx, u16 vid)
536 struct efx_ef10_nic_data *nic_data = efx->nic_data;
537 struct efx_ef10_vlan *vlan;
539 WARN_ON(!mutex_is_locked(&nic_data->vlan_lock));
541 list_for_each_entry(vlan, &nic_data->vlan_list, list) {
542 if (vlan->vid == vid)
549 static int efx_ef10_add_vlan(struct efx_nic *efx, u16 vid)
551 struct efx_ef10_nic_data *nic_data = efx->nic_data;
552 struct efx_ef10_vlan *vlan;
555 mutex_lock(&nic_data->vlan_lock);
557 vlan = efx_ef10_find_vlan(efx, vid);
559 /* We add VID 0 on init. 8021q adds it on module init
560 * for all interfaces with VLAN filtring feature.
564 netif_warn(efx, drv, efx->net_dev,
565 "VLAN %u already added\n", vid);
571 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL);
577 list_add_tail(&vlan->list, &nic_data->vlan_list);
579 if (efx->filter_state) {
580 mutex_lock(&efx->mac_lock);
581 down_write(&efx->filter_sem);
582 rc = efx_ef10_filter_add_vlan(efx, vlan->vid);
583 up_write(&efx->filter_sem);
584 mutex_unlock(&efx->mac_lock);
586 goto fail_filter_add_vlan;
590 mutex_unlock(&nic_data->vlan_lock);
593 fail_filter_add_vlan:
594 list_del(&vlan->list);
598 mutex_unlock(&nic_data->vlan_lock);
602 static void efx_ef10_del_vlan_internal(struct efx_nic *efx,
603 struct efx_ef10_vlan *vlan)
605 struct efx_ef10_nic_data *nic_data = efx->nic_data;
607 WARN_ON(!mutex_is_locked(&nic_data->vlan_lock));
609 if (efx->filter_state) {
610 down_write(&efx->filter_sem);
611 efx_ef10_filter_del_vlan(efx, vlan->vid);
612 up_write(&efx->filter_sem);
615 list_del(&vlan->list);
619 static int efx_ef10_del_vlan(struct efx_nic *efx, u16 vid)
621 struct efx_ef10_nic_data *nic_data = efx->nic_data;
622 struct efx_ef10_vlan *vlan;
625 /* 8021q removes VID 0 on module unload for all interfaces
626 * with VLAN filtering feature. We need to keep it to receive
632 mutex_lock(&nic_data->vlan_lock);
634 vlan = efx_ef10_find_vlan(efx, vid);
636 netif_err(efx, drv, efx->net_dev,
637 "VLAN %u to be deleted not found\n", vid);
640 efx_ef10_del_vlan_internal(efx, vlan);
643 mutex_unlock(&nic_data->vlan_lock);
648 static void efx_ef10_cleanup_vlans(struct efx_nic *efx)
650 struct efx_ef10_nic_data *nic_data = efx->nic_data;
651 struct efx_ef10_vlan *vlan, *next_vlan;
653 mutex_lock(&nic_data->vlan_lock);
654 list_for_each_entry_safe(vlan, next_vlan, &nic_data->vlan_list, list)
655 efx_ef10_del_vlan_internal(efx, vlan);
656 mutex_unlock(&nic_data->vlan_lock);
659 static DEVICE_ATTR(link_control_flag, 0444, efx_ef10_show_link_control_flag,
661 static DEVICE_ATTR(primary_flag, 0444, efx_ef10_show_primary_flag, NULL);
663 static int efx_ef10_probe(struct efx_nic *efx)
665 struct efx_ef10_nic_data *nic_data;
668 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
671 efx->nic_data = nic_data;
673 /* we assume later that we can copy from this buffer in dwords */
674 BUILD_BUG_ON(MCDI_CTL_SDU_LEN_MAX_V2 % 4);
676 rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf,
677 8 + MCDI_CTL_SDU_LEN_MAX_V2, GFP_KERNEL);
681 /* Get the MC's warm boot count. In case it's rebooting right
682 * now, be prepared to retry.
686 rc = efx_ef10_get_warm_boot_count(efx);
693 nic_data->warm_boot_count = rc;
695 efx->rss_context.context_id = EFX_EF10_RSS_CONTEXT_INVALID;
697 nic_data->vport_id = EVB_PORT_ID_ASSIGNED;
699 /* In case we're recovering from a crash (kexec), we want to
700 * cancel any outstanding request by the previous user of this
701 * function. We send a special message using the least
702 * significant bits of the 'high' (doorbell) register.
704 _efx_writed(efx, cpu_to_le32(1), ER_DZ_MC_DB_HWRD);
706 rc = efx_mcdi_init(efx);
710 mutex_init(&nic_data->udp_tunnels_lock);
712 /* Reset (most) configuration for this function */
713 rc = efx_mcdi_reset(efx, RESET_TYPE_ALL);
717 /* Enable event logging */
718 rc = efx_mcdi_log_ctrl(efx, true, false, 0);
722 rc = device_create_file(&efx->pci_dev->dev,
723 &dev_attr_link_control_flag);
727 rc = device_create_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
731 rc = efx_ef10_get_pf_index(efx);
735 rc = efx_ef10_init_datapath_caps(efx);
739 efx_ef10_read_licensed_features(efx);
741 /* We can have one VI for each vi_stride-byte region.
742 * However, until we use TX option descriptors we need two TX queues
745 efx->max_channels = min_t(unsigned int,
747 efx_ef10_mem_map_size(efx) /
748 (efx->vi_stride * EFX_TXQ_TYPES));
749 efx->max_tx_channels = efx->max_channels;
750 if (WARN_ON(efx->max_channels == 0)) {
755 efx->rx_packet_len_offset =
756 ES_DZ_RX_PREFIX_PKTLEN_OFST - ES_DZ_RX_PREFIX_SIZE;
758 if (nic_data->datapath_caps &
759 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_LBN))
760 efx->net_dev->hw_features |= NETIF_F_RXFCS;
762 rc = efx_mcdi_port_get_number(efx);
767 rc = efx->type->get_mac_address(efx, efx->net_dev->perm_addr);
771 rc = efx_ef10_get_timer_config(efx);
775 rc = efx_mcdi_mon_probe(efx);
776 if (rc && rc != -EPERM)
779 efx_ptp_defer_probe_with_channel(efx);
781 #ifdef CONFIG_SFC_SRIOV
782 if ((efx->pci_dev->physfn) && (!efx->pci_dev->is_physfn)) {
783 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn;
784 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
786 efx_pf->type->get_mac_address(efx_pf, nic_data->port_id);
789 ether_addr_copy(nic_data->port_id, efx->net_dev->perm_addr);
791 INIT_LIST_HEAD(&nic_data->vlan_list);
792 mutex_init(&nic_data->vlan_lock);
794 /* Add unspecified VID to support VLAN filtering being disabled */
795 rc = efx_ef10_add_vlan(efx, EFX_FILTER_VID_UNSPEC);
797 goto fail_add_vid_unspec;
799 /* If VLAN filtering is enabled, we need VID 0 to get untagged
800 * traffic. It is added automatically if 8021q module is loaded,
801 * but we can't rely on it since module may be not loaded.
803 rc = efx_ef10_add_vlan(efx, 0);
810 efx_ef10_cleanup_vlans(efx);
812 mutex_destroy(&nic_data->vlan_lock);
814 efx_mcdi_mon_remove(efx);
816 device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
818 device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag);
820 efx_mcdi_detach(efx);
822 mutex_lock(&nic_data->udp_tunnels_lock);
823 memset(nic_data->udp_tunnels, 0, sizeof(nic_data->udp_tunnels));
824 (void)efx_ef10_set_udp_tnl_ports(efx, true);
825 mutex_unlock(&nic_data->udp_tunnels_lock);
826 mutex_destroy(&nic_data->udp_tunnels_lock);
830 efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
833 efx->nic_data = NULL;
837 static int efx_ef10_free_vis(struct efx_nic *efx)
839 MCDI_DECLARE_BUF_ERR(outbuf);
841 int rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FREE_VIS, NULL, 0,
842 outbuf, sizeof(outbuf), &outlen);
844 /* -EALREADY means nothing to free, so ignore */
848 efx_mcdi_display_error(efx, MC_CMD_FREE_VIS, 0, outbuf, outlen,
855 static void efx_ef10_free_piobufs(struct efx_nic *efx)
857 struct efx_ef10_nic_data *nic_data = efx->nic_data;
858 MCDI_DECLARE_BUF(inbuf, MC_CMD_FREE_PIOBUF_IN_LEN);
862 BUILD_BUG_ON(MC_CMD_FREE_PIOBUF_OUT_LEN != 0);
864 for (i = 0; i < nic_data->n_piobufs; i++) {
865 MCDI_SET_DWORD(inbuf, FREE_PIOBUF_IN_PIOBUF_HANDLE,
866 nic_data->piobuf_handle[i]);
867 rc = efx_mcdi_rpc(efx, MC_CMD_FREE_PIOBUF, inbuf, sizeof(inbuf),
872 nic_data->n_piobufs = 0;
875 static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
877 struct efx_ef10_nic_data *nic_data = efx->nic_data;
878 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_PIOBUF_OUT_LEN);
883 BUILD_BUG_ON(MC_CMD_ALLOC_PIOBUF_IN_LEN != 0);
885 for (i = 0; i < n; i++) {
886 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_ALLOC_PIOBUF, NULL, 0,
887 outbuf, sizeof(outbuf), &outlen);
889 /* Don't display the MC error if we didn't have space
892 if (!(efx_ef10_is_vf(efx) && rc == -ENOSPC))
893 efx_mcdi_display_error(efx, MC_CMD_ALLOC_PIOBUF,
894 0, outbuf, outlen, rc);
897 if (outlen < MC_CMD_ALLOC_PIOBUF_OUT_LEN) {
901 nic_data->piobuf_handle[i] =
902 MCDI_DWORD(outbuf, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE);
903 netif_dbg(efx, probe, efx->net_dev,
904 "allocated PIO buffer %u handle %x\n", i,
905 nic_data->piobuf_handle[i]);
908 nic_data->n_piobufs = i;
910 efx_ef10_free_piobufs(efx);
914 static int efx_ef10_link_piobufs(struct efx_nic *efx)
916 struct efx_ef10_nic_data *nic_data = efx->nic_data;
917 MCDI_DECLARE_BUF(inbuf, MC_CMD_LINK_PIOBUF_IN_LEN);
918 struct efx_channel *channel;
919 struct efx_tx_queue *tx_queue;
920 unsigned int offset, index;
923 BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_OUT_LEN != 0);
924 BUILD_BUG_ON(MC_CMD_UNLINK_PIOBUF_OUT_LEN != 0);
926 /* Link a buffer to each VI in the write-combining mapping */
927 for (index = 0; index < nic_data->n_piobufs; ++index) {
928 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_PIOBUF_HANDLE,
929 nic_data->piobuf_handle[index]);
930 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_TXQ_INSTANCE,
931 nic_data->pio_write_vi_base + index);
932 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
933 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
936 netif_err(efx, drv, efx->net_dev,
937 "failed to link VI %u to PIO buffer %u (%d)\n",
938 nic_data->pio_write_vi_base + index, index,
942 netif_dbg(efx, probe, efx->net_dev,
943 "linked VI %u to PIO buffer %u\n",
944 nic_data->pio_write_vi_base + index, index);
947 /* Link a buffer to each TX queue */
948 efx_for_each_channel(channel, efx) {
949 /* Extra channels, even those with TXQs (PTP), do not require
952 if (!channel->type->want_pio)
954 efx_for_each_channel_tx_queue(tx_queue, channel) {
955 /* We assign the PIO buffers to queues in
956 * reverse order to allow for the following
959 offset = ((efx->tx_channel_offset + efx->n_tx_channels -
960 tx_queue->channel->channel - 1) *
962 index = offset / nic_data->piobuf_size;
963 offset = offset % nic_data->piobuf_size;
965 /* When the host page size is 4K, the first
966 * host page in the WC mapping may be within
967 * the same VI page as the last TX queue. We
968 * can only link one buffer to each VI.
970 if (tx_queue->queue == nic_data->pio_write_vi_base) {
974 MCDI_SET_DWORD(inbuf,
975 LINK_PIOBUF_IN_PIOBUF_HANDLE,
976 nic_data->piobuf_handle[index]);
977 MCDI_SET_DWORD(inbuf,
978 LINK_PIOBUF_IN_TXQ_INSTANCE,
980 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
981 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
986 /* This is non-fatal; the TX path just
987 * won't use PIO for this queue
989 netif_err(efx, drv, efx->net_dev,
990 "failed to link VI %u to PIO buffer %u (%d)\n",
991 tx_queue->queue, index, rc);
992 tx_queue->piobuf = NULL;
995 nic_data->pio_write_base +
996 index * efx->vi_stride + offset;
997 tx_queue->piobuf_offset = offset;
998 netif_dbg(efx, probe, efx->net_dev,
999 "linked VI %u to PIO buffer %u offset %x addr %p\n",
1000 tx_queue->queue, index,
1001 tx_queue->piobuf_offset,
1010 /* inbuf was defined for MC_CMD_LINK_PIOBUF. We can use the same
1011 * buffer for MC_CMD_UNLINK_PIOBUF because it's shorter.
1013 BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_IN_LEN < MC_CMD_UNLINK_PIOBUF_IN_LEN);
1015 MCDI_SET_DWORD(inbuf, UNLINK_PIOBUF_IN_TXQ_INSTANCE,
1016 nic_data->pio_write_vi_base + index);
1017 efx_mcdi_rpc(efx, MC_CMD_UNLINK_PIOBUF,
1018 inbuf, MC_CMD_UNLINK_PIOBUF_IN_LEN,
1024 static void efx_ef10_forget_old_piobufs(struct efx_nic *efx)
1026 struct efx_channel *channel;
1027 struct efx_tx_queue *tx_queue;
1029 /* All our existing PIO buffers went away */
1030 efx_for_each_channel(channel, efx)
1031 efx_for_each_channel_tx_queue(tx_queue, channel)
1032 tx_queue->piobuf = NULL;
1035 #else /* !EFX_USE_PIO */
1037 static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
1039 return n == 0 ? 0 : -ENOBUFS;
1042 static int efx_ef10_link_piobufs(struct efx_nic *efx)
1047 static void efx_ef10_free_piobufs(struct efx_nic *efx)
1051 static void efx_ef10_forget_old_piobufs(struct efx_nic *efx)
1055 #endif /* EFX_USE_PIO */
1057 static void efx_ef10_remove(struct efx_nic *efx)
1059 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1062 #ifdef CONFIG_SFC_SRIOV
1063 struct efx_ef10_nic_data *nic_data_pf;
1064 struct pci_dev *pci_dev_pf;
1065 struct efx_nic *efx_pf;
1068 if (efx->pci_dev->is_virtfn) {
1069 pci_dev_pf = efx->pci_dev->physfn;
1071 efx_pf = pci_get_drvdata(pci_dev_pf);
1072 nic_data_pf = efx_pf->nic_data;
1073 vf = nic_data_pf->vf + nic_data->vf_index;
1076 netif_info(efx, drv, efx->net_dev,
1077 "Could not get the PF id from VF\n");
1081 efx_ef10_cleanup_vlans(efx);
1082 mutex_destroy(&nic_data->vlan_lock);
1084 efx_ptp_remove(efx);
1086 efx_mcdi_mon_remove(efx);
1088 efx_ef10_rx_free_indir_table(efx);
1090 if (nic_data->wc_membase)
1091 iounmap(nic_data->wc_membase);
1093 rc = efx_ef10_free_vis(efx);
1096 if (!nic_data->must_restore_piobufs)
1097 efx_ef10_free_piobufs(efx);
1099 device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
1100 device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag);
1102 efx_mcdi_detach(efx);
1104 memset(nic_data->udp_tunnels, 0, sizeof(nic_data->udp_tunnels));
1105 mutex_lock(&nic_data->udp_tunnels_lock);
1106 (void)efx_ef10_set_udp_tnl_ports(efx, true);
1107 mutex_unlock(&nic_data->udp_tunnels_lock);
1109 mutex_destroy(&nic_data->udp_tunnels_lock);
1112 efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
1116 static int efx_ef10_probe_pf(struct efx_nic *efx)
1118 return efx_ef10_probe(efx);
1121 int efx_ef10_vadaptor_query(struct efx_nic *efx, unsigned int port_id,
1122 u32 *port_flags, u32 *vadaptor_flags,
1123 unsigned int *vlan_tags)
1125 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1126 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_QUERY_IN_LEN);
1127 MCDI_DECLARE_BUF(outbuf, MC_CMD_VADAPTOR_QUERY_OUT_LEN);
1131 if (nic_data->datapath_caps &
1132 (1 << MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_LBN)) {
1133 MCDI_SET_DWORD(inbuf, VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID,
1136 rc = efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_QUERY, inbuf, sizeof(inbuf),
1137 outbuf, sizeof(outbuf), &outlen);
1141 if (outlen < sizeof(outbuf)) {
1148 *port_flags = MCDI_DWORD(outbuf, VADAPTOR_QUERY_OUT_PORT_FLAGS);
1151 MCDI_DWORD(outbuf, VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS);
1155 VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS);
1160 int efx_ef10_vadaptor_alloc(struct efx_nic *efx, unsigned int port_id)
1162 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_ALLOC_IN_LEN);
1164 MCDI_SET_DWORD(inbuf, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID, port_id);
1165 return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_ALLOC, inbuf, sizeof(inbuf),
1169 int efx_ef10_vadaptor_free(struct efx_nic *efx, unsigned int port_id)
1171 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_FREE_IN_LEN);
1173 MCDI_SET_DWORD(inbuf, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID, port_id);
1174 return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_FREE, inbuf, sizeof(inbuf),
1178 int efx_ef10_vport_add_mac(struct efx_nic *efx,
1179 unsigned int port_id, u8 *mac)
1181 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN);
1183 MCDI_SET_DWORD(inbuf, VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID, port_id);
1184 ether_addr_copy(MCDI_PTR(inbuf, VPORT_ADD_MAC_ADDRESS_IN_MACADDR), mac);
1186 return efx_mcdi_rpc(efx, MC_CMD_VPORT_ADD_MAC_ADDRESS, inbuf,
1187 sizeof(inbuf), NULL, 0, NULL);
1190 int efx_ef10_vport_del_mac(struct efx_nic *efx,
1191 unsigned int port_id, u8 *mac)
1193 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN);
1195 MCDI_SET_DWORD(inbuf, VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID, port_id);
1196 ether_addr_copy(MCDI_PTR(inbuf, VPORT_DEL_MAC_ADDRESS_IN_MACADDR), mac);
1198 return efx_mcdi_rpc(efx, MC_CMD_VPORT_DEL_MAC_ADDRESS, inbuf,
1199 sizeof(inbuf), NULL, 0, NULL);
1202 #ifdef CONFIG_SFC_SRIOV
1203 static int efx_ef10_probe_vf(struct efx_nic *efx)
1206 struct pci_dev *pci_dev_pf;
1208 /* If the parent PF has no VF data structure, it doesn't know about this
1209 * VF so fail probe. The VF needs to be re-created. This can happen
1210 * if the PF driver is unloaded while the VF is assigned to a guest.
1212 pci_dev_pf = efx->pci_dev->physfn;
1214 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
1215 struct efx_ef10_nic_data *nic_data_pf = efx_pf->nic_data;
1217 if (!nic_data_pf->vf) {
1218 netif_info(efx, drv, efx->net_dev,
1219 "The VF cannot link to its parent PF; "
1220 "please destroy and re-create the VF\n");
1225 rc = efx_ef10_probe(efx);
1229 rc = efx_ef10_get_vf_index(efx);
1233 if (efx->pci_dev->is_virtfn) {
1234 if (efx->pci_dev->physfn) {
1235 struct efx_nic *efx_pf =
1236 pci_get_drvdata(efx->pci_dev->physfn);
1237 struct efx_ef10_nic_data *nic_data_p = efx_pf->nic_data;
1238 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1240 nic_data_p->vf[nic_data->vf_index].efx = efx;
1241 nic_data_p->vf[nic_data->vf_index].pci_dev =
1244 netif_info(efx, drv, efx->net_dev,
1245 "Could not get the PF id from VF\n");
1251 efx_ef10_remove(efx);
1255 static int efx_ef10_probe_vf(struct efx_nic *efx __attribute__ ((unused)))
1261 static int efx_ef10_alloc_vis(struct efx_nic *efx,
1262 unsigned int min_vis, unsigned int max_vis)
1264 MCDI_DECLARE_BUF(inbuf, MC_CMD_ALLOC_VIS_IN_LEN);
1265 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_VIS_OUT_LEN);
1266 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1270 MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MIN_VI_COUNT, min_vis);
1271 MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MAX_VI_COUNT, max_vis);
1272 rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_VIS, inbuf, sizeof(inbuf),
1273 outbuf, sizeof(outbuf), &outlen);
1277 if (outlen < MC_CMD_ALLOC_VIS_OUT_LEN)
1280 netif_dbg(efx, drv, efx->net_dev, "base VI is A0x%03x\n",
1281 MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE));
1283 nic_data->vi_base = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE);
1284 nic_data->n_allocated_vis = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_COUNT);
1288 /* Note that the failure path of this function does not free
1289 * resources, as this will be done by efx_ef10_remove().
1291 static int efx_ef10_dimension_resources(struct efx_nic *efx)
1293 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1294 unsigned int uc_mem_map_size, wc_mem_map_size;
1295 unsigned int min_vis = max(EFX_TXQ_TYPES,
1296 efx_separate_tx_channels ? 2 : 1);
1297 unsigned int channel_vis, pio_write_vi_base, max_vis;
1298 void __iomem *membase;
1301 channel_vis = max(efx->n_channels,
1302 (efx->n_tx_channels + efx->n_extra_tx_channels) *
1306 /* Try to allocate PIO buffers if wanted and if the full
1307 * number of PIO buffers would be sufficient to allocate one
1308 * copy-buffer per TX channel. Failure is non-fatal, as there
1309 * are only a small number of PIO buffers shared between all
1310 * functions of the controller.
1312 if (efx_piobuf_size != 0 &&
1313 nic_data->piobuf_size / efx_piobuf_size * EF10_TX_PIOBUF_COUNT >=
1314 efx->n_tx_channels) {
1315 unsigned int n_piobufs =
1316 DIV_ROUND_UP(efx->n_tx_channels,
1317 nic_data->piobuf_size / efx_piobuf_size);
1319 rc = efx_ef10_alloc_piobufs(efx, n_piobufs);
1321 netif_dbg(efx, probe, efx->net_dev,
1322 "out of PIO buffers; cannot allocate more\n");
1323 else if (rc == -EPERM)
1324 netif_dbg(efx, probe, efx->net_dev,
1325 "not permitted to allocate PIO buffers\n");
1327 netif_err(efx, probe, efx->net_dev,
1328 "failed to allocate PIO buffers (%d)\n", rc);
1330 netif_dbg(efx, probe, efx->net_dev,
1331 "allocated %u PIO buffers\n", n_piobufs);
1334 nic_data->n_piobufs = 0;
1337 /* PIO buffers should be mapped with write-combining enabled,
1338 * and we want to make single UC and WC mappings rather than
1339 * several of each (in fact that's the only option if host
1340 * page size is >4K). So we may allocate some extra VIs just
1341 * for writing PIO buffers through.
1343 * The UC mapping contains (channel_vis - 1) complete VIs and the
1344 * first 4K of the next VI. Then the WC mapping begins with
1345 * the remainder of this last VI.
1347 uc_mem_map_size = PAGE_ALIGN((channel_vis - 1) * efx->vi_stride +
1349 if (nic_data->n_piobufs) {
1350 /* pio_write_vi_base rounds down to give the number of complete
1351 * VIs inside the UC mapping.
1353 pio_write_vi_base = uc_mem_map_size / efx->vi_stride;
1354 wc_mem_map_size = (PAGE_ALIGN((pio_write_vi_base +
1355 nic_data->n_piobufs) *
1358 max_vis = pio_write_vi_base + nic_data->n_piobufs;
1360 pio_write_vi_base = 0;
1361 wc_mem_map_size = 0;
1362 max_vis = channel_vis;
1365 /* In case the last attached driver failed to free VIs, do it now */
1366 rc = efx_ef10_free_vis(efx);
1370 rc = efx_ef10_alloc_vis(efx, min_vis, max_vis);
1374 if (nic_data->n_allocated_vis < channel_vis) {
1375 netif_info(efx, drv, efx->net_dev,
1376 "Could not allocate enough VIs to satisfy RSS"
1377 " requirements. Performance may not be optimal.\n");
1378 /* We didn't get the VIs to populate our channels.
1379 * We could keep what we got but then we'd have more
1380 * interrupts than we need.
1381 * Instead calculate new max_channels and restart
1383 efx->max_channels = nic_data->n_allocated_vis;
1384 efx->max_tx_channels =
1385 nic_data->n_allocated_vis / EFX_TXQ_TYPES;
1387 efx_ef10_free_vis(efx);
1391 /* If we didn't get enough VIs to map all the PIO buffers, free the
1394 if (nic_data->n_piobufs &&
1395 nic_data->n_allocated_vis <
1396 pio_write_vi_base + nic_data->n_piobufs) {
1397 netif_dbg(efx, probe, efx->net_dev,
1398 "%u VIs are not sufficient to map %u PIO buffers\n",
1399 nic_data->n_allocated_vis, nic_data->n_piobufs);
1400 efx_ef10_free_piobufs(efx);
1403 /* Shrink the original UC mapping of the memory BAR */
1404 membase = ioremap_nocache(efx->membase_phys, uc_mem_map_size);
1406 netif_err(efx, probe, efx->net_dev,
1407 "could not shrink memory BAR to %x\n",
1411 iounmap(efx->membase);
1412 efx->membase = membase;
1414 /* Set up the WC mapping if needed */
1415 if (wc_mem_map_size) {
1416 nic_data->wc_membase = ioremap_wc(efx->membase_phys +
1419 if (!nic_data->wc_membase) {
1420 netif_err(efx, probe, efx->net_dev,
1421 "could not allocate WC mapping of size %x\n",
1425 nic_data->pio_write_vi_base = pio_write_vi_base;
1426 nic_data->pio_write_base =
1427 nic_data->wc_membase +
1428 (pio_write_vi_base * efx->vi_stride + ER_DZ_TX_PIOBUF -
1431 rc = efx_ef10_link_piobufs(efx);
1433 efx_ef10_free_piobufs(efx);
1436 netif_dbg(efx, probe, efx->net_dev,
1437 "memory BAR at %pa (virtual %p+%x UC, %p+%x WC)\n",
1438 &efx->membase_phys, efx->membase, uc_mem_map_size,
1439 nic_data->wc_membase, wc_mem_map_size);
1444 static int efx_ef10_init_nic(struct efx_nic *efx)
1446 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1449 if (nic_data->must_check_datapath_caps) {
1450 rc = efx_ef10_init_datapath_caps(efx);
1453 nic_data->must_check_datapath_caps = false;
1456 if (nic_data->must_realloc_vis) {
1457 /* We cannot let the number of VIs change now */
1458 rc = efx_ef10_alloc_vis(efx, nic_data->n_allocated_vis,
1459 nic_data->n_allocated_vis);
1462 nic_data->must_realloc_vis = false;
1465 if (nic_data->must_restore_piobufs && nic_data->n_piobufs) {
1466 rc = efx_ef10_alloc_piobufs(efx, nic_data->n_piobufs);
1468 rc = efx_ef10_link_piobufs(efx);
1470 efx_ef10_free_piobufs(efx);
1473 /* Log an error on failure, but this is non-fatal.
1474 * Permission errors are less important - we've presumably
1475 * had the PIO buffer licence removed.
1478 netif_dbg(efx, drv, efx->net_dev,
1479 "not permitted to restore PIO buffers\n");
1481 netif_err(efx, drv, efx->net_dev,
1482 "failed to restore PIO buffers (%d)\n", rc);
1483 nic_data->must_restore_piobufs = false;
1486 /* don't fail init if RSS setup doesn't work */
1487 rc = efx->type->rx_push_rss_config(efx, false,
1488 efx->rss_context.rx_indir_table, NULL);
1493 static void efx_ef10_reset_mc_allocations(struct efx_nic *efx)
1495 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1496 #ifdef CONFIG_SFC_SRIOV
1500 /* All our allocations have been reset */
1501 nic_data->must_realloc_vis = true;
1502 nic_data->must_restore_rss_contexts = true;
1503 nic_data->must_restore_filters = true;
1504 nic_data->must_restore_piobufs = true;
1505 efx_ef10_forget_old_piobufs(efx);
1506 efx->rss_context.context_id = EFX_EF10_RSS_CONTEXT_INVALID;
1508 /* Driver-created vswitches and vports must be re-created */
1509 nic_data->must_probe_vswitching = true;
1510 nic_data->vport_id = EVB_PORT_ID_ASSIGNED;
1511 #ifdef CONFIG_SFC_SRIOV
1513 for (i = 0; i < efx->vf_count; i++)
1514 nic_data->vf[i].vport_id = 0;
1518 static enum reset_type efx_ef10_map_reset_reason(enum reset_type reason)
1520 if (reason == RESET_TYPE_MC_FAILURE)
1521 return RESET_TYPE_DATAPATH;
1523 return efx_mcdi_map_reset_reason(reason);
1526 static int efx_ef10_map_reset_flags(u32 *flags)
1529 EF10_RESET_PORT = ((ETH_RESET_MAC | ETH_RESET_PHY) <<
1530 ETH_RESET_SHARED_SHIFT),
1531 EF10_RESET_MC = ((ETH_RESET_DMA | ETH_RESET_FILTER |
1532 ETH_RESET_OFFLOAD | ETH_RESET_MAC |
1533 ETH_RESET_PHY | ETH_RESET_MGMT) <<
1534 ETH_RESET_SHARED_SHIFT)
1537 /* We assume for now that our PCI function is permitted to
1541 if ((*flags & EF10_RESET_MC) == EF10_RESET_MC) {
1542 *flags &= ~EF10_RESET_MC;
1543 return RESET_TYPE_WORLD;
1546 if ((*flags & EF10_RESET_PORT) == EF10_RESET_PORT) {
1547 *flags &= ~EF10_RESET_PORT;
1548 return RESET_TYPE_ALL;
1551 /* no invisible reset implemented */
1556 static int efx_ef10_reset(struct efx_nic *efx, enum reset_type reset_type)
1558 int rc = efx_mcdi_reset(efx, reset_type);
1560 /* Unprivileged functions return -EPERM, but need to return success
1561 * here so that the datapath is brought back up.
1563 if (reset_type == RESET_TYPE_WORLD && rc == -EPERM)
1566 /* If it was a port reset, trigger reallocation of MC resources.
1567 * Note that on an MC reset nothing needs to be done now because we'll
1568 * detect the MC reset later and handle it then.
1569 * For an FLR, we never get an MC reset event, but the MC has reset all
1570 * resources assigned to us, so we have to trigger reallocation now.
1572 if ((reset_type == RESET_TYPE_ALL ||
1573 reset_type == RESET_TYPE_MCDI_TIMEOUT) && !rc)
1574 efx_ef10_reset_mc_allocations(efx);
1578 #define EF10_DMA_STAT(ext_name, mcdi_name) \
1579 [EF10_STAT_ ## ext_name] = \
1580 { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
1581 #define EF10_DMA_INVIS_STAT(int_name, mcdi_name) \
1582 [EF10_STAT_ ## int_name] = \
1583 { NULL, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
1584 #define EF10_OTHER_STAT(ext_name) \
1585 [EF10_STAT_ ## ext_name] = { #ext_name, 0, 0 }
1586 #define GENERIC_SW_STAT(ext_name) \
1587 [GENERIC_STAT_ ## ext_name] = { #ext_name, 0, 0 }
1589 static const struct efx_hw_stat_desc efx_ef10_stat_desc[EF10_STAT_COUNT] = {
1590 EF10_DMA_STAT(port_tx_bytes, TX_BYTES),
1591 EF10_DMA_STAT(port_tx_packets, TX_PKTS),
1592 EF10_DMA_STAT(port_tx_pause, TX_PAUSE_PKTS),
1593 EF10_DMA_STAT(port_tx_control, TX_CONTROL_PKTS),
1594 EF10_DMA_STAT(port_tx_unicast, TX_UNICAST_PKTS),
1595 EF10_DMA_STAT(port_tx_multicast, TX_MULTICAST_PKTS),
1596 EF10_DMA_STAT(port_tx_broadcast, TX_BROADCAST_PKTS),
1597 EF10_DMA_STAT(port_tx_lt64, TX_LT64_PKTS),
1598 EF10_DMA_STAT(port_tx_64, TX_64_PKTS),
1599 EF10_DMA_STAT(port_tx_65_to_127, TX_65_TO_127_PKTS),
1600 EF10_DMA_STAT(port_tx_128_to_255, TX_128_TO_255_PKTS),
1601 EF10_DMA_STAT(port_tx_256_to_511, TX_256_TO_511_PKTS),
1602 EF10_DMA_STAT(port_tx_512_to_1023, TX_512_TO_1023_PKTS),
1603 EF10_DMA_STAT(port_tx_1024_to_15xx, TX_1024_TO_15XX_PKTS),
1604 EF10_DMA_STAT(port_tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS),
1605 EF10_DMA_STAT(port_rx_bytes, RX_BYTES),
1606 EF10_DMA_INVIS_STAT(port_rx_bytes_minus_good_bytes, RX_BAD_BYTES),
1607 EF10_OTHER_STAT(port_rx_good_bytes),
1608 EF10_OTHER_STAT(port_rx_bad_bytes),
1609 EF10_DMA_STAT(port_rx_packets, RX_PKTS),
1610 EF10_DMA_STAT(port_rx_good, RX_GOOD_PKTS),
1611 EF10_DMA_STAT(port_rx_bad, RX_BAD_FCS_PKTS),
1612 EF10_DMA_STAT(port_rx_pause, RX_PAUSE_PKTS),
1613 EF10_DMA_STAT(port_rx_control, RX_CONTROL_PKTS),
1614 EF10_DMA_STAT(port_rx_unicast, RX_UNICAST_PKTS),
1615 EF10_DMA_STAT(port_rx_multicast, RX_MULTICAST_PKTS),
1616 EF10_DMA_STAT(port_rx_broadcast, RX_BROADCAST_PKTS),
1617 EF10_DMA_STAT(port_rx_lt64, RX_UNDERSIZE_PKTS),
1618 EF10_DMA_STAT(port_rx_64, RX_64_PKTS),
1619 EF10_DMA_STAT(port_rx_65_to_127, RX_65_TO_127_PKTS),
1620 EF10_DMA_STAT(port_rx_128_to_255, RX_128_TO_255_PKTS),
1621 EF10_DMA_STAT(port_rx_256_to_511, RX_256_TO_511_PKTS),
1622 EF10_DMA_STAT(port_rx_512_to_1023, RX_512_TO_1023_PKTS),
1623 EF10_DMA_STAT(port_rx_1024_to_15xx, RX_1024_TO_15XX_PKTS),
1624 EF10_DMA_STAT(port_rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS),
1625 EF10_DMA_STAT(port_rx_gtjumbo, RX_GTJUMBO_PKTS),
1626 EF10_DMA_STAT(port_rx_bad_gtjumbo, RX_JABBER_PKTS),
1627 EF10_DMA_STAT(port_rx_overflow, RX_OVERFLOW_PKTS),
1628 EF10_DMA_STAT(port_rx_align_error, RX_ALIGN_ERROR_PKTS),
1629 EF10_DMA_STAT(port_rx_length_error, RX_LENGTH_ERROR_PKTS),
1630 EF10_DMA_STAT(port_rx_nodesc_drops, RX_NODESC_DROPS),
1631 GENERIC_SW_STAT(rx_nodesc_trunc),
1632 GENERIC_SW_STAT(rx_noskb_drops),
1633 EF10_DMA_STAT(port_rx_pm_trunc_bb_overflow, PM_TRUNC_BB_OVERFLOW),
1634 EF10_DMA_STAT(port_rx_pm_discard_bb_overflow, PM_DISCARD_BB_OVERFLOW),
1635 EF10_DMA_STAT(port_rx_pm_trunc_vfifo_full, PM_TRUNC_VFIFO_FULL),
1636 EF10_DMA_STAT(port_rx_pm_discard_vfifo_full, PM_DISCARD_VFIFO_FULL),
1637 EF10_DMA_STAT(port_rx_pm_trunc_qbb, PM_TRUNC_QBB),
1638 EF10_DMA_STAT(port_rx_pm_discard_qbb, PM_DISCARD_QBB),
1639 EF10_DMA_STAT(port_rx_pm_discard_mapping, PM_DISCARD_MAPPING),
1640 EF10_DMA_STAT(port_rx_dp_q_disabled_packets, RXDP_Q_DISABLED_PKTS),
1641 EF10_DMA_STAT(port_rx_dp_di_dropped_packets, RXDP_DI_DROPPED_PKTS),
1642 EF10_DMA_STAT(port_rx_dp_streaming_packets, RXDP_STREAMING_PKTS),
1643 EF10_DMA_STAT(port_rx_dp_hlb_fetch, RXDP_HLB_FETCH_CONDITIONS),
1644 EF10_DMA_STAT(port_rx_dp_hlb_wait, RXDP_HLB_WAIT_CONDITIONS),
1645 EF10_DMA_STAT(rx_unicast, VADAPTER_RX_UNICAST_PACKETS),
1646 EF10_DMA_STAT(rx_unicast_bytes, VADAPTER_RX_UNICAST_BYTES),
1647 EF10_DMA_STAT(rx_multicast, VADAPTER_RX_MULTICAST_PACKETS),
1648 EF10_DMA_STAT(rx_multicast_bytes, VADAPTER_RX_MULTICAST_BYTES),
1649 EF10_DMA_STAT(rx_broadcast, VADAPTER_RX_BROADCAST_PACKETS),
1650 EF10_DMA_STAT(rx_broadcast_bytes, VADAPTER_RX_BROADCAST_BYTES),
1651 EF10_DMA_STAT(rx_bad, VADAPTER_RX_BAD_PACKETS),
1652 EF10_DMA_STAT(rx_bad_bytes, VADAPTER_RX_BAD_BYTES),
1653 EF10_DMA_STAT(rx_overflow, VADAPTER_RX_OVERFLOW),
1654 EF10_DMA_STAT(tx_unicast, VADAPTER_TX_UNICAST_PACKETS),
1655 EF10_DMA_STAT(tx_unicast_bytes, VADAPTER_TX_UNICAST_BYTES),
1656 EF10_DMA_STAT(tx_multicast, VADAPTER_TX_MULTICAST_PACKETS),
1657 EF10_DMA_STAT(tx_multicast_bytes, VADAPTER_TX_MULTICAST_BYTES),
1658 EF10_DMA_STAT(tx_broadcast, VADAPTER_TX_BROADCAST_PACKETS),
1659 EF10_DMA_STAT(tx_broadcast_bytes, VADAPTER_TX_BROADCAST_BYTES),
1660 EF10_DMA_STAT(tx_bad, VADAPTER_TX_BAD_PACKETS),
1661 EF10_DMA_STAT(tx_bad_bytes, VADAPTER_TX_BAD_BYTES),
1662 EF10_DMA_STAT(tx_overflow, VADAPTER_TX_OVERFLOW),
1663 EF10_DMA_STAT(fec_uncorrected_errors, FEC_UNCORRECTED_ERRORS),
1664 EF10_DMA_STAT(fec_corrected_errors, FEC_CORRECTED_ERRORS),
1665 EF10_DMA_STAT(fec_corrected_symbols_lane0, FEC_CORRECTED_SYMBOLS_LANE0),
1666 EF10_DMA_STAT(fec_corrected_symbols_lane1, FEC_CORRECTED_SYMBOLS_LANE1),
1667 EF10_DMA_STAT(fec_corrected_symbols_lane2, FEC_CORRECTED_SYMBOLS_LANE2),
1668 EF10_DMA_STAT(fec_corrected_symbols_lane3, FEC_CORRECTED_SYMBOLS_LANE3),
1669 EF10_DMA_STAT(ctpio_vi_busy_fallback, CTPIO_VI_BUSY_FALLBACK),
1670 EF10_DMA_STAT(ctpio_long_write_success, CTPIO_LONG_WRITE_SUCCESS),
1671 EF10_DMA_STAT(ctpio_missing_dbell_fail, CTPIO_MISSING_DBELL_FAIL),
1672 EF10_DMA_STAT(ctpio_overflow_fail, CTPIO_OVERFLOW_FAIL),
1673 EF10_DMA_STAT(ctpio_underflow_fail, CTPIO_UNDERFLOW_FAIL),
1674 EF10_DMA_STAT(ctpio_timeout_fail, CTPIO_TIMEOUT_FAIL),
1675 EF10_DMA_STAT(ctpio_noncontig_wr_fail, CTPIO_NONCONTIG_WR_FAIL),
1676 EF10_DMA_STAT(ctpio_frm_clobber_fail, CTPIO_FRM_CLOBBER_FAIL),
1677 EF10_DMA_STAT(ctpio_invalid_wr_fail, CTPIO_INVALID_WR_FAIL),
1678 EF10_DMA_STAT(ctpio_vi_clobber_fallback, CTPIO_VI_CLOBBER_FALLBACK),
1679 EF10_DMA_STAT(ctpio_unqualified_fallback, CTPIO_UNQUALIFIED_FALLBACK),
1680 EF10_DMA_STAT(ctpio_runt_fallback, CTPIO_RUNT_FALLBACK),
1681 EF10_DMA_STAT(ctpio_success, CTPIO_SUCCESS),
1682 EF10_DMA_STAT(ctpio_fallback, CTPIO_FALLBACK),
1683 EF10_DMA_STAT(ctpio_poison, CTPIO_POISON),
1684 EF10_DMA_STAT(ctpio_erase, CTPIO_ERASE),
1687 #define HUNT_COMMON_STAT_MASK ((1ULL << EF10_STAT_port_tx_bytes) | \
1688 (1ULL << EF10_STAT_port_tx_packets) | \
1689 (1ULL << EF10_STAT_port_tx_pause) | \
1690 (1ULL << EF10_STAT_port_tx_unicast) | \
1691 (1ULL << EF10_STAT_port_tx_multicast) | \
1692 (1ULL << EF10_STAT_port_tx_broadcast) | \
1693 (1ULL << EF10_STAT_port_rx_bytes) | \
1695 EF10_STAT_port_rx_bytes_minus_good_bytes) | \
1696 (1ULL << EF10_STAT_port_rx_good_bytes) | \
1697 (1ULL << EF10_STAT_port_rx_bad_bytes) | \
1698 (1ULL << EF10_STAT_port_rx_packets) | \
1699 (1ULL << EF10_STAT_port_rx_good) | \
1700 (1ULL << EF10_STAT_port_rx_bad) | \
1701 (1ULL << EF10_STAT_port_rx_pause) | \
1702 (1ULL << EF10_STAT_port_rx_control) | \
1703 (1ULL << EF10_STAT_port_rx_unicast) | \
1704 (1ULL << EF10_STAT_port_rx_multicast) | \
1705 (1ULL << EF10_STAT_port_rx_broadcast) | \
1706 (1ULL << EF10_STAT_port_rx_lt64) | \
1707 (1ULL << EF10_STAT_port_rx_64) | \
1708 (1ULL << EF10_STAT_port_rx_65_to_127) | \
1709 (1ULL << EF10_STAT_port_rx_128_to_255) | \
1710 (1ULL << EF10_STAT_port_rx_256_to_511) | \
1711 (1ULL << EF10_STAT_port_rx_512_to_1023) |\
1712 (1ULL << EF10_STAT_port_rx_1024_to_15xx) |\
1713 (1ULL << EF10_STAT_port_rx_15xx_to_jumbo) |\
1714 (1ULL << EF10_STAT_port_rx_gtjumbo) | \
1715 (1ULL << EF10_STAT_port_rx_bad_gtjumbo) |\
1716 (1ULL << EF10_STAT_port_rx_overflow) | \
1717 (1ULL << EF10_STAT_port_rx_nodesc_drops) |\
1718 (1ULL << GENERIC_STAT_rx_nodesc_trunc) | \
1719 (1ULL << GENERIC_STAT_rx_noskb_drops))
1721 /* On 7000 series NICs, these statistics are only provided by the 10G MAC.
1722 * For a 10G/40G switchable port we do not expose these because they might
1723 * not include all the packets they should.
1724 * On 8000 series NICs these statistics are always provided.
1726 #define HUNT_10G_ONLY_STAT_MASK ((1ULL << EF10_STAT_port_tx_control) | \
1727 (1ULL << EF10_STAT_port_tx_lt64) | \
1728 (1ULL << EF10_STAT_port_tx_64) | \
1729 (1ULL << EF10_STAT_port_tx_65_to_127) |\
1730 (1ULL << EF10_STAT_port_tx_128_to_255) |\
1731 (1ULL << EF10_STAT_port_tx_256_to_511) |\
1732 (1ULL << EF10_STAT_port_tx_512_to_1023) |\
1733 (1ULL << EF10_STAT_port_tx_1024_to_15xx) |\
1734 (1ULL << EF10_STAT_port_tx_15xx_to_jumbo))
1736 /* These statistics are only provided by the 40G MAC. For a 10G/40G
1737 * switchable port we do expose these because the errors will otherwise
1740 #define HUNT_40G_EXTRA_STAT_MASK ((1ULL << EF10_STAT_port_rx_align_error) |\
1741 (1ULL << EF10_STAT_port_rx_length_error))
1743 /* These statistics are only provided if the firmware supports the
1744 * capability PM_AND_RXDP_COUNTERS.
1746 #define HUNT_PM_AND_RXDP_STAT_MASK ( \
1747 (1ULL << EF10_STAT_port_rx_pm_trunc_bb_overflow) | \
1748 (1ULL << EF10_STAT_port_rx_pm_discard_bb_overflow) | \
1749 (1ULL << EF10_STAT_port_rx_pm_trunc_vfifo_full) | \
1750 (1ULL << EF10_STAT_port_rx_pm_discard_vfifo_full) | \
1751 (1ULL << EF10_STAT_port_rx_pm_trunc_qbb) | \
1752 (1ULL << EF10_STAT_port_rx_pm_discard_qbb) | \
1753 (1ULL << EF10_STAT_port_rx_pm_discard_mapping) | \
1754 (1ULL << EF10_STAT_port_rx_dp_q_disabled_packets) | \
1755 (1ULL << EF10_STAT_port_rx_dp_di_dropped_packets) | \
1756 (1ULL << EF10_STAT_port_rx_dp_streaming_packets) | \
1757 (1ULL << EF10_STAT_port_rx_dp_hlb_fetch) | \
1758 (1ULL << EF10_STAT_port_rx_dp_hlb_wait))
1760 /* These statistics are only provided if the NIC supports MC_CMD_MAC_STATS_V2,
1761 * indicated by returning a value >= MC_CMD_MAC_NSTATS_V2 in
1762 * MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS.
1763 * These bits are in the second u64 of the raw mask.
1765 #define EF10_FEC_STAT_MASK ( \
1766 (1ULL << (EF10_STAT_fec_uncorrected_errors - 64)) | \
1767 (1ULL << (EF10_STAT_fec_corrected_errors - 64)) | \
1768 (1ULL << (EF10_STAT_fec_corrected_symbols_lane0 - 64)) | \
1769 (1ULL << (EF10_STAT_fec_corrected_symbols_lane1 - 64)) | \
1770 (1ULL << (EF10_STAT_fec_corrected_symbols_lane2 - 64)) | \
1771 (1ULL << (EF10_STAT_fec_corrected_symbols_lane3 - 64)))
1773 /* These statistics are only provided if the NIC supports MC_CMD_MAC_STATS_V3,
1774 * indicated by returning a value >= MC_CMD_MAC_NSTATS_V3 in
1775 * MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS.
1776 * These bits are in the second u64 of the raw mask.
1778 #define EF10_CTPIO_STAT_MASK ( \
1779 (1ULL << (EF10_STAT_ctpio_vi_busy_fallback - 64)) | \
1780 (1ULL << (EF10_STAT_ctpio_long_write_success - 64)) | \
1781 (1ULL << (EF10_STAT_ctpio_missing_dbell_fail - 64)) | \
1782 (1ULL << (EF10_STAT_ctpio_overflow_fail - 64)) | \
1783 (1ULL << (EF10_STAT_ctpio_underflow_fail - 64)) | \
1784 (1ULL << (EF10_STAT_ctpio_timeout_fail - 64)) | \
1785 (1ULL << (EF10_STAT_ctpio_noncontig_wr_fail - 64)) | \
1786 (1ULL << (EF10_STAT_ctpio_frm_clobber_fail - 64)) | \
1787 (1ULL << (EF10_STAT_ctpio_invalid_wr_fail - 64)) | \
1788 (1ULL << (EF10_STAT_ctpio_vi_clobber_fallback - 64)) | \
1789 (1ULL << (EF10_STAT_ctpio_unqualified_fallback - 64)) | \
1790 (1ULL << (EF10_STAT_ctpio_runt_fallback - 64)) | \
1791 (1ULL << (EF10_STAT_ctpio_success - 64)) | \
1792 (1ULL << (EF10_STAT_ctpio_fallback - 64)) | \
1793 (1ULL << (EF10_STAT_ctpio_poison - 64)) | \
1794 (1ULL << (EF10_STAT_ctpio_erase - 64)))
1796 static u64 efx_ef10_raw_stat_mask(struct efx_nic *efx)
1798 u64 raw_mask = HUNT_COMMON_STAT_MASK;
1799 u32 port_caps = efx_mcdi_phy_get_caps(efx);
1800 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1802 if (!(efx->mcdi->fn_flags &
1803 1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL))
1806 if (port_caps & (1 << MC_CMD_PHY_CAP_40000FDX_LBN)) {
1807 raw_mask |= HUNT_40G_EXTRA_STAT_MASK;
1808 /* 8000 series have everything even at 40G */
1809 if (nic_data->datapath_caps2 &
1810 (1 << MC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN))
1811 raw_mask |= HUNT_10G_ONLY_STAT_MASK;
1813 raw_mask |= HUNT_10G_ONLY_STAT_MASK;
1816 if (nic_data->datapath_caps &
1817 (1 << MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN))
1818 raw_mask |= HUNT_PM_AND_RXDP_STAT_MASK;
1823 static void efx_ef10_get_stat_mask(struct efx_nic *efx, unsigned long *mask)
1825 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1828 raw_mask[0] = efx_ef10_raw_stat_mask(efx);
1830 /* Only show vadaptor stats when EVB capability is present */
1831 if (nic_data->datapath_caps &
1832 (1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN)) {
1833 raw_mask[0] |= ~((1ULL << EF10_STAT_rx_unicast) - 1);
1834 raw_mask[1] = (1ULL << (EF10_STAT_V1_COUNT - 64)) - 1;
1838 /* Only show FEC stats when NIC supports MC_CMD_MAC_STATS_V2 */
1839 if (efx->num_mac_stats >= MC_CMD_MAC_NSTATS_V2)
1840 raw_mask[1] |= EF10_FEC_STAT_MASK;
1842 /* CTPIO stats appear in V3. Only show them on devices that actually
1843 * support CTPIO. Although this driver doesn't use CTPIO others might,
1844 * and we may be reporting the stats for the underlying port.
1846 if (efx->num_mac_stats >= MC_CMD_MAC_NSTATS_V3 &&
1847 (nic_data->datapath_caps2 &
1848 (1 << MC_CMD_GET_CAPABILITIES_V4_OUT_CTPIO_LBN)))
1849 raw_mask[1] |= EF10_CTPIO_STAT_MASK;
1851 #if BITS_PER_LONG == 64
1852 BUILD_BUG_ON(BITS_TO_LONGS(EF10_STAT_COUNT) != 2);
1853 mask[0] = raw_mask[0];
1854 mask[1] = raw_mask[1];
1856 BUILD_BUG_ON(BITS_TO_LONGS(EF10_STAT_COUNT) != 3);
1857 mask[0] = raw_mask[0] & 0xffffffff;
1858 mask[1] = raw_mask[0] >> 32;
1859 mask[2] = raw_mask[1] & 0xffffffff;
1863 static size_t efx_ef10_describe_stats(struct efx_nic *efx, u8 *names)
1865 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1867 efx_ef10_get_stat_mask(efx, mask);
1868 return efx_nic_describe_stats(efx_ef10_stat_desc, EF10_STAT_COUNT,
1872 static size_t efx_ef10_update_stats_common(struct efx_nic *efx, u64 *full_stats,
1873 struct rtnl_link_stats64 *core_stats)
1875 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1876 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1877 u64 *stats = nic_data->stats;
1878 size_t stats_count = 0, index;
1880 efx_ef10_get_stat_mask(efx, mask);
1883 for_each_set_bit(index, mask, EF10_STAT_COUNT) {
1884 if (efx_ef10_stat_desc[index].name) {
1885 *full_stats++ = stats[index];
1894 if (nic_data->datapath_caps &
1895 1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN) {
1896 /* Use vadaptor stats. */
1897 core_stats->rx_packets = stats[EF10_STAT_rx_unicast] +
1898 stats[EF10_STAT_rx_multicast] +
1899 stats[EF10_STAT_rx_broadcast];
1900 core_stats->tx_packets = stats[EF10_STAT_tx_unicast] +
1901 stats[EF10_STAT_tx_multicast] +
1902 stats[EF10_STAT_tx_broadcast];
1903 core_stats->rx_bytes = stats[EF10_STAT_rx_unicast_bytes] +
1904 stats[EF10_STAT_rx_multicast_bytes] +
1905 stats[EF10_STAT_rx_broadcast_bytes];
1906 core_stats->tx_bytes = stats[EF10_STAT_tx_unicast_bytes] +
1907 stats[EF10_STAT_tx_multicast_bytes] +
1908 stats[EF10_STAT_tx_broadcast_bytes];
1909 core_stats->rx_dropped = stats[GENERIC_STAT_rx_nodesc_trunc] +
1910 stats[GENERIC_STAT_rx_noskb_drops];
1911 core_stats->multicast = stats[EF10_STAT_rx_multicast];
1912 core_stats->rx_crc_errors = stats[EF10_STAT_rx_bad];
1913 core_stats->rx_fifo_errors = stats[EF10_STAT_rx_overflow];
1914 core_stats->rx_errors = core_stats->rx_crc_errors;
1915 core_stats->tx_errors = stats[EF10_STAT_tx_bad];
1917 /* Use port stats. */
1918 core_stats->rx_packets = stats[EF10_STAT_port_rx_packets];
1919 core_stats->tx_packets = stats[EF10_STAT_port_tx_packets];
1920 core_stats->rx_bytes = stats[EF10_STAT_port_rx_bytes];
1921 core_stats->tx_bytes = stats[EF10_STAT_port_tx_bytes];
1922 core_stats->rx_dropped = stats[EF10_STAT_port_rx_nodesc_drops] +
1923 stats[GENERIC_STAT_rx_nodesc_trunc] +
1924 stats[GENERIC_STAT_rx_noskb_drops];
1925 core_stats->multicast = stats[EF10_STAT_port_rx_multicast];
1926 core_stats->rx_length_errors =
1927 stats[EF10_STAT_port_rx_gtjumbo] +
1928 stats[EF10_STAT_port_rx_length_error];
1929 core_stats->rx_crc_errors = stats[EF10_STAT_port_rx_bad];
1930 core_stats->rx_frame_errors =
1931 stats[EF10_STAT_port_rx_align_error];
1932 core_stats->rx_fifo_errors = stats[EF10_STAT_port_rx_overflow];
1933 core_stats->rx_errors = (core_stats->rx_length_errors +
1934 core_stats->rx_crc_errors +
1935 core_stats->rx_frame_errors);
1941 static int efx_ef10_try_update_nic_stats_pf(struct efx_nic *efx)
1943 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1944 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1945 __le64 generation_start, generation_end;
1946 u64 *stats = nic_data->stats;
1949 efx_ef10_get_stat_mask(efx, mask);
1951 dma_stats = efx->stats_buffer.addr;
1953 generation_end = dma_stats[efx->num_mac_stats - 1];
1954 if (generation_end == EFX_MC_STATS_GENERATION_INVALID)
1957 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask,
1958 stats, efx->stats_buffer.addr, false);
1960 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
1961 if (generation_end != generation_start)
1964 /* Update derived statistics */
1965 efx_nic_fix_nodesc_drop_stat(efx,
1966 &stats[EF10_STAT_port_rx_nodesc_drops]);
1967 stats[EF10_STAT_port_rx_good_bytes] =
1968 stats[EF10_STAT_port_rx_bytes] -
1969 stats[EF10_STAT_port_rx_bytes_minus_good_bytes];
1970 efx_update_diff_stat(&stats[EF10_STAT_port_rx_bad_bytes],
1971 stats[EF10_STAT_port_rx_bytes_minus_good_bytes]);
1972 efx_update_sw_stats(efx, stats);
1977 static size_t efx_ef10_update_stats_pf(struct efx_nic *efx, u64 *full_stats,
1978 struct rtnl_link_stats64 *core_stats)
1982 /* If we're unlucky enough to read statistics during the DMA, wait
1983 * up to 10ms for it to finish (typically takes <500us)
1985 for (retry = 0; retry < 100; ++retry) {
1986 if (efx_ef10_try_update_nic_stats_pf(efx) == 0)
1991 return efx_ef10_update_stats_common(efx, full_stats, core_stats);
1994 static int efx_ef10_try_update_nic_stats_vf(struct efx_nic *efx)
1996 MCDI_DECLARE_BUF(inbuf, MC_CMD_MAC_STATS_IN_LEN);
1997 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1998 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1999 __le64 generation_start, generation_end;
2000 u64 *stats = nic_data->stats;
2001 u32 dma_len = efx->num_mac_stats * sizeof(u64);
2002 struct efx_buffer stats_buf;
2006 spin_unlock_bh(&efx->stats_lock);
2008 if (in_interrupt()) {
2009 /* If in atomic context, cannot update stats. Just update the
2010 * software stats and return so the caller can continue.
2012 spin_lock_bh(&efx->stats_lock);
2013 efx_update_sw_stats(efx, stats);
2017 efx_ef10_get_stat_mask(efx, mask);
2019 rc = efx_nic_alloc_buffer(efx, &stats_buf, dma_len, GFP_ATOMIC);
2021 spin_lock_bh(&efx->stats_lock);
2025 dma_stats = stats_buf.addr;
2026 dma_stats[efx->num_mac_stats - 1] = EFX_MC_STATS_GENERATION_INVALID;
2028 MCDI_SET_QWORD(inbuf, MAC_STATS_IN_DMA_ADDR, stats_buf.dma_addr);
2029 MCDI_POPULATE_DWORD_1(inbuf, MAC_STATS_IN_CMD,
2030 MAC_STATS_IN_DMA, 1);
2031 MCDI_SET_DWORD(inbuf, MAC_STATS_IN_DMA_LEN, dma_len);
2032 MCDI_SET_DWORD(inbuf, MAC_STATS_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
2034 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_MAC_STATS, inbuf, sizeof(inbuf),
2036 spin_lock_bh(&efx->stats_lock);
2038 /* Expect ENOENT if DMA queues have not been set up */
2039 if (rc != -ENOENT || atomic_read(&efx->active_queues))
2040 efx_mcdi_display_error(efx, MC_CMD_MAC_STATS,
2041 sizeof(inbuf), NULL, 0, rc);
2045 generation_end = dma_stats[efx->num_mac_stats - 1];
2046 if (generation_end == EFX_MC_STATS_GENERATION_INVALID) {
2051 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask,
2052 stats, stats_buf.addr, false);
2054 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
2055 if (generation_end != generation_start) {
2060 efx_update_sw_stats(efx, stats);
2062 efx_nic_free_buffer(efx, &stats_buf);
2066 static size_t efx_ef10_update_stats_vf(struct efx_nic *efx, u64 *full_stats,
2067 struct rtnl_link_stats64 *core_stats)
2069 if (efx_ef10_try_update_nic_stats_vf(efx))
2072 return efx_ef10_update_stats_common(efx, full_stats, core_stats);
2075 static void efx_ef10_push_irq_moderation(struct efx_channel *channel)
2077 struct efx_nic *efx = channel->efx;
2078 unsigned int mode, usecs;
2079 efx_dword_t timer_cmd;
2081 if (channel->irq_moderation_us) {
2083 usecs = channel->irq_moderation_us;
2089 if (EFX_EF10_WORKAROUND_61265(efx)) {
2090 MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_EVQ_TMR_IN_LEN);
2091 unsigned int ns = usecs * 1000;
2093 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_INSTANCE,
2095 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_LOAD_REQ_NS, ns);
2096 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_RELOAD_REQ_NS, ns);
2097 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_MODE, mode);
2099 efx_mcdi_rpc_async(efx, MC_CMD_SET_EVQ_TMR,
2100 inbuf, sizeof(inbuf), 0, NULL, 0);
2101 } else if (EFX_EF10_WORKAROUND_35388(efx)) {
2102 unsigned int ticks = efx_usecs_to_ticks(efx, usecs);
2104 EFX_POPULATE_DWORD_3(timer_cmd, ERF_DD_EVQ_IND_TIMER_FLAGS,
2105 EFE_DD_EVQ_IND_TIMER_FLAGS,
2106 ERF_DD_EVQ_IND_TIMER_MODE, mode,
2107 ERF_DD_EVQ_IND_TIMER_VAL, ticks);
2108 efx_writed_page(efx, &timer_cmd, ER_DD_EVQ_INDIRECT,
2111 unsigned int ticks = efx_usecs_to_ticks(efx, usecs);
2113 EFX_POPULATE_DWORD_3(timer_cmd, ERF_DZ_TC_TIMER_MODE, mode,
2114 ERF_DZ_TC_TIMER_VAL, ticks,
2115 ERF_FZ_TC_TMR_REL_VAL, ticks);
2116 efx_writed_page(efx, &timer_cmd, ER_DZ_EVQ_TMR,
2121 static void efx_ef10_get_wol_vf(struct efx_nic *efx,
2122 struct ethtool_wolinfo *wol) {}
2124 static int efx_ef10_set_wol_vf(struct efx_nic *efx, u32 type)
2129 static void efx_ef10_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
2133 memset(&wol->sopass, 0, sizeof(wol->sopass));
2136 static int efx_ef10_set_wol(struct efx_nic *efx, u32 type)
2143 static void efx_ef10_mcdi_request(struct efx_nic *efx,
2144 const efx_dword_t *hdr, size_t hdr_len,
2145 const efx_dword_t *sdu, size_t sdu_len)
2147 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2148 u8 *pdu = nic_data->mcdi_buf.addr;
2150 memcpy(pdu, hdr, hdr_len);
2151 memcpy(pdu + hdr_len, sdu, sdu_len);
2154 /* The hardware provides 'low' and 'high' (doorbell) registers
2155 * for passing the 64-bit address of an MCDI request to
2156 * firmware. However the dwords are swapped by firmware. The
2157 * least significant bits of the doorbell are then 0 for all
2158 * MCDI requests due to alignment.
2160 _efx_writed(efx, cpu_to_le32((u64)nic_data->mcdi_buf.dma_addr >> 32),
2162 _efx_writed(efx, cpu_to_le32((u32)nic_data->mcdi_buf.dma_addr),
2166 static bool efx_ef10_mcdi_poll_response(struct efx_nic *efx)
2168 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2169 const efx_dword_t hdr = *(const efx_dword_t *)nic_data->mcdi_buf.addr;
2172 return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE);
2176 efx_ef10_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf,
2177 size_t offset, size_t outlen)
2179 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2180 const u8 *pdu = nic_data->mcdi_buf.addr;
2182 memcpy(outbuf, pdu + offset, outlen);
2185 static void efx_ef10_mcdi_reboot_detected(struct efx_nic *efx)
2187 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2189 /* All our allocations have been reset */
2190 efx_ef10_reset_mc_allocations(efx);
2192 /* The datapath firmware might have been changed */
2193 nic_data->must_check_datapath_caps = true;
2195 /* MAC statistics have been cleared on the NIC; clear the local
2196 * statistic that we update with efx_update_diff_stat().
2198 nic_data->stats[EF10_STAT_port_rx_bad_bytes] = 0;
2201 static int efx_ef10_mcdi_poll_reboot(struct efx_nic *efx)
2203 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2206 rc = efx_ef10_get_warm_boot_count(efx);
2208 /* The firmware is presumably in the process of
2209 * rebooting. However, we are supposed to report each
2210 * reboot just once, so we must only do that once we
2211 * can read and store the updated warm boot count.
2216 if (rc == nic_data->warm_boot_count)
2219 nic_data->warm_boot_count = rc;
2220 efx_ef10_mcdi_reboot_detected(efx);
2225 /* Handle an MSI interrupt
2227 * Handle an MSI hardware interrupt. This routine schedules event
2228 * queue processing. No interrupt acknowledgement cycle is necessary.
2229 * Also, we never need to check that the interrupt is for us, since
2230 * MSI interrupts cannot be shared.
2232 static irqreturn_t efx_ef10_msi_interrupt(int irq, void *dev_id)
2234 struct efx_msi_context *context = dev_id;
2235 struct efx_nic *efx = context->efx;
2237 netif_vdbg(efx, intr, efx->net_dev,
2238 "IRQ %d on CPU %d\n", irq, raw_smp_processor_id());
2240 if (likely(READ_ONCE(efx->irq_soft_enabled))) {
2241 /* Note test interrupts */
2242 if (context->index == efx->irq_level)
2243 efx->last_irq_cpu = raw_smp_processor_id();
2245 /* Schedule processing of the channel */
2246 efx_schedule_channel_irq(efx->channel[context->index]);
2252 static irqreturn_t efx_ef10_legacy_interrupt(int irq, void *dev_id)
2254 struct efx_nic *efx = dev_id;
2255 bool soft_enabled = READ_ONCE(efx->irq_soft_enabled);
2256 struct efx_channel *channel;
2260 /* Read the ISR which also ACKs the interrupts */
2261 efx_readd(efx, ®, ER_DZ_BIU_INT_ISR);
2262 queues = EFX_DWORD_FIELD(reg, ERF_DZ_ISR_REG);
2267 if (likely(soft_enabled)) {
2268 /* Note test interrupts */
2269 if (queues & (1U << efx->irq_level))
2270 efx->last_irq_cpu = raw_smp_processor_id();
2272 efx_for_each_channel(channel, efx) {
2274 efx_schedule_channel_irq(channel);
2279 netif_vdbg(efx, intr, efx->net_dev,
2280 "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
2281 irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
2286 static int efx_ef10_irq_test_generate(struct efx_nic *efx)
2288 MCDI_DECLARE_BUF(inbuf, MC_CMD_TRIGGER_INTERRUPT_IN_LEN);
2290 if (efx_mcdi_set_workaround(efx, MC_CMD_WORKAROUND_BUG41750, true,
2294 BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN != 0);
2296 MCDI_SET_DWORD(inbuf, TRIGGER_INTERRUPT_IN_INTR_LEVEL, efx->irq_level);
2297 return efx_mcdi_rpc(efx, MC_CMD_TRIGGER_INTERRUPT,
2298 inbuf, sizeof(inbuf), NULL, 0, NULL);
2301 static int efx_ef10_tx_probe(struct efx_tx_queue *tx_queue)
2303 return efx_nic_alloc_buffer(tx_queue->efx, &tx_queue->txd.buf,
2304 (tx_queue->ptr_mask + 1) *
2305 sizeof(efx_qword_t),
2309 /* This writes to the TX_DESC_WPTR and also pushes data */
2310 static inline void efx_ef10_push_tx_desc(struct efx_tx_queue *tx_queue,
2311 const efx_qword_t *txd)
2313 unsigned int write_ptr;
2316 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
2317 EFX_POPULATE_OWORD_1(reg, ERF_DZ_TX_DESC_WPTR, write_ptr);
2318 reg.qword[0] = *txd;
2319 efx_writeo_page(tx_queue->efx, ®,
2320 ER_DZ_TX_DESC_UPD, tx_queue->queue);
2323 /* Add Firmware-Assisted TSO v2 option descriptors to a queue.
2325 static int efx_ef10_tx_tso_desc(struct efx_tx_queue *tx_queue,
2326 struct sk_buff *skb,
2329 struct efx_tx_buffer *buffer;
2337 EFX_WARN_ON_ONCE_PARANOID(tx_queue->tso_version != 2);
2339 mss = skb_shinfo(skb)->gso_size;
2341 if (unlikely(mss < 4)) {
2342 WARN_ONCE(1, "MSS of %u is too small for TSO v2\n", mss);
2347 if (ip->version == 4) {
2348 /* Modify IPv4 header if needed. */
2351 ipv4_id = ntohs(ip->id);
2353 /* Modify IPv6 header if needed. */
2354 struct ipv6hdr *ipv6 = ipv6_hdr(skb);
2356 ipv6->payload_len = 0;
2361 seqnum = ntohl(tcp->seq);
2363 buffer = efx_tx_queue_get_insert_buffer(tx_queue);
2365 buffer->flags = EFX_TX_BUF_OPTION;
2367 buffer->unmap_len = 0;
2368 EFX_POPULATE_QWORD_5(buffer->option,
2369 ESF_DZ_TX_DESC_IS_OPT, 1,
2370 ESF_DZ_TX_OPTION_TYPE, ESE_DZ_TX_OPTION_DESC_TSO,
2371 ESF_DZ_TX_TSO_OPTION_TYPE,
2372 ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A,
2373 ESF_DZ_TX_TSO_IP_ID, ipv4_id,
2374 ESF_DZ_TX_TSO_TCP_SEQNO, seqnum
2376 ++tx_queue->insert_count;
2378 buffer = efx_tx_queue_get_insert_buffer(tx_queue);
2380 buffer->flags = EFX_TX_BUF_OPTION;
2382 buffer->unmap_len = 0;
2383 EFX_POPULATE_QWORD_4(buffer->option,
2384 ESF_DZ_TX_DESC_IS_OPT, 1,
2385 ESF_DZ_TX_OPTION_TYPE, ESE_DZ_TX_OPTION_DESC_TSO,
2386 ESF_DZ_TX_TSO_OPTION_TYPE,
2387 ESE_DZ_TX_TSO_OPTION_DESC_FATSO2B,
2388 ESF_DZ_TX_TSO_TCP_MSS, mss
2390 ++tx_queue->insert_count;
2395 static u32 efx_ef10_tso_versions(struct efx_nic *efx)
2397 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2398 u32 tso_versions = 0;
2400 if (nic_data->datapath_caps &
2401 (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN))
2402 tso_versions |= BIT(1);
2403 if (nic_data->datapath_caps2 &
2404 (1 << MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_LBN))
2405 tso_versions |= BIT(2);
2406 return tso_versions;
2409 static void efx_ef10_tx_init(struct efx_tx_queue *tx_queue)
2411 MCDI_DECLARE_BUF(inbuf, MC_CMD_INIT_TXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
2413 bool csum_offload = tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD;
2414 size_t entries = tx_queue->txd.buf.len / EFX_BUF_SIZE;
2415 struct efx_channel *channel = tx_queue->channel;
2416 struct efx_nic *efx = tx_queue->efx;
2417 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2418 bool tso_v2 = false;
2420 dma_addr_t dma_addr;
2424 BUILD_BUG_ON(MC_CMD_INIT_TXQ_OUT_LEN != 0);
2426 /* Only attempt to enable TX timestamping if we have the license for it,
2427 * otherwise TXQ init will fail
2429 if (!(nic_data->licensed_features &
2430 (1 << LICENSED_V3_FEATURES_TX_TIMESTAMPS_LBN))) {
2431 tx_queue->timestamping = false;
2432 /* Disable sync events on this channel. */
2433 if (efx->type->ptp_set_ts_sync_events)
2434 efx->type->ptp_set_ts_sync_events(efx, false, false);
2437 /* TSOv2 is a limited resource that can only be configured on a limited
2438 * number of queues. TSO without checksum offload is not really a thing,
2439 * so we only enable it for those queues.
2440 * TSOv2 cannot be used with Hardware timestamping.
2442 if (csum_offload && (nic_data->datapath_caps2 &
2443 (1 << MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_LBN)) &&
2444 !tx_queue->timestamping) {
2446 netif_dbg(efx, hw, efx->net_dev, "Using TSOv2 for channel %u\n",
2450 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_SIZE, tx_queue->ptr_mask + 1);
2451 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_TARGET_EVQ, channel->channel);
2452 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_LABEL, tx_queue->queue);
2453 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_INSTANCE, tx_queue->queue);
2454 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_OWNER_ID, 0);
2455 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_PORT_ID, nic_data->vport_id);
2457 dma_addr = tx_queue->txd.buf.dma_addr;
2459 netif_dbg(efx, hw, efx->net_dev, "pushing TXQ %d. %zu entries (%llx)\n",
2460 tx_queue->queue, entries, (u64)dma_addr);
2462 for (i = 0; i < entries; ++i) {
2463 MCDI_SET_ARRAY_QWORD(inbuf, INIT_TXQ_IN_DMA_ADDR, i, dma_addr);
2464 dma_addr += EFX_BUF_SIZE;
2467 inlen = MC_CMD_INIT_TXQ_IN_LEN(entries);
2470 MCDI_POPULATE_DWORD_4(inbuf, INIT_TXQ_IN_FLAGS,
2471 /* This flag was removed from mcdi_pcol.h for
2472 * the non-_EXT version of INIT_TXQ. However,
2473 * firmware still honours it.
2475 INIT_TXQ_EXT_IN_FLAG_TSOV2_EN, tso_v2,
2476 INIT_TXQ_IN_FLAG_IP_CSUM_DIS, !csum_offload,
2477 INIT_TXQ_IN_FLAG_TCP_CSUM_DIS, !csum_offload,
2478 INIT_TXQ_EXT_IN_FLAG_TIMESTAMP,
2479 tx_queue->timestamping);
2481 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_INIT_TXQ, inbuf, inlen,
2483 if (rc == -ENOSPC && tso_v2) {
2484 /* Retry without TSOv2 if we're short on contexts. */
2486 netif_warn(efx, probe, efx->net_dev,
2487 "TSOv2 context not available to segment in hardware. TCP performance may be reduced.\n");
2489 efx_mcdi_display_error(efx, MC_CMD_INIT_TXQ,
2490 MC_CMD_INIT_TXQ_EXT_IN_LEN,
2496 /* A previous user of this TX queue might have set us up the
2497 * bomb by writing a descriptor to the TX push collector but
2498 * not the doorbell. (Each collector belongs to a port, not a
2499 * queue or function, so cannot easily be reset.) We must
2500 * attempt to push a no-op descriptor in its place.
2502 tx_queue->buffer[0].flags = EFX_TX_BUF_OPTION;
2503 tx_queue->insert_count = 1;
2504 txd = efx_tx_desc(tx_queue, 0);
2505 EFX_POPULATE_QWORD_5(*txd,
2506 ESF_DZ_TX_DESC_IS_OPT, true,
2507 ESF_DZ_TX_OPTION_TYPE,
2508 ESE_DZ_TX_OPTION_DESC_CRC_CSUM,
2509 ESF_DZ_TX_OPTION_UDP_TCP_CSUM, csum_offload,
2510 ESF_DZ_TX_OPTION_IP_CSUM, csum_offload,
2511 ESF_DZ_TX_TIMESTAMP, tx_queue->timestamping);
2512 tx_queue->write_count = 1;
2515 tx_queue->handle_tso = efx_ef10_tx_tso_desc;
2516 tx_queue->tso_version = 2;
2517 } else if (nic_data->datapath_caps &
2518 (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN)) {
2519 tx_queue->tso_version = 1;
2523 efx_ef10_push_tx_desc(tx_queue, txd);
2528 netdev_WARN(efx->net_dev, "failed to initialise TXQ %d\n",
2532 static void efx_ef10_tx_fini(struct efx_tx_queue *tx_queue)
2534 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_TXQ_IN_LEN);
2535 MCDI_DECLARE_BUF_ERR(outbuf);
2536 struct efx_nic *efx = tx_queue->efx;
2540 MCDI_SET_DWORD(inbuf, FINI_TXQ_IN_INSTANCE,
2543 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_TXQ, inbuf, sizeof(inbuf),
2544 outbuf, sizeof(outbuf), &outlen);
2546 if (rc && rc != -EALREADY)
2552 efx_mcdi_display_error(efx, MC_CMD_FINI_TXQ, MC_CMD_FINI_TXQ_IN_LEN,
2553 outbuf, outlen, rc);
2556 static void efx_ef10_tx_remove(struct efx_tx_queue *tx_queue)
2558 efx_nic_free_buffer(tx_queue->efx, &tx_queue->txd.buf);
2561 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
2562 static inline void efx_ef10_notify_tx_desc(struct efx_tx_queue *tx_queue)
2564 unsigned int write_ptr;
2567 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
2568 EFX_POPULATE_DWORD_1(reg, ERF_DZ_TX_DESC_WPTR_DWORD, write_ptr);
2569 efx_writed_page(tx_queue->efx, ®,
2570 ER_DZ_TX_DESC_UPD_DWORD, tx_queue->queue);
2573 #define EFX_EF10_MAX_TX_DESCRIPTOR_LEN 0x3fff
2575 static unsigned int efx_ef10_tx_limit_len(struct efx_tx_queue *tx_queue,
2576 dma_addr_t dma_addr, unsigned int len)
2578 if (len > EFX_EF10_MAX_TX_DESCRIPTOR_LEN) {
2579 /* If we need to break across multiple descriptors we should
2580 * stop at a page boundary. This assumes the length limit is
2581 * greater than the page size.
2583 dma_addr_t end = dma_addr + EFX_EF10_MAX_TX_DESCRIPTOR_LEN;
2585 BUILD_BUG_ON(EFX_EF10_MAX_TX_DESCRIPTOR_LEN < EFX_PAGE_SIZE);
2586 len = (end & (~(EFX_PAGE_SIZE - 1))) - dma_addr;
2592 static void efx_ef10_tx_write(struct efx_tx_queue *tx_queue)
2594 unsigned int old_write_count = tx_queue->write_count;
2595 struct efx_tx_buffer *buffer;
2596 unsigned int write_ptr;
2599 tx_queue->xmit_more_available = false;
2600 if (unlikely(tx_queue->write_count == tx_queue->insert_count))
2604 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
2605 buffer = &tx_queue->buffer[write_ptr];
2606 txd = efx_tx_desc(tx_queue, write_ptr);
2607 ++tx_queue->write_count;
2609 /* Create TX descriptor ring entry */
2610 if (buffer->flags & EFX_TX_BUF_OPTION) {
2611 *txd = buffer->option;
2612 if (EFX_QWORD_FIELD(*txd, ESF_DZ_TX_OPTION_TYPE) == 1)
2613 /* PIO descriptor */
2614 tx_queue->packet_write_count = tx_queue->write_count;
2616 tx_queue->packet_write_count = tx_queue->write_count;
2617 BUILD_BUG_ON(EFX_TX_BUF_CONT != 1);
2618 EFX_POPULATE_QWORD_3(
2621 buffer->flags & EFX_TX_BUF_CONT,
2622 ESF_DZ_TX_KER_BYTE_CNT, buffer->len,
2623 ESF_DZ_TX_KER_BUF_ADDR, buffer->dma_addr);
2625 } while (tx_queue->write_count != tx_queue->insert_count);
2627 wmb(); /* Ensure descriptors are written before they are fetched */
2629 if (efx_nic_may_push_tx_desc(tx_queue, old_write_count)) {
2630 txd = efx_tx_desc(tx_queue,
2631 old_write_count & tx_queue->ptr_mask);
2632 efx_ef10_push_tx_desc(tx_queue, txd);
2635 efx_ef10_notify_tx_desc(tx_queue);
2639 #define RSS_MODE_HASH_ADDRS (1 << RSS_MODE_HASH_SRC_ADDR_LBN |\
2640 1 << RSS_MODE_HASH_DST_ADDR_LBN)
2641 #define RSS_MODE_HASH_PORTS (1 << RSS_MODE_HASH_SRC_PORT_LBN |\
2642 1 << RSS_MODE_HASH_DST_PORT_LBN)
2643 #define RSS_CONTEXT_FLAGS_DEFAULT (1 << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_LBN |\
2644 1 << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_LBN |\
2645 1 << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_LBN |\
2646 1 << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_LBN |\
2647 (RSS_MODE_HASH_ADDRS | RSS_MODE_HASH_PORTS) << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_LBN |\
2648 RSS_MODE_HASH_ADDRS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_LBN |\
2649 RSS_MODE_HASH_ADDRS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_LBN |\
2650 (RSS_MODE_HASH_ADDRS | RSS_MODE_HASH_PORTS) << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_LBN |\
2651 RSS_MODE_HASH_ADDRS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_LBN |\
2652 RSS_MODE_HASH_ADDRS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_LBN)
2654 static int efx_ef10_get_rss_flags(struct efx_nic *efx, u32 context, u32 *flags)
2656 /* Firmware had a bug (sfc bug 61952) where it would not actually
2657 * fill in the flags field in the response to MC_CMD_RSS_CONTEXT_GET_FLAGS.
2658 * This meant that it would always contain whatever was previously
2659 * in the MCDI buffer. Fortunately, all firmware versions with
2660 * this bug have the same default flags value for a newly-allocated
2661 * RSS context, and the only time we want to get the flags is just
2662 * after allocating. Moreover, the response has a 32-bit hole
2663 * where the context ID would be in the request, so we can use an
2664 * overlength buffer in the request and pre-fill the flags field
2665 * with what we believe the default to be. Thus if the firmware
2666 * has the bug, it will leave our pre-filled value in the flags
2667 * field of the response, and we will get the right answer.
2669 * However, this does mean that this function should NOT be used if
2670 * the RSS context flags might not be their defaults - it is ONLY
2671 * reliably correct for a newly-allocated RSS context.
2673 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN);
2674 MCDI_DECLARE_BUF(outbuf, MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN);
2678 /* Check we have a hole for the context ID */
2679 BUILD_BUG_ON(MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_LEN != MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_FLAGS_OFST);
2680 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_GET_FLAGS_IN_RSS_CONTEXT_ID, context);
2681 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_GET_FLAGS_OUT_FLAGS,
2682 RSS_CONTEXT_FLAGS_DEFAULT);
2683 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_GET_FLAGS, inbuf,
2684 sizeof(inbuf), outbuf, sizeof(outbuf), &outlen);
2686 if (outlen < MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN)
2689 *flags = MCDI_DWORD(outbuf, RSS_CONTEXT_GET_FLAGS_OUT_FLAGS);
2694 /* Attempt to enable 4-tuple UDP hashing on the specified RSS context.
2695 * If we fail, we just leave the RSS context at its default hash settings,
2696 * which is safe but may slightly reduce performance.
2697 * Defaults are 4-tuple for TCP and 2-tuple for UDP and other-IP, so we
2698 * just need to set the UDP ports flags (for both IP versions).
2700 static void efx_ef10_set_rss_flags(struct efx_nic *efx,
2701 struct efx_rss_context *ctx)
2703 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_LEN);
2706 BUILD_BUG_ON(MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT_LEN != 0);
2708 if (efx_ef10_get_rss_flags(efx, ctx->context_id, &flags) != 0)
2710 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID,
2712 flags |= RSS_MODE_HASH_PORTS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_LBN;
2713 flags |= RSS_MODE_HASH_PORTS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_LBN;
2714 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_SET_FLAGS_IN_FLAGS, flags);
2715 if (!efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_FLAGS, inbuf, sizeof(inbuf),
2717 /* Succeeded, so UDP 4-tuple is now enabled */
2718 ctx->rx_hash_udp_4tuple = true;
2721 static int efx_ef10_alloc_rss_context(struct efx_nic *efx, bool exclusive,
2722 struct efx_rss_context *ctx,
2723 unsigned *context_size)
2725 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN);
2726 MCDI_DECLARE_BUF(outbuf, MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN);
2727 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2730 u32 alloc_type = exclusive ?
2731 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE :
2732 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED;
2733 unsigned rss_spread = exclusive ?
2735 min(rounddown_pow_of_two(efx->rss_spread),
2736 EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE);
2738 if (!exclusive && rss_spread == 1) {
2739 ctx->context_id = EFX_EF10_RSS_CONTEXT_INVALID;
2745 if (nic_data->datapath_caps &
2746 1 << MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_LBN)
2749 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID,
2750 nic_data->vport_id);
2751 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_TYPE, alloc_type);
2752 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_NUM_QUEUES, rss_spread);
2754 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_ALLOC, inbuf, sizeof(inbuf),
2755 outbuf, sizeof(outbuf), &outlen);
2759 if (outlen < MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN)
2762 ctx->context_id = MCDI_DWORD(outbuf, RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID);
2765 *context_size = rss_spread;
2767 if (nic_data->datapath_caps &
2768 1 << MC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_LBN)
2769 efx_ef10_set_rss_flags(efx, ctx);
2774 static int efx_ef10_free_rss_context(struct efx_nic *efx, u32 context)
2776 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_FREE_IN_LEN);
2778 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID,
2780 return efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_FREE, inbuf, sizeof(inbuf),
2784 static int efx_ef10_populate_rss_table(struct efx_nic *efx, u32 context,
2785 const u32 *rx_indir_table, const u8 *key)
2787 MCDI_DECLARE_BUF(tablebuf, MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN);
2788 MCDI_DECLARE_BUF(keybuf, MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN);
2791 MCDI_SET_DWORD(tablebuf, RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID,
2793 BUILD_BUG_ON(ARRAY_SIZE(efx->rss_context.rx_indir_table) !=
2794 MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN);
2796 /* This iterates over the length of efx->rss_context.rx_indir_table, but
2797 * copies bytes from rx_indir_table. That's because the latter is a
2798 * pointer rather than an array, but should have the same length.
2799 * The efx->rss_context.rx_hash_key loop below is similar.
2801 for (i = 0; i < ARRAY_SIZE(efx->rss_context.rx_indir_table); ++i)
2803 RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE)[i] =
2804 (u8) rx_indir_table[i];
2806 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_TABLE, tablebuf,
2807 sizeof(tablebuf), NULL, 0, NULL);
2811 MCDI_SET_DWORD(keybuf, RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID,
2813 BUILD_BUG_ON(ARRAY_SIZE(efx->rss_context.rx_hash_key) !=
2814 MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN);
2815 for (i = 0; i < ARRAY_SIZE(efx->rss_context.rx_hash_key); ++i)
2816 MCDI_PTR(keybuf, RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY)[i] = key[i];
2818 return efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_KEY, keybuf,
2819 sizeof(keybuf), NULL, 0, NULL);
2822 static void efx_ef10_rx_free_indir_table(struct efx_nic *efx)
2826 if (efx->rss_context.context_id != EFX_EF10_RSS_CONTEXT_INVALID) {
2827 rc = efx_ef10_free_rss_context(efx, efx->rss_context.context_id);
2830 efx->rss_context.context_id = EFX_EF10_RSS_CONTEXT_INVALID;
2833 static int efx_ef10_rx_push_shared_rss_config(struct efx_nic *efx,
2834 unsigned *context_size)
2836 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2837 int rc = efx_ef10_alloc_rss_context(efx, false, &efx->rss_context,
2843 nic_data->rx_rss_context_exclusive = false;
2844 efx_set_default_rx_indir_table(efx, &efx->rss_context);
2848 static int efx_ef10_rx_push_exclusive_rss_config(struct efx_nic *efx,
2849 const u32 *rx_indir_table,
2852 u32 old_rx_rss_context = efx->rss_context.context_id;
2853 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2856 if (efx->rss_context.context_id == EFX_EF10_RSS_CONTEXT_INVALID ||
2857 !nic_data->rx_rss_context_exclusive) {
2858 rc = efx_ef10_alloc_rss_context(efx, true, &efx->rss_context,
2860 if (rc == -EOPNOTSUPP)
2866 rc = efx_ef10_populate_rss_table(efx, efx->rss_context.context_id,
2867 rx_indir_table, key);
2871 if (efx->rss_context.context_id != old_rx_rss_context &&
2872 old_rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID)
2873 WARN_ON(efx_ef10_free_rss_context(efx, old_rx_rss_context) != 0);
2874 nic_data->rx_rss_context_exclusive = true;
2875 if (rx_indir_table != efx->rss_context.rx_indir_table)
2876 memcpy(efx->rss_context.rx_indir_table, rx_indir_table,
2877 sizeof(efx->rss_context.rx_indir_table));
2878 if (key != efx->rss_context.rx_hash_key)
2879 memcpy(efx->rss_context.rx_hash_key, key,
2880 efx->type->rx_hash_key_size);
2885 if (old_rx_rss_context != efx->rss_context.context_id) {
2886 WARN_ON(efx_ef10_free_rss_context(efx, efx->rss_context.context_id) != 0);
2887 efx->rss_context.context_id = old_rx_rss_context;
2890 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
2894 static int efx_ef10_rx_push_rss_context_config(struct efx_nic *efx,
2895 struct efx_rss_context *ctx,
2896 const u32 *rx_indir_table,
2901 WARN_ON(!mutex_is_locked(&efx->rss_lock));
2903 if (ctx->context_id == EFX_EF10_RSS_CONTEXT_INVALID) {
2904 rc = efx_ef10_alloc_rss_context(efx, true, ctx, NULL);
2909 if (!rx_indir_table) /* Delete this context */
2910 return efx_ef10_free_rss_context(efx, ctx->context_id);
2912 rc = efx_ef10_populate_rss_table(efx, ctx->context_id,
2913 rx_indir_table, key);
2917 memcpy(ctx->rx_indir_table, rx_indir_table,
2918 sizeof(efx->rss_context.rx_indir_table));
2919 memcpy(ctx->rx_hash_key, key, efx->type->rx_hash_key_size);
2924 static int efx_ef10_rx_pull_rss_context_config(struct efx_nic *efx,
2925 struct efx_rss_context *ctx)
2927 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_GET_TABLE_IN_LEN);
2928 MCDI_DECLARE_BUF(tablebuf, MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_LEN);
2929 MCDI_DECLARE_BUF(keybuf, MC_CMD_RSS_CONTEXT_GET_KEY_OUT_LEN);
2933 WARN_ON(!mutex_is_locked(&efx->rss_lock));
2935 BUILD_BUG_ON(MC_CMD_RSS_CONTEXT_GET_TABLE_IN_LEN !=
2936 MC_CMD_RSS_CONTEXT_GET_KEY_IN_LEN);
2938 if (ctx->context_id == EFX_EF10_RSS_CONTEXT_INVALID)
2941 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_GET_TABLE_IN_RSS_CONTEXT_ID,
2943 BUILD_BUG_ON(ARRAY_SIZE(ctx->rx_indir_table) !=
2944 MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_LEN);
2945 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_GET_TABLE, inbuf, sizeof(inbuf),
2946 tablebuf, sizeof(tablebuf), &outlen);
2950 if (WARN_ON(outlen != MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_LEN))
2953 for (i = 0; i < ARRAY_SIZE(ctx->rx_indir_table); i++)
2954 ctx->rx_indir_table[i] = MCDI_PTR(tablebuf,
2955 RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE)[i];
2957 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_GET_KEY_IN_RSS_CONTEXT_ID,
2959 BUILD_BUG_ON(ARRAY_SIZE(ctx->rx_hash_key) !=
2960 MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN);
2961 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_GET_KEY, inbuf, sizeof(inbuf),
2962 keybuf, sizeof(keybuf), &outlen);
2966 if (WARN_ON(outlen != MC_CMD_RSS_CONTEXT_GET_KEY_OUT_LEN))
2969 for (i = 0; i < ARRAY_SIZE(ctx->rx_hash_key); ++i)
2970 ctx->rx_hash_key[i] = MCDI_PTR(
2971 keybuf, RSS_CONTEXT_GET_KEY_OUT_TOEPLITZ_KEY)[i];
2976 static int efx_ef10_rx_pull_rss_config(struct efx_nic *efx)
2980 mutex_lock(&efx->rss_lock);
2981 rc = efx_ef10_rx_pull_rss_context_config(efx, &efx->rss_context);
2982 mutex_unlock(&efx->rss_lock);
2986 static void efx_ef10_rx_restore_rss_contexts(struct efx_nic *efx)
2988 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2989 struct efx_rss_context *ctx;
2992 WARN_ON(!mutex_is_locked(&efx->rss_lock));
2994 if (!nic_data->must_restore_rss_contexts)
2997 list_for_each_entry(ctx, &efx->rss_context.list, list) {
2998 /* previous NIC RSS context is gone */
2999 ctx->context_id = EFX_EF10_RSS_CONTEXT_INVALID;
3000 /* so try to allocate a new one */
3001 rc = efx_ef10_rx_push_rss_context_config(efx, ctx,
3002 ctx->rx_indir_table,
3005 netif_warn(efx, probe, efx->net_dev,
3006 "failed to restore RSS context %u, rc=%d"
3007 "; RSS filters may fail to be applied\n",
3010 nic_data->must_restore_rss_contexts = false;
3013 static int efx_ef10_pf_rx_push_rss_config(struct efx_nic *efx, bool user,
3014 const u32 *rx_indir_table,
3019 if (efx->rss_spread == 1)
3023 key = efx->rss_context.rx_hash_key;
3025 rc = efx_ef10_rx_push_exclusive_rss_config(efx, rx_indir_table, key);
3027 if (rc == -ENOBUFS && !user) {
3028 unsigned context_size;
3029 bool mismatch = false;
3033 i < ARRAY_SIZE(efx->rss_context.rx_indir_table) && !mismatch;
3035 mismatch = rx_indir_table[i] !=
3036 ethtool_rxfh_indir_default(i, efx->rss_spread);
3038 rc = efx_ef10_rx_push_shared_rss_config(efx, &context_size);
3040 if (context_size != efx->rss_spread)
3041 netif_warn(efx, probe, efx->net_dev,
3042 "Could not allocate an exclusive RSS"
3043 " context; allocated a shared one of"
3045 " Wanted %u, got %u.\n",
3046 efx->rss_spread, context_size);
3048 netif_warn(efx, probe, efx->net_dev,
3049 "Could not allocate an exclusive RSS"
3050 " context; allocated a shared one but"
3051 " could not apply custom"
3054 netif_info(efx, probe, efx->net_dev,
3055 "Could not allocate an exclusive RSS"
3056 " context; allocated a shared one.\n");
3062 static int efx_ef10_vf_rx_push_rss_config(struct efx_nic *efx, bool user,
3063 const u32 *rx_indir_table
3064 __attribute__ ((unused)),
3066 __attribute__ ((unused)))
3070 if (efx->rss_context.context_id != EFX_EF10_RSS_CONTEXT_INVALID)
3072 return efx_ef10_rx_push_shared_rss_config(efx, NULL);
3075 static int efx_ef10_rx_probe(struct efx_rx_queue *rx_queue)
3077 return efx_nic_alloc_buffer(rx_queue->efx, &rx_queue->rxd.buf,
3078 (rx_queue->ptr_mask + 1) *
3079 sizeof(efx_qword_t),
3083 static void efx_ef10_rx_init(struct efx_rx_queue *rx_queue)
3085 MCDI_DECLARE_BUF(inbuf,
3086 MC_CMD_INIT_RXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
3088 struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
3089 size_t entries = rx_queue->rxd.buf.len / EFX_BUF_SIZE;
3090 struct efx_nic *efx = rx_queue->efx;
3091 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3093 dma_addr_t dma_addr;
3096 BUILD_BUG_ON(MC_CMD_INIT_RXQ_OUT_LEN != 0);
3098 rx_queue->scatter_n = 0;
3099 rx_queue->scatter_len = 0;
3101 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_SIZE, rx_queue->ptr_mask + 1);
3102 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_TARGET_EVQ, channel->channel);
3103 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_LABEL, efx_rx_queue_index(rx_queue));
3104 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_INSTANCE,
3105 efx_rx_queue_index(rx_queue));
3106 MCDI_POPULATE_DWORD_2(inbuf, INIT_RXQ_IN_FLAGS,
3107 INIT_RXQ_IN_FLAG_PREFIX, 1,
3108 INIT_RXQ_IN_FLAG_TIMESTAMP, 1);
3109 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_OWNER_ID, 0);
3110 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_PORT_ID, nic_data->vport_id);
3112 dma_addr = rx_queue->rxd.buf.dma_addr;
3114 netif_dbg(efx, hw, efx->net_dev, "pushing RXQ %d. %zu entries (%llx)\n",
3115 efx_rx_queue_index(rx_queue), entries, (u64)dma_addr);
3117 for (i = 0; i < entries; ++i) {
3118 MCDI_SET_ARRAY_QWORD(inbuf, INIT_RXQ_IN_DMA_ADDR, i, dma_addr);
3119 dma_addr += EFX_BUF_SIZE;
3122 inlen = MC_CMD_INIT_RXQ_IN_LEN(entries);
3124 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_RXQ, inbuf, inlen,
3127 netdev_WARN(efx->net_dev, "failed to initialise RXQ %d\n",
3128 efx_rx_queue_index(rx_queue));
3131 static void efx_ef10_rx_fini(struct efx_rx_queue *rx_queue)
3133 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_RXQ_IN_LEN);
3134 MCDI_DECLARE_BUF_ERR(outbuf);
3135 struct efx_nic *efx = rx_queue->efx;
3139 MCDI_SET_DWORD(inbuf, FINI_RXQ_IN_INSTANCE,
3140 efx_rx_queue_index(rx_queue));
3142 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_RXQ, inbuf, sizeof(inbuf),
3143 outbuf, sizeof(outbuf), &outlen);
3145 if (rc && rc != -EALREADY)
3151 efx_mcdi_display_error(efx, MC_CMD_FINI_RXQ, MC_CMD_FINI_RXQ_IN_LEN,
3152 outbuf, outlen, rc);
3155 static void efx_ef10_rx_remove(struct efx_rx_queue *rx_queue)
3157 efx_nic_free_buffer(rx_queue->efx, &rx_queue->rxd.buf);
3160 /* This creates an entry in the RX descriptor queue */
3162 efx_ef10_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index)
3164 struct efx_rx_buffer *rx_buf;
3167 rxd = efx_rx_desc(rx_queue, index);
3168 rx_buf = efx_rx_buffer(rx_queue, index);
3169 EFX_POPULATE_QWORD_2(*rxd,
3170 ESF_DZ_RX_KER_BYTE_CNT, rx_buf->len,
3171 ESF_DZ_RX_KER_BUF_ADDR, rx_buf->dma_addr);
3174 static void efx_ef10_rx_write(struct efx_rx_queue *rx_queue)
3176 struct efx_nic *efx = rx_queue->efx;
3177 unsigned int write_count;
3180 /* Firmware requires that RX_DESC_WPTR be a multiple of 8 */
3181 write_count = rx_queue->added_count & ~7;
3182 if (rx_queue->notified_count == write_count)
3186 efx_ef10_build_rx_desc(
3188 rx_queue->notified_count & rx_queue->ptr_mask);
3189 while (++rx_queue->notified_count != write_count);
3192 EFX_POPULATE_DWORD_1(reg, ERF_DZ_RX_DESC_WPTR,
3193 write_count & rx_queue->ptr_mask);
3194 efx_writed_page(efx, ®, ER_DZ_RX_DESC_UPD,
3195 efx_rx_queue_index(rx_queue));
3198 static efx_mcdi_async_completer efx_ef10_rx_defer_refill_complete;
3200 static void efx_ef10_rx_defer_refill(struct efx_rx_queue *rx_queue)
3202 struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
3203 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
3206 EFX_POPULATE_QWORD_2(event,
3207 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
3208 ESF_DZ_EV_DATA, EFX_EF10_REFILL);
3210 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
3212 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
3213 * already swapped the data to little-endian order.
3215 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
3216 sizeof(efx_qword_t));
3218 efx_mcdi_rpc_async(channel->efx, MC_CMD_DRIVER_EVENT,
3219 inbuf, sizeof(inbuf), 0,
3220 efx_ef10_rx_defer_refill_complete, 0);
3224 efx_ef10_rx_defer_refill_complete(struct efx_nic *efx, unsigned long cookie,
3225 int rc, efx_dword_t *outbuf,
3226 size_t outlen_actual)
3231 static int efx_ef10_ev_probe(struct efx_channel *channel)
3233 return efx_nic_alloc_buffer(channel->efx, &channel->eventq.buf,
3234 (channel->eventq_mask + 1) *
3235 sizeof(efx_qword_t),
3239 static void efx_ef10_ev_fini(struct efx_channel *channel)
3241 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_EVQ_IN_LEN);
3242 MCDI_DECLARE_BUF_ERR(outbuf);
3243 struct efx_nic *efx = channel->efx;
3247 MCDI_SET_DWORD(inbuf, FINI_EVQ_IN_INSTANCE, channel->channel);
3249 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_EVQ, inbuf, sizeof(inbuf),
3250 outbuf, sizeof(outbuf), &outlen);
3252 if (rc && rc != -EALREADY)
3258 efx_mcdi_display_error(efx, MC_CMD_FINI_EVQ, MC_CMD_FINI_EVQ_IN_LEN,
3259 outbuf, outlen, rc);
3262 static int efx_ef10_ev_init(struct efx_channel *channel)
3264 MCDI_DECLARE_BUF(inbuf,
3265 MC_CMD_INIT_EVQ_V2_IN_LEN(EFX_MAX_EVQ_SIZE * 8 /
3267 MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_EVQ_V2_OUT_LEN);
3268 size_t entries = channel->eventq.buf.len / EFX_BUF_SIZE;
3269 struct efx_nic *efx = channel->efx;
3270 struct efx_ef10_nic_data *nic_data;
3271 size_t inlen, outlen;
3272 unsigned int enabled, implemented;
3273 dma_addr_t dma_addr;
3277 nic_data = efx->nic_data;
3279 /* Fill event queue with all ones (i.e. empty events) */
3280 memset(channel->eventq.buf.addr, 0xff, channel->eventq.buf.len);
3282 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_SIZE, channel->eventq_mask + 1);
3283 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_INSTANCE, channel->channel);
3284 /* INIT_EVQ expects index in vector table, not absolute */
3285 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_IRQ_NUM, channel->channel);
3286 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_MODE,
3287 MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS);
3288 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_LOAD, 0);
3289 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_RELOAD, 0);
3290 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_MODE,
3291 MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS);
3292 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_THRSHLD, 0);
3294 if (nic_data->datapath_caps2 &
3295 1 << MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_LBN) {
3296 /* Use the new generic approach to specifying event queue
3297 * configuration, requesting lower latency or higher throughput.
3298 * The options that actually get used appear in the output.
3300 MCDI_POPULATE_DWORD_2(inbuf, INIT_EVQ_V2_IN_FLAGS,
3301 INIT_EVQ_V2_IN_FLAG_INTERRUPTING, 1,
3302 INIT_EVQ_V2_IN_FLAG_TYPE,
3303 MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_AUTO);
3305 bool cut_thru = !(nic_data->datapath_caps &
3306 1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN);
3308 MCDI_POPULATE_DWORD_4(inbuf, INIT_EVQ_IN_FLAGS,
3309 INIT_EVQ_IN_FLAG_INTERRUPTING, 1,
3310 INIT_EVQ_IN_FLAG_RX_MERGE, 1,
3311 INIT_EVQ_IN_FLAG_TX_MERGE, 1,
3312 INIT_EVQ_IN_FLAG_CUT_THRU, cut_thru);
3315 dma_addr = channel->eventq.buf.dma_addr;
3316 for (i = 0; i < entries; ++i) {
3317 MCDI_SET_ARRAY_QWORD(inbuf, INIT_EVQ_IN_DMA_ADDR, i, dma_addr);
3318 dma_addr += EFX_BUF_SIZE;
3321 inlen = MC_CMD_INIT_EVQ_IN_LEN(entries);
3323 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_EVQ, inbuf, inlen,
3324 outbuf, sizeof(outbuf), &outlen);
3326 if (outlen >= MC_CMD_INIT_EVQ_V2_OUT_LEN)
3327 netif_dbg(efx, drv, efx->net_dev,
3328 "Channel %d using event queue flags %08x\n",
3330 MCDI_DWORD(outbuf, INIT_EVQ_V2_OUT_FLAGS));
3332 /* IRQ return is ignored */
3333 if (channel->channel || rc)
3336 /* Successfully created event queue on channel 0 */
3337 rc = efx_mcdi_get_workarounds(efx, &implemented, &enabled);
3338 if (rc == -ENOSYS) {
3339 /* GET_WORKAROUNDS was implemented before this workaround,
3340 * thus it must be unavailable in this firmware.
3342 nic_data->workaround_26807 = false;
3347 nic_data->workaround_26807 =
3348 !!(enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807);
3350 if (implemented & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807 &&
3351 !nic_data->workaround_26807) {
3354 rc = efx_mcdi_set_workaround(efx,
3355 MC_CMD_WORKAROUND_BUG26807,
3360 1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN) {
3361 netif_info(efx, drv, efx->net_dev,
3362 "other functions on NIC have been reset\n");
3364 /* With MCFW v4.6.x and earlier, the
3365 * boot count will have incremented,
3366 * so re-read the warm_boot_count
3367 * value now to ensure this function
3368 * doesn't think it has changed next
3371 rc = efx_ef10_get_warm_boot_count(efx);
3373 nic_data->warm_boot_count = rc;
3377 nic_data->workaround_26807 = true;
3378 } else if (rc == -EPERM) {
3388 efx_ef10_ev_fini(channel);
3392 static void efx_ef10_ev_remove(struct efx_channel *channel)
3394 efx_nic_free_buffer(channel->efx, &channel->eventq.buf);
3397 static void efx_ef10_handle_rx_wrong_queue(struct efx_rx_queue *rx_queue,
3398 unsigned int rx_queue_label)
3400 struct efx_nic *efx = rx_queue->efx;
3402 netif_info(efx, hw, efx->net_dev,
3403 "rx event arrived on queue %d labeled as queue %u\n",
3404 efx_rx_queue_index(rx_queue), rx_queue_label);
3406 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
3410 efx_ef10_handle_rx_bad_lbits(struct efx_rx_queue *rx_queue,
3411 unsigned int actual, unsigned int expected)
3413 unsigned int dropped = (actual - expected) & rx_queue->ptr_mask;
3414 struct efx_nic *efx = rx_queue->efx;
3416 netif_info(efx, hw, efx->net_dev,
3417 "dropped %d events (index=%d expected=%d)\n",
3418 dropped, actual, expected);
3420 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
3423 /* partially received RX was aborted. clean up. */
3424 static void efx_ef10_handle_rx_abort(struct efx_rx_queue *rx_queue)
3426 unsigned int rx_desc_ptr;
3428 netif_dbg(rx_queue->efx, hw, rx_queue->efx->net_dev,
3429 "scattered RX aborted (dropping %u buffers)\n",
3430 rx_queue->scatter_n);
3432 rx_desc_ptr = rx_queue->removed_count & rx_queue->ptr_mask;
3434 efx_rx_packet(rx_queue, rx_desc_ptr, rx_queue->scatter_n,
3435 0, EFX_RX_PKT_DISCARD);
3437 rx_queue->removed_count += rx_queue->scatter_n;
3438 rx_queue->scatter_n = 0;
3439 rx_queue->scatter_len = 0;
3440 ++efx_rx_queue_channel(rx_queue)->n_rx_nodesc_trunc;
3443 static u16 efx_ef10_handle_rx_event_errors(struct efx_channel *channel,
3444 unsigned int n_packets,
3445 unsigned int rx_encap_hdr,
3446 unsigned int rx_l3_class,
3447 unsigned int rx_l4_class,
3448 const efx_qword_t *event)
3450 struct efx_nic *efx = channel->efx;
3451 bool handled = false;
3453 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_ECRC_ERR)) {
3454 if (!(efx->net_dev->features & NETIF_F_RXALL)) {
3455 if (!efx->loopback_selftest)
3456 channel->n_rx_eth_crc_err += n_packets;
3457 return EFX_RX_PKT_DISCARD;
3461 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_IPCKSUM_ERR)) {
3462 if (unlikely(rx_encap_hdr != ESE_EZ_ENCAP_HDR_VXLAN &&
3463 rx_l3_class != ESE_DZ_L3_CLASS_IP4 &&
3464 rx_l3_class != ESE_DZ_L3_CLASS_IP4_FRAG &&
3465 rx_l3_class != ESE_DZ_L3_CLASS_IP6 &&
3466 rx_l3_class != ESE_DZ_L3_CLASS_IP6_FRAG))
3467 netdev_WARN(efx->net_dev,
3468 "invalid class for RX_IPCKSUM_ERR: event="
3470 EFX_QWORD_VAL(*event));
3471 if (!efx->loopback_selftest)
3473 &channel->n_rx_outer_ip_hdr_chksum_err :
3474 &channel->n_rx_ip_hdr_chksum_err) += n_packets;
3477 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_TCPUDP_CKSUM_ERR)) {
3478 if (unlikely(rx_encap_hdr != ESE_EZ_ENCAP_HDR_VXLAN &&
3479 ((rx_l3_class != ESE_DZ_L3_CLASS_IP4 &&
3480 rx_l3_class != ESE_DZ_L3_CLASS_IP6) ||
3481 (rx_l4_class != ESE_FZ_L4_CLASS_TCP &&
3482 rx_l4_class != ESE_FZ_L4_CLASS_UDP))))
3483 netdev_WARN(efx->net_dev,
3484 "invalid class for RX_TCPUDP_CKSUM_ERR: event="
3486 EFX_QWORD_VAL(*event));
3487 if (!efx->loopback_selftest)
3489 &channel->n_rx_outer_tcp_udp_chksum_err :
3490 &channel->n_rx_tcp_udp_chksum_err) += n_packets;
3493 if (EFX_QWORD_FIELD(*event, ESF_EZ_RX_IP_INNER_CHKSUM_ERR)) {
3494 if (unlikely(!rx_encap_hdr))
3495 netdev_WARN(efx->net_dev,
3496 "invalid encapsulation type for RX_IP_INNER_CHKSUM_ERR: event="
3498 EFX_QWORD_VAL(*event));
3499 else if (unlikely(rx_l3_class != ESE_DZ_L3_CLASS_IP4 &&
3500 rx_l3_class != ESE_DZ_L3_CLASS_IP4_FRAG &&
3501 rx_l3_class != ESE_DZ_L3_CLASS_IP6 &&
3502 rx_l3_class != ESE_DZ_L3_CLASS_IP6_FRAG))
3503 netdev_WARN(efx->net_dev,
3504 "invalid class for RX_IP_INNER_CHKSUM_ERR: event="
3506 EFX_QWORD_VAL(*event));
3507 if (!efx->loopback_selftest)
3508 channel->n_rx_inner_ip_hdr_chksum_err += n_packets;
3511 if (EFX_QWORD_FIELD(*event, ESF_EZ_RX_TCP_UDP_INNER_CHKSUM_ERR)) {
3512 if (unlikely(!rx_encap_hdr))
3513 netdev_WARN(efx->net_dev,
3514 "invalid encapsulation type for RX_TCP_UDP_INNER_CHKSUM_ERR: event="
3516 EFX_QWORD_VAL(*event));
3517 else if (unlikely((rx_l3_class != ESE_DZ_L3_CLASS_IP4 &&
3518 rx_l3_class != ESE_DZ_L3_CLASS_IP6) ||
3519 (rx_l4_class != ESE_FZ_L4_CLASS_TCP &&
3520 rx_l4_class != ESE_FZ_L4_CLASS_UDP)))
3521 netdev_WARN(efx->net_dev,
3522 "invalid class for RX_TCP_UDP_INNER_CHKSUM_ERR: event="
3524 EFX_QWORD_VAL(*event));
3525 if (!efx->loopback_selftest)
3526 channel->n_rx_inner_tcp_udp_chksum_err += n_packets;
3530 WARN_ON(!handled); /* No error bits were recognised */
3534 static int efx_ef10_handle_rx_event(struct efx_channel *channel,
3535 const efx_qword_t *event)
3537 unsigned int rx_bytes, next_ptr_lbits, rx_queue_label;
3538 unsigned int rx_l3_class, rx_l4_class, rx_encap_hdr;
3539 unsigned int n_descs, n_packets, i;
3540 struct efx_nic *efx = channel->efx;
3541 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3542 struct efx_rx_queue *rx_queue;
3547 if (unlikely(READ_ONCE(efx->reset_pending)))
3550 /* Basic packet information */
3551 rx_bytes = EFX_QWORD_FIELD(*event, ESF_DZ_RX_BYTES);
3552 next_ptr_lbits = EFX_QWORD_FIELD(*event, ESF_DZ_RX_DSC_PTR_LBITS);
3553 rx_queue_label = EFX_QWORD_FIELD(*event, ESF_DZ_RX_QLABEL);
3554 rx_l3_class = EFX_QWORD_FIELD(*event, ESF_DZ_RX_L3_CLASS);
3555 rx_l4_class = EFX_QWORD_FIELD(*event, ESF_FZ_RX_L4_CLASS);
3556 rx_cont = EFX_QWORD_FIELD(*event, ESF_DZ_RX_CONT);
3558 nic_data->datapath_caps &
3559 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN) ?
3560 EFX_QWORD_FIELD(*event, ESF_EZ_RX_ENCAP_HDR) :
3561 ESE_EZ_ENCAP_HDR_NONE;
3563 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_DROP_EVENT))
3564 netdev_WARN(efx->net_dev, "saw RX_DROP_EVENT: event="
3566 EFX_QWORD_VAL(*event));
3568 rx_queue = efx_channel_get_rx_queue(channel);
3570 if (unlikely(rx_queue_label != efx_rx_queue_index(rx_queue)))
3571 efx_ef10_handle_rx_wrong_queue(rx_queue, rx_queue_label);
3573 n_descs = ((next_ptr_lbits - rx_queue->removed_count) &
3574 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
3576 if (n_descs != rx_queue->scatter_n + 1) {
3577 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3579 /* detect rx abort */
3580 if (unlikely(n_descs == rx_queue->scatter_n)) {
3581 if (rx_queue->scatter_n == 0 || rx_bytes != 0)
3582 netdev_WARN(efx->net_dev,
3583 "invalid RX abort: scatter_n=%u event="
3585 rx_queue->scatter_n,
3586 EFX_QWORD_VAL(*event));
3587 efx_ef10_handle_rx_abort(rx_queue);
3591 /* Check that RX completion merging is valid, i.e.
3592 * the current firmware supports it and this is a
3593 * non-scattered packet.
3595 if (!(nic_data->datapath_caps &
3596 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN)) ||
3597 rx_queue->scatter_n != 0 || rx_cont) {
3598 efx_ef10_handle_rx_bad_lbits(
3599 rx_queue, next_ptr_lbits,
3600 (rx_queue->removed_count +
3601 rx_queue->scatter_n + 1) &
3602 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
3606 /* Merged completion for multiple non-scattered packets */
3607 rx_queue->scatter_n = 1;
3608 rx_queue->scatter_len = 0;
3609 n_packets = n_descs;
3610 ++channel->n_rx_merge_events;
3611 channel->n_rx_merge_packets += n_packets;
3612 flags |= EFX_RX_PKT_PREFIX_LEN;
3614 ++rx_queue->scatter_n;
3615 rx_queue->scatter_len += rx_bytes;
3621 EFX_POPULATE_QWORD_5(errors, ESF_DZ_RX_ECRC_ERR, 1,
3622 ESF_DZ_RX_IPCKSUM_ERR, 1,
3623 ESF_DZ_RX_TCPUDP_CKSUM_ERR, 1,
3624 ESF_EZ_RX_IP_INNER_CHKSUM_ERR, 1,
3625 ESF_EZ_RX_TCP_UDP_INNER_CHKSUM_ERR, 1);
3626 EFX_AND_QWORD(errors, *event, errors);
3627 if (unlikely(!EFX_QWORD_IS_ZERO(errors))) {
3628 flags |= efx_ef10_handle_rx_event_errors(channel, n_packets,
3630 rx_l3_class, rx_l4_class,
3633 bool tcpudp = rx_l4_class == ESE_FZ_L4_CLASS_TCP ||
3634 rx_l4_class == ESE_FZ_L4_CLASS_UDP;
3636 switch (rx_encap_hdr) {
3637 case ESE_EZ_ENCAP_HDR_VXLAN: /* VxLAN or GENEVE */
3638 flags |= EFX_RX_PKT_CSUMMED; /* outer UDP csum */
3640 flags |= EFX_RX_PKT_CSUM_LEVEL; /* inner L4 */
3642 case ESE_EZ_ENCAP_HDR_GRE:
3643 case ESE_EZ_ENCAP_HDR_NONE:
3645 flags |= EFX_RX_PKT_CSUMMED;
3648 netdev_WARN(efx->net_dev,
3649 "unknown encapsulation type: event="
3651 EFX_QWORD_VAL(*event));
3655 if (rx_l4_class == ESE_FZ_L4_CLASS_TCP)
3656 flags |= EFX_RX_PKT_TCP;
3658 channel->irq_mod_score += 2 * n_packets;
3660 /* Handle received packet(s) */
3661 for (i = 0; i < n_packets; i++) {
3662 efx_rx_packet(rx_queue,
3663 rx_queue->removed_count & rx_queue->ptr_mask,
3664 rx_queue->scatter_n, rx_queue->scatter_len,
3666 rx_queue->removed_count += rx_queue->scatter_n;
3669 rx_queue->scatter_n = 0;
3670 rx_queue->scatter_len = 0;
3675 static u32 efx_ef10_extract_event_ts(efx_qword_t *event)
3679 tstamp = EFX_QWORD_FIELD(*event, TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI);
3681 tstamp |= EFX_QWORD_FIELD(*event, TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO);
3687 efx_ef10_handle_tx_event(struct efx_channel *channel, efx_qword_t *event)
3689 struct efx_nic *efx = channel->efx;
3690 struct efx_tx_queue *tx_queue;
3691 unsigned int tx_ev_desc_ptr;
3692 unsigned int tx_ev_q_label;
3693 unsigned int tx_ev_type;
3696 if (unlikely(READ_ONCE(efx->reset_pending)))
3699 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_TX_DROP_EVENT)))
3702 /* Get the transmit queue */
3703 tx_ev_q_label = EFX_QWORD_FIELD(*event, ESF_DZ_TX_QLABEL);
3704 tx_queue = efx_channel_get_tx_queue(channel,
3705 tx_ev_q_label % EFX_TXQ_TYPES);
3707 if (!tx_queue->timestamping) {
3708 /* Transmit completion */
3709 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, ESF_DZ_TX_DESCR_INDX);
3710 efx_xmit_done(tx_queue, tx_ev_desc_ptr & tx_queue->ptr_mask);
3714 /* Transmit timestamps are only available for 8XXX series. They result
3715 * in three events per packet. These occur in order, and are:
3716 * - the normal completion event
3717 * - the low part of the timestamp
3718 * - the high part of the timestamp
3720 * Each part of the timestamp is itself split across two 16 bit
3721 * fields in the event.
3723 tx_ev_type = EFX_QWORD_FIELD(*event, ESF_EZ_TX_SOFT1);
3725 switch (tx_ev_type) {
3726 case TX_TIMESTAMP_EVENT_TX_EV_COMPLETION:
3727 /* In case of Queue flush or FLR, we might have received
3728 * the previous TX completion event but not the Timestamp
3731 if (tx_queue->completed_desc_ptr != tx_queue->ptr_mask)
3732 efx_xmit_done(tx_queue, tx_queue->completed_desc_ptr);
3734 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event,
3735 ESF_DZ_TX_DESCR_INDX);
3736 tx_queue->completed_desc_ptr =
3737 tx_ev_desc_ptr & tx_queue->ptr_mask;
3740 case TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_LO:
3741 ts_part = efx_ef10_extract_event_ts(event);
3742 tx_queue->completed_timestamp_minor = ts_part;
3745 case TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_HI:
3746 ts_part = efx_ef10_extract_event_ts(event);
3747 tx_queue->completed_timestamp_major = ts_part;
3749 efx_xmit_done(tx_queue, tx_queue->completed_desc_ptr);
3750 tx_queue->completed_desc_ptr = tx_queue->ptr_mask;
3754 netif_err(efx, hw, efx->net_dev,
3755 "channel %d unknown tx event type %d (data "
3756 EFX_QWORD_FMT ")\n",
3757 channel->channel, tx_ev_type,
3758 EFX_QWORD_VAL(*event));
3764 efx_ef10_handle_driver_event(struct efx_channel *channel, efx_qword_t *event)
3766 struct efx_nic *efx = channel->efx;
3769 subcode = EFX_QWORD_FIELD(*event, ESF_DZ_DRV_SUB_CODE);
3772 case ESE_DZ_DRV_TIMER_EV:
3773 case ESE_DZ_DRV_WAKE_UP_EV:
3775 case ESE_DZ_DRV_START_UP_EV:
3776 /* event queue init complete. ok. */
3779 netif_err(efx, hw, efx->net_dev,
3780 "channel %d unknown driver event type %d"
3781 " (data " EFX_QWORD_FMT ")\n",
3782 channel->channel, subcode,
3783 EFX_QWORD_VAL(*event));
3788 static void efx_ef10_handle_driver_generated_event(struct efx_channel *channel,
3791 struct efx_nic *efx = channel->efx;
3794 subcode = EFX_QWORD_FIELD(*event, EFX_DWORD_0);
3798 channel->event_test_cpu = raw_smp_processor_id();
3800 case EFX_EF10_REFILL:
3801 /* The queue must be empty, so we won't receive any rx
3802 * events, so efx_process_channel() won't refill the
3803 * queue. Refill it here
3805 efx_fast_push_rx_descriptors(&channel->rx_queue, true);
3808 netif_err(efx, hw, efx->net_dev,
3809 "channel %d unknown driver event type %u"
3810 " (data " EFX_QWORD_FMT ")\n",
3811 channel->channel, (unsigned) subcode,
3812 EFX_QWORD_VAL(*event));
3816 static int efx_ef10_ev_process(struct efx_channel *channel, int quota)
3818 struct efx_nic *efx = channel->efx;
3819 efx_qword_t event, *p_event;
3820 unsigned int read_ptr;
3827 read_ptr = channel->eventq_read_ptr;
3830 p_event = efx_event(channel, read_ptr);
3833 if (!efx_event_present(&event))
3836 EFX_SET_QWORD(*p_event);
3840 ev_code = EFX_QWORD_FIELD(event, ESF_DZ_EV_CODE);
3842 netif_vdbg(efx, drv, efx->net_dev,
3843 "processing event on %d " EFX_QWORD_FMT "\n",
3844 channel->channel, EFX_QWORD_VAL(event));
3847 case ESE_DZ_EV_CODE_MCDI_EV:
3848 efx_mcdi_process_event(channel, &event);
3850 case ESE_DZ_EV_CODE_RX_EV:
3851 spent += efx_ef10_handle_rx_event(channel, &event);
3852 if (spent >= quota) {
3853 /* XXX can we split a merged event to
3854 * avoid going over-quota?
3860 case ESE_DZ_EV_CODE_TX_EV:
3861 efx_ef10_handle_tx_event(channel, &event);
3863 case ESE_DZ_EV_CODE_DRIVER_EV:
3864 efx_ef10_handle_driver_event(channel, &event);
3865 if (++spent == quota)
3868 case EFX_EF10_DRVGEN_EV:
3869 efx_ef10_handle_driver_generated_event(channel, &event);
3872 netif_err(efx, hw, efx->net_dev,
3873 "channel %d unknown event type %d"
3874 " (data " EFX_QWORD_FMT ")\n",
3875 channel->channel, ev_code,
3876 EFX_QWORD_VAL(event));
3881 channel->eventq_read_ptr = read_ptr;
3885 static void efx_ef10_ev_read_ack(struct efx_channel *channel)
3887 struct efx_nic *efx = channel->efx;
3890 if (EFX_EF10_WORKAROUND_35388(efx)) {
3891 BUILD_BUG_ON(EFX_MIN_EVQ_SIZE <
3892 (1 << ERF_DD_EVQ_IND_RPTR_WIDTH));
3893 BUILD_BUG_ON(EFX_MAX_EVQ_SIZE >
3894 (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH));
3896 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
3897 EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH,
3898 ERF_DD_EVQ_IND_RPTR,
3899 (channel->eventq_read_ptr &
3900 channel->eventq_mask) >>
3901 ERF_DD_EVQ_IND_RPTR_WIDTH);
3902 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
3904 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
3905 EFE_DD_EVQ_IND_RPTR_FLAGS_LOW,
3906 ERF_DD_EVQ_IND_RPTR,
3907 channel->eventq_read_ptr &
3908 ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1));
3909 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
3912 EFX_POPULATE_DWORD_1(rptr, ERF_DZ_EVQ_RPTR,
3913 channel->eventq_read_ptr &
3914 channel->eventq_mask);
3915 efx_writed_page(efx, &rptr, ER_DZ_EVQ_RPTR, channel->channel);
3919 static void efx_ef10_ev_test_generate(struct efx_channel *channel)
3921 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
3922 struct efx_nic *efx = channel->efx;
3926 EFX_POPULATE_QWORD_2(event,
3927 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
3928 ESF_DZ_EV_DATA, EFX_EF10_TEST);
3930 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
3932 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
3933 * already swapped the data to little-endian order.
3935 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
3936 sizeof(efx_qword_t));
3938 rc = efx_mcdi_rpc(efx, MC_CMD_DRIVER_EVENT, inbuf, sizeof(inbuf),
3947 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
3950 void efx_ef10_handle_drain_event(struct efx_nic *efx)
3952 if (atomic_dec_and_test(&efx->active_queues))
3953 wake_up(&efx->flush_wq);
3955 WARN_ON(atomic_read(&efx->active_queues) < 0);
3958 static int efx_ef10_fini_dmaq(struct efx_nic *efx)
3960 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3961 struct efx_channel *channel;
3962 struct efx_tx_queue *tx_queue;
3963 struct efx_rx_queue *rx_queue;
3966 /* If the MC has just rebooted, the TX/RX queues will have already been
3967 * torn down, but efx->active_queues needs to be set to zero.
3969 if (nic_data->must_realloc_vis) {
3970 atomic_set(&efx->active_queues, 0);
3974 /* Do not attempt to write to the NIC during EEH recovery */
3975 if (efx->state != STATE_RECOVERY) {
3976 efx_for_each_channel(channel, efx) {
3977 efx_for_each_channel_rx_queue(rx_queue, channel)
3978 efx_ef10_rx_fini(rx_queue);
3979 efx_for_each_channel_tx_queue(tx_queue, channel)
3980 efx_ef10_tx_fini(tx_queue);
3983 wait_event_timeout(efx->flush_wq,
3984 atomic_read(&efx->active_queues) == 0,
3985 msecs_to_jiffies(EFX_MAX_FLUSH_TIME));
3986 pending = atomic_read(&efx->active_queues);
3988 netif_err(efx, hw, efx->net_dev, "failed to flush %d queues\n",
3997 static void efx_ef10_prepare_flr(struct efx_nic *efx)
3999 atomic_set(&efx->active_queues, 0);
4002 static bool efx_ef10_filter_equal(const struct efx_filter_spec *left,
4003 const struct efx_filter_spec *right)
4005 if ((left->match_flags ^ right->match_flags) |
4006 ((left->flags ^ right->flags) &
4007 (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)))
4010 return memcmp(&left->outer_vid, &right->outer_vid,
4011 sizeof(struct efx_filter_spec) -
4012 offsetof(struct efx_filter_spec, outer_vid)) == 0;
4015 static unsigned int efx_ef10_filter_hash(const struct efx_filter_spec *spec)
4017 BUILD_BUG_ON(offsetof(struct efx_filter_spec, outer_vid) & 3);
4018 return jhash2((const u32 *)&spec->outer_vid,
4019 (sizeof(struct efx_filter_spec) -
4020 offsetof(struct efx_filter_spec, outer_vid)) / 4,
4022 /* XXX should we randomise the initval? */
4025 /* Decide whether a filter should be exclusive or else should allow
4026 * delivery to additional recipients. Currently we decide that
4027 * filters for specific local unicast MAC and IP addresses are
4030 static bool efx_ef10_filter_is_exclusive(const struct efx_filter_spec *spec)
4032 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC &&
4033 !is_multicast_ether_addr(spec->loc_mac))
4036 if ((spec->match_flags &
4037 (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) ==
4038 (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) {
4039 if (spec->ether_type == htons(ETH_P_IP) &&
4040 !ipv4_is_multicast(spec->loc_host[0]))
4042 if (spec->ether_type == htons(ETH_P_IPV6) &&
4043 ((const u8 *)spec->loc_host)[0] != 0xff)
4050 static struct efx_filter_spec *
4051 efx_ef10_filter_entry_spec(const struct efx_ef10_filter_table *table,
4052 unsigned int filter_idx)
4054 return (struct efx_filter_spec *)(table->entry[filter_idx].spec &
4055 ~EFX_EF10_FILTER_FLAGS);
4059 efx_ef10_filter_entry_flags(const struct efx_ef10_filter_table *table,
4060 unsigned int filter_idx)
4062 return table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAGS;
4066 efx_ef10_filter_set_entry(struct efx_ef10_filter_table *table,
4067 unsigned int filter_idx,
4068 const struct efx_filter_spec *spec,
4071 table->entry[filter_idx].spec = (unsigned long)spec | flags;
4075 efx_ef10_filter_push_prep_set_match_fields(struct efx_nic *efx,
4076 const struct efx_filter_spec *spec,
4079 enum efx_encap_type encap_type = efx_filter_get_encap_type(spec);
4080 u32 match_fields = 0, uc_match, mc_match;
4082 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
4083 efx_ef10_filter_is_exclusive(spec) ?
4084 MC_CMD_FILTER_OP_IN_OP_INSERT :
4085 MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE);
4087 /* Convert match flags and values. Unlike almost
4088 * everything else in MCDI, these fields are in
4089 * network byte order.
4091 #define COPY_VALUE(value, mcdi_field) \
4094 1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \
4095 mcdi_field ## _LBN; \
4097 MC_CMD_FILTER_OP_IN_ ## mcdi_field ## _LEN < \
4099 memcpy(MCDI_PTR(inbuf, FILTER_OP_IN_ ## mcdi_field), \
4100 &value, sizeof(value)); \
4102 #define COPY_FIELD(gen_flag, gen_field, mcdi_field) \
4103 if (spec->match_flags & EFX_FILTER_MATCH_ ## gen_flag) { \
4104 COPY_VALUE(spec->gen_field, mcdi_field); \
4106 /* Handle encap filters first. They will always be mismatch
4107 * (unknown UC or MC) filters
4110 /* ether_type and outer_ip_proto need to be variables
4111 * because COPY_VALUE wants to memcpy them
4114 htons(encap_type & EFX_ENCAP_FLAG_IPV6 ?
4115 ETH_P_IPV6 : ETH_P_IP);
4116 u8 vni_type = MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_GENEVE;
4119 switch (encap_type & EFX_ENCAP_TYPES_MASK) {
4120 case EFX_ENCAP_TYPE_VXLAN:
4121 vni_type = MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_VXLAN;
4123 case EFX_ENCAP_TYPE_GENEVE:
4124 COPY_VALUE(ether_type, ETHER_TYPE);
4125 outer_ip_proto = IPPROTO_UDP;
4126 COPY_VALUE(outer_ip_proto, IP_PROTO);
4127 /* We always need to set the type field, even
4128 * though we're not matching on the TNI.
4130 MCDI_POPULATE_DWORD_1(inbuf,
4131 FILTER_OP_EXT_IN_VNI_OR_VSID,
4132 FILTER_OP_EXT_IN_VNI_TYPE,
4135 case EFX_ENCAP_TYPE_NVGRE:
4136 COPY_VALUE(ether_type, ETHER_TYPE);
4137 outer_ip_proto = IPPROTO_GRE;
4138 COPY_VALUE(outer_ip_proto, IP_PROTO);
4144 uc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_LBN;
4145 mc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_LBN;
4147 uc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_LBN;
4148 mc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_LBN;
4151 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC_IG)
4153 is_multicast_ether_addr(spec->loc_mac) ?
4156 COPY_FIELD(REM_HOST, rem_host, SRC_IP);
4157 COPY_FIELD(LOC_HOST, loc_host, DST_IP);
4158 COPY_FIELD(REM_MAC, rem_mac, SRC_MAC);
4159 COPY_FIELD(REM_PORT, rem_port, SRC_PORT);
4160 COPY_FIELD(LOC_MAC, loc_mac, DST_MAC);
4161 COPY_FIELD(LOC_PORT, loc_port, DST_PORT);
4162 COPY_FIELD(ETHER_TYPE, ether_type, ETHER_TYPE);
4163 COPY_FIELD(INNER_VID, inner_vid, INNER_VLAN);
4164 COPY_FIELD(OUTER_VID, outer_vid, OUTER_VLAN);
4165 COPY_FIELD(IP_PROTO, ip_proto, IP_PROTO);
4168 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_MATCH_FIELDS,
4172 static void efx_ef10_filter_push_prep(struct efx_nic *efx,
4173 const struct efx_filter_spec *spec,
4174 efx_dword_t *inbuf, u64 handle,
4175 struct efx_rss_context *ctx,
4178 struct efx_ef10_nic_data *nic_data = efx->nic_data;
4179 u32 flags = spec->flags;
4181 memset(inbuf, 0, MC_CMD_FILTER_OP_EXT_IN_LEN);
4183 /* If RSS filter, caller better have given us an RSS context */
4184 if (flags & EFX_FILTER_FLAG_RX_RSS) {
4185 /* We don't have the ability to return an error, so we'll just
4186 * log a warning and disable RSS for the filter.
4188 if (WARN_ON_ONCE(!ctx))
4189 flags &= ~EFX_FILTER_FLAG_RX_RSS;
4190 else if (WARN_ON_ONCE(ctx->context_id == EFX_EF10_RSS_CONTEXT_INVALID))
4191 flags &= ~EFX_FILTER_FLAG_RX_RSS;
4195 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
4196 MC_CMD_FILTER_OP_IN_OP_REPLACE);
4197 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, handle);
4199 efx_ef10_filter_push_prep_set_match_fields(efx, spec, inbuf);
4202 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_PORT_ID, nic_data->vport_id);
4203 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_DEST,
4204 spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
4205 MC_CMD_FILTER_OP_IN_RX_DEST_DROP :
4206 MC_CMD_FILTER_OP_IN_RX_DEST_HOST);
4207 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DOMAIN, 0);
4208 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DEST,
4209 MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT);
4210 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_QUEUE,
4211 spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
4213 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_MODE,
4214 (flags & EFX_FILTER_FLAG_RX_RSS) ?
4215 MC_CMD_FILTER_OP_IN_RX_MODE_RSS :
4216 MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE);
4217 if (flags & EFX_FILTER_FLAG_RX_RSS)
4218 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_CONTEXT, ctx->context_id);
4221 static int efx_ef10_filter_push(struct efx_nic *efx,
4222 const struct efx_filter_spec *spec, u64 *handle,
4223 struct efx_rss_context *ctx, bool replacing)
4225 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_EXT_IN_LEN);
4226 MCDI_DECLARE_BUF(outbuf, MC_CMD_FILTER_OP_EXT_OUT_LEN);
4229 efx_ef10_filter_push_prep(efx, spec, inbuf, *handle, ctx, replacing);
4230 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
4231 outbuf, sizeof(outbuf), NULL);
4233 *handle = MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
4235 rc = -EBUSY; /* to match efx_farch_filter_insert() */
4239 static u32 efx_ef10_filter_mcdi_flags_from_spec(const struct efx_filter_spec *spec)
4241 enum efx_encap_type encap_type = efx_filter_get_encap_type(spec);
4242 unsigned int match_flags = spec->match_flags;
4243 unsigned int uc_match, mc_match;
4246 #define MAP_FILTER_TO_MCDI_FLAG(gen_flag, mcdi_field, encap) { \
4247 unsigned int old_match_flags = match_flags; \
4248 match_flags &= ~EFX_FILTER_MATCH_ ## gen_flag; \
4249 if (match_flags != old_match_flags) \
4252 MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_ ## \
4253 mcdi_field ## _LBN : \
4254 MC_CMD_FILTER_OP_EXT_IN_MATCH_ ##\
4255 mcdi_field ## _LBN)); \
4257 /* inner or outer based on encap type */
4258 MAP_FILTER_TO_MCDI_FLAG(REM_HOST, SRC_IP, encap_type);
4259 MAP_FILTER_TO_MCDI_FLAG(LOC_HOST, DST_IP, encap_type);
4260 MAP_FILTER_TO_MCDI_FLAG(REM_MAC, SRC_MAC, encap_type);
4261 MAP_FILTER_TO_MCDI_FLAG(REM_PORT, SRC_PORT, encap_type);
4262 MAP_FILTER_TO_MCDI_FLAG(LOC_MAC, DST_MAC, encap_type);
4263 MAP_FILTER_TO_MCDI_FLAG(LOC_PORT, DST_PORT, encap_type);
4264 MAP_FILTER_TO_MCDI_FLAG(ETHER_TYPE, ETHER_TYPE, encap_type);
4265 MAP_FILTER_TO_MCDI_FLAG(IP_PROTO, IP_PROTO, encap_type);
4267 MAP_FILTER_TO_MCDI_FLAG(INNER_VID, INNER_VLAN, false);
4268 MAP_FILTER_TO_MCDI_FLAG(OUTER_VID, OUTER_VLAN, false);
4269 #undef MAP_FILTER_TO_MCDI_FLAG
4271 /* special handling for encap type, and mismatch */
4273 match_flags &= ~EFX_FILTER_MATCH_ENCAP_TYPE;
4275 (1 << MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_LBN);
4276 mcdi_flags |= (1 << MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_LBN);
4278 uc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_LBN;
4279 mc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_LBN;
4281 uc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_LBN;
4282 mc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_LBN;
4285 if (match_flags & EFX_FILTER_MATCH_LOC_MAC_IG) {
4286 match_flags &= ~EFX_FILTER_MATCH_LOC_MAC_IG;
4288 is_multicast_ether_addr(spec->loc_mac) ?
4293 /* Did we map them all? */
4294 WARN_ON_ONCE(match_flags);
4299 static int efx_ef10_filter_pri(struct efx_ef10_filter_table *table,
4300 const struct efx_filter_spec *spec)
4302 u32 mcdi_flags = efx_ef10_filter_mcdi_flags_from_spec(spec);
4303 unsigned int match_pri;
4306 match_pri < table->rx_match_count;
4308 if (table->rx_match_mcdi_flags[match_pri] == mcdi_flags)
4311 return -EPROTONOSUPPORT;
4314 static s32 efx_ef10_filter_insert(struct efx_nic *efx,
4315 struct efx_filter_spec *spec,
4318 DECLARE_BITMAP(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
4319 struct efx_ef10_nic_data *nic_data = efx->nic_data;
4320 struct efx_ef10_filter_table *table;
4321 struct efx_filter_spec *saved_spec;
4322 struct efx_rss_context *ctx = NULL;
4323 unsigned int match_pri, hash;
4324 unsigned int priv_flags;
4325 bool rss_locked = false;
4326 bool replacing = false;
4327 unsigned int depth, i;
4333 down_read(&efx->filter_sem);
4334 table = efx->filter_state;
4335 down_write(&table->lock);
4337 /* For now, only support RX filters */
4338 if ((spec->flags & (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)) !=
4339 EFX_FILTER_FLAG_RX) {
4344 rc = efx_ef10_filter_pri(table, spec);
4349 hash = efx_ef10_filter_hash(spec);
4350 is_mc_recip = efx_filter_is_mc_recipient(spec);
4352 bitmap_zero(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
4354 if (spec->flags & EFX_FILTER_FLAG_RX_RSS) {
4355 mutex_lock(&efx->rss_lock);
4357 if (spec->rss_context)
4358 ctx = efx_find_rss_context_entry(efx, spec->rss_context);
4360 ctx = &efx->rss_context;
4365 if (ctx->context_id == EFX_EF10_RSS_CONTEXT_INVALID) {
4371 /* Find any existing filters with the same match tuple or
4372 * else a free slot to insert at.
4374 for (depth = 1; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
4375 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
4376 saved_spec = efx_ef10_filter_entry_spec(table, i);
4381 } else if (efx_ef10_filter_equal(spec, saved_spec)) {
4382 if (spec->priority < saved_spec->priority &&
4383 spec->priority != EFX_FILTER_PRI_AUTO) {
4388 /* This is the only one */
4389 if (spec->priority ==
4390 saved_spec->priority &&
4397 } else if (spec->priority >
4398 saved_spec->priority ||
4400 saved_spec->priority &&
4405 __set_bit(depth, mc_rem_map);
4410 /* Once we reach the maximum search depth, use the first suitable
4411 * slot, or return -EBUSY if there was none
4413 if (ins_index < 0) {
4418 /* Create a software table entry if necessary. */
4419 saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
4421 if (spec->priority == EFX_FILTER_PRI_AUTO &&
4422 saved_spec->priority >= EFX_FILTER_PRI_AUTO) {
4423 /* Just make sure it won't be removed */
4424 if (saved_spec->priority > EFX_FILTER_PRI_AUTO)
4425 saved_spec->flags |= EFX_FILTER_FLAG_RX_OVER_AUTO;
4426 table->entry[ins_index].spec &=
4427 ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
4432 priv_flags = efx_ef10_filter_entry_flags(table, ins_index);
4434 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
4439 *saved_spec = *spec;
4442 efx_ef10_filter_set_entry(table, ins_index, saved_spec, priv_flags);
4444 /* Actually insert the filter on the HW */
4445 rc = efx_ef10_filter_push(efx, spec, &table->entry[ins_index].handle,
4448 if (rc == -EINVAL && nic_data->must_realloc_vis)
4449 /* The MC rebooted under us, causing it to reject our filter
4450 * insertion as pointing to an invalid VI (spec->dmaq_id).
4454 /* Finalise the software table entry */
4457 /* Update the fields that may differ */
4458 if (saved_spec->priority == EFX_FILTER_PRI_AUTO)
4459 saved_spec->flags |=
4460 EFX_FILTER_FLAG_RX_OVER_AUTO;
4461 saved_spec->priority = spec->priority;
4462 saved_spec->flags &= EFX_FILTER_FLAG_RX_OVER_AUTO;
4463 saved_spec->flags |= spec->flags;
4464 saved_spec->rss_context = spec->rss_context;
4465 saved_spec->dmaq_id = spec->dmaq_id;
4467 } else if (!replacing) {
4471 /* We failed to replace, so the old filter is still present.
4472 * Roll back the software table to reflect this. In fact the
4473 * efx_ef10_filter_set_entry() call below will do the right
4474 * thing, so nothing extra is needed here.
4477 efx_ef10_filter_set_entry(table, ins_index, saved_spec, priv_flags);
4479 /* Remove and finalise entries for lower-priority multicast
4483 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_EXT_IN_LEN);
4484 unsigned int depth, i;
4486 memset(inbuf, 0, sizeof(inbuf));
4488 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
4489 if (!test_bit(depth, mc_rem_map))
4492 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
4493 saved_spec = efx_ef10_filter_entry_spec(table, i);
4494 priv_flags = efx_ef10_filter_entry_flags(table, i);
4497 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
4498 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
4499 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
4500 table->entry[i].handle);
4501 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
4502 inbuf, sizeof(inbuf),
4511 efx_ef10_filter_set_entry(table, i, saved_spec,
4516 /* If successful, return the inserted filter ID */
4518 rc = efx_ef10_make_filter_id(match_pri, ins_index);
4522 mutex_unlock(&efx->rss_lock);
4523 up_write(&table->lock);
4524 up_read(&efx->filter_sem);
4528 static void efx_ef10_filter_update_rx_scatter(struct efx_nic *efx)
4530 /* no need to do anything here on EF10 */
4534 * If !by_index, remove by ID
4535 * If by_index, remove by index
4536 * Filter ID may come from userland and must be range-checked.
4537 * Caller must hold efx->filter_sem for read, and efx->filter_state->lock
4540 static int efx_ef10_filter_remove_internal(struct efx_nic *efx,
4541 unsigned int priority_mask,
4542 u32 filter_id, bool by_index)
4544 unsigned int filter_idx = efx_ef10_filter_get_unsafe_id(filter_id);
4545 struct efx_ef10_filter_table *table = efx->filter_state;
4546 MCDI_DECLARE_BUF(inbuf,
4547 MC_CMD_FILTER_OP_IN_HANDLE_OFST +
4548 MC_CMD_FILTER_OP_IN_HANDLE_LEN);
4549 struct efx_filter_spec *spec;
4553 spec = efx_ef10_filter_entry_spec(table, filter_idx);
4556 efx_ef10_filter_pri(table, spec) !=
4557 efx_ef10_filter_get_unsafe_pri(filter_id)))
4560 if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO &&
4561 priority_mask == (1U << EFX_FILTER_PRI_AUTO)) {
4562 /* Just remove flags */
4563 spec->flags &= ~EFX_FILTER_FLAG_RX_OVER_AUTO;
4564 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
4568 if (!(priority_mask & (1U << spec->priority)))
4571 if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO) {
4572 /* Reset to an automatic filter */
4574 struct efx_filter_spec new_spec = *spec;
4576 new_spec.priority = EFX_FILTER_PRI_AUTO;
4577 new_spec.flags = (EFX_FILTER_FLAG_RX |
4578 (efx_rss_active(&efx->rss_context) ?
4579 EFX_FILTER_FLAG_RX_RSS : 0));
4580 new_spec.dmaq_id = 0;
4581 new_spec.rss_context = 0;
4582 rc = efx_ef10_filter_push(efx, &new_spec,
4583 &table->entry[filter_idx].handle,
4590 /* Really remove the filter */
4592 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
4593 efx_ef10_filter_is_exclusive(spec) ?
4594 MC_CMD_FILTER_OP_IN_OP_REMOVE :
4595 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
4596 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
4597 table->entry[filter_idx].handle);
4598 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FILTER_OP,
4599 inbuf, sizeof(inbuf), NULL, 0, NULL);
4601 if ((rc == 0) || (rc == -ENOENT)) {
4602 /* Filter removed OK or didn't actually exist */
4604 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
4606 efx_mcdi_display_error(efx, MC_CMD_FILTER_OP,
4607 MC_CMD_FILTER_OP_EXT_IN_LEN,
4615 static int efx_ef10_filter_remove_safe(struct efx_nic *efx,
4616 enum efx_filter_priority priority,
4619 struct efx_ef10_filter_table *table;
4622 down_read(&efx->filter_sem);
4623 table = efx->filter_state;
4624 down_write(&table->lock);
4625 rc = efx_ef10_filter_remove_internal(efx, 1U << priority, filter_id,
4627 up_write(&table->lock);
4628 up_read(&efx->filter_sem);
4632 /* Caller must hold efx->filter_sem for read */
4633 static void efx_ef10_filter_remove_unsafe(struct efx_nic *efx,
4634 enum efx_filter_priority priority,
4637 struct efx_ef10_filter_table *table = efx->filter_state;
4639 if (filter_id == EFX_EF10_FILTER_ID_INVALID)
4642 down_write(&table->lock);
4643 efx_ef10_filter_remove_internal(efx, 1U << priority, filter_id,
4645 up_write(&table->lock);
4648 static int efx_ef10_filter_get_safe(struct efx_nic *efx,
4649 enum efx_filter_priority priority,
4650 u32 filter_id, struct efx_filter_spec *spec)
4652 unsigned int filter_idx = efx_ef10_filter_get_unsafe_id(filter_id);
4653 const struct efx_filter_spec *saved_spec;
4654 struct efx_ef10_filter_table *table;
4657 down_read(&efx->filter_sem);
4658 table = efx->filter_state;
4659 down_read(&table->lock);
4660 saved_spec = efx_ef10_filter_entry_spec(table, filter_idx);
4661 if (saved_spec && saved_spec->priority == priority &&
4662 efx_ef10_filter_pri(table, saved_spec) ==
4663 efx_ef10_filter_get_unsafe_pri(filter_id)) {
4664 *spec = *saved_spec;
4669 up_read(&table->lock);
4670 up_read(&efx->filter_sem);
4674 static int efx_ef10_filter_clear_rx(struct efx_nic *efx,
4675 enum efx_filter_priority priority)
4677 struct efx_ef10_filter_table *table;
4678 unsigned int priority_mask;
4682 priority_mask = (((1U << (priority + 1)) - 1) &
4683 ~(1U << EFX_FILTER_PRI_AUTO));
4685 down_read(&efx->filter_sem);
4686 table = efx->filter_state;
4687 down_write(&table->lock);
4688 for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
4689 rc = efx_ef10_filter_remove_internal(efx, priority_mask,
4691 if (rc && rc != -ENOENT)
4696 up_write(&table->lock);
4697 up_read(&efx->filter_sem);
4701 static u32 efx_ef10_filter_count_rx_used(struct efx_nic *efx,
4702 enum efx_filter_priority priority)
4704 struct efx_ef10_filter_table *table;
4705 unsigned int filter_idx;
4708 down_read(&efx->filter_sem);
4709 table = efx->filter_state;
4710 down_read(&table->lock);
4711 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
4712 if (table->entry[filter_idx].spec &&
4713 efx_ef10_filter_entry_spec(table, filter_idx)->priority ==
4717 up_read(&table->lock);
4718 up_read(&efx->filter_sem);
4722 static u32 efx_ef10_filter_get_rx_id_limit(struct efx_nic *efx)
4724 struct efx_ef10_filter_table *table = efx->filter_state;
4726 return table->rx_match_count * HUNT_FILTER_TBL_ROWS * 2;
4729 static s32 efx_ef10_filter_get_rx_ids(struct efx_nic *efx,
4730 enum efx_filter_priority priority,
4733 struct efx_ef10_filter_table *table;
4734 struct efx_filter_spec *spec;
4735 unsigned int filter_idx;
4738 down_read(&efx->filter_sem);
4739 table = efx->filter_state;
4740 down_read(&table->lock);
4742 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
4743 spec = efx_ef10_filter_entry_spec(table, filter_idx);
4744 if (spec && spec->priority == priority) {
4745 if (count == size) {
4750 efx_ef10_make_filter_id(
4751 efx_ef10_filter_pri(table, spec),
4755 up_read(&table->lock);
4756 up_read(&efx->filter_sem);
4760 #ifdef CONFIG_RFS_ACCEL
4762 static bool efx_ef10_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id,
4763 unsigned int filter_idx)
4765 struct efx_ef10_filter_table *table;
4766 struct efx_filter_spec *spec;
4769 down_read(&efx->filter_sem);
4770 table = efx->filter_state;
4771 down_write(&table->lock);
4772 spec = efx_ef10_filter_entry_spec(table, filter_idx);
4774 if (!spec || spec->priority != EFX_FILTER_PRI_HINT) {
4779 if (!rps_may_expire_flow(efx->net_dev, spec->dmaq_id, flow_id, 0)) {
4784 ret = efx_ef10_filter_remove_internal(efx, 1U << spec->priority,
4785 filter_idx, true) == 0;
4787 up_write(&table->lock);
4788 up_read(&efx->filter_sem);
4792 #endif /* CONFIG_RFS_ACCEL */
4794 static int efx_ef10_filter_match_flags_from_mcdi(bool encap, u32 mcdi_flags)
4796 int match_flags = 0;
4798 #define MAP_FLAG(gen_flag, mcdi_field) do { \
4799 u32 old_mcdi_flags = mcdi_flags; \
4800 mcdi_flags &= ~(1 << MC_CMD_FILTER_OP_EXT_IN_MATCH_ ## \
4801 mcdi_field ## _LBN); \
4802 if (mcdi_flags != old_mcdi_flags) \
4803 match_flags |= EFX_FILTER_MATCH_ ## gen_flag; \
4807 /* encap filters must specify encap type */
4808 match_flags |= EFX_FILTER_MATCH_ENCAP_TYPE;
4809 /* and imply ethertype and ip proto */
4811 ~(1 << MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_LBN);
4813 ~(1 << MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_LBN);
4814 /* VLAN tags refer to the outer packet */
4815 MAP_FLAG(INNER_VID, INNER_VLAN);
4816 MAP_FLAG(OUTER_VID, OUTER_VLAN);
4817 /* everything else refers to the inner packet */
4818 MAP_FLAG(LOC_MAC_IG, IFRM_UNKNOWN_UCAST_DST);
4819 MAP_FLAG(LOC_MAC_IG, IFRM_UNKNOWN_MCAST_DST);
4820 MAP_FLAG(REM_HOST, IFRM_SRC_IP);
4821 MAP_FLAG(LOC_HOST, IFRM_DST_IP);
4822 MAP_FLAG(REM_MAC, IFRM_SRC_MAC);
4823 MAP_FLAG(REM_PORT, IFRM_SRC_PORT);
4824 MAP_FLAG(LOC_MAC, IFRM_DST_MAC);
4825 MAP_FLAG(LOC_PORT, IFRM_DST_PORT);
4826 MAP_FLAG(ETHER_TYPE, IFRM_ETHER_TYPE);
4827 MAP_FLAG(IP_PROTO, IFRM_IP_PROTO);
4829 MAP_FLAG(LOC_MAC_IG, UNKNOWN_UCAST_DST);
4830 MAP_FLAG(LOC_MAC_IG, UNKNOWN_MCAST_DST);
4831 MAP_FLAG(REM_HOST, SRC_IP);
4832 MAP_FLAG(LOC_HOST, DST_IP);
4833 MAP_FLAG(REM_MAC, SRC_MAC);
4834 MAP_FLAG(REM_PORT, SRC_PORT);
4835 MAP_FLAG(LOC_MAC, DST_MAC);
4836 MAP_FLAG(LOC_PORT, DST_PORT);
4837 MAP_FLAG(ETHER_TYPE, ETHER_TYPE);
4838 MAP_FLAG(INNER_VID, INNER_VLAN);
4839 MAP_FLAG(OUTER_VID, OUTER_VLAN);
4840 MAP_FLAG(IP_PROTO, IP_PROTO);
4844 /* Did we map them all? */
4851 static void efx_ef10_filter_cleanup_vlans(struct efx_nic *efx)
4853 struct efx_ef10_filter_table *table = efx->filter_state;
4854 struct efx_ef10_filter_vlan *vlan, *next_vlan;
4856 /* See comment in efx_ef10_filter_table_remove() */
4857 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
4863 list_for_each_entry_safe(vlan, next_vlan, &table->vlan_list, list)
4864 efx_ef10_filter_del_vlan_internal(efx, vlan);
4867 static bool efx_ef10_filter_match_supported(struct efx_ef10_filter_table *table,
4869 enum efx_filter_match_flags match_flags)
4871 unsigned int match_pri;
4875 match_pri < table->rx_match_count;
4877 mf = efx_ef10_filter_match_flags_from_mcdi(encap,
4878 table->rx_match_mcdi_flags[match_pri]);
4879 if (mf == match_flags)
4887 efx_ef10_filter_table_probe_matches(struct efx_nic *efx,
4888 struct efx_ef10_filter_table *table,
4891 MCDI_DECLARE_BUF(inbuf, MC_CMD_GET_PARSER_DISP_INFO_IN_LEN);
4892 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX);
4893 unsigned int pd_match_pri, pd_match_count;
4897 /* Find out which RX filter types are supported, and their priorities */
4898 MCDI_SET_DWORD(inbuf, GET_PARSER_DISP_INFO_IN_OP,
4900 MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_ENCAP_RX_MATCHES :
4901 MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES);
4902 rc = efx_mcdi_rpc(efx, MC_CMD_GET_PARSER_DISP_INFO,
4903 inbuf, sizeof(inbuf), outbuf, sizeof(outbuf),
4908 pd_match_count = MCDI_VAR_ARRAY_LEN(
4909 outlen, GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES);
4911 for (pd_match_pri = 0; pd_match_pri < pd_match_count; pd_match_pri++) {
4915 GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES,
4917 rc = efx_ef10_filter_match_flags_from_mcdi(encap, mcdi_flags);
4919 netif_dbg(efx, probe, efx->net_dev,
4920 "%s: fw flags %#x pri %u not supported in driver\n",
4921 __func__, mcdi_flags, pd_match_pri);
4923 netif_dbg(efx, probe, efx->net_dev,
4924 "%s: fw flags %#x pri %u supported as driver flags %#x pri %u\n",
4925 __func__, mcdi_flags, pd_match_pri,
4926 rc, table->rx_match_count);
4927 table->rx_match_mcdi_flags[table->rx_match_count] = mcdi_flags;
4928 table->rx_match_count++;
4935 static int efx_ef10_filter_table_probe(struct efx_nic *efx)
4937 struct efx_ef10_nic_data *nic_data = efx->nic_data;
4938 struct net_device *net_dev = efx->net_dev;
4939 struct efx_ef10_filter_table *table;
4940 struct efx_ef10_vlan *vlan;
4943 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
4946 if (efx->filter_state) /* already probed */
4949 table = kzalloc(sizeof(*table), GFP_KERNEL);
4953 table->rx_match_count = 0;
4954 rc = efx_ef10_filter_table_probe_matches(efx, table, false);
4957 if (nic_data->datapath_caps &
4958 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN))
4959 rc = efx_ef10_filter_table_probe_matches(efx, table, true);
4962 if ((efx_supported_features(efx) & NETIF_F_HW_VLAN_CTAG_FILTER) &&
4963 !(efx_ef10_filter_match_supported(table, false,
4964 (EFX_FILTER_MATCH_OUTER_VID | EFX_FILTER_MATCH_LOC_MAC)) &&
4965 efx_ef10_filter_match_supported(table, false,
4966 (EFX_FILTER_MATCH_OUTER_VID | EFX_FILTER_MATCH_LOC_MAC_IG)))) {
4967 netif_info(efx, probe, net_dev,
4968 "VLAN filters are not supported in this firmware variant\n");
4969 net_dev->features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
4970 efx->fixed_features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
4971 net_dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
4974 table->entry = vzalloc(HUNT_FILTER_TBL_ROWS * sizeof(*table->entry));
4975 if (!table->entry) {
4980 table->mc_promisc_last = false;
4981 table->vlan_filter =
4982 !!(efx->net_dev->features & NETIF_F_HW_VLAN_CTAG_FILTER);
4983 INIT_LIST_HEAD(&table->vlan_list);
4984 init_rwsem(&table->lock);
4986 efx->filter_state = table;
4988 list_for_each_entry(vlan, &nic_data->vlan_list, list) {
4989 rc = efx_ef10_filter_add_vlan(efx, vlan->vid);
4997 efx_ef10_filter_cleanup_vlans(efx);
4998 efx->filter_state = NULL;
5004 /* Caller must hold efx->filter_sem for read if race against
5005 * efx_ef10_filter_table_remove() is possible
5007 static void efx_ef10_filter_table_restore(struct efx_nic *efx)
5009 struct efx_ef10_filter_table *table = efx->filter_state;
5010 struct efx_ef10_nic_data *nic_data = efx->nic_data;
5011 unsigned int invalid_filters = 0, failed = 0;
5012 struct efx_ef10_filter_vlan *vlan;
5013 struct efx_filter_spec *spec;
5014 struct efx_rss_context *ctx;
5015 unsigned int filter_idx;
5020 WARN_ON(!rwsem_is_locked(&efx->filter_sem));
5022 if (!nic_data->must_restore_filters)
5028 down_write(&table->lock);
5029 mutex_lock(&efx->rss_lock);
5031 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
5032 spec = efx_ef10_filter_entry_spec(table, filter_idx);
5036 mcdi_flags = efx_ef10_filter_mcdi_flags_from_spec(spec);
5038 while (match_pri < table->rx_match_count &&
5039 table->rx_match_mcdi_flags[match_pri] != mcdi_flags)
5041 if (match_pri >= table->rx_match_count) {
5045 if (spec->rss_context)
5046 ctx = efx_find_rss_context_entry(efx, spec->rss_context);
5048 ctx = &efx->rss_context;
5049 if (spec->flags & EFX_FILTER_FLAG_RX_RSS) {
5051 netif_warn(efx, drv, efx->net_dev,
5052 "Warning: unable to restore a filter with nonexistent RSS context %u.\n",
5057 if (ctx->context_id == EFX_EF10_RSS_CONTEXT_INVALID) {
5058 netif_warn(efx, drv, efx->net_dev,
5059 "Warning: unable to restore a filter with RSS context %u as it was not created.\n",
5066 rc = efx_ef10_filter_push(efx, spec,
5067 &table->entry[filter_idx].handle,
5074 list_for_each_entry(vlan, &table->vlan_list, list)
5075 for (i = 0; i < EFX_EF10_NUM_DEFAULT_FILTERS; ++i)
5076 if (vlan->default_filters[i] == filter_idx)
5077 vlan->default_filters[i] =
5078 EFX_EF10_FILTER_ID_INVALID;
5081 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
5085 mutex_unlock(&efx->rss_lock);
5086 up_write(&table->lock);
5088 /* This can happen validly if the MC's capabilities have changed, so
5091 if (invalid_filters)
5092 netif_dbg(efx, drv, efx->net_dev,
5093 "Did not restore %u filters that are now unsupported.\n",
5097 netif_err(efx, hw, efx->net_dev,
5098 "unable to restore %u filters\n", failed);
5100 nic_data->must_restore_filters = false;
5103 static void efx_ef10_filter_table_remove(struct efx_nic *efx)
5105 struct efx_ef10_filter_table *table = efx->filter_state;
5106 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_EXT_IN_LEN);
5107 struct efx_filter_spec *spec;
5108 unsigned int filter_idx;
5111 efx_ef10_filter_cleanup_vlans(efx);
5112 efx->filter_state = NULL;
5113 /* If we were called without locking, then it's not safe to free
5114 * the table as others might be using it. So we just WARN, leak
5115 * the memory, and potentially get an inconsistent filter table
5117 * This should never actually happen.
5119 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
5125 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
5126 spec = efx_ef10_filter_entry_spec(table, filter_idx);
5130 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
5131 efx_ef10_filter_is_exclusive(spec) ?
5132 MC_CMD_FILTER_OP_IN_OP_REMOVE :
5133 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
5134 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
5135 table->entry[filter_idx].handle);
5136 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FILTER_OP, inbuf,
5137 sizeof(inbuf), NULL, 0, NULL);
5139 netif_info(efx, drv, efx->net_dev,
5140 "%s: filter %04x remove failed\n",
5141 __func__, filter_idx);
5145 vfree(table->entry);
5149 static void efx_ef10_filter_mark_one_old(struct efx_nic *efx, uint16_t *id)
5151 struct efx_ef10_filter_table *table = efx->filter_state;
5152 unsigned int filter_idx;
5154 efx_rwsem_assert_write_locked(&table->lock);
5156 if (*id != EFX_EF10_FILTER_ID_INVALID) {
5157 filter_idx = efx_ef10_filter_get_unsafe_id(*id);
5158 if (!table->entry[filter_idx].spec)
5159 netif_dbg(efx, drv, efx->net_dev,
5160 "marked null spec old %04x:%04x\n", *id,
5162 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_AUTO_OLD;
5163 *id = EFX_EF10_FILTER_ID_INVALID;
5167 /* Mark old per-VLAN filters that may need to be removed */
5168 static void _efx_ef10_filter_vlan_mark_old(struct efx_nic *efx,
5169 struct efx_ef10_filter_vlan *vlan)
5171 struct efx_ef10_filter_table *table = efx->filter_state;
5174 for (i = 0; i < table->dev_uc_count; i++)
5175 efx_ef10_filter_mark_one_old(efx, &vlan->uc[i]);
5176 for (i = 0; i < table->dev_mc_count; i++)
5177 efx_ef10_filter_mark_one_old(efx, &vlan->mc[i]);
5178 for (i = 0; i < EFX_EF10_NUM_DEFAULT_FILTERS; i++)
5179 efx_ef10_filter_mark_one_old(efx, &vlan->default_filters[i]);
5182 /* Mark old filters that may need to be removed.
5183 * Caller must hold efx->filter_sem for read if race against
5184 * efx_ef10_filter_table_remove() is possible
5186 static void efx_ef10_filter_mark_old(struct efx_nic *efx)
5188 struct efx_ef10_filter_table *table = efx->filter_state;
5189 struct efx_ef10_filter_vlan *vlan;
5191 down_write(&table->lock);
5192 list_for_each_entry(vlan, &table->vlan_list, list)
5193 _efx_ef10_filter_vlan_mark_old(efx, vlan);
5194 up_write(&table->lock);
5197 static void efx_ef10_filter_uc_addr_list(struct efx_nic *efx)
5199 struct efx_ef10_filter_table *table = efx->filter_state;
5200 struct net_device *net_dev = efx->net_dev;
5201 struct netdev_hw_addr *uc;
5204 table->uc_promisc = !!(net_dev->flags & IFF_PROMISC);
5205 ether_addr_copy(table->dev_uc_list[0].addr, net_dev->dev_addr);
5207 netdev_for_each_uc_addr(uc, net_dev) {
5208 if (i >= EFX_EF10_FILTER_DEV_UC_MAX) {
5209 table->uc_promisc = true;
5212 ether_addr_copy(table->dev_uc_list[i].addr, uc->addr);
5216 table->dev_uc_count = i;
5219 static void efx_ef10_filter_mc_addr_list(struct efx_nic *efx)
5221 struct efx_ef10_filter_table *table = efx->filter_state;
5222 struct net_device *net_dev = efx->net_dev;
5223 struct netdev_hw_addr *mc;
5226 table->mc_overflow = false;
5227 table->mc_promisc = !!(net_dev->flags & (IFF_PROMISC | IFF_ALLMULTI));
5230 netdev_for_each_mc_addr(mc, net_dev) {
5231 if (i >= EFX_EF10_FILTER_DEV_MC_MAX) {
5232 table->mc_promisc = true;
5233 table->mc_overflow = true;
5236 ether_addr_copy(table->dev_mc_list[i].addr, mc->addr);
5240 table->dev_mc_count = i;
5243 static int efx_ef10_filter_insert_addr_list(struct efx_nic *efx,
5244 struct efx_ef10_filter_vlan *vlan,
5245 bool multicast, bool rollback)
5247 struct efx_ef10_filter_table *table = efx->filter_state;
5248 struct efx_ef10_dev_addr *addr_list;
5249 enum efx_filter_flags filter_flags;
5250 struct efx_filter_spec spec;
5258 addr_list = table->dev_mc_list;
5259 addr_count = table->dev_mc_count;
5262 addr_list = table->dev_uc_list;
5263 addr_count = table->dev_uc_count;
5267 filter_flags = efx_rss_enabled(efx) ? EFX_FILTER_FLAG_RX_RSS : 0;
5269 /* Insert/renew filters */
5270 for (i = 0; i < addr_count; i++) {
5271 EFX_WARN_ON_PARANOID(ids[i] != EFX_EF10_FILTER_ID_INVALID);
5272 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0);
5273 efx_filter_set_eth_local(&spec, vlan->vid, addr_list[i].addr);
5274 rc = efx_ef10_filter_insert(efx, &spec, true);
5277 netif_info(efx, drv, efx->net_dev,
5278 "efx_ef10_filter_insert failed rc=%d\n",
5280 /* Fall back to promiscuous */
5281 for (j = 0; j < i; j++) {
5282 efx_ef10_filter_remove_unsafe(
5283 efx, EFX_FILTER_PRI_AUTO,
5285 ids[j] = EFX_EF10_FILTER_ID_INVALID;
5289 /* keep invalid ID, and carry on */
5292 ids[i] = efx_ef10_filter_get_unsafe_id(rc);
5296 if (multicast && rollback) {
5297 /* Also need an Ethernet broadcast filter */
5298 EFX_WARN_ON_PARANOID(vlan->default_filters[EFX_EF10_BCAST] !=
5299 EFX_EF10_FILTER_ID_INVALID);
5300 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0);
5301 eth_broadcast_addr(baddr);
5302 efx_filter_set_eth_local(&spec, vlan->vid, baddr);
5303 rc = efx_ef10_filter_insert(efx, &spec, true);
5305 netif_warn(efx, drv, efx->net_dev,
5306 "Broadcast filter insert failed rc=%d\n", rc);
5307 /* Fall back to promiscuous */
5308 for (j = 0; j < i; j++) {
5309 efx_ef10_filter_remove_unsafe(
5310 efx, EFX_FILTER_PRI_AUTO,
5312 ids[j] = EFX_EF10_FILTER_ID_INVALID;
5316 vlan->default_filters[EFX_EF10_BCAST] =
5317 efx_ef10_filter_get_unsafe_id(rc);
5324 static int efx_ef10_filter_insert_def(struct efx_nic *efx,
5325 struct efx_ef10_filter_vlan *vlan,
5326 enum efx_encap_type encap_type,
5327 bool multicast, bool rollback)
5329 struct efx_ef10_nic_data *nic_data = efx->nic_data;
5330 enum efx_filter_flags filter_flags;
5331 struct efx_filter_spec spec;
5336 filter_flags = efx_rss_enabled(efx) ? EFX_FILTER_FLAG_RX_RSS : 0;
5338 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0);
5341 efx_filter_set_mc_def(&spec);
5343 efx_filter_set_uc_def(&spec);
5346 if (nic_data->datapath_caps &
5347 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN))
5348 efx_filter_set_encap_type(&spec, encap_type);
5350 /* don't insert encap filters on non-supporting
5351 * platforms. ID will be left as INVALID.
5356 if (vlan->vid != EFX_FILTER_VID_UNSPEC)
5357 efx_filter_set_eth_local(&spec, vlan->vid, NULL);
5359 rc = efx_ef10_filter_insert(efx, &spec, true);
5361 const char *um = multicast ? "Multicast" : "Unicast";
5362 const char *encap_name = "";
5363 const char *encap_ipv = "";
5365 if ((encap_type & EFX_ENCAP_TYPES_MASK) ==
5366 EFX_ENCAP_TYPE_VXLAN)
5367 encap_name = "VXLAN ";
5368 else if ((encap_type & EFX_ENCAP_TYPES_MASK) ==
5369 EFX_ENCAP_TYPE_NVGRE)
5370 encap_name = "NVGRE ";
5371 else if ((encap_type & EFX_ENCAP_TYPES_MASK) ==
5372 EFX_ENCAP_TYPE_GENEVE)
5373 encap_name = "GENEVE ";
5374 if (encap_type & EFX_ENCAP_FLAG_IPV6)
5375 encap_ipv = "IPv6 ";
5376 else if (encap_type)
5377 encap_ipv = "IPv4 ";
5379 /* unprivileged functions can't insert mismatch filters
5380 * for encapsulated or unicast traffic, so downgrade
5381 * those warnings to debug.
5383 netif_cond_dbg(efx, drv, efx->net_dev,
5384 rc == -EPERM && (encap_type || !multicast), warn,
5385 "%s%s%s mismatch filter insert failed rc=%d\n",
5386 encap_name, encap_ipv, um, rc);
5387 } else if (multicast) {
5388 /* mapping from encap types to default filter IDs (multicast) */
5389 static enum efx_ef10_default_filters map[] = {
5390 [EFX_ENCAP_TYPE_NONE] = EFX_EF10_MCDEF,
5391 [EFX_ENCAP_TYPE_VXLAN] = EFX_EF10_VXLAN4_MCDEF,
5392 [EFX_ENCAP_TYPE_NVGRE] = EFX_EF10_NVGRE4_MCDEF,
5393 [EFX_ENCAP_TYPE_GENEVE] = EFX_EF10_GENEVE4_MCDEF,
5394 [EFX_ENCAP_TYPE_VXLAN | EFX_ENCAP_FLAG_IPV6] =
5395 EFX_EF10_VXLAN6_MCDEF,
5396 [EFX_ENCAP_TYPE_NVGRE | EFX_ENCAP_FLAG_IPV6] =
5397 EFX_EF10_NVGRE6_MCDEF,
5398 [EFX_ENCAP_TYPE_GENEVE | EFX_ENCAP_FLAG_IPV6] =
5399 EFX_EF10_GENEVE6_MCDEF,
5402 /* quick bounds check (BCAST result impossible) */
5403 BUILD_BUG_ON(EFX_EF10_BCAST != 0);
5404 if (encap_type >= ARRAY_SIZE(map) || map[encap_type] == 0) {
5408 /* then follow map */
5409 id = &vlan->default_filters[map[encap_type]];
5411 EFX_WARN_ON_PARANOID(*id != EFX_EF10_FILTER_ID_INVALID);
5412 *id = efx_ef10_filter_get_unsafe_id(rc);
5413 if (!nic_data->workaround_26807 && !encap_type) {
5414 /* Also need an Ethernet broadcast filter */
5415 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
5417 eth_broadcast_addr(baddr);
5418 efx_filter_set_eth_local(&spec, vlan->vid, baddr);
5419 rc = efx_ef10_filter_insert(efx, &spec, true);
5421 netif_warn(efx, drv, efx->net_dev,
5422 "Broadcast filter insert failed rc=%d\n",
5425 /* Roll back the mc_def filter */
5426 efx_ef10_filter_remove_unsafe(
5427 efx, EFX_FILTER_PRI_AUTO,
5429 *id = EFX_EF10_FILTER_ID_INVALID;
5433 EFX_WARN_ON_PARANOID(
5434 vlan->default_filters[EFX_EF10_BCAST] !=
5435 EFX_EF10_FILTER_ID_INVALID);
5436 vlan->default_filters[EFX_EF10_BCAST] =
5437 efx_ef10_filter_get_unsafe_id(rc);
5442 /* mapping from encap types to default filter IDs (unicast) */
5443 static enum efx_ef10_default_filters map[] = {
5444 [EFX_ENCAP_TYPE_NONE] = EFX_EF10_UCDEF,
5445 [EFX_ENCAP_TYPE_VXLAN] = EFX_EF10_VXLAN4_UCDEF,
5446 [EFX_ENCAP_TYPE_NVGRE] = EFX_EF10_NVGRE4_UCDEF,
5447 [EFX_ENCAP_TYPE_GENEVE] = EFX_EF10_GENEVE4_UCDEF,
5448 [EFX_ENCAP_TYPE_VXLAN | EFX_ENCAP_FLAG_IPV6] =
5449 EFX_EF10_VXLAN6_UCDEF,
5450 [EFX_ENCAP_TYPE_NVGRE | EFX_ENCAP_FLAG_IPV6] =
5451 EFX_EF10_NVGRE6_UCDEF,
5452 [EFX_ENCAP_TYPE_GENEVE | EFX_ENCAP_FLAG_IPV6] =
5453 EFX_EF10_GENEVE6_UCDEF,
5456 /* quick bounds check (BCAST result impossible) */
5457 BUILD_BUG_ON(EFX_EF10_BCAST != 0);
5458 if (encap_type >= ARRAY_SIZE(map) || map[encap_type] == 0) {
5462 /* then follow map */
5463 id = &vlan->default_filters[map[encap_type]];
5464 EFX_WARN_ON_PARANOID(*id != EFX_EF10_FILTER_ID_INVALID);
5471 /* Remove filters that weren't renewed. */
5472 static void efx_ef10_filter_remove_old(struct efx_nic *efx)
5474 struct efx_ef10_filter_table *table = efx->filter_state;
5475 int remove_failed = 0;
5476 int remove_noent = 0;
5480 down_write(&table->lock);
5481 for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
5482 if (READ_ONCE(table->entry[i].spec) &
5483 EFX_EF10_FILTER_FLAG_AUTO_OLD) {
5484 rc = efx_ef10_filter_remove_internal(efx,
5485 1U << EFX_FILTER_PRI_AUTO, i, true);
5492 up_write(&table->lock);
5495 netif_info(efx, drv, efx->net_dev,
5496 "%s: failed to remove %d filters\n",
5497 __func__, remove_failed);
5499 netif_info(efx, drv, efx->net_dev,
5500 "%s: failed to remove %d non-existent filters\n",
5501 __func__, remove_noent);
5504 static int efx_ef10_vport_set_mac_address(struct efx_nic *efx)
5506 struct efx_ef10_nic_data *nic_data = efx->nic_data;
5507 u8 mac_old[ETH_ALEN];
5510 /* Only reconfigure a PF-created vport */
5511 if (is_zero_ether_addr(nic_data->vport_mac))
5514 efx_device_detach_sync(efx);
5515 efx_net_stop(efx->net_dev);
5516 down_write(&efx->filter_sem);
5517 efx_ef10_filter_table_remove(efx);
5518 up_write(&efx->filter_sem);
5520 rc = efx_ef10_vadaptor_free(efx, nic_data->vport_id);
5522 goto restore_filters;
5524 ether_addr_copy(mac_old, nic_data->vport_mac);
5525 rc = efx_ef10_vport_del_mac(efx, nic_data->vport_id,
5526 nic_data->vport_mac);
5528 goto restore_vadaptor;
5530 rc = efx_ef10_vport_add_mac(efx, nic_data->vport_id,
5531 efx->net_dev->dev_addr);
5533 ether_addr_copy(nic_data->vport_mac, efx->net_dev->dev_addr);
5535 rc2 = efx_ef10_vport_add_mac(efx, nic_data->vport_id, mac_old);
5537 /* Failed to add original MAC, so clear vport_mac */
5538 eth_zero_addr(nic_data->vport_mac);
5544 rc2 = efx_ef10_vadaptor_alloc(efx, nic_data->vport_id);
5548 down_write(&efx->filter_sem);
5549 rc2 = efx_ef10_filter_table_probe(efx);
5550 up_write(&efx->filter_sem);
5554 rc2 = efx_net_open(efx->net_dev);
5558 efx_device_attach_if_not_resetting(efx);
5563 netif_err(efx, drv, efx->net_dev,
5564 "Failed to restore when changing MAC address - scheduling reset\n");
5565 efx_schedule_reset(efx, RESET_TYPE_DATAPATH);
5567 return rc ? rc : rc2;
5570 /* Caller must hold efx->filter_sem for read if race against
5571 * efx_ef10_filter_table_remove() is possible
5573 static void efx_ef10_filter_vlan_sync_rx_mode(struct efx_nic *efx,
5574 struct efx_ef10_filter_vlan *vlan)
5576 struct efx_ef10_filter_table *table = efx->filter_state;
5577 struct efx_ef10_nic_data *nic_data = efx->nic_data;
5579 /* Do not install unspecified VID if VLAN filtering is enabled.
5580 * Do not install all specified VIDs if VLAN filtering is disabled.
5582 if ((vlan->vid == EFX_FILTER_VID_UNSPEC) == table->vlan_filter)
5585 /* Insert/renew unicast filters */
5586 if (table->uc_promisc) {
5587 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_NONE,
5589 efx_ef10_filter_insert_addr_list(efx, vlan, false, false);
5591 /* If any of the filters failed to insert, fall back to
5592 * promiscuous mode - add in the uc_def filter. But keep
5593 * our individual unicast filters.
5595 if (efx_ef10_filter_insert_addr_list(efx, vlan, false, false))
5596 efx_ef10_filter_insert_def(efx, vlan,
5597 EFX_ENCAP_TYPE_NONE,
5600 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_VXLAN,
5602 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_VXLAN |
5603 EFX_ENCAP_FLAG_IPV6,
5605 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_NVGRE,
5607 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_NVGRE |
5608 EFX_ENCAP_FLAG_IPV6,
5610 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_GENEVE,
5612 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_GENEVE |
5613 EFX_ENCAP_FLAG_IPV6,
5616 /* Insert/renew multicast filters */
5617 /* If changing promiscuous state with cascaded multicast filters, remove
5618 * old filters first, so that packets are dropped rather than duplicated
5620 if (nic_data->workaround_26807 &&
5621 table->mc_promisc_last != table->mc_promisc)
5622 efx_ef10_filter_remove_old(efx);
5623 if (table->mc_promisc) {
5624 if (nic_data->workaround_26807) {
5625 /* If we failed to insert promiscuous filters, rollback
5626 * and fall back to individual multicast filters
5628 if (efx_ef10_filter_insert_def(efx, vlan,
5629 EFX_ENCAP_TYPE_NONE,
5631 /* Changing promisc state, so remove old filters */
5632 efx_ef10_filter_remove_old(efx);
5633 efx_ef10_filter_insert_addr_list(efx, vlan,
5637 /* If we failed to insert promiscuous filters, don't
5638 * rollback. Regardless, also insert the mc_list,
5639 * unless it's incomplete due to overflow
5641 efx_ef10_filter_insert_def(efx, vlan,
5642 EFX_ENCAP_TYPE_NONE,
5644 if (!table->mc_overflow)
5645 efx_ef10_filter_insert_addr_list(efx, vlan,
5649 /* If any filters failed to insert, rollback and fall back to
5650 * promiscuous mode - mc_def filter and maybe broadcast. If
5651 * that fails, roll back again and insert as many of our
5652 * individual multicast filters as we can.
5654 if (efx_ef10_filter_insert_addr_list(efx, vlan, true, true)) {
5655 /* Changing promisc state, so remove old filters */
5656 if (nic_data->workaround_26807)
5657 efx_ef10_filter_remove_old(efx);
5658 if (efx_ef10_filter_insert_def(efx, vlan,
5659 EFX_ENCAP_TYPE_NONE,
5661 efx_ef10_filter_insert_addr_list(efx, vlan,
5665 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_VXLAN,
5667 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_VXLAN |
5668 EFX_ENCAP_FLAG_IPV6,
5670 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_NVGRE,
5672 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_NVGRE |
5673 EFX_ENCAP_FLAG_IPV6,
5675 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_GENEVE,
5677 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_GENEVE |
5678 EFX_ENCAP_FLAG_IPV6,
5682 /* Caller must hold efx->filter_sem for read if race against
5683 * efx_ef10_filter_table_remove() is possible
5685 static void efx_ef10_filter_sync_rx_mode(struct efx_nic *efx)
5687 struct efx_ef10_filter_table *table = efx->filter_state;
5688 struct net_device *net_dev = efx->net_dev;
5689 struct efx_ef10_filter_vlan *vlan;
5692 if (!efx_dev_registered(efx))
5698 efx_ef10_filter_mark_old(efx);
5700 /* Copy/convert the address lists; add the primary station
5701 * address and broadcast address
5703 netif_addr_lock_bh(net_dev);
5704 efx_ef10_filter_uc_addr_list(efx);
5705 efx_ef10_filter_mc_addr_list(efx);
5706 netif_addr_unlock_bh(net_dev);
5708 /* If VLAN filtering changes, all old filters are finally removed.
5709 * Do it in advance to avoid conflicts for unicast untagged and
5710 * VLAN 0 tagged filters.
5712 vlan_filter = !!(net_dev->features & NETIF_F_HW_VLAN_CTAG_FILTER);
5713 if (table->vlan_filter != vlan_filter) {
5714 table->vlan_filter = vlan_filter;
5715 efx_ef10_filter_remove_old(efx);
5718 list_for_each_entry(vlan, &table->vlan_list, list)
5719 efx_ef10_filter_vlan_sync_rx_mode(efx, vlan);
5721 efx_ef10_filter_remove_old(efx);
5722 table->mc_promisc_last = table->mc_promisc;
5725 static struct efx_ef10_filter_vlan *efx_ef10_filter_find_vlan(struct efx_nic *efx, u16 vid)
5727 struct efx_ef10_filter_table *table = efx->filter_state;
5728 struct efx_ef10_filter_vlan *vlan;
5730 WARN_ON(!rwsem_is_locked(&efx->filter_sem));
5732 list_for_each_entry(vlan, &table->vlan_list, list) {
5733 if (vlan->vid == vid)
5740 static int efx_ef10_filter_add_vlan(struct efx_nic *efx, u16 vid)
5742 struct efx_ef10_filter_table *table = efx->filter_state;
5743 struct efx_ef10_filter_vlan *vlan;
5746 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
5749 vlan = efx_ef10_filter_find_vlan(efx, vid);
5750 if (WARN_ON(vlan)) {
5751 netif_err(efx, drv, efx->net_dev,
5752 "VLAN %u already added\n", vid);
5756 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL);
5762 for (i = 0; i < ARRAY_SIZE(vlan->uc); i++)
5763 vlan->uc[i] = EFX_EF10_FILTER_ID_INVALID;
5764 for (i = 0; i < ARRAY_SIZE(vlan->mc); i++)
5765 vlan->mc[i] = EFX_EF10_FILTER_ID_INVALID;
5766 for (i = 0; i < EFX_EF10_NUM_DEFAULT_FILTERS; i++)
5767 vlan->default_filters[i] = EFX_EF10_FILTER_ID_INVALID;
5769 list_add_tail(&vlan->list, &table->vlan_list);
5771 if (efx_dev_registered(efx))
5772 efx_ef10_filter_vlan_sync_rx_mode(efx, vlan);
5777 static void efx_ef10_filter_del_vlan_internal(struct efx_nic *efx,
5778 struct efx_ef10_filter_vlan *vlan)
5782 /* See comment in efx_ef10_filter_table_remove() */
5783 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
5786 list_del(&vlan->list);
5788 for (i = 0; i < ARRAY_SIZE(vlan->uc); i++)
5789 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO,
5791 for (i = 0; i < ARRAY_SIZE(vlan->mc); i++)
5792 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO,
5794 for (i = 0; i < EFX_EF10_NUM_DEFAULT_FILTERS; i++)
5795 if (vlan->default_filters[i] != EFX_EF10_FILTER_ID_INVALID)
5796 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO,
5797 vlan->default_filters[i]);
5802 static void efx_ef10_filter_del_vlan(struct efx_nic *efx, u16 vid)
5804 struct efx_ef10_filter_vlan *vlan;
5806 /* See comment in efx_ef10_filter_table_remove() */
5807 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
5810 vlan = efx_ef10_filter_find_vlan(efx, vid);
5812 netif_err(efx, drv, efx->net_dev,
5813 "VLAN %u not found in filter state\n", vid);
5817 efx_ef10_filter_del_vlan_internal(efx, vlan);
5820 static int efx_ef10_set_mac_address(struct efx_nic *efx)
5822 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_SET_MAC_IN_LEN);
5823 struct efx_ef10_nic_data *nic_data = efx->nic_data;
5824 bool was_enabled = efx->port_enabled;
5827 efx_device_detach_sync(efx);
5828 efx_net_stop(efx->net_dev);
5830 mutex_lock(&efx->mac_lock);
5831 down_write(&efx->filter_sem);
5832 efx_ef10_filter_table_remove(efx);
5834 ether_addr_copy(MCDI_PTR(inbuf, VADAPTOR_SET_MAC_IN_MACADDR),
5835 efx->net_dev->dev_addr);
5836 MCDI_SET_DWORD(inbuf, VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID,
5837 nic_data->vport_id);
5838 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_VADAPTOR_SET_MAC, inbuf,
5839 sizeof(inbuf), NULL, 0, NULL);
5841 efx_ef10_filter_table_probe(efx);
5842 up_write(&efx->filter_sem);
5843 mutex_unlock(&efx->mac_lock);
5846 efx_net_open(efx->net_dev);
5847 efx_device_attach_if_not_resetting(efx);
5849 #ifdef CONFIG_SFC_SRIOV
5850 if (efx->pci_dev->is_virtfn && efx->pci_dev->physfn) {
5851 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn;
5854 struct efx_nic *efx_pf;
5856 /* Switch to PF and change MAC address on vport */
5857 efx_pf = pci_get_drvdata(pci_dev_pf);
5859 rc = efx_ef10_sriov_set_vf_mac(efx_pf,
5861 efx->net_dev->dev_addr);
5863 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
5864 struct efx_ef10_nic_data *nic_data = efx_pf->nic_data;
5867 /* MAC address successfully changed by VF (with MAC
5868 * spoofing) so update the parent PF if possible.
5870 for (i = 0; i < efx_pf->vf_count; ++i) {
5871 struct ef10_vf *vf = nic_data->vf + i;
5873 if (vf->efx == efx) {
5874 ether_addr_copy(vf->mac,
5875 efx->net_dev->dev_addr);
5883 netif_err(efx, drv, efx->net_dev,
5884 "Cannot change MAC address; use sfboot to enable"
5885 " mac-spoofing on this interface\n");
5886 } else if (rc == -ENOSYS && !efx_ef10_is_vf(efx)) {
5887 /* If the active MCFW does not support MC_CMD_VADAPTOR_SET_MAC
5888 * fall-back to the method of changing the MAC address on the
5889 * vport. This only applies to PFs because such versions of
5890 * MCFW do not support VFs.
5892 rc = efx_ef10_vport_set_mac_address(efx);
5894 efx_mcdi_display_error(efx, MC_CMD_VADAPTOR_SET_MAC,
5895 sizeof(inbuf), NULL, 0, rc);
5901 static int efx_ef10_mac_reconfigure(struct efx_nic *efx)
5903 efx_ef10_filter_sync_rx_mode(efx);
5905 return efx_mcdi_set_mac(efx);
5908 static int efx_ef10_mac_reconfigure_vf(struct efx_nic *efx)
5910 efx_ef10_filter_sync_rx_mode(efx);
5915 static int efx_ef10_start_bist(struct efx_nic *efx, u32 bist_type)
5917 MCDI_DECLARE_BUF(inbuf, MC_CMD_START_BIST_IN_LEN);
5919 MCDI_SET_DWORD(inbuf, START_BIST_IN_TYPE, bist_type);
5920 return efx_mcdi_rpc(efx, MC_CMD_START_BIST, inbuf, sizeof(inbuf),
5924 /* MC BISTs follow a different poll mechanism to phy BISTs.
5925 * The BIST is done in the poll handler on the MC, and the MCDI command
5926 * will block until the BIST is done.
5928 static int efx_ef10_poll_bist(struct efx_nic *efx)
5931 MCDI_DECLARE_BUF(outbuf, MC_CMD_POLL_BIST_OUT_LEN);
5935 rc = efx_mcdi_rpc(efx, MC_CMD_POLL_BIST, NULL, 0,
5936 outbuf, sizeof(outbuf), &outlen);
5940 if (outlen < MC_CMD_POLL_BIST_OUT_LEN)
5943 result = MCDI_DWORD(outbuf, POLL_BIST_OUT_RESULT);
5945 case MC_CMD_POLL_BIST_PASSED:
5946 netif_dbg(efx, hw, efx->net_dev, "BIST passed.\n");
5948 case MC_CMD_POLL_BIST_TIMEOUT:
5949 netif_err(efx, hw, efx->net_dev, "BIST timed out\n");
5951 case MC_CMD_POLL_BIST_FAILED:
5952 netif_err(efx, hw, efx->net_dev, "BIST failed.\n");
5955 netif_err(efx, hw, efx->net_dev,
5956 "BIST returned unknown result %u", result);
5961 static int efx_ef10_run_bist(struct efx_nic *efx, u32 bist_type)
5965 netif_dbg(efx, drv, efx->net_dev, "starting BIST type %u\n", bist_type);
5967 rc = efx_ef10_start_bist(efx, bist_type);
5971 return efx_ef10_poll_bist(efx);
5975 efx_ef10_test_chip(struct efx_nic *efx, struct efx_self_tests *tests)
5979 efx_reset_down(efx, RESET_TYPE_WORLD);
5981 rc = efx_mcdi_rpc(efx, MC_CMD_ENABLE_OFFLINE_BIST,
5982 NULL, 0, NULL, 0, NULL);
5986 tests->memory = efx_ef10_run_bist(efx, MC_CMD_MC_MEM_BIST) ? -1 : 1;
5987 tests->registers = efx_ef10_run_bist(efx, MC_CMD_REG_BIST) ? -1 : 1;
5989 rc = efx_mcdi_reset(efx, RESET_TYPE_WORLD);
5994 rc2 = efx_reset_up(efx, RESET_TYPE_WORLD, rc == 0);
5995 return rc ? rc : rc2;
5998 #ifdef CONFIG_SFC_MTD
6000 struct efx_ef10_nvram_type_info {
6001 u16 type, type_mask;
6006 static const struct efx_ef10_nvram_type_info efx_ef10_nvram_types[] = {
6007 { NVRAM_PARTITION_TYPE_MC_FIRMWARE, 0, 0, "sfc_mcfw" },
6008 { NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 0, 0, "sfc_mcfw_backup" },
6009 { NVRAM_PARTITION_TYPE_EXPANSION_ROM, 0, 0, "sfc_exp_rom" },
6010 { NVRAM_PARTITION_TYPE_STATIC_CONFIG, 0, 0, "sfc_static_cfg" },
6011 { NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 0, 0, "sfc_dynamic_cfg" },
6012 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 0, 0, "sfc_exp_rom_cfg" },
6013 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1, 0, 1, "sfc_exp_rom_cfg" },
6014 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2, 0, 2, "sfc_exp_rom_cfg" },
6015 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3, 0, 3, "sfc_exp_rom_cfg" },
6016 { NVRAM_PARTITION_TYPE_LICENSE, 0, 0, "sfc_license" },
6017 { NVRAM_PARTITION_TYPE_PHY_MIN, 0xff, 0, "sfc_phy_fw" },
6020 static int efx_ef10_mtd_probe_partition(struct efx_nic *efx,
6021 struct efx_mcdi_mtd_partition *part,
6024 MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_METADATA_IN_LEN);
6025 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_METADATA_OUT_LENMAX);
6026 const struct efx_ef10_nvram_type_info *info;
6027 size_t size, erase_size, outlen;
6031 for (info = efx_ef10_nvram_types; ; info++) {
6033 efx_ef10_nvram_types + ARRAY_SIZE(efx_ef10_nvram_types))
6035 if ((type & ~info->type_mask) == info->type)
6038 if (info->port != efx_port_num(efx))
6041 rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected);
6045 return -ENODEV; /* hide it */
6047 part->nvram_type = type;
6049 MCDI_SET_DWORD(inbuf, NVRAM_METADATA_IN_TYPE, type);
6050 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_METADATA, inbuf, sizeof(inbuf),
6051 outbuf, sizeof(outbuf), &outlen);
6054 if (outlen < MC_CMD_NVRAM_METADATA_OUT_LENMIN)
6056 if (MCDI_DWORD(outbuf, NVRAM_METADATA_OUT_FLAGS) &
6057 (1 << MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN))
6058 part->fw_subtype = MCDI_DWORD(outbuf,
6059 NVRAM_METADATA_OUT_SUBTYPE);
6061 part->common.dev_type_name = "EF10 NVRAM manager";
6062 part->common.type_name = info->name;
6064 part->common.mtd.type = MTD_NORFLASH;
6065 part->common.mtd.flags = MTD_CAP_NORFLASH;
6066 part->common.mtd.size = size;
6067 part->common.mtd.erasesize = erase_size;
6072 static int efx_ef10_mtd_probe(struct efx_nic *efx)
6074 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX);
6075 struct efx_mcdi_mtd_partition *parts;
6076 size_t outlen, n_parts_total, i, n_parts;
6082 BUILD_BUG_ON(MC_CMD_NVRAM_PARTITIONS_IN_LEN != 0);
6083 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_PARTITIONS, NULL, 0,
6084 outbuf, sizeof(outbuf), &outlen);
6087 if (outlen < MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN)
6090 n_parts_total = MCDI_DWORD(outbuf, NVRAM_PARTITIONS_OUT_NUM_PARTITIONS);
6092 MCDI_VAR_ARRAY_LEN(outlen, NVRAM_PARTITIONS_OUT_TYPE_ID))
6095 parts = kcalloc(n_parts_total, sizeof(*parts), GFP_KERNEL);
6100 for (i = 0; i < n_parts_total; i++) {
6101 type = MCDI_ARRAY_DWORD(outbuf, NVRAM_PARTITIONS_OUT_TYPE_ID,
6103 rc = efx_ef10_mtd_probe_partition(efx, &parts[n_parts], type);
6106 else if (rc != -ENODEV)
6110 rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts));
6117 #endif /* CONFIG_SFC_MTD */
6119 static void efx_ef10_ptp_write_host_time(struct efx_nic *efx, u32 host_time)
6121 _efx_writed(efx, cpu_to_le32(host_time), ER_DZ_MC_DB_LWRD);
6124 static void efx_ef10_ptp_write_host_time_vf(struct efx_nic *efx,
6127 static int efx_ef10_rx_enable_timestamping(struct efx_channel *channel,
6130 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN);
6133 if (channel->sync_events_state == SYNC_EVENTS_REQUESTED ||
6134 channel->sync_events_state == SYNC_EVENTS_VALID ||
6135 (temp && channel->sync_events_state == SYNC_EVENTS_DISABLED))
6137 channel->sync_events_state = SYNC_EVENTS_REQUESTED;
6139 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE);
6140 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
6141 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE,
6144 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
6145 inbuf, sizeof(inbuf), NULL, 0, NULL);
6148 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
6149 SYNC_EVENTS_DISABLED;
6154 static int efx_ef10_rx_disable_timestamping(struct efx_channel *channel,
6157 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN);
6160 if (channel->sync_events_state == SYNC_EVENTS_DISABLED ||
6161 (temp && channel->sync_events_state == SYNC_EVENTS_QUIESCENT))
6163 if (channel->sync_events_state == SYNC_EVENTS_QUIESCENT) {
6164 channel->sync_events_state = SYNC_EVENTS_DISABLED;
6167 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
6168 SYNC_EVENTS_DISABLED;
6170 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE);
6171 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
6172 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL,
6173 MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE);
6174 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE,
6177 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
6178 inbuf, sizeof(inbuf), NULL, 0, NULL);
6183 static int efx_ef10_ptp_set_ts_sync_events(struct efx_nic *efx, bool en,
6186 int (*set)(struct efx_channel *channel, bool temp);
6187 struct efx_channel *channel;
6190 efx_ef10_rx_enable_timestamping :
6191 efx_ef10_rx_disable_timestamping;
6193 channel = efx_ptp_channel(efx);
6195 int rc = set(channel, temp);
6196 if (en && rc != 0) {
6197 efx_ef10_ptp_set_ts_sync_events(efx, false, temp);
6205 static int efx_ef10_ptp_set_ts_config_vf(struct efx_nic *efx,
6206 struct hwtstamp_config *init)
6211 static int efx_ef10_ptp_set_ts_config(struct efx_nic *efx,
6212 struct hwtstamp_config *init)
6216 switch (init->rx_filter) {
6217 case HWTSTAMP_FILTER_NONE:
6218 efx_ef10_ptp_set_ts_sync_events(efx, false, false);
6219 /* if TX timestamping is still requested then leave PTP on */
6220 return efx_ptp_change_mode(efx,
6221 init->tx_type != HWTSTAMP_TX_OFF, 0);
6222 case HWTSTAMP_FILTER_ALL:
6223 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
6224 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
6225 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
6226 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
6227 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
6228 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
6229 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
6230 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
6231 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
6232 case HWTSTAMP_FILTER_PTP_V2_EVENT:
6233 case HWTSTAMP_FILTER_PTP_V2_SYNC:
6234 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
6235 case HWTSTAMP_FILTER_NTP_ALL:
6236 init->rx_filter = HWTSTAMP_FILTER_ALL;
6237 rc = efx_ptp_change_mode(efx, true, 0);
6239 rc = efx_ef10_ptp_set_ts_sync_events(efx, true, false);
6241 efx_ptp_change_mode(efx, false, 0);
6248 static int efx_ef10_get_phys_port_id(struct efx_nic *efx,
6249 struct netdev_phys_item_id *ppid)
6251 struct efx_ef10_nic_data *nic_data = efx->nic_data;
6253 if (!is_valid_ether_addr(nic_data->port_id))
6256 ppid->id_len = ETH_ALEN;
6257 memcpy(ppid->id, nic_data->port_id, ppid->id_len);
6262 static int efx_ef10_vlan_rx_add_vid(struct efx_nic *efx, __be16 proto, u16 vid)
6264 if (proto != htons(ETH_P_8021Q))
6267 return efx_ef10_add_vlan(efx, vid);
6270 static int efx_ef10_vlan_rx_kill_vid(struct efx_nic *efx, __be16 proto, u16 vid)
6272 if (proto != htons(ETH_P_8021Q))
6275 return efx_ef10_del_vlan(efx, vid);
6278 /* We rely on the MCDI wiping out our TX rings if it made any changes to the
6279 * ports table, ensuring that any TSO descriptors that were made on a now-
6280 * removed tunnel port will be blown away and won't break things when we try
6281 * to transmit them using the new ports table.
6283 static int efx_ef10_set_udp_tnl_ports(struct efx_nic *efx, bool unloading)
6285 struct efx_ef10_nic_data *nic_data = efx->nic_data;
6286 MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LENMAX);
6287 MCDI_DECLARE_BUF(outbuf, MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_LEN);
6288 bool will_reset = false;
6289 size_t num_entries = 0;
6290 size_t inlen, outlen;
6293 efx_dword_t flags_and_num_entries;
6295 WARN_ON(!mutex_is_locked(&nic_data->udp_tunnels_lock));
6297 nic_data->udp_tunnels_dirty = false;
6299 if (!(nic_data->datapath_caps &
6300 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN))) {
6301 efx_device_attach_if_not_resetting(efx);
6305 BUILD_BUG_ON(ARRAY_SIZE(nic_data->udp_tunnels) >
6306 MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MAXNUM);
6308 for (i = 0; i < ARRAY_SIZE(nic_data->udp_tunnels); ++i) {
6309 if (nic_data->udp_tunnels[i].count &&
6310 nic_data->udp_tunnels[i].port) {
6313 EFX_POPULATE_DWORD_2(entry,
6314 TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT,
6315 ntohs(nic_data->udp_tunnels[i].port),
6316 TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL,
6317 nic_data->udp_tunnels[i].type);
6318 *_MCDI_ARRAY_DWORD(inbuf,
6319 SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES,
6320 num_entries++) = entry;
6324 BUILD_BUG_ON((MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_OFST -
6325 MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS_OFST) * 8 !=
6327 BUILD_BUG_ON(MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_LEN * 8 !=
6329 EFX_POPULATE_DWORD_2(flags_and_num_entries,
6330 MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING,
6332 EFX_WORD_1, num_entries);
6333 *_MCDI_DWORD(inbuf, SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS) =
6334 flags_and_num_entries;
6336 inlen = MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LEN(num_entries);
6338 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS,
6339 inbuf, inlen, outbuf, sizeof(outbuf), &outlen);
6341 /* Most likely the MC rebooted due to another function also
6342 * setting its tunnel port list. Mark the tunnel port list as
6343 * dirty, so it will be pushed upon coming up from the reboot.
6345 nic_data->udp_tunnels_dirty = true;
6350 /* expected not available on unprivileged functions */
6352 netif_warn(efx, drv, efx->net_dev,
6353 "Unable to set UDP tunnel ports; rc=%d.\n", rc);
6354 } else if (MCDI_DWORD(outbuf, SET_TUNNEL_ENCAP_UDP_PORTS_OUT_FLAGS) &
6355 (1 << MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_LBN)) {
6356 netif_info(efx, drv, efx->net_dev,
6357 "Rebooting MC due to UDP tunnel port list change\n");
6360 /* Delay for the MC reset to complete. This will make
6361 * unloading other functions a bit smoother. This is a
6362 * race, but the other unload will work whichever way
6363 * it goes, this just avoids an unnecessary error
6368 if (!will_reset && !unloading) {
6369 /* The caller will have detached, relying on the MC reset to
6370 * trigger a re-attach. Since there won't be an MC reset, we
6371 * have to do the attach ourselves.
6373 efx_device_attach_if_not_resetting(efx);
6379 static int efx_ef10_udp_tnl_push_ports(struct efx_nic *efx)
6381 struct efx_ef10_nic_data *nic_data = efx->nic_data;
6384 mutex_lock(&nic_data->udp_tunnels_lock);
6385 if (nic_data->udp_tunnels_dirty) {
6386 /* Make sure all TX are stopped while we modify the table, else
6387 * we might race against an efx_features_check().
6389 efx_device_detach_sync(efx);
6390 rc = efx_ef10_set_udp_tnl_ports(efx, false);
6392 mutex_unlock(&nic_data->udp_tunnels_lock);
6396 static struct efx_udp_tunnel *__efx_ef10_udp_tnl_lookup_port(struct efx_nic *efx,
6399 struct efx_ef10_nic_data *nic_data = efx->nic_data;
6402 for (i = 0; i < ARRAY_SIZE(nic_data->udp_tunnels); ++i) {
6403 if (!nic_data->udp_tunnels[i].count)
6405 if (nic_data->udp_tunnels[i].port == port)
6406 return &nic_data->udp_tunnels[i];
6411 static int efx_ef10_udp_tnl_add_port(struct efx_nic *efx,
6412 struct efx_udp_tunnel tnl)
6414 struct efx_ef10_nic_data *nic_data = efx->nic_data;
6415 struct efx_udp_tunnel *match;
6420 if (!(nic_data->datapath_caps &
6421 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN)))
6424 efx_get_udp_tunnel_type_name(tnl.type, typebuf, sizeof(typebuf));
6425 netif_dbg(efx, drv, efx->net_dev, "Adding UDP tunnel (%s) port %d\n",
6426 typebuf, ntohs(tnl.port));
6428 mutex_lock(&nic_data->udp_tunnels_lock);
6429 /* Make sure all TX are stopped while we add to the table, else we
6430 * might race against an efx_features_check().
6432 efx_device_detach_sync(efx);
6434 match = __efx_ef10_udp_tnl_lookup_port(efx, tnl.port);
6435 if (match != NULL) {
6436 if (match->type == tnl.type) {
6437 netif_dbg(efx, drv, efx->net_dev,
6438 "Referencing existing tunnel entry\n");
6440 /* No need to cause an MCDI update */
6444 efx_get_udp_tunnel_type_name(match->type,
6445 typebuf, sizeof(typebuf));
6446 netif_dbg(efx, drv, efx->net_dev,
6447 "UDP port %d is already in use by %s\n",
6448 ntohs(tnl.port), typebuf);
6453 for (i = 0; i < ARRAY_SIZE(nic_data->udp_tunnels); ++i)
6454 if (!nic_data->udp_tunnels[i].count) {
6455 nic_data->udp_tunnels[i] = tnl;
6456 nic_data->udp_tunnels[i].count = 1;
6457 rc = efx_ef10_set_udp_tnl_ports(efx, false);
6461 netif_dbg(efx, drv, efx->net_dev,
6462 "Unable to add UDP tunnel (%s) port %d; insufficient resources.\n",
6463 typebuf, ntohs(tnl.port));
6468 mutex_unlock(&nic_data->udp_tunnels_lock);
6472 /* Called under the TX lock with the TX queue running, hence no-one can be
6473 * in the middle of updating the UDP tunnels table. However, they could
6474 * have tried and failed the MCDI, in which case they'll have set the dirty
6475 * flag before dropping their locks.
6477 static bool efx_ef10_udp_tnl_has_port(struct efx_nic *efx, __be16 port)
6479 struct efx_ef10_nic_data *nic_data = efx->nic_data;
6481 if (!(nic_data->datapath_caps &
6482 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN)))
6485 if (nic_data->udp_tunnels_dirty)
6486 /* SW table may not match HW state, so just assume we can't
6487 * use any UDP tunnel offloads.
6491 return __efx_ef10_udp_tnl_lookup_port(efx, port) != NULL;
6494 static int efx_ef10_udp_tnl_del_port(struct efx_nic *efx,
6495 struct efx_udp_tunnel tnl)
6497 struct efx_ef10_nic_data *nic_data = efx->nic_data;
6498 struct efx_udp_tunnel *match;
6502 if (!(nic_data->datapath_caps &
6503 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN)))
6506 efx_get_udp_tunnel_type_name(tnl.type, typebuf, sizeof(typebuf));
6507 netif_dbg(efx, drv, efx->net_dev, "Removing UDP tunnel (%s) port %d\n",
6508 typebuf, ntohs(tnl.port));
6510 mutex_lock(&nic_data->udp_tunnels_lock);
6511 /* Make sure all TX are stopped while we remove from the table, else we
6512 * might race against an efx_features_check().
6514 efx_device_detach_sync(efx);
6516 match = __efx_ef10_udp_tnl_lookup_port(efx, tnl.port);
6517 if (match != NULL) {
6518 if (match->type == tnl.type) {
6519 if (--match->count) {
6520 /* Port is still in use, so nothing to do */
6521 netif_dbg(efx, drv, efx->net_dev,
6522 "UDP tunnel port %d remains active\n",
6527 rc = efx_ef10_set_udp_tnl_ports(efx, false);
6530 efx_get_udp_tunnel_type_name(match->type,
6531 typebuf, sizeof(typebuf));
6532 netif_warn(efx, drv, efx->net_dev,
6533 "UDP port %d is actually in use by %s, not removing\n",
6534 ntohs(tnl.port), typebuf);
6539 mutex_unlock(&nic_data->udp_tunnels_lock);
6543 #define EF10_OFFLOAD_FEATURES \
6544 (NETIF_F_IP_CSUM | \
6545 NETIF_F_HW_VLAN_CTAG_FILTER | \
6546 NETIF_F_IPV6_CSUM | \
6550 const struct efx_nic_type efx_hunt_a0_vf_nic_type = {
6552 .mem_bar = efx_ef10_vf_mem_bar,
6553 .mem_map_size = efx_ef10_mem_map_size,
6554 .probe = efx_ef10_probe_vf,
6555 .remove = efx_ef10_remove,
6556 .dimension_resources = efx_ef10_dimension_resources,
6557 .init = efx_ef10_init_nic,
6558 .fini = efx_port_dummy_op_void,
6559 .map_reset_reason = efx_ef10_map_reset_reason,
6560 .map_reset_flags = efx_ef10_map_reset_flags,
6561 .reset = efx_ef10_reset,
6562 .probe_port = efx_mcdi_port_probe,
6563 .remove_port = efx_mcdi_port_remove,
6564 .fini_dmaq = efx_ef10_fini_dmaq,
6565 .prepare_flr = efx_ef10_prepare_flr,
6566 .finish_flr = efx_port_dummy_op_void,
6567 .describe_stats = efx_ef10_describe_stats,
6568 .update_stats = efx_ef10_update_stats_vf,
6569 .start_stats = efx_port_dummy_op_void,
6570 .pull_stats = efx_port_dummy_op_void,
6571 .stop_stats = efx_port_dummy_op_void,
6572 .set_id_led = efx_mcdi_set_id_led,
6573 .push_irq_moderation = efx_ef10_push_irq_moderation,
6574 .reconfigure_mac = efx_ef10_mac_reconfigure_vf,
6575 .check_mac_fault = efx_mcdi_mac_check_fault,
6576 .reconfigure_port = efx_mcdi_port_reconfigure,
6577 .get_wol = efx_ef10_get_wol_vf,
6578 .set_wol = efx_ef10_set_wol_vf,
6579 .resume_wol = efx_port_dummy_op_void,
6580 .mcdi_request = efx_ef10_mcdi_request,
6581 .mcdi_poll_response = efx_ef10_mcdi_poll_response,
6582 .mcdi_read_response = efx_ef10_mcdi_read_response,
6583 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
6584 .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected,
6585 .irq_enable_master = efx_port_dummy_op_void,
6586 .irq_test_generate = efx_ef10_irq_test_generate,
6587 .irq_disable_non_ev = efx_port_dummy_op_void,
6588 .irq_handle_msi = efx_ef10_msi_interrupt,
6589 .irq_handle_legacy = efx_ef10_legacy_interrupt,
6590 .tx_probe = efx_ef10_tx_probe,
6591 .tx_init = efx_ef10_tx_init,
6592 .tx_remove = efx_ef10_tx_remove,
6593 .tx_write = efx_ef10_tx_write,
6594 .tx_limit_len = efx_ef10_tx_limit_len,
6595 .rx_push_rss_config = efx_ef10_vf_rx_push_rss_config,
6596 .rx_pull_rss_config = efx_ef10_rx_pull_rss_config,
6597 .rx_probe = efx_ef10_rx_probe,
6598 .rx_init = efx_ef10_rx_init,
6599 .rx_remove = efx_ef10_rx_remove,
6600 .rx_write = efx_ef10_rx_write,
6601 .rx_defer_refill = efx_ef10_rx_defer_refill,
6602 .ev_probe = efx_ef10_ev_probe,
6603 .ev_init = efx_ef10_ev_init,
6604 .ev_fini = efx_ef10_ev_fini,
6605 .ev_remove = efx_ef10_ev_remove,
6606 .ev_process = efx_ef10_ev_process,
6607 .ev_read_ack = efx_ef10_ev_read_ack,
6608 .ev_test_generate = efx_ef10_ev_test_generate,
6609 .filter_table_probe = efx_ef10_filter_table_probe,
6610 .filter_table_restore = efx_ef10_filter_table_restore,
6611 .filter_table_remove = efx_ef10_filter_table_remove,
6612 .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
6613 .filter_insert = efx_ef10_filter_insert,
6614 .filter_remove_safe = efx_ef10_filter_remove_safe,
6615 .filter_get_safe = efx_ef10_filter_get_safe,
6616 .filter_clear_rx = efx_ef10_filter_clear_rx,
6617 .filter_count_rx_used = efx_ef10_filter_count_rx_used,
6618 .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
6619 .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
6620 #ifdef CONFIG_RFS_ACCEL
6621 .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
6623 #ifdef CONFIG_SFC_MTD
6624 .mtd_probe = efx_port_dummy_op_int,
6626 .ptp_write_host_time = efx_ef10_ptp_write_host_time_vf,
6627 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config_vf,
6628 .vlan_rx_add_vid = efx_ef10_vlan_rx_add_vid,
6629 .vlan_rx_kill_vid = efx_ef10_vlan_rx_kill_vid,
6630 #ifdef CONFIG_SFC_SRIOV
6631 .vswitching_probe = efx_ef10_vswitching_probe_vf,
6632 .vswitching_restore = efx_ef10_vswitching_restore_vf,
6633 .vswitching_remove = efx_ef10_vswitching_remove_vf,
6635 .get_mac_address = efx_ef10_get_mac_address_vf,
6636 .set_mac_address = efx_ef10_set_mac_address,
6638 .get_phys_port_id = efx_ef10_get_phys_port_id,
6639 .revision = EFX_REV_HUNT_A0,
6640 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
6641 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
6642 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
6643 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
6644 .can_rx_scatter = true,
6645 .always_rx_scatter = true,
6646 .min_interrupt_mode = EFX_INT_MODE_MSIX,
6647 .max_interrupt_mode = EFX_INT_MODE_MSIX,
6648 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
6649 .offload_features = EF10_OFFLOAD_FEATURES,
6651 .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,
6652 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
6653 1 << HWTSTAMP_FILTER_ALL,
6654 .rx_hash_key_size = 40,
6657 const struct efx_nic_type efx_hunt_a0_nic_type = {
6659 .mem_bar = efx_ef10_pf_mem_bar,
6660 .mem_map_size = efx_ef10_mem_map_size,
6661 .probe = efx_ef10_probe_pf,
6662 .remove = efx_ef10_remove,
6663 .dimension_resources = efx_ef10_dimension_resources,
6664 .init = efx_ef10_init_nic,
6665 .fini = efx_port_dummy_op_void,
6666 .map_reset_reason = efx_ef10_map_reset_reason,
6667 .map_reset_flags = efx_ef10_map_reset_flags,
6668 .reset = efx_ef10_reset,
6669 .probe_port = efx_mcdi_port_probe,
6670 .remove_port = efx_mcdi_port_remove,
6671 .fini_dmaq = efx_ef10_fini_dmaq,
6672 .prepare_flr = efx_ef10_prepare_flr,
6673 .finish_flr = efx_port_dummy_op_void,
6674 .describe_stats = efx_ef10_describe_stats,
6675 .update_stats = efx_ef10_update_stats_pf,
6676 .start_stats = efx_mcdi_mac_start_stats,
6677 .pull_stats = efx_mcdi_mac_pull_stats,
6678 .stop_stats = efx_mcdi_mac_stop_stats,
6679 .set_id_led = efx_mcdi_set_id_led,
6680 .push_irq_moderation = efx_ef10_push_irq_moderation,
6681 .reconfigure_mac = efx_ef10_mac_reconfigure,
6682 .check_mac_fault = efx_mcdi_mac_check_fault,
6683 .reconfigure_port = efx_mcdi_port_reconfigure,
6684 .get_wol = efx_ef10_get_wol,
6685 .set_wol = efx_ef10_set_wol,
6686 .resume_wol = efx_port_dummy_op_void,
6687 .test_chip = efx_ef10_test_chip,
6688 .test_nvram = efx_mcdi_nvram_test_all,
6689 .mcdi_request = efx_ef10_mcdi_request,
6690 .mcdi_poll_response = efx_ef10_mcdi_poll_response,
6691 .mcdi_read_response = efx_ef10_mcdi_read_response,
6692 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
6693 .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected,
6694 .irq_enable_master = efx_port_dummy_op_void,
6695 .irq_test_generate = efx_ef10_irq_test_generate,
6696 .irq_disable_non_ev = efx_port_dummy_op_void,
6697 .irq_handle_msi = efx_ef10_msi_interrupt,
6698 .irq_handle_legacy = efx_ef10_legacy_interrupt,
6699 .tx_probe = efx_ef10_tx_probe,
6700 .tx_init = efx_ef10_tx_init,
6701 .tx_remove = efx_ef10_tx_remove,
6702 .tx_write = efx_ef10_tx_write,
6703 .tx_limit_len = efx_ef10_tx_limit_len,
6704 .rx_push_rss_config = efx_ef10_pf_rx_push_rss_config,
6705 .rx_pull_rss_config = efx_ef10_rx_pull_rss_config,
6706 .rx_push_rss_context_config = efx_ef10_rx_push_rss_context_config,
6707 .rx_pull_rss_context_config = efx_ef10_rx_pull_rss_context_config,
6708 .rx_restore_rss_contexts = efx_ef10_rx_restore_rss_contexts,
6709 .rx_probe = efx_ef10_rx_probe,
6710 .rx_init = efx_ef10_rx_init,
6711 .rx_remove = efx_ef10_rx_remove,
6712 .rx_write = efx_ef10_rx_write,
6713 .rx_defer_refill = efx_ef10_rx_defer_refill,
6714 .ev_probe = efx_ef10_ev_probe,
6715 .ev_init = efx_ef10_ev_init,
6716 .ev_fini = efx_ef10_ev_fini,
6717 .ev_remove = efx_ef10_ev_remove,
6718 .ev_process = efx_ef10_ev_process,
6719 .ev_read_ack = efx_ef10_ev_read_ack,
6720 .ev_test_generate = efx_ef10_ev_test_generate,
6721 .filter_table_probe = efx_ef10_filter_table_probe,
6722 .filter_table_restore = efx_ef10_filter_table_restore,
6723 .filter_table_remove = efx_ef10_filter_table_remove,
6724 .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
6725 .filter_insert = efx_ef10_filter_insert,
6726 .filter_remove_safe = efx_ef10_filter_remove_safe,
6727 .filter_get_safe = efx_ef10_filter_get_safe,
6728 .filter_clear_rx = efx_ef10_filter_clear_rx,
6729 .filter_count_rx_used = efx_ef10_filter_count_rx_used,
6730 .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
6731 .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
6732 #ifdef CONFIG_RFS_ACCEL
6733 .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
6735 #ifdef CONFIG_SFC_MTD
6736 .mtd_probe = efx_ef10_mtd_probe,
6737 .mtd_rename = efx_mcdi_mtd_rename,
6738 .mtd_read = efx_mcdi_mtd_read,
6739 .mtd_erase = efx_mcdi_mtd_erase,
6740 .mtd_write = efx_mcdi_mtd_write,
6741 .mtd_sync = efx_mcdi_mtd_sync,
6743 .ptp_write_host_time = efx_ef10_ptp_write_host_time,
6744 .ptp_set_ts_sync_events = efx_ef10_ptp_set_ts_sync_events,
6745 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config,
6746 .vlan_rx_add_vid = efx_ef10_vlan_rx_add_vid,
6747 .vlan_rx_kill_vid = efx_ef10_vlan_rx_kill_vid,
6748 .udp_tnl_push_ports = efx_ef10_udp_tnl_push_ports,
6749 .udp_tnl_add_port = efx_ef10_udp_tnl_add_port,
6750 .udp_tnl_has_port = efx_ef10_udp_tnl_has_port,
6751 .udp_tnl_del_port = efx_ef10_udp_tnl_del_port,
6752 #ifdef CONFIG_SFC_SRIOV
6753 .sriov_configure = efx_ef10_sriov_configure,
6754 .sriov_init = efx_ef10_sriov_init,
6755 .sriov_fini = efx_ef10_sriov_fini,
6756 .sriov_wanted = efx_ef10_sriov_wanted,
6757 .sriov_reset = efx_ef10_sriov_reset,
6758 .sriov_flr = efx_ef10_sriov_flr,
6759 .sriov_set_vf_mac = efx_ef10_sriov_set_vf_mac,
6760 .sriov_set_vf_vlan = efx_ef10_sriov_set_vf_vlan,
6761 .sriov_set_vf_spoofchk = efx_ef10_sriov_set_vf_spoofchk,
6762 .sriov_get_vf_config = efx_ef10_sriov_get_vf_config,
6763 .sriov_set_vf_link_state = efx_ef10_sriov_set_vf_link_state,
6764 .vswitching_probe = efx_ef10_vswitching_probe_pf,
6765 .vswitching_restore = efx_ef10_vswitching_restore_pf,
6766 .vswitching_remove = efx_ef10_vswitching_remove_pf,
6768 .get_mac_address = efx_ef10_get_mac_address_pf,
6769 .set_mac_address = efx_ef10_set_mac_address,
6770 .tso_versions = efx_ef10_tso_versions,
6772 .get_phys_port_id = efx_ef10_get_phys_port_id,
6773 .revision = EFX_REV_HUNT_A0,
6774 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
6775 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
6776 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
6777 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
6778 .can_rx_scatter = true,
6779 .always_rx_scatter = true,
6780 .option_descriptors = true,
6781 .min_interrupt_mode = EFX_INT_MODE_LEGACY,
6782 .max_interrupt_mode = EFX_INT_MODE_MSIX,
6783 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
6784 .offload_features = EF10_OFFLOAD_FEATURES,
6786 .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,
6787 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
6788 1 << HWTSTAMP_FILTER_ALL,
6789 .rx_hash_key_size = 40,