1 // SPDX-License-Identifier: GPL-2.0-only
2 /****************************************************************************
3 * Driver for Solarflare network controllers and boards
4 * Copyright 2012-2013 Solarflare Communications Inc.
7 #include "net_driver.h"
10 #include "ef10_regs.h"
13 #include "mcdi_pcol.h"
14 #include "mcdi_port.h"
15 #include "mcdi_port_common.h"
16 #include "mcdi_functions.h"
18 #include "mcdi_filters.h"
19 #include "workarounds.h"
21 #include "ef10_sriov.h"
23 #include <linux/jhash.h>
24 #include <linux/wait.h>
25 #include <linux/workqueue.h>
26 #include <net/udp_tunnel.h>
28 /* Hardware control for EF10 architecture including 'Huntington'. */
30 #define EFX_EF10_DRVGEN_EV 7
37 struct efx_ef10_vlan {
38 struct list_head list;
42 static int efx_ef10_set_udp_tnl_ports(struct efx_nic *efx, bool unloading);
43 static const struct udp_tunnel_nic_info efx_ef10_udp_tunnels;
45 static int efx_ef10_get_warm_boot_count(struct efx_nic *efx)
49 efx_readd(efx, ®, ER_DZ_BIU_MC_SFT_STATUS);
50 return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ?
51 EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO;
54 /* On all EF10s up to and including SFC9220 (Medford1), all PFs use BAR 0 for
55 * I/O space and BAR 2(&3) for memory. On SFC9250 (Medford2), there is no I/O
56 * bar; PFs use BAR 0/1 for memory.
58 static unsigned int efx_ef10_pf_mem_bar(struct efx_nic *efx)
60 switch (efx->pci_dev->device) {
61 case 0x0b03: /* SFC9250 PF */
68 /* All VFs use BAR 0/1 for memory */
69 static unsigned int efx_ef10_vf_mem_bar(struct efx_nic *efx)
74 static unsigned int efx_ef10_mem_map_size(struct efx_nic *efx)
78 bar = efx->type->mem_bar(efx);
79 return resource_size(&efx->pci_dev->resource[bar]);
82 static bool efx_ef10_is_vf(struct efx_nic *efx)
84 return efx->type->is_vf;
87 #ifdef CONFIG_SFC_SRIOV
88 static int efx_ef10_get_vf_index(struct efx_nic *efx)
90 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN);
91 struct efx_ef10_nic_data *nic_data = efx->nic_data;
95 rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf,
96 sizeof(outbuf), &outlen);
99 if (outlen < sizeof(outbuf))
102 nic_data->vf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_VF);
107 static int efx_ef10_init_datapath_caps(struct efx_nic *efx)
109 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_V4_OUT_LEN);
110 struct efx_ef10_nic_data *nic_data = efx->nic_data;
114 BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0);
116 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0,
117 outbuf, sizeof(outbuf), &outlen);
120 if (outlen < MC_CMD_GET_CAPABILITIES_OUT_LEN) {
121 netif_err(efx, drv, efx->net_dev,
122 "unable to read datapath firmware capabilities\n");
126 nic_data->datapath_caps =
127 MCDI_DWORD(outbuf, GET_CAPABILITIES_OUT_FLAGS1);
129 if (outlen >= MC_CMD_GET_CAPABILITIES_V2_OUT_LEN) {
130 nic_data->datapath_caps2 = MCDI_DWORD(outbuf,
131 GET_CAPABILITIES_V2_OUT_FLAGS2);
132 nic_data->piobuf_size = MCDI_WORD(outbuf,
133 GET_CAPABILITIES_V2_OUT_SIZE_PIO_BUFF);
135 nic_data->datapath_caps2 = 0;
136 nic_data->piobuf_size = ER_DZ_TX_PIOBUF_SIZE;
139 /* record the DPCPU firmware IDs to determine VEB vswitching support.
141 nic_data->rx_dpcpu_fw_id =
142 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID);
143 nic_data->tx_dpcpu_fw_id =
144 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID);
146 if (!(nic_data->datapath_caps &
147 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN))) {
148 netif_err(efx, probe, efx->net_dev,
149 "current firmware does not support an RX prefix\n");
153 if (outlen >= MC_CMD_GET_CAPABILITIES_V3_OUT_LEN) {
154 u8 vi_window_mode = MCDI_BYTE(outbuf,
155 GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE);
157 rc = efx_mcdi_window_mode_to_stride(efx, vi_window_mode);
161 /* keep default VI stride */
162 netif_dbg(efx, probe, efx->net_dev,
163 "firmware did not report VI window mode, assuming vi_stride = %u\n",
167 if (outlen >= MC_CMD_GET_CAPABILITIES_V4_OUT_LEN) {
168 efx->num_mac_stats = MCDI_WORD(outbuf,
169 GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS);
170 netif_dbg(efx, probe, efx->net_dev,
171 "firmware reports num_mac_stats = %u\n",
174 /* leave num_mac_stats as the default value, MC_CMD_MAC_NSTATS */
175 netif_dbg(efx, probe, efx->net_dev,
176 "firmware did not report num_mac_stats, assuming %u\n",
183 static void efx_ef10_read_licensed_features(struct efx_nic *efx)
185 MCDI_DECLARE_BUF(inbuf, MC_CMD_LICENSING_V3_IN_LEN);
186 MCDI_DECLARE_BUF(outbuf, MC_CMD_LICENSING_V3_OUT_LEN);
187 struct efx_ef10_nic_data *nic_data = efx->nic_data;
191 MCDI_SET_DWORD(inbuf, LICENSING_V3_IN_OP,
192 MC_CMD_LICENSING_V3_IN_OP_REPORT_LICENSE);
193 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_LICENSING_V3, inbuf, sizeof(inbuf),
194 outbuf, sizeof(outbuf), &outlen);
195 if (rc || (outlen < MC_CMD_LICENSING_V3_OUT_LEN))
198 nic_data->licensed_features = MCDI_QWORD(outbuf,
199 LICENSING_V3_OUT_LICENSED_FEATURES);
202 static int efx_ef10_get_sysclk_freq(struct efx_nic *efx)
204 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CLOCK_OUT_LEN);
207 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CLOCK, NULL, 0,
208 outbuf, sizeof(outbuf), NULL);
211 rc = MCDI_DWORD(outbuf, GET_CLOCK_OUT_SYS_FREQ);
212 return rc > 0 ? rc : -ERANGE;
215 static int efx_ef10_get_timer_workarounds(struct efx_nic *efx)
217 struct efx_ef10_nic_data *nic_data = efx->nic_data;
218 unsigned int implemented;
219 unsigned int enabled;
222 nic_data->workaround_35388 = false;
223 nic_data->workaround_61265 = false;
225 rc = efx_mcdi_get_workarounds(efx, &implemented, &enabled);
228 /* Firmware without GET_WORKAROUNDS - not a problem. */
230 } else if (rc == 0) {
231 /* Bug61265 workaround is always enabled if implemented. */
232 if (enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG61265)
233 nic_data->workaround_61265 = true;
235 if (enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG35388) {
236 nic_data->workaround_35388 = true;
237 } else if (implemented & MC_CMD_GET_WORKAROUNDS_OUT_BUG35388) {
238 /* Workaround is implemented but not enabled.
241 rc = efx_mcdi_set_workaround(efx,
242 MC_CMD_WORKAROUND_BUG35388,
245 nic_data->workaround_35388 = true;
246 /* If we failed to set the workaround just carry on. */
251 netif_dbg(efx, probe, efx->net_dev,
252 "workaround for bug 35388 is %sabled\n",
253 nic_data->workaround_35388 ? "en" : "dis");
254 netif_dbg(efx, probe, efx->net_dev,
255 "workaround for bug 61265 is %sabled\n",
256 nic_data->workaround_61265 ? "en" : "dis");
261 static void efx_ef10_process_timer_config(struct efx_nic *efx,
262 const efx_dword_t *data)
264 unsigned int max_count;
266 if (EFX_EF10_WORKAROUND_61265(efx)) {
267 efx->timer_quantum_ns = MCDI_DWORD(data,
268 GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_STEP_NS);
269 efx->timer_max_ns = MCDI_DWORD(data,
270 GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_MAX_NS);
271 } else if (EFX_EF10_WORKAROUND_35388(efx)) {
272 efx->timer_quantum_ns = MCDI_DWORD(data,
273 GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_NS_PER_COUNT);
274 max_count = MCDI_DWORD(data,
275 GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_MAX_COUNT);
276 efx->timer_max_ns = max_count * efx->timer_quantum_ns;
278 efx->timer_quantum_ns = MCDI_DWORD(data,
279 GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_NS_PER_COUNT);
280 max_count = MCDI_DWORD(data,
281 GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_MAX_COUNT);
282 efx->timer_max_ns = max_count * efx->timer_quantum_ns;
285 netif_dbg(efx, probe, efx->net_dev,
286 "got timer properties from MC: quantum %u ns; max %u ns\n",
287 efx->timer_quantum_ns, efx->timer_max_ns);
290 static int efx_ef10_get_timer_config(struct efx_nic *efx)
292 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN);
295 rc = efx_ef10_get_timer_workarounds(efx);
299 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_GET_EVQ_TMR_PROPERTIES, NULL, 0,
300 outbuf, sizeof(outbuf), NULL);
303 efx_ef10_process_timer_config(efx, outbuf);
304 } else if (rc == -ENOSYS || rc == -EPERM) {
305 /* Not available - fall back to Huntington defaults. */
306 unsigned int quantum;
308 rc = efx_ef10_get_sysclk_freq(efx);
312 quantum = 1536000 / rc; /* 1536 cycles */
313 efx->timer_quantum_ns = quantum;
314 efx->timer_max_ns = efx->type->timer_period_max * quantum;
317 efx_mcdi_display_error(efx, MC_CMD_GET_EVQ_TMR_PROPERTIES,
318 MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN,
325 static int efx_ef10_get_mac_address_pf(struct efx_nic *efx, u8 *mac_address)
327 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN);
331 BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0);
333 rc = efx_mcdi_rpc(efx, MC_CMD_GET_MAC_ADDRESSES, NULL, 0,
334 outbuf, sizeof(outbuf), &outlen);
337 if (outlen < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN)
340 ether_addr_copy(mac_address,
341 MCDI_PTR(outbuf, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE));
345 static int efx_ef10_get_mac_address_vf(struct efx_nic *efx, u8 *mac_address)
347 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN);
348 MCDI_DECLARE_BUF(outbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX);
352 MCDI_SET_DWORD(inbuf, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID,
353 EVB_PORT_ID_ASSIGNED);
354 rc = efx_mcdi_rpc(efx, MC_CMD_VPORT_GET_MAC_ADDRESSES, inbuf,
355 sizeof(inbuf), outbuf, sizeof(outbuf), &outlen);
359 if (outlen < MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN)
362 num_addrs = MCDI_DWORD(outbuf,
363 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT);
365 WARN_ON(num_addrs != 1);
367 ether_addr_copy(mac_address,
368 MCDI_PTR(outbuf, VPORT_GET_MAC_ADDRESSES_OUT_MACADDR));
373 static ssize_t efx_ef10_show_link_control_flag(struct device *dev,
374 struct device_attribute *attr,
377 struct efx_nic *efx = dev_get_drvdata(dev);
379 return sprintf(buf, "%d\n",
380 ((efx->mcdi->fn_flags) &
381 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL))
385 static ssize_t efx_ef10_show_primary_flag(struct device *dev,
386 struct device_attribute *attr,
389 struct efx_nic *efx = dev_get_drvdata(dev);
391 return sprintf(buf, "%d\n",
392 ((efx->mcdi->fn_flags) &
393 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY))
397 static struct efx_ef10_vlan *efx_ef10_find_vlan(struct efx_nic *efx, u16 vid)
399 struct efx_ef10_nic_data *nic_data = efx->nic_data;
400 struct efx_ef10_vlan *vlan;
402 WARN_ON(!mutex_is_locked(&nic_data->vlan_lock));
404 list_for_each_entry(vlan, &nic_data->vlan_list, list) {
405 if (vlan->vid == vid)
412 static int efx_ef10_add_vlan(struct efx_nic *efx, u16 vid)
414 struct efx_ef10_nic_data *nic_data = efx->nic_data;
415 struct efx_ef10_vlan *vlan;
418 mutex_lock(&nic_data->vlan_lock);
420 vlan = efx_ef10_find_vlan(efx, vid);
422 /* We add VID 0 on init. 8021q adds it on module init
423 * for all interfaces with VLAN filtring feature.
427 netif_warn(efx, drv, efx->net_dev,
428 "VLAN %u already added\n", vid);
434 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL);
440 list_add_tail(&vlan->list, &nic_data->vlan_list);
442 if (efx->filter_state) {
443 mutex_lock(&efx->mac_lock);
444 down_write(&efx->filter_sem);
445 rc = efx_mcdi_filter_add_vlan(efx, vlan->vid);
446 up_write(&efx->filter_sem);
447 mutex_unlock(&efx->mac_lock);
449 goto fail_filter_add_vlan;
453 mutex_unlock(&nic_data->vlan_lock);
456 fail_filter_add_vlan:
457 list_del(&vlan->list);
461 mutex_unlock(&nic_data->vlan_lock);
465 static void efx_ef10_del_vlan_internal(struct efx_nic *efx,
466 struct efx_ef10_vlan *vlan)
468 struct efx_ef10_nic_data *nic_data = efx->nic_data;
470 WARN_ON(!mutex_is_locked(&nic_data->vlan_lock));
472 if (efx->filter_state) {
473 down_write(&efx->filter_sem);
474 efx_mcdi_filter_del_vlan(efx, vlan->vid);
475 up_write(&efx->filter_sem);
478 list_del(&vlan->list);
482 static int efx_ef10_del_vlan(struct efx_nic *efx, u16 vid)
484 struct efx_ef10_nic_data *nic_data = efx->nic_data;
485 struct efx_ef10_vlan *vlan;
488 /* 8021q removes VID 0 on module unload for all interfaces
489 * with VLAN filtering feature. We need to keep it to receive
495 mutex_lock(&nic_data->vlan_lock);
497 vlan = efx_ef10_find_vlan(efx, vid);
499 netif_err(efx, drv, efx->net_dev,
500 "VLAN %u to be deleted not found\n", vid);
503 efx_ef10_del_vlan_internal(efx, vlan);
506 mutex_unlock(&nic_data->vlan_lock);
511 static void efx_ef10_cleanup_vlans(struct efx_nic *efx)
513 struct efx_ef10_nic_data *nic_data = efx->nic_data;
514 struct efx_ef10_vlan *vlan, *next_vlan;
516 mutex_lock(&nic_data->vlan_lock);
517 list_for_each_entry_safe(vlan, next_vlan, &nic_data->vlan_list, list)
518 efx_ef10_del_vlan_internal(efx, vlan);
519 mutex_unlock(&nic_data->vlan_lock);
522 static DEVICE_ATTR(link_control_flag, 0444, efx_ef10_show_link_control_flag,
524 static DEVICE_ATTR(primary_flag, 0444, efx_ef10_show_primary_flag, NULL);
526 static int efx_ef10_probe(struct efx_nic *efx)
528 struct efx_ef10_nic_data *nic_data;
531 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
534 efx->nic_data = nic_data;
536 /* we assume later that we can copy from this buffer in dwords */
537 BUILD_BUG_ON(MCDI_CTL_SDU_LEN_MAX_V2 % 4);
539 rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf,
540 8 + MCDI_CTL_SDU_LEN_MAX_V2, GFP_KERNEL);
544 /* Get the MC's warm boot count. In case it's rebooting right
545 * now, be prepared to retry.
549 rc = efx_ef10_get_warm_boot_count(efx);
556 nic_data->warm_boot_count = rc;
558 /* In case we're recovering from a crash (kexec), we want to
559 * cancel any outstanding request by the previous user of this
560 * function. We send a special message using the least
561 * significant bits of the 'high' (doorbell) register.
563 _efx_writed(efx, cpu_to_le32(1), ER_DZ_MC_DB_HWRD);
565 rc = efx_mcdi_init(efx);
569 mutex_init(&nic_data->udp_tunnels_lock);
570 for (i = 0; i < ARRAY_SIZE(nic_data->udp_tunnels); ++i)
571 nic_data->udp_tunnels[i].type =
572 TUNNEL_ENCAP_UDP_PORT_ENTRY_INVALID;
574 /* Reset (most) configuration for this function */
575 rc = efx_mcdi_reset(efx, RESET_TYPE_ALL);
579 /* Enable event logging */
580 rc = efx_mcdi_log_ctrl(efx, true, false, 0);
584 rc = device_create_file(&efx->pci_dev->dev,
585 &dev_attr_link_control_flag);
589 rc = device_create_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
593 rc = efx_get_pf_index(efx, &nic_data->pf_index);
597 rc = efx_ef10_init_datapath_caps(efx);
601 efx_ef10_read_licensed_features(efx);
603 /* We can have one VI for each vi_stride-byte region.
604 * However, until we use TX option descriptors we need up to four
605 * TX queues per channel for different checksumming combinations.
607 if (nic_data->datapath_caps &
608 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN))
609 efx->tx_queues_per_channel = 4;
611 efx->tx_queues_per_channel = 2;
612 efx->max_vis = efx_ef10_mem_map_size(efx) / efx->vi_stride;
614 netif_err(efx, drv, efx->net_dev, "error determining max VIs\n");
618 efx->max_channels = min_t(unsigned int, EFX_MAX_CHANNELS,
619 efx->max_vis / efx->tx_queues_per_channel);
620 efx->max_tx_channels = efx->max_channels;
621 if (WARN_ON(efx->max_channels == 0)) {
626 efx->rx_packet_len_offset =
627 ES_DZ_RX_PREFIX_PKTLEN_OFST - ES_DZ_RX_PREFIX_SIZE;
629 if (nic_data->datapath_caps &
630 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_LBN))
631 efx->net_dev->hw_features |= NETIF_F_RXFCS;
633 rc = efx_mcdi_port_get_number(efx);
638 rc = efx->type->get_mac_address(efx, efx->net_dev->perm_addr);
642 rc = efx_ef10_get_timer_config(efx);
646 rc = efx_mcdi_mon_probe(efx);
647 if (rc && rc != -EPERM)
650 efx_ptp_defer_probe_with_channel(efx);
652 #ifdef CONFIG_SFC_SRIOV
653 if ((efx->pci_dev->physfn) && (!efx->pci_dev->is_physfn)) {
654 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn;
655 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
657 efx_pf->type->get_mac_address(efx_pf, nic_data->port_id);
660 ether_addr_copy(nic_data->port_id, efx->net_dev->perm_addr);
662 INIT_LIST_HEAD(&nic_data->vlan_list);
663 mutex_init(&nic_data->vlan_lock);
665 /* Add unspecified VID to support VLAN filtering being disabled */
666 rc = efx_ef10_add_vlan(efx, EFX_FILTER_VID_UNSPEC);
668 goto fail_add_vid_unspec;
670 /* If VLAN filtering is enabled, we need VID 0 to get untagged
671 * traffic. It is added automatically if 8021q module is loaded,
672 * but we can't rely on it since module may be not loaded.
674 rc = efx_ef10_add_vlan(efx, 0);
678 if (nic_data->datapath_caps &
679 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN) &&
680 efx->mcdi->fn_flags &
681 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_TRUSTED))
682 efx->net_dev->udp_tunnel_nic_info = &efx_ef10_udp_tunnels;
687 efx_ef10_cleanup_vlans(efx);
689 mutex_destroy(&nic_data->vlan_lock);
691 efx_mcdi_mon_remove(efx);
693 device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
695 device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag);
697 efx_mcdi_detach(efx);
699 mutex_lock(&nic_data->udp_tunnels_lock);
700 memset(nic_data->udp_tunnels, 0, sizeof(nic_data->udp_tunnels));
701 (void)efx_ef10_set_udp_tnl_ports(efx, true);
702 mutex_unlock(&nic_data->udp_tunnels_lock);
703 mutex_destroy(&nic_data->udp_tunnels_lock);
707 efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
710 efx->nic_data = NULL;
716 static void efx_ef10_free_piobufs(struct efx_nic *efx)
718 struct efx_ef10_nic_data *nic_data = efx->nic_data;
719 MCDI_DECLARE_BUF(inbuf, MC_CMD_FREE_PIOBUF_IN_LEN);
723 BUILD_BUG_ON(MC_CMD_FREE_PIOBUF_OUT_LEN != 0);
725 for (i = 0; i < nic_data->n_piobufs; i++) {
726 MCDI_SET_DWORD(inbuf, FREE_PIOBUF_IN_PIOBUF_HANDLE,
727 nic_data->piobuf_handle[i]);
728 rc = efx_mcdi_rpc(efx, MC_CMD_FREE_PIOBUF, inbuf, sizeof(inbuf),
733 nic_data->n_piobufs = 0;
736 static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
738 struct efx_ef10_nic_data *nic_data = efx->nic_data;
739 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_PIOBUF_OUT_LEN);
744 BUILD_BUG_ON(MC_CMD_ALLOC_PIOBUF_IN_LEN != 0);
746 for (i = 0; i < n; i++) {
747 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_ALLOC_PIOBUF, NULL, 0,
748 outbuf, sizeof(outbuf), &outlen);
750 /* Don't display the MC error if we didn't have space
753 if (!(efx_ef10_is_vf(efx) && rc == -ENOSPC))
754 efx_mcdi_display_error(efx, MC_CMD_ALLOC_PIOBUF,
755 0, outbuf, outlen, rc);
758 if (outlen < MC_CMD_ALLOC_PIOBUF_OUT_LEN) {
762 nic_data->piobuf_handle[i] =
763 MCDI_DWORD(outbuf, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE);
764 netif_dbg(efx, probe, efx->net_dev,
765 "allocated PIO buffer %u handle %x\n", i,
766 nic_data->piobuf_handle[i]);
769 nic_data->n_piobufs = i;
771 efx_ef10_free_piobufs(efx);
775 static int efx_ef10_link_piobufs(struct efx_nic *efx)
777 struct efx_ef10_nic_data *nic_data = efx->nic_data;
778 MCDI_DECLARE_BUF(inbuf, MC_CMD_LINK_PIOBUF_IN_LEN);
779 struct efx_channel *channel;
780 struct efx_tx_queue *tx_queue;
781 unsigned int offset, index;
784 BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_OUT_LEN != 0);
785 BUILD_BUG_ON(MC_CMD_UNLINK_PIOBUF_OUT_LEN != 0);
787 /* Link a buffer to each VI in the write-combining mapping */
788 for (index = 0; index < nic_data->n_piobufs; ++index) {
789 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_PIOBUF_HANDLE,
790 nic_data->piobuf_handle[index]);
791 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_TXQ_INSTANCE,
792 nic_data->pio_write_vi_base + index);
793 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
794 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
797 netif_err(efx, drv, efx->net_dev,
798 "failed to link VI %u to PIO buffer %u (%d)\n",
799 nic_data->pio_write_vi_base + index, index,
803 netif_dbg(efx, probe, efx->net_dev,
804 "linked VI %u to PIO buffer %u\n",
805 nic_data->pio_write_vi_base + index, index);
808 /* Link a buffer to each TX queue */
809 efx_for_each_channel(channel, efx) {
810 /* Extra channels, even those with TXQs (PTP), do not require
813 if (!channel->type->want_pio ||
814 channel->channel >= efx->xdp_channel_offset)
817 efx_for_each_channel_tx_queue(tx_queue, channel) {
818 /* We assign the PIO buffers to queues in
819 * reverse order to allow for the following
822 offset = ((efx->tx_channel_offset + efx->n_tx_channels -
823 tx_queue->channel->channel - 1) *
825 index = offset / nic_data->piobuf_size;
826 offset = offset % nic_data->piobuf_size;
828 /* When the host page size is 4K, the first
829 * host page in the WC mapping may be within
830 * the same VI page as the last TX queue. We
831 * can only link one buffer to each VI.
833 if (tx_queue->queue == nic_data->pio_write_vi_base) {
837 MCDI_SET_DWORD(inbuf,
838 LINK_PIOBUF_IN_PIOBUF_HANDLE,
839 nic_data->piobuf_handle[index]);
840 MCDI_SET_DWORD(inbuf,
841 LINK_PIOBUF_IN_TXQ_INSTANCE,
843 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
844 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
849 /* This is non-fatal; the TX path just
850 * won't use PIO for this queue
852 netif_err(efx, drv, efx->net_dev,
853 "failed to link VI %u to PIO buffer %u (%d)\n",
854 tx_queue->queue, index, rc);
855 tx_queue->piobuf = NULL;
858 nic_data->pio_write_base +
859 index * efx->vi_stride + offset;
860 tx_queue->piobuf_offset = offset;
861 netif_dbg(efx, probe, efx->net_dev,
862 "linked VI %u to PIO buffer %u offset %x addr %p\n",
863 tx_queue->queue, index,
864 tx_queue->piobuf_offset,
873 /* inbuf was defined for MC_CMD_LINK_PIOBUF. We can use the same
874 * buffer for MC_CMD_UNLINK_PIOBUF because it's shorter.
876 BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_IN_LEN < MC_CMD_UNLINK_PIOBUF_IN_LEN);
878 MCDI_SET_DWORD(inbuf, UNLINK_PIOBUF_IN_TXQ_INSTANCE,
879 nic_data->pio_write_vi_base + index);
880 efx_mcdi_rpc(efx, MC_CMD_UNLINK_PIOBUF,
881 inbuf, MC_CMD_UNLINK_PIOBUF_IN_LEN,
887 static void efx_ef10_forget_old_piobufs(struct efx_nic *efx)
889 struct efx_channel *channel;
890 struct efx_tx_queue *tx_queue;
892 /* All our existing PIO buffers went away */
893 efx_for_each_channel(channel, efx)
894 efx_for_each_channel_tx_queue(tx_queue, channel)
895 tx_queue->piobuf = NULL;
898 #else /* !EFX_USE_PIO */
900 static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
902 return n == 0 ? 0 : -ENOBUFS;
905 static int efx_ef10_link_piobufs(struct efx_nic *efx)
910 static void efx_ef10_free_piobufs(struct efx_nic *efx)
914 static void efx_ef10_forget_old_piobufs(struct efx_nic *efx)
918 #endif /* EFX_USE_PIO */
920 static void efx_ef10_remove(struct efx_nic *efx)
922 struct efx_ef10_nic_data *nic_data = efx->nic_data;
925 #ifdef CONFIG_SFC_SRIOV
926 struct efx_ef10_nic_data *nic_data_pf;
927 struct pci_dev *pci_dev_pf;
928 struct efx_nic *efx_pf;
931 if (efx->pci_dev->is_virtfn) {
932 pci_dev_pf = efx->pci_dev->physfn;
934 efx_pf = pci_get_drvdata(pci_dev_pf);
935 nic_data_pf = efx_pf->nic_data;
936 vf = nic_data_pf->vf + nic_data->vf_index;
939 netif_info(efx, drv, efx->net_dev,
940 "Could not get the PF id from VF\n");
944 efx_ef10_cleanup_vlans(efx);
945 mutex_destroy(&nic_data->vlan_lock);
949 efx_mcdi_mon_remove(efx);
951 efx_mcdi_rx_free_indir_table(efx);
953 if (nic_data->wc_membase)
954 iounmap(nic_data->wc_membase);
956 rc = efx_mcdi_free_vis(efx);
959 if (!nic_data->must_restore_piobufs)
960 efx_ef10_free_piobufs(efx);
962 device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
963 device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag);
965 efx_mcdi_detach(efx);
967 memset(nic_data->udp_tunnels, 0, sizeof(nic_data->udp_tunnels));
968 mutex_lock(&nic_data->udp_tunnels_lock);
969 (void)efx_ef10_set_udp_tnl_ports(efx, true);
970 mutex_unlock(&nic_data->udp_tunnels_lock);
972 mutex_destroy(&nic_data->udp_tunnels_lock);
975 efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
979 static int efx_ef10_probe_pf(struct efx_nic *efx)
981 return efx_ef10_probe(efx);
984 int efx_ef10_vadaptor_query(struct efx_nic *efx, unsigned int port_id,
985 u32 *port_flags, u32 *vadaptor_flags,
986 unsigned int *vlan_tags)
988 struct efx_ef10_nic_data *nic_data = efx->nic_data;
989 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_QUERY_IN_LEN);
990 MCDI_DECLARE_BUF(outbuf, MC_CMD_VADAPTOR_QUERY_OUT_LEN);
994 if (nic_data->datapath_caps &
995 (1 << MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_LBN)) {
996 MCDI_SET_DWORD(inbuf, VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID,
999 rc = efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_QUERY, inbuf, sizeof(inbuf),
1000 outbuf, sizeof(outbuf), &outlen);
1004 if (outlen < sizeof(outbuf)) {
1011 *port_flags = MCDI_DWORD(outbuf, VADAPTOR_QUERY_OUT_PORT_FLAGS);
1014 MCDI_DWORD(outbuf, VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS);
1018 VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS);
1023 int efx_ef10_vadaptor_alloc(struct efx_nic *efx, unsigned int port_id)
1025 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_ALLOC_IN_LEN);
1027 MCDI_SET_DWORD(inbuf, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID, port_id);
1028 return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_ALLOC, inbuf, sizeof(inbuf),
1032 int efx_ef10_vadaptor_free(struct efx_nic *efx, unsigned int port_id)
1034 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_FREE_IN_LEN);
1036 MCDI_SET_DWORD(inbuf, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID, port_id);
1037 return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_FREE, inbuf, sizeof(inbuf),
1041 int efx_ef10_vport_add_mac(struct efx_nic *efx,
1042 unsigned int port_id, u8 *mac)
1044 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN);
1046 MCDI_SET_DWORD(inbuf, VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID, port_id);
1047 ether_addr_copy(MCDI_PTR(inbuf, VPORT_ADD_MAC_ADDRESS_IN_MACADDR), mac);
1049 return efx_mcdi_rpc(efx, MC_CMD_VPORT_ADD_MAC_ADDRESS, inbuf,
1050 sizeof(inbuf), NULL, 0, NULL);
1053 int efx_ef10_vport_del_mac(struct efx_nic *efx,
1054 unsigned int port_id, u8 *mac)
1056 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN);
1058 MCDI_SET_DWORD(inbuf, VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID, port_id);
1059 ether_addr_copy(MCDI_PTR(inbuf, VPORT_DEL_MAC_ADDRESS_IN_MACADDR), mac);
1061 return efx_mcdi_rpc(efx, MC_CMD_VPORT_DEL_MAC_ADDRESS, inbuf,
1062 sizeof(inbuf), NULL, 0, NULL);
1065 #ifdef CONFIG_SFC_SRIOV
1066 static int efx_ef10_probe_vf(struct efx_nic *efx)
1069 struct pci_dev *pci_dev_pf;
1071 /* If the parent PF has no VF data structure, it doesn't know about this
1072 * VF so fail probe. The VF needs to be re-created. This can happen
1073 * if the PF driver is unloaded while the VF is assigned to a guest.
1075 pci_dev_pf = efx->pci_dev->physfn;
1077 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
1078 struct efx_ef10_nic_data *nic_data_pf = efx_pf->nic_data;
1080 if (!nic_data_pf->vf) {
1081 netif_info(efx, drv, efx->net_dev,
1082 "The VF cannot link to its parent PF; "
1083 "please destroy and re-create the VF\n");
1088 rc = efx_ef10_probe(efx);
1092 rc = efx_ef10_get_vf_index(efx);
1096 if (efx->pci_dev->is_virtfn) {
1097 if (efx->pci_dev->physfn) {
1098 struct efx_nic *efx_pf =
1099 pci_get_drvdata(efx->pci_dev->physfn);
1100 struct efx_ef10_nic_data *nic_data_p = efx_pf->nic_data;
1101 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1103 nic_data_p->vf[nic_data->vf_index].efx = efx;
1104 nic_data_p->vf[nic_data->vf_index].pci_dev =
1107 netif_info(efx, drv, efx->net_dev,
1108 "Could not get the PF id from VF\n");
1114 efx_ef10_remove(efx);
1118 static int efx_ef10_probe_vf(struct efx_nic *efx __attribute__ ((unused)))
1124 static int efx_ef10_alloc_vis(struct efx_nic *efx,
1125 unsigned int min_vis, unsigned int max_vis)
1127 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1129 return efx_mcdi_alloc_vis(efx, min_vis, max_vis, &nic_data->vi_base,
1130 &nic_data->n_allocated_vis);
1133 /* Note that the failure path of this function does not free
1134 * resources, as this will be done by efx_ef10_remove().
1136 static int efx_ef10_dimension_resources(struct efx_nic *efx)
1138 unsigned int min_vis = max_t(unsigned int, efx->tx_queues_per_channel,
1139 efx_separate_tx_channels ? 2 : 1);
1140 unsigned int channel_vis, pio_write_vi_base, max_vis;
1141 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1142 unsigned int uc_mem_map_size, wc_mem_map_size;
1143 void __iomem *membase;
1146 channel_vis = max(efx->n_channels,
1147 ((efx->n_tx_channels + efx->n_extra_tx_channels) *
1148 efx->tx_queues_per_channel) +
1149 efx->n_xdp_channels * efx->xdp_tx_per_channel);
1150 if (efx->max_vis && efx->max_vis < channel_vis) {
1151 netif_dbg(efx, drv, efx->net_dev,
1152 "Reducing channel VIs from %u to %u\n",
1153 channel_vis, efx->max_vis);
1154 channel_vis = efx->max_vis;
1158 /* Try to allocate PIO buffers if wanted and if the full
1159 * number of PIO buffers would be sufficient to allocate one
1160 * copy-buffer per TX channel. Failure is non-fatal, as there
1161 * are only a small number of PIO buffers shared between all
1162 * functions of the controller.
1164 if (efx_piobuf_size != 0 &&
1165 nic_data->piobuf_size / efx_piobuf_size * EF10_TX_PIOBUF_COUNT >=
1166 efx->n_tx_channels) {
1167 unsigned int n_piobufs =
1168 DIV_ROUND_UP(efx->n_tx_channels,
1169 nic_data->piobuf_size / efx_piobuf_size);
1171 rc = efx_ef10_alloc_piobufs(efx, n_piobufs);
1173 netif_dbg(efx, probe, efx->net_dev,
1174 "out of PIO buffers; cannot allocate more\n");
1175 else if (rc == -EPERM)
1176 netif_dbg(efx, probe, efx->net_dev,
1177 "not permitted to allocate PIO buffers\n");
1179 netif_err(efx, probe, efx->net_dev,
1180 "failed to allocate PIO buffers (%d)\n", rc);
1182 netif_dbg(efx, probe, efx->net_dev,
1183 "allocated %u PIO buffers\n", n_piobufs);
1186 nic_data->n_piobufs = 0;
1189 /* PIO buffers should be mapped with write-combining enabled,
1190 * and we want to make single UC and WC mappings rather than
1191 * several of each (in fact that's the only option if host
1192 * page size is >4K). So we may allocate some extra VIs just
1193 * for writing PIO buffers through.
1195 * The UC mapping contains (channel_vis - 1) complete VIs and the
1196 * first 4K of the next VI. Then the WC mapping begins with
1197 * the remainder of this last VI.
1199 uc_mem_map_size = PAGE_ALIGN((channel_vis - 1) * efx->vi_stride +
1201 if (nic_data->n_piobufs) {
1202 /* pio_write_vi_base rounds down to give the number of complete
1203 * VIs inside the UC mapping.
1205 pio_write_vi_base = uc_mem_map_size / efx->vi_stride;
1206 wc_mem_map_size = (PAGE_ALIGN((pio_write_vi_base +
1207 nic_data->n_piobufs) *
1210 max_vis = pio_write_vi_base + nic_data->n_piobufs;
1212 pio_write_vi_base = 0;
1213 wc_mem_map_size = 0;
1214 max_vis = channel_vis;
1217 /* In case the last attached driver failed to free VIs, do it now */
1218 rc = efx_mcdi_free_vis(efx);
1222 rc = efx_ef10_alloc_vis(efx, min_vis, max_vis);
1226 if (nic_data->n_allocated_vis < channel_vis) {
1227 netif_info(efx, drv, efx->net_dev,
1228 "Could not allocate enough VIs to satisfy RSS"
1229 " requirements. Performance may not be optimal.\n");
1230 /* We didn't get the VIs to populate our channels.
1231 * We could keep what we got but then we'd have more
1232 * interrupts than we need.
1233 * Instead calculate new max_channels and restart
1235 efx->max_channels = nic_data->n_allocated_vis;
1236 efx->max_tx_channels =
1237 nic_data->n_allocated_vis / efx->tx_queues_per_channel;
1239 efx_mcdi_free_vis(efx);
1243 /* If we didn't get enough VIs to map all the PIO buffers, free the
1246 if (nic_data->n_piobufs &&
1247 nic_data->n_allocated_vis <
1248 pio_write_vi_base + nic_data->n_piobufs) {
1249 netif_dbg(efx, probe, efx->net_dev,
1250 "%u VIs are not sufficient to map %u PIO buffers\n",
1251 nic_data->n_allocated_vis, nic_data->n_piobufs);
1252 efx_ef10_free_piobufs(efx);
1255 /* Shrink the original UC mapping of the memory BAR */
1256 membase = ioremap(efx->membase_phys, uc_mem_map_size);
1258 netif_err(efx, probe, efx->net_dev,
1259 "could not shrink memory BAR to %x\n",
1263 iounmap(efx->membase);
1264 efx->membase = membase;
1266 /* Set up the WC mapping if needed */
1267 if (wc_mem_map_size) {
1268 nic_data->wc_membase = ioremap_wc(efx->membase_phys +
1271 if (!nic_data->wc_membase) {
1272 netif_err(efx, probe, efx->net_dev,
1273 "could not allocate WC mapping of size %x\n",
1277 nic_data->pio_write_vi_base = pio_write_vi_base;
1278 nic_data->pio_write_base =
1279 nic_data->wc_membase +
1280 (pio_write_vi_base * efx->vi_stride + ER_DZ_TX_PIOBUF -
1283 rc = efx_ef10_link_piobufs(efx);
1285 efx_ef10_free_piobufs(efx);
1288 netif_dbg(efx, probe, efx->net_dev,
1289 "memory BAR at %pa (virtual %p+%x UC, %p+%x WC)\n",
1290 &efx->membase_phys, efx->membase, uc_mem_map_size,
1291 nic_data->wc_membase, wc_mem_map_size);
1296 static void efx_ef10_fini_nic(struct efx_nic *efx)
1298 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1300 kfree(nic_data->mc_stats);
1301 nic_data->mc_stats = NULL;
1304 static int efx_ef10_init_nic(struct efx_nic *efx)
1306 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1309 if (nic_data->must_check_datapath_caps) {
1310 rc = efx_ef10_init_datapath_caps(efx);
1313 nic_data->must_check_datapath_caps = false;
1316 if (efx->must_realloc_vis) {
1317 /* We cannot let the number of VIs change now */
1318 rc = efx_ef10_alloc_vis(efx, nic_data->n_allocated_vis,
1319 nic_data->n_allocated_vis);
1322 efx->must_realloc_vis = false;
1325 nic_data->mc_stats = kmalloc(efx->num_mac_stats * sizeof(__le64),
1327 if (!nic_data->mc_stats)
1330 if (nic_data->must_restore_piobufs && nic_data->n_piobufs) {
1331 rc = efx_ef10_alloc_piobufs(efx, nic_data->n_piobufs);
1333 rc = efx_ef10_link_piobufs(efx);
1335 efx_ef10_free_piobufs(efx);
1338 /* Log an error on failure, but this is non-fatal.
1339 * Permission errors are less important - we've presumably
1340 * had the PIO buffer licence removed.
1343 netif_dbg(efx, drv, efx->net_dev,
1344 "not permitted to restore PIO buffers\n");
1346 netif_err(efx, drv, efx->net_dev,
1347 "failed to restore PIO buffers (%d)\n", rc);
1348 nic_data->must_restore_piobufs = false;
1351 /* don't fail init if RSS setup doesn't work */
1352 rc = efx->type->rx_push_rss_config(efx, false,
1353 efx->rss_context.rx_indir_table, NULL);
1358 static void efx_ef10_table_reset_mc_allocations(struct efx_nic *efx)
1360 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1361 #ifdef CONFIG_SFC_SRIOV
1365 /* All our allocations have been reset */
1366 efx->must_realloc_vis = true;
1367 efx_mcdi_filter_table_reset_mc_allocations(efx);
1368 nic_data->must_restore_piobufs = true;
1369 efx_ef10_forget_old_piobufs(efx);
1370 efx->rss_context.context_id = EFX_MCDI_RSS_CONTEXT_INVALID;
1372 /* Driver-created vswitches and vports must be re-created */
1373 nic_data->must_probe_vswitching = true;
1374 efx->vport_id = EVB_PORT_ID_ASSIGNED;
1375 #ifdef CONFIG_SFC_SRIOV
1377 for (i = 0; i < efx->vf_count; i++)
1378 nic_data->vf[i].vport_id = 0;
1382 static enum reset_type efx_ef10_map_reset_reason(enum reset_type reason)
1384 if (reason == RESET_TYPE_MC_FAILURE)
1385 return RESET_TYPE_DATAPATH;
1387 return efx_mcdi_map_reset_reason(reason);
1390 static int efx_ef10_map_reset_flags(u32 *flags)
1393 EF10_RESET_PORT = ((ETH_RESET_MAC | ETH_RESET_PHY) <<
1394 ETH_RESET_SHARED_SHIFT),
1395 EF10_RESET_MC = ((ETH_RESET_DMA | ETH_RESET_FILTER |
1396 ETH_RESET_OFFLOAD | ETH_RESET_MAC |
1397 ETH_RESET_PHY | ETH_RESET_MGMT) <<
1398 ETH_RESET_SHARED_SHIFT)
1401 /* We assume for now that our PCI function is permitted to
1405 if ((*flags & EF10_RESET_MC) == EF10_RESET_MC) {
1406 *flags &= ~EF10_RESET_MC;
1407 return RESET_TYPE_WORLD;
1410 if ((*flags & EF10_RESET_PORT) == EF10_RESET_PORT) {
1411 *flags &= ~EF10_RESET_PORT;
1412 return RESET_TYPE_ALL;
1415 /* no invisible reset implemented */
1420 static int efx_ef10_reset(struct efx_nic *efx, enum reset_type reset_type)
1422 int rc = efx_mcdi_reset(efx, reset_type);
1424 /* Unprivileged functions return -EPERM, but need to return success
1425 * here so that the datapath is brought back up.
1427 if (reset_type == RESET_TYPE_WORLD && rc == -EPERM)
1430 /* If it was a port reset, trigger reallocation of MC resources.
1431 * Note that on an MC reset nothing needs to be done now because we'll
1432 * detect the MC reset later and handle it then.
1433 * For an FLR, we never get an MC reset event, but the MC has reset all
1434 * resources assigned to us, so we have to trigger reallocation now.
1436 if ((reset_type == RESET_TYPE_ALL ||
1437 reset_type == RESET_TYPE_MCDI_TIMEOUT) && !rc)
1438 efx_ef10_table_reset_mc_allocations(efx);
1442 #define EF10_DMA_STAT(ext_name, mcdi_name) \
1443 [EF10_STAT_ ## ext_name] = \
1444 { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
1445 #define EF10_DMA_INVIS_STAT(int_name, mcdi_name) \
1446 [EF10_STAT_ ## int_name] = \
1447 { NULL, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
1448 #define EF10_OTHER_STAT(ext_name) \
1449 [EF10_STAT_ ## ext_name] = { #ext_name, 0, 0 }
1451 static const struct efx_hw_stat_desc efx_ef10_stat_desc[EF10_STAT_COUNT] = {
1452 EF10_DMA_STAT(port_tx_bytes, TX_BYTES),
1453 EF10_DMA_STAT(port_tx_packets, TX_PKTS),
1454 EF10_DMA_STAT(port_tx_pause, TX_PAUSE_PKTS),
1455 EF10_DMA_STAT(port_tx_control, TX_CONTROL_PKTS),
1456 EF10_DMA_STAT(port_tx_unicast, TX_UNICAST_PKTS),
1457 EF10_DMA_STAT(port_tx_multicast, TX_MULTICAST_PKTS),
1458 EF10_DMA_STAT(port_tx_broadcast, TX_BROADCAST_PKTS),
1459 EF10_DMA_STAT(port_tx_lt64, TX_LT64_PKTS),
1460 EF10_DMA_STAT(port_tx_64, TX_64_PKTS),
1461 EF10_DMA_STAT(port_tx_65_to_127, TX_65_TO_127_PKTS),
1462 EF10_DMA_STAT(port_tx_128_to_255, TX_128_TO_255_PKTS),
1463 EF10_DMA_STAT(port_tx_256_to_511, TX_256_TO_511_PKTS),
1464 EF10_DMA_STAT(port_tx_512_to_1023, TX_512_TO_1023_PKTS),
1465 EF10_DMA_STAT(port_tx_1024_to_15xx, TX_1024_TO_15XX_PKTS),
1466 EF10_DMA_STAT(port_tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS),
1467 EF10_DMA_STAT(port_rx_bytes, RX_BYTES),
1468 EF10_DMA_INVIS_STAT(port_rx_bytes_minus_good_bytes, RX_BAD_BYTES),
1469 EF10_OTHER_STAT(port_rx_good_bytes),
1470 EF10_OTHER_STAT(port_rx_bad_bytes),
1471 EF10_DMA_STAT(port_rx_packets, RX_PKTS),
1472 EF10_DMA_STAT(port_rx_good, RX_GOOD_PKTS),
1473 EF10_DMA_STAT(port_rx_bad, RX_BAD_FCS_PKTS),
1474 EF10_DMA_STAT(port_rx_pause, RX_PAUSE_PKTS),
1475 EF10_DMA_STAT(port_rx_control, RX_CONTROL_PKTS),
1476 EF10_DMA_STAT(port_rx_unicast, RX_UNICAST_PKTS),
1477 EF10_DMA_STAT(port_rx_multicast, RX_MULTICAST_PKTS),
1478 EF10_DMA_STAT(port_rx_broadcast, RX_BROADCAST_PKTS),
1479 EF10_DMA_STAT(port_rx_lt64, RX_UNDERSIZE_PKTS),
1480 EF10_DMA_STAT(port_rx_64, RX_64_PKTS),
1481 EF10_DMA_STAT(port_rx_65_to_127, RX_65_TO_127_PKTS),
1482 EF10_DMA_STAT(port_rx_128_to_255, RX_128_TO_255_PKTS),
1483 EF10_DMA_STAT(port_rx_256_to_511, RX_256_TO_511_PKTS),
1484 EF10_DMA_STAT(port_rx_512_to_1023, RX_512_TO_1023_PKTS),
1485 EF10_DMA_STAT(port_rx_1024_to_15xx, RX_1024_TO_15XX_PKTS),
1486 EF10_DMA_STAT(port_rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS),
1487 EF10_DMA_STAT(port_rx_gtjumbo, RX_GTJUMBO_PKTS),
1488 EF10_DMA_STAT(port_rx_bad_gtjumbo, RX_JABBER_PKTS),
1489 EF10_DMA_STAT(port_rx_overflow, RX_OVERFLOW_PKTS),
1490 EF10_DMA_STAT(port_rx_align_error, RX_ALIGN_ERROR_PKTS),
1491 EF10_DMA_STAT(port_rx_length_error, RX_LENGTH_ERROR_PKTS),
1492 EF10_DMA_STAT(port_rx_nodesc_drops, RX_NODESC_DROPS),
1493 EFX_GENERIC_SW_STAT(rx_nodesc_trunc),
1494 EFX_GENERIC_SW_STAT(rx_noskb_drops),
1495 EF10_DMA_STAT(port_rx_pm_trunc_bb_overflow, PM_TRUNC_BB_OVERFLOW),
1496 EF10_DMA_STAT(port_rx_pm_discard_bb_overflow, PM_DISCARD_BB_OVERFLOW),
1497 EF10_DMA_STAT(port_rx_pm_trunc_vfifo_full, PM_TRUNC_VFIFO_FULL),
1498 EF10_DMA_STAT(port_rx_pm_discard_vfifo_full, PM_DISCARD_VFIFO_FULL),
1499 EF10_DMA_STAT(port_rx_pm_trunc_qbb, PM_TRUNC_QBB),
1500 EF10_DMA_STAT(port_rx_pm_discard_qbb, PM_DISCARD_QBB),
1501 EF10_DMA_STAT(port_rx_pm_discard_mapping, PM_DISCARD_MAPPING),
1502 EF10_DMA_STAT(port_rx_dp_q_disabled_packets, RXDP_Q_DISABLED_PKTS),
1503 EF10_DMA_STAT(port_rx_dp_di_dropped_packets, RXDP_DI_DROPPED_PKTS),
1504 EF10_DMA_STAT(port_rx_dp_streaming_packets, RXDP_STREAMING_PKTS),
1505 EF10_DMA_STAT(port_rx_dp_hlb_fetch, RXDP_HLB_FETCH_CONDITIONS),
1506 EF10_DMA_STAT(port_rx_dp_hlb_wait, RXDP_HLB_WAIT_CONDITIONS),
1507 EF10_DMA_STAT(rx_unicast, VADAPTER_RX_UNICAST_PACKETS),
1508 EF10_DMA_STAT(rx_unicast_bytes, VADAPTER_RX_UNICAST_BYTES),
1509 EF10_DMA_STAT(rx_multicast, VADAPTER_RX_MULTICAST_PACKETS),
1510 EF10_DMA_STAT(rx_multicast_bytes, VADAPTER_RX_MULTICAST_BYTES),
1511 EF10_DMA_STAT(rx_broadcast, VADAPTER_RX_BROADCAST_PACKETS),
1512 EF10_DMA_STAT(rx_broadcast_bytes, VADAPTER_RX_BROADCAST_BYTES),
1513 EF10_DMA_STAT(rx_bad, VADAPTER_RX_BAD_PACKETS),
1514 EF10_DMA_STAT(rx_bad_bytes, VADAPTER_RX_BAD_BYTES),
1515 EF10_DMA_STAT(rx_overflow, VADAPTER_RX_OVERFLOW),
1516 EF10_DMA_STAT(tx_unicast, VADAPTER_TX_UNICAST_PACKETS),
1517 EF10_DMA_STAT(tx_unicast_bytes, VADAPTER_TX_UNICAST_BYTES),
1518 EF10_DMA_STAT(tx_multicast, VADAPTER_TX_MULTICAST_PACKETS),
1519 EF10_DMA_STAT(tx_multicast_bytes, VADAPTER_TX_MULTICAST_BYTES),
1520 EF10_DMA_STAT(tx_broadcast, VADAPTER_TX_BROADCAST_PACKETS),
1521 EF10_DMA_STAT(tx_broadcast_bytes, VADAPTER_TX_BROADCAST_BYTES),
1522 EF10_DMA_STAT(tx_bad, VADAPTER_TX_BAD_PACKETS),
1523 EF10_DMA_STAT(tx_bad_bytes, VADAPTER_TX_BAD_BYTES),
1524 EF10_DMA_STAT(tx_overflow, VADAPTER_TX_OVERFLOW),
1525 EF10_DMA_STAT(fec_uncorrected_errors, FEC_UNCORRECTED_ERRORS),
1526 EF10_DMA_STAT(fec_corrected_errors, FEC_CORRECTED_ERRORS),
1527 EF10_DMA_STAT(fec_corrected_symbols_lane0, FEC_CORRECTED_SYMBOLS_LANE0),
1528 EF10_DMA_STAT(fec_corrected_symbols_lane1, FEC_CORRECTED_SYMBOLS_LANE1),
1529 EF10_DMA_STAT(fec_corrected_symbols_lane2, FEC_CORRECTED_SYMBOLS_LANE2),
1530 EF10_DMA_STAT(fec_corrected_symbols_lane3, FEC_CORRECTED_SYMBOLS_LANE3),
1531 EF10_DMA_STAT(ctpio_vi_busy_fallback, CTPIO_VI_BUSY_FALLBACK),
1532 EF10_DMA_STAT(ctpio_long_write_success, CTPIO_LONG_WRITE_SUCCESS),
1533 EF10_DMA_STAT(ctpio_missing_dbell_fail, CTPIO_MISSING_DBELL_FAIL),
1534 EF10_DMA_STAT(ctpio_overflow_fail, CTPIO_OVERFLOW_FAIL),
1535 EF10_DMA_STAT(ctpio_underflow_fail, CTPIO_UNDERFLOW_FAIL),
1536 EF10_DMA_STAT(ctpio_timeout_fail, CTPIO_TIMEOUT_FAIL),
1537 EF10_DMA_STAT(ctpio_noncontig_wr_fail, CTPIO_NONCONTIG_WR_FAIL),
1538 EF10_DMA_STAT(ctpio_frm_clobber_fail, CTPIO_FRM_CLOBBER_FAIL),
1539 EF10_DMA_STAT(ctpio_invalid_wr_fail, CTPIO_INVALID_WR_FAIL),
1540 EF10_DMA_STAT(ctpio_vi_clobber_fallback, CTPIO_VI_CLOBBER_FALLBACK),
1541 EF10_DMA_STAT(ctpio_unqualified_fallback, CTPIO_UNQUALIFIED_FALLBACK),
1542 EF10_DMA_STAT(ctpio_runt_fallback, CTPIO_RUNT_FALLBACK),
1543 EF10_DMA_STAT(ctpio_success, CTPIO_SUCCESS),
1544 EF10_DMA_STAT(ctpio_fallback, CTPIO_FALLBACK),
1545 EF10_DMA_STAT(ctpio_poison, CTPIO_POISON),
1546 EF10_DMA_STAT(ctpio_erase, CTPIO_ERASE),
1549 #define HUNT_COMMON_STAT_MASK ((1ULL << EF10_STAT_port_tx_bytes) | \
1550 (1ULL << EF10_STAT_port_tx_packets) | \
1551 (1ULL << EF10_STAT_port_tx_pause) | \
1552 (1ULL << EF10_STAT_port_tx_unicast) | \
1553 (1ULL << EF10_STAT_port_tx_multicast) | \
1554 (1ULL << EF10_STAT_port_tx_broadcast) | \
1555 (1ULL << EF10_STAT_port_rx_bytes) | \
1557 EF10_STAT_port_rx_bytes_minus_good_bytes) | \
1558 (1ULL << EF10_STAT_port_rx_good_bytes) | \
1559 (1ULL << EF10_STAT_port_rx_bad_bytes) | \
1560 (1ULL << EF10_STAT_port_rx_packets) | \
1561 (1ULL << EF10_STAT_port_rx_good) | \
1562 (1ULL << EF10_STAT_port_rx_bad) | \
1563 (1ULL << EF10_STAT_port_rx_pause) | \
1564 (1ULL << EF10_STAT_port_rx_control) | \
1565 (1ULL << EF10_STAT_port_rx_unicast) | \
1566 (1ULL << EF10_STAT_port_rx_multicast) | \
1567 (1ULL << EF10_STAT_port_rx_broadcast) | \
1568 (1ULL << EF10_STAT_port_rx_lt64) | \
1569 (1ULL << EF10_STAT_port_rx_64) | \
1570 (1ULL << EF10_STAT_port_rx_65_to_127) | \
1571 (1ULL << EF10_STAT_port_rx_128_to_255) | \
1572 (1ULL << EF10_STAT_port_rx_256_to_511) | \
1573 (1ULL << EF10_STAT_port_rx_512_to_1023) |\
1574 (1ULL << EF10_STAT_port_rx_1024_to_15xx) |\
1575 (1ULL << EF10_STAT_port_rx_15xx_to_jumbo) |\
1576 (1ULL << EF10_STAT_port_rx_gtjumbo) | \
1577 (1ULL << EF10_STAT_port_rx_bad_gtjumbo) |\
1578 (1ULL << EF10_STAT_port_rx_overflow) | \
1579 (1ULL << EF10_STAT_port_rx_nodesc_drops) |\
1580 (1ULL << GENERIC_STAT_rx_nodesc_trunc) | \
1581 (1ULL << GENERIC_STAT_rx_noskb_drops))
1583 /* On 7000 series NICs, these statistics are only provided by the 10G MAC.
1584 * For a 10G/40G switchable port we do not expose these because they might
1585 * not include all the packets they should.
1586 * On 8000 series NICs these statistics are always provided.
1588 #define HUNT_10G_ONLY_STAT_MASK ((1ULL << EF10_STAT_port_tx_control) | \
1589 (1ULL << EF10_STAT_port_tx_lt64) | \
1590 (1ULL << EF10_STAT_port_tx_64) | \
1591 (1ULL << EF10_STAT_port_tx_65_to_127) |\
1592 (1ULL << EF10_STAT_port_tx_128_to_255) |\
1593 (1ULL << EF10_STAT_port_tx_256_to_511) |\
1594 (1ULL << EF10_STAT_port_tx_512_to_1023) |\
1595 (1ULL << EF10_STAT_port_tx_1024_to_15xx) |\
1596 (1ULL << EF10_STAT_port_tx_15xx_to_jumbo))
1598 /* These statistics are only provided by the 40G MAC. For a 10G/40G
1599 * switchable port we do expose these because the errors will otherwise
1602 #define HUNT_40G_EXTRA_STAT_MASK ((1ULL << EF10_STAT_port_rx_align_error) |\
1603 (1ULL << EF10_STAT_port_rx_length_error))
1605 /* These statistics are only provided if the firmware supports the
1606 * capability PM_AND_RXDP_COUNTERS.
1608 #define HUNT_PM_AND_RXDP_STAT_MASK ( \
1609 (1ULL << EF10_STAT_port_rx_pm_trunc_bb_overflow) | \
1610 (1ULL << EF10_STAT_port_rx_pm_discard_bb_overflow) | \
1611 (1ULL << EF10_STAT_port_rx_pm_trunc_vfifo_full) | \
1612 (1ULL << EF10_STAT_port_rx_pm_discard_vfifo_full) | \
1613 (1ULL << EF10_STAT_port_rx_pm_trunc_qbb) | \
1614 (1ULL << EF10_STAT_port_rx_pm_discard_qbb) | \
1615 (1ULL << EF10_STAT_port_rx_pm_discard_mapping) | \
1616 (1ULL << EF10_STAT_port_rx_dp_q_disabled_packets) | \
1617 (1ULL << EF10_STAT_port_rx_dp_di_dropped_packets) | \
1618 (1ULL << EF10_STAT_port_rx_dp_streaming_packets) | \
1619 (1ULL << EF10_STAT_port_rx_dp_hlb_fetch) | \
1620 (1ULL << EF10_STAT_port_rx_dp_hlb_wait))
1622 /* These statistics are only provided if the NIC supports MC_CMD_MAC_STATS_V2,
1623 * indicated by returning a value >= MC_CMD_MAC_NSTATS_V2 in
1624 * MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS.
1625 * These bits are in the second u64 of the raw mask.
1627 #define EF10_FEC_STAT_MASK ( \
1628 (1ULL << (EF10_STAT_fec_uncorrected_errors - 64)) | \
1629 (1ULL << (EF10_STAT_fec_corrected_errors - 64)) | \
1630 (1ULL << (EF10_STAT_fec_corrected_symbols_lane0 - 64)) | \
1631 (1ULL << (EF10_STAT_fec_corrected_symbols_lane1 - 64)) | \
1632 (1ULL << (EF10_STAT_fec_corrected_symbols_lane2 - 64)) | \
1633 (1ULL << (EF10_STAT_fec_corrected_symbols_lane3 - 64)))
1635 /* These statistics are only provided if the NIC supports MC_CMD_MAC_STATS_V3,
1636 * indicated by returning a value >= MC_CMD_MAC_NSTATS_V3 in
1637 * MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS.
1638 * These bits are in the second u64 of the raw mask.
1640 #define EF10_CTPIO_STAT_MASK ( \
1641 (1ULL << (EF10_STAT_ctpio_vi_busy_fallback - 64)) | \
1642 (1ULL << (EF10_STAT_ctpio_long_write_success - 64)) | \
1643 (1ULL << (EF10_STAT_ctpio_missing_dbell_fail - 64)) | \
1644 (1ULL << (EF10_STAT_ctpio_overflow_fail - 64)) | \
1645 (1ULL << (EF10_STAT_ctpio_underflow_fail - 64)) | \
1646 (1ULL << (EF10_STAT_ctpio_timeout_fail - 64)) | \
1647 (1ULL << (EF10_STAT_ctpio_noncontig_wr_fail - 64)) | \
1648 (1ULL << (EF10_STAT_ctpio_frm_clobber_fail - 64)) | \
1649 (1ULL << (EF10_STAT_ctpio_invalid_wr_fail - 64)) | \
1650 (1ULL << (EF10_STAT_ctpio_vi_clobber_fallback - 64)) | \
1651 (1ULL << (EF10_STAT_ctpio_unqualified_fallback - 64)) | \
1652 (1ULL << (EF10_STAT_ctpio_runt_fallback - 64)) | \
1653 (1ULL << (EF10_STAT_ctpio_success - 64)) | \
1654 (1ULL << (EF10_STAT_ctpio_fallback - 64)) | \
1655 (1ULL << (EF10_STAT_ctpio_poison - 64)) | \
1656 (1ULL << (EF10_STAT_ctpio_erase - 64)))
1658 static u64 efx_ef10_raw_stat_mask(struct efx_nic *efx)
1660 u64 raw_mask = HUNT_COMMON_STAT_MASK;
1661 u32 port_caps = efx_mcdi_phy_get_caps(efx);
1662 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1664 if (!(efx->mcdi->fn_flags &
1665 1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL))
1668 if (port_caps & (1 << MC_CMD_PHY_CAP_40000FDX_LBN)) {
1669 raw_mask |= HUNT_40G_EXTRA_STAT_MASK;
1670 /* 8000 series have everything even at 40G */
1671 if (nic_data->datapath_caps2 &
1672 (1 << MC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN))
1673 raw_mask |= HUNT_10G_ONLY_STAT_MASK;
1675 raw_mask |= HUNT_10G_ONLY_STAT_MASK;
1678 if (nic_data->datapath_caps &
1679 (1 << MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN))
1680 raw_mask |= HUNT_PM_AND_RXDP_STAT_MASK;
1685 static void efx_ef10_get_stat_mask(struct efx_nic *efx, unsigned long *mask)
1687 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1690 raw_mask[0] = efx_ef10_raw_stat_mask(efx);
1692 /* Only show vadaptor stats when EVB capability is present */
1693 if (nic_data->datapath_caps &
1694 (1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN)) {
1695 raw_mask[0] |= ~((1ULL << EF10_STAT_rx_unicast) - 1);
1696 raw_mask[1] = (1ULL << (EF10_STAT_V1_COUNT - 64)) - 1;
1700 /* Only show FEC stats when NIC supports MC_CMD_MAC_STATS_V2 */
1701 if (efx->num_mac_stats >= MC_CMD_MAC_NSTATS_V2)
1702 raw_mask[1] |= EF10_FEC_STAT_MASK;
1704 /* CTPIO stats appear in V3. Only show them on devices that actually
1705 * support CTPIO. Although this driver doesn't use CTPIO others might,
1706 * and we may be reporting the stats for the underlying port.
1708 if (efx->num_mac_stats >= MC_CMD_MAC_NSTATS_V3 &&
1709 (nic_data->datapath_caps2 &
1710 (1 << MC_CMD_GET_CAPABILITIES_V4_OUT_CTPIO_LBN)))
1711 raw_mask[1] |= EF10_CTPIO_STAT_MASK;
1713 #if BITS_PER_LONG == 64
1714 BUILD_BUG_ON(BITS_TO_LONGS(EF10_STAT_COUNT) != 2);
1715 mask[0] = raw_mask[0];
1716 mask[1] = raw_mask[1];
1718 BUILD_BUG_ON(BITS_TO_LONGS(EF10_STAT_COUNT) != 3);
1719 mask[0] = raw_mask[0] & 0xffffffff;
1720 mask[1] = raw_mask[0] >> 32;
1721 mask[2] = raw_mask[1] & 0xffffffff;
1725 static size_t efx_ef10_describe_stats(struct efx_nic *efx, u8 *names)
1727 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1729 efx_ef10_get_stat_mask(efx, mask);
1730 return efx_nic_describe_stats(efx_ef10_stat_desc, EF10_STAT_COUNT,
1734 static size_t efx_ef10_update_stats_common(struct efx_nic *efx, u64 *full_stats,
1735 struct rtnl_link_stats64 *core_stats)
1737 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1738 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1739 u64 *stats = nic_data->stats;
1740 size_t stats_count = 0, index;
1742 efx_ef10_get_stat_mask(efx, mask);
1745 for_each_set_bit(index, mask, EF10_STAT_COUNT) {
1746 if (efx_ef10_stat_desc[index].name) {
1747 *full_stats++ = stats[index];
1756 if (nic_data->datapath_caps &
1757 1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN) {
1758 /* Use vadaptor stats. */
1759 core_stats->rx_packets = stats[EF10_STAT_rx_unicast] +
1760 stats[EF10_STAT_rx_multicast] +
1761 stats[EF10_STAT_rx_broadcast];
1762 core_stats->tx_packets = stats[EF10_STAT_tx_unicast] +
1763 stats[EF10_STAT_tx_multicast] +
1764 stats[EF10_STAT_tx_broadcast];
1765 core_stats->rx_bytes = stats[EF10_STAT_rx_unicast_bytes] +
1766 stats[EF10_STAT_rx_multicast_bytes] +
1767 stats[EF10_STAT_rx_broadcast_bytes];
1768 core_stats->tx_bytes = stats[EF10_STAT_tx_unicast_bytes] +
1769 stats[EF10_STAT_tx_multicast_bytes] +
1770 stats[EF10_STAT_tx_broadcast_bytes];
1771 core_stats->rx_dropped = stats[GENERIC_STAT_rx_nodesc_trunc] +
1772 stats[GENERIC_STAT_rx_noskb_drops];
1773 core_stats->multicast = stats[EF10_STAT_rx_multicast];
1774 core_stats->rx_crc_errors = stats[EF10_STAT_rx_bad];
1775 core_stats->rx_fifo_errors = stats[EF10_STAT_rx_overflow];
1776 core_stats->rx_errors = core_stats->rx_crc_errors;
1777 core_stats->tx_errors = stats[EF10_STAT_tx_bad];
1779 /* Use port stats. */
1780 core_stats->rx_packets = stats[EF10_STAT_port_rx_packets];
1781 core_stats->tx_packets = stats[EF10_STAT_port_tx_packets];
1782 core_stats->rx_bytes = stats[EF10_STAT_port_rx_bytes];
1783 core_stats->tx_bytes = stats[EF10_STAT_port_tx_bytes];
1784 core_stats->rx_dropped = stats[EF10_STAT_port_rx_nodesc_drops] +
1785 stats[GENERIC_STAT_rx_nodesc_trunc] +
1786 stats[GENERIC_STAT_rx_noskb_drops];
1787 core_stats->multicast = stats[EF10_STAT_port_rx_multicast];
1788 core_stats->rx_length_errors =
1789 stats[EF10_STAT_port_rx_gtjumbo] +
1790 stats[EF10_STAT_port_rx_length_error];
1791 core_stats->rx_crc_errors = stats[EF10_STAT_port_rx_bad];
1792 core_stats->rx_frame_errors =
1793 stats[EF10_STAT_port_rx_align_error];
1794 core_stats->rx_fifo_errors = stats[EF10_STAT_port_rx_overflow];
1795 core_stats->rx_errors = (core_stats->rx_length_errors +
1796 core_stats->rx_crc_errors +
1797 core_stats->rx_frame_errors);
1803 static size_t efx_ef10_update_stats_pf(struct efx_nic *efx, u64 *full_stats,
1804 struct rtnl_link_stats64 *core_stats)
1806 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1807 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1808 u64 *stats = nic_data->stats;
1810 efx_ef10_get_stat_mask(efx, mask);
1812 efx_nic_copy_stats(efx, nic_data->mc_stats);
1813 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT,
1814 mask, stats, nic_data->mc_stats, false);
1816 /* Update derived statistics */
1817 efx_nic_fix_nodesc_drop_stat(efx,
1818 &stats[EF10_STAT_port_rx_nodesc_drops]);
1819 /* MC Firmware reads RX_BYTES and RX_GOOD_BYTES from the MAC.
1820 * It then calculates RX_BAD_BYTES and DMAs it to us with RX_BYTES.
1821 * We report these as port_rx_ stats. We are not given RX_GOOD_BYTES.
1822 * Here we calculate port_rx_good_bytes.
1824 stats[EF10_STAT_port_rx_good_bytes] =
1825 stats[EF10_STAT_port_rx_bytes] -
1826 stats[EF10_STAT_port_rx_bytes_minus_good_bytes];
1828 /* The asynchronous reads used to calculate RX_BAD_BYTES in
1829 * MC Firmware are done such that we should not see an increase in
1830 * RX_BAD_BYTES when a good packet has arrived. Unfortunately this
1831 * does mean that the stat can decrease at times. Here we do not
1832 * update the stat unless it has increased or has gone to zero
1833 * (In the case of the NIC rebooting).
1834 * Please see Bug 33781 for a discussion of why things work this way.
1836 efx_update_diff_stat(&stats[EF10_STAT_port_rx_bad_bytes],
1837 stats[EF10_STAT_port_rx_bytes_minus_good_bytes]);
1838 efx_update_sw_stats(efx, stats);
1840 return efx_ef10_update_stats_common(efx, full_stats, core_stats);
1843 static int efx_ef10_try_update_nic_stats_vf(struct efx_nic *efx)
1844 __must_hold(&efx->stats_lock)
1846 MCDI_DECLARE_BUF(inbuf, MC_CMD_MAC_STATS_IN_LEN);
1847 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1848 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1849 __le64 generation_start, generation_end;
1850 u64 *stats = nic_data->stats;
1851 u32 dma_len = efx->num_mac_stats * sizeof(u64);
1852 struct efx_buffer stats_buf;
1856 spin_unlock_bh(&efx->stats_lock);
1858 if (in_interrupt()) {
1859 /* If in atomic context, cannot update stats. Just update the
1860 * software stats and return so the caller can continue.
1862 spin_lock_bh(&efx->stats_lock);
1863 efx_update_sw_stats(efx, stats);
1867 efx_ef10_get_stat_mask(efx, mask);
1869 rc = efx_nic_alloc_buffer(efx, &stats_buf, dma_len, GFP_ATOMIC);
1871 spin_lock_bh(&efx->stats_lock);
1875 dma_stats = stats_buf.addr;
1876 dma_stats[efx->num_mac_stats - 1] = EFX_MC_STATS_GENERATION_INVALID;
1878 MCDI_SET_QWORD(inbuf, MAC_STATS_IN_DMA_ADDR, stats_buf.dma_addr);
1879 MCDI_POPULATE_DWORD_1(inbuf, MAC_STATS_IN_CMD,
1880 MAC_STATS_IN_DMA, 1);
1881 MCDI_SET_DWORD(inbuf, MAC_STATS_IN_DMA_LEN, dma_len);
1882 MCDI_SET_DWORD(inbuf, MAC_STATS_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
1884 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_MAC_STATS, inbuf, sizeof(inbuf),
1886 spin_lock_bh(&efx->stats_lock);
1888 /* Expect ENOENT if DMA queues have not been set up */
1889 if (rc != -ENOENT || atomic_read(&efx->active_queues))
1890 efx_mcdi_display_error(efx, MC_CMD_MAC_STATS,
1891 sizeof(inbuf), NULL, 0, rc);
1895 generation_end = dma_stats[efx->num_mac_stats - 1];
1896 if (generation_end == EFX_MC_STATS_GENERATION_INVALID) {
1901 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask,
1902 stats, stats_buf.addr, false);
1904 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
1905 if (generation_end != generation_start) {
1910 efx_update_sw_stats(efx, stats);
1912 efx_nic_free_buffer(efx, &stats_buf);
1916 static size_t efx_ef10_update_stats_vf(struct efx_nic *efx, u64 *full_stats,
1917 struct rtnl_link_stats64 *core_stats)
1919 if (efx_ef10_try_update_nic_stats_vf(efx))
1922 return efx_ef10_update_stats_common(efx, full_stats, core_stats);
1925 static void efx_ef10_push_irq_moderation(struct efx_channel *channel)
1927 struct efx_nic *efx = channel->efx;
1928 unsigned int mode, usecs;
1929 efx_dword_t timer_cmd;
1931 if (channel->irq_moderation_us) {
1933 usecs = channel->irq_moderation_us;
1939 if (EFX_EF10_WORKAROUND_61265(efx)) {
1940 MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_EVQ_TMR_IN_LEN);
1941 unsigned int ns = usecs * 1000;
1943 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_INSTANCE,
1945 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_LOAD_REQ_NS, ns);
1946 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_RELOAD_REQ_NS, ns);
1947 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_MODE, mode);
1949 efx_mcdi_rpc_async(efx, MC_CMD_SET_EVQ_TMR,
1950 inbuf, sizeof(inbuf), 0, NULL, 0);
1951 } else if (EFX_EF10_WORKAROUND_35388(efx)) {
1952 unsigned int ticks = efx_usecs_to_ticks(efx, usecs);
1954 EFX_POPULATE_DWORD_3(timer_cmd, ERF_DD_EVQ_IND_TIMER_FLAGS,
1955 EFE_DD_EVQ_IND_TIMER_FLAGS,
1956 ERF_DD_EVQ_IND_TIMER_MODE, mode,
1957 ERF_DD_EVQ_IND_TIMER_VAL, ticks);
1958 efx_writed_page(efx, &timer_cmd, ER_DD_EVQ_INDIRECT,
1961 unsigned int ticks = efx_usecs_to_ticks(efx, usecs);
1963 EFX_POPULATE_DWORD_3(timer_cmd, ERF_DZ_TC_TIMER_MODE, mode,
1964 ERF_DZ_TC_TIMER_VAL, ticks,
1965 ERF_FZ_TC_TMR_REL_VAL, ticks);
1966 efx_writed_page(efx, &timer_cmd, ER_DZ_EVQ_TMR,
1971 static void efx_ef10_get_wol_vf(struct efx_nic *efx,
1972 struct ethtool_wolinfo *wol) {}
1974 static int efx_ef10_set_wol_vf(struct efx_nic *efx, u32 type)
1979 static void efx_ef10_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
1983 memset(&wol->sopass, 0, sizeof(wol->sopass));
1986 static int efx_ef10_set_wol(struct efx_nic *efx, u32 type)
1993 static void efx_ef10_mcdi_request(struct efx_nic *efx,
1994 const efx_dword_t *hdr, size_t hdr_len,
1995 const efx_dword_t *sdu, size_t sdu_len)
1997 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1998 u8 *pdu = nic_data->mcdi_buf.addr;
2000 memcpy(pdu, hdr, hdr_len);
2001 memcpy(pdu + hdr_len, sdu, sdu_len);
2004 /* The hardware provides 'low' and 'high' (doorbell) registers
2005 * for passing the 64-bit address of an MCDI request to
2006 * firmware. However the dwords are swapped by firmware. The
2007 * least significant bits of the doorbell are then 0 for all
2008 * MCDI requests due to alignment.
2010 _efx_writed(efx, cpu_to_le32((u64)nic_data->mcdi_buf.dma_addr >> 32),
2012 _efx_writed(efx, cpu_to_le32((u32)nic_data->mcdi_buf.dma_addr),
2016 static bool efx_ef10_mcdi_poll_response(struct efx_nic *efx)
2018 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2019 const efx_dword_t hdr = *(const efx_dword_t *)nic_data->mcdi_buf.addr;
2022 return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE);
2026 efx_ef10_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf,
2027 size_t offset, size_t outlen)
2029 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2030 const u8 *pdu = nic_data->mcdi_buf.addr;
2032 memcpy(outbuf, pdu + offset, outlen);
2035 static void efx_ef10_mcdi_reboot_detected(struct efx_nic *efx)
2037 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2039 /* All our allocations have been reset */
2040 efx_ef10_table_reset_mc_allocations(efx);
2042 /* The datapath firmware might have been changed */
2043 nic_data->must_check_datapath_caps = true;
2045 /* MAC statistics have been cleared on the NIC; clear the local
2046 * statistic that we update with efx_update_diff_stat().
2048 nic_data->stats[EF10_STAT_port_rx_bad_bytes] = 0;
2051 static int efx_ef10_mcdi_poll_reboot(struct efx_nic *efx)
2053 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2056 rc = efx_ef10_get_warm_boot_count(efx);
2058 /* The firmware is presumably in the process of
2059 * rebooting. However, we are supposed to report each
2060 * reboot just once, so we must only do that once we
2061 * can read and store the updated warm boot count.
2066 if (rc == nic_data->warm_boot_count)
2069 nic_data->warm_boot_count = rc;
2070 efx_ef10_mcdi_reboot_detected(efx);
2075 /* Handle an MSI interrupt
2077 * Handle an MSI hardware interrupt. This routine schedules event
2078 * queue processing. No interrupt acknowledgement cycle is necessary.
2079 * Also, we never need to check that the interrupt is for us, since
2080 * MSI interrupts cannot be shared.
2082 static irqreturn_t efx_ef10_msi_interrupt(int irq, void *dev_id)
2084 struct efx_msi_context *context = dev_id;
2085 struct efx_nic *efx = context->efx;
2087 netif_vdbg(efx, intr, efx->net_dev,
2088 "IRQ %d on CPU %d\n", irq, raw_smp_processor_id());
2090 if (likely(READ_ONCE(efx->irq_soft_enabled))) {
2091 /* Note test interrupts */
2092 if (context->index == efx->irq_level)
2093 efx->last_irq_cpu = raw_smp_processor_id();
2095 /* Schedule processing of the channel */
2096 efx_schedule_channel_irq(efx->channel[context->index]);
2102 static irqreturn_t efx_ef10_legacy_interrupt(int irq, void *dev_id)
2104 struct efx_nic *efx = dev_id;
2105 bool soft_enabled = READ_ONCE(efx->irq_soft_enabled);
2106 struct efx_channel *channel;
2110 /* Read the ISR which also ACKs the interrupts */
2111 efx_readd(efx, ®, ER_DZ_BIU_INT_ISR);
2112 queues = EFX_DWORD_FIELD(reg, ERF_DZ_ISR_REG);
2117 if (likely(soft_enabled)) {
2118 /* Note test interrupts */
2119 if (queues & (1U << efx->irq_level))
2120 efx->last_irq_cpu = raw_smp_processor_id();
2122 efx_for_each_channel(channel, efx) {
2124 efx_schedule_channel_irq(channel);
2129 netif_vdbg(efx, intr, efx->net_dev,
2130 "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
2131 irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
2136 static int efx_ef10_irq_test_generate(struct efx_nic *efx)
2138 MCDI_DECLARE_BUF(inbuf, MC_CMD_TRIGGER_INTERRUPT_IN_LEN);
2140 if (efx_mcdi_set_workaround(efx, MC_CMD_WORKAROUND_BUG41750, true,
2144 BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN != 0);
2146 MCDI_SET_DWORD(inbuf, TRIGGER_INTERRUPT_IN_INTR_LEVEL, efx->irq_level);
2147 return efx_mcdi_rpc(efx, MC_CMD_TRIGGER_INTERRUPT,
2148 inbuf, sizeof(inbuf), NULL, 0, NULL);
2151 static int efx_ef10_tx_probe(struct efx_tx_queue *tx_queue)
2153 /* low two bits of label are what we want for type */
2154 BUILD_BUG_ON((EFX_TXQ_TYPE_OUTER_CSUM | EFX_TXQ_TYPE_INNER_CSUM) != 3);
2155 tx_queue->type = tx_queue->label & 3;
2156 return efx_nic_alloc_buffer(tx_queue->efx, &tx_queue->txd.buf,
2157 (tx_queue->ptr_mask + 1) *
2158 sizeof(efx_qword_t),
2162 /* This writes to the TX_DESC_WPTR and also pushes data */
2163 static inline void efx_ef10_push_tx_desc(struct efx_tx_queue *tx_queue,
2164 const efx_qword_t *txd)
2166 unsigned int write_ptr;
2169 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
2170 EFX_POPULATE_OWORD_1(reg, ERF_DZ_TX_DESC_WPTR, write_ptr);
2171 reg.qword[0] = *txd;
2172 efx_writeo_page(tx_queue->efx, ®,
2173 ER_DZ_TX_DESC_UPD, tx_queue->queue);
2176 /* Add Firmware-Assisted TSO v2 option descriptors to a queue.
2178 static int efx_ef10_tx_tso_desc(struct efx_tx_queue *tx_queue,
2179 struct sk_buff *skb,
2182 struct efx_tx_buffer *buffer;
2190 EFX_WARN_ON_ONCE_PARANOID(tx_queue->tso_version != 2);
2192 mss = skb_shinfo(skb)->gso_size;
2194 if (unlikely(mss < 4)) {
2195 WARN_ONCE(1, "MSS of %u is too small for TSO v2\n", mss);
2200 if (ip->version == 4) {
2201 /* Modify IPv4 header if needed. */
2204 ipv4_id = ntohs(ip->id);
2206 /* Modify IPv6 header if needed. */
2207 struct ipv6hdr *ipv6 = ipv6_hdr(skb);
2209 ipv6->payload_len = 0;
2214 seqnum = ntohl(tcp->seq);
2216 buffer = efx_tx_queue_get_insert_buffer(tx_queue);
2218 buffer->flags = EFX_TX_BUF_OPTION;
2220 buffer->unmap_len = 0;
2221 EFX_POPULATE_QWORD_5(buffer->option,
2222 ESF_DZ_TX_DESC_IS_OPT, 1,
2223 ESF_DZ_TX_OPTION_TYPE, ESE_DZ_TX_OPTION_DESC_TSO,
2224 ESF_DZ_TX_TSO_OPTION_TYPE,
2225 ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A,
2226 ESF_DZ_TX_TSO_IP_ID, ipv4_id,
2227 ESF_DZ_TX_TSO_TCP_SEQNO, seqnum
2229 ++tx_queue->insert_count;
2231 buffer = efx_tx_queue_get_insert_buffer(tx_queue);
2233 buffer->flags = EFX_TX_BUF_OPTION;
2235 buffer->unmap_len = 0;
2236 EFX_POPULATE_QWORD_4(buffer->option,
2237 ESF_DZ_TX_DESC_IS_OPT, 1,
2238 ESF_DZ_TX_OPTION_TYPE, ESE_DZ_TX_OPTION_DESC_TSO,
2239 ESF_DZ_TX_TSO_OPTION_TYPE,
2240 ESE_DZ_TX_TSO_OPTION_DESC_FATSO2B,
2241 ESF_DZ_TX_TSO_TCP_MSS, mss
2243 ++tx_queue->insert_count;
2248 static u32 efx_ef10_tso_versions(struct efx_nic *efx)
2250 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2251 u32 tso_versions = 0;
2253 if (nic_data->datapath_caps &
2254 (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN))
2255 tso_versions |= BIT(1);
2256 if (nic_data->datapath_caps2 &
2257 (1 << MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_LBN))
2258 tso_versions |= BIT(2);
2259 return tso_versions;
2262 static void efx_ef10_tx_init(struct efx_tx_queue *tx_queue)
2264 bool csum_offload = tx_queue->type & EFX_TXQ_TYPE_OUTER_CSUM;
2265 bool inner_csum = tx_queue->type & EFX_TXQ_TYPE_INNER_CSUM;
2266 struct efx_channel *channel = tx_queue->channel;
2267 struct efx_nic *efx = tx_queue->efx;
2268 struct efx_ef10_nic_data *nic_data;
2269 bool tso_v2 = false;
2273 nic_data = efx->nic_data;
2275 /* Only attempt to enable TX timestamping if we have the license for it,
2276 * otherwise TXQ init will fail
2278 if (!(nic_data->licensed_features &
2279 (1 << LICENSED_V3_FEATURES_TX_TIMESTAMPS_LBN))) {
2280 tx_queue->timestamping = false;
2281 /* Disable sync events on this channel. */
2282 if (efx->type->ptp_set_ts_sync_events)
2283 efx->type->ptp_set_ts_sync_events(efx, false, false);
2286 /* TSOv2 is a limited resource that can only be configured on a limited
2287 * number of queues. TSO without checksum offload is not really a thing,
2288 * so we only enable it for those queues.
2289 * TSOv2 cannot be used with Hardware timestamping, and is never needed
2292 if ((csum_offload || inner_csum) && (nic_data->datapath_caps2 &
2293 (1 << MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_LBN)) &&
2294 !tx_queue->timestamping && !tx_queue->xdp_tx) {
2296 netif_dbg(efx, hw, efx->net_dev, "Using TSOv2 for channel %u\n",
2300 rc = efx_mcdi_tx_init(tx_queue, tso_v2);
2304 /* A previous user of this TX queue might have set us up the
2305 * bomb by writing a descriptor to the TX push collector but
2306 * not the doorbell. (Each collector belongs to a port, not a
2307 * queue or function, so cannot easily be reset.) We must
2308 * attempt to push a no-op descriptor in its place.
2310 tx_queue->buffer[0].flags = EFX_TX_BUF_OPTION;
2311 tx_queue->insert_count = 1;
2312 txd = efx_tx_desc(tx_queue, 0);
2313 EFX_POPULATE_QWORD_7(*txd,
2314 ESF_DZ_TX_DESC_IS_OPT, true,
2315 ESF_DZ_TX_OPTION_TYPE,
2316 ESE_DZ_TX_OPTION_DESC_CRC_CSUM,
2317 ESF_DZ_TX_OPTION_UDP_TCP_CSUM, csum_offload,
2318 ESF_DZ_TX_OPTION_IP_CSUM, csum_offload && !tso_v2,
2319 ESF_DZ_TX_OPTION_INNER_UDP_TCP_CSUM, inner_csum,
2320 ESF_DZ_TX_OPTION_INNER_IP_CSUM, inner_csum && !tso_v2,
2321 ESF_DZ_TX_TIMESTAMP, tx_queue->timestamping);
2322 tx_queue->write_count = 1;
2325 tx_queue->handle_tso = efx_ef10_tx_tso_desc;
2326 tx_queue->tso_version = 2;
2327 } else if (nic_data->datapath_caps &
2328 (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN)) {
2329 tx_queue->tso_version = 1;
2333 efx_ef10_push_tx_desc(tx_queue, txd);
2338 netdev_WARN(efx->net_dev, "failed to initialise TXQ %d\n",
2342 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
2343 static inline void efx_ef10_notify_tx_desc(struct efx_tx_queue *tx_queue)
2345 unsigned int write_ptr;
2348 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
2349 EFX_POPULATE_DWORD_1(reg, ERF_DZ_TX_DESC_WPTR_DWORD, write_ptr);
2350 efx_writed_page(tx_queue->efx, ®,
2351 ER_DZ_TX_DESC_UPD_DWORD, tx_queue->queue);
2354 #define EFX_EF10_MAX_TX_DESCRIPTOR_LEN 0x3fff
2356 static unsigned int efx_ef10_tx_limit_len(struct efx_tx_queue *tx_queue,
2357 dma_addr_t dma_addr, unsigned int len)
2359 if (len > EFX_EF10_MAX_TX_DESCRIPTOR_LEN) {
2360 /* If we need to break across multiple descriptors we should
2361 * stop at a page boundary. This assumes the length limit is
2362 * greater than the page size.
2364 dma_addr_t end = dma_addr + EFX_EF10_MAX_TX_DESCRIPTOR_LEN;
2366 BUILD_BUG_ON(EFX_EF10_MAX_TX_DESCRIPTOR_LEN < EFX_PAGE_SIZE);
2367 len = (end & (~(EFX_PAGE_SIZE - 1))) - dma_addr;
2373 static void efx_ef10_tx_write(struct efx_tx_queue *tx_queue)
2375 unsigned int old_write_count = tx_queue->write_count;
2376 struct efx_tx_buffer *buffer;
2377 unsigned int write_ptr;
2380 tx_queue->xmit_pending = false;
2381 if (unlikely(tx_queue->write_count == tx_queue->insert_count))
2385 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
2386 buffer = &tx_queue->buffer[write_ptr];
2387 txd = efx_tx_desc(tx_queue, write_ptr);
2388 ++tx_queue->write_count;
2390 /* Create TX descriptor ring entry */
2391 if (buffer->flags & EFX_TX_BUF_OPTION) {
2392 *txd = buffer->option;
2393 if (EFX_QWORD_FIELD(*txd, ESF_DZ_TX_OPTION_TYPE) == 1)
2394 /* PIO descriptor */
2395 tx_queue->packet_write_count = tx_queue->write_count;
2397 tx_queue->packet_write_count = tx_queue->write_count;
2398 BUILD_BUG_ON(EFX_TX_BUF_CONT != 1);
2399 EFX_POPULATE_QWORD_3(
2402 buffer->flags & EFX_TX_BUF_CONT,
2403 ESF_DZ_TX_KER_BYTE_CNT, buffer->len,
2404 ESF_DZ_TX_KER_BUF_ADDR, buffer->dma_addr);
2406 } while (tx_queue->write_count != tx_queue->insert_count);
2408 wmb(); /* Ensure descriptors are written before they are fetched */
2410 if (efx_nic_may_push_tx_desc(tx_queue, old_write_count)) {
2411 txd = efx_tx_desc(tx_queue,
2412 old_write_count & tx_queue->ptr_mask);
2413 efx_ef10_push_tx_desc(tx_queue, txd);
2416 efx_ef10_notify_tx_desc(tx_queue);
2420 static int efx_ef10_probe_multicast_chaining(struct efx_nic *efx)
2422 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2423 unsigned int enabled, implemented;
2424 bool want_workaround_26807;
2427 rc = efx_mcdi_get_workarounds(efx, &implemented, &enabled);
2428 if (rc == -ENOSYS) {
2429 /* GET_WORKAROUNDS was implemented before this workaround,
2430 * thus it must be unavailable in this firmware.
2432 nic_data->workaround_26807 = false;
2437 want_workaround_26807 =
2438 implemented & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807;
2439 nic_data->workaround_26807 =
2440 !!(enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807);
2442 if (want_workaround_26807 && !nic_data->workaround_26807) {
2445 rc = efx_mcdi_set_workaround(efx,
2446 MC_CMD_WORKAROUND_BUG26807,
2450 1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN) {
2451 netif_info(efx, drv, efx->net_dev,
2452 "other functions on NIC have been reset\n");
2454 /* With MCFW v4.6.x and earlier, the
2455 * boot count will have incremented,
2456 * so re-read the warm_boot_count
2457 * value now to ensure this function
2458 * doesn't think it has changed next
2461 rc = efx_ef10_get_warm_boot_count(efx);
2463 nic_data->warm_boot_count = rc;
2467 nic_data->workaround_26807 = true;
2468 } else if (rc == -EPERM) {
2475 static int efx_ef10_filter_table_probe(struct efx_nic *efx)
2477 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2478 int rc = efx_ef10_probe_multicast_chaining(efx);
2479 struct efx_mcdi_filter_vlan *vlan;
2483 rc = efx_mcdi_filter_table_probe(efx, nic_data->workaround_26807);
2488 list_for_each_entry(vlan, &nic_data->vlan_list, list) {
2489 rc = efx_mcdi_filter_add_vlan(efx, vlan->vid);
2496 efx_mcdi_filter_table_remove(efx);
2500 /* This creates an entry in the RX descriptor queue */
2502 efx_ef10_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index)
2504 struct efx_rx_buffer *rx_buf;
2507 rxd = efx_rx_desc(rx_queue, index);
2508 rx_buf = efx_rx_buffer(rx_queue, index);
2509 EFX_POPULATE_QWORD_2(*rxd,
2510 ESF_DZ_RX_KER_BYTE_CNT, rx_buf->len,
2511 ESF_DZ_RX_KER_BUF_ADDR, rx_buf->dma_addr);
2514 static void efx_ef10_rx_write(struct efx_rx_queue *rx_queue)
2516 struct efx_nic *efx = rx_queue->efx;
2517 unsigned int write_count;
2520 /* Firmware requires that RX_DESC_WPTR be a multiple of 8 */
2521 write_count = rx_queue->added_count & ~7;
2522 if (rx_queue->notified_count == write_count)
2526 efx_ef10_build_rx_desc(
2528 rx_queue->notified_count & rx_queue->ptr_mask);
2529 while (++rx_queue->notified_count != write_count);
2532 EFX_POPULATE_DWORD_1(reg, ERF_DZ_RX_DESC_WPTR,
2533 write_count & rx_queue->ptr_mask);
2534 efx_writed_page(efx, ®, ER_DZ_RX_DESC_UPD,
2535 efx_rx_queue_index(rx_queue));
2538 static efx_mcdi_async_completer efx_ef10_rx_defer_refill_complete;
2540 static void efx_ef10_rx_defer_refill(struct efx_rx_queue *rx_queue)
2542 struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
2543 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
2546 EFX_POPULATE_QWORD_2(event,
2547 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
2548 ESF_DZ_EV_DATA, EFX_EF10_REFILL);
2550 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
2552 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
2553 * already swapped the data to little-endian order.
2555 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
2556 sizeof(efx_qword_t));
2558 efx_mcdi_rpc_async(channel->efx, MC_CMD_DRIVER_EVENT,
2559 inbuf, sizeof(inbuf), 0,
2560 efx_ef10_rx_defer_refill_complete, 0);
2564 efx_ef10_rx_defer_refill_complete(struct efx_nic *efx, unsigned long cookie,
2565 int rc, efx_dword_t *outbuf,
2566 size_t outlen_actual)
2571 static int efx_ef10_ev_init(struct efx_channel *channel)
2573 struct efx_nic *efx = channel->efx;
2574 struct efx_ef10_nic_data *nic_data;
2575 bool use_v2, cut_thru;
2577 nic_data = efx->nic_data;
2578 use_v2 = nic_data->datapath_caps2 &
2579 1 << MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_LBN;
2580 cut_thru = !(nic_data->datapath_caps &
2581 1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN);
2582 return efx_mcdi_ev_init(channel, cut_thru, use_v2);
2585 static void efx_ef10_handle_rx_wrong_queue(struct efx_rx_queue *rx_queue,
2586 unsigned int rx_queue_label)
2588 struct efx_nic *efx = rx_queue->efx;
2590 netif_info(efx, hw, efx->net_dev,
2591 "rx event arrived on queue %d labeled as queue %u\n",
2592 efx_rx_queue_index(rx_queue), rx_queue_label);
2594 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
2598 efx_ef10_handle_rx_bad_lbits(struct efx_rx_queue *rx_queue,
2599 unsigned int actual, unsigned int expected)
2601 unsigned int dropped = (actual - expected) & rx_queue->ptr_mask;
2602 struct efx_nic *efx = rx_queue->efx;
2604 netif_info(efx, hw, efx->net_dev,
2605 "dropped %d events (index=%d expected=%d)\n",
2606 dropped, actual, expected);
2608 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
2611 /* partially received RX was aborted. clean up. */
2612 static void efx_ef10_handle_rx_abort(struct efx_rx_queue *rx_queue)
2614 unsigned int rx_desc_ptr;
2616 netif_dbg(rx_queue->efx, hw, rx_queue->efx->net_dev,
2617 "scattered RX aborted (dropping %u buffers)\n",
2618 rx_queue->scatter_n);
2620 rx_desc_ptr = rx_queue->removed_count & rx_queue->ptr_mask;
2622 efx_rx_packet(rx_queue, rx_desc_ptr, rx_queue->scatter_n,
2623 0, EFX_RX_PKT_DISCARD);
2625 rx_queue->removed_count += rx_queue->scatter_n;
2626 rx_queue->scatter_n = 0;
2627 rx_queue->scatter_len = 0;
2628 ++efx_rx_queue_channel(rx_queue)->n_rx_nodesc_trunc;
2631 static u16 efx_ef10_handle_rx_event_errors(struct efx_channel *channel,
2632 unsigned int n_packets,
2633 unsigned int rx_encap_hdr,
2634 unsigned int rx_l3_class,
2635 unsigned int rx_l4_class,
2636 const efx_qword_t *event)
2638 struct efx_nic *efx = channel->efx;
2639 bool handled = false;
2641 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_ECRC_ERR)) {
2642 if (!(efx->net_dev->features & NETIF_F_RXALL)) {
2643 if (!efx->loopback_selftest)
2644 channel->n_rx_eth_crc_err += n_packets;
2645 return EFX_RX_PKT_DISCARD;
2649 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_IPCKSUM_ERR)) {
2650 if (unlikely(rx_encap_hdr != ESE_EZ_ENCAP_HDR_VXLAN &&
2651 rx_l3_class != ESE_DZ_L3_CLASS_IP4 &&
2652 rx_l3_class != ESE_DZ_L3_CLASS_IP4_FRAG &&
2653 rx_l3_class != ESE_DZ_L3_CLASS_IP6 &&
2654 rx_l3_class != ESE_DZ_L3_CLASS_IP6_FRAG))
2655 netdev_WARN(efx->net_dev,
2656 "invalid class for RX_IPCKSUM_ERR: event="
2658 EFX_QWORD_VAL(*event));
2659 if (!efx->loopback_selftest)
2661 &channel->n_rx_outer_ip_hdr_chksum_err :
2662 &channel->n_rx_ip_hdr_chksum_err) += n_packets;
2665 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_TCPUDP_CKSUM_ERR)) {
2666 if (unlikely(rx_encap_hdr != ESE_EZ_ENCAP_HDR_VXLAN &&
2667 ((rx_l3_class != ESE_DZ_L3_CLASS_IP4 &&
2668 rx_l3_class != ESE_DZ_L3_CLASS_IP6) ||
2669 (rx_l4_class != ESE_FZ_L4_CLASS_TCP &&
2670 rx_l4_class != ESE_FZ_L4_CLASS_UDP))))
2671 netdev_WARN(efx->net_dev,
2672 "invalid class for RX_TCPUDP_CKSUM_ERR: event="
2674 EFX_QWORD_VAL(*event));
2675 if (!efx->loopback_selftest)
2677 &channel->n_rx_outer_tcp_udp_chksum_err :
2678 &channel->n_rx_tcp_udp_chksum_err) += n_packets;
2681 if (EFX_QWORD_FIELD(*event, ESF_EZ_RX_IP_INNER_CHKSUM_ERR)) {
2682 if (unlikely(!rx_encap_hdr))
2683 netdev_WARN(efx->net_dev,
2684 "invalid encapsulation type for RX_IP_INNER_CHKSUM_ERR: event="
2686 EFX_QWORD_VAL(*event));
2687 else if (unlikely(rx_l3_class != ESE_DZ_L3_CLASS_IP4 &&
2688 rx_l3_class != ESE_DZ_L3_CLASS_IP4_FRAG &&
2689 rx_l3_class != ESE_DZ_L3_CLASS_IP6 &&
2690 rx_l3_class != ESE_DZ_L3_CLASS_IP6_FRAG))
2691 netdev_WARN(efx->net_dev,
2692 "invalid class for RX_IP_INNER_CHKSUM_ERR: event="
2694 EFX_QWORD_VAL(*event));
2695 if (!efx->loopback_selftest)
2696 channel->n_rx_inner_ip_hdr_chksum_err += n_packets;
2699 if (EFX_QWORD_FIELD(*event, ESF_EZ_RX_TCP_UDP_INNER_CHKSUM_ERR)) {
2700 if (unlikely(!rx_encap_hdr))
2701 netdev_WARN(efx->net_dev,
2702 "invalid encapsulation type for RX_TCP_UDP_INNER_CHKSUM_ERR: event="
2704 EFX_QWORD_VAL(*event));
2705 else if (unlikely((rx_l3_class != ESE_DZ_L3_CLASS_IP4 &&
2706 rx_l3_class != ESE_DZ_L3_CLASS_IP6) ||
2707 (rx_l4_class != ESE_FZ_L4_CLASS_TCP &&
2708 rx_l4_class != ESE_FZ_L4_CLASS_UDP)))
2709 netdev_WARN(efx->net_dev,
2710 "invalid class for RX_TCP_UDP_INNER_CHKSUM_ERR: event="
2712 EFX_QWORD_VAL(*event));
2713 if (!efx->loopback_selftest)
2714 channel->n_rx_inner_tcp_udp_chksum_err += n_packets;
2718 WARN_ON(!handled); /* No error bits were recognised */
2722 static int efx_ef10_handle_rx_event(struct efx_channel *channel,
2723 const efx_qword_t *event)
2725 unsigned int rx_bytes, next_ptr_lbits, rx_queue_label;
2726 unsigned int rx_l3_class, rx_l4_class, rx_encap_hdr;
2727 unsigned int n_descs, n_packets, i;
2728 struct efx_nic *efx = channel->efx;
2729 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2730 struct efx_rx_queue *rx_queue;
2735 if (unlikely(READ_ONCE(efx->reset_pending)))
2738 /* Basic packet information */
2739 rx_bytes = EFX_QWORD_FIELD(*event, ESF_DZ_RX_BYTES);
2740 next_ptr_lbits = EFX_QWORD_FIELD(*event, ESF_DZ_RX_DSC_PTR_LBITS);
2741 rx_queue_label = EFX_QWORD_FIELD(*event, ESF_DZ_RX_QLABEL);
2742 rx_l3_class = EFX_QWORD_FIELD(*event, ESF_DZ_RX_L3_CLASS);
2743 rx_l4_class = EFX_QWORD_FIELD(*event, ESF_FZ_RX_L4_CLASS);
2744 rx_cont = EFX_QWORD_FIELD(*event, ESF_DZ_RX_CONT);
2746 nic_data->datapath_caps &
2747 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN) ?
2748 EFX_QWORD_FIELD(*event, ESF_EZ_RX_ENCAP_HDR) :
2749 ESE_EZ_ENCAP_HDR_NONE;
2751 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_DROP_EVENT))
2752 netdev_WARN(efx->net_dev, "saw RX_DROP_EVENT: event="
2754 EFX_QWORD_VAL(*event));
2756 rx_queue = efx_channel_get_rx_queue(channel);
2758 if (unlikely(rx_queue_label != efx_rx_queue_index(rx_queue)))
2759 efx_ef10_handle_rx_wrong_queue(rx_queue, rx_queue_label);
2761 n_descs = ((next_ptr_lbits - rx_queue->removed_count) &
2762 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
2764 if (n_descs != rx_queue->scatter_n + 1) {
2765 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2767 /* detect rx abort */
2768 if (unlikely(n_descs == rx_queue->scatter_n)) {
2769 if (rx_queue->scatter_n == 0 || rx_bytes != 0)
2770 netdev_WARN(efx->net_dev,
2771 "invalid RX abort: scatter_n=%u event="
2773 rx_queue->scatter_n,
2774 EFX_QWORD_VAL(*event));
2775 efx_ef10_handle_rx_abort(rx_queue);
2779 /* Check that RX completion merging is valid, i.e.
2780 * the current firmware supports it and this is a
2781 * non-scattered packet.
2783 if (!(nic_data->datapath_caps &
2784 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN)) ||
2785 rx_queue->scatter_n != 0 || rx_cont) {
2786 efx_ef10_handle_rx_bad_lbits(
2787 rx_queue, next_ptr_lbits,
2788 (rx_queue->removed_count +
2789 rx_queue->scatter_n + 1) &
2790 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
2794 /* Merged completion for multiple non-scattered packets */
2795 rx_queue->scatter_n = 1;
2796 rx_queue->scatter_len = 0;
2797 n_packets = n_descs;
2798 ++channel->n_rx_merge_events;
2799 channel->n_rx_merge_packets += n_packets;
2800 flags |= EFX_RX_PKT_PREFIX_LEN;
2802 ++rx_queue->scatter_n;
2803 rx_queue->scatter_len += rx_bytes;
2809 EFX_POPULATE_QWORD_5(errors, ESF_DZ_RX_ECRC_ERR, 1,
2810 ESF_DZ_RX_IPCKSUM_ERR, 1,
2811 ESF_DZ_RX_TCPUDP_CKSUM_ERR, 1,
2812 ESF_EZ_RX_IP_INNER_CHKSUM_ERR, 1,
2813 ESF_EZ_RX_TCP_UDP_INNER_CHKSUM_ERR, 1);
2814 EFX_AND_QWORD(errors, *event, errors);
2815 if (unlikely(!EFX_QWORD_IS_ZERO(errors))) {
2816 flags |= efx_ef10_handle_rx_event_errors(channel, n_packets,
2818 rx_l3_class, rx_l4_class,
2821 bool tcpudp = rx_l4_class == ESE_FZ_L4_CLASS_TCP ||
2822 rx_l4_class == ESE_FZ_L4_CLASS_UDP;
2824 switch (rx_encap_hdr) {
2825 case ESE_EZ_ENCAP_HDR_VXLAN: /* VxLAN or GENEVE */
2826 flags |= EFX_RX_PKT_CSUMMED; /* outer UDP csum */
2828 flags |= EFX_RX_PKT_CSUM_LEVEL; /* inner L4 */
2830 case ESE_EZ_ENCAP_HDR_GRE:
2831 case ESE_EZ_ENCAP_HDR_NONE:
2833 flags |= EFX_RX_PKT_CSUMMED;
2836 netdev_WARN(efx->net_dev,
2837 "unknown encapsulation type: event="
2839 EFX_QWORD_VAL(*event));
2843 if (rx_l4_class == ESE_FZ_L4_CLASS_TCP)
2844 flags |= EFX_RX_PKT_TCP;
2846 channel->irq_mod_score += 2 * n_packets;
2848 /* Handle received packet(s) */
2849 for (i = 0; i < n_packets; i++) {
2850 efx_rx_packet(rx_queue,
2851 rx_queue->removed_count & rx_queue->ptr_mask,
2852 rx_queue->scatter_n, rx_queue->scatter_len,
2854 rx_queue->removed_count += rx_queue->scatter_n;
2857 rx_queue->scatter_n = 0;
2858 rx_queue->scatter_len = 0;
2863 static u32 efx_ef10_extract_event_ts(efx_qword_t *event)
2867 tstamp = EFX_QWORD_FIELD(*event, TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI);
2869 tstamp |= EFX_QWORD_FIELD(*event, TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO);
2875 efx_ef10_handle_tx_event(struct efx_channel *channel, efx_qword_t *event)
2877 struct efx_nic *efx = channel->efx;
2878 struct efx_tx_queue *tx_queue;
2879 unsigned int tx_ev_desc_ptr;
2880 unsigned int tx_ev_q_label;
2881 unsigned int tx_ev_type;
2884 if (unlikely(READ_ONCE(efx->reset_pending)))
2887 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_TX_DROP_EVENT)))
2890 /* Get the transmit queue */
2891 tx_ev_q_label = EFX_QWORD_FIELD(*event, ESF_DZ_TX_QLABEL);
2892 tx_queue = efx_channel_get_tx_queue(channel,
2893 tx_ev_q_label % EFX_MAX_TXQ_PER_CHANNEL);
2895 if (!tx_queue->timestamping) {
2896 /* Transmit completion */
2897 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, ESF_DZ_TX_DESCR_INDX);
2898 efx_xmit_done(tx_queue, tx_ev_desc_ptr & tx_queue->ptr_mask);
2902 /* Transmit timestamps are only available for 8XXX series. They result
2903 * in up to three events per packet. These occur in order, and are:
2904 * - the normal completion event (may be omitted)
2905 * - the low part of the timestamp
2906 * - the high part of the timestamp
2908 * It's possible for multiple completion events to appear before the
2909 * corresponding timestamps. So we can for example get:
2917 * In addition it's also possible for the adjacent completions to be
2918 * merged, so we may not see COMP N above. As such, the completion
2919 * events are not very useful here.
2921 * Each part of the timestamp is itself split across two 16 bit
2922 * fields in the event.
2924 tx_ev_type = EFX_QWORD_FIELD(*event, ESF_EZ_TX_SOFT1);
2926 switch (tx_ev_type) {
2927 case TX_TIMESTAMP_EVENT_TX_EV_COMPLETION:
2928 /* Ignore this event - see above. */
2931 case TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_LO:
2932 ts_part = efx_ef10_extract_event_ts(event);
2933 tx_queue->completed_timestamp_minor = ts_part;
2936 case TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_HI:
2937 ts_part = efx_ef10_extract_event_ts(event);
2938 tx_queue->completed_timestamp_major = ts_part;
2940 efx_xmit_done_single(tx_queue);
2944 netif_err(efx, hw, efx->net_dev,
2945 "channel %d unknown tx event type %d (data "
2946 EFX_QWORD_FMT ")\n",
2947 channel->channel, tx_ev_type,
2948 EFX_QWORD_VAL(*event));
2954 efx_ef10_handle_driver_event(struct efx_channel *channel, efx_qword_t *event)
2956 struct efx_nic *efx = channel->efx;
2959 subcode = EFX_QWORD_FIELD(*event, ESF_DZ_DRV_SUB_CODE);
2962 case ESE_DZ_DRV_TIMER_EV:
2963 case ESE_DZ_DRV_WAKE_UP_EV:
2965 case ESE_DZ_DRV_START_UP_EV:
2966 /* event queue init complete. ok. */
2969 netif_err(efx, hw, efx->net_dev,
2970 "channel %d unknown driver event type %d"
2971 " (data " EFX_QWORD_FMT ")\n",
2972 channel->channel, subcode,
2973 EFX_QWORD_VAL(*event));
2978 static void efx_ef10_handle_driver_generated_event(struct efx_channel *channel,
2981 struct efx_nic *efx = channel->efx;
2984 subcode = EFX_QWORD_FIELD(*event, EFX_DWORD_0);
2988 channel->event_test_cpu = raw_smp_processor_id();
2990 case EFX_EF10_REFILL:
2991 /* The queue must be empty, so we won't receive any rx
2992 * events, so efx_process_channel() won't refill the
2993 * queue. Refill it here
2995 efx_fast_push_rx_descriptors(&channel->rx_queue, true);
2998 netif_err(efx, hw, efx->net_dev,
2999 "channel %d unknown driver event type %u"
3000 " (data " EFX_QWORD_FMT ")\n",
3001 channel->channel, (unsigned) subcode,
3002 EFX_QWORD_VAL(*event));
3006 static int efx_ef10_ev_process(struct efx_channel *channel, int quota)
3008 struct efx_nic *efx = channel->efx;
3009 efx_qword_t event, *p_event;
3010 unsigned int read_ptr;
3017 read_ptr = channel->eventq_read_ptr;
3020 p_event = efx_event(channel, read_ptr);
3023 if (!efx_event_present(&event))
3026 EFX_SET_QWORD(*p_event);
3030 ev_code = EFX_QWORD_FIELD(event, ESF_DZ_EV_CODE);
3032 netif_vdbg(efx, drv, efx->net_dev,
3033 "processing event on %d " EFX_QWORD_FMT "\n",
3034 channel->channel, EFX_QWORD_VAL(event));
3037 case ESE_DZ_EV_CODE_MCDI_EV:
3038 efx_mcdi_process_event(channel, &event);
3040 case ESE_DZ_EV_CODE_RX_EV:
3041 spent += efx_ef10_handle_rx_event(channel, &event);
3042 if (spent >= quota) {
3043 /* XXX can we split a merged event to
3044 * avoid going over-quota?
3050 case ESE_DZ_EV_CODE_TX_EV:
3051 efx_ef10_handle_tx_event(channel, &event);
3053 case ESE_DZ_EV_CODE_DRIVER_EV:
3054 efx_ef10_handle_driver_event(channel, &event);
3055 if (++spent == quota)
3058 case EFX_EF10_DRVGEN_EV:
3059 efx_ef10_handle_driver_generated_event(channel, &event);
3062 netif_err(efx, hw, efx->net_dev,
3063 "channel %d unknown event type %d"
3064 " (data " EFX_QWORD_FMT ")\n",
3065 channel->channel, ev_code,
3066 EFX_QWORD_VAL(event));
3071 channel->eventq_read_ptr = read_ptr;
3075 static void efx_ef10_ev_read_ack(struct efx_channel *channel)
3077 struct efx_nic *efx = channel->efx;
3080 if (EFX_EF10_WORKAROUND_35388(efx)) {
3081 BUILD_BUG_ON(EFX_MIN_EVQ_SIZE <
3082 (1 << ERF_DD_EVQ_IND_RPTR_WIDTH));
3083 BUILD_BUG_ON(EFX_MAX_EVQ_SIZE >
3084 (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH));
3086 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
3087 EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH,
3088 ERF_DD_EVQ_IND_RPTR,
3089 (channel->eventq_read_ptr &
3090 channel->eventq_mask) >>
3091 ERF_DD_EVQ_IND_RPTR_WIDTH);
3092 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
3094 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
3095 EFE_DD_EVQ_IND_RPTR_FLAGS_LOW,
3096 ERF_DD_EVQ_IND_RPTR,
3097 channel->eventq_read_ptr &
3098 ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1));
3099 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
3102 EFX_POPULATE_DWORD_1(rptr, ERF_DZ_EVQ_RPTR,
3103 channel->eventq_read_ptr &
3104 channel->eventq_mask);
3105 efx_writed_page(efx, &rptr, ER_DZ_EVQ_RPTR, channel->channel);
3109 static void efx_ef10_ev_test_generate(struct efx_channel *channel)
3111 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
3112 struct efx_nic *efx = channel->efx;
3116 EFX_POPULATE_QWORD_2(event,
3117 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
3118 ESF_DZ_EV_DATA, EFX_EF10_TEST);
3120 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
3122 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
3123 * already swapped the data to little-endian order.
3125 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
3126 sizeof(efx_qword_t));
3128 rc = efx_mcdi_rpc(efx, MC_CMD_DRIVER_EVENT, inbuf, sizeof(inbuf),
3137 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
3140 static void efx_ef10_prepare_flr(struct efx_nic *efx)
3142 atomic_set(&efx->active_queues, 0);
3145 static int efx_ef10_vport_set_mac_address(struct efx_nic *efx)
3147 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3148 u8 mac_old[ETH_ALEN];
3151 /* Only reconfigure a PF-created vport */
3152 if (is_zero_ether_addr(nic_data->vport_mac))
3155 efx_device_detach_sync(efx);
3156 efx_net_stop(efx->net_dev);
3157 down_write(&efx->filter_sem);
3158 efx_mcdi_filter_table_remove(efx);
3159 up_write(&efx->filter_sem);
3161 rc = efx_ef10_vadaptor_free(efx, efx->vport_id);
3163 goto restore_filters;
3165 ether_addr_copy(mac_old, nic_data->vport_mac);
3166 rc = efx_ef10_vport_del_mac(efx, efx->vport_id,
3167 nic_data->vport_mac);
3169 goto restore_vadaptor;
3171 rc = efx_ef10_vport_add_mac(efx, efx->vport_id,
3172 efx->net_dev->dev_addr);
3174 ether_addr_copy(nic_data->vport_mac, efx->net_dev->dev_addr);
3176 rc2 = efx_ef10_vport_add_mac(efx, efx->vport_id, mac_old);
3178 /* Failed to add original MAC, so clear vport_mac */
3179 eth_zero_addr(nic_data->vport_mac);
3185 rc2 = efx_ef10_vadaptor_alloc(efx, efx->vport_id);
3189 down_write(&efx->filter_sem);
3190 rc2 = efx_ef10_filter_table_probe(efx);
3191 up_write(&efx->filter_sem);
3195 rc2 = efx_net_open(efx->net_dev);
3199 efx_device_attach_if_not_resetting(efx);
3204 netif_err(efx, drv, efx->net_dev,
3205 "Failed to restore when changing MAC address - scheduling reset\n");
3206 efx_schedule_reset(efx, RESET_TYPE_DATAPATH);
3208 return rc ? rc : rc2;
3211 static int efx_ef10_set_mac_address(struct efx_nic *efx)
3213 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_SET_MAC_IN_LEN);
3214 bool was_enabled = efx->port_enabled;
3217 efx_device_detach_sync(efx);
3218 efx_net_stop(efx->net_dev);
3220 mutex_lock(&efx->mac_lock);
3221 down_write(&efx->filter_sem);
3222 efx_mcdi_filter_table_remove(efx);
3224 ether_addr_copy(MCDI_PTR(inbuf, VADAPTOR_SET_MAC_IN_MACADDR),
3225 efx->net_dev->dev_addr);
3226 MCDI_SET_DWORD(inbuf, VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID,
3228 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_VADAPTOR_SET_MAC, inbuf,
3229 sizeof(inbuf), NULL, 0, NULL);
3231 efx_ef10_filter_table_probe(efx);
3232 up_write(&efx->filter_sem);
3233 mutex_unlock(&efx->mac_lock);
3236 efx_net_open(efx->net_dev);
3237 efx_device_attach_if_not_resetting(efx);
3239 #ifdef CONFIG_SFC_SRIOV
3240 if (efx->pci_dev->is_virtfn && efx->pci_dev->physfn) {
3241 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3242 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn;
3245 struct efx_nic *efx_pf;
3247 /* Switch to PF and change MAC address on vport */
3248 efx_pf = pci_get_drvdata(pci_dev_pf);
3250 rc = efx_ef10_sriov_set_vf_mac(efx_pf,
3252 efx->net_dev->dev_addr);
3254 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
3255 struct efx_ef10_nic_data *nic_data = efx_pf->nic_data;
3258 /* MAC address successfully changed by VF (with MAC
3259 * spoofing) so update the parent PF if possible.
3261 for (i = 0; i < efx_pf->vf_count; ++i) {
3262 struct ef10_vf *vf = nic_data->vf + i;
3264 if (vf->efx == efx) {
3265 ether_addr_copy(vf->mac,
3266 efx->net_dev->dev_addr);
3274 netif_err(efx, drv, efx->net_dev,
3275 "Cannot change MAC address; use sfboot to enable"
3276 " mac-spoofing on this interface\n");
3277 } else if (rc == -ENOSYS && !efx_ef10_is_vf(efx)) {
3278 /* If the active MCFW does not support MC_CMD_VADAPTOR_SET_MAC
3279 * fall-back to the method of changing the MAC address on the
3280 * vport. This only applies to PFs because such versions of
3281 * MCFW do not support VFs.
3283 rc = efx_ef10_vport_set_mac_address(efx);
3285 efx_mcdi_display_error(efx, MC_CMD_VADAPTOR_SET_MAC,
3286 sizeof(inbuf), NULL, 0, rc);
3292 static int efx_ef10_mac_reconfigure(struct efx_nic *efx, bool mtu_only)
3294 WARN_ON(!mutex_is_locked(&efx->mac_lock));
3296 efx_mcdi_filter_sync_rx_mode(efx);
3298 if (mtu_only && efx_has_cap(efx, SET_MAC_ENHANCED))
3299 return efx_mcdi_set_mtu(efx);
3300 return efx_mcdi_set_mac(efx);
3303 static int efx_ef10_start_bist(struct efx_nic *efx, u32 bist_type)
3305 MCDI_DECLARE_BUF(inbuf, MC_CMD_START_BIST_IN_LEN);
3307 MCDI_SET_DWORD(inbuf, START_BIST_IN_TYPE, bist_type);
3308 return efx_mcdi_rpc(efx, MC_CMD_START_BIST, inbuf, sizeof(inbuf),
3312 /* MC BISTs follow a different poll mechanism to phy BISTs.
3313 * The BIST is done in the poll handler on the MC, and the MCDI command
3314 * will block until the BIST is done.
3316 static int efx_ef10_poll_bist(struct efx_nic *efx)
3319 MCDI_DECLARE_BUF(outbuf, MC_CMD_POLL_BIST_OUT_LEN);
3323 rc = efx_mcdi_rpc(efx, MC_CMD_POLL_BIST, NULL, 0,
3324 outbuf, sizeof(outbuf), &outlen);
3328 if (outlen < MC_CMD_POLL_BIST_OUT_LEN)
3331 result = MCDI_DWORD(outbuf, POLL_BIST_OUT_RESULT);
3333 case MC_CMD_POLL_BIST_PASSED:
3334 netif_dbg(efx, hw, efx->net_dev, "BIST passed.\n");
3336 case MC_CMD_POLL_BIST_TIMEOUT:
3337 netif_err(efx, hw, efx->net_dev, "BIST timed out\n");
3339 case MC_CMD_POLL_BIST_FAILED:
3340 netif_err(efx, hw, efx->net_dev, "BIST failed.\n");
3343 netif_err(efx, hw, efx->net_dev,
3344 "BIST returned unknown result %u", result);
3349 static int efx_ef10_run_bist(struct efx_nic *efx, u32 bist_type)
3353 netif_dbg(efx, drv, efx->net_dev, "starting BIST type %u\n", bist_type);
3355 rc = efx_ef10_start_bist(efx, bist_type);
3359 return efx_ef10_poll_bist(efx);
3363 efx_ef10_test_chip(struct efx_nic *efx, struct efx_self_tests *tests)
3367 efx_reset_down(efx, RESET_TYPE_WORLD);
3369 rc = efx_mcdi_rpc(efx, MC_CMD_ENABLE_OFFLINE_BIST,
3370 NULL, 0, NULL, 0, NULL);
3374 tests->memory = efx_ef10_run_bist(efx, MC_CMD_MC_MEM_BIST) ? -1 : 1;
3375 tests->registers = efx_ef10_run_bist(efx, MC_CMD_REG_BIST) ? -1 : 1;
3377 rc = efx_mcdi_reset(efx, RESET_TYPE_WORLD);
3382 rc2 = efx_reset_up(efx, RESET_TYPE_WORLD, rc == 0);
3383 return rc ? rc : rc2;
3386 #ifdef CONFIG_SFC_MTD
3388 struct efx_ef10_nvram_type_info {
3389 u16 type, type_mask;
3394 static const struct efx_ef10_nvram_type_info efx_ef10_nvram_types[] = {
3395 { NVRAM_PARTITION_TYPE_MC_FIRMWARE, 0, 0, "sfc_mcfw" },
3396 { NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 0, 0, "sfc_mcfw_backup" },
3397 { NVRAM_PARTITION_TYPE_EXPANSION_ROM, 0, 0, "sfc_exp_rom" },
3398 { NVRAM_PARTITION_TYPE_STATIC_CONFIG, 0, 0, "sfc_static_cfg" },
3399 { NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 0, 0, "sfc_dynamic_cfg" },
3400 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 0, 0, "sfc_exp_rom_cfg" },
3401 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1, 0, 1, "sfc_exp_rom_cfg" },
3402 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2, 0, 2, "sfc_exp_rom_cfg" },
3403 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3, 0, 3, "sfc_exp_rom_cfg" },
3404 { NVRAM_PARTITION_TYPE_LICENSE, 0, 0, "sfc_license" },
3405 { NVRAM_PARTITION_TYPE_PHY_MIN, 0xff, 0, "sfc_phy_fw" },
3406 { NVRAM_PARTITION_TYPE_MUM_FIRMWARE, 0, 0, "sfc_mumfw" },
3407 { NVRAM_PARTITION_TYPE_EXPANSION_UEFI, 0, 0, "sfc_uefi" },
3408 { NVRAM_PARTITION_TYPE_DYNCONFIG_DEFAULTS, 0, 0, "sfc_dynamic_cfg_dflt" },
3409 { NVRAM_PARTITION_TYPE_ROMCONFIG_DEFAULTS, 0, 0, "sfc_exp_rom_cfg_dflt" },
3410 { NVRAM_PARTITION_TYPE_STATUS, 0, 0, "sfc_status" },
3411 { NVRAM_PARTITION_TYPE_BUNDLE, 0, 0, "sfc_bundle" },
3412 { NVRAM_PARTITION_TYPE_BUNDLE_METADATA, 0, 0, "sfc_bundle_metadata" },
3414 #define EF10_NVRAM_PARTITION_COUNT ARRAY_SIZE(efx_ef10_nvram_types)
3416 static int efx_ef10_mtd_probe_partition(struct efx_nic *efx,
3417 struct efx_mcdi_mtd_partition *part,
3419 unsigned long *found)
3421 MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_METADATA_IN_LEN);
3422 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_METADATA_OUT_LENMAX);
3423 const struct efx_ef10_nvram_type_info *info;
3424 size_t size, erase_size, outlen;
3429 for (type_idx = 0; ; type_idx++) {
3430 if (type_idx == EF10_NVRAM_PARTITION_COUNT)
3432 info = efx_ef10_nvram_types + type_idx;
3433 if ((type & ~info->type_mask) == info->type)
3436 if (info->port != efx_port_num(efx))
3439 rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected);
3443 (type != NVRAM_PARTITION_TYPE_DYNCONFIG_DEFAULTS &&
3444 type != NVRAM_PARTITION_TYPE_ROMCONFIG_DEFAULTS))
3445 /* Hide protected partitions that don't provide defaults. */
3449 /* Protected partitions are read only. */
3452 /* If we've already exposed a partition of this type, hide this
3453 * duplicate. All operations on MTDs are keyed by the type anyway,
3454 * so we can't act on the duplicate.
3456 if (__test_and_set_bit(type_idx, found))
3459 part->nvram_type = type;
3461 MCDI_SET_DWORD(inbuf, NVRAM_METADATA_IN_TYPE, type);
3462 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_METADATA, inbuf, sizeof(inbuf),
3463 outbuf, sizeof(outbuf), &outlen);
3466 if (outlen < MC_CMD_NVRAM_METADATA_OUT_LENMIN)
3468 if (MCDI_DWORD(outbuf, NVRAM_METADATA_OUT_FLAGS) &
3469 (1 << MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN))
3470 part->fw_subtype = MCDI_DWORD(outbuf,
3471 NVRAM_METADATA_OUT_SUBTYPE);
3473 part->common.dev_type_name = "EF10 NVRAM manager";
3474 part->common.type_name = info->name;
3476 part->common.mtd.type = MTD_NORFLASH;
3477 part->common.mtd.flags = MTD_CAP_NORFLASH;
3478 part->common.mtd.size = size;
3479 part->common.mtd.erasesize = erase_size;
3480 /* sfc_status is read-only */
3482 part->common.mtd.flags |= MTD_NO_ERASE;
3487 static int efx_ef10_mtd_probe(struct efx_nic *efx)
3489 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX);
3490 DECLARE_BITMAP(found, EF10_NVRAM_PARTITION_COUNT) = { 0 };
3491 struct efx_mcdi_mtd_partition *parts;
3492 size_t outlen, n_parts_total, i, n_parts;
3498 BUILD_BUG_ON(MC_CMD_NVRAM_PARTITIONS_IN_LEN != 0);
3499 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_PARTITIONS, NULL, 0,
3500 outbuf, sizeof(outbuf), &outlen);
3503 if (outlen < MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN)
3506 n_parts_total = MCDI_DWORD(outbuf, NVRAM_PARTITIONS_OUT_NUM_PARTITIONS);
3508 MCDI_VAR_ARRAY_LEN(outlen, NVRAM_PARTITIONS_OUT_TYPE_ID))
3511 parts = kcalloc(n_parts_total, sizeof(*parts), GFP_KERNEL);
3516 for (i = 0; i < n_parts_total; i++) {
3517 type = MCDI_ARRAY_DWORD(outbuf, NVRAM_PARTITIONS_OUT_TYPE_ID,
3519 rc = efx_ef10_mtd_probe_partition(efx, &parts[n_parts], type,
3521 if (rc == -EEXIST || rc == -ENODEV)
3528 rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts));
3535 #endif /* CONFIG_SFC_MTD */
3537 static void efx_ef10_ptp_write_host_time(struct efx_nic *efx, u32 host_time)
3539 _efx_writed(efx, cpu_to_le32(host_time), ER_DZ_MC_DB_LWRD);
3542 static void efx_ef10_ptp_write_host_time_vf(struct efx_nic *efx,
3545 static int efx_ef10_rx_enable_timestamping(struct efx_channel *channel,
3548 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN);
3551 if (channel->sync_events_state == SYNC_EVENTS_REQUESTED ||
3552 channel->sync_events_state == SYNC_EVENTS_VALID ||
3553 (temp && channel->sync_events_state == SYNC_EVENTS_DISABLED))
3555 channel->sync_events_state = SYNC_EVENTS_REQUESTED;
3557 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE);
3558 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
3559 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE,
3562 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
3563 inbuf, sizeof(inbuf), NULL, 0, NULL);
3566 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
3567 SYNC_EVENTS_DISABLED;
3572 static int efx_ef10_rx_disable_timestamping(struct efx_channel *channel,
3575 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN);
3578 if (channel->sync_events_state == SYNC_EVENTS_DISABLED ||
3579 (temp && channel->sync_events_state == SYNC_EVENTS_QUIESCENT))
3581 if (channel->sync_events_state == SYNC_EVENTS_QUIESCENT) {
3582 channel->sync_events_state = SYNC_EVENTS_DISABLED;
3585 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
3586 SYNC_EVENTS_DISABLED;
3588 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE);
3589 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
3590 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL,
3591 MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE);
3592 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE,
3595 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
3596 inbuf, sizeof(inbuf), NULL, 0, NULL);
3601 static int efx_ef10_ptp_set_ts_sync_events(struct efx_nic *efx, bool en,
3604 int (*set)(struct efx_channel *channel, bool temp);
3605 struct efx_channel *channel;
3608 efx_ef10_rx_enable_timestamping :
3609 efx_ef10_rx_disable_timestamping;
3611 channel = efx_ptp_channel(efx);
3613 int rc = set(channel, temp);
3614 if (en && rc != 0) {
3615 efx_ef10_ptp_set_ts_sync_events(efx, false, temp);
3623 static int efx_ef10_ptp_set_ts_config_vf(struct efx_nic *efx,
3624 struct hwtstamp_config *init)
3629 static int efx_ef10_ptp_set_ts_config(struct efx_nic *efx,
3630 struct hwtstamp_config *init)
3634 switch (init->rx_filter) {
3635 case HWTSTAMP_FILTER_NONE:
3636 efx_ef10_ptp_set_ts_sync_events(efx, false, false);
3637 /* if TX timestamping is still requested then leave PTP on */
3638 return efx_ptp_change_mode(efx,
3639 init->tx_type != HWTSTAMP_TX_OFF, 0);
3640 case HWTSTAMP_FILTER_ALL:
3641 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3642 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3643 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3644 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3645 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3646 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3647 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3648 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3649 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3650 case HWTSTAMP_FILTER_PTP_V2_EVENT:
3651 case HWTSTAMP_FILTER_PTP_V2_SYNC:
3652 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3653 case HWTSTAMP_FILTER_NTP_ALL:
3654 init->rx_filter = HWTSTAMP_FILTER_ALL;
3655 rc = efx_ptp_change_mode(efx, true, 0);
3657 rc = efx_ef10_ptp_set_ts_sync_events(efx, true, false);
3659 efx_ptp_change_mode(efx, false, 0);
3666 static int efx_ef10_get_phys_port_id(struct efx_nic *efx,
3667 struct netdev_phys_item_id *ppid)
3669 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3671 if (!is_valid_ether_addr(nic_data->port_id))
3674 ppid->id_len = ETH_ALEN;
3675 memcpy(ppid->id, nic_data->port_id, ppid->id_len);
3680 static int efx_ef10_vlan_rx_add_vid(struct efx_nic *efx, __be16 proto, u16 vid)
3682 if (proto != htons(ETH_P_8021Q))
3685 return efx_ef10_add_vlan(efx, vid);
3688 static int efx_ef10_vlan_rx_kill_vid(struct efx_nic *efx, __be16 proto, u16 vid)
3690 if (proto != htons(ETH_P_8021Q))
3693 return efx_ef10_del_vlan(efx, vid);
3696 /* We rely on the MCDI wiping out our TX rings if it made any changes to the
3697 * ports table, ensuring that any TSO descriptors that were made on a now-
3698 * removed tunnel port will be blown away and won't break things when we try
3699 * to transmit them using the new ports table.
3701 static int efx_ef10_set_udp_tnl_ports(struct efx_nic *efx, bool unloading)
3703 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3704 MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LENMAX);
3705 MCDI_DECLARE_BUF(outbuf, MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_LEN);
3706 bool will_reset = false;
3707 size_t num_entries = 0;
3708 size_t inlen, outlen;
3711 efx_dword_t flags_and_num_entries;
3713 WARN_ON(!mutex_is_locked(&nic_data->udp_tunnels_lock));
3715 nic_data->udp_tunnels_dirty = false;
3717 if (!(nic_data->datapath_caps &
3718 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN))) {
3719 efx_device_attach_if_not_resetting(efx);
3723 BUILD_BUG_ON(ARRAY_SIZE(nic_data->udp_tunnels) >
3724 MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MAXNUM);
3726 for (i = 0; i < ARRAY_SIZE(nic_data->udp_tunnels); ++i) {
3727 if (nic_data->udp_tunnels[i].type !=
3728 TUNNEL_ENCAP_UDP_PORT_ENTRY_INVALID) {
3731 EFX_POPULATE_DWORD_2(entry,
3732 TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT,
3733 ntohs(nic_data->udp_tunnels[i].port),
3734 TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL,
3735 nic_data->udp_tunnels[i].type);
3736 *_MCDI_ARRAY_DWORD(inbuf,
3737 SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES,
3738 num_entries++) = entry;
3742 BUILD_BUG_ON((MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_OFST -
3743 MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS_OFST) * 8 !=
3745 BUILD_BUG_ON(MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_LEN * 8 !=
3747 EFX_POPULATE_DWORD_2(flags_and_num_entries,
3748 MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING,
3750 EFX_WORD_1, num_entries);
3751 *_MCDI_DWORD(inbuf, SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS) =
3752 flags_and_num_entries;
3754 inlen = MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LEN(num_entries);
3756 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS,
3757 inbuf, inlen, outbuf, sizeof(outbuf), &outlen);
3759 /* Most likely the MC rebooted due to another function also
3760 * setting its tunnel port list. Mark the tunnel port list as
3761 * dirty, so it will be pushed upon coming up from the reboot.
3763 nic_data->udp_tunnels_dirty = true;
3768 /* expected not available on unprivileged functions */
3770 netif_warn(efx, drv, efx->net_dev,
3771 "Unable to set UDP tunnel ports; rc=%d.\n", rc);
3772 } else if (MCDI_DWORD(outbuf, SET_TUNNEL_ENCAP_UDP_PORTS_OUT_FLAGS) &
3773 (1 << MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_LBN)) {
3774 netif_info(efx, drv, efx->net_dev,
3775 "Rebooting MC due to UDP tunnel port list change\n");
3778 /* Delay for the MC reset to complete. This will make
3779 * unloading other functions a bit smoother. This is a
3780 * race, but the other unload will work whichever way
3781 * it goes, this just avoids an unnecessary error
3786 if (!will_reset && !unloading) {
3787 /* The caller will have detached, relying on the MC reset to
3788 * trigger a re-attach. Since there won't be an MC reset, we
3789 * have to do the attach ourselves.
3791 efx_device_attach_if_not_resetting(efx);
3797 static int efx_ef10_udp_tnl_push_ports(struct efx_nic *efx)
3799 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3802 mutex_lock(&nic_data->udp_tunnels_lock);
3803 if (nic_data->udp_tunnels_dirty) {
3804 /* Make sure all TX are stopped while we modify the table, else
3805 * we might race against an efx_features_check().
3807 efx_device_detach_sync(efx);
3808 rc = efx_ef10_set_udp_tnl_ports(efx, false);
3810 mutex_unlock(&nic_data->udp_tunnels_lock);
3814 static int efx_ef10_udp_tnl_set_port(struct net_device *dev,
3815 unsigned int table, unsigned int entry,
3816 struct udp_tunnel_info *ti)
3818 struct efx_nic *efx = netdev_priv(dev);
3819 struct efx_ef10_nic_data *nic_data;
3820 int efx_tunnel_type, rc;
3822 if (ti->type == UDP_TUNNEL_TYPE_VXLAN)
3823 efx_tunnel_type = TUNNEL_ENCAP_UDP_PORT_ENTRY_VXLAN;
3825 efx_tunnel_type = TUNNEL_ENCAP_UDP_PORT_ENTRY_GENEVE;
3827 nic_data = efx->nic_data;
3828 if (!(nic_data->datapath_caps &
3829 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN)))
3832 mutex_lock(&nic_data->udp_tunnels_lock);
3833 /* Make sure all TX are stopped while we add to the table, else we
3834 * might race against an efx_features_check().
3836 efx_device_detach_sync(efx);
3837 nic_data->udp_tunnels[entry].type = efx_tunnel_type;
3838 nic_data->udp_tunnels[entry].port = ti->port;
3839 rc = efx_ef10_set_udp_tnl_ports(efx, false);
3840 mutex_unlock(&nic_data->udp_tunnels_lock);
3845 /* Called under the TX lock with the TX queue running, hence no-one can be
3846 * in the middle of updating the UDP tunnels table. However, they could
3847 * have tried and failed the MCDI, in which case they'll have set the dirty
3848 * flag before dropping their locks.
3850 static bool efx_ef10_udp_tnl_has_port(struct efx_nic *efx, __be16 port)
3852 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3855 if (!(nic_data->datapath_caps &
3856 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN)))
3859 if (nic_data->udp_tunnels_dirty)
3860 /* SW table may not match HW state, so just assume we can't
3861 * use any UDP tunnel offloads.
3865 for (i = 0; i < ARRAY_SIZE(nic_data->udp_tunnels); ++i)
3866 if (nic_data->udp_tunnels[i].type !=
3867 TUNNEL_ENCAP_UDP_PORT_ENTRY_INVALID &&
3868 nic_data->udp_tunnels[i].port == port)
3874 static int efx_ef10_udp_tnl_unset_port(struct net_device *dev,
3875 unsigned int table, unsigned int entry,
3876 struct udp_tunnel_info *ti)
3878 struct efx_nic *efx = netdev_priv(dev);
3879 struct efx_ef10_nic_data *nic_data;
3882 nic_data = efx->nic_data;
3884 mutex_lock(&nic_data->udp_tunnels_lock);
3885 /* Make sure all TX are stopped while we remove from the table, else we
3886 * might race against an efx_features_check().
3888 efx_device_detach_sync(efx);
3889 nic_data->udp_tunnels[entry].type = TUNNEL_ENCAP_UDP_PORT_ENTRY_INVALID;
3890 nic_data->udp_tunnels[entry].port = 0;
3891 rc = efx_ef10_set_udp_tnl_ports(efx, false);
3892 mutex_unlock(&nic_data->udp_tunnels_lock);
3897 static const struct udp_tunnel_nic_info efx_ef10_udp_tunnels = {
3898 .set_port = efx_ef10_udp_tnl_set_port,
3899 .unset_port = efx_ef10_udp_tnl_unset_port,
3900 .flags = UDP_TUNNEL_NIC_INFO_MAY_SLEEP,
3904 .tunnel_types = UDP_TUNNEL_TYPE_VXLAN |
3905 UDP_TUNNEL_TYPE_GENEVE,
3910 /* EF10 may have multiple datapath firmware variants within a
3911 * single version. Report which variants are running.
3913 static size_t efx_ef10_print_additional_fwver(struct efx_nic *efx, char *buf,
3916 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3918 return scnprintf(buf, len, " rx%x tx%x",
3919 nic_data->rx_dpcpu_fw_id,
3920 nic_data->tx_dpcpu_fw_id);
3923 static unsigned int ef10_check_caps(const struct efx_nic *efx,
3927 const struct efx_ef10_nic_data *nic_data = efx->nic_data;
3930 case(MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS1_OFST):
3931 return nic_data->datapath_caps & BIT_ULL(flag);
3932 case(MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS2_OFST):
3933 return nic_data->datapath_caps2 & BIT_ULL(flag);
3939 #define EF10_OFFLOAD_FEATURES \
3940 (NETIF_F_IP_CSUM | \
3941 NETIF_F_HW_VLAN_CTAG_FILTER | \
3942 NETIF_F_IPV6_CSUM | \
3946 const struct efx_nic_type efx_hunt_a0_vf_nic_type = {
3948 .mem_bar = efx_ef10_vf_mem_bar,
3949 .mem_map_size = efx_ef10_mem_map_size,
3950 .probe = efx_ef10_probe_vf,
3951 .remove = efx_ef10_remove,
3952 .dimension_resources = efx_ef10_dimension_resources,
3953 .init = efx_ef10_init_nic,
3954 .fini = efx_ef10_fini_nic,
3955 .map_reset_reason = efx_ef10_map_reset_reason,
3956 .map_reset_flags = efx_ef10_map_reset_flags,
3957 .reset = efx_ef10_reset,
3958 .probe_port = efx_mcdi_port_probe,
3959 .remove_port = efx_mcdi_port_remove,
3960 .fini_dmaq = efx_fini_dmaq,
3961 .prepare_flr = efx_ef10_prepare_flr,
3962 .finish_flr = efx_port_dummy_op_void,
3963 .describe_stats = efx_ef10_describe_stats,
3964 .update_stats = efx_ef10_update_stats_vf,
3965 .start_stats = efx_port_dummy_op_void,
3966 .pull_stats = efx_port_dummy_op_void,
3967 .stop_stats = efx_port_dummy_op_void,
3968 .push_irq_moderation = efx_ef10_push_irq_moderation,
3969 .reconfigure_mac = efx_ef10_mac_reconfigure,
3970 .check_mac_fault = efx_mcdi_mac_check_fault,
3971 .reconfigure_port = efx_mcdi_port_reconfigure,
3972 .get_wol = efx_ef10_get_wol_vf,
3973 .set_wol = efx_ef10_set_wol_vf,
3974 .resume_wol = efx_port_dummy_op_void,
3975 .mcdi_request = efx_ef10_mcdi_request,
3976 .mcdi_poll_response = efx_ef10_mcdi_poll_response,
3977 .mcdi_read_response = efx_ef10_mcdi_read_response,
3978 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
3979 .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected,
3980 .irq_enable_master = efx_port_dummy_op_void,
3981 .irq_test_generate = efx_ef10_irq_test_generate,
3982 .irq_disable_non_ev = efx_port_dummy_op_void,
3983 .irq_handle_msi = efx_ef10_msi_interrupt,
3984 .irq_handle_legacy = efx_ef10_legacy_interrupt,
3985 .tx_probe = efx_ef10_tx_probe,
3986 .tx_init = efx_ef10_tx_init,
3987 .tx_remove = efx_mcdi_tx_remove,
3988 .tx_write = efx_ef10_tx_write,
3989 .tx_limit_len = efx_ef10_tx_limit_len,
3990 .tx_enqueue = __efx_enqueue_skb,
3991 .rx_push_rss_config = efx_mcdi_vf_rx_push_rss_config,
3992 .rx_pull_rss_config = efx_mcdi_rx_pull_rss_config,
3993 .rx_probe = efx_mcdi_rx_probe,
3994 .rx_init = efx_mcdi_rx_init,
3995 .rx_remove = efx_mcdi_rx_remove,
3996 .rx_write = efx_ef10_rx_write,
3997 .rx_defer_refill = efx_ef10_rx_defer_refill,
3998 .rx_packet = __efx_rx_packet,
3999 .ev_probe = efx_mcdi_ev_probe,
4000 .ev_init = efx_ef10_ev_init,
4001 .ev_fini = efx_mcdi_ev_fini,
4002 .ev_remove = efx_mcdi_ev_remove,
4003 .ev_process = efx_ef10_ev_process,
4004 .ev_read_ack = efx_ef10_ev_read_ack,
4005 .ev_test_generate = efx_ef10_ev_test_generate,
4006 .filter_table_probe = efx_ef10_filter_table_probe,
4007 .filter_table_restore = efx_mcdi_filter_table_restore,
4008 .filter_table_remove = efx_mcdi_filter_table_remove,
4009 .filter_update_rx_scatter = efx_mcdi_update_rx_scatter,
4010 .filter_insert = efx_mcdi_filter_insert,
4011 .filter_remove_safe = efx_mcdi_filter_remove_safe,
4012 .filter_get_safe = efx_mcdi_filter_get_safe,
4013 .filter_clear_rx = efx_mcdi_filter_clear_rx,
4014 .filter_count_rx_used = efx_mcdi_filter_count_rx_used,
4015 .filter_get_rx_id_limit = efx_mcdi_filter_get_rx_id_limit,
4016 .filter_get_rx_ids = efx_mcdi_filter_get_rx_ids,
4017 #ifdef CONFIG_RFS_ACCEL
4018 .filter_rfs_expire_one = efx_mcdi_filter_rfs_expire_one,
4020 #ifdef CONFIG_SFC_MTD
4021 .mtd_probe = efx_port_dummy_op_int,
4023 .ptp_write_host_time = efx_ef10_ptp_write_host_time_vf,
4024 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config_vf,
4025 .vlan_rx_add_vid = efx_ef10_vlan_rx_add_vid,
4026 .vlan_rx_kill_vid = efx_ef10_vlan_rx_kill_vid,
4027 #ifdef CONFIG_SFC_SRIOV
4028 .vswitching_probe = efx_ef10_vswitching_probe_vf,
4029 .vswitching_restore = efx_ef10_vswitching_restore_vf,
4030 .vswitching_remove = efx_ef10_vswitching_remove_vf,
4032 .get_mac_address = efx_ef10_get_mac_address_vf,
4033 .set_mac_address = efx_ef10_set_mac_address,
4035 .get_phys_port_id = efx_ef10_get_phys_port_id,
4036 .revision = EFX_REV_HUNT_A0,
4037 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
4038 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
4039 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
4040 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
4041 .can_rx_scatter = true,
4042 .always_rx_scatter = true,
4043 .min_interrupt_mode = EFX_INT_MODE_MSIX,
4044 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
4045 .offload_features = EF10_OFFLOAD_FEATURES,
4047 .max_rx_ip_filters = EFX_MCDI_FILTER_TBL_ROWS,
4048 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
4049 1 << HWTSTAMP_FILTER_ALL,
4050 .rx_hash_key_size = 40,
4051 .check_caps = ef10_check_caps,
4052 .print_additional_fwver = efx_ef10_print_additional_fwver,
4053 .sensor_event = efx_mcdi_sensor_event,
4056 const struct efx_nic_type efx_hunt_a0_nic_type = {
4058 .mem_bar = efx_ef10_pf_mem_bar,
4059 .mem_map_size = efx_ef10_mem_map_size,
4060 .probe = efx_ef10_probe_pf,
4061 .remove = efx_ef10_remove,
4062 .dimension_resources = efx_ef10_dimension_resources,
4063 .init = efx_ef10_init_nic,
4064 .fini = efx_ef10_fini_nic,
4065 .map_reset_reason = efx_ef10_map_reset_reason,
4066 .map_reset_flags = efx_ef10_map_reset_flags,
4067 .reset = efx_ef10_reset,
4068 .probe_port = efx_mcdi_port_probe,
4069 .remove_port = efx_mcdi_port_remove,
4070 .fini_dmaq = efx_fini_dmaq,
4071 .prepare_flr = efx_ef10_prepare_flr,
4072 .finish_flr = efx_port_dummy_op_void,
4073 .describe_stats = efx_ef10_describe_stats,
4074 .update_stats = efx_ef10_update_stats_pf,
4075 .start_stats = efx_mcdi_mac_start_stats,
4076 .pull_stats = efx_mcdi_mac_pull_stats,
4077 .stop_stats = efx_mcdi_mac_stop_stats,
4078 .push_irq_moderation = efx_ef10_push_irq_moderation,
4079 .reconfigure_mac = efx_ef10_mac_reconfigure,
4080 .check_mac_fault = efx_mcdi_mac_check_fault,
4081 .reconfigure_port = efx_mcdi_port_reconfigure,
4082 .get_wol = efx_ef10_get_wol,
4083 .set_wol = efx_ef10_set_wol,
4084 .resume_wol = efx_port_dummy_op_void,
4085 .test_chip = efx_ef10_test_chip,
4086 .test_nvram = efx_mcdi_nvram_test_all,
4087 .mcdi_request = efx_ef10_mcdi_request,
4088 .mcdi_poll_response = efx_ef10_mcdi_poll_response,
4089 .mcdi_read_response = efx_ef10_mcdi_read_response,
4090 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
4091 .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected,
4092 .irq_enable_master = efx_port_dummy_op_void,
4093 .irq_test_generate = efx_ef10_irq_test_generate,
4094 .irq_disable_non_ev = efx_port_dummy_op_void,
4095 .irq_handle_msi = efx_ef10_msi_interrupt,
4096 .irq_handle_legacy = efx_ef10_legacy_interrupt,
4097 .tx_probe = efx_ef10_tx_probe,
4098 .tx_init = efx_ef10_tx_init,
4099 .tx_remove = efx_mcdi_tx_remove,
4100 .tx_write = efx_ef10_tx_write,
4101 .tx_limit_len = efx_ef10_tx_limit_len,
4102 .tx_enqueue = __efx_enqueue_skb,
4103 .rx_push_rss_config = efx_mcdi_pf_rx_push_rss_config,
4104 .rx_pull_rss_config = efx_mcdi_rx_pull_rss_config,
4105 .rx_push_rss_context_config = efx_mcdi_rx_push_rss_context_config,
4106 .rx_pull_rss_context_config = efx_mcdi_rx_pull_rss_context_config,
4107 .rx_restore_rss_contexts = efx_mcdi_rx_restore_rss_contexts,
4108 .rx_probe = efx_mcdi_rx_probe,
4109 .rx_init = efx_mcdi_rx_init,
4110 .rx_remove = efx_mcdi_rx_remove,
4111 .rx_write = efx_ef10_rx_write,
4112 .rx_defer_refill = efx_ef10_rx_defer_refill,
4113 .rx_packet = __efx_rx_packet,
4114 .ev_probe = efx_mcdi_ev_probe,
4115 .ev_init = efx_ef10_ev_init,
4116 .ev_fini = efx_mcdi_ev_fini,
4117 .ev_remove = efx_mcdi_ev_remove,
4118 .ev_process = efx_ef10_ev_process,
4119 .ev_read_ack = efx_ef10_ev_read_ack,
4120 .ev_test_generate = efx_ef10_ev_test_generate,
4121 .filter_table_probe = efx_ef10_filter_table_probe,
4122 .filter_table_restore = efx_mcdi_filter_table_restore,
4123 .filter_table_remove = efx_mcdi_filter_table_remove,
4124 .filter_update_rx_scatter = efx_mcdi_update_rx_scatter,
4125 .filter_insert = efx_mcdi_filter_insert,
4126 .filter_remove_safe = efx_mcdi_filter_remove_safe,
4127 .filter_get_safe = efx_mcdi_filter_get_safe,
4128 .filter_clear_rx = efx_mcdi_filter_clear_rx,
4129 .filter_count_rx_used = efx_mcdi_filter_count_rx_used,
4130 .filter_get_rx_id_limit = efx_mcdi_filter_get_rx_id_limit,
4131 .filter_get_rx_ids = efx_mcdi_filter_get_rx_ids,
4132 #ifdef CONFIG_RFS_ACCEL
4133 .filter_rfs_expire_one = efx_mcdi_filter_rfs_expire_one,
4135 #ifdef CONFIG_SFC_MTD
4136 .mtd_probe = efx_ef10_mtd_probe,
4137 .mtd_rename = efx_mcdi_mtd_rename,
4138 .mtd_read = efx_mcdi_mtd_read,
4139 .mtd_erase = efx_mcdi_mtd_erase,
4140 .mtd_write = efx_mcdi_mtd_write,
4141 .mtd_sync = efx_mcdi_mtd_sync,
4143 .ptp_write_host_time = efx_ef10_ptp_write_host_time,
4144 .ptp_set_ts_sync_events = efx_ef10_ptp_set_ts_sync_events,
4145 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config,
4146 .vlan_rx_add_vid = efx_ef10_vlan_rx_add_vid,
4147 .vlan_rx_kill_vid = efx_ef10_vlan_rx_kill_vid,
4148 .udp_tnl_push_ports = efx_ef10_udp_tnl_push_ports,
4149 .udp_tnl_has_port = efx_ef10_udp_tnl_has_port,
4150 #ifdef CONFIG_SFC_SRIOV
4151 .sriov_configure = efx_ef10_sriov_configure,
4152 .sriov_init = efx_ef10_sriov_init,
4153 .sriov_fini = efx_ef10_sriov_fini,
4154 .sriov_wanted = efx_ef10_sriov_wanted,
4155 .sriov_reset = efx_ef10_sriov_reset,
4156 .sriov_flr = efx_ef10_sriov_flr,
4157 .sriov_set_vf_mac = efx_ef10_sriov_set_vf_mac,
4158 .sriov_set_vf_vlan = efx_ef10_sriov_set_vf_vlan,
4159 .sriov_set_vf_spoofchk = efx_ef10_sriov_set_vf_spoofchk,
4160 .sriov_get_vf_config = efx_ef10_sriov_get_vf_config,
4161 .sriov_set_vf_link_state = efx_ef10_sriov_set_vf_link_state,
4162 .vswitching_probe = efx_ef10_vswitching_probe_pf,
4163 .vswitching_restore = efx_ef10_vswitching_restore_pf,
4164 .vswitching_remove = efx_ef10_vswitching_remove_pf,
4166 .get_mac_address = efx_ef10_get_mac_address_pf,
4167 .set_mac_address = efx_ef10_set_mac_address,
4168 .tso_versions = efx_ef10_tso_versions,
4170 .get_phys_port_id = efx_ef10_get_phys_port_id,
4171 .revision = EFX_REV_HUNT_A0,
4172 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
4173 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
4174 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
4175 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
4176 .can_rx_scatter = true,
4177 .always_rx_scatter = true,
4178 .option_descriptors = true,
4179 .min_interrupt_mode = EFX_INT_MODE_LEGACY,
4180 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
4181 .offload_features = EF10_OFFLOAD_FEATURES,
4183 .max_rx_ip_filters = EFX_MCDI_FILTER_TBL_ROWS,
4184 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
4185 1 << HWTSTAMP_FILTER_ALL,
4186 .rx_hash_key_size = 40,
4187 .check_caps = ef10_check_caps,
4188 .print_additional_fwver = efx_ef10_print_additional_fwver,
4189 .sensor_event = efx_mcdi_sensor_event,