1 // SPDX-License-Identifier: GPL-2.0
2 /* SuperH Ethernet device driver
4 * Copyright (C) 2014 Renesas Electronics Corporation
5 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu
6 * Copyright (C) 2008-2014 Renesas Solutions Corp.
7 * Copyright (C) 2013-2017 Cogent Embedded, Inc.
8 * Copyright (C) 2014 Codethink Limited
11 #include <linux/module.h>
12 #include <linux/kernel.h>
13 #include <linux/spinlock.h>
14 #include <linux/interrupt.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/etherdevice.h>
17 #include <linux/delay.h>
18 #include <linux/platform_device.h>
19 #include <linux/mdio-bitbang.h>
20 #include <linux/netdevice.h>
22 #include <linux/of_device.h>
23 #include <linux/of_irq.h>
24 #include <linux/of_net.h>
25 #include <linux/phy.h>
26 #include <linux/cache.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/slab.h>
30 #include <linux/ethtool.h>
31 #include <linux/if_vlan.h>
32 #include <linux/sh_eth.h>
33 #include <linux/of_mdio.h>
37 #define SH_ETH_DEF_MSG_ENABLE \
43 #define SH_ETH_OFFSET_INVALID ((u16)~0)
45 #define SH_ETH_OFFSET_DEFAULTS \
46 [0 ... SH_ETH_MAX_REGISTER_OFFSET - 1] = SH_ETH_OFFSET_INVALID
48 /* use some intentionally tricky logic here to initialize the whole struct to
49 * 0xffff, but then override certain fields, requiring us to indicate that we
50 * "know" that there are overrides in this structure, and we'll need to disable
51 * that warning from W=1 builds. GCC has supported this option since 4.2.X, but
52 * the macros available to do this only define GCC 8.
55 __diag_ignore(GCC, 8, "-Woverride-init",
56 "logic to initialize all and then override some is OK");
57 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
58 SH_ETH_OFFSET_DEFAULTS,
113 [TSU_CTRST] = 0x0004,
114 [TSU_FWEN0] = 0x0010,
115 [TSU_FWEN1] = 0x0014,
117 [TSU_BSYSL0] = 0x0020,
118 [TSU_BSYSL1] = 0x0024,
119 [TSU_PRISL0] = 0x0028,
120 [TSU_PRISL1] = 0x002c,
121 [TSU_FWSL0] = 0x0030,
122 [TSU_FWSL1] = 0x0034,
123 [TSU_FWSLC] = 0x0038,
124 [TSU_QTAGM0] = 0x0040,
125 [TSU_QTAGM1] = 0x0044,
127 [TSU_FWINMK] = 0x0054,
128 [TSU_ADQT0] = 0x0048,
129 [TSU_ADQT1] = 0x004c,
130 [TSU_VTAG0] = 0x0058,
131 [TSU_VTAG1] = 0x005c,
132 [TSU_ADSBSY] = 0x0060,
134 [TSU_POST1] = 0x0070,
135 [TSU_POST2] = 0x0074,
136 [TSU_POST3] = 0x0078,
137 [TSU_POST4] = 0x007c,
138 [TSU_ADRH0] = 0x0100,
154 static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
155 SH_ETH_OFFSET_DEFAULTS,
202 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
203 SH_ETH_OFFSET_DEFAULTS,
256 static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
257 SH_ETH_OFFSET_DEFAULTS,
305 [TSU_CTRST] = 0x0004,
306 [TSU_FWEN0] = 0x0010,
307 [TSU_FWEN1] = 0x0014,
309 [TSU_BSYSL0] = 0x0020,
310 [TSU_BSYSL1] = 0x0024,
311 [TSU_PRISL0] = 0x0028,
312 [TSU_PRISL1] = 0x002c,
313 [TSU_FWSL0] = 0x0030,
314 [TSU_FWSL1] = 0x0034,
315 [TSU_FWSLC] = 0x0038,
316 [TSU_QTAGM0] = 0x0040,
317 [TSU_QTAGM1] = 0x0044,
318 [TSU_ADQT0] = 0x0048,
319 [TSU_ADQT1] = 0x004c,
321 [TSU_FWINMK] = 0x0054,
322 [TSU_ADSBSY] = 0x0060,
324 [TSU_POST1] = 0x0070,
325 [TSU_POST2] = 0x0074,
326 [TSU_POST3] = 0x0078,
327 [TSU_POST4] = 0x007c,
342 [TSU_ADRH0] = 0x0100,
346 static void sh_eth_rcv_snd_disable(struct net_device *ndev);
347 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev);
349 static void sh_eth_write(struct net_device *ndev, u32 data, int enum_index)
351 struct sh_eth_private *mdp = netdev_priv(ndev);
352 u16 offset = mdp->reg_offset[enum_index];
354 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
357 iowrite32(data, mdp->addr + offset);
360 static u32 sh_eth_read(struct net_device *ndev, int enum_index)
362 struct sh_eth_private *mdp = netdev_priv(ndev);
363 u16 offset = mdp->reg_offset[enum_index];
365 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
368 return ioread32(mdp->addr + offset);
371 static void sh_eth_modify(struct net_device *ndev, int enum_index, u32 clear,
374 sh_eth_write(ndev, (sh_eth_read(ndev, enum_index) & ~clear) | set,
378 static u16 sh_eth_tsu_get_offset(struct sh_eth_private *mdp, int enum_index)
380 return mdp->reg_offset[enum_index];
383 static void sh_eth_tsu_write(struct sh_eth_private *mdp, u32 data,
386 u16 offset = sh_eth_tsu_get_offset(mdp, enum_index);
388 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
391 iowrite32(data, mdp->tsu_addr + offset);
394 static u32 sh_eth_tsu_read(struct sh_eth_private *mdp, int enum_index)
396 u16 offset = sh_eth_tsu_get_offset(mdp, enum_index);
398 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
401 return ioread32(mdp->tsu_addr + offset);
404 static void sh_eth_soft_swap(char *src, int len)
406 #ifdef __LITTLE_ENDIAN
408 u32 *maxp = p + DIV_ROUND_UP(len, sizeof(u32));
410 for (; p < maxp; p++)
415 static void sh_eth_select_mii(struct net_device *ndev)
417 struct sh_eth_private *mdp = netdev_priv(ndev);
420 switch (mdp->phy_interface) {
421 case PHY_INTERFACE_MODE_RGMII ... PHY_INTERFACE_MODE_RGMII_TXID:
424 case PHY_INTERFACE_MODE_GMII:
427 case PHY_INTERFACE_MODE_MII:
430 case PHY_INTERFACE_MODE_RMII:
435 "PHY interface mode was not setup. Set to MII.\n");
440 sh_eth_write(ndev, value, RMII_MII);
443 static void sh_eth_set_duplex(struct net_device *ndev)
445 struct sh_eth_private *mdp = netdev_priv(ndev);
447 sh_eth_modify(ndev, ECMR, ECMR_DM, mdp->duplex ? ECMR_DM : 0);
450 static void sh_eth_chip_reset(struct net_device *ndev)
452 struct sh_eth_private *mdp = netdev_priv(ndev);
455 sh_eth_tsu_write(mdp, ARSTR_ARST, ARSTR);
459 static int sh_eth_soft_reset(struct net_device *ndev)
461 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, EDMR_SRST_ETHER);
463 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, 0);
468 static int sh_eth_check_soft_reset(struct net_device *ndev)
472 for (cnt = 100; cnt > 0; cnt--) {
473 if (!(sh_eth_read(ndev, EDMR) & EDMR_SRST_GETHER))
478 netdev_err(ndev, "Device reset failed\n");
482 static int sh_eth_soft_reset_gether(struct net_device *ndev)
484 struct sh_eth_private *mdp = netdev_priv(ndev);
487 sh_eth_write(ndev, EDSR_ENALL, EDSR);
488 sh_eth_modify(ndev, EDMR, EDMR_SRST_GETHER, EDMR_SRST_GETHER);
490 ret = sh_eth_check_soft_reset(ndev);
495 sh_eth_write(ndev, 0, TDLAR);
496 sh_eth_write(ndev, 0, TDFAR);
497 sh_eth_write(ndev, 0, TDFXR);
498 sh_eth_write(ndev, 0, TDFFR);
499 sh_eth_write(ndev, 0, RDLAR);
500 sh_eth_write(ndev, 0, RDFAR);
501 sh_eth_write(ndev, 0, RDFXR);
502 sh_eth_write(ndev, 0, RDFFR);
504 /* Reset HW CRC register */
506 sh_eth_write(ndev, 0, CSMR);
508 /* Select MII mode */
509 if (mdp->cd->select_mii)
510 sh_eth_select_mii(ndev);
515 static void sh_eth_set_rate_gether(struct net_device *ndev)
517 struct sh_eth_private *mdp = netdev_priv(ndev);
519 if (WARN_ON(!mdp->cd->gecmr))
522 switch (mdp->speed) {
523 case 10: /* 10BASE */
524 sh_eth_write(ndev, GECMR_10, GECMR);
526 case 100:/* 100BASE */
527 sh_eth_write(ndev, GECMR_100, GECMR);
529 case 1000: /* 1000BASE */
530 sh_eth_write(ndev, GECMR_1000, GECMR);
537 static struct sh_eth_cpu_data r7s72100_data = {
538 .soft_reset = sh_eth_soft_reset_gether,
540 .chip_reset = sh_eth_chip_reset,
541 .set_duplex = sh_eth_set_duplex,
543 .register_type = SH_ETH_REG_GIGABIT,
545 .edtrr_trns = EDTRR_TRNS_GETHER,
546 .ecsr_value = ECSR_ICD,
547 .ecsipr_value = ECSIPR_ICDIP,
548 .eesipr_value = EESIPR_TWB1IP | EESIPR_TWBIP | EESIPR_TC1IP |
549 EESIPR_TABTIP | EESIPR_RABTIP | EESIPR_RFCOFIP |
551 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
552 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
553 EESIPR_RMAFIP | EESIPR_RRFIP |
554 EESIPR_RTLFIP | EESIPR_RTSFIP |
555 EESIPR_PREIP | EESIPR_CERFIP,
557 .tx_check = EESR_TC1 | EESR_FTC,
558 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
559 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
561 .fdr_value = 0x0000070f,
578 static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
580 sh_eth_chip_reset(ndev);
582 sh_eth_select_mii(ndev);
586 static struct sh_eth_cpu_data r8a7740_data = {
587 .soft_reset = sh_eth_soft_reset_gether,
589 .chip_reset = sh_eth_chip_reset_r8a7740,
590 .set_duplex = sh_eth_set_duplex,
591 .set_rate = sh_eth_set_rate_gether,
593 .register_type = SH_ETH_REG_GIGABIT,
595 .edtrr_trns = EDTRR_TRNS_GETHER,
596 .ecsr_value = ECSR_ICD | ECSR_MPD,
597 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
598 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
599 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
600 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
601 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
602 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
603 EESIPR_CEEFIP | EESIPR_CELFIP |
604 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
605 EESIPR_PREIP | EESIPR_CERFIP,
607 .tx_check = EESR_TC1 | EESR_FTC,
608 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
609 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
611 .fdr_value = 0x0000070f,
631 /* There is CPU dependent code */
632 static void sh_eth_set_rate_rcar(struct net_device *ndev)
634 struct sh_eth_private *mdp = netdev_priv(ndev);
636 switch (mdp->speed) {
637 case 10: /* 10BASE */
638 sh_eth_modify(ndev, ECMR, ECMR_ELB, 0);
640 case 100:/* 100BASE */
641 sh_eth_modify(ndev, ECMR, ECMR_ELB, ECMR_ELB);
647 static struct sh_eth_cpu_data rcar_gen1_data = {
648 .soft_reset = sh_eth_soft_reset,
650 .set_duplex = sh_eth_set_duplex,
651 .set_rate = sh_eth_set_rate_rcar,
653 .register_type = SH_ETH_REG_FAST_RCAR,
655 .edtrr_trns = EDTRR_TRNS_ETHER,
656 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
657 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
658 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP |
659 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
660 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
661 EESIPR_RMAFIP | EESIPR_RRFIP |
662 EESIPR_RTLFIP | EESIPR_RTSFIP |
663 EESIPR_PREIP | EESIPR_CERFIP,
665 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO,
666 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
667 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
668 .fdr_value = 0x00000f0f,
677 /* R-Car Gen2 and RZ/G1 */
678 static struct sh_eth_cpu_data rcar_gen2_data = {
679 .soft_reset = sh_eth_soft_reset,
681 .set_duplex = sh_eth_set_duplex,
682 .set_rate = sh_eth_set_rate_rcar,
684 .register_type = SH_ETH_REG_FAST_RCAR,
686 .edtrr_trns = EDTRR_TRNS_ETHER,
687 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD | ECSR_MPD,
688 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP |
690 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP |
691 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
692 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
693 EESIPR_RMAFIP | EESIPR_RRFIP |
694 EESIPR_RTLFIP | EESIPR_RTSFIP |
695 EESIPR_PREIP | EESIPR_CERFIP,
697 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO,
698 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
699 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
700 .fdr_value = 0x00000f0f,
702 .trscer_err_mask = DESC_I_RINT8,
714 static struct sh_eth_cpu_data r8a77980_data = {
715 .soft_reset = sh_eth_soft_reset_gether,
717 .set_duplex = sh_eth_set_duplex,
718 .set_rate = sh_eth_set_rate_gether,
720 .register_type = SH_ETH_REG_GIGABIT,
722 .edtrr_trns = EDTRR_TRNS_GETHER,
723 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD | ECSR_MPD,
724 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP |
726 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
727 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
728 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
729 EESIPR_RMAFIP | EESIPR_RRFIP |
730 EESIPR_RTLFIP | EESIPR_RTSFIP |
731 EESIPR_PREIP | EESIPR_CERFIP,
733 .tx_check = EESR_FTC | EESR_CD | EESR_TRO,
734 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
735 EESR_RFE | EESR_RDE | EESR_RFRMER |
736 EESR_TFE | EESR_TDE | EESR_ECI,
737 .fdr_value = 0x0000070f,
758 static struct sh_eth_cpu_data r7s9210_data = {
759 .soft_reset = sh_eth_soft_reset,
761 .set_duplex = sh_eth_set_duplex,
762 .set_rate = sh_eth_set_rate_rcar,
764 .register_type = SH_ETH_REG_FAST_SH4,
766 .edtrr_trns = EDTRR_TRNS_ETHER,
767 .ecsr_value = ECSR_ICD,
768 .ecsipr_value = ECSIPR_ICDIP,
769 .eesipr_value = EESIPR_TWBIP | EESIPR_TABTIP | EESIPR_RABTIP |
770 EESIPR_RFCOFIP | EESIPR_ECIIP | EESIPR_FTCIP |
771 EESIPR_TDEIP | EESIPR_TFUFIP | EESIPR_FRIP |
772 EESIPR_RDEIP | EESIPR_RFOFIP | EESIPR_CNDIP |
773 EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP |
774 EESIPR_RMAFIP | EESIPR_RRFIP | EESIPR_RTLFIP |
775 EESIPR_RTSFIP | EESIPR_PREIP | EESIPR_CERFIP,
777 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO,
778 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
779 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
781 .fdr_value = 0x0000070f,
791 #endif /* CONFIG_OF */
793 static void sh_eth_set_rate_sh7724(struct net_device *ndev)
795 struct sh_eth_private *mdp = netdev_priv(ndev);
797 switch (mdp->speed) {
798 case 10: /* 10BASE */
799 sh_eth_modify(ndev, ECMR, ECMR_RTM, 0);
801 case 100:/* 100BASE */
802 sh_eth_modify(ndev, ECMR, ECMR_RTM, ECMR_RTM);
808 static struct sh_eth_cpu_data sh7724_data = {
809 .soft_reset = sh_eth_soft_reset,
811 .set_duplex = sh_eth_set_duplex,
812 .set_rate = sh_eth_set_rate_sh7724,
814 .register_type = SH_ETH_REG_FAST_SH4,
816 .edtrr_trns = EDTRR_TRNS_ETHER,
817 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
818 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
819 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP |
820 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
821 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
822 EESIPR_RMAFIP | EESIPR_RRFIP |
823 EESIPR_RTLFIP | EESIPR_RTSFIP |
824 EESIPR_PREIP | EESIPR_CERFIP,
826 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO,
827 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
828 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
837 static void sh_eth_set_rate_sh7757(struct net_device *ndev)
839 struct sh_eth_private *mdp = netdev_priv(ndev);
841 switch (mdp->speed) {
842 case 10: /* 10BASE */
843 sh_eth_write(ndev, 0, RTRATE);
845 case 100:/* 100BASE */
846 sh_eth_write(ndev, 1, RTRATE);
852 static struct sh_eth_cpu_data sh7757_data = {
853 .soft_reset = sh_eth_soft_reset,
855 .set_duplex = sh_eth_set_duplex,
856 .set_rate = sh_eth_set_rate_sh7757,
858 .register_type = SH_ETH_REG_FAST_SH4,
860 .edtrr_trns = EDTRR_TRNS_ETHER,
861 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
862 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
863 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
864 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
865 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
866 EESIPR_CEEFIP | EESIPR_CELFIP |
867 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
868 EESIPR_PREIP | EESIPR_CERFIP,
870 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO,
871 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
872 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
874 .irq_flags = IRQF_SHARED,
885 #define SH_GIGA_ETH_BASE 0xfee00000UL
886 #define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
887 #define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
888 static void sh_eth_chip_reset_giga(struct net_device *ndev)
890 u32 mahr[2], malr[2];
893 /* save MAHR and MALR */
894 for (i = 0; i < 2; i++) {
895 malr[i] = ioread32((void *)GIGA_MALR(i));
896 mahr[i] = ioread32((void *)GIGA_MAHR(i));
899 sh_eth_chip_reset(ndev);
901 /* restore MAHR and MALR */
902 for (i = 0; i < 2; i++) {
903 iowrite32(malr[i], (void *)GIGA_MALR(i));
904 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
908 static void sh_eth_set_rate_giga(struct net_device *ndev)
910 struct sh_eth_private *mdp = netdev_priv(ndev);
912 if (WARN_ON(!mdp->cd->gecmr))
915 switch (mdp->speed) {
916 case 10: /* 10BASE */
917 sh_eth_write(ndev, 0x00000000, GECMR);
919 case 100:/* 100BASE */
920 sh_eth_write(ndev, 0x00000010, GECMR);
922 case 1000: /* 1000BASE */
923 sh_eth_write(ndev, 0x00000020, GECMR);
928 /* SH7757(GETHERC) */
929 static struct sh_eth_cpu_data sh7757_data_giga = {
930 .soft_reset = sh_eth_soft_reset_gether,
932 .chip_reset = sh_eth_chip_reset_giga,
933 .set_duplex = sh_eth_set_duplex,
934 .set_rate = sh_eth_set_rate_giga,
936 .register_type = SH_ETH_REG_GIGABIT,
938 .edtrr_trns = EDTRR_TRNS_GETHER,
939 .ecsr_value = ECSR_ICD | ECSR_MPD,
940 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
941 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
942 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
943 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
944 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
945 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
946 EESIPR_CEEFIP | EESIPR_CELFIP |
947 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
948 EESIPR_PREIP | EESIPR_CERFIP,
950 .tx_check = EESR_TC1 | EESR_FTC,
951 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
952 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
954 .fdr_value = 0x0000072f,
956 .irq_flags = IRQF_SHARED,
973 static struct sh_eth_cpu_data sh7734_data = {
974 .soft_reset = sh_eth_soft_reset_gether,
976 .chip_reset = sh_eth_chip_reset,
977 .set_duplex = sh_eth_set_duplex,
978 .set_rate = sh_eth_set_rate_gether,
980 .register_type = SH_ETH_REG_GIGABIT,
982 .edtrr_trns = EDTRR_TRNS_GETHER,
983 .ecsr_value = ECSR_ICD | ECSR_MPD,
984 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
985 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
986 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
987 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
988 EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP |
989 EESIPR_RMAFIP | EESIPR_CEEFIP | EESIPR_CELFIP |
990 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
991 EESIPR_PREIP | EESIPR_CERFIP,
993 .tx_check = EESR_TC1 | EESR_FTC,
994 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
995 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
1016 static struct sh_eth_cpu_data sh7763_data = {
1017 .soft_reset = sh_eth_soft_reset_gether,
1019 .chip_reset = sh_eth_chip_reset,
1020 .set_duplex = sh_eth_set_duplex,
1021 .set_rate = sh_eth_set_rate_gether,
1023 .register_type = SH_ETH_REG_GIGABIT,
1025 .edtrr_trns = EDTRR_TRNS_GETHER,
1026 .ecsr_value = ECSR_ICD | ECSR_MPD,
1027 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
1028 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
1029 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
1030 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
1031 EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP |
1032 EESIPR_RMAFIP | EESIPR_CEEFIP | EESIPR_CELFIP |
1033 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
1034 EESIPR_PREIP | EESIPR_CERFIP,
1036 .tx_check = EESR_TC1 | EESR_FTC,
1037 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
1038 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
1050 .irq_flags = IRQF_SHARED,
1057 static struct sh_eth_cpu_data sh7619_data = {
1058 .soft_reset = sh_eth_soft_reset,
1060 .register_type = SH_ETH_REG_FAST_SH3_SH2,
1062 .edtrr_trns = EDTRR_TRNS_ETHER,
1063 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
1064 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
1065 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
1066 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
1067 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
1068 EESIPR_CEEFIP | EESIPR_CELFIP |
1069 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
1070 EESIPR_PREIP | EESIPR_CERFIP,
1078 static struct sh_eth_cpu_data sh771x_data = {
1079 .soft_reset = sh_eth_soft_reset,
1081 .register_type = SH_ETH_REG_FAST_SH3_SH2,
1083 .edtrr_trns = EDTRR_TRNS_ETHER,
1084 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
1085 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
1086 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
1087 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
1088 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
1089 EESIPR_CEEFIP | EESIPR_CELFIP |
1090 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
1091 EESIPR_PREIP | EESIPR_CERFIP,
1096 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
1098 if (!cd->ecsr_value)
1099 cd->ecsr_value = DEFAULT_ECSR_INIT;
1101 if (!cd->ecsipr_value)
1102 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
1104 if (!cd->fcftr_value)
1105 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF |
1106 DEFAULT_FIFO_F_D_RFD;
1109 cd->fdr_value = DEFAULT_FDR_INIT;
1112 cd->tx_check = DEFAULT_TX_CHECK;
1114 if (!cd->eesr_err_check)
1115 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
1117 if (!cd->trscer_err_mask)
1118 cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK;
1121 static void sh_eth_set_receive_align(struct sk_buff *skb)
1123 uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1);
1126 skb_reserve(skb, SH_ETH_RX_ALIGN - reserve);
1129 /* Program the hardware MAC address from dev->dev_addr. */
1130 static void update_mac_address(struct net_device *ndev)
1133 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
1134 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
1136 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
1139 /* Get MAC address from SuperH MAC address register
1141 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
1142 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
1143 * When you want use this device, you must set MAC address in bootloader.
1146 static void read_mac_address(struct net_device *ndev, unsigned char *mac)
1148 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
1149 memcpy(ndev->dev_addr, mac, ETH_ALEN);
1151 u32 mahr = sh_eth_read(ndev, MAHR);
1152 u32 malr = sh_eth_read(ndev, MALR);
1154 ndev->dev_addr[0] = (mahr >> 24) & 0xFF;
1155 ndev->dev_addr[1] = (mahr >> 16) & 0xFF;
1156 ndev->dev_addr[2] = (mahr >> 8) & 0xFF;
1157 ndev->dev_addr[3] = (mahr >> 0) & 0xFF;
1158 ndev->dev_addr[4] = (malr >> 8) & 0xFF;
1159 ndev->dev_addr[5] = (malr >> 0) & 0xFF;
1164 void (*set_gate)(void *addr);
1165 struct mdiobb_ctrl ctrl;
1169 static void sh_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set)
1171 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1174 if (bitbang->set_gate)
1175 bitbang->set_gate(bitbang->addr);
1177 pir = ioread32(bitbang->addr);
1182 iowrite32(pir, bitbang->addr);
1185 /* Data I/O pin control */
1186 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1188 sh_mdio_ctrl(ctrl, PIR_MMD, bit);
1192 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
1194 sh_mdio_ctrl(ctrl, PIR_MDO, bit);
1198 static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
1200 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1202 if (bitbang->set_gate)
1203 bitbang->set_gate(bitbang->addr);
1205 return (ioread32(bitbang->addr) & PIR_MDI) != 0;
1208 /* MDC pin control */
1209 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1211 sh_mdio_ctrl(ctrl, PIR_MDC, bit);
1214 /* mdio bus control struct */
1215 static const struct mdiobb_ops bb_ops = {
1216 .owner = THIS_MODULE,
1217 .set_mdc = sh_mdc_ctrl,
1218 .set_mdio_dir = sh_mmd_ctrl,
1219 .set_mdio_data = sh_set_mdio,
1220 .get_mdio_data = sh_get_mdio,
1223 /* free Tx skb function */
1224 static int sh_eth_tx_free(struct net_device *ndev, bool sent_only)
1226 struct sh_eth_private *mdp = netdev_priv(ndev);
1227 struct sh_eth_txdesc *txdesc;
1232 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
1233 entry = mdp->dirty_tx % mdp->num_tx_ring;
1234 txdesc = &mdp->tx_ring[entry];
1235 sent = !(txdesc->status & cpu_to_le32(TD_TACT));
1236 if (sent_only && !sent)
1238 /* TACT bit must be checked before all the following reads */
1240 netif_info(mdp, tx_done, ndev,
1241 "tx entry %d status 0x%08x\n",
1242 entry, le32_to_cpu(txdesc->status));
1243 /* Free the original skb. */
1244 if (mdp->tx_skbuff[entry]) {
1245 dma_unmap_single(&mdp->pdev->dev,
1246 le32_to_cpu(txdesc->addr),
1247 le32_to_cpu(txdesc->len) >> 16,
1249 dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1250 mdp->tx_skbuff[entry] = NULL;
1253 txdesc->status = cpu_to_le32(TD_TFP);
1254 if (entry >= mdp->num_tx_ring - 1)
1255 txdesc->status |= cpu_to_le32(TD_TDLE);
1258 ndev->stats.tx_packets++;
1259 ndev->stats.tx_bytes += le32_to_cpu(txdesc->len) >> 16;
1265 /* free skb and descriptor buffer */
1266 static void sh_eth_ring_free(struct net_device *ndev)
1268 struct sh_eth_private *mdp = netdev_priv(ndev);
1272 for (i = 0; i < mdp->num_rx_ring; i++) {
1273 if (mdp->rx_skbuff[i]) {
1274 struct sh_eth_rxdesc *rxdesc = &mdp->rx_ring[i];
1276 dma_unmap_single(&mdp->pdev->dev,
1277 le32_to_cpu(rxdesc->addr),
1278 ALIGN(mdp->rx_buf_sz, 32),
1282 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1283 dma_free_coherent(&mdp->pdev->dev, ringsize, mdp->rx_ring,
1285 mdp->rx_ring = NULL;
1288 /* Free Rx skb ringbuffer */
1289 if (mdp->rx_skbuff) {
1290 for (i = 0; i < mdp->num_rx_ring; i++)
1291 dev_kfree_skb(mdp->rx_skbuff[i]);
1293 kfree(mdp->rx_skbuff);
1294 mdp->rx_skbuff = NULL;
1297 sh_eth_tx_free(ndev, false);
1299 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1300 dma_free_coherent(&mdp->pdev->dev, ringsize, mdp->tx_ring,
1302 mdp->tx_ring = NULL;
1305 /* Free Tx skb ringbuffer */
1306 kfree(mdp->tx_skbuff);
1307 mdp->tx_skbuff = NULL;
1310 /* format skb and descriptor buffer */
1311 static void sh_eth_ring_format(struct net_device *ndev)
1313 struct sh_eth_private *mdp = netdev_priv(ndev);
1315 struct sk_buff *skb;
1316 struct sh_eth_rxdesc *rxdesc = NULL;
1317 struct sh_eth_txdesc *txdesc = NULL;
1318 int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
1319 int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
1320 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
1321 dma_addr_t dma_addr;
1329 memset(mdp->rx_ring, 0, rx_ringsize);
1331 /* build Rx ring buffer */
1332 for (i = 0; i < mdp->num_rx_ring; i++) {
1334 mdp->rx_skbuff[i] = NULL;
1335 skb = netdev_alloc_skb(ndev, skbuff_size);
1338 sh_eth_set_receive_align(skb);
1340 /* The size of the buffer is a multiple of 32 bytes. */
1341 buf_len = ALIGN(mdp->rx_buf_sz, 32);
1342 dma_addr = dma_map_single(&mdp->pdev->dev, skb->data, buf_len,
1344 if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) {
1348 mdp->rx_skbuff[i] = skb;
1351 rxdesc = &mdp->rx_ring[i];
1352 rxdesc->len = cpu_to_le32(buf_len << 16);
1353 rxdesc->addr = cpu_to_le32(dma_addr);
1354 rxdesc->status = cpu_to_le32(RD_RACT | RD_RFP);
1356 /* Rx descriptor address set */
1358 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
1359 if (mdp->cd->xdfar_rw)
1360 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
1364 mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
1366 /* Mark the last entry as wrapping the ring. */
1368 rxdesc->status |= cpu_to_le32(RD_RDLE);
1370 memset(mdp->tx_ring, 0, tx_ringsize);
1372 /* build Tx ring buffer */
1373 for (i = 0; i < mdp->num_tx_ring; i++) {
1374 mdp->tx_skbuff[i] = NULL;
1375 txdesc = &mdp->tx_ring[i];
1376 txdesc->status = cpu_to_le32(TD_TFP);
1377 txdesc->len = cpu_to_le32(0);
1379 /* Tx descriptor address set */
1380 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
1381 if (mdp->cd->xdfar_rw)
1382 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
1386 txdesc->status |= cpu_to_le32(TD_TDLE);
1389 /* Get skb and descriptor buffer */
1390 static int sh_eth_ring_init(struct net_device *ndev)
1392 struct sh_eth_private *mdp = netdev_priv(ndev);
1393 int rx_ringsize, tx_ringsize;
1395 /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
1396 * card needs room to do 8 byte alignment, +2 so we can reserve
1397 * the first 2 bytes, and +16 gets room for the status word from the
1400 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1401 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
1402 if (mdp->cd->rpadir)
1403 mdp->rx_buf_sz += NET_IP_ALIGN;
1405 /* Allocate RX and TX skb rings */
1406 mdp->rx_skbuff = kcalloc(mdp->num_rx_ring, sizeof(*mdp->rx_skbuff),
1408 if (!mdp->rx_skbuff)
1411 mdp->tx_skbuff = kcalloc(mdp->num_tx_ring, sizeof(*mdp->tx_skbuff),
1413 if (!mdp->tx_skbuff)
1416 /* Allocate all Rx descriptors. */
1417 rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1418 mdp->rx_ring = dma_alloc_coherent(&mdp->pdev->dev, rx_ringsize,
1419 &mdp->rx_desc_dma, GFP_KERNEL);
1425 /* Allocate all Tx descriptors. */
1426 tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1427 mdp->tx_ring = dma_alloc_coherent(&mdp->pdev->dev, tx_ringsize,
1428 &mdp->tx_desc_dma, GFP_KERNEL);
1434 /* Free Rx and Tx skb ring buffer and DMA buffer */
1435 sh_eth_ring_free(ndev);
1440 static int sh_eth_dev_init(struct net_device *ndev)
1442 struct sh_eth_private *mdp = netdev_priv(ndev);
1446 ret = mdp->cd->soft_reset(ndev);
1450 if (mdp->cd->rmiimode)
1451 sh_eth_write(ndev, 0x1, RMIIMODE);
1453 /* Descriptor format */
1454 sh_eth_ring_format(ndev);
1455 if (mdp->cd->rpadir)
1456 sh_eth_write(ndev, NET_IP_ALIGN << 16, RPADIR);
1458 /* all sh_eth int mask */
1459 sh_eth_write(ndev, 0, EESIPR);
1461 #if defined(__LITTLE_ENDIAN)
1462 if (mdp->cd->hw_swap)
1463 sh_eth_write(ndev, EDMR_EL, EDMR);
1466 sh_eth_write(ndev, 0, EDMR);
1469 sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1470 sh_eth_write(ndev, 0, TFTR);
1472 /* Frame recv control (enable multiple-packets per rx irq) */
1473 sh_eth_write(ndev, RMCR_RNC, RMCR);
1475 sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER);
1477 /* DMA transfer burst mode */
1479 sh_eth_modify(ndev, EDMR, EDMR_NBST, EDMR_NBST);
1481 /* Burst cycle count upper-limit */
1483 sh_eth_write(ndev, 0x800, BCULR);
1485 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
1487 if (!mdp->cd->no_trimd)
1488 sh_eth_write(ndev, 0, TRIMD);
1490 /* Recv frame limit set register */
1491 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1494 sh_eth_modify(ndev, EESR, 0, 0);
1495 mdp->irq_enabled = true;
1496 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1498 /* EMAC Mode: PAUSE prohibition; Duplex; RX Checksum; TX; RX */
1499 sh_eth_write(ndev, ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) |
1500 (ndev->features & NETIF_F_RXCSUM ? ECMR_RCSC : 0) |
1501 ECMR_TE | ECMR_RE, ECMR);
1503 if (mdp->cd->set_rate)
1504 mdp->cd->set_rate(ndev);
1506 /* E-MAC Status Register clear */
1507 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
1509 /* E-MAC Interrupt Enable register */
1510 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
1512 /* Set MAC address */
1513 update_mac_address(ndev);
1517 sh_eth_write(ndev, 1, APR);
1519 sh_eth_write(ndev, 1, MPR);
1520 if (mdp->cd->tpauser)
1521 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
1523 /* Setting the Rx mode will start the Rx process. */
1524 sh_eth_write(ndev, EDRRR_R, EDRRR);
1529 static void sh_eth_dev_exit(struct net_device *ndev)
1531 struct sh_eth_private *mdp = netdev_priv(ndev);
1534 /* Deactivate all TX descriptors, so DMA should stop at next
1535 * packet boundary if it's currently running
1537 for (i = 0; i < mdp->num_tx_ring; i++)
1538 mdp->tx_ring[i].status &= ~cpu_to_le32(TD_TACT);
1540 /* Disable TX FIFO egress to MAC */
1541 sh_eth_rcv_snd_disable(ndev);
1543 /* Stop RX DMA at next packet boundary */
1544 sh_eth_write(ndev, 0, EDRRR);
1546 /* Aside from TX DMA, we can't tell when the hardware is
1547 * really stopped, so we need to reset to make sure.
1548 * Before doing that, wait for long enough to *probably*
1549 * finish transmitting the last packet and poll stats.
1551 msleep(2); /* max frame time at 10 Mbps < 1250 us */
1552 sh_eth_get_stats(ndev);
1553 mdp->cd->soft_reset(ndev);
1555 /* Set the RMII mode again if required */
1556 if (mdp->cd->rmiimode)
1557 sh_eth_write(ndev, 0x1, RMIIMODE);
1559 /* Set MAC address again */
1560 update_mac_address(ndev);
1563 static void sh_eth_rx_csum(struct sk_buff *skb)
1567 /* The hardware checksum is 2 bytes appended to packet data */
1568 if (unlikely(skb->len < sizeof(__sum16)))
1570 hw_csum = skb_tail_pointer(skb) - sizeof(__sum16);
1571 skb->csum = csum_unfold((__force __sum16)get_unaligned_le16(hw_csum));
1572 skb->ip_summed = CHECKSUM_COMPLETE;
1573 skb_trim(skb, skb->len - sizeof(__sum16));
1576 /* Packet receive function */
1577 static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
1579 struct sh_eth_private *mdp = netdev_priv(ndev);
1580 struct sh_eth_rxdesc *rxdesc;
1582 int entry = mdp->cur_rx % mdp->num_rx_ring;
1583 int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
1585 struct sk_buff *skb;
1587 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
1588 dma_addr_t dma_addr;
1592 boguscnt = min(boguscnt, *quota);
1594 rxdesc = &mdp->rx_ring[entry];
1595 while (!(rxdesc->status & cpu_to_le32(RD_RACT))) {
1596 /* RACT bit must be checked before all the following reads */
1598 desc_status = le32_to_cpu(rxdesc->status);
1599 pkt_len = le32_to_cpu(rxdesc->len) & RD_RFL;
1604 netif_info(mdp, rx_status, ndev,
1605 "rx entry %d status 0x%08x len %d\n",
1606 entry, desc_status, pkt_len);
1608 if (!(desc_status & RDFEND))
1609 ndev->stats.rx_length_errors++;
1611 /* In case of almost all GETHER/ETHERs, the Receive Frame State
1612 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
1613 * bit 0. However, in case of the R8A7740 and R7S72100
1614 * the RFS bits are from bit 25 to bit 16. So, the
1615 * driver needs right shifting by 16.
1620 skb = mdp->rx_skbuff[entry];
1621 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1622 RD_RFS5 | RD_RFS6 | RD_RFS10)) {
1623 ndev->stats.rx_errors++;
1624 if (desc_status & RD_RFS1)
1625 ndev->stats.rx_crc_errors++;
1626 if (desc_status & RD_RFS2)
1627 ndev->stats.rx_frame_errors++;
1628 if (desc_status & RD_RFS3)
1629 ndev->stats.rx_length_errors++;
1630 if (desc_status & RD_RFS4)
1631 ndev->stats.rx_length_errors++;
1632 if (desc_status & RD_RFS6)
1633 ndev->stats.rx_missed_errors++;
1634 if (desc_status & RD_RFS10)
1635 ndev->stats.rx_over_errors++;
1637 dma_addr = le32_to_cpu(rxdesc->addr);
1638 if (!mdp->cd->hw_swap)
1640 phys_to_virt(ALIGN(dma_addr, 4)),
1642 mdp->rx_skbuff[entry] = NULL;
1643 if (mdp->cd->rpadir)
1644 skb_reserve(skb, NET_IP_ALIGN);
1645 dma_unmap_single(&mdp->pdev->dev, dma_addr,
1646 ALIGN(mdp->rx_buf_sz, 32),
1648 skb_put(skb, pkt_len);
1649 skb->protocol = eth_type_trans(skb, ndev);
1650 if (ndev->features & NETIF_F_RXCSUM)
1651 sh_eth_rx_csum(skb);
1652 netif_receive_skb(skb);
1653 ndev->stats.rx_packets++;
1654 ndev->stats.rx_bytes += pkt_len;
1655 if (desc_status & RD_RFS8)
1656 ndev->stats.multicast++;
1658 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
1659 rxdesc = &mdp->rx_ring[entry];
1662 /* Refill the Rx ring buffers. */
1663 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
1664 entry = mdp->dirty_rx % mdp->num_rx_ring;
1665 rxdesc = &mdp->rx_ring[entry];
1666 /* The size of the buffer is 32 byte boundary. */
1667 buf_len = ALIGN(mdp->rx_buf_sz, 32);
1668 rxdesc->len = cpu_to_le32(buf_len << 16);
1670 if (mdp->rx_skbuff[entry] == NULL) {
1671 skb = netdev_alloc_skb(ndev, skbuff_size);
1673 break; /* Better luck next round. */
1674 sh_eth_set_receive_align(skb);
1675 dma_addr = dma_map_single(&mdp->pdev->dev, skb->data,
1676 buf_len, DMA_FROM_DEVICE);
1677 if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) {
1681 mdp->rx_skbuff[entry] = skb;
1683 skb_checksum_none_assert(skb);
1684 rxdesc->addr = cpu_to_le32(dma_addr);
1686 dma_wmb(); /* RACT bit must be set after all the above writes */
1687 if (entry >= mdp->num_rx_ring - 1)
1689 cpu_to_le32(RD_RACT | RD_RFP | RD_RDLE);
1691 rxdesc->status |= cpu_to_le32(RD_RACT | RD_RFP);
1694 /* Restart Rx engine if stopped. */
1695 /* If we don't need to check status, don't. -KDU */
1696 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
1697 /* fix the values for the next receiving if RDE is set */
1698 if (intr_status & EESR_RDE && !mdp->cd->no_xdfar) {
1699 u32 count = (sh_eth_read(ndev, RDFAR) -
1700 sh_eth_read(ndev, RDLAR)) >> 4;
1702 mdp->cur_rx = count;
1703 mdp->dirty_rx = count;
1705 sh_eth_write(ndev, EDRRR_R, EDRRR);
1708 *quota -= limit - boguscnt - 1;
1713 static void sh_eth_rcv_snd_disable(struct net_device *ndev)
1715 /* disable tx and rx */
1716 sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0);
1719 static void sh_eth_rcv_snd_enable(struct net_device *ndev)
1721 /* enable tx and rx */
1722 sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE);
1725 /* E-MAC interrupt handler */
1726 static void sh_eth_emac_interrupt(struct net_device *ndev)
1728 struct sh_eth_private *mdp = netdev_priv(ndev);
1732 felic_stat = sh_eth_read(ndev, ECSR) & sh_eth_read(ndev, ECSIPR);
1733 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */
1734 if (felic_stat & ECSR_ICD)
1735 ndev->stats.tx_carrier_errors++;
1736 if (felic_stat & ECSR_MPD)
1737 pm_wakeup_event(&mdp->pdev->dev, 0);
1738 if (felic_stat & ECSR_LCHNG) {
1740 if (mdp->cd->no_psr || mdp->no_ether_link)
1742 link_stat = sh_eth_read(ndev, PSR);
1743 if (mdp->ether_link_active_low)
1744 link_stat = ~link_stat;
1745 if (!(link_stat & PHY_ST_LINK)) {
1746 sh_eth_rcv_snd_disable(ndev);
1749 sh_eth_modify(ndev, EESIPR, EESIPR_ECIIP, 0);
1751 sh_eth_modify(ndev, ECSR, 0, 0);
1752 sh_eth_modify(ndev, EESIPR, EESIPR_ECIIP, EESIPR_ECIIP);
1753 /* enable tx and rx */
1754 sh_eth_rcv_snd_enable(ndev);
1759 /* error control function */
1760 static void sh_eth_error(struct net_device *ndev, u32 intr_status)
1762 struct sh_eth_private *mdp = netdev_priv(ndev);
1765 if (intr_status & EESR_TWB) {
1766 /* Unused write back interrupt */
1767 if (intr_status & EESR_TABT) { /* Transmit Abort int */
1768 ndev->stats.tx_aborted_errors++;
1769 netif_err(mdp, tx_err, ndev, "Transmit Abort\n");
1773 if (intr_status & EESR_RABT) {
1774 /* Receive Abort int */
1775 if (intr_status & EESR_RFRMER) {
1776 /* Receive Frame Overflow int */
1777 ndev->stats.rx_frame_errors++;
1781 if (intr_status & EESR_TDE) {
1782 /* Transmit Descriptor Empty int */
1783 ndev->stats.tx_fifo_errors++;
1784 netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n");
1787 if (intr_status & EESR_TFE) {
1788 /* FIFO under flow */
1789 ndev->stats.tx_fifo_errors++;
1790 netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n");
1793 if (intr_status & EESR_RDE) {
1794 /* Receive Descriptor Empty int */
1795 ndev->stats.rx_over_errors++;
1798 if (intr_status & EESR_RFE) {
1799 /* Receive FIFO Overflow int */
1800 ndev->stats.rx_fifo_errors++;
1803 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1805 ndev->stats.tx_fifo_errors++;
1806 netif_err(mdp, tx_err, ndev, "Address Error\n");
1809 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1810 if (mdp->cd->no_ade)
1812 if (intr_status & mask) {
1814 u32 edtrr = sh_eth_read(ndev, EDTRR);
1817 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1818 intr_status, mdp->cur_tx, mdp->dirty_tx,
1819 (u32)ndev->state, edtrr);
1820 /* dirty buffer free */
1821 sh_eth_tx_free(ndev, true);
1824 if (edtrr ^ mdp->cd->edtrr_trns) {
1826 sh_eth_write(ndev, mdp->cd->edtrr_trns, EDTRR);
1829 netif_wake_queue(ndev);
1833 static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1835 struct net_device *ndev = netdev;
1836 struct sh_eth_private *mdp = netdev_priv(ndev);
1837 struct sh_eth_cpu_data *cd = mdp->cd;
1838 irqreturn_t ret = IRQ_NONE;
1839 u32 intr_status, intr_enable;
1841 spin_lock(&mdp->lock);
1843 /* Get interrupt status */
1844 intr_status = sh_eth_read(ndev, EESR);
1845 /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1846 * enabled since it's the one that comes thru regardless of the mask,
1847 * and we need to fully handle it in sh_eth_emac_interrupt() in order
1848 * to quench it as it doesn't get cleared by just writing 1 to the ECI
1851 intr_enable = sh_eth_read(ndev, EESIPR);
1852 intr_status &= intr_enable | EESIPR_ECIIP;
1853 if (intr_status & (EESR_RX_CHECK | cd->tx_check | EESR_ECI |
1854 cd->eesr_err_check))
1859 if (unlikely(!mdp->irq_enabled)) {
1860 sh_eth_write(ndev, 0, EESIPR);
1864 if (intr_status & EESR_RX_CHECK) {
1865 if (napi_schedule_prep(&mdp->napi)) {
1866 /* Mask Rx interrupts */
1867 sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
1869 __napi_schedule(&mdp->napi);
1872 "ignoring interrupt, status 0x%08x, mask 0x%08x.\n",
1873 intr_status, intr_enable);
1878 if (intr_status & cd->tx_check) {
1879 /* Clear Tx interrupts */
1880 sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
1882 sh_eth_tx_free(ndev, true);
1883 netif_wake_queue(ndev);
1886 /* E-MAC interrupt */
1887 if (intr_status & EESR_ECI)
1888 sh_eth_emac_interrupt(ndev);
1890 if (intr_status & cd->eesr_err_check) {
1891 /* Clear error interrupts */
1892 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
1894 sh_eth_error(ndev, intr_status);
1898 spin_unlock(&mdp->lock);
1903 static int sh_eth_poll(struct napi_struct *napi, int budget)
1905 struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
1907 struct net_device *ndev = napi->dev;
1912 intr_status = sh_eth_read(ndev, EESR);
1913 if (!(intr_status & EESR_RX_CHECK))
1915 /* Clear Rx interrupts */
1916 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
1918 if (sh_eth_rx(ndev, intr_status, "a))
1922 napi_complete(napi);
1924 /* Reenable Rx interrupts */
1925 if (mdp->irq_enabled)
1926 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1928 return budget - quota;
1931 /* PHY state control function */
1932 static void sh_eth_adjust_link(struct net_device *ndev)
1934 struct sh_eth_private *mdp = netdev_priv(ndev);
1935 struct phy_device *phydev = ndev->phydev;
1936 unsigned long flags;
1939 spin_lock_irqsave(&mdp->lock, flags);
1941 /* Disable TX and RX right over here, if E-MAC change is ignored */
1942 if (mdp->cd->no_psr || mdp->no_ether_link)
1943 sh_eth_rcv_snd_disable(ndev);
1946 if (phydev->duplex != mdp->duplex) {
1948 mdp->duplex = phydev->duplex;
1949 if (mdp->cd->set_duplex)
1950 mdp->cd->set_duplex(ndev);
1953 if (phydev->speed != mdp->speed) {
1955 mdp->speed = phydev->speed;
1956 if (mdp->cd->set_rate)
1957 mdp->cd->set_rate(ndev);
1960 sh_eth_modify(ndev, ECMR, ECMR_TXF, 0);
1962 mdp->link = phydev->link;
1964 } else if (mdp->link) {
1971 /* Enable TX and RX right over here, if E-MAC change is ignored */
1972 if ((mdp->cd->no_psr || mdp->no_ether_link) && phydev->link)
1973 sh_eth_rcv_snd_enable(ndev);
1975 spin_unlock_irqrestore(&mdp->lock, flags);
1977 if (new_state && netif_msg_link(mdp))
1978 phy_print_status(phydev);
1981 /* PHY init function */
1982 static int sh_eth_phy_init(struct net_device *ndev)
1984 struct device_node *np = ndev->dev.parent->of_node;
1985 struct sh_eth_private *mdp = netdev_priv(ndev);
1986 struct phy_device *phydev;
1992 /* Try connect to PHY */
1994 struct device_node *pn;
1996 pn = of_parse_phandle(np, "phy-handle", 0);
1997 phydev = of_phy_connect(ndev, pn,
1998 sh_eth_adjust_link, 0,
1999 mdp->phy_interface);
2003 phydev = ERR_PTR(-ENOENT);
2005 char phy_id[MII_BUS_ID_SIZE + 3];
2007 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
2008 mdp->mii_bus->id, mdp->phy_id);
2010 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
2011 mdp->phy_interface);
2014 if (IS_ERR(phydev)) {
2015 netdev_err(ndev, "failed to connect PHY\n");
2016 return PTR_ERR(phydev);
2019 /* mask with MAC supported features */
2020 if (mdp->cd->register_type != SH_ETH_REG_GIGABIT) {
2021 int err = phy_set_max_speed(phydev, SPEED_100);
2023 netdev_err(ndev, "failed to limit PHY to 100 Mbit/s\n");
2024 phy_disconnect(phydev);
2029 phy_attached_info(phydev);
2034 /* PHY control start function */
2035 static int sh_eth_phy_start(struct net_device *ndev)
2039 ret = sh_eth_phy_init(ndev);
2043 phy_start(ndev->phydev);
2048 /* If it is ever necessary to increase SH_ETH_REG_DUMP_MAX_REGS, the
2049 * version must be bumped as well. Just adding registers up to that
2050 * limit is fine, as long as the existing register indices don't
2053 #define SH_ETH_REG_DUMP_VERSION 1
2054 #define SH_ETH_REG_DUMP_MAX_REGS 256
2056 static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf)
2058 struct sh_eth_private *mdp = netdev_priv(ndev);
2059 struct sh_eth_cpu_data *cd = mdp->cd;
2063 BUILD_BUG_ON(SH_ETH_MAX_REGISTER_OFFSET > SH_ETH_REG_DUMP_MAX_REGS);
2065 /* Dump starts with a bitmap that tells ethtool which
2066 * registers are defined for this chip.
2068 len = DIV_ROUND_UP(SH_ETH_REG_DUMP_MAX_REGS, 32);
2076 /* Add a register to the dump, if it has a defined offset.
2077 * This automatically skips most undefined registers, but for
2078 * some it is also necessary to check a capability flag in
2079 * struct sh_eth_cpu_data.
2081 #define mark_reg_valid(reg) valid_map[reg / 32] |= 1U << (reg % 32)
2082 #define add_reg_from(reg, read_expr) do { \
2083 if (mdp->reg_offset[reg] != SH_ETH_OFFSET_INVALID) { \
2085 mark_reg_valid(reg); \
2086 *buf++ = read_expr; \
2091 #define add_reg(reg) add_reg_from(reg, sh_eth_read(ndev, reg))
2092 #define add_tsu_reg(reg) add_reg_from(reg, sh_eth_tsu_read(mdp, reg))
2148 if (!cd->no_tx_cntrs) {
2171 add_tsu_reg(TSU_CTRST);
2172 if (cd->dual_port) {
2173 add_tsu_reg(TSU_FWEN0);
2174 add_tsu_reg(TSU_FWEN1);
2175 add_tsu_reg(TSU_FCM);
2176 add_tsu_reg(TSU_BSYSL0);
2177 add_tsu_reg(TSU_BSYSL1);
2178 add_tsu_reg(TSU_PRISL0);
2179 add_tsu_reg(TSU_PRISL1);
2180 add_tsu_reg(TSU_FWSL0);
2181 add_tsu_reg(TSU_FWSL1);
2183 add_tsu_reg(TSU_FWSLC);
2184 if (cd->dual_port) {
2185 add_tsu_reg(TSU_QTAGM0);
2186 add_tsu_reg(TSU_QTAGM1);
2187 add_tsu_reg(TSU_FWSR);
2188 add_tsu_reg(TSU_FWINMK);
2189 add_tsu_reg(TSU_ADQT0);
2190 add_tsu_reg(TSU_ADQT1);
2191 add_tsu_reg(TSU_VTAG0);
2192 add_tsu_reg(TSU_VTAG1);
2194 add_tsu_reg(TSU_ADSBSY);
2195 add_tsu_reg(TSU_TEN);
2196 add_tsu_reg(TSU_POST1);
2197 add_tsu_reg(TSU_POST2);
2198 add_tsu_reg(TSU_POST3);
2199 add_tsu_reg(TSU_POST4);
2200 /* This is the start of a table, not just a single register. */
2204 mark_reg_valid(TSU_ADRH0);
2205 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES * 2; i++)
2206 *buf++ = ioread32(mdp->tsu_addr +
2207 mdp->reg_offset[TSU_ADRH0] +
2210 len += SH_ETH_TSU_CAM_ENTRIES * 2;
2213 #undef mark_reg_valid
2221 static int sh_eth_get_regs_len(struct net_device *ndev)
2223 return __sh_eth_get_regs(ndev, NULL);
2226 static void sh_eth_get_regs(struct net_device *ndev, struct ethtool_regs *regs,
2229 struct sh_eth_private *mdp = netdev_priv(ndev);
2231 regs->version = SH_ETH_REG_DUMP_VERSION;
2233 pm_runtime_get_sync(&mdp->pdev->dev);
2234 __sh_eth_get_regs(ndev, buf);
2235 pm_runtime_put_sync(&mdp->pdev->dev);
2238 static u32 sh_eth_get_msglevel(struct net_device *ndev)
2240 struct sh_eth_private *mdp = netdev_priv(ndev);
2241 return mdp->msg_enable;
2244 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
2246 struct sh_eth_private *mdp = netdev_priv(ndev);
2247 mdp->msg_enable = value;
2250 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
2251 "rx_current", "tx_current",
2252 "rx_dirty", "tx_dirty",
2254 #define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
2256 static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
2260 return SH_ETH_STATS_LEN;
2266 static void sh_eth_get_ethtool_stats(struct net_device *ndev,
2267 struct ethtool_stats *stats, u64 *data)
2269 struct sh_eth_private *mdp = netdev_priv(ndev);
2272 /* device-specific stats */
2273 data[i++] = mdp->cur_rx;
2274 data[i++] = mdp->cur_tx;
2275 data[i++] = mdp->dirty_rx;
2276 data[i++] = mdp->dirty_tx;
2279 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
2281 switch (stringset) {
2283 memcpy(data, *sh_eth_gstrings_stats,
2284 sizeof(sh_eth_gstrings_stats));
2289 static void sh_eth_get_ringparam(struct net_device *ndev,
2290 struct ethtool_ringparam *ring)
2292 struct sh_eth_private *mdp = netdev_priv(ndev);
2294 ring->rx_max_pending = RX_RING_MAX;
2295 ring->tx_max_pending = TX_RING_MAX;
2296 ring->rx_pending = mdp->num_rx_ring;
2297 ring->tx_pending = mdp->num_tx_ring;
2300 static int sh_eth_set_ringparam(struct net_device *ndev,
2301 struct ethtool_ringparam *ring)
2303 struct sh_eth_private *mdp = netdev_priv(ndev);
2306 if (ring->tx_pending > TX_RING_MAX ||
2307 ring->rx_pending > RX_RING_MAX ||
2308 ring->tx_pending < TX_RING_MIN ||
2309 ring->rx_pending < RX_RING_MIN)
2311 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
2314 if (netif_running(ndev)) {
2315 netif_device_detach(ndev);
2316 netif_tx_disable(ndev);
2318 /* Serialise with the interrupt handler and NAPI, then
2319 * disable interrupts. We have to clear the
2320 * irq_enabled flag first to ensure that interrupts
2321 * won't be re-enabled.
2323 mdp->irq_enabled = false;
2324 synchronize_irq(ndev->irq);
2325 napi_synchronize(&mdp->napi);
2326 sh_eth_write(ndev, 0x0000, EESIPR);
2328 sh_eth_dev_exit(ndev);
2330 /* Free all the skbuffs in the Rx queue and the DMA buffers. */
2331 sh_eth_ring_free(ndev);
2334 /* Set new parameters */
2335 mdp->num_rx_ring = ring->rx_pending;
2336 mdp->num_tx_ring = ring->tx_pending;
2338 if (netif_running(ndev)) {
2339 ret = sh_eth_ring_init(ndev);
2341 netdev_err(ndev, "%s: sh_eth_ring_init failed.\n",
2345 ret = sh_eth_dev_init(ndev);
2347 netdev_err(ndev, "%s: sh_eth_dev_init failed.\n",
2352 netif_device_attach(ndev);
2358 static void sh_eth_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2360 struct sh_eth_private *mdp = netdev_priv(ndev);
2365 if (mdp->cd->magic) {
2366 wol->supported = WAKE_MAGIC;
2367 wol->wolopts = mdp->wol_enabled ? WAKE_MAGIC : 0;
2371 static int sh_eth_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2373 struct sh_eth_private *mdp = netdev_priv(ndev);
2375 if (!mdp->cd->magic || wol->wolopts & ~WAKE_MAGIC)
2378 mdp->wol_enabled = !!(wol->wolopts & WAKE_MAGIC);
2380 device_set_wakeup_enable(&mdp->pdev->dev, mdp->wol_enabled);
2385 static const struct ethtool_ops sh_eth_ethtool_ops = {
2386 .get_regs_len = sh_eth_get_regs_len,
2387 .get_regs = sh_eth_get_regs,
2388 .nway_reset = phy_ethtool_nway_reset,
2389 .get_msglevel = sh_eth_get_msglevel,
2390 .set_msglevel = sh_eth_set_msglevel,
2391 .get_link = ethtool_op_get_link,
2392 .get_strings = sh_eth_get_strings,
2393 .get_ethtool_stats = sh_eth_get_ethtool_stats,
2394 .get_sset_count = sh_eth_get_sset_count,
2395 .get_ringparam = sh_eth_get_ringparam,
2396 .set_ringparam = sh_eth_set_ringparam,
2397 .get_link_ksettings = phy_ethtool_get_link_ksettings,
2398 .set_link_ksettings = phy_ethtool_set_link_ksettings,
2399 .get_wol = sh_eth_get_wol,
2400 .set_wol = sh_eth_set_wol,
2403 /* network device open function */
2404 static int sh_eth_open(struct net_device *ndev)
2406 struct sh_eth_private *mdp = netdev_priv(ndev);
2409 pm_runtime_get_sync(&mdp->pdev->dev);
2411 napi_enable(&mdp->napi);
2413 ret = request_irq(ndev->irq, sh_eth_interrupt,
2414 mdp->cd->irq_flags, ndev->name, ndev);
2416 netdev_err(ndev, "Can not assign IRQ number\n");
2420 /* Descriptor set */
2421 ret = sh_eth_ring_init(ndev);
2426 ret = sh_eth_dev_init(ndev);
2430 /* PHY control start*/
2431 ret = sh_eth_phy_start(ndev);
2435 netif_start_queue(ndev);
2442 free_irq(ndev->irq, ndev);
2444 napi_disable(&mdp->napi);
2445 pm_runtime_put_sync(&mdp->pdev->dev);
2449 /* Timeout function */
2450 static void sh_eth_tx_timeout(struct net_device *ndev, unsigned int txqueue)
2452 struct sh_eth_private *mdp = netdev_priv(ndev);
2453 struct sh_eth_rxdesc *rxdesc;
2456 netif_stop_queue(ndev);
2458 netif_err(mdp, timer, ndev,
2459 "transmit timed out, status %8.8x, resetting...\n",
2460 sh_eth_read(ndev, EESR));
2462 /* tx_errors count up */
2463 ndev->stats.tx_errors++;
2465 /* Free all the skbuffs in the Rx queue. */
2466 for (i = 0; i < mdp->num_rx_ring; i++) {
2467 rxdesc = &mdp->rx_ring[i];
2468 rxdesc->status = cpu_to_le32(0);
2469 rxdesc->addr = cpu_to_le32(0xBADF00D0);
2470 dev_kfree_skb(mdp->rx_skbuff[i]);
2471 mdp->rx_skbuff[i] = NULL;
2473 for (i = 0; i < mdp->num_tx_ring; i++) {
2474 dev_kfree_skb(mdp->tx_skbuff[i]);
2475 mdp->tx_skbuff[i] = NULL;
2479 sh_eth_dev_init(ndev);
2481 netif_start_queue(ndev);
2484 /* Packet transmit function */
2485 static netdev_tx_t sh_eth_start_xmit(struct sk_buff *skb,
2486 struct net_device *ndev)
2488 struct sh_eth_private *mdp = netdev_priv(ndev);
2489 struct sh_eth_txdesc *txdesc;
2490 dma_addr_t dma_addr;
2492 unsigned long flags;
2494 spin_lock_irqsave(&mdp->lock, flags);
2495 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
2496 if (!sh_eth_tx_free(ndev, true)) {
2497 netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n");
2498 netif_stop_queue(ndev);
2499 spin_unlock_irqrestore(&mdp->lock, flags);
2500 return NETDEV_TX_BUSY;
2503 spin_unlock_irqrestore(&mdp->lock, flags);
2505 if (skb_put_padto(skb, ETH_ZLEN))
2506 return NETDEV_TX_OK;
2508 entry = mdp->cur_tx % mdp->num_tx_ring;
2509 mdp->tx_skbuff[entry] = skb;
2510 txdesc = &mdp->tx_ring[entry];
2512 if (!mdp->cd->hw_swap)
2513 sh_eth_soft_swap(PTR_ALIGN(skb->data, 4), skb->len + 2);
2514 dma_addr = dma_map_single(&mdp->pdev->dev, skb->data, skb->len,
2516 if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) {
2518 return NETDEV_TX_OK;
2520 txdesc->addr = cpu_to_le32(dma_addr);
2521 txdesc->len = cpu_to_le32(skb->len << 16);
2523 dma_wmb(); /* TACT bit must be set after all the above writes */
2524 if (entry >= mdp->num_tx_ring - 1)
2525 txdesc->status |= cpu_to_le32(TD_TACT | TD_TDLE);
2527 txdesc->status |= cpu_to_le32(TD_TACT);
2531 if (!(sh_eth_read(ndev, EDTRR) & mdp->cd->edtrr_trns))
2532 sh_eth_write(ndev, mdp->cd->edtrr_trns, EDTRR);
2534 return NETDEV_TX_OK;
2537 /* The statistics registers have write-clear behaviour, which means we
2538 * will lose any increment between the read and write. We mitigate
2539 * this by only clearing when we read a non-zero value, so we will
2540 * never falsely report a total of zero.
2543 sh_eth_update_stat(struct net_device *ndev, unsigned long *stat, int reg)
2545 u32 delta = sh_eth_read(ndev, reg);
2549 sh_eth_write(ndev, 0, reg);
2553 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2555 struct sh_eth_private *mdp = netdev_priv(ndev);
2557 if (mdp->cd->no_tx_cntrs)
2558 return &ndev->stats;
2560 if (!mdp->is_opened)
2561 return &ndev->stats;
2563 sh_eth_update_stat(ndev, &ndev->stats.tx_dropped, TROCR);
2564 sh_eth_update_stat(ndev, &ndev->stats.collisions, CDCR);
2565 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, LCCR);
2567 if (mdp->cd->cexcr) {
2568 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2570 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2573 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2577 return &ndev->stats;
2580 /* device close function */
2581 static int sh_eth_close(struct net_device *ndev)
2583 struct sh_eth_private *mdp = netdev_priv(ndev);
2585 netif_stop_queue(ndev);
2587 /* Serialise with the interrupt handler and NAPI, then disable
2588 * interrupts. We have to clear the irq_enabled flag first to
2589 * ensure that interrupts won't be re-enabled.
2591 mdp->irq_enabled = false;
2592 synchronize_irq(ndev->irq);
2593 napi_disable(&mdp->napi);
2594 sh_eth_write(ndev, 0x0000, EESIPR);
2596 sh_eth_dev_exit(ndev);
2598 /* PHY Disconnect */
2600 phy_stop(ndev->phydev);
2601 phy_disconnect(ndev->phydev);
2604 free_irq(ndev->irq, ndev);
2606 /* Free all the skbuffs in the Rx queue and the DMA buffer. */
2607 sh_eth_ring_free(ndev);
2609 pm_runtime_put_sync(&mdp->pdev->dev);
2616 static int sh_eth_change_mtu(struct net_device *ndev, int new_mtu)
2618 if (netif_running(ndev))
2621 ndev->mtu = new_mtu;
2622 netdev_update_features(ndev);
2627 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2628 static u32 sh_eth_tsu_get_post_mask(int entry)
2630 return 0x0f << (28 - ((entry % 8) * 4));
2633 static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2635 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2638 static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2641 struct sh_eth_private *mdp = netdev_priv(ndev);
2642 int reg = TSU_POST1 + entry / 8;
2645 tmp = sh_eth_tsu_read(mdp, reg);
2646 sh_eth_tsu_write(mdp, tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg);
2649 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2652 struct sh_eth_private *mdp = netdev_priv(ndev);
2653 int reg = TSU_POST1 + entry / 8;
2654 u32 post_mask, ref_mask, tmp;
2656 post_mask = sh_eth_tsu_get_post_mask(entry);
2657 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2659 tmp = sh_eth_tsu_read(mdp, reg);
2660 sh_eth_tsu_write(mdp, tmp & ~post_mask, reg);
2662 /* If other port enables, the function returns "true" */
2663 return tmp & ref_mask;
2666 static int sh_eth_tsu_busy(struct net_device *ndev)
2668 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2669 struct sh_eth_private *mdp = netdev_priv(ndev);
2671 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2675 netdev_err(ndev, "%s: timeout\n", __func__);
2683 static int sh_eth_tsu_write_entry(struct net_device *ndev, u16 offset,
2686 struct sh_eth_private *mdp = netdev_priv(ndev);
2689 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2690 iowrite32(val, mdp->tsu_addr + offset);
2691 if (sh_eth_tsu_busy(ndev) < 0)
2694 val = addr[4] << 8 | addr[5];
2695 iowrite32(val, mdp->tsu_addr + offset + 4);
2696 if (sh_eth_tsu_busy(ndev) < 0)
2702 static void sh_eth_tsu_read_entry(struct net_device *ndev, u16 offset, u8 *addr)
2704 struct sh_eth_private *mdp = netdev_priv(ndev);
2707 val = ioread32(mdp->tsu_addr + offset);
2708 addr[0] = (val >> 24) & 0xff;
2709 addr[1] = (val >> 16) & 0xff;
2710 addr[2] = (val >> 8) & 0xff;
2711 addr[3] = val & 0xff;
2712 val = ioread32(mdp->tsu_addr + offset + 4);
2713 addr[4] = (val >> 8) & 0xff;
2714 addr[5] = val & 0xff;
2718 static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2720 struct sh_eth_private *mdp = netdev_priv(ndev);
2721 u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2723 u8 c_addr[ETH_ALEN];
2725 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2726 sh_eth_tsu_read_entry(ndev, reg_offset, c_addr);
2727 if (ether_addr_equal(addr, c_addr))
2734 static int sh_eth_tsu_find_empty(struct net_device *ndev)
2739 memset(blank, 0, sizeof(blank));
2740 entry = sh_eth_tsu_find_entry(ndev, blank);
2741 return (entry < 0) ? -ENOMEM : entry;
2744 static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2747 struct sh_eth_private *mdp = netdev_priv(ndev);
2748 u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2752 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2753 ~(1 << (31 - entry)), TSU_TEN);
2755 memset(blank, 0, sizeof(blank));
2756 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2762 static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2764 struct sh_eth_private *mdp = netdev_priv(ndev);
2765 u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2771 i = sh_eth_tsu_find_entry(ndev, addr);
2773 /* No entry found, create one */
2774 i = sh_eth_tsu_find_empty(ndev);
2777 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2781 /* Enable the entry */
2782 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2783 (1 << (31 - i)), TSU_TEN);
2786 /* Entry found or created, enable POST */
2787 sh_eth_tsu_enable_cam_entry_post(ndev, i);
2792 static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2794 struct sh_eth_private *mdp = netdev_priv(ndev);
2800 i = sh_eth_tsu_find_entry(ndev, addr);
2803 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2806 /* Disable the entry if both ports was disabled */
2807 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2815 static int sh_eth_tsu_purge_all(struct net_device *ndev)
2817 struct sh_eth_private *mdp = netdev_priv(ndev);
2823 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2824 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2827 /* Disable the entry if both ports was disabled */
2828 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2836 static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2838 struct sh_eth_private *mdp = netdev_priv(ndev);
2839 u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2846 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2847 sh_eth_tsu_read_entry(ndev, reg_offset, addr);
2848 if (is_multicast_ether_addr(addr))
2849 sh_eth_tsu_del_entry(ndev, addr);
2853 /* Update promiscuous flag and multicast filter */
2854 static void sh_eth_set_rx_mode(struct net_device *ndev)
2856 struct sh_eth_private *mdp = netdev_priv(ndev);
2859 unsigned long flags;
2861 spin_lock_irqsave(&mdp->lock, flags);
2862 /* Initial condition is MCT = 1, PRM = 0.
2863 * Depending on ndev->flags, set PRM or clear MCT
2865 ecmr_bits = sh_eth_read(ndev, ECMR) & ~ECMR_PRM;
2867 ecmr_bits |= ECMR_MCT;
2869 if (!(ndev->flags & IFF_MULTICAST)) {
2870 sh_eth_tsu_purge_mcast(ndev);
2873 if (ndev->flags & IFF_ALLMULTI) {
2874 sh_eth_tsu_purge_mcast(ndev);
2875 ecmr_bits &= ~ECMR_MCT;
2879 if (ndev->flags & IFF_PROMISC) {
2880 sh_eth_tsu_purge_all(ndev);
2881 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2882 } else if (mdp->cd->tsu) {
2883 struct netdev_hw_addr *ha;
2884 netdev_for_each_mc_addr(ha, ndev) {
2885 if (mcast_all && is_multicast_ether_addr(ha->addr))
2888 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2890 sh_eth_tsu_purge_mcast(ndev);
2891 ecmr_bits &= ~ECMR_MCT;
2898 /* update the ethernet mode */
2899 sh_eth_write(ndev, ecmr_bits, ECMR);
2901 spin_unlock_irqrestore(&mdp->lock, flags);
2904 static void sh_eth_set_rx_csum(struct net_device *ndev, bool enable)
2906 struct sh_eth_private *mdp = netdev_priv(ndev);
2907 unsigned long flags;
2909 spin_lock_irqsave(&mdp->lock, flags);
2911 /* Disable TX and RX */
2912 sh_eth_rcv_snd_disable(ndev);
2914 /* Modify RX Checksum setting */
2915 sh_eth_modify(ndev, ECMR, ECMR_RCSC, enable ? ECMR_RCSC : 0);
2917 /* Enable TX and RX */
2918 sh_eth_rcv_snd_enable(ndev);
2920 spin_unlock_irqrestore(&mdp->lock, flags);
2923 static int sh_eth_set_features(struct net_device *ndev,
2924 netdev_features_t features)
2926 netdev_features_t changed = ndev->features ^ features;
2927 struct sh_eth_private *mdp = netdev_priv(ndev);
2929 if (changed & NETIF_F_RXCSUM && mdp->cd->rx_csum)
2930 sh_eth_set_rx_csum(ndev, features & NETIF_F_RXCSUM);
2932 ndev->features = features;
2937 static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2945 static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2946 __be16 proto, u16 vid)
2948 struct sh_eth_private *mdp = netdev_priv(ndev);
2949 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2951 if (unlikely(!mdp->cd->tsu))
2954 /* No filtering if vid = 0 */
2958 mdp->vlan_num_ids++;
2960 /* The controller has one VLAN tag HW filter. So, if the filter is
2961 * already enabled, the driver disables it and the filte
2963 if (mdp->vlan_num_ids > 1) {
2964 /* disable VLAN filter */
2965 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2969 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2975 static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2976 __be16 proto, u16 vid)
2978 struct sh_eth_private *mdp = netdev_priv(ndev);
2979 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2981 if (unlikely(!mdp->cd->tsu))
2984 /* No filtering if vid = 0 */
2988 mdp->vlan_num_ids--;
2989 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2994 /* SuperH's TSU register init function */
2995 static void sh_eth_tsu_init(struct sh_eth_private *mdp)
2997 if (!mdp->cd->dual_port) {
2998 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2999 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL,
3000 TSU_FWSLC); /* Enable POST registers */
3004 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */
3005 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */
3006 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */
3007 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
3008 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
3009 sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
3010 sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
3011 sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
3012 sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
3013 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
3014 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */
3015 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */
3016 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */
3017 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */
3018 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
3019 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */
3020 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */
3021 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */
3022 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */
3025 /* MDIO bus release function */
3026 static int sh_mdio_release(struct sh_eth_private *mdp)
3028 /* unregister mdio bus */
3029 mdiobus_unregister(mdp->mii_bus);
3031 /* free bitbang info */
3032 free_mdio_bitbang(mdp->mii_bus);
3037 /* MDIO bus init function */
3038 static int sh_mdio_init(struct sh_eth_private *mdp,
3039 struct sh_eth_plat_data *pd)
3042 struct bb_info *bitbang;
3043 struct platform_device *pdev = mdp->pdev;
3044 struct device *dev = &mdp->pdev->dev;
3046 /* create bit control struct for PHY */
3047 bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL);
3052 bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
3053 bitbang->set_gate = pd->set_mdio_gate;
3054 bitbang->ctrl.ops = &bb_ops;
3056 /* MII controller setting */
3057 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
3061 /* Hook up MII support for ethtool */
3062 mdp->mii_bus->name = "sh_mii";
3063 mdp->mii_bus->parent = dev;
3064 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
3065 pdev->name, pdev->id);
3067 /* register MDIO bus */
3068 if (pd->phy_irq > 0)
3069 mdp->mii_bus->irq[pd->phy] = pd->phy_irq;
3071 ret = of_mdiobus_register(mdp->mii_bus, dev->of_node);
3078 free_mdio_bitbang(mdp->mii_bus);
3082 static const u16 *sh_eth_get_register_offset(int register_type)
3084 const u16 *reg_offset = NULL;
3086 switch (register_type) {
3087 case SH_ETH_REG_GIGABIT:
3088 reg_offset = sh_eth_offset_gigabit;
3090 case SH_ETH_REG_FAST_RCAR:
3091 reg_offset = sh_eth_offset_fast_rcar;
3093 case SH_ETH_REG_FAST_SH4:
3094 reg_offset = sh_eth_offset_fast_sh4;
3096 case SH_ETH_REG_FAST_SH3_SH2:
3097 reg_offset = sh_eth_offset_fast_sh3_sh2;
3104 static const struct net_device_ops sh_eth_netdev_ops = {
3105 .ndo_open = sh_eth_open,
3106 .ndo_stop = sh_eth_close,
3107 .ndo_start_xmit = sh_eth_start_xmit,
3108 .ndo_get_stats = sh_eth_get_stats,
3109 .ndo_set_rx_mode = sh_eth_set_rx_mode,
3110 .ndo_tx_timeout = sh_eth_tx_timeout,
3111 .ndo_do_ioctl = phy_do_ioctl_running,
3112 .ndo_change_mtu = sh_eth_change_mtu,
3113 .ndo_validate_addr = eth_validate_addr,
3114 .ndo_set_mac_address = eth_mac_addr,
3115 .ndo_set_features = sh_eth_set_features,
3118 static const struct net_device_ops sh_eth_netdev_ops_tsu = {
3119 .ndo_open = sh_eth_open,
3120 .ndo_stop = sh_eth_close,
3121 .ndo_start_xmit = sh_eth_start_xmit,
3122 .ndo_get_stats = sh_eth_get_stats,
3123 .ndo_set_rx_mode = sh_eth_set_rx_mode,
3124 .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid,
3125 .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid,
3126 .ndo_tx_timeout = sh_eth_tx_timeout,
3127 .ndo_do_ioctl = phy_do_ioctl_running,
3128 .ndo_change_mtu = sh_eth_change_mtu,
3129 .ndo_validate_addr = eth_validate_addr,
3130 .ndo_set_mac_address = eth_mac_addr,
3131 .ndo_set_features = sh_eth_set_features,
3135 static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
3137 struct device_node *np = dev->of_node;
3138 struct sh_eth_plat_data *pdata;
3139 phy_interface_t interface;
3140 const char *mac_addr;
3143 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
3147 ret = of_get_phy_mode(np, &interface);
3150 pdata->phy_interface = interface;
3152 mac_addr = of_get_mac_address(np);
3153 if (!IS_ERR(mac_addr))
3154 ether_addr_copy(pdata->mac_addr, mac_addr);
3156 pdata->no_ether_link =
3157 of_property_read_bool(np, "renesas,no-ether-link");
3158 pdata->ether_link_active_low =
3159 of_property_read_bool(np, "renesas,ether-link-active-low");
3164 static const struct of_device_id sh_eth_match_table[] = {
3165 { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data },
3166 { .compatible = "renesas,ether-r8a7743", .data = &rcar_gen2_data },
3167 { .compatible = "renesas,ether-r8a7745", .data = &rcar_gen2_data },
3168 { .compatible = "renesas,ether-r8a7778", .data = &rcar_gen1_data },
3169 { .compatible = "renesas,ether-r8a7779", .data = &rcar_gen1_data },
3170 { .compatible = "renesas,ether-r8a7790", .data = &rcar_gen2_data },
3171 { .compatible = "renesas,ether-r8a7791", .data = &rcar_gen2_data },
3172 { .compatible = "renesas,ether-r8a7793", .data = &rcar_gen2_data },
3173 { .compatible = "renesas,ether-r8a7794", .data = &rcar_gen2_data },
3174 { .compatible = "renesas,gether-r8a77980", .data = &r8a77980_data },
3175 { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data },
3176 { .compatible = "renesas,ether-r7s9210", .data = &r7s9210_data },
3177 { .compatible = "renesas,rcar-gen1-ether", .data = &rcar_gen1_data },
3178 { .compatible = "renesas,rcar-gen2-ether", .data = &rcar_gen2_data },
3181 MODULE_DEVICE_TABLE(of, sh_eth_match_table);
3183 static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
3189 static int sh_eth_drv_probe(struct platform_device *pdev)
3191 struct resource *res;
3192 struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev);
3193 const struct platform_device_id *id = platform_get_device_id(pdev);
3194 struct sh_eth_private *mdp;
3195 struct net_device *ndev;
3199 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3201 ndev = alloc_etherdev(sizeof(struct sh_eth_private));
3205 pm_runtime_enable(&pdev->dev);
3206 pm_runtime_get_sync(&pdev->dev);
3208 ret = platform_get_irq(pdev, 0);
3213 SET_NETDEV_DEV(ndev, &pdev->dev);
3215 mdp = netdev_priv(ndev);
3216 mdp->num_tx_ring = TX_RING_SIZE;
3217 mdp->num_rx_ring = RX_RING_SIZE;
3218 mdp->addr = devm_ioremap_resource(&pdev->dev, res);
3219 if (IS_ERR(mdp->addr)) {
3220 ret = PTR_ERR(mdp->addr);
3224 ndev->base_addr = res->start;
3226 spin_lock_init(&mdp->lock);
3229 if (pdev->dev.of_node)
3230 pd = sh_eth_parse_dt(&pdev->dev);
3232 dev_err(&pdev->dev, "no platform data\n");
3238 mdp->phy_id = pd->phy;
3239 mdp->phy_interface = pd->phy_interface;
3240 mdp->no_ether_link = pd->no_ether_link;
3241 mdp->ether_link_active_low = pd->ether_link_active_low;
3245 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
3247 mdp->cd = (struct sh_eth_cpu_data *)of_device_get_match_data(&pdev->dev);
3249 mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type);
3250 if (!mdp->reg_offset) {
3251 dev_err(&pdev->dev, "Unknown register type (%d)\n",
3252 mdp->cd->register_type);
3256 sh_eth_set_default_cpu_data(mdp->cd);
3258 /* User's manual states max MTU should be 2048 but due to the
3259 * alignment calculations in sh_eth_ring_init() the practical
3260 * MTU is a bit less. Maybe this can be optimized some more.
3262 ndev->max_mtu = 2000 - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN);
3263 ndev->min_mtu = ETH_MIN_MTU;
3265 if (mdp->cd->rx_csum) {
3266 ndev->features = NETIF_F_RXCSUM;
3267 ndev->hw_features = NETIF_F_RXCSUM;
3272 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
3274 ndev->netdev_ops = &sh_eth_netdev_ops;
3275 ndev->ethtool_ops = &sh_eth_ethtool_ops;
3276 ndev->watchdog_timeo = TX_TIMEOUT;
3278 /* debug message level */
3279 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
3281 /* read and set MAC address */
3282 read_mac_address(ndev, pd->mac_addr);
3283 if (!is_valid_ether_addr(ndev->dev_addr)) {
3284 dev_warn(&pdev->dev,
3285 "no valid MAC address supplied, using a random one.\n");
3286 eth_hw_addr_random(ndev);
3290 int port = pdev->id < 0 ? 0 : pdev->id % 2;
3291 struct resource *rtsu;
3293 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
3295 dev_err(&pdev->dev, "no TSU resource\n");
3299 /* We can only request the TSU region for the first port
3300 * of the two sharing this TSU for the probe to succeed...
3303 !devm_request_mem_region(&pdev->dev, rtsu->start,
3304 resource_size(rtsu),
3305 dev_name(&pdev->dev))) {
3306 dev_err(&pdev->dev, "can't request TSU resource.\n");
3310 /* ioremap the TSU registers */
3311 mdp->tsu_addr = devm_ioremap(&pdev->dev, rtsu->start,
3312 resource_size(rtsu));
3313 if (!mdp->tsu_addr) {
3314 dev_err(&pdev->dev, "TSU region ioremap() failed.\n");
3319 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
3321 /* Need to init only the first port of the two sharing a TSU */
3323 if (mdp->cd->chip_reset)
3324 mdp->cd->chip_reset(ndev);
3326 /* TSU init (Init only)*/
3327 sh_eth_tsu_init(mdp);
3331 if (mdp->cd->rmiimode)
3332 sh_eth_write(ndev, 0x1, RMIIMODE);
3335 ret = sh_mdio_init(mdp, pd);
3337 if (ret != -EPROBE_DEFER)
3338 dev_err(&pdev->dev, "MDIO init failed: %d\n", ret);
3342 netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
3344 /* network device register */
3345 ret = register_netdev(ndev);
3350 device_set_wakeup_capable(&pdev->dev, 1);
3352 /* print device information */
3353 netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n",
3354 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
3356 pm_runtime_put(&pdev->dev);
3357 platform_set_drvdata(pdev, ndev);
3362 netif_napi_del(&mdp->napi);
3363 sh_mdio_release(mdp);
3369 pm_runtime_put(&pdev->dev);
3370 pm_runtime_disable(&pdev->dev);
3374 static int sh_eth_drv_remove(struct platform_device *pdev)
3376 struct net_device *ndev = platform_get_drvdata(pdev);
3377 struct sh_eth_private *mdp = netdev_priv(ndev);
3379 unregister_netdev(ndev);
3380 netif_napi_del(&mdp->napi);
3381 sh_mdio_release(mdp);
3382 pm_runtime_disable(&pdev->dev);
3389 #ifdef CONFIG_PM_SLEEP
3390 static int sh_eth_wol_setup(struct net_device *ndev)
3392 struct sh_eth_private *mdp = netdev_priv(ndev);
3394 /* Only allow ECI interrupts */
3395 synchronize_irq(ndev->irq);
3396 napi_disable(&mdp->napi);
3397 sh_eth_write(ndev, EESIPR_ECIIP, EESIPR);
3399 /* Enable MagicPacket */
3400 sh_eth_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE);
3402 return enable_irq_wake(ndev->irq);
3405 static int sh_eth_wol_restore(struct net_device *ndev)
3407 struct sh_eth_private *mdp = netdev_priv(ndev);
3410 napi_enable(&mdp->napi);
3412 /* Disable MagicPacket */
3413 sh_eth_modify(ndev, ECMR, ECMR_MPDE, 0);
3415 /* The device needs to be reset to restore MagicPacket logic
3416 * for next wakeup. If we close and open the device it will
3417 * both be reset and all registers restored. This is what
3418 * happens during suspend and resume without WoL enabled.
3420 ret = sh_eth_close(ndev);
3423 ret = sh_eth_open(ndev);
3427 return disable_irq_wake(ndev->irq);
3430 static int sh_eth_suspend(struct device *dev)
3432 struct net_device *ndev = dev_get_drvdata(dev);
3433 struct sh_eth_private *mdp = netdev_priv(ndev);
3436 if (!netif_running(ndev))
3439 netif_device_detach(ndev);
3441 if (mdp->wol_enabled)
3442 ret = sh_eth_wol_setup(ndev);
3444 ret = sh_eth_close(ndev);
3449 static int sh_eth_resume(struct device *dev)
3451 struct net_device *ndev = dev_get_drvdata(dev);
3452 struct sh_eth_private *mdp = netdev_priv(ndev);
3455 if (!netif_running(ndev))
3458 if (mdp->wol_enabled)
3459 ret = sh_eth_wol_restore(ndev);
3461 ret = sh_eth_open(ndev);
3466 netif_device_attach(ndev);
3472 static int sh_eth_runtime_nop(struct device *dev)
3474 /* Runtime PM callback shared between ->runtime_suspend()
3475 * and ->runtime_resume(). Simply returns success.
3477 * This driver re-initializes all registers after
3478 * pm_runtime_get_sync() anyway so there is no need
3479 * to save and restore registers here.
3484 static const struct dev_pm_ops sh_eth_dev_pm_ops = {
3485 SET_SYSTEM_SLEEP_PM_OPS(sh_eth_suspend, sh_eth_resume)
3486 SET_RUNTIME_PM_OPS(sh_eth_runtime_nop, sh_eth_runtime_nop, NULL)
3488 #define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
3490 #define SH_ETH_PM_OPS NULL
3493 static const struct platform_device_id sh_eth_id_table[] = {
3494 { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
3495 { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
3496 { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
3497 { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
3498 { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
3499 { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
3500 { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
3503 MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
3505 static struct platform_driver sh_eth_driver = {
3506 .probe = sh_eth_drv_probe,
3507 .remove = sh_eth_drv_remove,
3508 .id_table = sh_eth_id_table,
3511 .pm = SH_ETH_PM_OPS,
3512 .of_match_table = of_match_ptr(sh_eth_match_table),
3516 module_platform_driver(sh_eth_driver);
3518 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
3519 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
3520 MODULE_LICENSE("GPL v2");