drivers/net/ethernet/renesas/sh_eth.c

   1 /*  SuperH Ethernet device driver
   2  *
   3  *  Copyright (C) 2014 Renesas Electronics Corporation
   4  *  Copyright (C) 2006-2012 Nobuhiro Iwamatsu
   5  *  Copyright (C) 2008-2014 Renesas Solutions Corp.
   6  *  Copyright (C) 2013-2017 Cogent Embedded, Inc.
   7  *  Copyright (C) 2014 Codethink Limited
   8  *
   9  *  This program is free software; you can redistribute it and/or modify it
  10  *  under the terms and conditions of the GNU General Public License,
  11  *  version 2, as published by the Free Software Foundation.
  12  *
  13  *  This program is distributed in the hope it will be useful, but WITHOUT
  14  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  16  *  more details.
  17  *
  18  *  The full GNU General Public License is included in this distribution in
  19  *  the file called "COPYING".
  20  */
  21
  22 #include <linux/module.h>
  23 #include <linux/kernel.h>
  24 #include <linux/spinlock.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/etherdevice.h>
  28 #include <linux/delay.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/mdio-bitbang.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/of.h>
  33 #include <linux/of_device.h>
  34 #include <linux/of_irq.h>
  35 #include <linux/of_net.h>
  36 #include <linux/phy.h>
  37 #include <linux/cache.h>
  38 #include <linux/io.h>
  39 #include <linux/pm_runtime.h>
  40 #include <linux/slab.h>
  41 #include <linux/ethtool.h>
  42 #include <linux/if_vlan.h>
  43 #include <linux/sh_eth.h>
  44 #include <linux/of_mdio.h>
  45
  46 #include "sh_eth.h"
  47
  48 #define SH_ETH_DEF_MSG_ENABLE \
  49                 (NETIF_MSG_LINK | \
  50                 NETIF_MSG_TIMER | \
  51                 NETIF_MSG_RX_ERR| \
  52                 NETIF_MSG_TX_ERR)
  53
  54 #define SH_ETH_OFFSET_INVALID   ((u16)~0)
  55
  56 #define SH_ETH_OFFSET_DEFAULTS                  \
  57         [0 ... SH_ETH_MAX_REGISTER_OFFSET - 1] = SH_ETH_OFFSET_INVALID
  58
  59 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
  60         SH_ETH_OFFSET_DEFAULTS,
  61
  62         [EDSR]          = 0x0000,
  63         [EDMR]          = 0x0400,
  64         [EDTRR]         = 0x0408,
  65         [EDRRR]         = 0x0410,
  66         [EESR]          = 0x0428,
  67         [EESIPR]        = 0x0430,
  68         [TDLAR]         = 0x0010,
  69         [TDFAR]         = 0x0014,
  70         [TDFXR]         = 0x0018,
  71         [TDFFR]         = 0x001c,
  72         [RDLAR]         = 0x0030,
  73         [RDFAR]         = 0x0034,
  74         [RDFXR]         = 0x0038,
  75         [RDFFR]         = 0x003c,
  76         [TRSCER]        = 0x0438,
  77         [RMFCR]         = 0x0440,
  78         [TFTR]          = 0x0448,
  79         [FDR]           = 0x0450,
  80         [RMCR]          = 0x0458,
  81         [RPADIR]        = 0x0460,
  82         [FCFTR]         = 0x0468,
  83         [CSMR]          = 0x04E4,
  84
  85         [ECMR]          = 0x0500,
  86         [ECSR]          = 0x0510,
  87         [ECSIPR]        = 0x0518,
  88         [PIR]           = 0x0520,
  89         [PSR]           = 0x0528,
  90         [PIPR]          = 0x052c,
  91         [RFLR]          = 0x0508,
  92         [APR]           = 0x0554,
  93         [MPR]           = 0x0558,
  94         [PFTCR]         = 0x055c,
  95         [PFRCR]         = 0x0560,
  96         [TPAUSER]       = 0x0564,
  97         [GECMR]         = 0x05b0,
  98         [BCULR]         = 0x05b4,
  99         [MAHR]          = 0x05c0,
 100         [MALR]          = 0x05c8,
 101         [TROCR]         = 0x0700,
 102         [CDCR]          = 0x0708,
 103         [LCCR]          = 0x0710,
 104         [CEFCR]         = 0x0740,
 105         [FRECR]         = 0x0748,
 106         [TSFRCR]        = 0x0750,
 107         [TLFRCR]        = 0x0758,
 108         [RFCR]          = 0x0760,
 109         [CERCR]         = 0x0768,
 110         [CEECR]         = 0x0770,
 111         [MAFCR]         = 0x0778,
 112         [RMII_MII]      = 0x0790,
 113
 114         [ARSTR]         = 0x0000,
 115         [TSU_CTRST]     = 0x0004,
 116         [TSU_FWEN0]     = 0x0010,
 117         [TSU_FWEN1]     = 0x0014,
 118         [TSU_FCM]       = 0x0018,
 119         [TSU_BSYSL0]    = 0x0020,
 120         [TSU_BSYSL1]    = 0x0024,
 121         [TSU_PRISL0]    = 0x0028,
 122         [TSU_PRISL1]    = 0x002c,
 123         [TSU_FWSL0]     = 0x0030,
 124         [TSU_FWSL1]     = 0x0034,
 125         [TSU_FWSLC]     = 0x0038,
 126         [TSU_QTAGM0]    = 0x0040,
 127         [TSU_QTAGM1]    = 0x0044,
 128         [TSU_FWSR]      = 0x0050,
 129         [TSU_FWINMK]    = 0x0054,
 130         [TSU_ADQT0]     = 0x0048,
 131         [TSU_ADQT1]     = 0x004c,
 132         [TSU_VTAG0]     = 0x0058,
 133         [TSU_VTAG1]     = 0x005c,
 134         [TSU_ADSBSY]    = 0x0060,
 135         [TSU_TEN]       = 0x0064,
 136         [TSU_POST1]     = 0x0070,
 137         [TSU_POST2]     = 0x0074,
 138         [TSU_POST3]     = 0x0078,
 139         [TSU_POST4]     = 0x007c,
 140         [TSU_ADRH0]     = 0x0100,
 141
 142         [TXNLCR0]       = 0x0080,
 143         [TXALCR0]       = 0x0084,
 144         [RXNLCR0]       = 0x0088,
 145         [RXALCR0]       = 0x008c,
 146         [FWNLCR0]       = 0x0090,
 147         [FWALCR0]       = 0x0094,
 148         [TXNLCR1]       = 0x00a0,
 149         [TXALCR1]       = 0x00a4,
 150         [RXNLCR1]       = 0x00a8,
 151         [RXALCR1]       = 0x00ac,
 152         [FWNLCR1]       = 0x00b0,
 153         [FWALCR1]       = 0x00b4,
 154 };
 155
 156 static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
 157         SH_ETH_OFFSET_DEFAULTS,
 158
 159         [EDSR]          = 0x0000,
 160         [EDMR]          = 0x0400,
 161         [EDTRR]         = 0x0408,
 162         [EDRRR]         = 0x0410,
 163         [EESR]          = 0x0428,
 164         [EESIPR]        = 0x0430,
 165         [TDLAR]         = 0x0010,
 166         [TDFAR]         = 0x0014,
 167         [TDFXR]         = 0x0018,
 168         [TDFFR]         = 0x001c,
 169         [RDLAR]         = 0x0030,
 170         [RDFAR]         = 0x0034,
 171         [RDFXR]         = 0x0038,
 172         [RDFFR]         = 0x003c,
 173         [TRSCER]        = 0x0438,
 174         [RMFCR]         = 0x0440,
 175         [TFTR]          = 0x0448,
 176         [FDR]           = 0x0450,
 177         [RMCR]          = 0x0458,
 178         [RPADIR]        = 0x0460,
 179         [FCFTR]         = 0x0468,
 180         [CSMR]          = 0x04E4,
 181
 182         [ECMR]          = 0x0500,
 183         [RFLR]          = 0x0508,
 184         [ECSR]          = 0x0510,
 185         [ECSIPR]        = 0x0518,
 186         [PIR]           = 0x0520,
 187         [APR]           = 0x0554,
 188         [MPR]           = 0x0558,
 189         [PFTCR]         = 0x055c,
 190         [PFRCR]         = 0x0560,
 191         [TPAUSER]       = 0x0564,
 192         [MAHR]          = 0x05c0,
 193         [MALR]          = 0x05c8,
 194         [CEFCR]         = 0x0740,
 195         [FRECR]         = 0x0748,
 196         [TSFRCR]        = 0x0750,
 197         [TLFRCR]        = 0x0758,
 198         [RFCR]          = 0x0760,
 199         [MAFCR]         = 0x0778,
 200
 201         [ARSTR]         = 0x0000,
 202         [TSU_CTRST]     = 0x0004,
 203         [TSU_FWSLC]     = 0x0038,
 204         [TSU_VTAG0]     = 0x0058,
 205         [TSU_ADSBSY]    = 0x0060,
 206         [TSU_TEN]       = 0x0064,
 207         [TSU_POST1]     = 0x0070,
 208         [TSU_POST2]     = 0x0074,
 209         [TSU_POST3]     = 0x0078,
 210         [TSU_POST4]     = 0x007c,
 211         [TSU_ADRH0]     = 0x0100,
 212
 213         [TXNLCR0]       = 0x0080,
 214         [TXALCR0]       = 0x0084,
 215         [RXNLCR0]       = 0x0088,
 216         [RXALCR0]       = 0x008C,
 217 };
 218
 219 static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
 220         SH_ETH_OFFSET_DEFAULTS,
 221
 222         [ECMR]          = 0x0300,
 223         [RFLR]          = 0x0308,
 224         [ECSR]          = 0x0310,
 225         [ECSIPR]        = 0x0318,
 226         [PIR]           = 0x0320,
 227         [PSR]           = 0x0328,
 228         [RDMLR]         = 0x0340,
 229         [IPGR]          = 0x0350,
 230         [APR]           = 0x0354,
 231         [MPR]           = 0x0358,
 232         [RFCF]          = 0x0360,
 233         [TPAUSER]       = 0x0364,
 234         [TPAUSECR]      = 0x0368,
 235         [MAHR]          = 0x03c0,
 236         [MALR]          = 0x03c8,
 237         [TROCR]         = 0x03d0,
 238         [CDCR]          = 0x03d4,
 239         [LCCR]          = 0x03d8,
 240         [CNDCR]         = 0x03dc,
 241         [CEFCR]         = 0x03e4,
 242         [FRECR]         = 0x03e8,
 243         [TSFRCR]        = 0x03ec,
 244         [TLFRCR]        = 0x03f0,
 245         [RFCR]          = 0x03f4,
 246         [MAFCR]         = 0x03f8,
 247
 248         [EDMR]          = 0x0200,
 249         [EDTRR]         = 0x0208,
 250         [EDRRR]         = 0x0210,
 251         [TDLAR]         = 0x0218,
 252         [RDLAR]         = 0x0220,
 253         [EESR]          = 0x0228,
 254         [EESIPR]        = 0x0230,
 255         [TRSCER]        = 0x0238,
 256         [RMFCR]         = 0x0240,
 257         [TFTR]          = 0x0248,
 258         [FDR]           = 0x0250,
 259         [RMCR]          = 0x0258,
 260         [TFUCR]         = 0x0264,
 261         [RFOCR]         = 0x0268,
 262         [RMIIMODE]      = 0x026c,
 263         [FCFTR]         = 0x0270,
 264         [TRIMD]         = 0x027c,
 265 };
 266
 267 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
 268         SH_ETH_OFFSET_DEFAULTS,
 269
 270         [ECMR]          = 0x0100,
 271         [RFLR]          = 0x0108,
 272         [ECSR]          = 0x0110,
 273         [ECSIPR]        = 0x0118,
 274         [PIR]           = 0x0120,
 275         [PSR]           = 0x0128,
 276         [RDMLR]         = 0x0140,
 277         [IPGR]          = 0x0150,
 278         [APR]           = 0x0154,
 279         [MPR]           = 0x0158,
 280         [TPAUSER]       = 0x0164,
 281         [RFCF]          = 0x0160,
 282         [TPAUSECR]      = 0x0168,
 283         [BCFRR]         = 0x016c,
 284         [MAHR]          = 0x01c0,
 285         [MALR]          = 0x01c8,
 286         [TROCR]         = 0x01d0,
 287         [CDCR]          = 0x01d4,
 288         [LCCR]          = 0x01d8,
 289         [CNDCR]         = 0x01dc,
 290         [CEFCR]         = 0x01e4,
 291         [FRECR]         = 0x01e8,
 292         [TSFRCR]        = 0x01ec,
 293         [TLFRCR]        = 0x01f0,
 294         [RFCR]          = 0x01f4,
 295         [MAFCR]         = 0x01f8,
 296         [RTRATE]        = 0x01fc,
 297
 298         [EDMR]          = 0x0000,
 299         [EDTRR]         = 0x0008,
 300         [EDRRR]         = 0x0010,
 301         [TDLAR]         = 0x0018,
 302         [RDLAR]         = 0x0020,
 303         [EESR]          = 0x0028,
 304         [EESIPR]        = 0x0030,
 305         [TRSCER]        = 0x0038,
 306         [RMFCR]         = 0x0040,
 307         [TFTR]          = 0x0048,
 308         [FDR]           = 0x0050,
 309         [RMCR]          = 0x0058,
 310         [TFUCR]         = 0x0064,
 311         [RFOCR]         = 0x0068,
 312         [FCFTR]         = 0x0070,
 313         [RPADIR]        = 0x0078,
 314         [TRIMD]         = 0x007c,
 315         [RBWAR]         = 0x00c8,
 316         [RDFAR]         = 0x00cc,
 317         [TBRAR]         = 0x00d4,
 318         [TDFAR]         = 0x00d8,
 319 };
 320
 321 static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
 322         SH_ETH_OFFSET_DEFAULTS,
 323
 324         [EDMR]          = 0x0000,
 325         [EDTRR]         = 0x0004,
 326         [EDRRR]         = 0x0008,
 327         [TDLAR]         = 0x000c,
 328         [RDLAR]         = 0x0010,
 329         [EESR]          = 0x0014,
 330         [EESIPR]        = 0x0018,
 331         [TRSCER]        = 0x001c,
 332         [RMFCR]         = 0x0020,
 333         [TFTR]          = 0x0024,
 334         [FDR]           = 0x0028,
 335         [RMCR]          = 0x002c,
 336         [EDOCR]         = 0x0030,
 337         [FCFTR]         = 0x0034,
 338         [RPADIR]        = 0x0038,
 339         [TRIMD]         = 0x003c,
 340         [RBWAR]         = 0x0040,
 341         [RDFAR]         = 0x0044,
 342         [TBRAR]         = 0x004c,
 343         [TDFAR]         = 0x0050,
 344
 345         [ECMR]          = 0x0160,
 346         [ECSR]          = 0x0164,
 347         [ECSIPR]        = 0x0168,
 348         [PIR]           = 0x016c,
 349         [MAHR]          = 0x0170,
 350         [MALR]          = 0x0174,
 351         [RFLR]          = 0x0178,
 352         [PSR]           = 0x017c,
 353         [TROCR]         = 0x0180,
 354         [CDCR]          = 0x0184,
 355         [LCCR]          = 0x0188,
 356         [CNDCR]         = 0x018c,
 357         [CEFCR]         = 0x0194,
 358         [FRECR]         = 0x0198,
 359         [TSFRCR]        = 0x019c,
 360         [TLFRCR]        = 0x01a0,
 361         [RFCR]          = 0x01a4,
 362         [MAFCR]         = 0x01a8,
 363         [IPGR]          = 0x01b4,
 364         [APR]           = 0x01b8,
 365         [MPR]           = 0x01bc,
 366         [TPAUSER]       = 0x01c4,
 367         [BCFR]          = 0x01cc,
 368
 369         [ARSTR]         = 0x0000,
 370         [TSU_CTRST]     = 0x0004,
 371         [TSU_FWEN0]     = 0x0010,
 372         [TSU_FWEN1]     = 0x0014,
 373         [TSU_FCM]       = 0x0018,
 374         [TSU_BSYSL0]    = 0x0020,
 375         [TSU_BSYSL1]    = 0x0024,
 376         [TSU_PRISL0]    = 0x0028,
 377         [TSU_PRISL1]    = 0x002c,
 378         [TSU_FWSL0]     = 0x0030,
 379         [TSU_FWSL1]     = 0x0034,
 380         [TSU_FWSLC]     = 0x0038,
 381         [TSU_QTAGM0]    = 0x0040,
 382         [TSU_QTAGM1]    = 0x0044,
 383         [TSU_ADQT0]     = 0x0048,
 384         [TSU_ADQT1]     = 0x004c,
 385         [TSU_FWSR]      = 0x0050,
 386         [TSU_FWINMK]    = 0x0054,
 387         [TSU_ADSBSY]    = 0x0060,
 388         [TSU_TEN]       = 0x0064,
 389         [TSU_POST1]     = 0x0070,
 390         [TSU_POST2]     = 0x0074,
 391         [TSU_POST3]     = 0x0078,
 392         [TSU_POST4]     = 0x007c,
 393
 394         [TXNLCR0]       = 0x0080,
 395         [TXALCR0]       = 0x0084,
 396         [RXNLCR0]       = 0x0088,
 397         [RXALCR0]       = 0x008c,
 398         [FWNLCR0]       = 0x0090,
 399         [FWALCR0]       = 0x0094,
 400         [TXNLCR1]       = 0x00a0,
 401         [TXALCR1]       = 0x00a4,
 402         [RXNLCR1]       = 0x00a8,
 403         [RXALCR1]       = 0x00ac,
 404         [FWNLCR1]       = 0x00b0,
 405         [FWALCR1]       = 0x00b4,
 406
 407         [TSU_ADRH0]     = 0x0100,
 408 };
 409
 410 static void sh_eth_rcv_snd_disable(struct net_device *ndev);
 411 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev);
 412
 413 static void sh_eth_write(struct net_device *ndev, u32 data, int enum_index)
 414 {
 415         struct sh_eth_private *mdp = netdev_priv(ndev);
 416         u16 offset = mdp->reg_offset[enum_index];
 417
 418         if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
 419                 return;
 420
 421         iowrite32(data, mdp->addr + offset);
 422 }
 423
 424 static u32 sh_eth_read(struct net_device *ndev, int enum_index)
 425 {
 426         struct sh_eth_private *mdp = netdev_priv(ndev);
 427         u16 offset = mdp->reg_offset[enum_index];
 428
 429         if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
 430                 return ~0U;
 431
 432         return ioread32(mdp->addr + offset);
 433 }
 434
 435 static void sh_eth_modify(struct net_device *ndev, int enum_index, u32 clear,
 436                           u32 set)
 437 {
 438         sh_eth_write(ndev, (sh_eth_read(ndev, enum_index) & ~clear) | set,
 439                      enum_index);
 440 }
 441
 442 static void sh_eth_tsu_write(struct sh_eth_private *mdp, u32 data,
 443                              int enum_index)
 444 {
 445         u16 offset = mdp->reg_offset[enum_index];
 446
 447         if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
 448                 return;
 449
 450         iowrite32(data, mdp->tsu_addr + offset);
 451 }
 452
 453 static u32 sh_eth_tsu_read(struct sh_eth_private *mdp, int enum_index)
 454 {
 455         u16 offset = mdp->reg_offset[enum_index];
 456
 457         if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
 458                 return ~0U;
 459
 460         return ioread32(mdp->tsu_addr + offset);
 461 }
 462
 463 static void sh_eth_soft_swap(char *src, int len)
 464 {
 465 #ifdef __LITTLE_ENDIAN
 466         u32 *p = (u32 *)src;
 467         u32 *maxp = p + DIV_ROUND_UP(len, sizeof(u32));
 468
 469         for (; p < maxp; p++)
 470                 *p = swab32(*p);
 471 #endif
 472 }
 473
 474 static void sh_eth_select_mii(struct net_device *ndev)
 475 {
 476         struct sh_eth_private *mdp = netdev_priv(ndev);
 477         u32 value;
 478
 479         switch (mdp->phy_interface) {
 480         case PHY_INTERFACE_MODE_RGMII ... PHY_INTERFACE_MODE_RGMII_TXID:
 481                 value = 0x3;
 482                 break;
 483         case PHY_INTERFACE_MODE_GMII:
 484                 value = 0x2;
 485                 break;
 486         case PHY_INTERFACE_MODE_MII:
 487                 value = 0x1;
 488                 break;
 489         case PHY_INTERFACE_MODE_RMII:
 490                 value = 0x0;
 491                 break;
 492         default:
 493                 netdev_warn(ndev,
 494                             "PHY interface mode was not setup. Set to MII.\n");
 495                 value = 0x1;
 496                 break;
 497         }
 498
 499         sh_eth_write(ndev, value, RMII_MII);
 500 }
 501
 502 static void sh_eth_set_duplex(struct net_device *ndev)
 503 {
 504         struct sh_eth_private *mdp = netdev_priv(ndev);
 505
 506         sh_eth_modify(ndev, ECMR, ECMR_DM, mdp->duplex ? ECMR_DM : 0);
 507 }
 508
 509 static void sh_eth_chip_reset(struct net_device *ndev)
 510 {
 511         struct sh_eth_private *mdp = netdev_priv(ndev);
 512
 513         /* reset device */
 514         sh_eth_tsu_write(mdp, ARSTR_ARST, ARSTR);
 515         mdelay(1);
 516 }
 517
 518 static int sh_eth_soft_reset(struct net_device *ndev)
 519 {
 520         sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, EDMR_SRST_ETHER);
 521         mdelay(3);
 522         sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, 0);
 523
 524         return 0;
 525 }
 526
 527 static int sh_eth_check_soft_reset(struct net_device *ndev)
 528 {
 529         int cnt;
 530
 531         for (cnt = 100; cnt > 0; cnt--) {
 532                 if (!(sh_eth_read(ndev, EDMR) & EDMR_SRST_GETHER))
 533                         return 0;
 534                 mdelay(1);
 535         }
 536
 537         netdev_err(ndev, "Device reset failed\n");
 538         return -ETIMEDOUT;
 539 }
 540
 541 static int sh_eth_soft_reset_gether(struct net_device *ndev)
 542 {
 543         struct sh_eth_private *mdp = netdev_priv(ndev);
 544         int ret;
 545
 546         sh_eth_write(ndev, EDSR_ENALL, EDSR);
 547         sh_eth_modify(ndev, EDMR, EDMR_SRST_GETHER, EDMR_SRST_GETHER);
 548
 549         ret = sh_eth_check_soft_reset(ndev);
 550         if (ret)
 551                 return ret;
 552
 553         /* Table Init */
 554         sh_eth_write(ndev, 0, TDLAR);
 555         sh_eth_write(ndev, 0, TDFAR);
 556         sh_eth_write(ndev, 0, TDFXR);
 557         sh_eth_write(ndev, 0, TDFFR);
 558         sh_eth_write(ndev, 0, RDLAR);
 559         sh_eth_write(ndev, 0, RDFAR);
 560         sh_eth_write(ndev, 0, RDFXR);
 561         sh_eth_write(ndev, 0, RDFFR);
 562
 563         /* Reset HW CRC register */
 564         if (mdp->cd->hw_checksum)
 565                 sh_eth_write(ndev, 0, CSMR);
 566
 567         /* Select MII mode */
 568         if (mdp->cd->select_mii)
 569                 sh_eth_select_mii(ndev);
 570
 571         return ret;
 572 }
 573
 574 static void sh_eth_set_rate_gether(struct net_device *ndev)
 575 {
 576         struct sh_eth_private *mdp = netdev_priv(ndev);
 577
 578         switch (mdp->speed) {
 579         case 10: /* 10BASE */
 580                 sh_eth_write(ndev, GECMR_10, GECMR);
 581                 break;
 582         case 100:/* 100BASE */
 583                 sh_eth_write(ndev, GECMR_100, GECMR);
 584                 break;
 585         case 1000: /* 1000BASE */
 586                 sh_eth_write(ndev, GECMR_1000, GECMR);
 587                 break;
 588         }
 589 }
 590
 591 #ifdef CONFIG_OF
 592 /* R7S72100 */
 593 static struct sh_eth_cpu_data r7s72100_data = {
 594         .soft_reset     = sh_eth_soft_reset_gether,
 595
 596         .chip_reset     = sh_eth_chip_reset,
 597         .set_duplex     = sh_eth_set_duplex,
 598
 599         .register_type  = SH_ETH_REG_FAST_RZ,
 600
 601         .edtrr_trns     = EDTRR_TRNS_GETHER,
 602         .ecsr_value     = ECSR_ICD,
 603         .ecsipr_value   = ECSIPR_ICDIP,
 604         .eesipr_value   = EESIPR_TWB1IP | EESIPR_TWBIP | EESIPR_TC1IP |
 605                           EESIPR_TABTIP | EESIPR_RABTIP | EESIPR_RFCOFIP |
 606                           EESIPR_ECIIP |
 607                           EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
 608                           EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
 609                           EESIPR_RMAFIP | EESIPR_RRFIP |
 610                           EESIPR_RTLFIP | EESIPR_RTSFIP |
 611                           EESIPR_PREIP | EESIPR_CERFIP,
 612
 613         .tx_check       = EESR_TC1 | EESR_FTC,
 614         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 615                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 616                           EESR_TDE,
 617         .fdr_value      = 0x0000070f,
 618
 619         .no_psr         = 1,
 620         .apr            = 1,
 621         .mpr            = 1,
 622         .tpauser        = 1,
 623         .hw_swap        = 1,
 624         .rpadir         = 1,
 625         .no_trimd       = 1,
 626         .no_ade         = 1,
 627         .xdfar_rw       = 1,
 628         .hw_checksum    = 1,
 629         .tsu            = 1,
 630         .no_tx_cntrs    = 1,
 631 };
 632
 633 static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
 634 {
 635         sh_eth_chip_reset(ndev);
 636
 637         sh_eth_select_mii(ndev);
 638 }
 639
 640 /* R8A7740 */
 641 static struct sh_eth_cpu_data r8a7740_data = {
 642         .soft_reset     = sh_eth_soft_reset_gether,
 643
 644         .chip_reset     = sh_eth_chip_reset_r8a7740,
 645         .set_duplex     = sh_eth_set_duplex,
 646         .set_rate       = sh_eth_set_rate_gether,
 647
 648         .register_type  = SH_ETH_REG_GIGABIT,
 649
 650         .edtrr_trns     = EDTRR_TRNS_GETHER,
 651         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 652         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 653         .eesipr_value   = EESIPR_RFCOFIP | EESIPR_ECIIP |
 654                           EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
 655                           EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
 656                           0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
 657                           EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
 658                           EESIPR_CEEFIP | EESIPR_CELFIP |
 659                           EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
 660                           EESIPR_PREIP | EESIPR_CERFIP,
 661
 662         .tx_check       = EESR_TC1 | EESR_FTC,
 663         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 664                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 665                           EESR_TDE,
 666         .fdr_value      = 0x0000070f,
 667
 668         .apr            = 1,
 669         .mpr            = 1,
 670         .tpauser        = 1,
 671         .bculr          = 1,
 672         .hw_swap        = 1,
 673         .rpadir         = 1,
 674         .no_trimd       = 1,
 675         .no_ade         = 1,
 676         .xdfar_rw       = 1,
 677         .hw_checksum    = 1,
 678         .tsu            = 1,
 679         .select_mii     = 1,
 680         .magic          = 1,
 681         .cexcr          = 1,
 682 };
 683
 684 /* There is CPU dependent code */
 685 static void sh_eth_set_rate_rcar(struct net_device *ndev)
 686 {
 687         struct sh_eth_private *mdp = netdev_priv(ndev);
 688
 689         switch (mdp->speed) {
 690         case 10: /* 10BASE */
 691                 sh_eth_modify(ndev, ECMR, ECMR_ELB, 0);
 692                 break;
 693         case 100:/* 100BASE */
 694                 sh_eth_modify(ndev, ECMR, ECMR_ELB, ECMR_ELB);
 695                 break;
 696         }
 697 }
 698
 699 /* R-Car Gen1 */
 700 static struct sh_eth_cpu_data rcar_gen1_data = {
 701         .soft_reset     = sh_eth_soft_reset,
 702
 703         .set_duplex     = sh_eth_set_duplex,
 704         .set_rate       = sh_eth_set_rate_rcar,
 705
 706         .register_type  = SH_ETH_REG_FAST_RCAR,
 707
 708         .edtrr_trns     = EDTRR_TRNS_ETHER,
 709         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
 710         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
 711         .eesipr_value   = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP |
 712                           EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
 713                           EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
 714                           EESIPR_RMAFIP | EESIPR_RRFIP |
 715                           EESIPR_RTLFIP | EESIPR_RTSFIP |
 716                           EESIPR_PREIP | EESIPR_CERFIP,
 717
 718         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO,
 719         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 720                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
 721         .fdr_value      = 0x00000f0f,
 722
 723         .apr            = 1,
 724         .mpr            = 1,
 725         .tpauser        = 1,
 726         .hw_swap        = 1,
 727         .no_xdfar       = 1,
 728 };
 729
 730 /* R-Car Gen2 and RZ/G1 */
 731 static struct sh_eth_cpu_data rcar_gen2_data = {
 732         .soft_reset     = sh_eth_soft_reset,
 733
 734         .set_duplex     = sh_eth_set_duplex,
 735         .set_rate       = sh_eth_set_rate_rcar,
 736
 737         .register_type  = SH_ETH_REG_FAST_RCAR,
 738
 739         .edtrr_trns     = EDTRR_TRNS_ETHER,
 740         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD | ECSR_MPD,
 741         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP |
 742                           ECSIPR_MPDIP,
 743         .eesipr_value   = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP |
 744                           EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
 745                           EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
 746                           EESIPR_RMAFIP | EESIPR_RRFIP |
 747                           EESIPR_RTLFIP | EESIPR_RTSFIP |
 748                           EESIPR_PREIP | EESIPR_CERFIP,
 749
 750         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO,
 751         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 752                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
 753         .fdr_value      = 0x00000f0f,
 754
 755         .trscer_err_mask = DESC_I_RINT8,
 756
 757         .apr            = 1,
 758         .mpr            = 1,
 759         .tpauser        = 1,
 760         .hw_swap        = 1,
 761         .no_xdfar       = 1,
 762         .rmiimode       = 1,
 763         .magic          = 1,
 764 };
 765
 766 /* R8A77980 */
 767 static struct sh_eth_cpu_data r8a77980_data = {
 768         .soft_reset     = sh_eth_soft_reset_gether,
 769
 770         .set_duplex     = sh_eth_set_duplex,
 771         .set_rate       = sh_eth_set_rate_gether,
 772
 773         .register_type  = SH_ETH_REG_GIGABIT,
 774
 775         .edtrr_trns     = EDTRR_TRNS_GETHER,
 776         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD | ECSR_MPD,
 777         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP |
 778                           ECSIPR_MPDIP,
 779         .eesipr_value   = EESIPR_RFCOFIP | EESIPR_ECIIP |
 780                           EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
 781                           EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
 782                           EESIPR_RMAFIP | EESIPR_RRFIP |
 783                           EESIPR_RTLFIP | EESIPR_RTSFIP |
 784                           EESIPR_PREIP | EESIPR_CERFIP,
 785
 786         .tx_check       = EESR_FTC | EESR_CD | EESR_TRO,
 787         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 788                           EESR_RFE | EESR_RDE | EESR_RFRMER |
 789                           EESR_TFE | EESR_TDE | EESR_ECI,
 790         .fdr_value      = 0x0000070f,
 791
 792         .apr            = 1,
 793         .mpr            = 1,
 794         .tpauser        = 1,
 795         .bculr          = 1,
 796         .hw_swap        = 1,
 797         .nbst           = 1,
 798         .rpadir         = 1,
 799         .no_trimd       = 1,
 800         .no_ade         = 1,
 801         .xdfar_rw       = 1,
 802         .hw_checksum    = 1,
 803         .select_mii     = 1,
 804         .magic          = 1,
 805         .cexcr          = 1,
 806 };
 807 #endif /* CONFIG_OF */
 808
 809 static void sh_eth_set_rate_sh7724(struct net_device *ndev)
 810 {
 811         struct sh_eth_private *mdp = netdev_priv(ndev);
 812
 813         switch (mdp->speed) {
 814         case 10: /* 10BASE */
 815                 sh_eth_modify(ndev, ECMR, ECMR_RTM, 0);
 816                 break;
 817         case 100:/* 100BASE */
 818                 sh_eth_modify(ndev, ECMR, ECMR_RTM, ECMR_RTM);
 819                 break;
 820         }
 821 }
 822
 823 /* SH7724 */
 824 static struct sh_eth_cpu_data sh7724_data = {
 825         .soft_reset     = sh_eth_soft_reset,
 826
 827         .set_duplex     = sh_eth_set_duplex,
 828         .set_rate       = sh_eth_set_rate_sh7724,
 829
 830         .register_type  = SH_ETH_REG_FAST_SH4,
 831
 832         .edtrr_trns     = EDTRR_TRNS_ETHER,
 833         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
 834         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
 835         .eesipr_value   = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP |
 836                           EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
 837                           EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
 838                           EESIPR_RMAFIP | EESIPR_RRFIP |
 839                           EESIPR_RTLFIP | EESIPR_RTSFIP |
 840                           EESIPR_PREIP | EESIPR_CERFIP,
 841
 842         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO,
 843         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 844                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
 845
 846         .apr            = 1,
 847         .mpr            = 1,
 848         .tpauser        = 1,
 849         .hw_swap        = 1,
 850         .rpadir         = 1,
 851 };
 852
 853 static void sh_eth_set_rate_sh7757(struct net_device *ndev)
 854 {
 855         struct sh_eth_private *mdp = netdev_priv(ndev);
 856
 857         switch (mdp->speed) {
 858         case 10: /* 10BASE */
 859                 sh_eth_write(ndev, 0, RTRATE);
 860                 break;
 861         case 100:/* 100BASE */
 862                 sh_eth_write(ndev, 1, RTRATE);
 863                 break;
 864         }
 865 }
 866
 867 /* SH7757 */
 868 static struct sh_eth_cpu_data sh7757_data = {
 869         .soft_reset     = sh_eth_soft_reset,
 870
 871         .set_duplex     = sh_eth_set_duplex,
 872         .set_rate       = sh_eth_set_rate_sh7757,
 873
 874         .register_type  = SH_ETH_REG_FAST_SH4,
 875
 876         .edtrr_trns     = EDTRR_TRNS_ETHER,
 877         .eesipr_value   = EESIPR_RFCOFIP | EESIPR_ECIIP |
 878                           EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
 879                           EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
 880                           0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
 881                           EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
 882                           EESIPR_CEEFIP | EESIPR_CELFIP |
 883                           EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
 884                           EESIPR_PREIP | EESIPR_CERFIP,
 885
 886         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO,
 887         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 888                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
 889
 890         .irq_flags      = IRQF_SHARED,
 891         .apr            = 1,
 892         .mpr            = 1,
 893         .tpauser        = 1,
 894         .hw_swap        = 1,
 895         .no_ade         = 1,
 896         .rpadir         = 1,
 897         .rtrate         = 1,
 898         .dual_port      = 1,
 899 };
 900
 901 #define SH_GIGA_ETH_BASE        0xfee00000UL
 902 #define GIGA_MALR(port)         (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
 903 #define GIGA_MAHR(port)         (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
 904 static void sh_eth_chip_reset_giga(struct net_device *ndev)
 905 {
 906         u32 mahr[2], malr[2];
 907         int i;
 908
 909         /* save MAHR and MALR */
 910         for (i = 0; i < 2; i++) {
 911                 malr[i] = ioread32((void *)GIGA_MALR(i));
 912                 mahr[i] = ioread32((void *)GIGA_MAHR(i));
 913         }
 914
 915         sh_eth_chip_reset(ndev);
 916
 917         /* restore MAHR and MALR */
 918         for (i = 0; i < 2; i++) {
 919                 iowrite32(malr[i], (void *)GIGA_MALR(i));
 920                 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
 921         }
 922 }
 923
 924 static void sh_eth_set_rate_giga(struct net_device *ndev)
 925 {
 926         struct sh_eth_private *mdp = netdev_priv(ndev);
 927
 928         switch (mdp->speed) {
 929         case 10: /* 10BASE */
 930                 sh_eth_write(ndev, 0x00000000, GECMR);
 931                 break;
 932         case 100:/* 100BASE */
 933                 sh_eth_write(ndev, 0x00000010, GECMR);
 934                 break;
 935         case 1000: /* 1000BASE */
 936                 sh_eth_write(ndev, 0x00000020, GECMR);
 937                 break;
 938         }
 939 }
 940
 941 /* SH7757(GETHERC) */
 942 static struct sh_eth_cpu_data sh7757_data_giga = {
 943         .soft_reset     = sh_eth_soft_reset_gether,
 944
 945         .chip_reset     = sh_eth_chip_reset_giga,
 946         .set_duplex     = sh_eth_set_duplex,
 947         .set_rate       = sh_eth_set_rate_giga,
 948
 949         .register_type  = SH_ETH_REG_GIGABIT,
 950
 951         .edtrr_trns     = EDTRR_TRNS_GETHER,
 952         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 953         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 954         .eesipr_value   = EESIPR_RFCOFIP | EESIPR_ECIIP |
 955                           EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
 956                           EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
 957                           0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
 958                           EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
 959                           EESIPR_CEEFIP | EESIPR_CELFIP |
 960                           EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
 961                           EESIPR_PREIP | EESIPR_CERFIP,
 962
 963         .tx_check       = EESR_TC1 | EESR_FTC,
 964         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 965                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 966                           EESR_TDE,
 967         .fdr_value      = 0x0000072f,
 968
 969         .irq_flags      = IRQF_SHARED,
 970         .apr            = 1,
 971         .mpr            = 1,
 972         .tpauser        = 1,
 973         .bculr          = 1,
 974         .hw_swap        = 1,
 975         .rpadir         = 1,
 976         .no_trimd       = 1,
 977         .no_ade         = 1,
 978         .xdfar_rw       = 1,
 979         .tsu            = 1,
 980         .cexcr          = 1,
 981         .dual_port      = 1,
 982 };
 983
 984 /* SH7734 */
 985 static struct sh_eth_cpu_data sh7734_data = {
 986         .soft_reset     = sh_eth_soft_reset_gether,
 987
 988         .chip_reset     = sh_eth_chip_reset,
 989         .set_duplex     = sh_eth_set_duplex,
 990         .set_rate       = sh_eth_set_rate_gether,
 991
 992         .register_type  = SH_ETH_REG_GIGABIT,
 993
 994         .edtrr_trns     = EDTRR_TRNS_GETHER,
 995         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 996         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 997         .eesipr_value   = EESIPR_RFCOFIP | EESIPR_ECIIP |
 998                           EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
 999                           EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
1000                           EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP |
1001                           EESIPR_RMAFIP | EESIPR_CEEFIP | EESIPR_CELFIP |
1002                           EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
1003                           EESIPR_PREIP | EESIPR_CERFIP,
1004
1005         .tx_check       = EESR_TC1 | EESR_FTC,
1006         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
1007                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
1008                           EESR_TDE,
1009
1010         .apr            = 1,
1011         .mpr            = 1,
1012         .tpauser        = 1,
1013         .bculr          = 1,
1014         .hw_swap        = 1,
1015         .no_trimd       = 1,
1016         .no_ade         = 1,
1017         .xdfar_rw       = 1,
1018         .tsu            = 1,
1019         .hw_checksum    = 1,
1020         .select_mii     = 1,
1021         .magic          = 1,
1022         .cexcr          = 1,
1023 };
1024
1025 /* SH7763 */
1026 static struct sh_eth_cpu_data sh7763_data = {
1027         .soft_reset     = sh_eth_soft_reset_gether,
1028
1029         .chip_reset     = sh_eth_chip_reset,
1030         .set_duplex     = sh_eth_set_duplex,
1031         .set_rate       = sh_eth_set_rate_gether,
1032
1033         .register_type  = SH_ETH_REG_GIGABIT,
1034
1035         .edtrr_trns     = EDTRR_TRNS_GETHER,
1036         .ecsr_value     = ECSR_ICD | ECSR_MPD,
1037         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
1038         .eesipr_value   = EESIPR_RFCOFIP | EESIPR_ECIIP |
1039                           EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
1040                           EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
1041                           EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP |
1042                           EESIPR_RMAFIP | EESIPR_CEEFIP | EESIPR_CELFIP |
1043                           EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
1044                           EESIPR_PREIP | EESIPR_CERFIP,
1045
1046         .tx_check       = EESR_TC1 | EESR_FTC,
1047         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
1048                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
1049
1050         .apr            = 1,
1051         .mpr            = 1,
1052         .tpauser        = 1,
1053         .bculr          = 1,
1054         .hw_swap        = 1,
1055         .no_trimd       = 1,
1056         .no_ade         = 1,
1057         .xdfar_rw       = 1,
1058         .tsu            = 1,
1059         .irq_flags      = IRQF_SHARED,
1060         .magic          = 1,
1061         .cexcr          = 1,
1062         .dual_port      = 1,
1063 };
1064
1065 static struct sh_eth_cpu_data sh7619_data = {
1066         .soft_reset     = sh_eth_soft_reset,
1067
1068         .register_type  = SH_ETH_REG_FAST_SH3_SH2,
1069
1070         .edtrr_trns     = EDTRR_TRNS_ETHER,
1071         .eesipr_value   = EESIPR_RFCOFIP | EESIPR_ECIIP |
1072                           EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
1073                           EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
1074                           0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
1075                           EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
1076                           EESIPR_CEEFIP | EESIPR_CELFIP |
1077                           EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
1078                           EESIPR_PREIP | EESIPR_CERFIP,
1079
1080         .apr            = 1,
1081         .mpr            = 1,
1082         .tpauser        = 1,
1083         .hw_swap        = 1,
1084 };
1085
1086 static struct sh_eth_cpu_data sh771x_data = {
1087         .soft_reset     = sh_eth_soft_reset,
1088
1089         .register_type  = SH_ETH_REG_FAST_SH3_SH2,
1090
1091         .edtrr_trns     = EDTRR_TRNS_ETHER,
1092         .eesipr_value   = EESIPR_RFCOFIP | EESIPR_ECIIP |
1093                           EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
1094                           EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
1095                           0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
1096                           EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
1097                           EESIPR_CEEFIP | EESIPR_CELFIP |
1098                           EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
1099                           EESIPR_PREIP | EESIPR_CERFIP,
1100         .tsu            = 1,
1101         .dual_port      = 1,
1102 };
1103
1104 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
1105 {
1106         if (!cd->ecsr_value)
1107                 cd->ecsr_value = DEFAULT_ECSR_INIT;
1108
1109         if (!cd->ecsipr_value)
1110                 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
1111
1112         if (!cd->fcftr_value)
1113                 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF |
1114                                   DEFAULT_FIFO_F_D_RFD;
1115
1116         if (!cd->fdr_value)
1117                 cd->fdr_value = DEFAULT_FDR_INIT;
1118
1119         if (!cd->tx_check)
1120                 cd->tx_check = DEFAULT_TX_CHECK;
1121
1122         if (!cd->eesr_err_check)
1123                 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
1124
1125         if (!cd->trscer_err_mask)
1126                 cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK;
1127 }
1128
1129 static void sh_eth_set_receive_align(struct sk_buff *skb)
1130 {
1131         uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1);
1132
1133         if (reserve)
1134                 skb_reserve(skb, SH_ETH_RX_ALIGN - reserve);
1135 }
1136
1137 /* Program the hardware MAC address from dev->dev_addr. */
1138 static void update_mac_address(struct net_device *ndev)
1139 {
1140         sh_eth_write(ndev,
1141                      (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
1142                      (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
1143         sh_eth_write(ndev,
1144                      (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
1145 }
1146
1147 /* Get MAC address from SuperH MAC address register
1148  *
1149  * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
1150  * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
1151  * When you want use this device, you must set MAC address in bootloader.
1152  *
1153  */
1154 static void read_mac_address(struct net_device *ndev, unsigned char *mac)
1155 {
1156         if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
1157                 memcpy(ndev->dev_addr, mac, ETH_ALEN);
1158         } else {
1159                 u32 mahr = sh_eth_read(ndev, MAHR);
1160                 u32 malr = sh_eth_read(ndev, MALR);
1161
1162                 ndev->dev_addr[0] = (mahr >> 24) & 0xFF;
1163                 ndev->dev_addr[1] = (mahr >> 16) & 0xFF;
1164                 ndev->dev_addr[2] = (mahr >>  8) & 0xFF;
1165                 ndev->dev_addr[3] = (mahr >>  0) & 0xFF;
1166                 ndev->dev_addr[4] = (malr >>  8) & 0xFF;
1167                 ndev->dev_addr[5] = (malr >>  0) & 0xFF;
1168         }
1169 }
1170
1171 struct bb_info {
1172         void (*set_gate)(void *addr);
1173         struct mdiobb_ctrl ctrl;
1174         void *addr;
1175 };
1176
1177 static void sh_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set)
1178 {
1179         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1180         u32 pir;
1181
1182         if (bitbang->set_gate)
1183                 bitbang->set_gate(bitbang->addr);
1184
1185         pir = ioread32(bitbang->addr);
1186         if (set)
1187                 pir |=  mask;
1188         else
1189                 pir &= ~mask;
1190         iowrite32(pir, bitbang->addr);
1191 }
1192
1193 /* Data I/O pin control */
1194 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1195 {
1196         sh_mdio_ctrl(ctrl, PIR_MMD, bit);
1197 }
1198
1199 /* Set bit data*/
1200 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
1201 {
1202         sh_mdio_ctrl(ctrl, PIR_MDO, bit);
1203 }
1204
1205 /* Get bit data*/
1206 static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
1207 {
1208         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1209
1210         if (bitbang->set_gate)
1211                 bitbang->set_gate(bitbang->addr);
1212
1213         return (ioread32(bitbang->addr) & PIR_MDI) != 0;
1214 }
1215
1216 /* MDC pin control */
1217 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1218 {
1219         sh_mdio_ctrl(ctrl, PIR_MDC, bit);
1220 }
1221
1222 /* mdio bus control struct */
1223 static struct mdiobb_ops bb_ops = {
1224         .owner = THIS_MODULE,
1225         .set_mdc = sh_mdc_ctrl,
1226         .set_mdio_dir = sh_mmd_ctrl,
1227         .set_mdio_data = sh_set_mdio,
1228         .get_mdio_data = sh_get_mdio,
1229 };
1230
1231 /* free Tx skb function */
1232 static int sh_eth_tx_free(struct net_device *ndev, bool sent_only)
1233 {
1234         struct sh_eth_private *mdp = netdev_priv(ndev);
1235         struct sh_eth_txdesc *txdesc;
1236         int free_num = 0;
1237         int entry;
1238         bool sent;
1239
1240         for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
1241                 entry = mdp->dirty_tx % mdp->num_tx_ring;
1242                 txdesc = &mdp->tx_ring[entry];
1243                 sent = !(txdesc->status & cpu_to_le32(TD_TACT));
1244                 if (sent_only && !sent)
1245                         break;
1246                 /* TACT bit must be checked before all the following reads */
1247                 dma_rmb();
1248                 netif_info(mdp, tx_done, ndev,
1249                            "tx entry %d status 0x%08x\n",
1250                            entry, le32_to_cpu(txdesc->status));
1251                 /* Free the original skb. */
1252                 if (mdp->tx_skbuff[entry]) {
1253                         dma_unmap_single(&mdp->pdev->dev,
1254                                          le32_to_cpu(txdesc->addr),
1255                                          le32_to_cpu(txdesc->len) >> 16,
1256                                          DMA_TO_DEVICE);
1257                         dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1258                         mdp->tx_skbuff[entry] = NULL;
1259                         free_num++;
1260                 }
1261                 txdesc->status = cpu_to_le32(TD_TFP);
1262                 if (entry >= mdp->num_tx_ring - 1)
1263                         txdesc->status |= cpu_to_le32(TD_TDLE);
1264
1265                 if (sent) {
1266                         ndev->stats.tx_packets++;
1267                         ndev->stats.tx_bytes += le32_to_cpu(txdesc->len) >> 16;
1268                 }
1269         }
1270         return free_num;
1271 }
1272
1273 /* free skb and descriptor buffer */
1274 static void sh_eth_ring_free(struct net_device *ndev)
1275 {
1276         struct sh_eth_private *mdp = netdev_priv(ndev);
1277         int ringsize, i;
1278
1279         if (mdp->rx_ring) {
1280                 for (i = 0; i < mdp->num_rx_ring; i++) {
1281                         if (mdp->rx_skbuff[i]) {
1282                                 struct sh_eth_rxdesc *rxdesc = &mdp->rx_ring[i];
1283
1284                                 dma_unmap_single(&mdp->pdev->dev,
1285                                                  le32_to_cpu(rxdesc->addr),
1286                                                  ALIGN(mdp->rx_buf_sz, 32),
1287                                                  DMA_FROM_DEVICE);
1288                         }
1289                 }
1290                 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1291                 dma_free_coherent(&mdp->pdev->dev, ringsize, mdp->rx_ring,
1292                                   mdp->rx_desc_dma);
1293                 mdp->rx_ring = NULL;
1294         }
1295
1296         /* Free Rx skb ringbuffer */
1297         if (mdp->rx_skbuff) {
1298                 for (i = 0; i < mdp->num_rx_ring; i++)
1299                         dev_kfree_skb(mdp->rx_skbuff[i]);
1300         }
1301         kfree(mdp->rx_skbuff);
1302         mdp->rx_skbuff = NULL;
1303
1304         if (mdp->tx_ring) {
1305                 sh_eth_tx_free(ndev, false);
1306
1307                 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1308                 dma_free_coherent(&mdp->pdev->dev, ringsize, mdp->tx_ring,
1309                                   mdp->tx_desc_dma);
1310                 mdp->tx_ring = NULL;
1311         }
1312
1313         /* Free Tx skb ringbuffer */
1314         kfree(mdp->tx_skbuff);
1315         mdp->tx_skbuff = NULL;
1316 }
1317
1318 /* format skb and descriptor buffer */
1319 static void sh_eth_ring_format(struct net_device *ndev)
1320 {
1321         struct sh_eth_private *mdp = netdev_priv(ndev);
1322         int i;
1323         struct sk_buff *skb;
1324         struct sh_eth_rxdesc *rxdesc = NULL;
1325         struct sh_eth_txdesc *txdesc = NULL;
1326         int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
1327         int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
1328         int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
1329         dma_addr_t dma_addr;
1330         u32 buf_len;
1331
1332         mdp->cur_rx = 0;
1333         mdp->cur_tx = 0;
1334         mdp->dirty_rx = 0;
1335         mdp->dirty_tx = 0;
1336
1337         memset(mdp->rx_ring, 0, rx_ringsize);
1338
1339         /* build Rx ring buffer */
1340         for (i = 0; i < mdp->num_rx_ring; i++) {
1341                 /* skb */
1342                 mdp->rx_skbuff[i] = NULL;
1343                 skb = netdev_alloc_skb(ndev, skbuff_size);
1344                 if (skb == NULL)
1345                         break;
1346                 sh_eth_set_receive_align(skb);
1347
1348                 /* The size of the buffer is a multiple of 32 bytes. */
1349                 buf_len = ALIGN(mdp->rx_buf_sz, 32);
1350                 dma_addr = dma_map_single(&mdp->pdev->dev, skb->data, buf_len,
1351                                           DMA_FROM_DEVICE);
1352                 if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) {
1353                         kfree_skb(skb);
1354                         break;
1355                 }
1356                 mdp->rx_skbuff[i] = skb;
1357
1358                 /* RX descriptor */
1359                 rxdesc = &mdp->rx_ring[i];
1360                 rxdesc->len = cpu_to_le32(buf_len << 16);
1361                 rxdesc->addr = cpu_to_le32(dma_addr);
1362                 rxdesc->status = cpu_to_le32(RD_RACT | RD_RFP);
1363
1364                 /* Rx descriptor address set */
1365                 if (i == 0) {
1366                         sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
1367                         if (mdp->cd->xdfar_rw)
1368                                 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
1369                 }
1370         }
1371
1372         mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
1373
1374         /* Mark the last entry as wrapping the ring. */
1375         if (rxdesc)
1376                 rxdesc->status |= cpu_to_le32(RD_RDLE);
1377
1378         memset(mdp->tx_ring, 0, tx_ringsize);
1379
1380         /* build Tx ring buffer */
1381         for (i = 0; i < mdp->num_tx_ring; i++) {
1382                 mdp->tx_skbuff[i] = NULL;
1383                 txdesc = &mdp->tx_ring[i];
1384                 txdesc->status = cpu_to_le32(TD_TFP);
1385                 txdesc->len = cpu_to_le32(0);
1386                 if (i == 0) {
1387                         /* Tx descriptor address set */
1388                         sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
1389                         if (mdp->cd->xdfar_rw)
1390                                 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
1391                 }
1392         }
1393
1394         txdesc->status |= cpu_to_le32(TD_TDLE);
1395 }
1396
1397 /* Get skb and descriptor buffer */
1398 static int sh_eth_ring_init(struct net_device *ndev)
1399 {
1400         struct sh_eth_private *mdp = netdev_priv(ndev);
1401         int rx_ringsize, tx_ringsize;
1402
1403         /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
1404          * card needs room to do 8 byte alignment, +2 so we can reserve
1405          * the first 2 bytes, and +16 gets room for the status word from the
1406          * card.
1407          */
1408         mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1409                           (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
1410         if (mdp->cd->rpadir)
1411                 mdp->rx_buf_sz += NET_IP_ALIGN;
1412
1413         /* Allocate RX and TX skb rings */
1414         mdp->rx_skbuff = kcalloc(mdp->num_rx_ring, sizeof(*mdp->rx_skbuff),
1415                                  GFP_KERNEL);
1416         if (!mdp->rx_skbuff)
1417                 return -ENOMEM;
1418
1419         mdp->tx_skbuff = kcalloc(mdp->num_tx_ring, sizeof(*mdp->tx_skbuff),
1420                                  GFP_KERNEL);
1421         if (!mdp->tx_skbuff)
1422                 goto ring_free;
1423
1424         /* Allocate all Rx descriptors. */
1425         rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1426         mdp->rx_ring = dma_alloc_coherent(&mdp->pdev->dev, rx_ringsize,
1427                                           &mdp->rx_desc_dma, GFP_KERNEL);
1428         if (!mdp->rx_ring)
1429                 goto ring_free;
1430
1431         mdp->dirty_rx = 0;
1432
1433         /* Allocate all Tx descriptors. */
1434         tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1435         mdp->tx_ring = dma_alloc_coherent(&mdp->pdev->dev, tx_ringsize,
1436                                           &mdp->tx_desc_dma, GFP_KERNEL);
1437         if (!mdp->tx_ring)
1438                 goto ring_free;
1439         return 0;
1440
1441 ring_free:
1442         /* Free Rx and Tx skb ring buffer and DMA buffer */
1443         sh_eth_ring_free(ndev);
1444
1445         return -ENOMEM;
1446 }
1447
1448 static int sh_eth_dev_init(struct net_device *ndev)
1449 {
1450         struct sh_eth_private *mdp = netdev_priv(ndev);
1451         int ret;
1452
1453         /* Soft Reset */
1454         ret = mdp->cd->soft_reset(ndev);
1455         if (ret)
1456                 return ret;
1457
1458         if (mdp->cd->rmiimode)
1459                 sh_eth_write(ndev, 0x1, RMIIMODE);
1460
1461         /* Descriptor format */
1462         sh_eth_ring_format(ndev);
1463         if (mdp->cd->rpadir)
1464                 sh_eth_write(ndev, NET_IP_ALIGN << 16, RPADIR);
1465
1466         /* all sh_eth int mask */
1467         sh_eth_write(ndev, 0, EESIPR);
1468
1469 #if defined(__LITTLE_ENDIAN)
1470         if (mdp->cd->hw_swap)
1471                 sh_eth_write(ndev, EDMR_EL, EDMR);
1472         else
1473 #endif
1474                 sh_eth_write(ndev, 0, EDMR);
1475
1476         /* FIFO size set */
1477         sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1478         sh_eth_write(ndev, 0, TFTR);
1479
1480         /* Frame recv control (enable multiple-packets per rx irq) */
1481         sh_eth_write(ndev, RMCR_RNC, RMCR);
1482
1483         sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER);
1484
1485         /* DMA transfer burst mode */
1486         if (mdp->cd->nbst)
1487                 sh_eth_modify(ndev, EDMR, EDMR_NBST, EDMR_NBST);
1488
1489         /* Burst cycle count upper-limit */
1490         if (mdp->cd->bculr)
1491                 sh_eth_write(ndev, 0x800, BCULR);
1492
1493         sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
1494
1495         if (!mdp->cd->no_trimd)
1496                 sh_eth_write(ndev, 0, TRIMD);
1497
1498         /* Recv frame limit set register */
1499         sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1500                      RFLR);
1501
1502         sh_eth_modify(ndev, EESR, 0, 0);
1503         mdp->irq_enabled = true;
1504         sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1505
1506         /* PAUSE Prohibition */
1507         sh_eth_write(ndev, ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) |
1508                      ECMR_TE | ECMR_RE, ECMR);
1509
1510         if (mdp->cd->set_rate)
1511                 mdp->cd->set_rate(ndev);
1512
1513         /* E-MAC Status Register clear */
1514         sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
1515
1516         /* E-MAC Interrupt Enable register */
1517         sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
1518
1519         /* Set MAC address */
1520         update_mac_address(ndev);
1521
1522         /* mask reset */
1523         if (mdp->cd->apr)
1524                 sh_eth_write(ndev, 1, APR);
1525         if (mdp->cd->mpr)
1526                 sh_eth_write(ndev, 1, MPR);
1527         if (mdp->cd->tpauser)
1528                 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
1529
1530         /* Setting the Rx mode will start the Rx process. */
1531         sh_eth_write(ndev, EDRRR_R, EDRRR);
1532
1533         return ret;
1534 }
1535
1536 static void sh_eth_dev_exit(struct net_device *ndev)
1537 {
1538         struct sh_eth_private *mdp = netdev_priv(ndev);
1539         int i;
1540
1541         /* Deactivate all TX descriptors, so DMA should stop at next
1542          * packet boundary if it's currently running
1543          */
1544         for (i = 0; i < mdp->num_tx_ring; i++)
1545                 mdp->tx_ring[i].status &= ~cpu_to_le32(TD_TACT);
1546
1547         /* Disable TX FIFO egress to MAC */
1548         sh_eth_rcv_snd_disable(ndev);
1549
1550         /* Stop RX DMA at next packet boundary */
1551         sh_eth_write(ndev, 0, EDRRR);
1552
1553         /* Aside from TX DMA, we can't tell when the hardware is
1554          * really stopped, so we need to reset to make sure.
1555          * Before doing that, wait for long enough to *probably*
1556          * finish transmitting the last packet and poll stats.
1557          */
1558         msleep(2); /* max frame time at 10 Mbps < 1250 us */
1559         sh_eth_get_stats(ndev);
1560         mdp->cd->soft_reset(ndev);
1561
1562         /* Set MAC address again */
1563         update_mac_address(ndev);
1564 }
1565
1566 /* Packet receive function */
1567 static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
1568 {
1569         struct sh_eth_private *mdp = netdev_priv(ndev);
1570         struct sh_eth_rxdesc *rxdesc;
1571
1572         int entry = mdp->cur_rx % mdp->num_rx_ring;
1573         int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
1574         int limit;
1575         struct sk_buff *skb;
1576         u32 desc_status;
1577         int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
1578         dma_addr_t dma_addr;
1579         u16 pkt_len;
1580         u32 buf_len;
1581
1582         boguscnt = min(boguscnt, *quota);
1583         limit = boguscnt;
1584         rxdesc = &mdp->rx_ring[entry];
1585         while (!(rxdesc->status & cpu_to_le32(RD_RACT))) {
1586                 /* RACT bit must be checked before all the following reads */
1587                 dma_rmb();
1588                 desc_status = le32_to_cpu(rxdesc->status);
1589                 pkt_len = le32_to_cpu(rxdesc->len) & RD_RFL;
1590
1591                 if (--boguscnt < 0)
1592                         break;
1593
1594                 netif_info(mdp, rx_status, ndev,
1595                            "rx entry %d status 0x%08x len %d\n",
1596                            entry, desc_status, pkt_len);
1597
1598                 if (!(desc_status & RDFEND))
1599                         ndev->stats.rx_length_errors++;
1600
1601                 /* In case of almost all GETHER/ETHERs, the Receive Frame State
1602                  * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
1603                  * bit 0. However, in case of the R8A7740 and R7S72100
1604                  * the RFS bits are from bit 25 to bit 16. So, the
1605                  * driver needs right shifting by 16.
1606                  */
1607                 if (mdp->cd->hw_checksum)
1608                         desc_status >>= 16;
1609
1610                 skb = mdp->rx_skbuff[entry];
1611                 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1612                                    RD_RFS5 | RD_RFS6 | RD_RFS10)) {
1613                         ndev->stats.rx_errors++;
1614                         if (desc_status & RD_RFS1)
1615                                 ndev->stats.rx_crc_errors++;
1616                         if (desc_status & RD_RFS2)
1617                                 ndev->stats.rx_frame_errors++;
1618                         if (desc_status & RD_RFS3)
1619                                 ndev->stats.rx_length_errors++;
1620                         if (desc_status & RD_RFS4)
1621                                 ndev->stats.rx_length_errors++;
1622                         if (desc_status & RD_RFS6)
1623                                 ndev->stats.rx_missed_errors++;
1624                         if (desc_status & RD_RFS10)
1625                                 ndev->stats.rx_over_errors++;
1626                 } else  if (skb) {
1627                         dma_addr = le32_to_cpu(rxdesc->addr);
1628                         if (!mdp->cd->hw_swap)
1629                                 sh_eth_soft_swap(
1630                                         phys_to_virt(ALIGN(dma_addr, 4)),
1631                                         pkt_len + 2);
1632                         mdp->rx_skbuff[entry] = NULL;
1633                         if (mdp->cd->rpadir)
1634                                 skb_reserve(skb, NET_IP_ALIGN);
1635                         dma_unmap_single(&mdp->pdev->dev, dma_addr,
1636                                          ALIGN(mdp->rx_buf_sz, 32),
1637                                          DMA_FROM_DEVICE);
1638                         skb_put(skb, pkt_len);
1639                         skb->protocol = eth_type_trans(skb, ndev);
1640                         netif_receive_skb(skb);
1641                         ndev->stats.rx_packets++;
1642                         ndev->stats.rx_bytes += pkt_len;
1643                         if (desc_status & RD_RFS8)
1644                                 ndev->stats.multicast++;
1645                 }
1646                 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
1647                 rxdesc = &mdp->rx_ring[entry];
1648         }
1649
1650         /* Refill the Rx ring buffers. */
1651         for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
1652                 entry = mdp->dirty_rx % mdp->num_rx_ring;
1653                 rxdesc = &mdp->rx_ring[entry];
1654                 /* The size of the buffer is 32 byte boundary. */
1655                 buf_len = ALIGN(mdp->rx_buf_sz, 32);
1656                 rxdesc->len = cpu_to_le32(buf_len << 16);
1657
1658                 if (mdp->rx_skbuff[entry] == NULL) {
1659                         skb = netdev_alloc_skb(ndev, skbuff_size);
1660                         if (skb == NULL)
1661                                 break;  /* Better luck next round. */
1662                         sh_eth_set_receive_align(skb);
1663                         dma_addr = dma_map_single(&mdp->pdev->dev, skb->data,
1664                                                   buf_len, DMA_FROM_DEVICE);
1665                         if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) {
1666                                 kfree_skb(skb);
1667                                 break;
1668                         }
1669                         mdp->rx_skbuff[entry] = skb;
1670
1671                         skb_checksum_none_assert(skb);
1672                         rxdesc->addr = cpu_to_le32(dma_addr);
1673                 }
1674                 dma_wmb(); /* RACT bit must be set after all the above writes */
1675                 if (entry >= mdp->num_rx_ring - 1)
1676                         rxdesc->status |=
1677                                 cpu_to_le32(RD_RACT | RD_RFP | RD_RDLE);
1678                 else
1679                         rxdesc->status |= cpu_to_le32(RD_RACT | RD_RFP);
1680         }
1681
1682         /* Restart Rx engine if stopped. */
1683         /* If we don't need to check status, don't. -KDU */
1684         if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
1685                 /* fix the values for the next receiving if RDE is set */
1686                 if (intr_status & EESR_RDE && !mdp->cd->no_xdfar) {
1687                         u32 count = (sh_eth_read(ndev, RDFAR) -
1688                                      sh_eth_read(ndev, RDLAR)) >> 4;
1689
1690                         mdp->cur_rx = count;
1691                         mdp->dirty_rx = count;
1692                 }
1693                 sh_eth_write(ndev, EDRRR_R, EDRRR);
1694         }
1695
1696         *quota -= limit - boguscnt - 1;
1697
1698         return *quota <= 0;
1699 }
1700
1701 static void sh_eth_rcv_snd_disable(struct net_device *ndev)
1702 {
1703         /* disable tx and rx */
1704         sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0);
1705 }
1706
1707 static void sh_eth_rcv_snd_enable(struct net_device *ndev)
1708 {
1709         /* enable tx and rx */
1710         sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE);
1711 }
1712
1713 /* E-MAC interrupt handler */
1714 static void sh_eth_emac_interrupt(struct net_device *ndev)
1715 {
1716         struct sh_eth_private *mdp = netdev_priv(ndev);
1717         u32 felic_stat;
1718         u32 link_stat;
1719
1720         felic_stat = sh_eth_read(ndev, ECSR) & sh_eth_read(ndev, ECSIPR);
1721         sh_eth_write(ndev, felic_stat, ECSR);   /* clear int */
1722         if (felic_stat & ECSR_ICD)
1723                 ndev->stats.tx_carrier_errors++;
1724         if (felic_stat & ECSR_MPD)
1725                 pm_wakeup_event(&mdp->pdev->dev, 0);
1726         if (felic_stat & ECSR_LCHNG) {
1727                 /* Link Changed */
1728                 if (mdp->cd->no_psr || mdp->no_ether_link)
1729                         return;
1730                 link_stat = sh_eth_read(ndev, PSR);
1731                 if (mdp->ether_link_active_low)
1732                         link_stat = ~link_stat;
1733                 if (!(link_stat & PHY_ST_LINK)) {
1734                         sh_eth_rcv_snd_disable(ndev);
1735                 } else {
1736                         /* Link Up */
1737                         sh_eth_modify(ndev, EESIPR, EESIPR_ECIIP, 0);
1738                         /* clear int */
1739                         sh_eth_modify(ndev, ECSR, 0, 0);
1740                         sh_eth_modify(ndev, EESIPR, EESIPR_ECIIP, EESIPR_ECIIP);
1741                         /* enable tx and rx */
1742                         sh_eth_rcv_snd_enable(ndev);
1743                 }
1744         }
1745 }
1746
1747 /* error control function */
1748 static void sh_eth_error(struct net_device *ndev, u32 intr_status)
1749 {
1750         struct sh_eth_private *mdp = netdev_priv(ndev);
1751         u32 mask;
1752
1753         if (intr_status & EESR_TWB) {
1754                 /* Unused write back interrupt */
1755                 if (intr_status & EESR_TABT) {  /* Transmit Abort int */
1756                         ndev->stats.tx_aborted_errors++;
1757                         netif_err(mdp, tx_err, ndev, "Transmit Abort\n");
1758                 }
1759         }
1760
1761         if (intr_status & EESR_RABT) {
1762                 /* Receive Abort int */
1763                 if (intr_status & EESR_RFRMER) {
1764                         /* Receive Frame Overflow int */
1765                         ndev->stats.rx_frame_errors++;
1766                 }
1767         }
1768
1769         if (intr_status & EESR_TDE) {
1770                 /* Transmit Descriptor Empty int */
1771                 ndev->stats.tx_fifo_errors++;
1772                 netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n");
1773         }
1774
1775         if (intr_status & EESR_TFE) {
1776                 /* FIFO under flow */
1777                 ndev->stats.tx_fifo_errors++;
1778                 netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n");
1779         }
1780
1781         if (intr_status & EESR_RDE) {
1782                 /* Receive Descriptor Empty int */
1783                 ndev->stats.rx_over_errors++;
1784         }
1785
1786         if (intr_status & EESR_RFE) {
1787                 /* Receive FIFO Overflow int */
1788                 ndev->stats.rx_fifo_errors++;
1789         }
1790
1791         if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1792                 /* Address Error */
1793                 ndev->stats.tx_fifo_errors++;
1794                 netif_err(mdp, tx_err, ndev, "Address Error\n");
1795         }
1796
1797         mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1798         if (mdp->cd->no_ade)
1799                 mask &= ~EESR_ADE;
1800         if (intr_status & mask) {
1801                 /* Tx error */
1802                 u32 edtrr = sh_eth_read(ndev, EDTRR);
1803
1804                 /* dmesg */
1805                 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1806                            intr_status, mdp->cur_tx, mdp->dirty_tx,
1807                            (u32)ndev->state, edtrr);
1808                 /* dirty buffer free */
1809                 sh_eth_tx_free(ndev, true);
1810
1811                 /* SH7712 BUG */
1812                 if (edtrr ^ mdp->cd->edtrr_trns) {
1813                         /* tx dma start */
1814                         sh_eth_write(ndev, mdp->cd->edtrr_trns, EDTRR);
1815                 }
1816                 /* wakeup */
1817                 netif_wake_queue(ndev);
1818         }
1819 }
1820
1821 static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1822 {
1823         struct net_device *ndev = netdev;
1824         struct sh_eth_private *mdp = netdev_priv(ndev);
1825         struct sh_eth_cpu_data *cd = mdp->cd;
1826         irqreturn_t ret = IRQ_NONE;
1827         u32 intr_status, intr_enable;
1828
1829         spin_lock(&mdp->lock);
1830
1831         /* Get interrupt status */
1832         intr_status = sh_eth_read(ndev, EESR);
1833         /* Mask it with the interrupt mask, forcing ECI interrupt  to be always
1834          * enabled since it's the one that  comes  thru regardless of the mask,
1835          * and  we need to fully handle it  in sh_eth_emac_interrupt() in order
1836          * to quench it as it doesn't get cleared by just writing 1 to the  ECI
1837          * bit...
1838          */
1839         intr_enable = sh_eth_read(ndev, EESIPR);
1840         intr_status &= intr_enable | EESIPR_ECIIP;
1841         if (intr_status & (EESR_RX_CHECK | cd->tx_check | EESR_ECI |
1842                            cd->eesr_err_check))
1843                 ret = IRQ_HANDLED;
1844         else
1845                 goto out;
1846
1847         if (unlikely(!mdp->irq_enabled)) {
1848                 sh_eth_write(ndev, 0, EESIPR);
1849                 goto out;
1850         }
1851
1852         if (intr_status & EESR_RX_CHECK) {
1853                 if (napi_schedule_prep(&mdp->napi)) {
1854                         /* Mask Rx interrupts */
1855                         sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
1856                                      EESIPR);
1857                         __napi_schedule(&mdp->napi);
1858                 } else {
1859                         netdev_warn(ndev,
1860                                     "ignoring interrupt, status 0x%08x, mask 0x%08x.\n",
1861                                     intr_status, intr_enable);
1862                 }
1863         }
1864
1865         /* Tx Check */
1866         if (intr_status & cd->tx_check) {
1867                 /* Clear Tx interrupts */
1868                 sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
1869
1870                 sh_eth_tx_free(ndev, true);
1871                 netif_wake_queue(ndev);
1872         }
1873
1874         /* E-MAC interrupt */
1875         if (intr_status & EESR_ECI)
1876                 sh_eth_emac_interrupt(ndev);
1877
1878         if (intr_status & cd->eesr_err_check) {
1879                 /* Clear error interrupts */
1880                 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
1881
1882                 sh_eth_error(ndev, intr_status);
1883         }
1884
1885 out:
1886         spin_unlock(&mdp->lock);
1887
1888         return ret;
1889 }
1890
1891 static int sh_eth_poll(struct napi_struct *napi, int budget)
1892 {
1893         struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
1894                                                   napi);
1895         struct net_device *ndev = napi->dev;
1896         int quota = budget;
1897         u32 intr_status;
1898
1899         for (;;) {
1900                 intr_status = sh_eth_read(ndev, EESR);
1901                 if (!(intr_status & EESR_RX_CHECK))
1902                         break;
1903                 /* Clear Rx interrupts */
1904                 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
1905
1906                 if (sh_eth_rx(ndev, intr_status, &quota))
1907                         goto out;
1908         }
1909
1910         napi_complete(napi);
1911
1912         /* Reenable Rx interrupts */
1913         if (mdp->irq_enabled)
1914                 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1915 out:
1916         return budget - quota;
1917 }
1918
1919 /* PHY state control function */
1920 static void sh_eth_adjust_link(struct net_device *ndev)
1921 {
1922         struct sh_eth_private *mdp = netdev_priv(ndev);
1923         struct phy_device *phydev = ndev->phydev;
1924         unsigned long flags;
1925         int new_state = 0;
1926
1927         spin_lock_irqsave(&mdp->lock, flags);
1928
1929         /* Disable TX and RX right over here, if E-MAC change is ignored */
1930         if (mdp->cd->no_psr || mdp->no_ether_link)
1931                 sh_eth_rcv_snd_disable(ndev);
1932
1933         if (phydev->link) {
1934                 if (phydev->duplex != mdp->duplex) {
1935                         new_state = 1;
1936                         mdp->duplex = phydev->duplex;
1937                         if (mdp->cd->set_duplex)
1938                                 mdp->cd->set_duplex(ndev);
1939                 }
1940
1941                 if (phydev->speed != mdp->speed) {
1942                         new_state = 1;
1943                         mdp->speed = phydev->speed;
1944                         if (mdp->cd->set_rate)
1945                                 mdp->cd->set_rate(ndev);
1946                 }
1947                 if (!mdp->link) {
1948                         sh_eth_modify(ndev, ECMR, ECMR_TXF, 0);
1949                         new_state = 1;
1950                         mdp->link = phydev->link;
1951                 }
1952         } else if (mdp->link) {
1953                 new_state = 1;
1954                 mdp->link = 0;
1955                 mdp->speed = 0;
1956                 mdp->duplex = -1;
1957         }
1958
1959         /* Enable TX and RX right over here, if E-MAC change is ignored */
1960         if ((mdp->cd->no_psr || mdp->no_ether_link) && phydev->link)
1961                 sh_eth_rcv_snd_enable(ndev);
1962
1963         mmiowb();
1964         spin_unlock_irqrestore(&mdp->lock, flags);
1965
1966         if (new_state && netif_msg_link(mdp))
1967                 phy_print_status(phydev);
1968 }
1969
1970 /* PHY init function */
1971 static int sh_eth_phy_init(struct net_device *ndev)
1972 {
1973         struct device_node *np = ndev->dev.parent->of_node;
1974         struct sh_eth_private *mdp = netdev_priv(ndev);
1975         struct phy_device *phydev;
1976
1977         mdp->link = 0;
1978         mdp->speed = 0;
1979         mdp->duplex = -1;
1980
1981         /* Try connect to PHY */
1982         if (np) {
1983                 struct device_node *pn;
1984
1985                 pn = of_parse_phandle(np, "phy-handle", 0);
1986                 phydev = of_phy_connect(ndev, pn,
1987                                         sh_eth_adjust_link, 0,
1988                                         mdp->phy_interface);
1989
1990                 of_node_put(pn);
1991                 if (!phydev)
1992                         phydev = ERR_PTR(-ENOENT);
1993         } else {
1994                 char phy_id[MII_BUS_ID_SIZE + 3];
1995
1996                 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1997                          mdp->mii_bus->id, mdp->phy_id);
1998
1999                 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
2000                                      mdp->phy_interface);
2001         }
2002
2003         if (IS_ERR(phydev)) {
2004                 netdev_err(ndev, "failed to connect PHY\n");
2005                 return PTR_ERR(phydev);
2006         }
2007
2008         /* mask with MAC supported features */
2009         if (mdp->cd->register_type != SH_ETH_REG_GIGABIT) {
2010                 int err = phy_set_max_speed(phydev, SPEED_100);
2011                 if (err) {
2012                         netdev_err(ndev, "failed to limit PHY to 100 Mbit/s\n");
2013                         phy_disconnect(phydev);
2014                         return err;
2015                 }
2016         }
2017
2018         phy_attached_info(phydev);
2019
2020         return 0;
2021 }
2022
2023 /* PHY control start function */
2024 static int sh_eth_phy_start(struct net_device *ndev)
2025 {
2026         int ret;
2027
2028         ret = sh_eth_phy_init(ndev);
2029         if (ret)
2030                 return ret;
2031
2032         phy_start(ndev->phydev);
2033
2034         return 0;
2035 }
2036
2037 /* If it is ever necessary to increase SH_ETH_REG_DUMP_MAX_REGS, the
2038  * version must be bumped as well.  Just adding registers up to that
2039  * limit is fine, as long as the existing register indices don't
2040  * change.
2041  */
2042 #define SH_ETH_REG_DUMP_VERSION         1
2043 #define SH_ETH_REG_DUMP_MAX_REGS        256
2044
2045 static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf)
2046 {
2047         struct sh_eth_private *mdp = netdev_priv(ndev);
2048         struct sh_eth_cpu_data *cd = mdp->cd;
2049         u32 *valid_map;
2050         size_t len;
2051
2052         BUILD_BUG_ON(SH_ETH_MAX_REGISTER_OFFSET > SH_ETH_REG_DUMP_MAX_REGS);
2053
2054         /* Dump starts with a bitmap that tells ethtool which
2055          * registers are defined for this chip.
2056          */
2057         len = DIV_ROUND_UP(SH_ETH_REG_DUMP_MAX_REGS, 32);
2058         if (buf) {
2059                 valid_map = buf;
2060                 buf += len;
2061         } else {
2062                 valid_map = NULL;
2063         }
2064
2065         /* Add a register to the dump, if it has a defined offset.
2066          * This automatically skips most undefined registers, but for
2067          * some it is also necessary to check a capability flag in
2068          * struct sh_eth_cpu_data.
2069          */
2070 #define mark_reg_valid(reg) valid_map[reg / 32] |= 1U << (reg % 32)
2071 #define add_reg_from(reg, read_expr) do {                               \
2072                 if (mdp->reg_offset[reg] != SH_ETH_OFFSET_INVALID) {    \
2073                         if (buf) {                                      \
2074                                 mark_reg_valid(reg);                    \
2075                                 *buf++ = read_expr;                     \
2076                         }                                               \
2077                         ++len;                                          \
2078                 }                                                       \
2079         } while (0)
2080 #define add_reg(reg) add_reg_from(reg, sh_eth_read(ndev, reg))
2081 #define add_tsu_reg(reg) add_reg_from(reg, sh_eth_tsu_read(mdp, reg))
2082
2083         add_reg(EDSR);
2084         add_reg(EDMR);
2085         add_reg(EDTRR);
2086         add_reg(EDRRR);
2087         add_reg(EESR);
2088         add_reg(EESIPR);
2089         add_reg(TDLAR);
2090         add_reg(TDFAR);
2091         add_reg(TDFXR);
2092         add_reg(TDFFR);
2093         add_reg(RDLAR);
2094         add_reg(RDFAR);
2095         add_reg(RDFXR);
2096         add_reg(RDFFR);
2097         add_reg(TRSCER);
2098         add_reg(RMFCR);
2099         add_reg(TFTR);
2100         add_reg(FDR);
2101         add_reg(RMCR);
2102         add_reg(TFUCR);
2103         add_reg(RFOCR);
2104         if (cd->rmiimode)
2105                 add_reg(RMIIMODE);
2106         add_reg(FCFTR);
2107         if (cd->rpadir)
2108                 add_reg(RPADIR);
2109         if (!cd->no_trimd)
2110                 add_reg(TRIMD);
2111         add_reg(ECMR);
2112         add_reg(ECSR);
2113         add_reg(ECSIPR);
2114         add_reg(PIR);
2115         if (!cd->no_psr)
2116                 add_reg(PSR);
2117         add_reg(RDMLR);
2118         add_reg(RFLR);
2119         add_reg(IPGR);
2120         if (cd->apr)
2121                 add_reg(APR);
2122         if (cd->mpr)
2123                 add_reg(MPR);
2124         add_reg(RFCR);
2125         add_reg(RFCF);
2126         if (cd->tpauser)
2127                 add_reg(TPAUSER);
2128         add_reg(TPAUSECR);
2129         add_reg(GECMR);
2130         if (cd->bculr)
2131                 add_reg(BCULR);
2132         add_reg(MAHR);
2133         add_reg(MALR);
2134         add_reg(TROCR);
2135         add_reg(CDCR);
2136         add_reg(LCCR);
2137         add_reg(CNDCR);
2138         add_reg(CEFCR);
2139         add_reg(FRECR);
2140         add_reg(TSFRCR);
2141         add_reg(TLFRCR);
2142         add_reg(CERCR);
2143         add_reg(CEECR);
2144         add_reg(MAFCR);
2145         if (cd->rtrate)
2146                 add_reg(RTRATE);
2147         if (cd->hw_checksum)
2148                 add_reg(CSMR);
2149         if (cd->select_mii)
2150                 add_reg(RMII_MII);
2151         if (cd->tsu) {
2152                 add_tsu_reg(ARSTR);
2153                 add_tsu_reg(TSU_CTRST);
2154                 add_tsu_reg(TSU_FWEN0);
2155                 add_tsu_reg(TSU_FWEN1);
2156                 add_tsu_reg(TSU_FCM);
2157                 add_tsu_reg(TSU_BSYSL0);
2158                 add_tsu_reg(TSU_BSYSL1);
2159                 add_tsu_reg(TSU_PRISL0);
2160                 add_tsu_reg(TSU_PRISL1);
2161                 add_tsu_reg(TSU_FWSL0);
2162                 add_tsu_reg(TSU_FWSL1);
2163                 add_tsu_reg(TSU_FWSLC);
2164                 add_tsu_reg(TSU_QTAGM0);
2165                 add_tsu_reg(TSU_QTAGM1);
2166                 add_tsu_reg(TSU_FWSR);
2167                 add_tsu_reg(TSU_FWINMK);
2168                 add_tsu_reg(TSU_ADQT0);
2169                 add_tsu_reg(TSU_ADQT1);
2170                 add_tsu_reg(TSU_VTAG0);
2171                 add_tsu_reg(TSU_VTAG1);
2172                 add_tsu_reg(TSU_ADSBSY);
2173                 add_tsu_reg(TSU_TEN);
2174                 add_tsu_reg(TSU_POST1);
2175                 add_tsu_reg(TSU_POST2);
2176                 add_tsu_reg(TSU_POST3);
2177                 add_tsu_reg(TSU_POST4);
2178                 /* This is the start of a table, not just a single register. */
2179                 if (buf) {
2180                         unsigned int i;
2181
2182                         mark_reg_valid(TSU_ADRH0);
2183                         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES * 2; i++)
2184                                 *buf++ = ioread32(mdp->tsu_addr +
2185                                                   mdp->reg_offset[TSU_ADRH0] +
2186                                                   i * 4);
2187                 }
2188                 len += SH_ETH_TSU_CAM_ENTRIES * 2;
2189         }
2190
2191 #undef mark_reg_valid
2192 #undef add_reg_from
2193 #undef add_reg
2194 #undef add_tsu_reg
2195
2196         return len * 4;
2197 }
2198
2199 static int sh_eth_get_regs_len(struct net_device *ndev)
2200 {
2201         return __sh_eth_get_regs(ndev, NULL);
2202 }
2203
2204 static void sh_eth_get_regs(struct net_device *ndev, struct ethtool_regs *regs,
2205                             void *buf)
2206 {
2207         struct sh_eth_private *mdp = netdev_priv(ndev);
2208
2209         regs->version = SH_ETH_REG_DUMP_VERSION;
2210
2211         pm_runtime_get_sync(&mdp->pdev->dev);
2212         __sh_eth_get_regs(ndev, buf);
2213         pm_runtime_put_sync(&mdp->pdev->dev);
2214 }
2215
2216 static u32 sh_eth_get_msglevel(struct net_device *ndev)
2217 {
2218         struct sh_eth_private *mdp = netdev_priv(ndev);
2219         return mdp->msg_enable;
2220 }
2221
2222 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
2223 {
2224         struct sh_eth_private *mdp = netdev_priv(ndev);
2225         mdp->msg_enable = value;
2226 }
2227
2228 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
2229         "rx_current", "tx_current",
2230         "rx_dirty", "tx_dirty",
2231 };
2232 #define SH_ETH_STATS_LEN  ARRAY_SIZE(sh_eth_gstrings_stats)
2233
2234 static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
2235 {
2236         switch (sset) {
2237         case ETH_SS_STATS:
2238                 return SH_ETH_STATS_LEN;
2239         default:
2240                 return -EOPNOTSUPP;
2241         }
2242 }
2243
2244 static void sh_eth_get_ethtool_stats(struct net_device *ndev,
2245                                      struct ethtool_stats *stats, u64 *data)
2246 {
2247         struct sh_eth_private *mdp = netdev_priv(ndev);
2248         int i = 0;
2249
2250         /* device-specific stats */
2251         data[i++] = mdp->cur_rx;
2252         data[i++] = mdp->cur_tx;
2253         data[i++] = mdp->dirty_rx;
2254         data[i++] = mdp->dirty_tx;
2255 }
2256
2257 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
2258 {
2259         switch (stringset) {
2260         case ETH_SS_STATS:
2261                 memcpy(data, *sh_eth_gstrings_stats,
2262                        sizeof(sh_eth_gstrings_stats));
2263                 break;
2264         }
2265 }
2266
2267 static void sh_eth_get_ringparam(struct net_device *ndev,
2268                                  struct ethtool_ringparam *ring)
2269 {
2270         struct sh_eth_private *mdp = netdev_priv(ndev);
2271
2272         ring->rx_max_pending = RX_RING_MAX;
2273         ring->tx_max_pending = TX_RING_MAX;
2274         ring->rx_pending = mdp->num_rx_ring;
2275         ring->tx_pending = mdp->num_tx_ring;
2276 }
2277
2278 static int sh_eth_set_ringparam(struct net_device *ndev,
2279                                 struct ethtool_ringparam *ring)
2280 {
2281         struct sh_eth_private *mdp = netdev_priv(ndev);
2282         int ret;
2283
2284         if (ring->tx_pending > TX_RING_MAX ||
2285             ring->rx_pending > RX_RING_MAX ||
2286             ring->tx_pending < TX_RING_MIN ||
2287             ring->rx_pending < RX_RING_MIN)
2288                 return -EINVAL;
2289         if (ring->rx_mini_pending || ring->rx_jumbo_pending)
2290                 return -EINVAL;
2291
2292         if (netif_running(ndev)) {
2293                 netif_device_detach(ndev);
2294                 netif_tx_disable(ndev);
2295
2296                 /* Serialise with the interrupt handler and NAPI, then
2297                  * disable interrupts.  We have to clear the
2298                  * irq_enabled flag first to ensure that interrupts
2299                  * won't be re-enabled.
2300                  */
2301                 mdp->irq_enabled = false;
2302                 synchronize_irq(ndev->irq);
2303                 napi_synchronize(&mdp->napi);
2304                 sh_eth_write(ndev, 0x0000, EESIPR);
2305
2306                 sh_eth_dev_exit(ndev);
2307
2308                 /* Free all the skbuffs in the Rx queue and the DMA buffers. */
2309                 sh_eth_ring_free(ndev);
2310         }
2311
2312         /* Set new parameters */
2313         mdp->num_rx_ring = ring->rx_pending;
2314         mdp->num_tx_ring = ring->tx_pending;
2315
2316         if (netif_running(ndev)) {
2317                 ret = sh_eth_ring_init(ndev);
2318                 if (ret < 0) {
2319                         netdev_err(ndev, "%s: sh_eth_ring_init failed.\n",
2320                                    __func__);
2321                         return ret;
2322                 }
2323                 ret = sh_eth_dev_init(ndev);
2324                 if (ret < 0) {
2325                         netdev_err(ndev, "%s: sh_eth_dev_init failed.\n",
2326                                    __func__);
2327                         return ret;
2328                 }
2329
2330                 netif_device_attach(ndev);
2331         }
2332
2333         return 0;
2334 }
2335
2336 static void sh_eth_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2337 {
2338         struct sh_eth_private *mdp = netdev_priv(ndev);
2339
2340         wol->supported = 0;
2341         wol->wolopts = 0;
2342
2343         if (mdp->cd->magic) {
2344                 wol->supported = WAKE_MAGIC;
2345                 wol->wolopts = mdp->wol_enabled ? WAKE_MAGIC : 0;
2346         }
2347 }
2348
2349 static int sh_eth_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2350 {
2351         struct sh_eth_private *mdp = netdev_priv(ndev);
2352
2353         if (!mdp->cd->magic || wol->wolopts & ~WAKE_MAGIC)
2354                 return -EOPNOTSUPP;
2355
2356         mdp->wol_enabled = !!(wol->wolopts & WAKE_MAGIC);
2357
2358         device_set_wakeup_enable(&mdp->pdev->dev, mdp->wol_enabled);
2359
2360         return 0;
2361 }
2362
2363 static const struct ethtool_ops sh_eth_ethtool_ops = {
2364         .get_regs_len   = sh_eth_get_regs_len,
2365         .get_regs       = sh_eth_get_regs,
2366         .nway_reset     = phy_ethtool_nway_reset,
2367         .get_msglevel   = sh_eth_get_msglevel,
2368         .set_msglevel   = sh_eth_set_msglevel,
2369         .get_link       = ethtool_op_get_link,
2370         .get_strings    = sh_eth_get_strings,
2371         .get_ethtool_stats  = sh_eth_get_ethtool_stats,
2372         .get_sset_count     = sh_eth_get_sset_count,
2373         .get_ringparam  = sh_eth_get_ringparam,
2374         .set_ringparam  = sh_eth_set_ringparam,
2375         .get_link_ksettings = phy_ethtool_get_link_ksettings,
2376         .set_link_ksettings = phy_ethtool_set_link_ksettings,
2377         .get_wol        = sh_eth_get_wol,
2378         .set_wol        = sh_eth_set_wol,
2379 };
2380
2381 /* network device open function */
2382 static int sh_eth_open(struct net_device *ndev)
2383 {
2384         struct sh_eth_private *mdp = netdev_priv(ndev);
2385         int ret;
2386
2387         pm_runtime_get_sync(&mdp->pdev->dev);
2388
2389         napi_enable(&mdp->napi);
2390
2391         ret = request_irq(ndev->irq, sh_eth_interrupt,
2392                           mdp->cd->irq_flags, ndev->name, ndev);
2393         if (ret) {
2394                 netdev_err(ndev, "Can not assign IRQ number\n");
2395                 goto out_napi_off;
2396         }
2397
2398         /* Descriptor set */
2399         ret = sh_eth_ring_init(ndev);
2400         if (ret)
2401                 goto out_free_irq;
2402
2403         /* device init */
2404         ret = sh_eth_dev_init(ndev);
2405         if (ret)
2406                 goto out_free_irq;
2407
2408         /* PHY control start*/
2409         ret = sh_eth_phy_start(ndev);
2410         if (ret)
2411                 goto out_free_irq;
2412
2413         netif_start_queue(ndev);
2414
2415         mdp->is_opened = 1;
2416
2417         return ret;
2418
2419 out_free_irq:
2420         free_irq(ndev->irq, ndev);
2421 out_napi_off:
2422         napi_disable(&mdp->napi);
2423         pm_runtime_put_sync(&mdp->pdev->dev);
2424         return ret;
2425 }
2426
2427 /* Timeout function */
2428 static void sh_eth_tx_timeout(struct net_device *ndev)
2429 {
2430         struct sh_eth_private *mdp = netdev_priv(ndev);
2431         struct sh_eth_rxdesc *rxdesc;
2432         int i;
2433
2434         netif_stop_queue(ndev);
2435
2436         netif_err(mdp, timer, ndev,
2437                   "transmit timed out, status %8.8x, resetting...\n",
2438                   sh_eth_read(ndev, EESR));
2439
2440         /* tx_errors count up */
2441         ndev->stats.tx_errors++;
2442
2443         /* Free all the skbuffs in the Rx queue. */
2444         for (i = 0; i < mdp->num_rx_ring; i++) {
2445                 rxdesc = &mdp->rx_ring[i];
2446                 rxdesc->status = cpu_to_le32(0);
2447                 rxdesc->addr = cpu_to_le32(0xBADF00D0);
2448                 dev_kfree_skb(mdp->rx_skbuff[i]);
2449                 mdp->rx_skbuff[i] = NULL;
2450         }
2451         for (i = 0; i < mdp->num_tx_ring; i++) {
2452                 dev_kfree_skb(mdp->tx_skbuff[i]);
2453                 mdp->tx_skbuff[i] = NULL;
2454         }
2455
2456         /* device init */
2457         sh_eth_dev_init(ndev);
2458
2459         netif_start_queue(ndev);
2460 }
2461
2462 /* Packet transmit function */
2463 static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
2464 {
2465         struct sh_eth_private *mdp = netdev_priv(ndev);
2466         struct sh_eth_txdesc *txdesc;
2467         dma_addr_t dma_addr;
2468         u32 entry;
2469         unsigned long flags;
2470
2471         spin_lock_irqsave(&mdp->lock, flags);
2472         if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
2473                 if (!sh_eth_tx_free(ndev, true)) {
2474                         netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n");
2475                         netif_stop_queue(ndev);
2476                         spin_unlock_irqrestore(&mdp->lock, flags);
2477                         return NETDEV_TX_BUSY;
2478                 }
2479         }
2480         spin_unlock_irqrestore(&mdp->lock, flags);
2481
2482         if (skb_put_padto(skb, ETH_ZLEN))
2483                 return NETDEV_TX_OK;
2484
2485         entry = mdp->cur_tx % mdp->num_tx_ring;
2486         mdp->tx_skbuff[entry] = skb;
2487         txdesc = &mdp->tx_ring[entry];
2488         /* soft swap. */
2489         if (!mdp->cd->hw_swap)
2490                 sh_eth_soft_swap(PTR_ALIGN(skb->data, 4), skb->len + 2);
2491         dma_addr = dma_map_single(&mdp->pdev->dev, skb->data, skb->len,
2492                                   DMA_TO_DEVICE);
2493         if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) {
2494                 kfree_skb(skb);
2495                 return NETDEV_TX_OK;
2496         }
2497         txdesc->addr = cpu_to_le32(dma_addr);
2498         txdesc->len  = cpu_to_le32(skb->len << 16);
2499
2500         dma_wmb(); /* TACT bit must be set after all the above writes */
2501         if (entry >= mdp->num_tx_ring - 1)
2502                 txdesc->status |= cpu_to_le32(TD_TACT | TD_TDLE);
2503         else
2504                 txdesc->status |= cpu_to_le32(TD_TACT);
2505
2506         mdp->cur_tx++;
2507
2508         if (!(sh_eth_read(ndev, EDTRR) & mdp->cd->edtrr_trns))
2509                 sh_eth_write(ndev, mdp->cd->edtrr_trns, EDTRR);
2510
2511         return NETDEV_TX_OK;
2512 }
2513
2514 /* The statistics registers have write-clear behaviour, which means we
2515  * will lose any increment between the read and write.  We mitigate
2516  * this by only clearing when we read a non-zero value, so we will
2517  * never falsely report a total of zero.
2518  */
2519 static void
2520 sh_eth_update_stat(struct net_device *ndev, unsigned long *stat, int reg)
2521 {
2522         u32 delta = sh_eth_read(ndev, reg);
2523
2524         if (delta) {
2525                 *stat += delta;
2526                 sh_eth_write(ndev, 0, reg);
2527         }
2528 }
2529
2530 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2531 {
2532         struct sh_eth_private *mdp = netdev_priv(ndev);
2533
2534         if (mdp->cd->no_tx_cntrs)
2535                 return &ndev->stats;
2536
2537         if (!mdp->is_opened)
2538                 return &ndev->stats;
2539
2540         sh_eth_update_stat(ndev, &ndev->stats.tx_dropped, TROCR);
2541         sh_eth_update_stat(ndev, &ndev->stats.collisions, CDCR);
2542         sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, LCCR);
2543
2544         if (mdp->cd->cexcr) {
2545                 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2546                                    CERCR);
2547                 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2548                                    CEECR);
2549         } else {
2550                 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2551                                    CNDCR);
2552         }
2553
2554         return &ndev->stats;
2555 }
2556
2557 /* device close function */
2558 static int sh_eth_close(struct net_device *ndev)
2559 {
2560         struct sh_eth_private *mdp = netdev_priv(ndev);
2561
2562         netif_stop_queue(ndev);
2563
2564         /* Serialise with the interrupt handler and NAPI, then disable
2565          * interrupts.  We have to clear the irq_enabled flag first to
2566          * ensure that interrupts won't be re-enabled.
2567          */
2568         mdp->irq_enabled = false;
2569         synchronize_irq(ndev->irq);
2570         napi_disable(&mdp->napi);
2571         sh_eth_write(ndev, 0x0000, EESIPR);
2572
2573         sh_eth_dev_exit(ndev);
2574
2575         /* PHY Disconnect */
2576         if (ndev->phydev) {
2577                 phy_stop(ndev->phydev);
2578                 phy_disconnect(ndev->phydev);
2579         }
2580
2581         free_irq(ndev->irq, ndev);
2582
2583         /* Free all the skbuffs in the Rx queue and the DMA buffer. */
2584         sh_eth_ring_free(ndev);
2585
2586         pm_runtime_put_sync(&mdp->pdev->dev);
2587
2588         mdp->is_opened = 0;
2589
2590         return 0;
2591 }
2592
2593 /* ioctl to device function */
2594 static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2595 {
2596         struct phy_device *phydev = ndev->phydev;
2597
2598         if (!netif_running(ndev))
2599                 return -EINVAL;
2600
2601         if (!phydev)
2602                 return -ENODEV;
2603
2604         return phy_mii_ioctl(phydev, rq, cmd);
2605 }
2606
2607 static int sh_eth_change_mtu(struct net_device *ndev, int new_mtu)
2608 {
2609         if (netif_running(ndev))
2610                 return -EBUSY;
2611
2612         ndev->mtu = new_mtu;
2613         netdev_update_features(ndev);
2614
2615         return 0;
2616 }
2617
2618 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2619 static u32 sh_eth_tsu_get_post_mask(int entry)
2620 {
2621         return 0x0f << (28 - ((entry % 8) * 4));
2622 }
2623
2624 static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2625 {
2626         return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2627 }
2628
2629 static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2630                                              int entry)
2631 {
2632         struct sh_eth_private *mdp = netdev_priv(ndev);
2633         int reg = TSU_POST1 + entry / 8;
2634         u32 tmp;
2635
2636         tmp = sh_eth_tsu_read(mdp, reg);
2637         sh_eth_tsu_write(mdp, tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg);
2638 }
2639
2640 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2641                                               int entry)
2642 {
2643         struct sh_eth_private *mdp = netdev_priv(ndev);
2644         int reg = TSU_POST1 + entry / 8;
2645         u32 post_mask, ref_mask, tmp;
2646
2647         post_mask = sh_eth_tsu_get_post_mask(entry);
2648         ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2649
2650         tmp = sh_eth_tsu_read(mdp, reg);
2651         sh_eth_tsu_write(mdp, tmp & ~post_mask, reg);
2652
2653         /* If other port enables, the function returns "true" */
2654         return tmp & ref_mask;
2655 }
2656
2657 static int sh_eth_tsu_busy(struct net_device *ndev)
2658 {
2659         int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2660         struct sh_eth_private *mdp = netdev_priv(ndev);
2661
2662         while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2663                 udelay(10);
2664                 timeout--;
2665                 if (timeout <= 0) {
2666                         netdev_err(ndev, "%s: timeout\n", __func__);
2667                         return -ETIMEDOUT;
2668                 }
2669         }
2670
2671         return 0;
2672 }
2673
2674 static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
2675                                   const u8 *addr)
2676 {
2677         u32 val;
2678
2679         val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2680         iowrite32(val, reg);
2681         if (sh_eth_tsu_busy(ndev) < 0)
2682                 return -EBUSY;
2683
2684         val = addr[4] << 8 | addr[5];
2685         iowrite32(val, reg + 4);
2686         if (sh_eth_tsu_busy(ndev) < 0)
2687                 return -EBUSY;
2688
2689         return 0;
2690 }
2691
2692 static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
2693 {
2694         u32 val;
2695
2696         val = ioread32(reg);
2697         addr[0] = (val >> 24) & 0xff;
2698         addr[1] = (val >> 16) & 0xff;
2699         addr[2] = (val >> 8) & 0xff;
2700         addr[3] = val & 0xff;
2701         val = ioread32(reg + 4);
2702         addr[4] = (val >> 8) & 0xff;
2703         addr[5] = val & 0xff;
2704 }
2705
2706
2707 static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2708 {
2709         struct sh_eth_private *mdp = netdev_priv(ndev);
2710         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2711         int i;
2712         u8 c_addr[ETH_ALEN];
2713
2714         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2715                 sh_eth_tsu_read_entry(reg_offset, c_addr);
2716                 if (ether_addr_equal(addr, c_addr))
2717                         return i;
2718         }
2719
2720         return -ENOENT;
2721 }
2722
2723 static int sh_eth_tsu_find_empty(struct net_device *ndev)
2724 {
2725         u8 blank[ETH_ALEN];
2726         int entry;
2727
2728         memset(blank, 0, sizeof(blank));
2729         entry = sh_eth_tsu_find_entry(ndev, blank);
2730         return (entry < 0) ? -ENOMEM : entry;
2731 }
2732
2733 static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2734                                               int entry)
2735 {
2736         struct sh_eth_private *mdp = netdev_priv(ndev);
2737         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2738         int ret;
2739         u8 blank[ETH_ALEN];
2740
2741         sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2742                          ~(1 << (31 - entry)), TSU_TEN);
2743
2744         memset(blank, 0, sizeof(blank));
2745         ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2746         if (ret < 0)
2747                 return ret;
2748         return 0;
2749 }
2750
2751 static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2752 {
2753         struct sh_eth_private *mdp = netdev_priv(ndev);
2754         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2755         int i, ret;
2756
2757         if (!mdp->cd->tsu)
2758                 return 0;
2759
2760         i = sh_eth_tsu_find_entry(ndev, addr);
2761         if (i < 0) {
2762                 /* No entry found, create one */
2763                 i = sh_eth_tsu_find_empty(ndev);
2764                 if (i < 0)
2765                         return -ENOMEM;
2766                 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2767                 if (ret < 0)
2768                         return ret;
2769
2770                 /* Enable the entry */
2771                 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2772                                  (1 << (31 - i)), TSU_TEN);
2773         }
2774
2775         /* Entry found or created, enable POST */
2776         sh_eth_tsu_enable_cam_entry_post(ndev, i);
2777
2778         return 0;
2779 }
2780
2781 static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2782 {
2783         struct sh_eth_private *mdp = netdev_priv(ndev);
2784         int i, ret;
2785
2786         if (!mdp->cd->tsu)
2787                 return 0;
2788
2789         i = sh_eth_tsu_find_entry(ndev, addr);
2790         if (i) {
2791                 /* Entry found */
2792                 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2793                         goto done;
2794
2795                 /* Disable the entry if both ports was disabled */
2796                 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2797                 if (ret < 0)
2798                         return ret;
2799         }
2800 done:
2801         return 0;
2802 }
2803
2804 static int sh_eth_tsu_purge_all(struct net_device *ndev)
2805 {
2806         struct sh_eth_private *mdp = netdev_priv(ndev);
2807         int i, ret;
2808
2809         if (!mdp->cd->tsu)
2810                 return 0;
2811
2812         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2813                 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2814                         continue;
2815
2816                 /* Disable the entry if both ports was disabled */
2817                 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2818                 if (ret < 0)
2819                         return ret;
2820         }
2821
2822         return 0;
2823 }
2824
2825 static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2826 {
2827         struct sh_eth_private *mdp = netdev_priv(ndev);
2828         u8 addr[ETH_ALEN];
2829         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2830         int i;
2831
2832         if (!mdp->cd->tsu)
2833                 return;
2834
2835         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2836                 sh_eth_tsu_read_entry(reg_offset, addr);
2837                 if (is_multicast_ether_addr(addr))
2838                         sh_eth_tsu_del_entry(ndev, addr);
2839         }
2840 }
2841
2842 /* Update promiscuous flag and multicast filter */
2843 static void sh_eth_set_rx_mode(struct net_device *ndev)
2844 {
2845         struct sh_eth_private *mdp = netdev_priv(ndev);
2846         u32 ecmr_bits;
2847         int mcast_all = 0;
2848         unsigned long flags;
2849
2850         spin_lock_irqsave(&mdp->lock, flags);
2851         /* Initial condition is MCT = 1, PRM = 0.
2852          * Depending on ndev->flags, set PRM or clear MCT
2853          */
2854         ecmr_bits = sh_eth_read(ndev, ECMR) & ~ECMR_PRM;
2855         if (mdp->cd->tsu)
2856                 ecmr_bits |= ECMR_MCT;
2857
2858         if (!(ndev->flags & IFF_MULTICAST)) {
2859                 sh_eth_tsu_purge_mcast(ndev);
2860                 mcast_all = 1;
2861         }
2862         if (ndev->flags & IFF_ALLMULTI) {
2863                 sh_eth_tsu_purge_mcast(ndev);
2864                 ecmr_bits &= ~ECMR_MCT;
2865                 mcast_all = 1;
2866         }
2867
2868         if (ndev->flags & IFF_PROMISC) {
2869                 sh_eth_tsu_purge_all(ndev);
2870                 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2871         } else if (mdp->cd->tsu) {
2872                 struct netdev_hw_addr *ha;
2873                 netdev_for_each_mc_addr(ha, ndev) {
2874                         if (mcast_all && is_multicast_ether_addr(ha->addr))
2875                                 continue;
2876
2877                         if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2878                                 if (!mcast_all) {
2879                                         sh_eth_tsu_purge_mcast(ndev);
2880                                         ecmr_bits &= ~ECMR_MCT;
2881                                         mcast_all = 1;
2882                                 }
2883                         }
2884                 }
2885         }
2886
2887         /* update the ethernet mode */
2888         sh_eth_write(ndev, ecmr_bits, ECMR);
2889
2890         spin_unlock_irqrestore(&mdp->lock, flags);
2891 }
2892
2893 static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2894 {
2895         if (!mdp->port)
2896                 return TSU_VTAG0;
2897         else
2898                 return TSU_VTAG1;
2899 }
2900
2901 static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2902                                   __be16 proto, u16 vid)
2903 {
2904         struct sh_eth_private *mdp = netdev_priv(ndev);
2905         int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2906
2907         if (unlikely(!mdp->cd->tsu))
2908                 return -EPERM;
2909
2910         /* No filtering if vid = 0 */
2911         if (!vid)
2912                 return 0;
2913
2914         mdp->vlan_num_ids++;
2915
2916         /* The controller has one VLAN tag HW filter. So, if the filter is
2917          * already enabled, the driver disables it and the filte
2918          */
2919         if (mdp->vlan_num_ids > 1) {
2920                 /* disable VLAN filter */
2921                 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2922                 return 0;
2923         }
2924
2925         sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2926                          vtag_reg_index);
2927
2928         return 0;
2929 }
2930
2931 static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2932                                    __be16 proto, u16 vid)
2933 {
2934         struct sh_eth_private *mdp = netdev_priv(ndev);
2935         int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2936
2937         if (unlikely(!mdp->cd->tsu))
2938                 return -EPERM;
2939
2940         /* No filtering if vid = 0 */
2941         if (!vid)
2942                 return 0;
2943
2944         mdp->vlan_num_ids--;
2945         sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2946
2947         return 0;
2948 }
2949
2950 /* SuperH's TSU register init function */
2951 static void sh_eth_tsu_init(struct sh_eth_private *mdp)
2952 {
2953         if (!mdp->cd->dual_port) {
2954                 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2955                 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL,
2956                                  TSU_FWSLC);    /* Enable POST registers */
2957                 return;
2958         }
2959
2960         sh_eth_tsu_write(mdp, 0, TSU_FWEN0);    /* Disable forward(0->1) */
2961         sh_eth_tsu_write(mdp, 0, TSU_FWEN1);    /* Disable forward(1->0) */
2962         sh_eth_tsu_write(mdp, 0, TSU_FCM);      /* forward fifo 3k-3k */
2963         sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2964         sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2965         sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
2966         sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
2967         sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
2968         sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
2969         sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
2970         sh_eth_tsu_write(mdp, 0, TSU_QTAGM0);   /* Disable QTAG(0->1) */
2971         sh_eth_tsu_write(mdp, 0, TSU_QTAGM1);   /* Disable QTAG(1->0) */
2972         sh_eth_tsu_write(mdp, 0, TSU_FWSR);     /* all interrupt status clear */
2973         sh_eth_tsu_write(mdp, 0, TSU_FWINMK);   /* Disable all interrupt */
2974         sh_eth_tsu_write(mdp, 0, TSU_TEN);      /* Disable all CAM entry */
2975         sh_eth_tsu_write(mdp, 0, TSU_POST1);    /* Disable CAM entry [ 0- 7] */
2976         sh_eth_tsu_write(mdp, 0, TSU_POST2);    /* Disable CAM entry [ 8-15] */
2977         sh_eth_tsu_write(mdp, 0, TSU_POST3);    /* Disable CAM entry [16-23] */
2978         sh_eth_tsu_write(mdp, 0, TSU_POST4);    /* Disable CAM entry [24-31] */
2979 }
2980
2981 /* MDIO bus release function */
2982 static int sh_mdio_release(struct sh_eth_private *mdp)
2983 {
2984         /* unregister mdio bus */
2985         mdiobus_unregister(mdp->mii_bus);
2986
2987         /* free bitbang info */
2988         free_mdio_bitbang(mdp->mii_bus);
2989
2990         return 0;
2991 }
2992
2993 /* MDIO bus init function */
2994 static int sh_mdio_init(struct sh_eth_private *mdp,
2995                         struct sh_eth_plat_data *pd)
2996 {
2997         int ret;
2998         struct bb_info *bitbang;
2999         struct platform_device *pdev = mdp->pdev;
3000         struct device *dev = &mdp->pdev->dev;
3001
3002         /* create bit control struct for PHY */
3003         bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL);
3004         if (!bitbang)
3005                 return -ENOMEM;
3006
3007         /* bitbang init */
3008         bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
3009         bitbang->set_gate = pd->set_mdio_gate;
3010         bitbang->ctrl.ops = &bb_ops;
3011
3012         /* MII controller setting */
3013         mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
3014         if (!mdp->mii_bus)
3015                 return -ENOMEM;
3016
3017         /* Hook up MII support for ethtool */
3018         mdp->mii_bus->name = "sh_mii";
3019         mdp->mii_bus->parent = dev;
3020         snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
3021                  pdev->name, pdev->id);
3022
3023         /* register MDIO bus */
3024         if (pd->phy_irq > 0)
3025                 mdp->mii_bus->irq[pd->phy] = pd->phy_irq;
3026
3027         ret = of_mdiobus_register(mdp->mii_bus, dev->of_node);
3028         if (ret)
3029                 goto out_free_bus;
3030
3031         return 0;
3032
3033 out_free_bus:
3034         free_mdio_bitbang(mdp->mii_bus);
3035         return ret;
3036 }
3037
3038 static const u16 *sh_eth_get_register_offset(int register_type)
3039 {
3040         const u16 *reg_offset = NULL;
3041
3042         switch (register_type) {
3043         case SH_ETH_REG_GIGABIT:
3044                 reg_offset = sh_eth_offset_gigabit;
3045                 break;
3046         case SH_ETH_REG_FAST_RZ:
3047                 reg_offset = sh_eth_offset_fast_rz;
3048                 break;
3049         case SH_ETH_REG_FAST_RCAR:
3050                 reg_offset = sh_eth_offset_fast_rcar;
3051                 break;
3052         case SH_ETH_REG_FAST_SH4:
3053                 reg_offset = sh_eth_offset_fast_sh4;
3054                 break;
3055         case SH_ETH_REG_FAST_SH3_SH2:
3056                 reg_offset = sh_eth_offset_fast_sh3_sh2;
3057                 break;
3058         }
3059
3060         return reg_offset;
3061 }
3062
3063 static const struct net_device_ops sh_eth_netdev_ops = {
3064         .ndo_open               = sh_eth_open,
3065         .ndo_stop               = sh_eth_close,
3066         .ndo_start_xmit         = sh_eth_start_xmit,
3067         .ndo_get_stats          = sh_eth_get_stats,
3068         .ndo_set_rx_mode        = sh_eth_set_rx_mode,
3069         .ndo_tx_timeout         = sh_eth_tx_timeout,
3070         .ndo_do_ioctl           = sh_eth_do_ioctl,
3071         .ndo_change_mtu         = sh_eth_change_mtu,
3072         .ndo_validate_addr      = eth_validate_addr,
3073         .ndo_set_mac_address    = eth_mac_addr,
3074 };
3075
3076 static const struct net_device_ops sh_eth_netdev_ops_tsu = {
3077         .ndo_open               = sh_eth_open,
3078         .ndo_stop               = sh_eth_close,
3079         .ndo_start_xmit         = sh_eth_start_xmit,
3080         .ndo_get_stats          = sh_eth_get_stats,
3081         .ndo_set_rx_mode        = sh_eth_set_rx_mode,
3082         .ndo_vlan_rx_add_vid    = sh_eth_vlan_rx_add_vid,
3083         .ndo_vlan_rx_kill_vid   = sh_eth_vlan_rx_kill_vid,
3084         .ndo_tx_timeout         = sh_eth_tx_timeout,
3085         .ndo_do_ioctl           = sh_eth_do_ioctl,
3086         .ndo_change_mtu         = sh_eth_change_mtu,
3087         .ndo_validate_addr      = eth_validate_addr,
3088         .ndo_set_mac_address    = eth_mac_addr,
3089 };
3090
3091 #ifdef CONFIG_OF
3092 static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
3093 {
3094         struct device_node *np = dev->of_node;
3095         struct sh_eth_plat_data *pdata;
3096         const char *mac_addr;
3097
3098         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
3099         if (!pdata)
3100                 return NULL;
3101
3102         pdata->phy_interface = of_get_phy_mode(np);
3103
3104         mac_addr = of_get_mac_address(np);
3105         if (mac_addr)
3106                 memcpy(pdata->mac_addr, mac_addr, ETH_ALEN);
3107
3108         pdata->no_ether_link =
3109                 of_property_read_bool(np, "renesas,no-ether-link");
3110         pdata->ether_link_active_low =
3111                 of_property_read_bool(np, "renesas,ether-link-active-low");
3112
3113         return pdata;
3114 }
3115
3116 static const struct of_device_id sh_eth_match_table[] = {
3117         { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data },
3118         { .compatible = "renesas,ether-r8a7743", .data = &rcar_gen2_data },
3119         { .compatible = "renesas,ether-r8a7745", .data = &rcar_gen2_data },
3120         { .compatible = "renesas,ether-r8a7778", .data = &rcar_gen1_data },
3121         { .compatible = "renesas,ether-r8a7779", .data = &rcar_gen1_data },
3122         { .compatible = "renesas,ether-r8a7790", .data = &rcar_gen2_data },
3123         { .compatible = "renesas,ether-r8a7791", .data = &rcar_gen2_data },
3124         { .compatible = "renesas,ether-r8a7793", .data = &rcar_gen2_data },
3125         { .compatible = "renesas,ether-r8a7794", .data = &rcar_gen2_data },
3126         { .compatible = "renesas,gether-r8a77980", .data = &r8a77980_data },
3127         { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data },
3128         { .compatible = "renesas,rcar-gen1-ether", .data = &rcar_gen1_data },
3129         { .compatible = "renesas,rcar-gen2-ether", .data = &rcar_gen2_data },
3130         { }
3131 };
3132 MODULE_DEVICE_TABLE(of, sh_eth_match_table);
3133 #else
3134 static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
3135 {
3136         return NULL;
3137 }
3138 #endif
3139
3140 static int sh_eth_drv_probe(struct platform_device *pdev)
3141 {
3142         struct resource *res;
3143         struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev);
3144         const struct platform_device_id *id = platform_get_device_id(pdev);
3145         struct sh_eth_private *mdp;
3146         struct net_device *ndev;
3147         int ret;
3148
3149         /* get base addr */
3150         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3151
3152         ndev = alloc_etherdev(sizeof(struct sh_eth_private));
3153         if (!ndev)
3154                 return -ENOMEM;
3155
3156         pm_runtime_enable(&pdev->dev);
3157         pm_runtime_get_sync(&pdev->dev);
3158
3159         ret = platform_get_irq(pdev, 0);
3160         if (ret < 0)
3161                 goto out_release;
3162         ndev->irq = ret;
3163
3164         SET_NETDEV_DEV(ndev, &pdev->dev);
3165
3166         mdp = netdev_priv(ndev);
3167         mdp->num_tx_ring = TX_RING_SIZE;
3168         mdp->num_rx_ring = RX_RING_SIZE;
3169         mdp->addr = devm_ioremap_resource(&pdev->dev, res);
3170         if (IS_ERR(mdp->addr)) {
3171                 ret = PTR_ERR(mdp->addr);
3172                 goto out_release;
3173         }
3174
3175         ndev->base_addr = res->start;
3176
3177         spin_lock_init(&mdp->lock);
3178         mdp->pdev = pdev;
3179
3180         if (pdev->dev.of_node)
3181                 pd = sh_eth_parse_dt(&pdev->dev);
3182         if (!pd) {
3183                 dev_err(&pdev->dev, "no platform data\n");
3184                 ret = -EINVAL;
3185                 goto out_release;
3186         }
3187
3188         /* get PHY ID */
3189         mdp->phy_id = pd->phy;
3190         mdp->phy_interface = pd->phy_interface;
3191         mdp->no_ether_link = pd->no_ether_link;
3192         mdp->ether_link_active_low = pd->ether_link_active_low;
3193
3194         /* set cpu data */
3195         if (id)
3196                 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
3197         else
3198                 mdp->cd = (struct sh_eth_cpu_data *)of_device_get_match_data(&pdev->dev);
3199
3200         mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type);
3201         if (!mdp->reg_offset) {
3202                 dev_err(&pdev->dev, "Unknown register type (%d)\n",
3203                         mdp->cd->register_type);
3204                 ret = -EINVAL;
3205                 goto out_release;
3206         }
3207         sh_eth_set_default_cpu_data(mdp->cd);
3208
3209         /* User's manual states max MTU should be 2048 but due to the
3210          * alignment calculations in sh_eth_ring_init() the practical
3211          * MTU is a bit less. Maybe this can be optimized some more.
3212          */
3213         ndev->max_mtu = 2000 - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN);
3214         ndev->min_mtu = ETH_MIN_MTU;
3215
3216         /* set function */
3217         if (mdp->cd->tsu)
3218                 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
3219         else
3220                 ndev->netdev_ops = &sh_eth_netdev_ops;
3221         ndev->ethtool_ops = &sh_eth_ethtool_ops;
3222         ndev->watchdog_timeo = TX_TIMEOUT;
3223
3224         /* debug message level */
3225         mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
3226
3227         /* read and set MAC address */
3228         read_mac_address(ndev, pd->mac_addr);
3229         if (!is_valid_ether_addr(ndev->dev_addr)) {
3230                 dev_warn(&pdev->dev,
3231                          "no valid MAC address supplied, using a random one.\n");
3232                 eth_hw_addr_random(ndev);
3233         }
3234
3235         if (mdp->cd->tsu) {
3236                 int port = pdev->id < 0 ? 0 : pdev->id % 2;
3237                 struct resource *rtsu;
3238
3239                 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
3240                 if (!rtsu) {
3241                         dev_err(&pdev->dev, "no TSU resource\n");
3242                         ret = -ENODEV;
3243                         goto out_release;
3244                 }
3245                 /* We can only request the  TSU region  for the first port
3246                  * of the two  sharing this TSU for the probe to succeed...
3247                  */
3248                 if (port == 0 &&
3249                     !devm_request_mem_region(&pdev->dev, rtsu->start,
3250                                              resource_size(rtsu),
3251                                              dev_name(&pdev->dev))) {
3252                         dev_err(&pdev->dev, "can't request TSU resource.\n");
3253                         ret = -EBUSY;
3254                         goto out_release;
3255                 }
3256                 /* ioremap the TSU registers */
3257                 mdp->tsu_addr = devm_ioremap(&pdev->dev, rtsu->start,
3258                                              resource_size(rtsu));
3259                 if (!mdp->tsu_addr) {
3260                         dev_err(&pdev->dev, "TSU region ioremap() failed.\n");
3261                         ret = -ENOMEM;
3262                         goto out_release;
3263                 }
3264                 mdp->port = port;
3265                 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
3266
3267                 /* Need to init only the first port of the two sharing a TSU */
3268                 if (port == 0) {
3269                         if (mdp->cd->chip_reset)
3270                                 mdp->cd->chip_reset(ndev);
3271
3272                         /* TSU init (Init only)*/
3273                         sh_eth_tsu_init(mdp);
3274                 }
3275         }
3276
3277         if (mdp->cd->rmiimode)
3278                 sh_eth_write(ndev, 0x1, RMIIMODE);
3279
3280         /* MDIO bus init */
3281         ret = sh_mdio_init(mdp, pd);
3282         if (ret) {
3283                 if (ret != -EPROBE_DEFER)
3284                         dev_err(&pdev->dev, "MDIO init failed: %d\n", ret);
3285                 goto out_release;
3286         }
3287
3288         netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
3289
3290         /* network device register */
3291         ret = register_netdev(ndev);
3292         if (ret)
3293                 goto out_napi_del;
3294
3295         if (mdp->cd->magic)
3296                 device_set_wakeup_capable(&pdev->dev, 1);
3297
3298         /* print device information */
3299         netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n",
3300                     (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
3301
3302         pm_runtime_put(&pdev->dev);
3303         platform_set_drvdata(pdev, ndev);
3304
3305         return ret;
3306
3307 out_napi_del:
3308         netif_napi_del(&mdp->napi);
3309         sh_mdio_release(mdp);
3310
3311 out_release:
3312         /* net_dev free */
3313         free_netdev(ndev);
3314
3315         pm_runtime_put(&pdev->dev);
3316         pm_runtime_disable(&pdev->dev);
3317         return ret;
3318 }
3319
3320 static int sh_eth_drv_remove(struct platform_device *pdev)
3321 {
3322         struct net_device *ndev = platform_get_drvdata(pdev);
3323         struct sh_eth_private *mdp = netdev_priv(ndev);
3324
3325         unregister_netdev(ndev);
3326         netif_napi_del(&mdp->napi);
3327         sh_mdio_release(mdp);
3328         pm_runtime_disable(&pdev->dev);
3329         free_netdev(ndev);
3330
3331         return 0;
3332 }
3333
3334 #ifdef CONFIG_PM
3335 #ifdef CONFIG_PM_SLEEP
3336 static int sh_eth_wol_setup(struct net_device *ndev)
3337 {
3338         struct sh_eth_private *mdp = netdev_priv(ndev);
3339
3340         /* Only allow ECI interrupts */
3341         synchronize_irq(ndev->irq);
3342         napi_disable(&mdp->napi);
3343         sh_eth_write(ndev, EESIPR_ECIIP, EESIPR);
3344
3345         /* Enable MagicPacket */
3346         sh_eth_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE);
3347
3348         return enable_irq_wake(ndev->irq);
3349 }
3350
3351 static int sh_eth_wol_restore(struct net_device *ndev)
3352 {
3353         struct sh_eth_private *mdp = netdev_priv(ndev);
3354         int ret;
3355
3356         napi_enable(&mdp->napi);
3357
3358         /* Disable MagicPacket */
3359         sh_eth_modify(ndev, ECMR, ECMR_MPDE, 0);
3360
3361         /* The device needs to be reset to restore MagicPacket logic
3362          * for next wakeup. If we close and open the device it will
3363          * both be reset and all registers restored. This is what
3364          * happens during suspend and resume without WoL enabled.
3365          */
3366         ret = sh_eth_close(ndev);
3367         if (ret < 0)
3368                 return ret;
3369         ret = sh_eth_open(ndev);
3370         if (ret < 0)
3371                 return ret;
3372
3373         return disable_irq_wake(ndev->irq);
3374 }
3375
3376 static int sh_eth_suspend(struct device *dev)
3377 {
3378         struct net_device *ndev = dev_get_drvdata(dev);
3379         struct sh_eth_private *mdp = netdev_priv(ndev);
3380         int ret = 0;
3381
3382         if (!netif_running(ndev))
3383                 return 0;
3384
3385         netif_device_detach(ndev);
3386
3387         if (mdp->wol_enabled)
3388                 ret = sh_eth_wol_setup(ndev);
3389         else
3390                 ret = sh_eth_close(ndev);
3391
3392         return ret;
3393 }
3394
3395 static int sh_eth_resume(struct device *dev)
3396 {
3397         struct net_device *ndev = dev_get_drvdata(dev);
3398         struct sh_eth_private *mdp = netdev_priv(ndev);
3399         int ret = 0;
3400
3401         if (!netif_running(ndev))
3402                 return 0;
3403
3404         if (mdp->wol_enabled)
3405                 ret = sh_eth_wol_restore(ndev);
3406         else
3407                 ret = sh_eth_open(ndev);
3408
3409         if (ret < 0)
3410                 return ret;
3411
3412         netif_device_attach(ndev);
3413
3414         return ret;
3415 }
3416 #endif
3417
3418 static int sh_eth_runtime_nop(struct device *dev)
3419 {
3420         /* Runtime PM callback shared between ->runtime_suspend()
3421          * and ->runtime_resume(). Simply returns success.
3422          *
3423          * This driver re-initializes all registers after
3424          * pm_runtime_get_sync() anyway so there is no need
3425          * to save and restore registers here.
3426          */
3427         return 0;
3428 }
3429
3430 static const struct dev_pm_ops sh_eth_dev_pm_ops = {
3431         SET_SYSTEM_SLEEP_PM_OPS(sh_eth_suspend, sh_eth_resume)
3432         SET_RUNTIME_PM_OPS(sh_eth_runtime_nop, sh_eth_runtime_nop, NULL)
3433 };
3434 #define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
3435 #else
3436 #define SH_ETH_PM_OPS NULL
3437 #endif
3438
3439 static const struct platform_device_id sh_eth_id_table[] = {
3440         { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
3441         { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
3442         { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
3443         { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
3444         { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
3445         { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
3446         { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
3447         { }
3448 };
3449 MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
3450
3451 static struct platform_driver sh_eth_driver = {
3452         .probe = sh_eth_drv_probe,
3453         .remove = sh_eth_drv_remove,
3454         .id_table = sh_eth_id_table,
3455         .driver = {
3456                    .name = CARDNAME,
3457                    .pm = SH_ETH_PM_OPS,
3458                    .of_match_table = of_match_ptr(sh_eth_match_table),
3459         },
3460 };
3461
3462 module_platform_driver(sh_eth_driver);
3463
3464 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
3465 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
3466 MODULE_LICENSE("GPL v2");