1 /* SuperH Ethernet device driver
3 * Copyright (C) 2014 Renesas Electronics Corporation
4 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu
5 * Copyright (C) 2008-2014 Renesas Solutions Corp.
6 * Copyright (C) 2013-2017 Cogent Embedded, Inc.
7 * Copyright (C) 2014 Codethink Limited
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License,
11 * version 2, as published by the Free Software Foundation.
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/spinlock.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/etherdevice.h>
28 #include <linux/delay.h>
29 #include <linux/platform_device.h>
30 #include <linux/mdio-bitbang.h>
31 #include <linux/netdevice.h>
33 #include <linux/of_device.h>
34 #include <linux/of_irq.h>
35 #include <linux/of_net.h>
36 #include <linux/phy.h>
37 #include <linux/cache.h>
39 #include <linux/pm_runtime.h>
40 #include <linux/slab.h>
41 #include <linux/ethtool.h>
42 #include <linux/if_vlan.h>
43 #include <linux/sh_eth.h>
44 #include <linux/of_mdio.h>
48 #define SH_ETH_DEF_MSG_ENABLE \
54 #define SH_ETH_OFFSET_INVALID ((u16)~0)
56 #define SH_ETH_OFFSET_DEFAULTS \
57 [0 ... SH_ETH_MAX_REGISTER_OFFSET - 1] = SH_ETH_OFFSET_INVALID
59 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
60 SH_ETH_OFFSET_DEFAULTS,
115 [TSU_CTRST] = 0x0004,
116 [TSU_FWEN0] = 0x0010,
117 [TSU_FWEN1] = 0x0014,
119 [TSU_BSYSL0] = 0x0020,
120 [TSU_BSYSL1] = 0x0024,
121 [TSU_PRISL0] = 0x0028,
122 [TSU_PRISL1] = 0x002c,
123 [TSU_FWSL0] = 0x0030,
124 [TSU_FWSL1] = 0x0034,
125 [TSU_FWSLC] = 0x0038,
126 [TSU_QTAGM0] = 0x0040,
127 [TSU_QTAGM1] = 0x0044,
129 [TSU_FWINMK] = 0x0054,
130 [TSU_ADQT0] = 0x0048,
131 [TSU_ADQT1] = 0x004c,
132 [TSU_VTAG0] = 0x0058,
133 [TSU_VTAG1] = 0x005c,
134 [TSU_ADSBSY] = 0x0060,
136 [TSU_POST1] = 0x0070,
137 [TSU_POST2] = 0x0074,
138 [TSU_POST3] = 0x0078,
139 [TSU_POST4] = 0x007c,
140 [TSU_ADRH0] = 0x0100,
156 static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
157 SH_ETH_OFFSET_DEFAULTS,
202 [TSU_CTRST] = 0x0004,
203 [TSU_FWSLC] = 0x0038,
204 [TSU_VTAG0] = 0x0058,
205 [TSU_ADSBSY] = 0x0060,
207 [TSU_POST1] = 0x0070,
208 [TSU_POST2] = 0x0074,
209 [TSU_POST3] = 0x0078,
210 [TSU_POST4] = 0x007c,
211 [TSU_ADRH0] = 0x0100,
219 static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
220 SH_ETH_OFFSET_DEFAULTS,
267 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
268 SH_ETH_OFFSET_DEFAULTS,
321 static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
322 SH_ETH_OFFSET_DEFAULTS,
370 [TSU_CTRST] = 0x0004,
371 [TSU_FWEN0] = 0x0010,
372 [TSU_FWEN1] = 0x0014,
374 [TSU_BSYSL0] = 0x0020,
375 [TSU_BSYSL1] = 0x0024,
376 [TSU_PRISL0] = 0x0028,
377 [TSU_PRISL1] = 0x002c,
378 [TSU_FWSL0] = 0x0030,
379 [TSU_FWSL1] = 0x0034,
380 [TSU_FWSLC] = 0x0038,
381 [TSU_QTAGM0] = 0x0040,
382 [TSU_QTAGM1] = 0x0044,
383 [TSU_ADQT0] = 0x0048,
384 [TSU_ADQT1] = 0x004c,
386 [TSU_FWINMK] = 0x0054,
387 [TSU_ADSBSY] = 0x0060,
389 [TSU_POST1] = 0x0070,
390 [TSU_POST2] = 0x0074,
391 [TSU_POST3] = 0x0078,
392 [TSU_POST4] = 0x007c,
407 [TSU_ADRH0] = 0x0100,
410 static void sh_eth_rcv_snd_disable(struct net_device *ndev);
411 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev);
413 static void sh_eth_write(struct net_device *ndev, u32 data, int enum_index)
415 struct sh_eth_private *mdp = netdev_priv(ndev);
416 u16 offset = mdp->reg_offset[enum_index];
418 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
421 iowrite32(data, mdp->addr + offset);
424 static u32 sh_eth_read(struct net_device *ndev, int enum_index)
426 struct sh_eth_private *mdp = netdev_priv(ndev);
427 u16 offset = mdp->reg_offset[enum_index];
429 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
432 return ioread32(mdp->addr + offset);
435 static void sh_eth_modify(struct net_device *ndev, int enum_index, u32 clear,
438 sh_eth_write(ndev, (sh_eth_read(ndev, enum_index) & ~clear) | set,
442 static void sh_eth_tsu_write(struct sh_eth_private *mdp, u32 data,
445 u16 offset = mdp->reg_offset[enum_index];
447 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
450 iowrite32(data, mdp->tsu_addr + offset);
453 static u32 sh_eth_tsu_read(struct sh_eth_private *mdp, int enum_index)
455 u16 offset = mdp->reg_offset[enum_index];
457 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
460 return ioread32(mdp->tsu_addr + offset);
463 static void sh_eth_soft_swap(char *src, int len)
465 #ifdef __LITTLE_ENDIAN
467 u32 *maxp = p + DIV_ROUND_UP(len, sizeof(u32));
469 for (; p < maxp; p++)
474 static void sh_eth_select_mii(struct net_device *ndev)
476 struct sh_eth_private *mdp = netdev_priv(ndev);
479 switch (mdp->phy_interface) {
480 case PHY_INTERFACE_MODE_RGMII ... PHY_INTERFACE_MODE_RGMII_TXID:
483 case PHY_INTERFACE_MODE_GMII:
486 case PHY_INTERFACE_MODE_MII:
489 case PHY_INTERFACE_MODE_RMII:
494 "PHY interface mode was not setup. Set to MII.\n");
499 sh_eth_write(ndev, value, RMII_MII);
502 static void sh_eth_set_duplex(struct net_device *ndev)
504 struct sh_eth_private *mdp = netdev_priv(ndev);
506 sh_eth_modify(ndev, ECMR, ECMR_DM, mdp->duplex ? ECMR_DM : 0);
509 static void sh_eth_chip_reset(struct net_device *ndev)
511 struct sh_eth_private *mdp = netdev_priv(ndev);
514 sh_eth_tsu_write(mdp, ARSTR_ARST, ARSTR);
518 static int sh_eth_soft_reset(struct net_device *ndev)
520 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, EDMR_SRST_ETHER);
522 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, 0);
527 static int sh_eth_check_soft_reset(struct net_device *ndev)
531 for (cnt = 100; cnt > 0; cnt--) {
532 if (!(sh_eth_read(ndev, EDMR) & EDMR_SRST_GETHER))
537 netdev_err(ndev, "Device reset failed\n");
541 static int sh_eth_soft_reset_gether(struct net_device *ndev)
543 struct sh_eth_private *mdp = netdev_priv(ndev);
546 sh_eth_write(ndev, EDSR_ENALL, EDSR);
547 sh_eth_modify(ndev, EDMR, EDMR_SRST_GETHER, EDMR_SRST_GETHER);
549 ret = sh_eth_check_soft_reset(ndev);
554 sh_eth_write(ndev, 0, TDLAR);
555 sh_eth_write(ndev, 0, TDFAR);
556 sh_eth_write(ndev, 0, TDFXR);
557 sh_eth_write(ndev, 0, TDFFR);
558 sh_eth_write(ndev, 0, RDLAR);
559 sh_eth_write(ndev, 0, RDFAR);
560 sh_eth_write(ndev, 0, RDFXR);
561 sh_eth_write(ndev, 0, RDFFR);
563 /* Reset HW CRC register */
564 if (mdp->cd->hw_checksum)
565 sh_eth_write(ndev, 0, CSMR);
567 /* Select MII mode */
568 if (mdp->cd->select_mii)
569 sh_eth_select_mii(ndev);
574 static void sh_eth_set_rate_gether(struct net_device *ndev)
576 struct sh_eth_private *mdp = netdev_priv(ndev);
578 switch (mdp->speed) {
579 case 10: /* 10BASE */
580 sh_eth_write(ndev, GECMR_10, GECMR);
582 case 100:/* 100BASE */
583 sh_eth_write(ndev, GECMR_100, GECMR);
585 case 1000: /* 1000BASE */
586 sh_eth_write(ndev, GECMR_1000, GECMR);
593 static struct sh_eth_cpu_data r7s72100_data = {
594 .soft_reset = sh_eth_soft_reset_gether,
596 .chip_reset = sh_eth_chip_reset,
597 .set_duplex = sh_eth_set_duplex,
599 .register_type = SH_ETH_REG_FAST_RZ,
601 .edtrr_trns = EDTRR_TRNS_GETHER,
602 .ecsr_value = ECSR_ICD,
603 .ecsipr_value = ECSIPR_ICDIP,
604 .eesipr_value = EESIPR_TWB1IP | EESIPR_TWBIP | EESIPR_TC1IP |
605 EESIPR_TABTIP | EESIPR_RABTIP | EESIPR_RFCOFIP |
607 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
608 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
609 EESIPR_RMAFIP | EESIPR_RRFIP |
610 EESIPR_RTLFIP | EESIPR_RTSFIP |
611 EESIPR_PREIP | EESIPR_CERFIP,
613 .tx_check = EESR_TC1 | EESR_FTC,
614 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
615 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
617 .fdr_value = 0x0000070f,
625 .rpadir_value = 2 << 16,
634 static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
636 sh_eth_chip_reset(ndev);
638 sh_eth_select_mii(ndev);
642 static struct sh_eth_cpu_data r8a7740_data = {
643 .soft_reset = sh_eth_soft_reset_gether,
645 .chip_reset = sh_eth_chip_reset_r8a7740,
646 .set_duplex = sh_eth_set_duplex,
647 .set_rate = sh_eth_set_rate_gether,
649 .register_type = SH_ETH_REG_GIGABIT,
651 .edtrr_trns = EDTRR_TRNS_GETHER,
652 .ecsr_value = ECSR_ICD | ECSR_MPD,
653 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
654 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
655 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
656 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
657 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
658 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
659 EESIPR_CEEFIP | EESIPR_CELFIP |
660 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
661 EESIPR_PREIP | EESIPR_CERFIP,
663 .tx_check = EESR_TC1 | EESR_FTC,
664 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
665 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
667 .fdr_value = 0x0000070f,
675 .rpadir_value = 2 << 16,
686 /* There is CPU dependent code */
687 static void sh_eth_set_rate_rcar(struct net_device *ndev)
689 struct sh_eth_private *mdp = netdev_priv(ndev);
691 switch (mdp->speed) {
692 case 10: /* 10BASE */
693 sh_eth_modify(ndev, ECMR, ECMR_ELB, 0);
695 case 100:/* 100BASE */
696 sh_eth_modify(ndev, ECMR, ECMR_ELB, ECMR_ELB);
702 static struct sh_eth_cpu_data rcar_gen1_data = {
703 .soft_reset = sh_eth_soft_reset,
705 .set_duplex = sh_eth_set_duplex,
706 .set_rate = sh_eth_set_rate_rcar,
708 .register_type = SH_ETH_REG_FAST_RCAR,
710 .edtrr_trns = EDTRR_TRNS_ETHER,
711 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
712 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
713 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP |
714 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
715 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
716 EESIPR_RMAFIP | EESIPR_RRFIP |
717 EESIPR_RTLFIP | EESIPR_RTSFIP |
718 EESIPR_PREIP | EESIPR_CERFIP,
720 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO,
721 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
722 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
723 .fdr_value = 0x00000f0f,
732 /* R-Car Gen2 and RZ/G1 */
733 static struct sh_eth_cpu_data rcar_gen2_data = {
734 .soft_reset = sh_eth_soft_reset,
736 .set_duplex = sh_eth_set_duplex,
737 .set_rate = sh_eth_set_rate_rcar,
739 .register_type = SH_ETH_REG_FAST_RCAR,
741 .edtrr_trns = EDTRR_TRNS_ETHER,
742 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD | ECSR_MPD,
743 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP |
745 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP |
746 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
747 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
748 EESIPR_RMAFIP | EESIPR_RRFIP |
749 EESIPR_RTLFIP | EESIPR_RTSFIP |
750 EESIPR_PREIP | EESIPR_CERFIP,
752 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO,
753 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
754 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
755 .fdr_value = 0x00000f0f,
757 .trscer_err_mask = DESC_I_RINT8,
769 static struct sh_eth_cpu_data r8a77980_data = {
770 .soft_reset = sh_eth_soft_reset_gether,
772 .set_duplex = sh_eth_set_duplex,
773 .set_rate = sh_eth_set_rate_gether,
775 .register_type = SH_ETH_REG_GIGABIT,
777 .edtrr_trns = EDTRR_TRNS_GETHER,
778 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD | ECSR_MPD,
779 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP |
781 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
782 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
783 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
784 EESIPR_RMAFIP | EESIPR_RRFIP |
785 EESIPR_RTLFIP | EESIPR_RTSFIP |
786 EESIPR_PREIP | EESIPR_CERFIP,
788 .tx_check = EESR_FTC | EESR_CD | EESR_TRO,
789 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
790 EESR_RFE | EESR_RDE | EESR_RFRMER |
791 EESR_TFE | EESR_TDE | EESR_ECI,
792 .fdr_value = 0x0000070f,
801 .rpadir_value = 2 << 16,
810 #endif /* CONFIG_OF */
812 static void sh_eth_set_rate_sh7724(struct net_device *ndev)
814 struct sh_eth_private *mdp = netdev_priv(ndev);
816 switch (mdp->speed) {
817 case 10: /* 10BASE */
818 sh_eth_modify(ndev, ECMR, ECMR_RTM, 0);
820 case 100:/* 100BASE */
821 sh_eth_modify(ndev, ECMR, ECMR_RTM, ECMR_RTM);
827 static struct sh_eth_cpu_data sh7724_data = {
828 .soft_reset = sh_eth_soft_reset,
830 .set_duplex = sh_eth_set_duplex,
831 .set_rate = sh_eth_set_rate_sh7724,
833 .register_type = SH_ETH_REG_FAST_SH4,
835 .edtrr_trns = EDTRR_TRNS_ETHER,
836 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
837 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
838 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP |
839 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
840 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
841 EESIPR_RMAFIP | EESIPR_RRFIP |
842 EESIPR_RTLFIP | EESIPR_RTSFIP |
843 EESIPR_PREIP | EESIPR_CERFIP,
845 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO,
846 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
847 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
854 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
857 static void sh_eth_set_rate_sh7757(struct net_device *ndev)
859 struct sh_eth_private *mdp = netdev_priv(ndev);
861 switch (mdp->speed) {
862 case 10: /* 10BASE */
863 sh_eth_write(ndev, 0, RTRATE);
865 case 100:/* 100BASE */
866 sh_eth_write(ndev, 1, RTRATE);
872 static struct sh_eth_cpu_data sh7757_data = {
873 .soft_reset = sh_eth_soft_reset,
875 .set_duplex = sh_eth_set_duplex,
876 .set_rate = sh_eth_set_rate_sh7757,
878 .register_type = SH_ETH_REG_FAST_SH4,
880 .edtrr_trns = EDTRR_TRNS_ETHER,
881 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
882 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
883 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
884 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
885 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
886 EESIPR_CEEFIP | EESIPR_CELFIP |
887 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
888 EESIPR_PREIP | EESIPR_CERFIP,
890 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO,
891 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
892 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
894 .irq_flags = IRQF_SHARED,
901 .rpadir_value = 2 << 16,
906 #define SH_GIGA_ETH_BASE 0xfee00000UL
907 #define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
908 #define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
909 static void sh_eth_chip_reset_giga(struct net_device *ndev)
911 u32 mahr[2], malr[2];
914 /* save MAHR and MALR */
915 for (i = 0; i < 2; i++) {
916 malr[i] = ioread32((void *)GIGA_MALR(i));
917 mahr[i] = ioread32((void *)GIGA_MAHR(i));
920 sh_eth_chip_reset(ndev);
922 /* restore MAHR and MALR */
923 for (i = 0; i < 2; i++) {
924 iowrite32(malr[i], (void *)GIGA_MALR(i));
925 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
929 static void sh_eth_set_rate_giga(struct net_device *ndev)
931 struct sh_eth_private *mdp = netdev_priv(ndev);
933 switch (mdp->speed) {
934 case 10: /* 10BASE */
935 sh_eth_write(ndev, 0x00000000, GECMR);
937 case 100:/* 100BASE */
938 sh_eth_write(ndev, 0x00000010, GECMR);
940 case 1000: /* 1000BASE */
941 sh_eth_write(ndev, 0x00000020, GECMR);
946 /* SH7757(GETHERC) */
947 static struct sh_eth_cpu_data sh7757_data_giga = {
948 .soft_reset = sh_eth_soft_reset_gether,
950 .chip_reset = sh_eth_chip_reset_giga,
951 .set_duplex = sh_eth_set_duplex,
952 .set_rate = sh_eth_set_rate_giga,
954 .register_type = SH_ETH_REG_GIGABIT,
956 .edtrr_trns = EDTRR_TRNS_GETHER,
957 .ecsr_value = ECSR_ICD | ECSR_MPD,
958 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
959 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
960 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
961 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
962 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
963 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
964 EESIPR_CEEFIP | EESIPR_CELFIP |
965 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
966 EESIPR_PREIP | EESIPR_CERFIP,
968 .tx_check = EESR_TC1 | EESR_FTC,
969 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
970 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
972 .fdr_value = 0x0000072f,
974 .irq_flags = IRQF_SHARED,
981 .rpadir_value = 2 << 16,
991 static struct sh_eth_cpu_data sh7734_data = {
992 .soft_reset = sh_eth_soft_reset_gether,
994 .chip_reset = sh_eth_chip_reset,
995 .set_duplex = sh_eth_set_duplex,
996 .set_rate = sh_eth_set_rate_gether,
998 .register_type = SH_ETH_REG_GIGABIT,
1000 .edtrr_trns = EDTRR_TRNS_GETHER,
1001 .ecsr_value = ECSR_ICD | ECSR_MPD,
1002 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
1003 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
1004 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
1005 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
1006 EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP |
1007 EESIPR_RMAFIP | EESIPR_CEEFIP | EESIPR_CELFIP |
1008 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
1009 EESIPR_PREIP | EESIPR_CERFIP,
1011 .tx_check = EESR_TC1 | EESR_FTC,
1012 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
1013 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
1032 static struct sh_eth_cpu_data sh7763_data = {
1033 .soft_reset = sh_eth_soft_reset_gether,
1035 .chip_reset = sh_eth_chip_reset,
1036 .set_duplex = sh_eth_set_duplex,
1037 .set_rate = sh_eth_set_rate_gether,
1039 .register_type = SH_ETH_REG_GIGABIT,
1041 .edtrr_trns = EDTRR_TRNS_GETHER,
1042 .ecsr_value = ECSR_ICD | ECSR_MPD,
1043 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
1044 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
1045 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
1046 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
1047 EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP |
1048 EESIPR_RMAFIP | EESIPR_CEEFIP | EESIPR_CELFIP |
1049 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
1050 EESIPR_PREIP | EESIPR_CERFIP,
1052 .tx_check = EESR_TC1 | EESR_FTC,
1053 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
1054 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
1065 .irq_flags = IRQF_SHARED,
1071 static struct sh_eth_cpu_data sh7619_data = {
1072 .soft_reset = sh_eth_soft_reset,
1074 .register_type = SH_ETH_REG_FAST_SH3_SH2,
1076 .edtrr_trns = EDTRR_TRNS_ETHER,
1077 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
1078 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
1079 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
1080 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
1081 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
1082 EESIPR_CEEFIP | EESIPR_CELFIP |
1083 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
1084 EESIPR_PREIP | EESIPR_CERFIP,
1092 static struct sh_eth_cpu_data sh771x_data = {
1093 .soft_reset = sh_eth_soft_reset,
1095 .register_type = SH_ETH_REG_FAST_SH3_SH2,
1097 .edtrr_trns = EDTRR_TRNS_ETHER,
1098 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
1099 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
1100 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
1101 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
1102 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
1103 EESIPR_CEEFIP | EESIPR_CELFIP |
1104 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
1105 EESIPR_PREIP | EESIPR_CERFIP,
1110 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
1112 if (!cd->ecsr_value)
1113 cd->ecsr_value = DEFAULT_ECSR_INIT;
1115 if (!cd->ecsipr_value)
1116 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
1118 if (!cd->fcftr_value)
1119 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF |
1120 DEFAULT_FIFO_F_D_RFD;
1123 cd->fdr_value = DEFAULT_FDR_INIT;
1126 cd->tx_check = DEFAULT_TX_CHECK;
1128 if (!cd->eesr_err_check)
1129 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
1131 if (!cd->trscer_err_mask)
1132 cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK;
1135 static void sh_eth_set_receive_align(struct sk_buff *skb)
1137 uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1);
1140 skb_reserve(skb, SH_ETH_RX_ALIGN - reserve);
1143 /* Program the hardware MAC address from dev->dev_addr. */
1144 static void update_mac_address(struct net_device *ndev)
1147 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
1148 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
1150 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
1153 /* Get MAC address from SuperH MAC address register
1155 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
1156 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
1157 * When you want use this device, you must set MAC address in bootloader.
1160 static void read_mac_address(struct net_device *ndev, unsigned char *mac)
1162 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
1163 memcpy(ndev->dev_addr, mac, ETH_ALEN);
1165 u32 mahr = sh_eth_read(ndev, MAHR);
1166 u32 malr = sh_eth_read(ndev, MALR);
1168 ndev->dev_addr[0] = (mahr >> 24) & 0xFF;
1169 ndev->dev_addr[1] = (mahr >> 16) & 0xFF;
1170 ndev->dev_addr[2] = (mahr >> 8) & 0xFF;
1171 ndev->dev_addr[3] = (mahr >> 0) & 0xFF;
1172 ndev->dev_addr[4] = (malr >> 8) & 0xFF;
1173 ndev->dev_addr[5] = (malr >> 0) & 0xFF;
1178 void (*set_gate)(void *addr);
1179 struct mdiobb_ctrl ctrl;
1183 static void sh_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set)
1185 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1188 if (bitbang->set_gate)
1189 bitbang->set_gate(bitbang->addr);
1191 pir = ioread32(bitbang->addr);
1196 iowrite32(pir, bitbang->addr);
1199 /* Data I/O pin control */
1200 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1202 sh_mdio_ctrl(ctrl, PIR_MMD, bit);
1206 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
1208 sh_mdio_ctrl(ctrl, PIR_MDO, bit);
1212 static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
1214 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1216 if (bitbang->set_gate)
1217 bitbang->set_gate(bitbang->addr);
1219 return (ioread32(bitbang->addr) & PIR_MDI) != 0;
1222 /* MDC pin control */
1223 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1225 sh_mdio_ctrl(ctrl, PIR_MDC, bit);
1228 /* mdio bus control struct */
1229 static struct mdiobb_ops bb_ops = {
1230 .owner = THIS_MODULE,
1231 .set_mdc = sh_mdc_ctrl,
1232 .set_mdio_dir = sh_mmd_ctrl,
1233 .set_mdio_data = sh_set_mdio,
1234 .get_mdio_data = sh_get_mdio,
1237 /* free Tx skb function */
1238 static int sh_eth_tx_free(struct net_device *ndev, bool sent_only)
1240 struct sh_eth_private *mdp = netdev_priv(ndev);
1241 struct sh_eth_txdesc *txdesc;
1246 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
1247 entry = mdp->dirty_tx % mdp->num_tx_ring;
1248 txdesc = &mdp->tx_ring[entry];
1249 sent = !(txdesc->status & cpu_to_le32(TD_TACT));
1250 if (sent_only && !sent)
1252 /* TACT bit must be checked before all the following reads */
1254 netif_info(mdp, tx_done, ndev,
1255 "tx entry %d status 0x%08x\n",
1256 entry, le32_to_cpu(txdesc->status));
1257 /* Free the original skb. */
1258 if (mdp->tx_skbuff[entry]) {
1259 dma_unmap_single(&mdp->pdev->dev,
1260 le32_to_cpu(txdesc->addr),
1261 le32_to_cpu(txdesc->len) >> 16,
1263 dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1264 mdp->tx_skbuff[entry] = NULL;
1267 txdesc->status = cpu_to_le32(TD_TFP);
1268 if (entry >= mdp->num_tx_ring - 1)
1269 txdesc->status |= cpu_to_le32(TD_TDLE);
1272 ndev->stats.tx_packets++;
1273 ndev->stats.tx_bytes += le32_to_cpu(txdesc->len) >> 16;
1279 /* free skb and descriptor buffer */
1280 static void sh_eth_ring_free(struct net_device *ndev)
1282 struct sh_eth_private *mdp = netdev_priv(ndev);
1286 for (i = 0; i < mdp->num_rx_ring; i++) {
1287 if (mdp->rx_skbuff[i]) {
1288 struct sh_eth_rxdesc *rxdesc = &mdp->rx_ring[i];
1290 dma_unmap_single(&mdp->pdev->dev,
1291 le32_to_cpu(rxdesc->addr),
1292 ALIGN(mdp->rx_buf_sz, 32),
1296 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1297 dma_free_coherent(&mdp->pdev->dev, ringsize, mdp->rx_ring,
1299 mdp->rx_ring = NULL;
1302 /* Free Rx skb ringbuffer */
1303 if (mdp->rx_skbuff) {
1304 for (i = 0; i < mdp->num_rx_ring; i++)
1305 dev_kfree_skb(mdp->rx_skbuff[i]);
1307 kfree(mdp->rx_skbuff);
1308 mdp->rx_skbuff = NULL;
1311 sh_eth_tx_free(ndev, false);
1313 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1314 dma_free_coherent(&mdp->pdev->dev, ringsize, mdp->tx_ring,
1316 mdp->tx_ring = NULL;
1319 /* Free Tx skb ringbuffer */
1320 kfree(mdp->tx_skbuff);
1321 mdp->tx_skbuff = NULL;
1324 /* format skb and descriptor buffer */
1325 static void sh_eth_ring_format(struct net_device *ndev)
1327 struct sh_eth_private *mdp = netdev_priv(ndev);
1329 struct sk_buff *skb;
1330 struct sh_eth_rxdesc *rxdesc = NULL;
1331 struct sh_eth_txdesc *txdesc = NULL;
1332 int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
1333 int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
1334 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
1335 dma_addr_t dma_addr;
1343 memset(mdp->rx_ring, 0, rx_ringsize);
1345 /* build Rx ring buffer */
1346 for (i = 0; i < mdp->num_rx_ring; i++) {
1348 mdp->rx_skbuff[i] = NULL;
1349 skb = netdev_alloc_skb(ndev, skbuff_size);
1352 sh_eth_set_receive_align(skb);
1354 /* The size of the buffer is a multiple of 32 bytes. */
1355 buf_len = ALIGN(mdp->rx_buf_sz, 32);
1356 dma_addr = dma_map_single(&mdp->pdev->dev, skb->data, buf_len,
1358 if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) {
1362 mdp->rx_skbuff[i] = skb;
1365 rxdesc = &mdp->rx_ring[i];
1366 rxdesc->len = cpu_to_le32(buf_len << 16);
1367 rxdesc->addr = cpu_to_le32(dma_addr);
1368 rxdesc->status = cpu_to_le32(RD_RACT | RD_RFP);
1370 /* Rx descriptor address set */
1372 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
1373 if (mdp->cd->xdfar_rw)
1374 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
1378 mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
1380 /* Mark the last entry as wrapping the ring. */
1382 rxdesc->status |= cpu_to_le32(RD_RDLE);
1384 memset(mdp->tx_ring, 0, tx_ringsize);
1386 /* build Tx ring buffer */
1387 for (i = 0; i < mdp->num_tx_ring; i++) {
1388 mdp->tx_skbuff[i] = NULL;
1389 txdesc = &mdp->tx_ring[i];
1390 txdesc->status = cpu_to_le32(TD_TFP);
1391 txdesc->len = cpu_to_le32(0);
1393 /* Tx descriptor address set */
1394 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
1395 if (mdp->cd->xdfar_rw)
1396 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
1400 txdesc->status |= cpu_to_le32(TD_TDLE);
1403 /* Get skb and descriptor buffer */
1404 static int sh_eth_ring_init(struct net_device *ndev)
1406 struct sh_eth_private *mdp = netdev_priv(ndev);
1407 int rx_ringsize, tx_ringsize;
1409 /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
1410 * card needs room to do 8 byte alignment, +2 so we can reserve
1411 * the first 2 bytes, and +16 gets room for the status word from the
1414 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1415 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
1416 if (mdp->cd->rpadir)
1417 mdp->rx_buf_sz += NET_IP_ALIGN;
1419 /* Allocate RX and TX skb rings */
1420 mdp->rx_skbuff = kcalloc(mdp->num_rx_ring, sizeof(*mdp->rx_skbuff),
1422 if (!mdp->rx_skbuff)
1425 mdp->tx_skbuff = kcalloc(mdp->num_tx_ring, sizeof(*mdp->tx_skbuff),
1427 if (!mdp->tx_skbuff)
1430 /* Allocate all Rx descriptors. */
1431 rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1432 mdp->rx_ring = dma_alloc_coherent(&mdp->pdev->dev, rx_ringsize,
1433 &mdp->rx_desc_dma, GFP_KERNEL);
1439 /* Allocate all Tx descriptors. */
1440 tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1441 mdp->tx_ring = dma_alloc_coherent(&mdp->pdev->dev, tx_ringsize,
1442 &mdp->tx_desc_dma, GFP_KERNEL);
1448 /* Free Rx and Tx skb ring buffer and DMA buffer */
1449 sh_eth_ring_free(ndev);
1454 static int sh_eth_dev_init(struct net_device *ndev)
1456 struct sh_eth_private *mdp = netdev_priv(ndev);
1460 ret = mdp->cd->soft_reset(ndev);
1464 if (mdp->cd->rmiimode)
1465 sh_eth_write(ndev, 0x1, RMIIMODE);
1467 /* Descriptor format */
1468 sh_eth_ring_format(ndev);
1469 if (mdp->cd->rpadir)
1470 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
1472 /* all sh_eth int mask */
1473 sh_eth_write(ndev, 0, EESIPR);
1475 #if defined(__LITTLE_ENDIAN)
1476 if (mdp->cd->hw_swap)
1477 sh_eth_write(ndev, EDMR_EL, EDMR);
1480 sh_eth_write(ndev, 0, EDMR);
1483 sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1484 sh_eth_write(ndev, 0, TFTR);
1486 /* Frame recv control (enable multiple-packets per rx irq) */
1487 sh_eth_write(ndev, RMCR_RNC, RMCR);
1489 sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER);
1491 /* DMA transfer burst mode */
1493 sh_eth_modify(ndev, EDMR, EDMR_NBST, EDMR_NBST);
1495 /* Burst cycle count upper-limit */
1497 sh_eth_write(ndev, 0x800, BCULR);
1499 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
1501 if (!mdp->cd->no_trimd)
1502 sh_eth_write(ndev, 0, TRIMD);
1504 /* Recv frame limit set register */
1505 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1508 sh_eth_modify(ndev, EESR, 0, 0);
1509 mdp->irq_enabled = true;
1510 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1512 /* PAUSE Prohibition */
1513 sh_eth_write(ndev, ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) |
1514 ECMR_TE | ECMR_RE, ECMR);
1516 if (mdp->cd->set_rate)
1517 mdp->cd->set_rate(ndev);
1519 /* E-MAC Status Register clear */
1520 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
1522 /* E-MAC Interrupt Enable register */
1523 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
1525 /* Set MAC address */
1526 update_mac_address(ndev);
1530 sh_eth_write(ndev, APR_AP, APR);
1532 sh_eth_write(ndev, MPR_MP, MPR);
1533 if (mdp->cd->tpauser)
1534 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
1536 /* Setting the Rx mode will start the Rx process. */
1537 sh_eth_write(ndev, EDRRR_R, EDRRR);
1542 static void sh_eth_dev_exit(struct net_device *ndev)
1544 struct sh_eth_private *mdp = netdev_priv(ndev);
1547 /* Deactivate all TX descriptors, so DMA should stop at next
1548 * packet boundary if it's currently running
1550 for (i = 0; i < mdp->num_tx_ring; i++)
1551 mdp->tx_ring[i].status &= ~cpu_to_le32(TD_TACT);
1553 /* Disable TX FIFO egress to MAC */
1554 sh_eth_rcv_snd_disable(ndev);
1556 /* Stop RX DMA at next packet boundary */
1557 sh_eth_write(ndev, 0, EDRRR);
1559 /* Aside from TX DMA, we can't tell when the hardware is
1560 * really stopped, so we need to reset to make sure.
1561 * Before doing that, wait for long enough to *probably*
1562 * finish transmitting the last packet and poll stats.
1564 msleep(2); /* max frame time at 10 Mbps < 1250 us */
1565 sh_eth_get_stats(ndev);
1566 mdp->cd->soft_reset(ndev);
1568 /* Set MAC address again */
1569 update_mac_address(ndev);
1572 /* Packet receive function */
1573 static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
1575 struct sh_eth_private *mdp = netdev_priv(ndev);
1576 struct sh_eth_rxdesc *rxdesc;
1578 int entry = mdp->cur_rx % mdp->num_rx_ring;
1579 int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
1581 struct sk_buff *skb;
1583 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
1584 dma_addr_t dma_addr;
1588 boguscnt = min(boguscnt, *quota);
1590 rxdesc = &mdp->rx_ring[entry];
1591 while (!(rxdesc->status & cpu_to_le32(RD_RACT))) {
1592 /* RACT bit must be checked before all the following reads */
1594 desc_status = le32_to_cpu(rxdesc->status);
1595 pkt_len = le32_to_cpu(rxdesc->len) & RD_RFL;
1600 netif_info(mdp, rx_status, ndev,
1601 "rx entry %d status 0x%08x len %d\n",
1602 entry, desc_status, pkt_len);
1604 if (!(desc_status & RDFEND))
1605 ndev->stats.rx_length_errors++;
1607 /* In case of almost all GETHER/ETHERs, the Receive Frame State
1608 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
1609 * bit 0. However, in case of the R8A7740 and R7S72100
1610 * the RFS bits are from bit 25 to bit 16. So, the
1611 * driver needs right shifting by 16.
1613 if (mdp->cd->hw_checksum)
1616 skb = mdp->rx_skbuff[entry];
1617 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1618 RD_RFS5 | RD_RFS6 | RD_RFS10)) {
1619 ndev->stats.rx_errors++;
1620 if (desc_status & RD_RFS1)
1621 ndev->stats.rx_crc_errors++;
1622 if (desc_status & RD_RFS2)
1623 ndev->stats.rx_frame_errors++;
1624 if (desc_status & RD_RFS3)
1625 ndev->stats.rx_length_errors++;
1626 if (desc_status & RD_RFS4)
1627 ndev->stats.rx_length_errors++;
1628 if (desc_status & RD_RFS6)
1629 ndev->stats.rx_missed_errors++;
1630 if (desc_status & RD_RFS10)
1631 ndev->stats.rx_over_errors++;
1633 dma_addr = le32_to_cpu(rxdesc->addr);
1634 if (!mdp->cd->hw_swap)
1636 phys_to_virt(ALIGN(dma_addr, 4)),
1638 mdp->rx_skbuff[entry] = NULL;
1639 if (mdp->cd->rpadir)
1640 skb_reserve(skb, NET_IP_ALIGN);
1641 dma_unmap_single(&mdp->pdev->dev, dma_addr,
1642 ALIGN(mdp->rx_buf_sz, 32),
1644 skb_put(skb, pkt_len);
1645 skb->protocol = eth_type_trans(skb, ndev);
1646 netif_receive_skb(skb);
1647 ndev->stats.rx_packets++;
1648 ndev->stats.rx_bytes += pkt_len;
1649 if (desc_status & RD_RFS8)
1650 ndev->stats.multicast++;
1652 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
1653 rxdesc = &mdp->rx_ring[entry];
1656 /* Refill the Rx ring buffers. */
1657 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
1658 entry = mdp->dirty_rx % mdp->num_rx_ring;
1659 rxdesc = &mdp->rx_ring[entry];
1660 /* The size of the buffer is 32 byte boundary. */
1661 buf_len = ALIGN(mdp->rx_buf_sz, 32);
1662 rxdesc->len = cpu_to_le32(buf_len << 16);
1664 if (mdp->rx_skbuff[entry] == NULL) {
1665 skb = netdev_alloc_skb(ndev, skbuff_size);
1667 break; /* Better luck next round. */
1668 sh_eth_set_receive_align(skb);
1669 dma_addr = dma_map_single(&mdp->pdev->dev, skb->data,
1670 buf_len, DMA_FROM_DEVICE);
1671 if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) {
1675 mdp->rx_skbuff[entry] = skb;
1677 skb_checksum_none_assert(skb);
1678 rxdesc->addr = cpu_to_le32(dma_addr);
1680 dma_wmb(); /* RACT bit must be set after all the above writes */
1681 if (entry >= mdp->num_rx_ring - 1)
1683 cpu_to_le32(RD_RACT | RD_RFP | RD_RDLE);
1685 rxdesc->status |= cpu_to_le32(RD_RACT | RD_RFP);
1688 /* Restart Rx engine if stopped. */
1689 /* If we don't need to check status, don't. -KDU */
1690 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
1691 /* fix the values for the next receiving if RDE is set */
1692 if (intr_status & EESR_RDE && !mdp->cd->no_xdfar) {
1693 u32 count = (sh_eth_read(ndev, RDFAR) -
1694 sh_eth_read(ndev, RDLAR)) >> 4;
1696 mdp->cur_rx = count;
1697 mdp->dirty_rx = count;
1699 sh_eth_write(ndev, EDRRR_R, EDRRR);
1702 *quota -= limit - boguscnt - 1;
1707 static void sh_eth_rcv_snd_disable(struct net_device *ndev)
1709 /* disable tx and rx */
1710 sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0);
1713 static void sh_eth_rcv_snd_enable(struct net_device *ndev)
1715 /* enable tx and rx */
1716 sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE);
1719 /* E-MAC interrupt handler */
1720 static void sh_eth_emac_interrupt(struct net_device *ndev)
1722 struct sh_eth_private *mdp = netdev_priv(ndev);
1726 felic_stat = sh_eth_read(ndev, ECSR) & sh_eth_read(ndev, ECSIPR);
1727 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */
1728 if (felic_stat & ECSR_ICD)
1729 ndev->stats.tx_carrier_errors++;
1730 if (felic_stat & ECSR_MPD)
1731 pm_wakeup_event(&mdp->pdev->dev, 0);
1732 if (felic_stat & ECSR_LCHNG) {
1734 if (mdp->cd->no_psr || mdp->no_ether_link)
1736 link_stat = sh_eth_read(ndev, PSR);
1737 if (mdp->ether_link_active_low)
1738 link_stat = ~link_stat;
1739 if (!(link_stat & PHY_ST_LINK)) {
1740 sh_eth_rcv_snd_disable(ndev);
1743 sh_eth_modify(ndev, EESIPR, EESIPR_ECIIP, 0);
1745 sh_eth_modify(ndev, ECSR, 0, 0);
1746 sh_eth_modify(ndev, EESIPR, EESIPR_ECIIP, EESIPR_ECIIP);
1747 /* enable tx and rx */
1748 sh_eth_rcv_snd_enable(ndev);
1753 /* error control function */
1754 static void sh_eth_error(struct net_device *ndev, u32 intr_status)
1756 struct sh_eth_private *mdp = netdev_priv(ndev);
1759 if (intr_status & EESR_TWB) {
1760 /* Unused write back interrupt */
1761 if (intr_status & EESR_TABT) { /* Transmit Abort int */
1762 ndev->stats.tx_aborted_errors++;
1763 netif_err(mdp, tx_err, ndev, "Transmit Abort\n");
1767 if (intr_status & EESR_RABT) {
1768 /* Receive Abort int */
1769 if (intr_status & EESR_RFRMER) {
1770 /* Receive Frame Overflow int */
1771 ndev->stats.rx_frame_errors++;
1775 if (intr_status & EESR_TDE) {
1776 /* Transmit Descriptor Empty int */
1777 ndev->stats.tx_fifo_errors++;
1778 netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n");
1781 if (intr_status & EESR_TFE) {
1782 /* FIFO under flow */
1783 ndev->stats.tx_fifo_errors++;
1784 netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n");
1787 if (intr_status & EESR_RDE) {
1788 /* Receive Descriptor Empty int */
1789 ndev->stats.rx_over_errors++;
1792 if (intr_status & EESR_RFE) {
1793 /* Receive FIFO Overflow int */
1794 ndev->stats.rx_fifo_errors++;
1797 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1799 ndev->stats.tx_fifo_errors++;
1800 netif_err(mdp, tx_err, ndev, "Address Error\n");
1803 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1804 if (mdp->cd->no_ade)
1806 if (intr_status & mask) {
1808 u32 edtrr = sh_eth_read(ndev, EDTRR);
1811 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1812 intr_status, mdp->cur_tx, mdp->dirty_tx,
1813 (u32)ndev->state, edtrr);
1814 /* dirty buffer free */
1815 sh_eth_tx_free(ndev, true);
1818 if (edtrr ^ mdp->cd->edtrr_trns) {
1820 sh_eth_write(ndev, mdp->cd->edtrr_trns, EDTRR);
1823 netif_wake_queue(ndev);
1827 static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1829 struct net_device *ndev = netdev;
1830 struct sh_eth_private *mdp = netdev_priv(ndev);
1831 struct sh_eth_cpu_data *cd = mdp->cd;
1832 irqreturn_t ret = IRQ_NONE;
1833 u32 intr_status, intr_enable;
1835 spin_lock(&mdp->lock);
1837 /* Get interrupt status */
1838 intr_status = sh_eth_read(ndev, EESR);
1839 /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1840 * enabled since it's the one that comes thru regardless of the mask,
1841 * and we need to fully handle it in sh_eth_emac_interrupt() in order
1842 * to quench it as it doesn't get cleared by just writing 1 to the ECI
1845 intr_enable = sh_eth_read(ndev, EESIPR);
1846 intr_status &= intr_enable | EESIPR_ECIIP;
1847 if (intr_status & (EESR_RX_CHECK | cd->tx_check | EESR_ECI |
1848 cd->eesr_err_check))
1853 if (unlikely(!mdp->irq_enabled)) {
1854 sh_eth_write(ndev, 0, EESIPR);
1858 if (intr_status & EESR_RX_CHECK) {
1859 if (napi_schedule_prep(&mdp->napi)) {
1860 /* Mask Rx interrupts */
1861 sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
1863 __napi_schedule(&mdp->napi);
1866 "ignoring interrupt, status 0x%08x, mask 0x%08x.\n",
1867 intr_status, intr_enable);
1872 if (intr_status & cd->tx_check) {
1873 /* Clear Tx interrupts */
1874 sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
1876 sh_eth_tx_free(ndev, true);
1877 netif_wake_queue(ndev);
1880 /* E-MAC interrupt */
1881 if (intr_status & EESR_ECI)
1882 sh_eth_emac_interrupt(ndev);
1884 if (intr_status & cd->eesr_err_check) {
1885 /* Clear error interrupts */
1886 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
1888 sh_eth_error(ndev, intr_status);
1892 spin_unlock(&mdp->lock);
1897 static int sh_eth_poll(struct napi_struct *napi, int budget)
1899 struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
1901 struct net_device *ndev = napi->dev;
1906 intr_status = sh_eth_read(ndev, EESR);
1907 if (!(intr_status & EESR_RX_CHECK))
1909 /* Clear Rx interrupts */
1910 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
1912 if (sh_eth_rx(ndev, intr_status, "a))
1916 napi_complete(napi);
1918 /* Reenable Rx interrupts */
1919 if (mdp->irq_enabled)
1920 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1922 return budget - quota;
1925 /* PHY state control function */
1926 static void sh_eth_adjust_link(struct net_device *ndev)
1928 struct sh_eth_private *mdp = netdev_priv(ndev);
1929 struct phy_device *phydev = ndev->phydev;
1930 unsigned long flags;
1933 spin_lock_irqsave(&mdp->lock, flags);
1935 /* Disable TX and RX right over here, if E-MAC change is ignored */
1936 if (mdp->cd->no_psr || mdp->no_ether_link)
1937 sh_eth_rcv_snd_disable(ndev);
1940 if (phydev->duplex != mdp->duplex) {
1942 mdp->duplex = phydev->duplex;
1943 if (mdp->cd->set_duplex)
1944 mdp->cd->set_duplex(ndev);
1947 if (phydev->speed != mdp->speed) {
1949 mdp->speed = phydev->speed;
1950 if (mdp->cd->set_rate)
1951 mdp->cd->set_rate(ndev);
1954 sh_eth_modify(ndev, ECMR, ECMR_TXF, 0);
1956 mdp->link = phydev->link;
1958 } else if (mdp->link) {
1965 /* Enable TX and RX right over here, if E-MAC change is ignored */
1966 if ((mdp->cd->no_psr || mdp->no_ether_link) && phydev->link)
1967 sh_eth_rcv_snd_enable(ndev);
1970 spin_unlock_irqrestore(&mdp->lock, flags);
1972 if (new_state && netif_msg_link(mdp))
1973 phy_print_status(phydev);
1976 /* PHY init function */
1977 static int sh_eth_phy_init(struct net_device *ndev)
1979 struct device_node *np = ndev->dev.parent->of_node;
1980 struct sh_eth_private *mdp = netdev_priv(ndev);
1981 struct phy_device *phydev;
1987 /* Try connect to PHY */
1989 struct device_node *pn;
1991 pn = of_parse_phandle(np, "phy-handle", 0);
1992 phydev = of_phy_connect(ndev, pn,
1993 sh_eth_adjust_link, 0,
1994 mdp->phy_interface);
1998 phydev = ERR_PTR(-ENOENT);
2000 char phy_id[MII_BUS_ID_SIZE + 3];
2002 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
2003 mdp->mii_bus->id, mdp->phy_id);
2005 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
2006 mdp->phy_interface);
2009 if (IS_ERR(phydev)) {
2010 netdev_err(ndev, "failed to connect PHY\n");
2011 return PTR_ERR(phydev);
2014 /* mask with MAC supported features */
2015 if (mdp->cd->register_type != SH_ETH_REG_GIGABIT) {
2016 int err = phy_set_max_speed(phydev, SPEED_100);
2018 netdev_err(ndev, "failed to limit PHY to 100 Mbit/s\n");
2019 phy_disconnect(phydev);
2024 phy_attached_info(phydev);
2029 /* PHY control start function */
2030 static int sh_eth_phy_start(struct net_device *ndev)
2034 ret = sh_eth_phy_init(ndev);
2038 phy_start(ndev->phydev);
2043 static int sh_eth_get_link_ksettings(struct net_device *ndev,
2044 struct ethtool_link_ksettings *cmd)
2046 struct sh_eth_private *mdp = netdev_priv(ndev);
2047 unsigned long flags;
2052 spin_lock_irqsave(&mdp->lock, flags);
2053 phy_ethtool_ksettings_get(ndev->phydev, cmd);
2054 spin_unlock_irqrestore(&mdp->lock, flags);
2059 static int sh_eth_set_link_ksettings(struct net_device *ndev,
2060 const struct ethtool_link_ksettings *cmd)
2065 return phy_ethtool_ksettings_set(ndev->phydev, cmd);
2068 /* If it is ever necessary to increase SH_ETH_REG_DUMP_MAX_REGS, the
2069 * version must be bumped as well. Just adding registers up to that
2070 * limit is fine, as long as the existing register indices don't
2073 #define SH_ETH_REG_DUMP_VERSION 1
2074 #define SH_ETH_REG_DUMP_MAX_REGS 256
2076 static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf)
2078 struct sh_eth_private *mdp = netdev_priv(ndev);
2079 struct sh_eth_cpu_data *cd = mdp->cd;
2083 BUILD_BUG_ON(SH_ETH_MAX_REGISTER_OFFSET > SH_ETH_REG_DUMP_MAX_REGS);
2085 /* Dump starts with a bitmap that tells ethtool which
2086 * registers are defined for this chip.
2088 len = DIV_ROUND_UP(SH_ETH_REG_DUMP_MAX_REGS, 32);
2096 /* Add a register to the dump, if it has a defined offset.
2097 * This automatically skips most undefined registers, but for
2098 * some it is also necessary to check a capability flag in
2099 * struct sh_eth_cpu_data.
2101 #define mark_reg_valid(reg) valid_map[reg / 32] |= 1U << (reg % 32)
2102 #define add_reg_from(reg, read_expr) do { \
2103 if (mdp->reg_offset[reg] != SH_ETH_OFFSET_INVALID) { \
2105 mark_reg_valid(reg); \
2106 *buf++ = read_expr; \
2111 #define add_reg(reg) add_reg_from(reg, sh_eth_read(ndev, reg))
2112 #define add_tsu_reg(reg) add_reg_from(reg, sh_eth_tsu_read(mdp, reg))
2178 if (cd->hw_checksum)
2184 add_tsu_reg(TSU_CTRST);
2185 add_tsu_reg(TSU_FWEN0);
2186 add_tsu_reg(TSU_FWEN1);
2187 add_tsu_reg(TSU_FCM);
2188 add_tsu_reg(TSU_BSYSL0);
2189 add_tsu_reg(TSU_BSYSL1);
2190 add_tsu_reg(TSU_PRISL0);
2191 add_tsu_reg(TSU_PRISL1);
2192 add_tsu_reg(TSU_FWSL0);
2193 add_tsu_reg(TSU_FWSL1);
2194 add_tsu_reg(TSU_FWSLC);
2195 add_tsu_reg(TSU_QTAGM0);
2196 add_tsu_reg(TSU_QTAGM1);
2197 add_tsu_reg(TSU_FWSR);
2198 add_tsu_reg(TSU_FWINMK);
2199 add_tsu_reg(TSU_ADQT0);
2200 add_tsu_reg(TSU_ADQT1);
2201 add_tsu_reg(TSU_VTAG0);
2202 add_tsu_reg(TSU_VTAG1);
2203 add_tsu_reg(TSU_ADSBSY);
2204 add_tsu_reg(TSU_TEN);
2205 add_tsu_reg(TSU_POST1);
2206 add_tsu_reg(TSU_POST2);
2207 add_tsu_reg(TSU_POST3);
2208 add_tsu_reg(TSU_POST4);
2209 /* This is the start of a table, not just a single register. */
2213 mark_reg_valid(TSU_ADRH0);
2214 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES * 2; i++)
2215 *buf++ = ioread32(mdp->tsu_addr +
2216 mdp->reg_offset[TSU_ADRH0] +
2219 len += SH_ETH_TSU_CAM_ENTRIES * 2;
2222 #undef mark_reg_valid
2230 static int sh_eth_get_regs_len(struct net_device *ndev)
2232 return __sh_eth_get_regs(ndev, NULL);
2235 static void sh_eth_get_regs(struct net_device *ndev, struct ethtool_regs *regs,
2238 struct sh_eth_private *mdp = netdev_priv(ndev);
2240 regs->version = SH_ETH_REG_DUMP_VERSION;
2242 pm_runtime_get_sync(&mdp->pdev->dev);
2243 __sh_eth_get_regs(ndev, buf);
2244 pm_runtime_put_sync(&mdp->pdev->dev);
2247 static int sh_eth_nway_reset(struct net_device *ndev)
2252 return phy_restart_aneg(ndev->phydev);
2255 static u32 sh_eth_get_msglevel(struct net_device *ndev)
2257 struct sh_eth_private *mdp = netdev_priv(ndev);
2258 return mdp->msg_enable;
2261 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
2263 struct sh_eth_private *mdp = netdev_priv(ndev);
2264 mdp->msg_enable = value;
2267 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
2268 "rx_current", "tx_current",
2269 "rx_dirty", "tx_dirty",
2271 #define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
2273 static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
2277 return SH_ETH_STATS_LEN;
2283 static void sh_eth_get_ethtool_stats(struct net_device *ndev,
2284 struct ethtool_stats *stats, u64 *data)
2286 struct sh_eth_private *mdp = netdev_priv(ndev);
2289 /* device-specific stats */
2290 data[i++] = mdp->cur_rx;
2291 data[i++] = mdp->cur_tx;
2292 data[i++] = mdp->dirty_rx;
2293 data[i++] = mdp->dirty_tx;
2296 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
2298 switch (stringset) {
2300 memcpy(data, *sh_eth_gstrings_stats,
2301 sizeof(sh_eth_gstrings_stats));
2306 static void sh_eth_get_ringparam(struct net_device *ndev,
2307 struct ethtool_ringparam *ring)
2309 struct sh_eth_private *mdp = netdev_priv(ndev);
2311 ring->rx_max_pending = RX_RING_MAX;
2312 ring->tx_max_pending = TX_RING_MAX;
2313 ring->rx_pending = mdp->num_rx_ring;
2314 ring->tx_pending = mdp->num_tx_ring;
2317 static int sh_eth_set_ringparam(struct net_device *ndev,
2318 struct ethtool_ringparam *ring)
2320 struct sh_eth_private *mdp = netdev_priv(ndev);
2323 if (ring->tx_pending > TX_RING_MAX ||
2324 ring->rx_pending > RX_RING_MAX ||
2325 ring->tx_pending < TX_RING_MIN ||
2326 ring->rx_pending < RX_RING_MIN)
2328 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
2331 if (netif_running(ndev)) {
2332 netif_device_detach(ndev);
2333 netif_tx_disable(ndev);
2335 /* Serialise with the interrupt handler and NAPI, then
2336 * disable interrupts. We have to clear the
2337 * irq_enabled flag first to ensure that interrupts
2338 * won't be re-enabled.
2340 mdp->irq_enabled = false;
2341 synchronize_irq(ndev->irq);
2342 napi_synchronize(&mdp->napi);
2343 sh_eth_write(ndev, 0x0000, EESIPR);
2345 sh_eth_dev_exit(ndev);
2347 /* Free all the skbuffs in the Rx queue and the DMA buffers. */
2348 sh_eth_ring_free(ndev);
2351 /* Set new parameters */
2352 mdp->num_rx_ring = ring->rx_pending;
2353 mdp->num_tx_ring = ring->tx_pending;
2355 if (netif_running(ndev)) {
2356 ret = sh_eth_ring_init(ndev);
2358 netdev_err(ndev, "%s: sh_eth_ring_init failed.\n",
2362 ret = sh_eth_dev_init(ndev);
2364 netdev_err(ndev, "%s: sh_eth_dev_init failed.\n",
2369 netif_device_attach(ndev);
2375 static void sh_eth_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2377 struct sh_eth_private *mdp = netdev_priv(ndev);
2382 if (mdp->cd->magic) {
2383 wol->supported = WAKE_MAGIC;
2384 wol->wolopts = mdp->wol_enabled ? WAKE_MAGIC : 0;
2388 static int sh_eth_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2390 struct sh_eth_private *mdp = netdev_priv(ndev);
2392 if (!mdp->cd->magic || wol->wolopts & ~WAKE_MAGIC)
2395 mdp->wol_enabled = !!(wol->wolopts & WAKE_MAGIC);
2397 device_set_wakeup_enable(&mdp->pdev->dev, mdp->wol_enabled);
2402 static const struct ethtool_ops sh_eth_ethtool_ops = {
2403 .get_regs_len = sh_eth_get_regs_len,
2404 .get_regs = sh_eth_get_regs,
2405 .nway_reset = sh_eth_nway_reset,
2406 .get_msglevel = sh_eth_get_msglevel,
2407 .set_msglevel = sh_eth_set_msglevel,
2408 .get_link = ethtool_op_get_link,
2409 .get_strings = sh_eth_get_strings,
2410 .get_ethtool_stats = sh_eth_get_ethtool_stats,
2411 .get_sset_count = sh_eth_get_sset_count,
2412 .get_ringparam = sh_eth_get_ringparam,
2413 .set_ringparam = sh_eth_set_ringparam,
2414 .get_link_ksettings = sh_eth_get_link_ksettings,
2415 .set_link_ksettings = sh_eth_set_link_ksettings,
2416 .get_wol = sh_eth_get_wol,
2417 .set_wol = sh_eth_set_wol,
2420 /* network device open function */
2421 static int sh_eth_open(struct net_device *ndev)
2423 struct sh_eth_private *mdp = netdev_priv(ndev);
2426 pm_runtime_get_sync(&mdp->pdev->dev);
2428 napi_enable(&mdp->napi);
2430 ret = request_irq(ndev->irq, sh_eth_interrupt,
2431 mdp->cd->irq_flags, ndev->name, ndev);
2433 netdev_err(ndev, "Can not assign IRQ number\n");
2437 /* Descriptor set */
2438 ret = sh_eth_ring_init(ndev);
2443 ret = sh_eth_dev_init(ndev);
2447 /* PHY control start*/
2448 ret = sh_eth_phy_start(ndev);
2452 netif_start_queue(ndev);
2459 free_irq(ndev->irq, ndev);
2461 napi_disable(&mdp->napi);
2462 pm_runtime_put_sync(&mdp->pdev->dev);
2466 /* Timeout function */
2467 static void sh_eth_tx_timeout(struct net_device *ndev)
2469 struct sh_eth_private *mdp = netdev_priv(ndev);
2470 struct sh_eth_rxdesc *rxdesc;
2473 netif_stop_queue(ndev);
2475 netif_err(mdp, timer, ndev,
2476 "transmit timed out, status %8.8x, resetting...\n",
2477 sh_eth_read(ndev, EESR));
2479 /* tx_errors count up */
2480 ndev->stats.tx_errors++;
2482 /* Free all the skbuffs in the Rx queue. */
2483 for (i = 0; i < mdp->num_rx_ring; i++) {
2484 rxdesc = &mdp->rx_ring[i];
2485 rxdesc->status = cpu_to_le32(0);
2486 rxdesc->addr = cpu_to_le32(0xBADF00D0);
2487 dev_kfree_skb(mdp->rx_skbuff[i]);
2488 mdp->rx_skbuff[i] = NULL;
2490 for (i = 0; i < mdp->num_tx_ring; i++) {
2491 dev_kfree_skb(mdp->tx_skbuff[i]);
2492 mdp->tx_skbuff[i] = NULL;
2496 sh_eth_dev_init(ndev);
2498 netif_start_queue(ndev);
2501 /* Packet transmit function */
2502 static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
2504 struct sh_eth_private *mdp = netdev_priv(ndev);
2505 struct sh_eth_txdesc *txdesc;
2506 dma_addr_t dma_addr;
2508 unsigned long flags;
2510 spin_lock_irqsave(&mdp->lock, flags);
2511 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
2512 if (!sh_eth_tx_free(ndev, true)) {
2513 netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n");
2514 netif_stop_queue(ndev);
2515 spin_unlock_irqrestore(&mdp->lock, flags);
2516 return NETDEV_TX_BUSY;
2519 spin_unlock_irqrestore(&mdp->lock, flags);
2521 if (skb_put_padto(skb, ETH_ZLEN))
2522 return NETDEV_TX_OK;
2524 entry = mdp->cur_tx % mdp->num_tx_ring;
2525 mdp->tx_skbuff[entry] = skb;
2526 txdesc = &mdp->tx_ring[entry];
2528 if (!mdp->cd->hw_swap)
2529 sh_eth_soft_swap(PTR_ALIGN(skb->data, 4), skb->len + 2);
2530 dma_addr = dma_map_single(&mdp->pdev->dev, skb->data, skb->len,
2532 if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) {
2534 return NETDEV_TX_OK;
2536 txdesc->addr = cpu_to_le32(dma_addr);
2537 txdesc->len = cpu_to_le32(skb->len << 16);
2539 dma_wmb(); /* TACT bit must be set after all the above writes */
2540 if (entry >= mdp->num_tx_ring - 1)
2541 txdesc->status |= cpu_to_le32(TD_TACT | TD_TDLE);
2543 txdesc->status |= cpu_to_le32(TD_TACT);
2547 if (!(sh_eth_read(ndev, EDTRR) & mdp->cd->edtrr_trns))
2548 sh_eth_write(ndev, mdp->cd->edtrr_trns, EDTRR);
2550 return NETDEV_TX_OK;
2553 /* The statistics registers have write-clear behaviour, which means we
2554 * will lose any increment between the read and write. We mitigate
2555 * this by only clearing when we read a non-zero value, so we will
2556 * never falsely report a total of zero.
2559 sh_eth_update_stat(struct net_device *ndev, unsigned long *stat, int reg)
2561 u32 delta = sh_eth_read(ndev, reg);
2565 sh_eth_write(ndev, 0, reg);
2569 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2571 struct sh_eth_private *mdp = netdev_priv(ndev);
2573 if (mdp->cd->no_tx_cntrs)
2574 return &ndev->stats;
2576 if (!mdp->is_opened)
2577 return &ndev->stats;
2579 sh_eth_update_stat(ndev, &ndev->stats.tx_dropped, TROCR);
2580 sh_eth_update_stat(ndev, &ndev->stats.collisions, CDCR);
2581 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, LCCR);
2583 if (mdp->cd->cexcr) {
2584 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2586 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2589 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2593 return &ndev->stats;
2596 /* device close function */
2597 static int sh_eth_close(struct net_device *ndev)
2599 struct sh_eth_private *mdp = netdev_priv(ndev);
2601 netif_stop_queue(ndev);
2603 /* Serialise with the interrupt handler and NAPI, then disable
2604 * interrupts. We have to clear the irq_enabled flag first to
2605 * ensure that interrupts won't be re-enabled.
2607 mdp->irq_enabled = false;
2608 synchronize_irq(ndev->irq);
2609 napi_disable(&mdp->napi);
2610 sh_eth_write(ndev, 0x0000, EESIPR);
2612 sh_eth_dev_exit(ndev);
2614 /* PHY Disconnect */
2616 phy_stop(ndev->phydev);
2617 phy_disconnect(ndev->phydev);
2620 free_irq(ndev->irq, ndev);
2622 /* Free all the skbuffs in the Rx queue and the DMA buffer. */
2623 sh_eth_ring_free(ndev);
2625 pm_runtime_put_sync(&mdp->pdev->dev);
2632 /* ioctl to device function */
2633 static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2635 struct phy_device *phydev = ndev->phydev;
2637 if (!netif_running(ndev))
2643 return phy_mii_ioctl(phydev, rq, cmd);
2646 static int sh_eth_change_mtu(struct net_device *ndev, int new_mtu)
2648 if (netif_running(ndev))
2651 ndev->mtu = new_mtu;
2652 netdev_update_features(ndev);
2657 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2658 static u32 sh_eth_tsu_get_post_mask(int entry)
2660 return 0x0f << (28 - ((entry % 8) * 4));
2663 static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2665 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2668 static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2671 struct sh_eth_private *mdp = netdev_priv(ndev);
2672 int reg = TSU_POST1 + entry / 8;
2675 tmp = sh_eth_tsu_read(mdp, reg);
2676 sh_eth_tsu_write(mdp, tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg);
2679 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2682 struct sh_eth_private *mdp = netdev_priv(ndev);
2683 int reg = TSU_POST1 + entry / 8;
2684 u32 post_mask, ref_mask, tmp;
2686 post_mask = sh_eth_tsu_get_post_mask(entry);
2687 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2689 tmp = sh_eth_tsu_read(mdp, reg);
2690 sh_eth_tsu_write(mdp, tmp & ~post_mask, reg);
2692 /* If other port enables, the function returns "true" */
2693 return tmp & ref_mask;
2696 static int sh_eth_tsu_busy(struct net_device *ndev)
2698 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2699 struct sh_eth_private *mdp = netdev_priv(ndev);
2701 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2705 netdev_err(ndev, "%s: timeout\n", __func__);
2713 static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
2718 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2719 iowrite32(val, reg);
2720 if (sh_eth_tsu_busy(ndev) < 0)
2723 val = addr[4] << 8 | addr[5];
2724 iowrite32(val, reg + 4);
2725 if (sh_eth_tsu_busy(ndev) < 0)
2731 static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
2735 val = ioread32(reg);
2736 addr[0] = (val >> 24) & 0xff;
2737 addr[1] = (val >> 16) & 0xff;
2738 addr[2] = (val >> 8) & 0xff;
2739 addr[3] = val & 0xff;
2740 val = ioread32(reg + 4);
2741 addr[4] = (val >> 8) & 0xff;
2742 addr[5] = val & 0xff;
2746 static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2748 struct sh_eth_private *mdp = netdev_priv(ndev);
2749 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2751 u8 c_addr[ETH_ALEN];
2753 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2754 sh_eth_tsu_read_entry(reg_offset, c_addr);
2755 if (ether_addr_equal(addr, c_addr))
2762 static int sh_eth_tsu_find_empty(struct net_device *ndev)
2767 memset(blank, 0, sizeof(blank));
2768 entry = sh_eth_tsu_find_entry(ndev, blank);
2769 return (entry < 0) ? -ENOMEM : entry;
2772 static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2775 struct sh_eth_private *mdp = netdev_priv(ndev);
2776 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2780 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2781 ~(1 << (31 - entry)), TSU_TEN);
2783 memset(blank, 0, sizeof(blank));
2784 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2790 static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2792 struct sh_eth_private *mdp = netdev_priv(ndev);
2793 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2799 i = sh_eth_tsu_find_entry(ndev, addr);
2801 /* No entry found, create one */
2802 i = sh_eth_tsu_find_empty(ndev);
2805 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2809 /* Enable the entry */
2810 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2811 (1 << (31 - i)), TSU_TEN);
2814 /* Entry found or created, enable POST */
2815 sh_eth_tsu_enable_cam_entry_post(ndev, i);
2820 static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2822 struct sh_eth_private *mdp = netdev_priv(ndev);
2828 i = sh_eth_tsu_find_entry(ndev, addr);
2831 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2834 /* Disable the entry if both ports was disabled */
2835 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2843 static int sh_eth_tsu_purge_all(struct net_device *ndev)
2845 struct sh_eth_private *mdp = netdev_priv(ndev);
2851 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2852 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2855 /* Disable the entry if both ports was disabled */
2856 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2864 static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2866 struct sh_eth_private *mdp = netdev_priv(ndev);
2868 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2874 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2875 sh_eth_tsu_read_entry(reg_offset, addr);
2876 if (is_multicast_ether_addr(addr))
2877 sh_eth_tsu_del_entry(ndev, addr);
2881 /* Update promiscuous flag and multicast filter */
2882 static void sh_eth_set_rx_mode(struct net_device *ndev)
2884 struct sh_eth_private *mdp = netdev_priv(ndev);
2887 unsigned long flags;
2889 spin_lock_irqsave(&mdp->lock, flags);
2890 /* Initial condition is MCT = 1, PRM = 0.
2891 * Depending on ndev->flags, set PRM or clear MCT
2893 ecmr_bits = sh_eth_read(ndev, ECMR) & ~ECMR_PRM;
2895 ecmr_bits |= ECMR_MCT;
2897 if (!(ndev->flags & IFF_MULTICAST)) {
2898 sh_eth_tsu_purge_mcast(ndev);
2901 if (ndev->flags & IFF_ALLMULTI) {
2902 sh_eth_tsu_purge_mcast(ndev);
2903 ecmr_bits &= ~ECMR_MCT;
2907 if (ndev->flags & IFF_PROMISC) {
2908 sh_eth_tsu_purge_all(ndev);
2909 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2910 } else if (mdp->cd->tsu) {
2911 struct netdev_hw_addr *ha;
2912 netdev_for_each_mc_addr(ha, ndev) {
2913 if (mcast_all && is_multicast_ether_addr(ha->addr))
2916 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2918 sh_eth_tsu_purge_mcast(ndev);
2919 ecmr_bits &= ~ECMR_MCT;
2926 /* update the ethernet mode */
2927 sh_eth_write(ndev, ecmr_bits, ECMR);
2929 spin_unlock_irqrestore(&mdp->lock, flags);
2932 static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2940 static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2941 __be16 proto, u16 vid)
2943 struct sh_eth_private *mdp = netdev_priv(ndev);
2944 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2946 if (unlikely(!mdp->cd->tsu))
2949 /* No filtering if vid = 0 */
2953 mdp->vlan_num_ids++;
2955 /* The controller has one VLAN tag HW filter. So, if the filter is
2956 * already enabled, the driver disables it and the filte
2958 if (mdp->vlan_num_ids > 1) {
2959 /* disable VLAN filter */
2960 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2964 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2970 static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2971 __be16 proto, u16 vid)
2973 struct sh_eth_private *mdp = netdev_priv(ndev);
2974 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2976 if (unlikely(!mdp->cd->tsu))
2979 /* No filtering if vid = 0 */
2983 mdp->vlan_num_ids--;
2984 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2989 /* SuperH's TSU register init function */
2990 static void sh_eth_tsu_init(struct sh_eth_private *mdp)
2992 if (!mdp->cd->dual_port) {
2993 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2994 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL,
2995 TSU_FWSLC); /* Enable POST registers */
2999 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */
3000 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */
3001 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */
3002 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
3003 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
3004 sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
3005 sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
3006 sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
3007 sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
3008 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
3009 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */
3010 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */
3011 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */
3012 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */
3013 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
3014 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */
3015 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */
3016 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */
3017 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */
3020 /* MDIO bus release function */
3021 static int sh_mdio_release(struct sh_eth_private *mdp)
3023 /* unregister mdio bus */
3024 mdiobus_unregister(mdp->mii_bus);
3026 /* free bitbang info */
3027 free_mdio_bitbang(mdp->mii_bus);
3032 /* MDIO bus init function */
3033 static int sh_mdio_init(struct sh_eth_private *mdp,
3034 struct sh_eth_plat_data *pd)
3037 struct bb_info *bitbang;
3038 struct platform_device *pdev = mdp->pdev;
3039 struct device *dev = &mdp->pdev->dev;
3041 /* create bit control struct for PHY */
3042 bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL);
3047 bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
3048 bitbang->set_gate = pd->set_mdio_gate;
3049 bitbang->ctrl.ops = &bb_ops;
3051 /* MII controller setting */
3052 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
3056 /* Hook up MII support for ethtool */
3057 mdp->mii_bus->name = "sh_mii";
3058 mdp->mii_bus->parent = dev;
3059 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
3060 pdev->name, pdev->id);
3062 /* register MDIO bus */
3063 if (pd->phy_irq > 0)
3064 mdp->mii_bus->irq[pd->phy] = pd->phy_irq;
3066 ret = of_mdiobus_register(mdp->mii_bus, dev->of_node);
3073 free_mdio_bitbang(mdp->mii_bus);
3077 static const u16 *sh_eth_get_register_offset(int register_type)
3079 const u16 *reg_offset = NULL;
3081 switch (register_type) {
3082 case SH_ETH_REG_GIGABIT:
3083 reg_offset = sh_eth_offset_gigabit;
3085 case SH_ETH_REG_FAST_RZ:
3086 reg_offset = sh_eth_offset_fast_rz;
3088 case SH_ETH_REG_FAST_RCAR:
3089 reg_offset = sh_eth_offset_fast_rcar;
3091 case SH_ETH_REG_FAST_SH4:
3092 reg_offset = sh_eth_offset_fast_sh4;
3094 case SH_ETH_REG_FAST_SH3_SH2:
3095 reg_offset = sh_eth_offset_fast_sh3_sh2;
3102 static const struct net_device_ops sh_eth_netdev_ops = {
3103 .ndo_open = sh_eth_open,
3104 .ndo_stop = sh_eth_close,
3105 .ndo_start_xmit = sh_eth_start_xmit,
3106 .ndo_get_stats = sh_eth_get_stats,
3107 .ndo_set_rx_mode = sh_eth_set_rx_mode,
3108 .ndo_tx_timeout = sh_eth_tx_timeout,
3109 .ndo_do_ioctl = sh_eth_do_ioctl,
3110 .ndo_change_mtu = sh_eth_change_mtu,
3111 .ndo_validate_addr = eth_validate_addr,
3112 .ndo_set_mac_address = eth_mac_addr,
3115 static const struct net_device_ops sh_eth_netdev_ops_tsu = {
3116 .ndo_open = sh_eth_open,
3117 .ndo_stop = sh_eth_close,
3118 .ndo_start_xmit = sh_eth_start_xmit,
3119 .ndo_get_stats = sh_eth_get_stats,
3120 .ndo_set_rx_mode = sh_eth_set_rx_mode,
3121 .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid,
3122 .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid,
3123 .ndo_tx_timeout = sh_eth_tx_timeout,
3124 .ndo_do_ioctl = sh_eth_do_ioctl,
3125 .ndo_change_mtu = sh_eth_change_mtu,
3126 .ndo_validate_addr = eth_validate_addr,
3127 .ndo_set_mac_address = eth_mac_addr,
3131 static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
3133 struct device_node *np = dev->of_node;
3134 struct sh_eth_plat_data *pdata;
3135 const char *mac_addr;
3137 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
3141 pdata->phy_interface = of_get_phy_mode(np);
3143 mac_addr = of_get_mac_address(np);
3145 memcpy(pdata->mac_addr, mac_addr, ETH_ALEN);
3147 pdata->no_ether_link =
3148 of_property_read_bool(np, "renesas,no-ether-link");
3149 pdata->ether_link_active_low =
3150 of_property_read_bool(np, "renesas,ether-link-active-low");
3155 static const struct of_device_id sh_eth_match_table[] = {
3156 { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data },
3157 { .compatible = "renesas,ether-r8a7743", .data = &rcar_gen2_data },
3158 { .compatible = "renesas,ether-r8a7745", .data = &rcar_gen2_data },
3159 { .compatible = "renesas,ether-r8a7778", .data = &rcar_gen1_data },
3160 { .compatible = "renesas,ether-r8a7779", .data = &rcar_gen1_data },
3161 { .compatible = "renesas,ether-r8a7790", .data = &rcar_gen2_data },
3162 { .compatible = "renesas,ether-r8a7791", .data = &rcar_gen2_data },
3163 { .compatible = "renesas,ether-r8a7793", .data = &rcar_gen2_data },
3164 { .compatible = "renesas,ether-r8a7794", .data = &rcar_gen2_data },
3165 { .compatible = "renesas,gether-r8a77980", .data = &r8a77980_data },
3166 { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data },
3167 { .compatible = "renesas,rcar-gen1-ether", .data = &rcar_gen1_data },
3168 { .compatible = "renesas,rcar-gen2-ether", .data = &rcar_gen2_data },
3171 MODULE_DEVICE_TABLE(of, sh_eth_match_table);
3173 static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
3179 static int sh_eth_drv_probe(struct platform_device *pdev)
3181 struct resource *res;
3182 struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev);
3183 const struct platform_device_id *id = platform_get_device_id(pdev);
3184 struct sh_eth_private *mdp;
3185 struct net_device *ndev;
3189 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3191 ndev = alloc_etherdev(sizeof(struct sh_eth_private));
3195 pm_runtime_enable(&pdev->dev);
3196 pm_runtime_get_sync(&pdev->dev);
3198 ret = platform_get_irq(pdev, 0);
3203 SET_NETDEV_DEV(ndev, &pdev->dev);
3205 mdp = netdev_priv(ndev);
3206 mdp->num_tx_ring = TX_RING_SIZE;
3207 mdp->num_rx_ring = RX_RING_SIZE;
3208 mdp->addr = devm_ioremap_resource(&pdev->dev, res);
3209 if (IS_ERR(mdp->addr)) {
3210 ret = PTR_ERR(mdp->addr);
3214 ndev->base_addr = res->start;
3216 spin_lock_init(&mdp->lock);
3219 if (pdev->dev.of_node)
3220 pd = sh_eth_parse_dt(&pdev->dev);
3222 dev_err(&pdev->dev, "no platform data\n");
3228 mdp->phy_id = pd->phy;
3229 mdp->phy_interface = pd->phy_interface;
3230 mdp->no_ether_link = pd->no_ether_link;
3231 mdp->ether_link_active_low = pd->ether_link_active_low;
3235 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
3237 mdp->cd = (struct sh_eth_cpu_data *)of_device_get_match_data(&pdev->dev);
3239 mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type);
3240 if (!mdp->reg_offset) {
3241 dev_err(&pdev->dev, "Unknown register type (%d)\n",
3242 mdp->cd->register_type);
3246 sh_eth_set_default_cpu_data(mdp->cd);
3248 /* User's manual states max MTU should be 2048 but due to the
3249 * alignment calculations in sh_eth_ring_init() the practical
3250 * MTU is a bit less. Maybe this can be optimized some more.
3252 ndev->max_mtu = 2000 - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN);
3253 ndev->min_mtu = ETH_MIN_MTU;
3257 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
3259 ndev->netdev_ops = &sh_eth_netdev_ops;
3260 ndev->ethtool_ops = &sh_eth_ethtool_ops;
3261 ndev->watchdog_timeo = TX_TIMEOUT;
3263 /* debug message level */
3264 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
3266 /* read and set MAC address */
3267 read_mac_address(ndev, pd->mac_addr);
3268 if (!is_valid_ether_addr(ndev->dev_addr)) {
3269 dev_warn(&pdev->dev,
3270 "no valid MAC address supplied, using a random one.\n");
3271 eth_hw_addr_random(ndev);
3275 int port = pdev->id < 0 ? 0 : pdev->id % 2;
3276 struct resource *rtsu;
3278 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
3280 dev_err(&pdev->dev, "no TSU resource\n");
3284 /* We can only request the TSU region for the first port
3285 * of the two sharing this TSU for the probe to succeed...
3288 !devm_request_mem_region(&pdev->dev, rtsu->start,
3289 resource_size(rtsu),
3290 dev_name(&pdev->dev))) {
3291 dev_err(&pdev->dev, "can't request TSU resource.\n");
3295 /* ioremap the TSU registers */
3296 mdp->tsu_addr = devm_ioremap(&pdev->dev, rtsu->start,
3297 resource_size(rtsu));
3298 if (!mdp->tsu_addr) {
3299 dev_err(&pdev->dev, "TSU region ioremap() failed.\n");
3304 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
3306 /* Need to init only the first port of the two sharing a TSU */
3308 if (mdp->cd->chip_reset)
3309 mdp->cd->chip_reset(ndev);
3311 /* TSU init (Init only)*/
3312 sh_eth_tsu_init(mdp);
3316 if (mdp->cd->rmiimode)
3317 sh_eth_write(ndev, 0x1, RMIIMODE);
3320 ret = sh_mdio_init(mdp, pd);
3322 if (ret != -EPROBE_DEFER)
3323 dev_err(&pdev->dev, "MDIO init failed: %d\n", ret);
3327 netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
3329 /* network device register */
3330 ret = register_netdev(ndev);
3335 device_set_wakeup_capable(&pdev->dev, 1);
3337 /* print device information */
3338 netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n",
3339 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
3341 pm_runtime_put(&pdev->dev);
3342 platform_set_drvdata(pdev, ndev);
3347 netif_napi_del(&mdp->napi);
3348 sh_mdio_release(mdp);
3354 pm_runtime_put(&pdev->dev);
3355 pm_runtime_disable(&pdev->dev);
3359 static int sh_eth_drv_remove(struct platform_device *pdev)
3361 struct net_device *ndev = platform_get_drvdata(pdev);
3362 struct sh_eth_private *mdp = netdev_priv(ndev);
3364 unregister_netdev(ndev);
3365 netif_napi_del(&mdp->napi);
3366 sh_mdio_release(mdp);
3367 pm_runtime_disable(&pdev->dev);
3374 #ifdef CONFIG_PM_SLEEP
3375 static int sh_eth_wol_setup(struct net_device *ndev)
3377 struct sh_eth_private *mdp = netdev_priv(ndev);
3379 /* Only allow ECI interrupts */
3380 synchronize_irq(ndev->irq);
3381 napi_disable(&mdp->napi);
3382 sh_eth_write(ndev, EESIPR_ECIIP, EESIPR);
3384 /* Enable MagicPacket */
3385 sh_eth_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE);
3387 return enable_irq_wake(ndev->irq);
3390 static int sh_eth_wol_restore(struct net_device *ndev)
3392 struct sh_eth_private *mdp = netdev_priv(ndev);
3395 napi_enable(&mdp->napi);
3397 /* Disable MagicPacket */
3398 sh_eth_modify(ndev, ECMR, ECMR_MPDE, 0);
3400 /* The device needs to be reset to restore MagicPacket logic
3401 * for next wakeup. If we close and open the device it will
3402 * both be reset and all registers restored. This is what
3403 * happens during suspend and resume without WoL enabled.
3405 ret = sh_eth_close(ndev);
3408 ret = sh_eth_open(ndev);
3412 return disable_irq_wake(ndev->irq);
3415 static int sh_eth_suspend(struct device *dev)
3417 struct net_device *ndev = dev_get_drvdata(dev);
3418 struct sh_eth_private *mdp = netdev_priv(ndev);
3421 if (!netif_running(ndev))
3424 netif_device_detach(ndev);
3426 if (mdp->wol_enabled)
3427 ret = sh_eth_wol_setup(ndev);
3429 ret = sh_eth_close(ndev);
3434 static int sh_eth_resume(struct device *dev)
3436 struct net_device *ndev = dev_get_drvdata(dev);
3437 struct sh_eth_private *mdp = netdev_priv(ndev);
3440 if (!netif_running(ndev))
3443 if (mdp->wol_enabled)
3444 ret = sh_eth_wol_restore(ndev);
3446 ret = sh_eth_open(ndev);
3451 netif_device_attach(ndev);
3457 static int sh_eth_runtime_nop(struct device *dev)
3459 /* Runtime PM callback shared between ->runtime_suspend()
3460 * and ->runtime_resume(). Simply returns success.
3462 * This driver re-initializes all registers after
3463 * pm_runtime_get_sync() anyway so there is no need
3464 * to save and restore registers here.
3469 static const struct dev_pm_ops sh_eth_dev_pm_ops = {
3470 SET_SYSTEM_SLEEP_PM_OPS(sh_eth_suspend, sh_eth_resume)
3471 SET_RUNTIME_PM_OPS(sh_eth_runtime_nop, sh_eth_runtime_nop, NULL)
3473 #define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
3475 #define SH_ETH_PM_OPS NULL
3478 static const struct platform_device_id sh_eth_id_table[] = {
3479 { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
3480 { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
3481 { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
3482 { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
3483 { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
3484 { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
3485 { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
3488 MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
3490 static struct platform_driver sh_eth_driver = {
3491 .probe = sh_eth_drv_probe,
3492 .remove = sh_eth_drv_remove,
3493 .id_table = sh_eth_id_table,
3496 .pm = SH_ETH_PM_OPS,
3497 .of_match_table = of_match_ptr(sh_eth_match_table),
3501 module_platform_driver(sh_eth_driver);
3503 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
3504 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
3505 MODULE_LICENSE("GPL v2");