1 /* Renesas Ethernet AVB device driver
3 * Copyright (C) 2014-2015 Renesas Electronics Corporation
4 * Copyright (C) 2015 Renesas Solutions Corp.
5 * Copyright (C) 2015 Cogent Embedded, Inc. <source@cogentembedded.com>
7 * Based on the SuperH Ethernet driver
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License version 2,
11 * as published by the Free Software Foundation.
14 #include <linux/cache.h>
15 #include <linux/clk.h>
16 #include <linux/delay.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/err.h>
19 #include <linux/etherdevice.h>
20 #include <linux/ethtool.h>
21 #include <linux/if_vlan.h>
22 #include <linux/kernel.h>
23 #include <linux/list.h>
24 #include <linux/module.h>
25 #include <linux/net_tstamp.h>
27 #include <linux/of_device.h>
28 #include <linux/of_irq.h>
29 #include <linux/of_mdio.h>
30 #include <linux/of_net.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/slab.h>
33 #include <linux/spinlock.h>
37 #define RAVB_DEF_MSG_ENABLE \
43 int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value)
47 for (i = 0; i < 10000; i++) {
48 if ((ravb_read(ndev, reg) & mask) == value)
55 static int ravb_config(struct net_device *ndev)
60 ravb_write(ndev, (ravb_read(ndev, CCC) & ~CCC_OPC) | CCC_OPC_CONFIG,
62 /* Check if the operating mode is changed to the config mode */
63 error = ravb_wait(ndev, CSR, CSR_OPS, CSR_OPS_CONFIG);
65 netdev_err(ndev, "failed to switch device to config mode\n");
70 static void ravb_set_duplex(struct net_device *ndev)
72 struct ravb_private *priv = netdev_priv(ndev);
73 u32 ecmr = ravb_read(ndev, ECMR);
75 if (priv->duplex) /* Full */
79 ravb_write(ndev, ecmr, ECMR);
82 static void ravb_set_rate(struct net_device *ndev)
84 struct ravb_private *priv = netdev_priv(ndev);
86 switch (priv->speed) {
87 case 100: /* 100BASE */
88 ravb_write(ndev, GECMR_SPEED_100, GECMR);
90 case 1000: /* 1000BASE */
91 ravb_write(ndev, GECMR_SPEED_1000, GECMR);
98 static void ravb_set_buffer_align(struct sk_buff *skb)
100 u32 reserve = (unsigned long)skb->data & (RAVB_ALIGN - 1);
103 skb_reserve(skb, RAVB_ALIGN - reserve);
106 /* Get MAC address from the MAC address registers
108 * Ethernet AVB device doesn't have ROM for MAC address.
109 * This function gets the MAC address that was used by a bootloader.
111 static void ravb_read_mac_address(struct net_device *ndev, const u8 *mac)
114 ether_addr_copy(ndev->dev_addr, mac);
116 ndev->dev_addr[0] = (ravb_read(ndev, MAHR) >> 24);
117 ndev->dev_addr[1] = (ravb_read(ndev, MAHR) >> 16) & 0xFF;
118 ndev->dev_addr[2] = (ravb_read(ndev, MAHR) >> 8) & 0xFF;
119 ndev->dev_addr[3] = (ravb_read(ndev, MAHR) >> 0) & 0xFF;
120 ndev->dev_addr[4] = (ravb_read(ndev, MALR) >> 8) & 0xFF;
121 ndev->dev_addr[5] = (ravb_read(ndev, MALR) >> 0) & 0xFF;
125 static void ravb_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set)
127 struct ravb_private *priv = container_of(ctrl, struct ravb_private,
129 u32 pir = ravb_read(priv->ndev, PIR);
135 ravb_write(priv->ndev, pir, PIR);
138 /* MDC pin control */
139 static void ravb_set_mdc(struct mdiobb_ctrl *ctrl, int level)
141 ravb_mdio_ctrl(ctrl, PIR_MDC, level);
144 /* Data I/O pin control */
145 static void ravb_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output)
147 ravb_mdio_ctrl(ctrl, PIR_MMD, output);
151 static void ravb_set_mdio_data(struct mdiobb_ctrl *ctrl, int value)
153 ravb_mdio_ctrl(ctrl, PIR_MDO, value);
157 static int ravb_get_mdio_data(struct mdiobb_ctrl *ctrl)
159 struct ravb_private *priv = container_of(ctrl, struct ravb_private,
162 return (ravb_read(priv->ndev, PIR) & PIR_MDI) != 0;
165 /* MDIO bus control struct */
166 static struct mdiobb_ops bb_ops = {
167 .owner = THIS_MODULE,
168 .set_mdc = ravb_set_mdc,
169 .set_mdio_dir = ravb_set_mdio_dir,
170 .set_mdio_data = ravb_set_mdio_data,
171 .get_mdio_data = ravb_get_mdio_data,
174 /* Free skb's and DMA buffers for Ethernet AVB */
175 static void ravb_ring_free(struct net_device *ndev, int q)
177 struct ravb_private *priv = netdev_priv(ndev);
181 /* Free RX skb ringbuffer */
182 if (priv->rx_skb[q]) {
183 for (i = 0; i < priv->num_rx_ring[q]; i++)
184 dev_kfree_skb(priv->rx_skb[q][i]);
186 kfree(priv->rx_skb[q]);
187 priv->rx_skb[q] = NULL;
189 /* Free TX skb ringbuffer */
190 if (priv->tx_skb[q]) {
191 for (i = 0; i < priv->num_tx_ring[q]; i++)
192 dev_kfree_skb(priv->tx_skb[q][i]);
194 kfree(priv->tx_skb[q]);
195 priv->tx_skb[q] = NULL;
197 /* Free aligned TX buffers */
198 kfree(priv->tx_align[q]);
199 priv->tx_align[q] = NULL;
201 if (priv->rx_ring[q]) {
202 ring_size = sizeof(struct ravb_ex_rx_desc) *
203 (priv->num_rx_ring[q] + 1);
204 dma_free_coherent(ndev->dev.parent, ring_size, priv->rx_ring[q],
205 priv->rx_desc_dma[q]);
206 priv->rx_ring[q] = NULL;
209 if (priv->tx_ring[q]) {
210 ring_size = sizeof(struct ravb_tx_desc) *
211 (priv->num_tx_ring[q] * NUM_TX_DESC + 1);
212 dma_free_coherent(ndev->dev.parent, ring_size, priv->tx_ring[q],
213 priv->tx_desc_dma[q]);
214 priv->tx_ring[q] = NULL;
218 /* Format skb and descriptor buffer for Ethernet AVB */
219 static void ravb_ring_format(struct net_device *ndev, int q)
221 struct ravb_private *priv = netdev_priv(ndev);
222 struct ravb_ex_rx_desc *rx_desc;
223 struct ravb_tx_desc *tx_desc;
224 struct ravb_desc *desc;
225 int rx_ring_size = sizeof(*rx_desc) * priv->num_rx_ring[q];
226 int tx_ring_size = sizeof(*tx_desc) * priv->num_tx_ring[q] *
233 priv->dirty_rx[q] = 0;
234 priv->dirty_tx[q] = 0;
236 memset(priv->rx_ring[q], 0, rx_ring_size);
237 /* Build RX ring buffer */
238 for (i = 0; i < priv->num_rx_ring[q]; i++) {
240 rx_desc = &priv->rx_ring[q][i];
241 /* The size of the buffer should be on 16-byte boundary. */
242 rx_desc->ds_cc = cpu_to_le16(ALIGN(PKT_BUF_SZ, 16));
243 dma_addr = dma_map_single(ndev->dev.parent, priv->rx_skb[q][i]->data,
244 ALIGN(PKT_BUF_SZ, 16),
246 /* We just set the data size to 0 for a failed mapping which
247 * should prevent DMA from happening...
249 if (dma_mapping_error(ndev->dev.parent, dma_addr))
250 rx_desc->ds_cc = cpu_to_le16(0);
251 rx_desc->dptr = cpu_to_le32(dma_addr);
252 rx_desc->die_dt = DT_FEMPTY;
254 rx_desc = &priv->rx_ring[q][i];
255 rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]);
256 rx_desc->die_dt = DT_LINKFIX; /* type */
258 memset(priv->tx_ring[q], 0, tx_ring_size);
259 /* Build TX ring buffer */
260 for (i = 0, tx_desc = priv->tx_ring[q]; i < priv->num_tx_ring[q];
262 tx_desc->die_dt = DT_EEMPTY;
264 tx_desc->die_dt = DT_EEMPTY;
266 tx_desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]);
267 tx_desc->die_dt = DT_LINKFIX; /* type */
269 /* RX descriptor base address for best effort */
270 desc = &priv->desc_bat[RX_QUEUE_OFFSET + q];
271 desc->die_dt = DT_LINKFIX; /* type */
272 desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]);
274 /* TX descriptor base address for best effort */
275 desc = &priv->desc_bat[q];
276 desc->die_dt = DT_LINKFIX; /* type */
277 desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]);
280 /* Init skb and descriptor buffer for Ethernet AVB */
281 static int ravb_ring_init(struct net_device *ndev, int q)
283 struct ravb_private *priv = netdev_priv(ndev);
288 /* Allocate RX and TX skb rings */
289 priv->rx_skb[q] = kcalloc(priv->num_rx_ring[q],
290 sizeof(*priv->rx_skb[q]), GFP_KERNEL);
291 priv->tx_skb[q] = kcalloc(priv->num_tx_ring[q],
292 sizeof(*priv->tx_skb[q]), GFP_KERNEL);
293 if (!priv->rx_skb[q] || !priv->tx_skb[q])
296 for (i = 0; i < priv->num_rx_ring[q]; i++) {
297 skb = netdev_alloc_skb(ndev, PKT_BUF_SZ + RAVB_ALIGN - 1);
300 ravb_set_buffer_align(skb);
301 priv->rx_skb[q][i] = skb;
304 /* Allocate rings for the aligned buffers */
305 priv->tx_align[q] = kmalloc(DPTR_ALIGN * priv->num_tx_ring[q] +
306 DPTR_ALIGN - 1, GFP_KERNEL);
307 if (!priv->tx_align[q])
310 /* Allocate all RX descriptors. */
311 ring_size = sizeof(struct ravb_ex_rx_desc) * (priv->num_rx_ring[q] + 1);
312 priv->rx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size,
313 &priv->rx_desc_dma[q],
315 if (!priv->rx_ring[q])
318 priv->dirty_rx[q] = 0;
320 /* Allocate all TX descriptors. */
321 ring_size = sizeof(struct ravb_tx_desc) *
322 (priv->num_tx_ring[q] * NUM_TX_DESC + 1);
323 priv->tx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size,
324 &priv->tx_desc_dma[q],
326 if (!priv->tx_ring[q])
332 ravb_ring_free(ndev, q);
337 /* E-MAC init function */
338 static void ravb_emac_init(struct net_device *ndev)
340 struct ravb_private *priv = netdev_priv(ndev);
343 /* Receive frame limit set register */
344 ravb_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, RFLR);
346 /* PAUSE prohibition */
347 ecmr = ravb_read(ndev, ECMR);
349 ecmr |= ECMR_ZPF | (priv->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
350 ravb_write(ndev, ecmr, ECMR);
354 /* Set MAC address */
356 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
357 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
359 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
361 ravb_write(ndev, 1, MPR);
363 /* E-MAC status register clear */
364 ravb_write(ndev, ECSR_ICD | ECSR_MPD, ECSR);
366 /* E-MAC interrupt enable register */
367 ravb_write(ndev, ECSIPR_ICDIP | ECSIPR_MPDIP | ECSIPR_LCHNGIP, ECSIPR);
370 /* Device init function for Ethernet AVB */
371 static int ravb_dmac_init(struct net_device *ndev)
375 /* Set CONFIG mode */
376 error = ravb_config(ndev);
380 error = ravb_ring_init(ndev, RAVB_BE);
383 error = ravb_ring_init(ndev, RAVB_NC);
385 ravb_ring_free(ndev, RAVB_BE);
389 /* Descriptor format */
390 ravb_ring_format(ndev, RAVB_BE);
391 ravb_ring_format(ndev, RAVB_NC);
393 #if defined(__LITTLE_ENDIAN)
394 ravb_write(ndev, ravb_read(ndev, CCC) & ~CCC_BOC, CCC);
396 ravb_write(ndev, ravb_read(ndev, CCC) | CCC_BOC, CCC);
400 ravb_write(ndev, RCR_EFFS | RCR_ENCF | RCR_ETS0 | 0x18000000, RCR);
403 ravb_write(ndev, TGC_TQP_AVBMODE1 | 0x00222200, TGC);
405 /* Timestamp enable */
406 ravb_write(ndev, TCCR_TFEN, TCCR);
408 /* Interrupt enable: */
410 ravb_write(ndev, RIC0_FRE0 | RIC0_FRE1, RIC0);
411 /* Receive FIFO full error, descriptor empty */
412 ravb_write(ndev, RIC2_QFE0 | RIC2_QFE1 | RIC2_RFFE, RIC2);
413 /* Frame transmitted, timestamp FIFO updated */
414 ravb_write(ndev, TIC_FTE0 | TIC_FTE1 | TIC_TFUE, TIC);
416 /* Setting the control will start the AVB-DMAC process. */
417 ravb_write(ndev, (ravb_read(ndev, CCC) & ~CCC_OPC) | CCC_OPC_OPERATION,
423 /* Free TX skb function for AVB-IP */
424 static int ravb_tx_free(struct net_device *ndev, int q)
426 struct ravb_private *priv = netdev_priv(ndev);
427 struct net_device_stats *stats = &priv->stats[q];
428 struct ravb_tx_desc *desc;
433 for (; priv->cur_tx[q] - priv->dirty_tx[q] > 0; priv->dirty_tx[q]++) {
434 entry = priv->dirty_tx[q] % (priv->num_tx_ring[q] *
436 desc = &priv->tx_ring[q][entry];
437 if (desc->die_dt != DT_FEMPTY)
439 /* Descriptor type must be checked before all other reads */
441 size = le16_to_cpu(desc->ds_tagl) & TX_DS;
442 /* Free the original skb. */
443 if (priv->tx_skb[q][entry / NUM_TX_DESC]) {
444 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
445 size, DMA_TO_DEVICE);
446 /* Last packet descriptor? */
447 if (entry % NUM_TX_DESC == NUM_TX_DESC - 1) {
448 entry /= NUM_TX_DESC;
449 dev_kfree_skb_any(priv->tx_skb[q][entry]);
450 priv->tx_skb[q][entry] = NULL;
455 stats->tx_bytes += size;
456 desc->die_dt = DT_EEMPTY;
461 static void ravb_get_tx_tstamp(struct net_device *ndev)
463 struct ravb_private *priv = netdev_priv(ndev);
464 struct ravb_tstamp_skb *ts_skb, *ts_skb2;
465 struct skb_shared_hwtstamps shhwtstamps;
467 struct timespec64 ts;
472 count = (ravb_read(ndev, TSR) & TSR_TFFL) >> 8;
474 tfa2 = ravb_read(ndev, TFA2);
475 tfa_tag = (tfa2 & TFA2_TST) >> 16;
476 ts.tv_nsec = (u64)ravb_read(ndev, TFA0);
477 ts.tv_sec = ((u64)(tfa2 & TFA2_TSV) << 32) |
478 ravb_read(ndev, TFA1);
479 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
480 shhwtstamps.hwtstamp = timespec64_to_ktime(ts);
481 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list,
485 list_del(&ts_skb->list);
487 if (tag == tfa_tag) {
488 skb_tstamp_tx(skb, &shhwtstamps);
492 ravb_write(ndev, ravb_read(ndev, TCCR) | TCCR_TFR, TCCR);
496 /* Packet receive function for Ethernet AVB */
497 static bool ravb_rx(struct net_device *ndev, int *quota, int q)
499 struct ravb_private *priv = netdev_priv(ndev);
500 int entry = priv->cur_rx[q] % priv->num_rx_ring[q];
501 int boguscnt = (priv->dirty_rx[q] + priv->num_rx_ring[q]) -
503 struct net_device_stats *stats = &priv->stats[q];
504 struct ravb_ex_rx_desc *desc;
507 struct timespec64 ts;
512 boguscnt = min(boguscnt, *quota);
514 desc = &priv->rx_ring[q][entry];
515 while (desc->die_dt != DT_FEMPTY) {
516 /* Descriptor type must be checked before all other reads */
518 desc_status = desc->msc;
519 pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS;
524 /* We use 0-byte descriptors to mark the DMA mapping errors */
528 if (desc_status & MSC_MC)
531 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF |
534 if (desc_status & MSC_CRC)
535 stats->rx_crc_errors++;
536 if (desc_status & MSC_RFE)
537 stats->rx_frame_errors++;
538 if (desc_status & (MSC_RTLF | MSC_RTSF))
539 stats->rx_length_errors++;
540 if (desc_status & MSC_CEEF)
541 stats->rx_missed_errors++;
543 u32 get_ts = priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE;
545 skb = priv->rx_skb[q][entry];
546 priv->rx_skb[q][entry] = NULL;
547 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
548 ALIGN(PKT_BUF_SZ, 16),
550 get_ts &= (q == RAVB_NC) ?
551 RAVB_RXTSTAMP_TYPE_V2_L2_EVENT :
552 ~RAVB_RXTSTAMP_TYPE_V2_L2_EVENT;
554 struct skb_shared_hwtstamps *shhwtstamps;
556 shhwtstamps = skb_hwtstamps(skb);
557 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
558 ts.tv_sec = ((u64) le16_to_cpu(desc->ts_sh) <<
559 32) | le32_to_cpu(desc->ts_sl);
560 ts.tv_nsec = le32_to_cpu(desc->ts_n);
561 shhwtstamps->hwtstamp = timespec64_to_ktime(ts);
563 skb_put(skb, pkt_len);
564 skb->protocol = eth_type_trans(skb, ndev);
565 napi_gro_receive(&priv->napi[q], skb);
567 stats->rx_bytes += pkt_len;
570 entry = (++priv->cur_rx[q]) % priv->num_rx_ring[q];
571 desc = &priv->rx_ring[q][entry];
574 /* Refill the RX ring buffers. */
575 for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) {
576 entry = priv->dirty_rx[q] % priv->num_rx_ring[q];
577 desc = &priv->rx_ring[q][entry];
578 /* The size of the buffer should be on 16-byte boundary. */
579 desc->ds_cc = cpu_to_le16(ALIGN(PKT_BUF_SZ, 16));
581 if (!priv->rx_skb[q][entry]) {
582 skb = netdev_alloc_skb(ndev,
583 PKT_BUF_SZ + RAVB_ALIGN - 1);
585 break; /* Better luck next round. */
586 ravb_set_buffer_align(skb);
587 dma_addr = dma_map_single(ndev->dev.parent, skb->data,
588 le16_to_cpu(desc->ds_cc),
590 skb_checksum_none_assert(skb);
591 /* We just set the data size to 0 for a failed mapping
592 * which should prevent DMA from happening...
594 if (dma_mapping_error(ndev->dev.parent, dma_addr))
595 desc->ds_cc = cpu_to_le16(0);
596 desc->dptr = cpu_to_le32(dma_addr);
597 priv->rx_skb[q][entry] = skb;
599 /* Descriptor type must be set after all the above writes */
601 desc->die_dt = DT_FEMPTY;
604 *quota -= limit - (++boguscnt);
606 return boguscnt <= 0;
609 static void ravb_rcv_snd_disable(struct net_device *ndev)
611 /* Disable TX and RX */
612 ravb_write(ndev, ravb_read(ndev, ECMR) & ~(ECMR_RE | ECMR_TE), ECMR);
615 static void ravb_rcv_snd_enable(struct net_device *ndev)
617 /* Enable TX and RX */
618 ravb_write(ndev, ravb_read(ndev, ECMR) | ECMR_RE | ECMR_TE, ECMR);
621 /* function for waiting dma process finished */
622 static int ravb_stop_dma(struct net_device *ndev)
626 /* Wait for stopping the hardware TX process */
627 error = ravb_wait(ndev, TCCR,
628 TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 0);
632 error = ravb_wait(ndev, CSR, CSR_TPO0 | CSR_TPO1 | CSR_TPO2 | CSR_TPO3,
637 /* Stop the E-MAC's RX/TX processes. */
638 ravb_rcv_snd_disable(ndev);
640 /* Wait for stopping the RX DMA process */
641 error = ravb_wait(ndev, CSR, CSR_RPO, 0);
645 /* Stop AVB-DMAC process */
646 return ravb_config(ndev);
649 /* E-MAC interrupt handler */
650 static void ravb_emac_interrupt(struct net_device *ndev)
652 struct ravb_private *priv = netdev_priv(ndev);
655 ecsr = ravb_read(ndev, ECSR);
656 ravb_write(ndev, ecsr, ECSR); /* clear interrupt */
658 ndev->stats.tx_carrier_errors++;
659 if (ecsr & ECSR_LCHNG) {
661 if (priv->no_avb_link)
663 psr = ravb_read(ndev, PSR);
664 if (priv->avb_link_active_low)
666 if (!(psr & PSR_LMON)) {
667 /* DIsable RX and TX */
668 ravb_rcv_snd_disable(ndev);
670 /* Enable RX and TX */
671 ravb_rcv_snd_enable(ndev);
676 /* Error interrupt handler */
677 static void ravb_error_interrupt(struct net_device *ndev)
679 struct ravb_private *priv = netdev_priv(ndev);
682 eis = ravb_read(ndev, EIS);
683 ravb_write(ndev, ~EIS_QFS, EIS);
685 ris2 = ravb_read(ndev, RIS2);
686 ravb_write(ndev, ~(RIS2_QFF0 | RIS2_RFFF), RIS2);
688 /* Receive Descriptor Empty int */
689 if (ris2 & RIS2_QFF0)
690 priv->stats[RAVB_BE].rx_over_errors++;
692 /* Receive Descriptor Empty int */
693 if (ris2 & RIS2_QFF1)
694 priv->stats[RAVB_NC].rx_over_errors++;
696 /* Receive FIFO Overflow int */
697 if (ris2 & RIS2_RFFF)
698 priv->rx_fifo_errors++;
702 static irqreturn_t ravb_interrupt(int irq, void *dev_id)
704 struct net_device *ndev = dev_id;
705 struct ravb_private *priv = netdev_priv(ndev);
706 irqreturn_t result = IRQ_NONE;
709 spin_lock(&priv->lock);
710 /* Get interrupt status */
711 iss = ravb_read(ndev, ISS);
713 /* Received and transmitted interrupts */
714 if (iss & (ISS_FRS | ISS_FTS | ISS_TFUS)) {
715 u32 ris0 = ravb_read(ndev, RIS0);
716 u32 ric0 = ravb_read(ndev, RIC0);
717 u32 tis = ravb_read(ndev, TIS);
718 u32 tic = ravb_read(ndev, TIC);
721 /* Timestamp updated */
722 if (tis & TIS_TFUF) {
723 ravb_write(ndev, ~TIS_TFUF, TIS);
724 ravb_get_tx_tstamp(ndev);
725 result = IRQ_HANDLED;
728 /* Network control and best effort queue RX/TX */
729 for (q = RAVB_NC; q >= RAVB_BE; q--) {
730 if (((ris0 & ric0) & BIT(q)) ||
731 ((tis & tic) & BIT(q))) {
732 if (napi_schedule_prep(&priv->napi[q])) {
733 /* Mask RX and TX interrupts */
736 ravb_write(ndev, ric0, RIC0);
737 ravb_write(ndev, tic, TIC);
738 __napi_schedule(&priv->napi[q]);
741 "ignoring interrupt, rx status 0x%08x, rx mask 0x%08x,\n",
744 " tx status 0x%08x, tx mask 0x%08x.\n",
747 result = IRQ_HANDLED;
752 /* E-MAC status summary */
754 ravb_emac_interrupt(ndev);
755 result = IRQ_HANDLED;
758 /* Error status summary */
760 ravb_error_interrupt(ndev);
761 result = IRQ_HANDLED;
765 result = ravb_ptp_interrupt(ndev);
768 spin_unlock(&priv->lock);
772 static int ravb_poll(struct napi_struct *napi, int budget)
774 struct net_device *ndev = napi->dev;
775 struct ravb_private *priv = netdev_priv(ndev);
777 int q = napi - priv->napi;
783 tis = ravb_read(ndev, TIS);
784 ris0 = ravb_read(ndev, RIS0);
785 if (!((ris0 & mask) || (tis & mask)))
788 /* Processing RX Descriptor Ring */
790 /* Clear RX interrupt */
791 ravb_write(ndev, ~mask, RIS0);
792 if (ravb_rx(ndev, "a, q))
795 /* Processing TX Descriptor Ring */
797 spin_lock_irqsave(&priv->lock, flags);
798 /* Clear TX interrupt */
799 ravb_write(ndev, ~mask, TIS);
800 ravb_tx_free(ndev, q);
801 netif_wake_subqueue(ndev, q);
803 spin_unlock_irqrestore(&priv->lock, flags);
809 /* Re-enable RX/TX interrupts */
810 spin_lock_irqsave(&priv->lock, flags);
811 ravb_write(ndev, ravb_read(ndev, RIC0) | mask, RIC0);
812 ravb_write(ndev, ravb_read(ndev, TIC) | mask, TIC);
814 spin_unlock_irqrestore(&priv->lock, flags);
816 /* Receive error message handling */
817 priv->rx_over_errors = priv->stats[RAVB_BE].rx_over_errors;
818 priv->rx_over_errors += priv->stats[RAVB_NC].rx_over_errors;
819 if (priv->rx_over_errors != ndev->stats.rx_over_errors) {
820 ndev->stats.rx_over_errors = priv->rx_over_errors;
821 netif_err(priv, rx_err, ndev, "Receive Descriptor Empty\n");
823 if (priv->rx_fifo_errors != ndev->stats.rx_fifo_errors) {
824 ndev->stats.rx_fifo_errors = priv->rx_fifo_errors;
825 netif_err(priv, rx_err, ndev, "Receive FIFO Overflow\n");
828 return budget - quota;
831 /* PHY state control function */
832 static void ravb_adjust_link(struct net_device *ndev)
834 struct ravb_private *priv = netdev_priv(ndev);
835 struct phy_device *phydev = priv->phydev;
836 bool new_state = false;
839 if (phydev->duplex != priv->duplex) {
841 priv->duplex = phydev->duplex;
842 ravb_set_duplex(ndev);
845 if (phydev->speed != priv->speed) {
847 priv->speed = phydev->speed;
851 ravb_write(ndev, ravb_read(ndev, ECMR) & ~ECMR_TXF,
854 priv->link = phydev->link;
855 if (priv->no_avb_link)
856 ravb_rcv_snd_enable(ndev);
858 } else if (priv->link) {
863 if (priv->no_avb_link)
864 ravb_rcv_snd_disable(ndev);
867 if (new_state && netif_msg_link(priv))
868 phy_print_status(phydev);
871 /* PHY init function */
872 static int ravb_phy_init(struct net_device *ndev)
874 struct device_node *np = ndev->dev.parent->of_node;
875 struct ravb_private *priv = netdev_priv(ndev);
876 struct phy_device *phydev;
877 struct device_node *pn;
883 /* Try connecting to PHY */
884 pn = of_parse_phandle(np, "phy-handle", 0);
885 phydev = of_phy_connect(ndev, pn, ravb_adjust_link, 0,
886 priv->phy_interface);
888 netdev_err(ndev, "failed to connect PHY\n");
892 /* This driver only support 10/100Mbit speeds on Gen3
895 if (priv->chip_id == RCAR_GEN3) {
898 err = phy_set_max_speed(phydev, SPEED_100);
900 netdev_err(ndev, "failed to limit PHY to 100Mbit/s\n");
901 phy_disconnect(phydev);
905 netdev_info(ndev, "limited PHY to 100Mbit/s\n");
908 netdev_info(ndev, "attached PHY %d (IRQ %d) to driver %s\n",
909 phydev->addr, phydev->irq, phydev->drv->name);
911 priv->phydev = phydev;
916 /* PHY control start function */
917 static int ravb_phy_start(struct net_device *ndev)
919 struct ravb_private *priv = netdev_priv(ndev);
922 error = ravb_phy_init(ndev);
926 phy_start(priv->phydev);
931 static int ravb_get_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
933 struct ravb_private *priv = netdev_priv(ndev);
938 spin_lock_irqsave(&priv->lock, flags);
939 error = phy_ethtool_gset(priv->phydev, ecmd);
940 spin_unlock_irqrestore(&priv->lock, flags);
946 static int ravb_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
948 struct ravb_private *priv = netdev_priv(ndev);
955 spin_lock_irqsave(&priv->lock, flags);
957 /* Disable TX and RX */
958 ravb_rcv_snd_disable(ndev);
960 error = phy_ethtool_sset(priv->phydev, ecmd);
964 if (ecmd->duplex == DUPLEX_FULL)
969 ravb_set_duplex(ndev);
974 /* Enable TX and RX */
975 ravb_rcv_snd_enable(ndev);
978 spin_unlock_irqrestore(&priv->lock, flags);
983 static int ravb_nway_reset(struct net_device *ndev)
985 struct ravb_private *priv = netdev_priv(ndev);
990 spin_lock_irqsave(&priv->lock, flags);
991 error = phy_start_aneg(priv->phydev);
992 spin_unlock_irqrestore(&priv->lock, flags);
998 static u32 ravb_get_msglevel(struct net_device *ndev)
1000 struct ravb_private *priv = netdev_priv(ndev);
1002 return priv->msg_enable;
1005 static void ravb_set_msglevel(struct net_device *ndev, u32 value)
1007 struct ravb_private *priv = netdev_priv(ndev);
1009 priv->msg_enable = value;
1012 static const char ravb_gstrings_stats[][ETH_GSTRING_LEN] = {
1013 "rx_queue_0_current",
1014 "tx_queue_0_current",
1017 "rx_queue_0_packets",
1018 "tx_queue_0_packets",
1021 "rx_queue_0_mcast_packets",
1022 "rx_queue_0_errors",
1023 "rx_queue_0_crc_errors",
1024 "rx_queue_0_frame_errors",
1025 "rx_queue_0_length_errors",
1026 "rx_queue_0_missed_errors",
1027 "rx_queue_0_over_errors",
1029 "rx_queue_1_current",
1030 "tx_queue_1_current",
1033 "rx_queue_1_packets",
1034 "tx_queue_1_packets",
1037 "rx_queue_1_mcast_packets",
1038 "rx_queue_1_errors",
1039 "rx_queue_1_crc_errors",
1040 "rx_queue_1_frame_errors_",
1041 "rx_queue_1_length_errors",
1042 "rx_queue_1_missed_errors",
1043 "rx_queue_1_over_errors",
1046 #define RAVB_STATS_LEN ARRAY_SIZE(ravb_gstrings_stats)
1048 static int ravb_get_sset_count(struct net_device *netdev, int sset)
1052 return RAVB_STATS_LEN;
1058 static void ravb_get_ethtool_stats(struct net_device *ndev,
1059 struct ethtool_stats *stats, u64 *data)
1061 struct ravb_private *priv = netdev_priv(ndev);
1065 /* Device-specific stats */
1066 for (q = RAVB_BE; q < NUM_RX_QUEUE; q++) {
1067 struct net_device_stats *stats = &priv->stats[q];
1069 data[i++] = priv->cur_rx[q];
1070 data[i++] = priv->cur_tx[q];
1071 data[i++] = priv->dirty_rx[q];
1072 data[i++] = priv->dirty_tx[q];
1073 data[i++] = stats->rx_packets;
1074 data[i++] = stats->tx_packets;
1075 data[i++] = stats->rx_bytes;
1076 data[i++] = stats->tx_bytes;
1077 data[i++] = stats->multicast;
1078 data[i++] = stats->rx_errors;
1079 data[i++] = stats->rx_crc_errors;
1080 data[i++] = stats->rx_frame_errors;
1081 data[i++] = stats->rx_length_errors;
1082 data[i++] = stats->rx_missed_errors;
1083 data[i++] = stats->rx_over_errors;
1087 static void ravb_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1089 switch (stringset) {
1091 memcpy(data, *ravb_gstrings_stats, sizeof(ravb_gstrings_stats));
1096 static void ravb_get_ringparam(struct net_device *ndev,
1097 struct ethtool_ringparam *ring)
1099 struct ravb_private *priv = netdev_priv(ndev);
1101 ring->rx_max_pending = BE_RX_RING_MAX;
1102 ring->tx_max_pending = BE_TX_RING_MAX;
1103 ring->rx_pending = priv->num_rx_ring[RAVB_BE];
1104 ring->tx_pending = priv->num_tx_ring[RAVB_BE];
1107 static int ravb_set_ringparam(struct net_device *ndev,
1108 struct ethtool_ringparam *ring)
1110 struct ravb_private *priv = netdev_priv(ndev);
1113 if (ring->tx_pending > BE_TX_RING_MAX ||
1114 ring->rx_pending > BE_RX_RING_MAX ||
1115 ring->tx_pending < BE_TX_RING_MIN ||
1116 ring->rx_pending < BE_RX_RING_MIN)
1118 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
1121 if (netif_running(ndev)) {
1122 netif_device_detach(ndev);
1123 /* Stop PTP Clock driver */
1124 ravb_ptp_stop(ndev);
1125 /* Wait for DMA stopping */
1126 error = ravb_stop_dma(ndev);
1129 "cannot set ringparam! Any AVB processes are still running?\n");
1132 synchronize_irq(ndev->irq);
1134 /* Free all the skb's in the RX queue and the DMA buffers. */
1135 ravb_ring_free(ndev, RAVB_BE);
1136 ravb_ring_free(ndev, RAVB_NC);
1139 /* Set new parameters */
1140 priv->num_rx_ring[RAVB_BE] = ring->rx_pending;
1141 priv->num_tx_ring[RAVB_BE] = ring->tx_pending;
1143 if (netif_running(ndev)) {
1144 error = ravb_dmac_init(ndev);
1147 "%s: ravb_dmac_init() failed, error %d\n",
1152 ravb_emac_init(ndev);
1154 /* Initialise PTP Clock driver */
1155 ravb_ptp_init(ndev, priv->pdev);
1157 netif_device_attach(ndev);
1163 static int ravb_get_ts_info(struct net_device *ndev,
1164 struct ethtool_ts_info *info)
1166 struct ravb_private *priv = netdev_priv(ndev);
1168 info->so_timestamping =
1169 SOF_TIMESTAMPING_TX_SOFTWARE |
1170 SOF_TIMESTAMPING_RX_SOFTWARE |
1171 SOF_TIMESTAMPING_SOFTWARE |
1172 SOF_TIMESTAMPING_TX_HARDWARE |
1173 SOF_TIMESTAMPING_RX_HARDWARE |
1174 SOF_TIMESTAMPING_RAW_HARDWARE;
1175 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
1177 (1 << HWTSTAMP_FILTER_NONE) |
1178 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
1179 (1 << HWTSTAMP_FILTER_ALL);
1180 info->phc_index = ptp_clock_index(priv->ptp.clock);
1185 static const struct ethtool_ops ravb_ethtool_ops = {
1186 .get_settings = ravb_get_settings,
1187 .set_settings = ravb_set_settings,
1188 .nway_reset = ravb_nway_reset,
1189 .get_msglevel = ravb_get_msglevel,
1190 .set_msglevel = ravb_set_msglevel,
1191 .get_link = ethtool_op_get_link,
1192 .get_strings = ravb_get_strings,
1193 .get_ethtool_stats = ravb_get_ethtool_stats,
1194 .get_sset_count = ravb_get_sset_count,
1195 .get_ringparam = ravb_get_ringparam,
1196 .set_ringparam = ravb_set_ringparam,
1197 .get_ts_info = ravb_get_ts_info,
1200 /* Network device open function for Ethernet AVB */
1201 static int ravb_open(struct net_device *ndev)
1203 struct ravb_private *priv = netdev_priv(ndev);
1206 napi_enable(&priv->napi[RAVB_BE]);
1207 napi_enable(&priv->napi[RAVB_NC]);
1209 error = request_irq(ndev->irq, ravb_interrupt, IRQF_SHARED, ndev->name,
1212 netdev_err(ndev, "cannot request IRQ\n");
1216 if (priv->chip_id == RCAR_GEN3) {
1217 error = request_irq(priv->emac_irq, ravb_interrupt,
1218 IRQF_SHARED, ndev->name, ndev);
1220 netdev_err(ndev, "cannot request IRQ\n");
1226 error = ravb_dmac_init(ndev);
1229 ravb_emac_init(ndev);
1231 /* Initialise PTP Clock driver */
1232 ravb_ptp_init(ndev, priv->pdev);
1234 netif_tx_start_all_queues(ndev);
1236 /* PHY control start */
1237 error = ravb_phy_start(ndev);
1244 /* Stop PTP Clock driver */
1245 ravb_ptp_stop(ndev);
1247 free_irq(ndev->irq, ndev);
1248 free_irq(priv->emac_irq, ndev);
1250 napi_disable(&priv->napi[RAVB_NC]);
1251 napi_disable(&priv->napi[RAVB_BE]);
1255 /* Timeout function for Ethernet AVB */
1256 static void ravb_tx_timeout(struct net_device *ndev)
1258 struct ravb_private *priv = netdev_priv(ndev);
1260 netif_err(priv, tx_err, ndev,
1261 "transmit timed out, status %08x, resetting...\n",
1262 ravb_read(ndev, ISS));
1264 /* tx_errors count up */
1265 ndev->stats.tx_errors++;
1267 schedule_work(&priv->work);
1270 static void ravb_tx_timeout_work(struct work_struct *work)
1272 struct ravb_private *priv = container_of(work, struct ravb_private,
1274 struct net_device *ndev = priv->ndev;
1276 netif_tx_stop_all_queues(ndev);
1278 /* Stop PTP Clock driver */
1279 ravb_ptp_stop(ndev);
1281 /* Wait for DMA stopping */
1282 ravb_stop_dma(ndev);
1284 ravb_ring_free(ndev, RAVB_BE);
1285 ravb_ring_free(ndev, RAVB_NC);
1288 ravb_dmac_init(ndev);
1289 ravb_emac_init(ndev);
1291 /* Initialise PTP Clock driver */
1292 ravb_ptp_init(ndev, priv->pdev);
1294 netif_tx_start_all_queues(ndev);
1297 /* Packet transmit function for Ethernet AVB */
1298 static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1300 struct ravb_private *priv = netdev_priv(ndev);
1301 u16 q = skb_get_queue_mapping(skb);
1302 struct ravb_tstamp_skb *ts_skb;
1303 struct ravb_tx_desc *desc;
1304 unsigned long flags;
1310 spin_lock_irqsave(&priv->lock, flags);
1311 if (priv->cur_tx[q] - priv->dirty_tx[q] > (priv->num_tx_ring[q] - 1) *
1313 netif_err(priv, tx_queued, ndev,
1314 "still transmitting with the full ring!\n");
1315 netif_stop_subqueue(ndev, q);
1316 spin_unlock_irqrestore(&priv->lock, flags);
1317 return NETDEV_TX_BUSY;
1319 entry = priv->cur_tx[q] % (priv->num_tx_ring[q] * NUM_TX_DESC);
1320 priv->tx_skb[q][entry / NUM_TX_DESC] = skb;
1322 if (skb_put_padto(skb, ETH_ZLEN))
1325 buffer = PTR_ALIGN(priv->tx_align[q], DPTR_ALIGN) +
1326 entry / NUM_TX_DESC * DPTR_ALIGN;
1327 len = PTR_ALIGN(skb->data, DPTR_ALIGN) - skb->data;
1328 memcpy(buffer, skb->data, len);
1329 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, DMA_TO_DEVICE);
1330 if (dma_mapping_error(ndev->dev.parent, dma_addr))
1333 desc = &priv->tx_ring[q][entry];
1334 desc->ds_tagl = cpu_to_le16(len);
1335 desc->dptr = cpu_to_le32(dma_addr);
1337 buffer = skb->data + len;
1338 len = skb->len - len;
1339 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, DMA_TO_DEVICE);
1340 if (dma_mapping_error(ndev->dev.parent, dma_addr))
1344 desc->ds_tagl = cpu_to_le16(len);
1345 desc->dptr = cpu_to_le32(dma_addr);
1347 /* TX timestamp required */
1349 ts_skb = kmalloc(sizeof(*ts_skb), GFP_ATOMIC);
1352 dma_unmap_single(ndev->dev.parent, dma_addr, len,
1357 ts_skb->tag = priv->ts_skb_tag++;
1358 priv->ts_skb_tag &= 0x3ff;
1359 list_add_tail(&ts_skb->list, &priv->ts_skb_list);
1361 /* TAG and timestamp required flag */
1362 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1363 skb_tx_timestamp(skb);
1364 desc->tagh_tsr = (ts_skb->tag >> 4) | TX_TSR;
1365 desc->ds_tagl |= le16_to_cpu(ts_skb->tag << 12);
1368 /* Descriptor type must be set after all the above writes */
1370 desc->die_dt = DT_FEND;
1372 desc->die_dt = DT_FSTART;
1374 ravb_write(ndev, ravb_read(ndev, TCCR) | (TCCR_TSRQ0 << q), TCCR);
1376 priv->cur_tx[q] += NUM_TX_DESC;
1377 if (priv->cur_tx[q] - priv->dirty_tx[q] >
1378 (priv->num_tx_ring[q] - 1) * NUM_TX_DESC && !ravb_tx_free(ndev, q))
1379 netif_stop_subqueue(ndev, q);
1383 spin_unlock_irqrestore(&priv->lock, flags);
1384 return NETDEV_TX_OK;
1387 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
1388 le16_to_cpu(desc->ds_tagl), DMA_TO_DEVICE);
1390 dev_kfree_skb_any(skb);
1391 priv->tx_skb[q][entry / NUM_TX_DESC] = NULL;
1395 static u16 ravb_select_queue(struct net_device *ndev, struct sk_buff *skb,
1396 void *accel_priv, select_queue_fallback_t fallback)
1398 /* If skb needs TX timestamp, it is handled in network control queue */
1399 return (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) ? RAVB_NC :
1404 static struct net_device_stats *ravb_get_stats(struct net_device *ndev)
1406 struct ravb_private *priv = netdev_priv(ndev);
1407 struct net_device_stats *nstats, *stats0, *stats1;
1409 nstats = &ndev->stats;
1410 stats0 = &priv->stats[RAVB_BE];
1411 stats1 = &priv->stats[RAVB_NC];
1413 nstats->tx_dropped += ravb_read(ndev, TROCR);
1414 ravb_write(ndev, 0, TROCR); /* (write clear) */
1415 nstats->collisions += ravb_read(ndev, CDCR);
1416 ravb_write(ndev, 0, CDCR); /* (write clear) */
1417 nstats->tx_carrier_errors += ravb_read(ndev, LCCR);
1418 ravb_write(ndev, 0, LCCR); /* (write clear) */
1420 nstats->tx_carrier_errors += ravb_read(ndev, CERCR);
1421 ravb_write(ndev, 0, CERCR); /* (write clear) */
1422 nstats->tx_carrier_errors += ravb_read(ndev, CEECR);
1423 ravb_write(ndev, 0, CEECR); /* (write clear) */
1425 nstats->rx_packets = stats0->rx_packets + stats1->rx_packets;
1426 nstats->tx_packets = stats0->tx_packets + stats1->tx_packets;
1427 nstats->rx_bytes = stats0->rx_bytes + stats1->rx_bytes;
1428 nstats->tx_bytes = stats0->tx_bytes + stats1->tx_bytes;
1429 nstats->multicast = stats0->multicast + stats1->multicast;
1430 nstats->rx_errors = stats0->rx_errors + stats1->rx_errors;
1431 nstats->rx_crc_errors = stats0->rx_crc_errors + stats1->rx_crc_errors;
1432 nstats->rx_frame_errors =
1433 stats0->rx_frame_errors + stats1->rx_frame_errors;
1434 nstats->rx_length_errors =
1435 stats0->rx_length_errors + stats1->rx_length_errors;
1436 nstats->rx_missed_errors =
1437 stats0->rx_missed_errors + stats1->rx_missed_errors;
1438 nstats->rx_over_errors =
1439 stats0->rx_over_errors + stats1->rx_over_errors;
1444 /* Update promiscuous bit */
1445 static void ravb_set_rx_mode(struct net_device *ndev)
1447 struct ravb_private *priv = netdev_priv(ndev);
1448 unsigned long flags;
1451 spin_lock_irqsave(&priv->lock, flags);
1452 ecmr = ravb_read(ndev, ECMR);
1453 if (ndev->flags & IFF_PROMISC)
1457 ravb_write(ndev, ecmr, ECMR);
1459 spin_unlock_irqrestore(&priv->lock, flags);
1462 /* Device close function for Ethernet AVB */
1463 static int ravb_close(struct net_device *ndev)
1465 struct ravb_private *priv = netdev_priv(ndev);
1466 struct ravb_tstamp_skb *ts_skb, *ts_skb2;
1468 netif_tx_stop_all_queues(ndev);
1470 /* Disable interrupts by clearing the interrupt masks. */
1471 ravb_write(ndev, 0, RIC0);
1472 ravb_write(ndev, 0, RIC1);
1473 ravb_write(ndev, 0, RIC2);
1474 ravb_write(ndev, 0, TIC);
1476 /* Stop PTP Clock driver */
1477 ravb_ptp_stop(ndev);
1479 /* Set the config mode to stop the AVB-DMAC's processes */
1480 if (ravb_stop_dma(ndev) < 0)
1482 "device will be stopped after h/w processes are done.\n");
1484 /* Clear the timestamp list */
1485 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, list) {
1486 list_del(&ts_skb->list);
1490 /* PHY disconnect */
1492 phy_stop(priv->phydev);
1493 phy_disconnect(priv->phydev);
1494 priv->phydev = NULL;
1497 free_irq(ndev->irq, ndev);
1499 napi_disable(&priv->napi[RAVB_NC]);
1500 napi_disable(&priv->napi[RAVB_BE]);
1502 /* Free all the skb's in the RX queue and the DMA buffers. */
1503 ravb_ring_free(ndev, RAVB_BE);
1504 ravb_ring_free(ndev, RAVB_NC);
1509 static int ravb_hwtstamp_get(struct net_device *ndev, struct ifreq *req)
1511 struct ravb_private *priv = netdev_priv(ndev);
1512 struct hwtstamp_config config;
1515 config.tx_type = priv->tstamp_tx_ctrl ? HWTSTAMP_TX_ON :
1517 if (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE_V2_L2_EVENT)
1518 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
1519 else if (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE_ALL)
1520 config.rx_filter = HWTSTAMP_FILTER_ALL;
1522 config.rx_filter = HWTSTAMP_FILTER_NONE;
1524 return copy_to_user(req->ifr_data, &config, sizeof(config)) ?
1528 /* Control hardware time stamping */
1529 static int ravb_hwtstamp_set(struct net_device *ndev, struct ifreq *req)
1531 struct ravb_private *priv = netdev_priv(ndev);
1532 struct hwtstamp_config config;
1533 u32 tstamp_rx_ctrl = RAVB_RXTSTAMP_ENABLED;
1536 if (copy_from_user(&config, req->ifr_data, sizeof(config)))
1539 /* Reserved for future extensions */
1543 switch (config.tx_type) {
1544 case HWTSTAMP_TX_OFF:
1547 case HWTSTAMP_TX_ON:
1548 tstamp_tx_ctrl = RAVB_TXTSTAMP_ENABLED;
1554 switch (config.rx_filter) {
1555 case HWTSTAMP_FILTER_NONE:
1558 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1559 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_V2_L2_EVENT;
1562 config.rx_filter = HWTSTAMP_FILTER_ALL;
1563 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_ALL;
1566 priv->tstamp_tx_ctrl = tstamp_tx_ctrl;
1567 priv->tstamp_rx_ctrl = tstamp_rx_ctrl;
1569 return copy_to_user(req->ifr_data, &config, sizeof(config)) ?
1573 /* ioctl to device function */
1574 static int ravb_do_ioctl(struct net_device *ndev, struct ifreq *req, int cmd)
1576 struct ravb_private *priv = netdev_priv(ndev);
1577 struct phy_device *phydev = priv->phydev;
1579 if (!netif_running(ndev))
1587 return ravb_hwtstamp_get(ndev, req);
1589 return ravb_hwtstamp_set(ndev, req);
1592 return phy_mii_ioctl(phydev, req, cmd);
1595 static const struct net_device_ops ravb_netdev_ops = {
1596 .ndo_open = ravb_open,
1597 .ndo_stop = ravb_close,
1598 .ndo_start_xmit = ravb_start_xmit,
1599 .ndo_select_queue = ravb_select_queue,
1600 .ndo_get_stats = ravb_get_stats,
1601 .ndo_set_rx_mode = ravb_set_rx_mode,
1602 .ndo_tx_timeout = ravb_tx_timeout,
1603 .ndo_do_ioctl = ravb_do_ioctl,
1604 .ndo_validate_addr = eth_validate_addr,
1605 .ndo_set_mac_address = eth_mac_addr,
1606 .ndo_change_mtu = eth_change_mtu,
1609 /* MDIO bus init function */
1610 static int ravb_mdio_init(struct ravb_private *priv)
1612 struct platform_device *pdev = priv->pdev;
1613 struct device *dev = &pdev->dev;
1617 priv->mdiobb.ops = &bb_ops;
1619 /* MII controller setting */
1620 priv->mii_bus = alloc_mdio_bitbang(&priv->mdiobb);
1624 /* Hook up MII support for ethtool */
1625 priv->mii_bus->name = "ravb_mii";
1626 priv->mii_bus->parent = dev;
1627 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1628 pdev->name, pdev->id);
1630 /* Register MDIO bus */
1631 error = of_mdiobus_register(priv->mii_bus, dev->of_node);
1638 free_mdio_bitbang(priv->mii_bus);
1642 /* MDIO bus release function */
1643 static int ravb_mdio_release(struct ravb_private *priv)
1645 /* Unregister mdio bus */
1646 mdiobus_unregister(priv->mii_bus);
1648 /* Free bitbang info */
1649 free_mdio_bitbang(priv->mii_bus);
1654 static const struct of_device_id ravb_match_table[] = {
1655 { .compatible = "renesas,etheravb-r8a7790", .data = (void *)RCAR_GEN2 },
1656 { .compatible = "renesas,etheravb-r8a7794", .data = (void *)RCAR_GEN2 },
1657 { .compatible = "renesas,etheravb-r8a7795", .data = (void *)RCAR_GEN3 },
1660 MODULE_DEVICE_TABLE(of, ravb_match_table);
1662 static int ravb_probe(struct platform_device *pdev)
1664 struct device_node *np = pdev->dev.of_node;
1665 const struct of_device_id *match;
1666 struct ravb_private *priv;
1667 enum ravb_chip_id chip_id;
1668 struct net_device *ndev;
1670 struct resource *res;
1674 "this driver is required to be instantiated from device tree\n");
1678 /* Get base address */
1679 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1681 dev_err(&pdev->dev, "invalid resource\n");
1685 ndev = alloc_etherdev_mqs(sizeof(struct ravb_private),
1686 NUM_TX_QUEUE, NUM_RX_QUEUE);
1690 pm_runtime_enable(&pdev->dev);
1691 pm_runtime_get_sync(&pdev->dev);
1693 /* The Ether-specific entries in the device structure. */
1694 ndev->base_addr = res->start;
1697 match = of_match_device(of_match_ptr(ravb_match_table), &pdev->dev);
1698 chip_id = (enum ravb_chip_id)match->data;
1700 if (chip_id == RCAR_GEN3)
1701 irq = platform_get_irq_byname(pdev, "ch22");
1703 irq = platform_get_irq(pdev, 0);
1710 SET_NETDEV_DEV(ndev, &pdev->dev);
1712 priv = netdev_priv(ndev);
1715 priv->num_tx_ring[RAVB_BE] = BE_TX_RING_SIZE;
1716 priv->num_rx_ring[RAVB_BE] = BE_RX_RING_SIZE;
1717 priv->num_tx_ring[RAVB_NC] = NC_TX_RING_SIZE;
1718 priv->num_rx_ring[RAVB_NC] = NC_RX_RING_SIZE;
1719 priv->addr = devm_ioremap_resource(&pdev->dev, res);
1720 if (IS_ERR(priv->addr)) {
1721 error = PTR_ERR(priv->addr);
1725 spin_lock_init(&priv->lock);
1726 INIT_WORK(&priv->work, ravb_tx_timeout_work);
1728 priv->phy_interface = of_get_phy_mode(np);
1730 priv->no_avb_link = of_property_read_bool(np, "renesas,no-ether-link");
1731 priv->avb_link_active_low =
1732 of_property_read_bool(np, "renesas,ether-link-active-low");
1734 if (chip_id == RCAR_GEN3) {
1735 irq = platform_get_irq_byname(pdev, "ch24");
1740 priv->emac_irq = irq;
1743 priv->chip_id = chip_id;
1746 ndev->netdev_ops = &ravb_netdev_ops;
1747 ndev->ethtool_ops = &ravb_ethtool_ops;
1749 /* Set AVB config mode */
1750 ravb_write(ndev, (ravb_read(ndev, CCC) & ~CCC_OPC) | CCC_OPC_CONFIG,
1753 /* Set CSEL value */
1754 ravb_write(ndev, (ravb_read(ndev, CCC) & ~CCC_CSEL) | CCC_CSEL_HPB,
1758 ravb_write(ndev, ((1000 << 20) / 130) & GTI_TIV, GTI);
1760 /* Request GTI loading */
1761 ravb_write(ndev, ravb_read(ndev, GCCR) | GCCR_LTI, GCCR);
1763 /* Allocate descriptor base address table */
1764 priv->desc_bat_size = sizeof(struct ravb_desc) * DBAT_ENTRY_NUM;
1765 priv->desc_bat = dma_alloc_coherent(ndev->dev.parent, priv->desc_bat_size,
1766 &priv->desc_bat_dma, GFP_KERNEL);
1767 if (!priv->desc_bat) {
1769 "Cannot allocate desc base address table (size %d bytes)\n",
1770 priv->desc_bat_size);
1774 for (q = RAVB_BE; q < DBAT_ENTRY_NUM; q++)
1775 priv->desc_bat[q].die_dt = DT_EOS;
1776 ravb_write(ndev, priv->desc_bat_dma, DBAT);
1778 /* Initialise HW timestamp list */
1779 INIT_LIST_HEAD(&priv->ts_skb_list);
1781 /* Debug message level */
1782 priv->msg_enable = RAVB_DEF_MSG_ENABLE;
1784 /* Read and set MAC address */
1785 ravb_read_mac_address(ndev, of_get_mac_address(np));
1786 if (!is_valid_ether_addr(ndev->dev_addr)) {
1787 dev_warn(&pdev->dev,
1788 "no valid MAC address supplied, using a random one\n");
1789 eth_hw_addr_random(ndev);
1793 error = ravb_mdio_init(priv);
1795 dev_err(&pdev->dev, "failed to initialize MDIO\n");
1799 netif_napi_add(ndev, &priv->napi[RAVB_BE], ravb_poll, 64);
1800 netif_napi_add(ndev, &priv->napi[RAVB_NC], ravb_poll, 64);
1802 /* Network device register */
1803 error = register_netdev(ndev);
1807 /* Print device information */
1808 netdev_info(ndev, "Base address at %#x, %pM, IRQ %d.\n",
1809 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
1811 platform_set_drvdata(pdev, ndev);
1816 netif_napi_del(&priv->napi[RAVB_NC]);
1817 netif_napi_del(&priv->napi[RAVB_BE]);
1818 ravb_mdio_release(priv);
1820 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat,
1821 priv->desc_bat_dma);
1826 pm_runtime_put(&pdev->dev);
1827 pm_runtime_disable(&pdev->dev);
1831 static int ravb_remove(struct platform_device *pdev)
1833 struct net_device *ndev = platform_get_drvdata(pdev);
1834 struct ravb_private *priv = netdev_priv(ndev);
1836 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat,
1837 priv->desc_bat_dma);
1838 /* Set reset mode */
1839 ravb_write(ndev, CCC_OPC_RESET, CCC);
1840 pm_runtime_put_sync(&pdev->dev);
1841 unregister_netdev(ndev);
1842 netif_napi_del(&priv->napi[RAVB_NC]);
1843 netif_napi_del(&priv->napi[RAVB_BE]);
1844 ravb_mdio_release(priv);
1845 pm_runtime_disable(&pdev->dev);
1847 platform_set_drvdata(pdev, NULL);
1853 static int ravb_runtime_nop(struct device *dev)
1855 /* Runtime PM callback shared between ->runtime_suspend()
1856 * and ->runtime_resume(). Simply returns success.
1858 * This driver re-initializes all registers after
1859 * pm_runtime_get_sync() anyway so there is no need
1860 * to save and restore registers here.
1865 static const struct dev_pm_ops ravb_dev_pm_ops = {
1866 .runtime_suspend = ravb_runtime_nop,
1867 .runtime_resume = ravb_runtime_nop,
1870 #define RAVB_PM_OPS (&ravb_dev_pm_ops)
1872 #define RAVB_PM_OPS NULL
1875 static struct platform_driver ravb_driver = {
1876 .probe = ravb_probe,
1877 .remove = ravb_remove,
1881 .of_match_table = ravb_match_table,
1885 module_platform_driver(ravb_driver);
1887 MODULE_AUTHOR("Mitsuhiro Kimura, Masaru Nagai");
1888 MODULE_DESCRIPTION("Renesas Ethernet AVB driver");
1889 MODULE_LICENSE("GPL v2");