1 /* Renesas Ethernet AVB device driver
3 * Copyright (C) 2014-2015 Renesas Electronics Corporation
4 * Copyright (C) 2015 Renesas Solutions Corp.
5 * Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com>
7 * Based on the SuperH Ethernet driver
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License version 2,
11 * as published by the Free Software Foundation.
14 #include <linux/cache.h>
15 #include <linux/clk.h>
16 #include <linux/delay.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/err.h>
19 #include <linux/etherdevice.h>
20 #include <linux/ethtool.h>
21 #include <linux/if_vlan.h>
22 #include <linux/kernel.h>
23 #include <linux/list.h>
24 #include <linux/module.h>
25 #include <linux/net_tstamp.h>
27 #include <linux/of_device.h>
28 #include <linux/of_irq.h>
29 #include <linux/of_mdio.h>
30 #include <linux/of_net.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/slab.h>
33 #include <linux/spinlock.h>
34 #include <linux/sys_soc.h>
36 #include <asm/div64.h>
40 #define RAVB_DEF_MSG_ENABLE \
46 static const char *ravb_rx_irqs[NUM_RX_QUEUE] = {
51 static const char *ravb_tx_irqs[NUM_TX_QUEUE] = {
56 void ravb_modify(struct net_device *ndev, enum ravb_reg reg, u32 clear,
59 ravb_write(ndev, (ravb_read(ndev, reg) & ~clear) | set, reg);
62 int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value)
66 for (i = 0; i < 10000; i++) {
67 if ((ravb_read(ndev, reg) & mask) == value)
74 static int ravb_config(struct net_device *ndev)
79 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG);
80 /* Check if the operating mode is changed to the config mode */
81 error = ravb_wait(ndev, CSR, CSR_OPS, CSR_OPS_CONFIG);
83 netdev_err(ndev, "failed to switch device to config mode\n");
88 static void ravb_set_duplex(struct net_device *ndev)
90 struct ravb_private *priv = netdev_priv(ndev);
92 ravb_modify(ndev, ECMR, ECMR_DM, priv->duplex ? ECMR_DM : 0);
95 static void ravb_set_rate(struct net_device *ndev)
97 struct ravb_private *priv = netdev_priv(ndev);
99 switch (priv->speed) {
100 case 100: /* 100BASE */
101 ravb_write(ndev, GECMR_SPEED_100, GECMR);
103 case 1000: /* 1000BASE */
104 ravb_write(ndev, GECMR_SPEED_1000, GECMR);
109 static void ravb_set_buffer_align(struct sk_buff *skb)
111 u32 reserve = (unsigned long)skb->data & (RAVB_ALIGN - 1);
114 skb_reserve(skb, RAVB_ALIGN - reserve);
117 /* Get MAC address from the MAC address registers
119 * Ethernet AVB device doesn't have ROM for MAC address.
120 * This function gets the MAC address that was used by a bootloader.
122 static void ravb_read_mac_address(struct net_device *ndev, const u8 *mac)
125 ether_addr_copy(ndev->dev_addr, mac);
127 u32 mahr = ravb_read(ndev, MAHR);
128 u32 malr = ravb_read(ndev, MALR);
130 ndev->dev_addr[0] = (mahr >> 24) & 0xFF;
131 ndev->dev_addr[1] = (mahr >> 16) & 0xFF;
132 ndev->dev_addr[2] = (mahr >> 8) & 0xFF;
133 ndev->dev_addr[3] = (mahr >> 0) & 0xFF;
134 ndev->dev_addr[4] = (malr >> 8) & 0xFF;
135 ndev->dev_addr[5] = (malr >> 0) & 0xFF;
139 static void ravb_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set)
141 struct ravb_private *priv = container_of(ctrl, struct ravb_private,
144 ravb_modify(priv->ndev, PIR, mask, set ? mask : 0);
147 /* MDC pin control */
148 static void ravb_set_mdc(struct mdiobb_ctrl *ctrl, int level)
150 ravb_mdio_ctrl(ctrl, PIR_MDC, level);
153 /* Data I/O pin control */
154 static void ravb_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output)
156 ravb_mdio_ctrl(ctrl, PIR_MMD, output);
160 static void ravb_set_mdio_data(struct mdiobb_ctrl *ctrl, int value)
162 ravb_mdio_ctrl(ctrl, PIR_MDO, value);
166 static int ravb_get_mdio_data(struct mdiobb_ctrl *ctrl)
168 struct ravb_private *priv = container_of(ctrl, struct ravb_private,
171 return (ravb_read(priv->ndev, PIR) & PIR_MDI) != 0;
174 /* MDIO bus control struct */
175 static struct mdiobb_ops bb_ops = {
176 .owner = THIS_MODULE,
177 .set_mdc = ravb_set_mdc,
178 .set_mdio_dir = ravb_set_mdio_dir,
179 .set_mdio_data = ravb_set_mdio_data,
180 .get_mdio_data = ravb_get_mdio_data,
183 /* Free TX skb function for AVB-IP */
184 static int ravb_tx_free(struct net_device *ndev, int q, bool free_txed_only)
186 struct ravb_private *priv = netdev_priv(ndev);
187 struct net_device_stats *stats = &priv->stats[q];
188 struct ravb_tx_desc *desc;
193 for (; priv->cur_tx[q] - priv->dirty_tx[q] > 0; priv->dirty_tx[q]++) {
196 entry = priv->dirty_tx[q] % (priv->num_tx_ring[q] *
198 desc = &priv->tx_ring[q][entry];
199 txed = desc->die_dt == DT_FEMPTY;
200 if (free_txed_only && !txed)
202 /* Descriptor type must be checked before all other reads */
204 size = le16_to_cpu(desc->ds_tagl) & TX_DS;
205 /* Free the original skb. */
206 if (priv->tx_skb[q][entry / NUM_TX_DESC]) {
207 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
208 size, DMA_TO_DEVICE);
209 /* Last packet descriptor? */
210 if (entry % NUM_TX_DESC == NUM_TX_DESC - 1) {
211 entry /= NUM_TX_DESC;
212 dev_kfree_skb_any(priv->tx_skb[q][entry]);
213 priv->tx_skb[q][entry] = NULL;
220 stats->tx_bytes += size;
221 desc->die_dt = DT_EEMPTY;
226 /* Free skb's and DMA buffers for Ethernet AVB */
227 static void ravb_ring_free(struct net_device *ndev, int q)
229 struct ravb_private *priv = netdev_priv(ndev);
233 if (priv->rx_ring[q]) {
234 for (i = 0; i < priv->num_rx_ring[q]; i++) {
235 struct ravb_ex_rx_desc *desc = &priv->rx_ring[q][i];
237 if (!dma_mapping_error(ndev->dev.parent,
238 le32_to_cpu(desc->dptr)))
239 dma_unmap_single(ndev->dev.parent,
240 le32_to_cpu(desc->dptr),
244 ring_size = sizeof(struct ravb_ex_rx_desc) *
245 (priv->num_rx_ring[q] + 1);
246 dma_free_coherent(ndev->dev.parent, ring_size, priv->rx_ring[q],
247 priv->rx_desc_dma[q]);
248 priv->rx_ring[q] = NULL;
251 if (priv->tx_ring[q]) {
252 ravb_tx_free(ndev, q, false);
254 ring_size = sizeof(struct ravb_tx_desc) *
255 (priv->num_tx_ring[q] * NUM_TX_DESC + 1);
256 dma_free_coherent(ndev->dev.parent, ring_size, priv->tx_ring[q],
257 priv->tx_desc_dma[q]);
258 priv->tx_ring[q] = NULL;
261 /* Free RX skb ringbuffer */
262 if (priv->rx_skb[q]) {
263 for (i = 0; i < priv->num_rx_ring[q]; i++)
264 dev_kfree_skb(priv->rx_skb[q][i]);
266 kfree(priv->rx_skb[q]);
267 priv->rx_skb[q] = NULL;
269 /* Free aligned TX buffers */
270 kfree(priv->tx_align[q]);
271 priv->tx_align[q] = NULL;
273 /* Free TX skb ringbuffer.
274 * SKBs are freed by ravb_tx_free() call above.
276 kfree(priv->tx_skb[q]);
277 priv->tx_skb[q] = NULL;
280 /* Format skb and descriptor buffer for Ethernet AVB */
281 static void ravb_ring_format(struct net_device *ndev, int q)
283 struct ravb_private *priv = netdev_priv(ndev);
284 struct ravb_ex_rx_desc *rx_desc;
285 struct ravb_tx_desc *tx_desc;
286 struct ravb_desc *desc;
287 int rx_ring_size = sizeof(*rx_desc) * priv->num_rx_ring[q];
288 int tx_ring_size = sizeof(*tx_desc) * priv->num_tx_ring[q] *
295 priv->dirty_rx[q] = 0;
296 priv->dirty_tx[q] = 0;
298 memset(priv->rx_ring[q], 0, rx_ring_size);
299 /* Build RX ring buffer */
300 for (i = 0; i < priv->num_rx_ring[q]; i++) {
302 rx_desc = &priv->rx_ring[q][i];
303 rx_desc->ds_cc = cpu_to_le16(priv->rx_buf_sz);
304 dma_addr = dma_map_single(ndev->dev.parent, priv->rx_skb[q][i]->data,
307 /* We just set the data size to 0 for a failed mapping which
308 * should prevent DMA from happening...
310 if (dma_mapping_error(ndev->dev.parent, dma_addr))
311 rx_desc->ds_cc = cpu_to_le16(0);
312 rx_desc->dptr = cpu_to_le32(dma_addr);
313 rx_desc->die_dt = DT_FEMPTY;
315 rx_desc = &priv->rx_ring[q][i];
316 rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]);
317 rx_desc->die_dt = DT_LINKFIX; /* type */
319 memset(priv->tx_ring[q], 0, tx_ring_size);
320 /* Build TX ring buffer */
321 for (i = 0, tx_desc = priv->tx_ring[q]; i < priv->num_tx_ring[q];
323 tx_desc->die_dt = DT_EEMPTY;
325 tx_desc->die_dt = DT_EEMPTY;
327 tx_desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]);
328 tx_desc->die_dt = DT_LINKFIX; /* type */
330 /* RX descriptor base address for best effort */
331 desc = &priv->desc_bat[RX_QUEUE_OFFSET + q];
332 desc->die_dt = DT_LINKFIX; /* type */
333 desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]);
335 /* TX descriptor base address for best effort */
336 desc = &priv->desc_bat[q];
337 desc->die_dt = DT_LINKFIX; /* type */
338 desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]);
341 /* Init skb and descriptor buffer for Ethernet AVB */
342 static int ravb_ring_init(struct net_device *ndev, int q)
344 struct ravb_private *priv = netdev_priv(ndev);
349 priv->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ : ndev->mtu) +
350 ETH_HLEN + VLAN_HLEN;
352 /* Allocate RX and TX skb rings */
353 priv->rx_skb[q] = kcalloc(priv->num_rx_ring[q],
354 sizeof(*priv->rx_skb[q]), GFP_KERNEL);
355 priv->tx_skb[q] = kcalloc(priv->num_tx_ring[q],
356 sizeof(*priv->tx_skb[q]), GFP_KERNEL);
357 if (!priv->rx_skb[q] || !priv->tx_skb[q])
360 for (i = 0; i < priv->num_rx_ring[q]; i++) {
361 skb = netdev_alloc_skb(ndev, priv->rx_buf_sz + RAVB_ALIGN - 1);
364 ravb_set_buffer_align(skb);
365 priv->rx_skb[q][i] = skb;
368 /* Allocate rings for the aligned buffers */
369 priv->tx_align[q] = kmalloc(DPTR_ALIGN * priv->num_tx_ring[q] +
370 DPTR_ALIGN - 1, GFP_KERNEL);
371 if (!priv->tx_align[q])
374 /* Allocate all RX descriptors. */
375 ring_size = sizeof(struct ravb_ex_rx_desc) * (priv->num_rx_ring[q] + 1);
376 priv->rx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size,
377 &priv->rx_desc_dma[q],
379 if (!priv->rx_ring[q])
382 priv->dirty_rx[q] = 0;
384 /* Allocate all TX descriptors. */
385 ring_size = sizeof(struct ravb_tx_desc) *
386 (priv->num_tx_ring[q] * NUM_TX_DESC + 1);
387 priv->tx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size,
388 &priv->tx_desc_dma[q],
390 if (!priv->tx_ring[q])
396 ravb_ring_free(ndev, q);
401 /* E-MAC init function */
402 static void ravb_emac_init(struct net_device *ndev)
404 struct ravb_private *priv = netdev_priv(ndev);
406 /* Receive frame limit set register */
407 ravb_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, RFLR);
409 /* EMAC Mode: PAUSE prohibition; Duplex; RX Checksum; TX; RX */
410 ravb_write(ndev, ECMR_ZPF | (priv->duplex ? ECMR_DM : 0) |
411 (ndev->features & NETIF_F_RXCSUM ? ECMR_RCSC : 0) |
412 ECMR_TE | ECMR_RE, ECMR);
416 /* Set MAC address */
418 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
419 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
421 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
423 /* E-MAC status register clear */
424 ravb_write(ndev, ECSR_ICD | ECSR_MPD, ECSR);
426 /* E-MAC interrupt enable register */
427 ravb_write(ndev, ECSIPR_ICDIP | ECSIPR_MPDIP | ECSIPR_LCHNGIP, ECSIPR);
430 /* Device init function for Ethernet AVB */
431 static int ravb_dmac_init(struct net_device *ndev)
433 struct ravb_private *priv = netdev_priv(ndev);
436 /* Set CONFIG mode */
437 error = ravb_config(ndev);
441 error = ravb_ring_init(ndev, RAVB_BE);
444 error = ravb_ring_init(ndev, RAVB_NC);
446 ravb_ring_free(ndev, RAVB_BE);
450 /* Descriptor format */
451 ravb_ring_format(ndev, RAVB_BE);
452 ravb_ring_format(ndev, RAVB_NC);
454 #if defined(__LITTLE_ENDIAN)
455 ravb_modify(ndev, CCC, CCC_BOC, 0);
457 ravb_modify(ndev, CCC, CCC_BOC, CCC_BOC);
462 RCR_EFFS | RCR_ENCF | RCR_ETS0 | RCR_ESF | 0x18000000, RCR);
465 ravb_write(ndev, TGC_TQP_AVBMODE1 | 0x00222200, TGC);
467 /* Timestamp enable */
468 ravb_write(ndev, TCCR_TFEN, TCCR);
470 /* Interrupt init: */
471 if (priv->chip_id == RCAR_GEN3) {
473 ravb_write(ndev, 0, DIL);
474 /* Set queue specific interrupt */
475 ravb_write(ndev, CIE_CRIE | CIE_CTIE | CIE_CL0M, CIE);
478 ravb_write(ndev, RIC0_FRE0 | RIC0_FRE1, RIC0);
479 /* Disable FIFO full warning */
480 ravb_write(ndev, 0, RIC1);
481 /* Receive FIFO full error, descriptor empty */
482 ravb_write(ndev, RIC2_QFE0 | RIC2_QFE1 | RIC2_RFFE, RIC2);
483 /* Frame transmitted, timestamp FIFO updated */
484 ravb_write(ndev, TIC_FTE0 | TIC_FTE1 | TIC_TFUE, TIC);
486 /* Setting the control will start the AVB-DMAC process. */
487 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_OPERATION);
492 static void ravb_get_tx_tstamp(struct net_device *ndev)
494 struct ravb_private *priv = netdev_priv(ndev);
495 struct ravb_tstamp_skb *ts_skb, *ts_skb2;
496 struct skb_shared_hwtstamps shhwtstamps;
498 struct timespec64 ts;
503 count = (ravb_read(ndev, TSR) & TSR_TFFL) >> 8;
505 tfa2 = ravb_read(ndev, TFA2);
506 tfa_tag = (tfa2 & TFA2_TST) >> 16;
507 ts.tv_nsec = (u64)ravb_read(ndev, TFA0);
508 ts.tv_sec = ((u64)(tfa2 & TFA2_TSV) << 32) |
509 ravb_read(ndev, TFA1);
510 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
511 shhwtstamps.hwtstamp = timespec64_to_ktime(ts);
512 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list,
516 list_del(&ts_skb->list);
518 if (tag == tfa_tag) {
519 skb_tstamp_tx(skb, &shhwtstamps);
523 ravb_modify(ndev, TCCR, TCCR_TFR, TCCR_TFR);
527 static void ravb_rx_csum(struct sk_buff *skb)
531 /* The hardware checksum is 2 bytes appended to packet data */
532 if (unlikely(skb->len < 2))
534 hw_csum = skb_tail_pointer(skb) - 2;
535 skb->csum = csum_unfold((__force __sum16)get_unaligned_le16(hw_csum));
536 skb->ip_summed = CHECKSUM_COMPLETE;
537 skb_trim(skb, skb->len - 2);
540 /* Packet receive function for Ethernet AVB */
541 static bool ravb_rx(struct net_device *ndev, int *quota, int q)
543 struct ravb_private *priv = netdev_priv(ndev);
544 int entry = priv->cur_rx[q] % priv->num_rx_ring[q];
545 int boguscnt = (priv->dirty_rx[q] + priv->num_rx_ring[q]) -
547 struct net_device_stats *stats = &priv->stats[q];
548 struct ravb_ex_rx_desc *desc;
551 struct timespec64 ts;
556 boguscnt = min(boguscnt, *quota);
558 desc = &priv->rx_ring[q][entry];
559 while (desc->die_dt != DT_FEMPTY) {
560 /* Descriptor type must be checked before all other reads */
562 desc_status = desc->msc;
563 pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS;
568 /* We use 0-byte descriptors to mark the DMA mapping errors */
572 if (desc_status & MSC_MC)
575 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF |
578 if (desc_status & MSC_CRC)
579 stats->rx_crc_errors++;
580 if (desc_status & MSC_RFE)
581 stats->rx_frame_errors++;
582 if (desc_status & (MSC_RTLF | MSC_RTSF))
583 stats->rx_length_errors++;
584 if (desc_status & MSC_CEEF)
585 stats->rx_missed_errors++;
587 u32 get_ts = priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE;
589 skb = priv->rx_skb[q][entry];
590 priv->rx_skb[q][entry] = NULL;
591 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
594 get_ts &= (q == RAVB_NC) ?
595 RAVB_RXTSTAMP_TYPE_V2_L2_EVENT :
596 ~RAVB_RXTSTAMP_TYPE_V2_L2_EVENT;
598 struct skb_shared_hwtstamps *shhwtstamps;
600 shhwtstamps = skb_hwtstamps(skb);
601 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
602 ts.tv_sec = ((u64) le16_to_cpu(desc->ts_sh) <<
603 32) | le32_to_cpu(desc->ts_sl);
604 ts.tv_nsec = le32_to_cpu(desc->ts_n);
605 shhwtstamps->hwtstamp = timespec64_to_ktime(ts);
608 skb_put(skb, pkt_len);
609 skb->protocol = eth_type_trans(skb, ndev);
610 if (ndev->features & NETIF_F_RXCSUM)
612 napi_gro_receive(&priv->napi[q], skb);
614 stats->rx_bytes += pkt_len;
617 entry = (++priv->cur_rx[q]) % priv->num_rx_ring[q];
618 desc = &priv->rx_ring[q][entry];
621 /* Refill the RX ring buffers. */
622 for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) {
623 entry = priv->dirty_rx[q] % priv->num_rx_ring[q];
624 desc = &priv->rx_ring[q][entry];
625 desc->ds_cc = cpu_to_le16(priv->rx_buf_sz);
627 if (!priv->rx_skb[q][entry]) {
628 skb = netdev_alloc_skb(ndev,
632 break; /* Better luck next round. */
633 ravb_set_buffer_align(skb);
634 dma_addr = dma_map_single(ndev->dev.parent, skb->data,
635 le16_to_cpu(desc->ds_cc),
637 skb_checksum_none_assert(skb);
638 /* We just set the data size to 0 for a failed mapping
639 * which should prevent DMA from happening...
641 if (dma_mapping_error(ndev->dev.parent, dma_addr))
642 desc->ds_cc = cpu_to_le16(0);
643 desc->dptr = cpu_to_le32(dma_addr);
644 priv->rx_skb[q][entry] = skb;
646 /* Descriptor type must be set after all the above writes */
648 desc->die_dt = DT_FEMPTY;
651 *quota -= limit - (++boguscnt);
653 return boguscnt <= 0;
656 static void ravb_rcv_snd_disable(struct net_device *ndev)
658 /* Disable TX and RX */
659 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0);
662 static void ravb_rcv_snd_enable(struct net_device *ndev)
664 /* Enable TX and RX */
665 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE);
668 /* function for waiting dma process finished */
669 static int ravb_stop_dma(struct net_device *ndev)
673 /* Wait for stopping the hardware TX process */
674 error = ravb_wait(ndev, TCCR,
675 TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 0);
679 error = ravb_wait(ndev, CSR, CSR_TPO0 | CSR_TPO1 | CSR_TPO2 | CSR_TPO3,
684 /* Stop the E-MAC's RX/TX processes. */
685 ravb_rcv_snd_disable(ndev);
687 /* Wait for stopping the RX DMA process */
688 error = ravb_wait(ndev, CSR, CSR_RPO, 0);
692 /* Stop AVB-DMAC process */
693 return ravb_config(ndev);
696 /* E-MAC interrupt handler */
697 static void ravb_emac_interrupt_unlocked(struct net_device *ndev)
699 struct ravb_private *priv = netdev_priv(ndev);
702 ecsr = ravb_read(ndev, ECSR);
703 ravb_write(ndev, ecsr, ECSR); /* clear interrupt */
706 pm_wakeup_event(&priv->pdev->dev, 0);
708 ndev->stats.tx_carrier_errors++;
709 if (ecsr & ECSR_LCHNG) {
711 if (priv->no_avb_link)
713 psr = ravb_read(ndev, PSR);
714 if (priv->avb_link_active_low)
716 if (!(psr & PSR_LMON)) {
717 /* DIsable RX and TX */
718 ravb_rcv_snd_disable(ndev);
720 /* Enable RX and TX */
721 ravb_rcv_snd_enable(ndev);
726 static irqreturn_t ravb_emac_interrupt(int irq, void *dev_id)
728 struct net_device *ndev = dev_id;
729 struct ravb_private *priv = netdev_priv(ndev);
731 spin_lock(&priv->lock);
732 ravb_emac_interrupt_unlocked(ndev);
734 spin_unlock(&priv->lock);
738 /* Error interrupt handler */
739 static void ravb_error_interrupt(struct net_device *ndev)
741 struct ravb_private *priv = netdev_priv(ndev);
744 eis = ravb_read(ndev, EIS);
745 ravb_write(ndev, ~EIS_QFS, EIS);
747 ris2 = ravb_read(ndev, RIS2);
748 ravb_write(ndev, ~(RIS2_QFF0 | RIS2_RFFF), RIS2);
750 /* Receive Descriptor Empty int */
751 if (ris2 & RIS2_QFF0)
752 priv->stats[RAVB_BE].rx_over_errors++;
754 /* Receive Descriptor Empty int */
755 if (ris2 & RIS2_QFF1)
756 priv->stats[RAVB_NC].rx_over_errors++;
758 /* Receive FIFO Overflow int */
759 if (ris2 & RIS2_RFFF)
760 priv->rx_fifo_errors++;
764 static bool ravb_queue_interrupt(struct net_device *ndev, int q)
766 struct ravb_private *priv = netdev_priv(ndev);
767 u32 ris0 = ravb_read(ndev, RIS0);
768 u32 ric0 = ravb_read(ndev, RIC0);
769 u32 tis = ravb_read(ndev, TIS);
770 u32 tic = ravb_read(ndev, TIC);
772 if (((ris0 & ric0) & BIT(q)) || ((tis & tic) & BIT(q))) {
773 if (napi_schedule_prep(&priv->napi[q])) {
774 /* Mask RX and TX interrupts */
775 if (priv->chip_id == RCAR_GEN2) {
776 ravb_write(ndev, ric0 & ~BIT(q), RIC0);
777 ravb_write(ndev, tic & ~BIT(q), TIC);
779 ravb_write(ndev, BIT(q), RID0);
780 ravb_write(ndev, BIT(q), TID);
782 __napi_schedule(&priv->napi[q]);
785 "ignoring interrupt, rx status 0x%08x, rx mask 0x%08x,\n",
788 " tx status 0x%08x, tx mask 0x%08x.\n",
796 static bool ravb_timestamp_interrupt(struct net_device *ndev)
798 u32 tis = ravb_read(ndev, TIS);
800 if (tis & TIS_TFUF) {
801 ravb_write(ndev, ~TIS_TFUF, TIS);
802 ravb_get_tx_tstamp(ndev);
808 static irqreturn_t ravb_interrupt(int irq, void *dev_id)
810 struct net_device *ndev = dev_id;
811 struct ravb_private *priv = netdev_priv(ndev);
812 irqreturn_t result = IRQ_NONE;
815 spin_lock(&priv->lock);
816 /* Get interrupt status */
817 iss = ravb_read(ndev, ISS);
819 /* Received and transmitted interrupts */
820 if (iss & (ISS_FRS | ISS_FTS | ISS_TFUS)) {
823 /* Timestamp updated */
824 if (ravb_timestamp_interrupt(ndev))
825 result = IRQ_HANDLED;
827 /* Network control and best effort queue RX/TX */
828 for (q = RAVB_NC; q >= RAVB_BE; q--) {
829 if (ravb_queue_interrupt(ndev, q))
830 result = IRQ_HANDLED;
834 /* E-MAC status summary */
836 ravb_emac_interrupt_unlocked(ndev);
837 result = IRQ_HANDLED;
840 /* Error status summary */
842 ravb_error_interrupt(ndev);
843 result = IRQ_HANDLED;
846 /* gPTP interrupt status summary */
847 if (iss & ISS_CGIS) {
848 ravb_ptp_interrupt(ndev);
849 result = IRQ_HANDLED;
853 spin_unlock(&priv->lock);
857 /* Timestamp/Error/gPTP interrupt handler */
858 static irqreturn_t ravb_multi_interrupt(int irq, void *dev_id)
860 struct net_device *ndev = dev_id;
861 struct ravb_private *priv = netdev_priv(ndev);
862 irqreturn_t result = IRQ_NONE;
865 spin_lock(&priv->lock);
866 /* Get interrupt status */
867 iss = ravb_read(ndev, ISS);
869 /* Timestamp updated */
870 if ((iss & ISS_TFUS) && ravb_timestamp_interrupt(ndev))
871 result = IRQ_HANDLED;
873 /* Error status summary */
875 ravb_error_interrupt(ndev);
876 result = IRQ_HANDLED;
879 /* gPTP interrupt status summary */
880 if (iss & ISS_CGIS) {
881 ravb_ptp_interrupt(ndev);
882 result = IRQ_HANDLED;
886 spin_unlock(&priv->lock);
890 static irqreturn_t ravb_dma_interrupt(int irq, void *dev_id, int q)
892 struct net_device *ndev = dev_id;
893 struct ravb_private *priv = netdev_priv(ndev);
894 irqreturn_t result = IRQ_NONE;
896 spin_lock(&priv->lock);
898 /* Network control/Best effort queue RX/TX */
899 if (ravb_queue_interrupt(ndev, q))
900 result = IRQ_HANDLED;
903 spin_unlock(&priv->lock);
907 static irqreturn_t ravb_be_interrupt(int irq, void *dev_id)
909 return ravb_dma_interrupt(irq, dev_id, RAVB_BE);
912 static irqreturn_t ravb_nc_interrupt(int irq, void *dev_id)
914 return ravb_dma_interrupt(irq, dev_id, RAVB_NC);
917 static int ravb_poll(struct napi_struct *napi, int budget)
919 struct net_device *ndev = napi->dev;
920 struct ravb_private *priv = netdev_priv(ndev);
922 int q = napi - priv->napi;
928 tis = ravb_read(ndev, TIS);
929 ris0 = ravb_read(ndev, RIS0);
930 if (!((ris0 & mask) || (tis & mask)))
933 /* Processing RX Descriptor Ring */
935 /* Clear RX interrupt */
936 ravb_write(ndev, ~mask, RIS0);
937 if (ravb_rx(ndev, "a, q))
940 /* Processing TX Descriptor Ring */
942 spin_lock_irqsave(&priv->lock, flags);
943 /* Clear TX interrupt */
944 ravb_write(ndev, ~mask, TIS);
945 ravb_tx_free(ndev, q, true);
946 netif_wake_subqueue(ndev, q);
948 spin_unlock_irqrestore(&priv->lock, flags);
954 /* Re-enable RX/TX interrupts */
955 spin_lock_irqsave(&priv->lock, flags);
956 if (priv->chip_id == RCAR_GEN2) {
957 ravb_modify(ndev, RIC0, mask, mask);
958 ravb_modify(ndev, TIC, mask, mask);
960 ravb_write(ndev, mask, RIE0);
961 ravb_write(ndev, mask, TIE);
964 spin_unlock_irqrestore(&priv->lock, flags);
966 /* Receive error message handling */
967 priv->rx_over_errors = priv->stats[RAVB_BE].rx_over_errors;
968 priv->rx_over_errors += priv->stats[RAVB_NC].rx_over_errors;
969 if (priv->rx_over_errors != ndev->stats.rx_over_errors)
970 ndev->stats.rx_over_errors = priv->rx_over_errors;
971 if (priv->rx_fifo_errors != ndev->stats.rx_fifo_errors)
972 ndev->stats.rx_fifo_errors = priv->rx_fifo_errors;
974 return budget - quota;
977 /* PHY state control function */
978 static void ravb_adjust_link(struct net_device *ndev)
980 struct ravb_private *priv = netdev_priv(ndev);
981 struct phy_device *phydev = ndev->phydev;
982 bool new_state = false;
985 spin_lock_irqsave(&priv->lock, flags);
987 /* Disable TX and RX right over here, if E-MAC change is ignored */
988 if (priv->no_avb_link)
989 ravb_rcv_snd_disable(ndev);
992 if (phydev->duplex != priv->duplex) {
994 priv->duplex = phydev->duplex;
995 ravb_set_duplex(ndev);
998 if (phydev->speed != priv->speed) {
1000 priv->speed = phydev->speed;
1001 ravb_set_rate(ndev);
1004 ravb_modify(ndev, ECMR, ECMR_TXF, 0);
1006 priv->link = phydev->link;
1008 } else if (priv->link) {
1015 /* Enable TX and RX right over here, if E-MAC change is ignored */
1016 if (priv->no_avb_link && phydev->link)
1017 ravb_rcv_snd_enable(ndev);
1020 spin_unlock_irqrestore(&priv->lock, flags);
1022 if (new_state && netif_msg_link(priv))
1023 phy_print_status(phydev);
1026 static const struct soc_device_attribute r8a7795es10[] = {
1027 { .soc_id = "r8a7795", .revision = "ES1.0", },
1031 /* PHY init function */
1032 static int ravb_phy_init(struct net_device *ndev)
1034 struct device_node *np = ndev->dev.parent->of_node;
1035 struct ravb_private *priv = netdev_priv(ndev);
1036 struct phy_device *phydev;
1037 struct device_node *pn;
1044 /* Try connecting to PHY */
1045 pn = of_parse_phandle(np, "phy-handle", 0);
1047 /* In the case of a fixed PHY, the DT node associated
1048 * to the PHY is the Ethernet MAC DT node.
1050 if (of_phy_is_fixed_link(np)) {
1051 err = of_phy_register_fixed_link(np);
1055 pn = of_node_get(np);
1057 phydev = of_phy_connect(ndev, pn, ravb_adjust_link, 0,
1058 priv->phy_interface);
1061 netdev_err(ndev, "failed to connect PHY\n");
1063 goto err_deregister_fixed_link;
1066 /* This driver only support 10/100Mbit speeds on R-Car H3 ES1.0
1069 if (soc_device_match(r8a7795es10)) {
1070 err = phy_set_max_speed(phydev, SPEED_100);
1072 netdev_err(ndev, "failed to limit PHY to 100Mbit/s\n");
1073 goto err_phy_disconnect;
1076 netdev_info(ndev, "limited PHY to 100Mbit/s\n");
1079 /* 10BASE is not supported */
1080 phydev->supported &= ~PHY_10BT_FEATURES;
1082 phy_attached_info(phydev);
1087 phy_disconnect(phydev);
1088 err_deregister_fixed_link:
1089 if (of_phy_is_fixed_link(np))
1090 of_phy_deregister_fixed_link(np);
1095 /* PHY control start function */
1096 static int ravb_phy_start(struct net_device *ndev)
1100 error = ravb_phy_init(ndev);
1104 phy_start(ndev->phydev);
1109 static int ravb_set_link_ksettings(struct net_device *ndev,
1110 const struct ethtool_link_ksettings *cmd)
1115 return phy_ethtool_ksettings_set(ndev->phydev, cmd);
1118 static u32 ravb_get_msglevel(struct net_device *ndev)
1120 struct ravb_private *priv = netdev_priv(ndev);
1122 return priv->msg_enable;
1125 static void ravb_set_msglevel(struct net_device *ndev, u32 value)
1127 struct ravb_private *priv = netdev_priv(ndev);
1129 priv->msg_enable = value;
1132 static const char ravb_gstrings_stats[][ETH_GSTRING_LEN] = {
1133 "rx_queue_0_current",
1134 "tx_queue_0_current",
1137 "rx_queue_0_packets",
1138 "tx_queue_0_packets",
1141 "rx_queue_0_mcast_packets",
1142 "rx_queue_0_errors",
1143 "rx_queue_0_crc_errors",
1144 "rx_queue_0_frame_errors",
1145 "rx_queue_0_length_errors",
1146 "rx_queue_0_missed_errors",
1147 "rx_queue_0_over_errors",
1149 "rx_queue_1_current",
1150 "tx_queue_1_current",
1153 "rx_queue_1_packets",
1154 "tx_queue_1_packets",
1157 "rx_queue_1_mcast_packets",
1158 "rx_queue_1_errors",
1159 "rx_queue_1_crc_errors",
1160 "rx_queue_1_frame_errors",
1161 "rx_queue_1_length_errors",
1162 "rx_queue_1_missed_errors",
1163 "rx_queue_1_over_errors",
1166 #define RAVB_STATS_LEN ARRAY_SIZE(ravb_gstrings_stats)
1168 static int ravb_get_sset_count(struct net_device *netdev, int sset)
1172 return RAVB_STATS_LEN;
1178 static void ravb_get_ethtool_stats(struct net_device *ndev,
1179 struct ethtool_stats *stats, u64 *data)
1181 struct ravb_private *priv = netdev_priv(ndev);
1185 /* Device-specific stats */
1186 for (q = RAVB_BE; q < NUM_RX_QUEUE; q++) {
1187 struct net_device_stats *stats = &priv->stats[q];
1189 data[i++] = priv->cur_rx[q];
1190 data[i++] = priv->cur_tx[q];
1191 data[i++] = priv->dirty_rx[q];
1192 data[i++] = priv->dirty_tx[q];
1193 data[i++] = stats->rx_packets;
1194 data[i++] = stats->tx_packets;
1195 data[i++] = stats->rx_bytes;
1196 data[i++] = stats->tx_bytes;
1197 data[i++] = stats->multicast;
1198 data[i++] = stats->rx_errors;
1199 data[i++] = stats->rx_crc_errors;
1200 data[i++] = stats->rx_frame_errors;
1201 data[i++] = stats->rx_length_errors;
1202 data[i++] = stats->rx_missed_errors;
1203 data[i++] = stats->rx_over_errors;
1207 static void ravb_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1209 switch (stringset) {
1211 memcpy(data, *ravb_gstrings_stats, sizeof(ravb_gstrings_stats));
1216 static void ravb_get_ringparam(struct net_device *ndev,
1217 struct ethtool_ringparam *ring)
1219 struct ravb_private *priv = netdev_priv(ndev);
1221 ring->rx_max_pending = BE_RX_RING_MAX;
1222 ring->tx_max_pending = BE_TX_RING_MAX;
1223 ring->rx_pending = priv->num_rx_ring[RAVB_BE];
1224 ring->tx_pending = priv->num_tx_ring[RAVB_BE];
1227 static int ravb_set_ringparam(struct net_device *ndev,
1228 struct ethtool_ringparam *ring)
1230 struct ravb_private *priv = netdev_priv(ndev);
1233 if (ring->tx_pending > BE_TX_RING_MAX ||
1234 ring->rx_pending > BE_RX_RING_MAX ||
1235 ring->tx_pending < BE_TX_RING_MIN ||
1236 ring->rx_pending < BE_RX_RING_MIN)
1238 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
1241 if (netif_running(ndev)) {
1242 netif_device_detach(ndev);
1243 /* Stop PTP Clock driver */
1244 if (priv->chip_id == RCAR_GEN2)
1245 ravb_ptp_stop(ndev);
1246 /* Wait for DMA stopping */
1247 error = ravb_stop_dma(ndev);
1250 "cannot set ringparam! Any AVB processes are still running?\n");
1253 synchronize_irq(ndev->irq);
1255 /* Free all the skb's in the RX queue and the DMA buffers. */
1256 ravb_ring_free(ndev, RAVB_BE);
1257 ravb_ring_free(ndev, RAVB_NC);
1260 /* Set new parameters */
1261 priv->num_rx_ring[RAVB_BE] = ring->rx_pending;
1262 priv->num_tx_ring[RAVB_BE] = ring->tx_pending;
1264 if (netif_running(ndev)) {
1265 error = ravb_dmac_init(ndev);
1268 "%s: ravb_dmac_init() failed, error %d\n",
1273 ravb_emac_init(ndev);
1275 /* Initialise PTP Clock driver */
1276 if (priv->chip_id == RCAR_GEN2)
1277 ravb_ptp_init(ndev, priv->pdev);
1279 netif_device_attach(ndev);
1285 static int ravb_get_ts_info(struct net_device *ndev,
1286 struct ethtool_ts_info *info)
1288 struct ravb_private *priv = netdev_priv(ndev);
1290 info->so_timestamping =
1291 SOF_TIMESTAMPING_TX_SOFTWARE |
1292 SOF_TIMESTAMPING_RX_SOFTWARE |
1293 SOF_TIMESTAMPING_SOFTWARE |
1294 SOF_TIMESTAMPING_TX_HARDWARE |
1295 SOF_TIMESTAMPING_RX_HARDWARE |
1296 SOF_TIMESTAMPING_RAW_HARDWARE;
1297 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
1299 (1 << HWTSTAMP_FILTER_NONE) |
1300 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
1301 (1 << HWTSTAMP_FILTER_ALL);
1302 info->phc_index = ptp_clock_index(priv->ptp.clock);
1307 static void ravb_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1309 struct ravb_private *priv = netdev_priv(ndev);
1311 wol->supported = WAKE_MAGIC;
1312 wol->wolopts = priv->wol_enabled ? WAKE_MAGIC : 0;
1315 static int ravb_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1317 struct ravb_private *priv = netdev_priv(ndev);
1319 if (wol->wolopts & ~WAKE_MAGIC)
1322 priv->wol_enabled = !!(wol->wolopts & WAKE_MAGIC);
1324 device_set_wakeup_enable(&priv->pdev->dev, priv->wol_enabled);
1329 static const struct ethtool_ops ravb_ethtool_ops = {
1330 .nway_reset = phy_ethtool_nway_reset,
1331 .get_msglevel = ravb_get_msglevel,
1332 .set_msglevel = ravb_set_msglevel,
1333 .get_link = ethtool_op_get_link,
1334 .get_strings = ravb_get_strings,
1335 .get_ethtool_stats = ravb_get_ethtool_stats,
1336 .get_sset_count = ravb_get_sset_count,
1337 .get_ringparam = ravb_get_ringparam,
1338 .set_ringparam = ravb_set_ringparam,
1339 .get_ts_info = ravb_get_ts_info,
1340 .get_link_ksettings = phy_ethtool_get_link_ksettings,
1341 .set_link_ksettings = ravb_set_link_ksettings,
1342 .get_wol = ravb_get_wol,
1343 .set_wol = ravb_set_wol,
1346 static inline int ravb_hook_irq(unsigned int irq, irq_handler_t handler,
1347 struct net_device *ndev, struct device *dev,
1353 name = devm_kasprintf(dev, GFP_KERNEL, "%s:%s", ndev->name, ch);
1356 error = request_irq(irq, handler, 0, name, ndev);
1358 netdev_err(ndev, "cannot request IRQ %s\n", name);
1363 /* Network device open function for Ethernet AVB */
1364 static int ravb_open(struct net_device *ndev)
1366 struct ravb_private *priv = netdev_priv(ndev);
1367 struct platform_device *pdev = priv->pdev;
1368 struct device *dev = &pdev->dev;
1371 napi_enable(&priv->napi[RAVB_BE]);
1372 napi_enable(&priv->napi[RAVB_NC]);
1374 if (priv->chip_id == RCAR_GEN2) {
1375 error = request_irq(ndev->irq, ravb_interrupt, IRQF_SHARED,
1378 netdev_err(ndev, "cannot request IRQ\n");
1382 error = ravb_hook_irq(ndev->irq, ravb_multi_interrupt, ndev,
1386 error = ravb_hook_irq(priv->emac_irq, ravb_emac_interrupt, ndev,
1390 error = ravb_hook_irq(priv->rx_irqs[RAVB_BE], ravb_be_interrupt,
1391 ndev, dev, "ch0:rx_be");
1393 goto out_free_irq_emac;
1394 error = ravb_hook_irq(priv->tx_irqs[RAVB_BE], ravb_be_interrupt,
1395 ndev, dev, "ch18:tx_be");
1397 goto out_free_irq_be_rx;
1398 error = ravb_hook_irq(priv->rx_irqs[RAVB_NC], ravb_nc_interrupt,
1399 ndev, dev, "ch1:rx_nc");
1401 goto out_free_irq_be_tx;
1402 error = ravb_hook_irq(priv->tx_irqs[RAVB_NC], ravb_nc_interrupt,
1403 ndev, dev, "ch19:tx_nc");
1405 goto out_free_irq_nc_rx;
1409 error = ravb_dmac_init(ndev);
1411 goto out_free_irq_nc_tx;
1412 ravb_emac_init(ndev);
1414 /* Initialise PTP Clock driver */
1415 if (priv->chip_id == RCAR_GEN2)
1416 ravb_ptp_init(ndev, priv->pdev);
1418 netif_tx_start_all_queues(ndev);
1420 /* PHY control start */
1421 error = ravb_phy_start(ndev);
1428 /* Stop PTP Clock driver */
1429 if (priv->chip_id == RCAR_GEN2)
1430 ravb_ptp_stop(ndev);
1432 if (priv->chip_id == RCAR_GEN2)
1434 free_irq(priv->tx_irqs[RAVB_NC], ndev);
1436 free_irq(priv->rx_irqs[RAVB_NC], ndev);
1438 free_irq(priv->tx_irqs[RAVB_BE], ndev);
1440 free_irq(priv->rx_irqs[RAVB_BE], ndev);
1442 free_irq(priv->emac_irq, ndev);
1444 free_irq(ndev->irq, ndev);
1446 napi_disable(&priv->napi[RAVB_NC]);
1447 napi_disable(&priv->napi[RAVB_BE]);
1451 /* Timeout function for Ethernet AVB */
1452 static void ravb_tx_timeout(struct net_device *ndev)
1454 struct ravb_private *priv = netdev_priv(ndev);
1456 netif_err(priv, tx_err, ndev,
1457 "transmit timed out, status %08x, resetting...\n",
1458 ravb_read(ndev, ISS));
1460 /* tx_errors count up */
1461 ndev->stats.tx_errors++;
1463 schedule_work(&priv->work);
1466 static void ravb_tx_timeout_work(struct work_struct *work)
1468 struct ravb_private *priv = container_of(work, struct ravb_private,
1470 struct net_device *ndev = priv->ndev;
1472 netif_tx_stop_all_queues(ndev);
1474 /* Stop PTP Clock driver */
1475 if (priv->chip_id == RCAR_GEN2)
1476 ravb_ptp_stop(ndev);
1478 /* Wait for DMA stopping */
1479 ravb_stop_dma(ndev);
1481 ravb_ring_free(ndev, RAVB_BE);
1482 ravb_ring_free(ndev, RAVB_NC);
1485 ravb_dmac_init(ndev);
1486 ravb_emac_init(ndev);
1488 /* Initialise PTP Clock driver */
1489 if (priv->chip_id == RCAR_GEN2)
1490 ravb_ptp_init(ndev, priv->pdev);
1492 netif_tx_start_all_queues(ndev);
1495 /* Packet transmit function for Ethernet AVB */
1496 static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1498 struct ravb_private *priv = netdev_priv(ndev);
1499 u16 q = skb_get_queue_mapping(skb);
1500 struct ravb_tstamp_skb *ts_skb;
1501 struct ravb_tx_desc *desc;
1502 unsigned long flags;
1508 spin_lock_irqsave(&priv->lock, flags);
1509 if (priv->cur_tx[q] - priv->dirty_tx[q] > (priv->num_tx_ring[q] - 1) *
1511 netif_err(priv, tx_queued, ndev,
1512 "still transmitting with the full ring!\n");
1513 netif_stop_subqueue(ndev, q);
1514 spin_unlock_irqrestore(&priv->lock, flags);
1515 return NETDEV_TX_BUSY;
1518 if (skb_put_padto(skb, ETH_ZLEN))
1521 entry = priv->cur_tx[q] % (priv->num_tx_ring[q] * NUM_TX_DESC);
1522 priv->tx_skb[q][entry / NUM_TX_DESC] = skb;
1524 buffer = PTR_ALIGN(priv->tx_align[q], DPTR_ALIGN) +
1525 entry / NUM_TX_DESC * DPTR_ALIGN;
1526 len = PTR_ALIGN(skb->data, DPTR_ALIGN) - skb->data;
1527 /* Zero length DMA descriptors are problematic as they seem to
1528 * terminate DMA transfers. Avoid them by simply using a length of
1529 * DPTR_ALIGN (4) when skb data is aligned to DPTR_ALIGN.
1531 * As skb is guaranteed to have at least ETH_ZLEN (60) bytes of
1532 * data by the call to skb_put_padto() above this is safe with
1533 * respect to both the length of the first DMA descriptor (len)
1534 * overflowing the available data and the length of the second DMA
1535 * descriptor (skb->len - len) being negative.
1540 memcpy(buffer, skb->data, len);
1541 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, DMA_TO_DEVICE);
1542 if (dma_mapping_error(ndev->dev.parent, dma_addr))
1545 desc = &priv->tx_ring[q][entry];
1546 desc->ds_tagl = cpu_to_le16(len);
1547 desc->dptr = cpu_to_le32(dma_addr);
1549 buffer = skb->data + len;
1550 len = skb->len - len;
1551 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, DMA_TO_DEVICE);
1552 if (dma_mapping_error(ndev->dev.parent, dma_addr))
1556 desc->ds_tagl = cpu_to_le16(len);
1557 desc->dptr = cpu_to_le32(dma_addr);
1559 /* TX timestamp required */
1561 ts_skb = kmalloc(sizeof(*ts_skb), GFP_ATOMIC);
1564 dma_unmap_single(ndev->dev.parent, dma_addr, len,
1569 ts_skb->tag = priv->ts_skb_tag++;
1570 priv->ts_skb_tag &= 0x3ff;
1571 list_add_tail(&ts_skb->list, &priv->ts_skb_list);
1573 /* TAG and timestamp required flag */
1574 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1575 desc->tagh_tsr = (ts_skb->tag >> 4) | TX_TSR;
1576 desc->ds_tagl |= le16_to_cpu(ts_skb->tag << 12);
1579 skb_tx_timestamp(skb);
1580 /* Descriptor type must be set after all the above writes */
1582 desc->die_dt = DT_FEND;
1584 desc->die_dt = DT_FSTART;
1586 ravb_modify(ndev, TCCR, TCCR_TSRQ0 << q, TCCR_TSRQ0 << q);
1588 priv->cur_tx[q] += NUM_TX_DESC;
1589 if (priv->cur_tx[q] - priv->dirty_tx[q] >
1590 (priv->num_tx_ring[q] - 1) * NUM_TX_DESC &&
1591 !ravb_tx_free(ndev, q, true))
1592 netif_stop_subqueue(ndev, q);
1596 spin_unlock_irqrestore(&priv->lock, flags);
1597 return NETDEV_TX_OK;
1600 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
1601 le16_to_cpu(desc->ds_tagl), DMA_TO_DEVICE);
1603 dev_kfree_skb_any(skb);
1604 priv->tx_skb[q][entry / NUM_TX_DESC] = NULL;
1608 static u16 ravb_select_queue(struct net_device *ndev, struct sk_buff *skb,
1609 void *accel_priv, select_queue_fallback_t fallback)
1611 /* If skb needs TX timestamp, it is handled in network control queue */
1612 return (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) ? RAVB_NC :
1617 static struct net_device_stats *ravb_get_stats(struct net_device *ndev)
1619 struct ravb_private *priv = netdev_priv(ndev);
1620 struct net_device_stats *nstats, *stats0, *stats1;
1622 nstats = &ndev->stats;
1623 stats0 = &priv->stats[RAVB_BE];
1624 stats1 = &priv->stats[RAVB_NC];
1626 nstats->tx_dropped += ravb_read(ndev, TROCR);
1627 ravb_write(ndev, 0, TROCR); /* (write clear) */
1628 nstats->collisions += ravb_read(ndev, CDCR);
1629 ravb_write(ndev, 0, CDCR); /* (write clear) */
1630 nstats->tx_carrier_errors += ravb_read(ndev, LCCR);
1631 ravb_write(ndev, 0, LCCR); /* (write clear) */
1633 nstats->tx_carrier_errors += ravb_read(ndev, CERCR);
1634 ravb_write(ndev, 0, CERCR); /* (write clear) */
1635 nstats->tx_carrier_errors += ravb_read(ndev, CEECR);
1636 ravb_write(ndev, 0, CEECR); /* (write clear) */
1638 nstats->rx_packets = stats0->rx_packets + stats1->rx_packets;
1639 nstats->tx_packets = stats0->tx_packets + stats1->tx_packets;
1640 nstats->rx_bytes = stats0->rx_bytes + stats1->rx_bytes;
1641 nstats->tx_bytes = stats0->tx_bytes + stats1->tx_bytes;
1642 nstats->multicast = stats0->multicast + stats1->multicast;
1643 nstats->rx_errors = stats0->rx_errors + stats1->rx_errors;
1644 nstats->rx_crc_errors = stats0->rx_crc_errors + stats1->rx_crc_errors;
1645 nstats->rx_frame_errors =
1646 stats0->rx_frame_errors + stats1->rx_frame_errors;
1647 nstats->rx_length_errors =
1648 stats0->rx_length_errors + stats1->rx_length_errors;
1649 nstats->rx_missed_errors =
1650 stats0->rx_missed_errors + stats1->rx_missed_errors;
1651 nstats->rx_over_errors =
1652 stats0->rx_over_errors + stats1->rx_over_errors;
1657 /* Update promiscuous bit */
1658 static void ravb_set_rx_mode(struct net_device *ndev)
1660 struct ravb_private *priv = netdev_priv(ndev);
1661 unsigned long flags;
1663 spin_lock_irqsave(&priv->lock, flags);
1664 ravb_modify(ndev, ECMR, ECMR_PRM,
1665 ndev->flags & IFF_PROMISC ? ECMR_PRM : 0);
1667 spin_unlock_irqrestore(&priv->lock, flags);
1670 /* Device close function for Ethernet AVB */
1671 static int ravb_close(struct net_device *ndev)
1673 struct device_node *np = ndev->dev.parent->of_node;
1674 struct ravb_private *priv = netdev_priv(ndev);
1675 struct ravb_tstamp_skb *ts_skb, *ts_skb2;
1677 netif_tx_stop_all_queues(ndev);
1679 /* Disable interrupts by clearing the interrupt masks. */
1680 ravb_write(ndev, 0, RIC0);
1681 ravb_write(ndev, 0, RIC2);
1682 ravb_write(ndev, 0, TIC);
1684 /* Stop PTP Clock driver */
1685 if (priv->chip_id == RCAR_GEN2)
1686 ravb_ptp_stop(ndev);
1688 /* Set the config mode to stop the AVB-DMAC's processes */
1689 if (ravb_stop_dma(ndev) < 0)
1691 "device will be stopped after h/w processes are done.\n");
1693 /* Clear the timestamp list */
1694 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, list) {
1695 list_del(&ts_skb->list);
1699 /* PHY disconnect */
1701 phy_stop(ndev->phydev);
1702 phy_disconnect(ndev->phydev);
1703 if (of_phy_is_fixed_link(np))
1704 of_phy_deregister_fixed_link(np);
1707 if (priv->chip_id != RCAR_GEN2) {
1708 free_irq(priv->tx_irqs[RAVB_NC], ndev);
1709 free_irq(priv->rx_irqs[RAVB_NC], ndev);
1710 free_irq(priv->tx_irqs[RAVB_BE], ndev);
1711 free_irq(priv->rx_irqs[RAVB_BE], ndev);
1712 free_irq(priv->emac_irq, ndev);
1714 free_irq(ndev->irq, ndev);
1716 napi_disable(&priv->napi[RAVB_NC]);
1717 napi_disable(&priv->napi[RAVB_BE]);
1719 /* Free all the skb's in the RX queue and the DMA buffers. */
1720 ravb_ring_free(ndev, RAVB_BE);
1721 ravb_ring_free(ndev, RAVB_NC);
1726 static int ravb_hwtstamp_get(struct net_device *ndev, struct ifreq *req)
1728 struct ravb_private *priv = netdev_priv(ndev);
1729 struct hwtstamp_config config;
1732 config.tx_type = priv->tstamp_tx_ctrl ? HWTSTAMP_TX_ON :
1734 if (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE_V2_L2_EVENT)
1735 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
1736 else if (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE_ALL)
1737 config.rx_filter = HWTSTAMP_FILTER_ALL;
1739 config.rx_filter = HWTSTAMP_FILTER_NONE;
1741 return copy_to_user(req->ifr_data, &config, sizeof(config)) ?
1745 /* Control hardware time stamping */
1746 static int ravb_hwtstamp_set(struct net_device *ndev, struct ifreq *req)
1748 struct ravb_private *priv = netdev_priv(ndev);
1749 struct hwtstamp_config config;
1750 u32 tstamp_rx_ctrl = RAVB_RXTSTAMP_ENABLED;
1753 if (copy_from_user(&config, req->ifr_data, sizeof(config)))
1756 /* Reserved for future extensions */
1760 switch (config.tx_type) {
1761 case HWTSTAMP_TX_OFF:
1764 case HWTSTAMP_TX_ON:
1765 tstamp_tx_ctrl = RAVB_TXTSTAMP_ENABLED;
1771 switch (config.rx_filter) {
1772 case HWTSTAMP_FILTER_NONE:
1775 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1776 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_V2_L2_EVENT;
1779 config.rx_filter = HWTSTAMP_FILTER_ALL;
1780 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_ALL;
1783 priv->tstamp_tx_ctrl = tstamp_tx_ctrl;
1784 priv->tstamp_rx_ctrl = tstamp_rx_ctrl;
1786 return copy_to_user(req->ifr_data, &config, sizeof(config)) ?
1790 /* ioctl to device function */
1791 static int ravb_do_ioctl(struct net_device *ndev, struct ifreq *req, int cmd)
1793 struct phy_device *phydev = ndev->phydev;
1795 if (!netif_running(ndev))
1803 return ravb_hwtstamp_get(ndev, req);
1805 return ravb_hwtstamp_set(ndev, req);
1808 return phy_mii_ioctl(phydev, req, cmd);
1811 static int ravb_change_mtu(struct net_device *ndev, int new_mtu)
1813 if (netif_running(ndev))
1816 ndev->mtu = new_mtu;
1817 netdev_update_features(ndev);
1822 static void ravb_set_rx_csum(struct net_device *ndev, bool enable)
1824 struct ravb_private *priv = netdev_priv(ndev);
1825 unsigned long flags;
1827 spin_lock_irqsave(&priv->lock, flags);
1829 /* Disable TX and RX */
1830 ravb_rcv_snd_disable(ndev);
1832 /* Modify RX Checksum setting */
1833 ravb_modify(ndev, ECMR, ECMR_RCSC, enable ? ECMR_RCSC : 0);
1835 /* Enable TX and RX */
1836 ravb_rcv_snd_enable(ndev);
1838 spin_unlock_irqrestore(&priv->lock, flags);
1841 static int ravb_set_features(struct net_device *ndev,
1842 netdev_features_t features)
1844 netdev_features_t changed = ndev->features ^ features;
1846 if (changed & NETIF_F_RXCSUM)
1847 ravb_set_rx_csum(ndev, features & NETIF_F_RXCSUM);
1849 ndev->features = features;
1854 static const struct net_device_ops ravb_netdev_ops = {
1855 .ndo_open = ravb_open,
1856 .ndo_stop = ravb_close,
1857 .ndo_start_xmit = ravb_start_xmit,
1858 .ndo_select_queue = ravb_select_queue,
1859 .ndo_get_stats = ravb_get_stats,
1860 .ndo_set_rx_mode = ravb_set_rx_mode,
1861 .ndo_tx_timeout = ravb_tx_timeout,
1862 .ndo_do_ioctl = ravb_do_ioctl,
1863 .ndo_change_mtu = ravb_change_mtu,
1864 .ndo_validate_addr = eth_validate_addr,
1865 .ndo_set_mac_address = eth_mac_addr,
1866 .ndo_set_features = ravb_set_features,
1869 /* MDIO bus init function */
1870 static int ravb_mdio_init(struct ravb_private *priv)
1872 struct platform_device *pdev = priv->pdev;
1873 struct device *dev = &pdev->dev;
1877 priv->mdiobb.ops = &bb_ops;
1879 /* MII controller setting */
1880 priv->mii_bus = alloc_mdio_bitbang(&priv->mdiobb);
1884 /* Hook up MII support for ethtool */
1885 priv->mii_bus->name = "ravb_mii";
1886 priv->mii_bus->parent = dev;
1887 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1888 pdev->name, pdev->id);
1890 /* Register MDIO bus */
1891 error = of_mdiobus_register(priv->mii_bus, dev->of_node);
1898 free_mdio_bitbang(priv->mii_bus);
1902 /* MDIO bus release function */
1903 static int ravb_mdio_release(struct ravb_private *priv)
1905 /* Unregister mdio bus */
1906 mdiobus_unregister(priv->mii_bus);
1908 /* Free bitbang info */
1909 free_mdio_bitbang(priv->mii_bus);
1914 static const struct of_device_id ravb_match_table[] = {
1915 { .compatible = "renesas,etheravb-r8a7790", .data = (void *)RCAR_GEN2 },
1916 { .compatible = "renesas,etheravb-r8a7794", .data = (void *)RCAR_GEN2 },
1917 { .compatible = "renesas,etheravb-rcar-gen2", .data = (void *)RCAR_GEN2 },
1918 { .compatible = "renesas,etheravb-r8a7795", .data = (void *)RCAR_GEN3 },
1919 { .compatible = "renesas,etheravb-rcar-gen3", .data = (void *)RCAR_GEN3 },
1922 MODULE_DEVICE_TABLE(of, ravb_match_table);
1924 static int ravb_set_gti(struct net_device *ndev)
1926 struct ravb_private *priv = netdev_priv(ndev);
1927 struct device *dev = ndev->dev.parent;
1931 rate = clk_get_rate(priv->clk);
1935 inc = 1000000000ULL << 20;
1938 if (inc < GTI_TIV_MIN || inc > GTI_TIV_MAX) {
1939 dev_err(dev, "gti.tiv increment 0x%llx is outside the range 0x%x - 0x%x\n",
1940 inc, GTI_TIV_MIN, GTI_TIV_MAX);
1944 ravb_write(ndev, inc, GTI);
1949 static void ravb_set_config_mode(struct net_device *ndev)
1951 struct ravb_private *priv = netdev_priv(ndev);
1953 if (priv->chip_id == RCAR_GEN2) {
1954 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG);
1955 /* Set CSEL value */
1956 ravb_modify(ndev, CCC, CCC_CSEL, CCC_CSEL_HPB);
1958 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG |
1959 CCC_GAC | CCC_CSEL_HPB);
1963 /* Set tx and rx clock internal delay modes */
1964 static void ravb_set_delay_mode(struct net_device *ndev)
1966 struct ravb_private *priv = netdev_priv(ndev);
1969 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
1970 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID)
1973 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
1974 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID)
1977 ravb_modify(ndev, APSR, APSR_DM, set);
1980 static int ravb_probe(struct platform_device *pdev)
1982 struct device_node *np = pdev->dev.of_node;
1983 struct ravb_private *priv;
1984 enum ravb_chip_id chip_id;
1985 struct net_device *ndev;
1987 struct resource *res;
1992 "this driver is required to be instantiated from device tree\n");
1996 /* Get base address */
1997 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1999 dev_err(&pdev->dev, "invalid resource\n");
2003 ndev = alloc_etherdev_mqs(sizeof(struct ravb_private),
2004 NUM_TX_QUEUE, NUM_RX_QUEUE);
2008 ndev->features = NETIF_F_RXCSUM;
2009 ndev->hw_features = NETIF_F_RXCSUM;
2011 pm_runtime_enable(&pdev->dev);
2012 pm_runtime_get_sync(&pdev->dev);
2014 /* The Ether-specific entries in the device structure. */
2015 ndev->base_addr = res->start;
2017 chip_id = (enum ravb_chip_id)of_device_get_match_data(&pdev->dev);
2019 if (chip_id == RCAR_GEN3)
2020 irq = platform_get_irq_byname(pdev, "ch22");
2022 irq = platform_get_irq(pdev, 0);
2029 SET_NETDEV_DEV(ndev, &pdev->dev);
2031 priv = netdev_priv(ndev);
2034 priv->num_tx_ring[RAVB_BE] = BE_TX_RING_SIZE;
2035 priv->num_rx_ring[RAVB_BE] = BE_RX_RING_SIZE;
2036 priv->num_tx_ring[RAVB_NC] = NC_TX_RING_SIZE;
2037 priv->num_rx_ring[RAVB_NC] = NC_RX_RING_SIZE;
2038 priv->addr = devm_ioremap_resource(&pdev->dev, res);
2039 if (IS_ERR(priv->addr)) {
2040 error = PTR_ERR(priv->addr);
2044 spin_lock_init(&priv->lock);
2045 INIT_WORK(&priv->work, ravb_tx_timeout_work);
2047 priv->phy_interface = of_get_phy_mode(np);
2049 priv->no_avb_link = of_property_read_bool(np, "renesas,no-ether-link");
2050 priv->avb_link_active_low =
2051 of_property_read_bool(np, "renesas,ether-link-active-low");
2053 if (chip_id == RCAR_GEN3) {
2054 irq = platform_get_irq_byname(pdev, "ch24");
2059 priv->emac_irq = irq;
2060 for (i = 0; i < NUM_RX_QUEUE; i++) {
2061 irq = platform_get_irq_byname(pdev, ravb_rx_irqs[i]);
2066 priv->rx_irqs[i] = irq;
2068 for (i = 0; i < NUM_TX_QUEUE; i++) {
2069 irq = platform_get_irq_byname(pdev, ravb_tx_irqs[i]);
2074 priv->tx_irqs[i] = irq;
2078 priv->chip_id = chip_id;
2080 priv->clk = devm_clk_get(&pdev->dev, NULL);
2081 if (IS_ERR(priv->clk)) {
2082 error = PTR_ERR(priv->clk);
2086 ndev->max_mtu = 2048 - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN);
2087 ndev->min_mtu = ETH_MIN_MTU;
2090 ndev->netdev_ops = &ravb_netdev_ops;
2091 ndev->ethtool_ops = &ravb_ethtool_ops;
2093 /* Set AVB config mode */
2094 ravb_set_config_mode(ndev);
2097 error = ravb_set_gti(ndev);
2101 /* Request GTI loading */
2102 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI);
2104 if (priv->chip_id != RCAR_GEN2)
2105 ravb_set_delay_mode(ndev);
2107 /* Allocate descriptor base address table */
2108 priv->desc_bat_size = sizeof(struct ravb_desc) * DBAT_ENTRY_NUM;
2109 priv->desc_bat = dma_alloc_coherent(ndev->dev.parent, priv->desc_bat_size,
2110 &priv->desc_bat_dma, GFP_KERNEL);
2111 if (!priv->desc_bat) {
2113 "Cannot allocate desc base address table (size %d bytes)\n",
2114 priv->desc_bat_size);
2118 for (q = RAVB_BE; q < DBAT_ENTRY_NUM; q++)
2119 priv->desc_bat[q].die_dt = DT_EOS;
2120 ravb_write(ndev, priv->desc_bat_dma, DBAT);
2122 /* Initialise HW timestamp list */
2123 INIT_LIST_HEAD(&priv->ts_skb_list);
2125 /* Initialise PTP Clock driver */
2126 if (chip_id != RCAR_GEN2)
2127 ravb_ptp_init(ndev, pdev);
2129 /* Debug message level */
2130 priv->msg_enable = RAVB_DEF_MSG_ENABLE;
2132 /* Read and set MAC address */
2133 ravb_read_mac_address(ndev, of_get_mac_address(np));
2134 if (!is_valid_ether_addr(ndev->dev_addr)) {
2135 dev_warn(&pdev->dev,
2136 "no valid MAC address supplied, using a random one\n");
2137 eth_hw_addr_random(ndev);
2141 error = ravb_mdio_init(priv);
2143 dev_err(&pdev->dev, "failed to initialize MDIO\n");
2147 netif_napi_add(ndev, &priv->napi[RAVB_BE], ravb_poll, 64);
2148 netif_napi_add(ndev, &priv->napi[RAVB_NC], ravb_poll, 64);
2150 /* Network device register */
2151 error = register_netdev(ndev);
2155 device_set_wakeup_capable(&pdev->dev, 1);
2157 /* Print device information */
2158 netdev_info(ndev, "Base address at %#x, %pM, IRQ %d.\n",
2159 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
2161 platform_set_drvdata(pdev, ndev);
2166 netif_napi_del(&priv->napi[RAVB_NC]);
2167 netif_napi_del(&priv->napi[RAVB_BE]);
2168 ravb_mdio_release(priv);
2170 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat,
2171 priv->desc_bat_dma);
2173 /* Stop PTP Clock driver */
2174 if (chip_id != RCAR_GEN2)
2175 ravb_ptp_stop(ndev);
2179 pm_runtime_put(&pdev->dev);
2180 pm_runtime_disable(&pdev->dev);
2184 static int ravb_remove(struct platform_device *pdev)
2186 struct net_device *ndev = platform_get_drvdata(pdev);
2187 struct ravb_private *priv = netdev_priv(ndev);
2189 /* Stop PTP Clock driver */
2190 if (priv->chip_id != RCAR_GEN2)
2191 ravb_ptp_stop(ndev);
2193 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat,
2194 priv->desc_bat_dma);
2195 /* Set reset mode */
2196 ravb_write(ndev, CCC_OPC_RESET, CCC);
2197 pm_runtime_put_sync(&pdev->dev);
2198 unregister_netdev(ndev);
2199 netif_napi_del(&priv->napi[RAVB_NC]);
2200 netif_napi_del(&priv->napi[RAVB_BE]);
2201 ravb_mdio_release(priv);
2202 pm_runtime_disable(&pdev->dev);
2204 platform_set_drvdata(pdev, NULL);
2209 static int ravb_wol_setup(struct net_device *ndev)
2211 struct ravb_private *priv = netdev_priv(ndev);
2213 /* Disable interrupts by clearing the interrupt masks. */
2214 ravb_write(ndev, 0, RIC0);
2215 ravb_write(ndev, 0, RIC2);
2216 ravb_write(ndev, 0, TIC);
2218 /* Only allow ECI interrupts */
2219 synchronize_irq(priv->emac_irq);
2220 napi_disable(&priv->napi[RAVB_NC]);
2221 napi_disable(&priv->napi[RAVB_BE]);
2222 ravb_write(ndev, ECSIPR_MPDIP, ECSIPR);
2224 /* Enable MagicPacket */
2225 ravb_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE);
2227 return enable_irq_wake(priv->emac_irq);
2230 static int ravb_wol_restore(struct net_device *ndev)
2232 struct ravb_private *priv = netdev_priv(ndev);
2235 napi_enable(&priv->napi[RAVB_NC]);
2236 napi_enable(&priv->napi[RAVB_BE]);
2238 /* Disable MagicPacket */
2239 ravb_modify(ndev, ECMR, ECMR_MPDE, 0);
2241 ret = ravb_close(ndev);
2245 return disable_irq_wake(priv->emac_irq);
2248 static int __maybe_unused ravb_suspend(struct device *dev)
2250 struct net_device *ndev = dev_get_drvdata(dev);
2251 struct ravb_private *priv = netdev_priv(ndev);
2254 if (!netif_running(ndev))
2257 netif_device_detach(ndev);
2259 if (priv->wol_enabled)
2260 ret = ravb_wol_setup(ndev);
2262 ret = ravb_close(ndev);
2267 static int __maybe_unused ravb_resume(struct device *dev)
2269 struct net_device *ndev = dev_get_drvdata(dev);
2270 struct ravb_private *priv = netdev_priv(ndev);
2273 /* If WoL is enabled set reset mode to rearm the WoL logic */
2274 if (priv->wol_enabled)
2275 ravb_write(ndev, CCC_OPC_RESET, CCC);
2277 /* All register have been reset to default values.
2278 * Restore all registers which where setup at probe time and
2279 * reopen device if it was running before system suspended.
2282 /* Set AVB config mode */
2283 ravb_set_config_mode(ndev);
2286 ret = ravb_set_gti(ndev);
2290 /* Request GTI loading */
2291 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI);
2293 if (priv->chip_id != RCAR_GEN2)
2294 ravb_set_delay_mode(ndev);
2296 /* Restore descriptor base address table */
2297 ravb_write(ndev, priv->desc_bat_dma, DBAT);
2299 if (netif_running(ndev)) {
2300 if (priv->wol_enabled) {
2301 ret = ravb_wol_restore(ndev);
2305 ret = ravb_open(ndev);
2308 netif_device_attach(ndev);
2314 static int __maybe_unused ravb_runtime_nop(struct device *dev)
2316 /* Runtime PM callback shared between ->runtime_suspend()
2317 * and ->runtime_resume(). Simply returns success.
2319 * This driver re-initializes all registers after
2320 * pm_runtime_get_sync() anyway so there is no need
2321 * to save and restore registers here.
2326 static const struct dev_pm_ops ravb_dev_pm_ops = {
2327 SET_SYSTEM_SLEEP_PM_OPS(ravb_suspend, ravb_resume)
2328 SET_RUNTIME_PM_OPS(ravb_runtime_nop, ravb_runtime_nop, NULL)
2331 static struct platform_driver ravb_driver = {
2332 .probe = ravb_probe,
2333 .remove = ravb_remove,
2336 .pm = &ravb_dev_pm_ops,
2337 .of_match_table = ravb_match_table,
2341 module_platform_driver(ravb_driver);
2343 MODULE_AUTHOR("Mitsuhiro Kimura, Masaru Nagai");
2344 MODULE_DESCRIPTION("Renesas Ethernet AVB driver");
2345 MODULE_LICENSE("GPL v2");