drivers/net/ethernet/realtek/r8169_phy_config.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * r8169_phy_config.c: RealTek 8169/8168/8101 ethernet driver.
   4  *
   5  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   6  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   7  * Copyright (c) a lot of people too. Please respect their work.
   8  *
   9  * See MAINTAINERS file for support contact information.
  10  */
  11
  12 #include <linux/delay.h>
  13 #include <linux/phy.h>
  14
  15 #include "r8169.h"
  16
  17 typedef void (*rtl_phy_cfg_fct)(struct rtl8169_private *tp,
  18                                 struct phy_device *phydev);
  19
  20 static void r8168d_modify_extpage(struct phy_device *phydev, int extpage,
  21                                   int reg, u16 mask, u16 val)
  22 {
  23         int oldpage = phy_select_page(phydev, 0x0007);
  24
  25         __phy_write(phydev, 0x1e, extpage);
  26         __phy_modify(phydev, reg, mask, val);
  27
  28         phy_restore_page(phydev, oldpage, 0);
  29 }
  30
  31 static void r8168d_phy_param(struct phy_device *phydev, u16 parm,
  32                              u16 mask, u16 val)
  33 {
  34         int oldpage = phy_select_page(phydev, 0x0005);
  35
  36         __phy_write(phydev, 0x05, parm);
  37         __phy_modify(phydev, 0x06, mask, val);
  38
  39         phy_restore_page(phydev, oldpage, 0);
  40 }
  41
  42 static void r8168g_phy_param(struct phy_device *phydev, u16 parm,
  43                              u16 mask, u16 val)
  44 {
  45         int oldpage = phy_select_page(phydev, 0x0a43);
  46
  47         __phy_write(phydev, 0x13, parm);
  48         __phy_modify(phydev, 0x14, mask, val);
  49
  50         phy_restore_page(phydev, oldpage, 0);
  51 }
  52
  53 struct phy_reg {
  54         u16 reg;
  55         u16 val;
  56 };
  57
  58 static void __rtl_writephy_batch(struct phy_device *phydev,
  59                                  const struct phy_reg *regs, int len)
  60 {
  61         phy_lock_mdio_bus(phydev);
  62
  63         while (len-- > 0) {
  64                 __phy_write(phydev, regs->reg, regs->val);
  65                 regs++;
  66         }
  67
  68         phy_unlock_mdio_bus(phydev);
  69 }
  70
  71 #define rtl_writephy_batch(p, a) __rtl_writephy_batch(p, a, ARRAY_SIZE(a))
  72
  73 static void rtl8168f_config_eee_phy(struct phy_device *phydev)
  74 {
  75         r8168d_modify_extpage(phydev, 0x0020, 0x15, 0, BIT(8));
  76         r8168d_phy_param(phydev, 0x8b85, 0, BIT(13));
  77 }
  78
  79 static void rtl8168g_config_eee_phy(struct phy_device *phydev)
  80 {
  81         phy_modify_paged(phydev, 0x0a43, 0x11, 0, BIT(4));
  82 }
  83
  84 static void rtl8168h_config_eee_phy(struct phy_device *phydev)
  85 {
  86         rtl8168g_config_eee_phy(phydev);
  87
  88         phy_modify_paged(phydev, 0xa4a, 0x11, 0x0000, 0x0200);
  89         phy_modify_paged(phydev, 0xa42, 0x14, 0x0000, 0x0080);
  90 }
  91
  92 static void rtl8125a_config_eee_phy(struct phy_device *phydev)
  93 {
  94         rtl8168h_config_eee_phy(phydev);
  95
  96         phy_modify_paged(phydev, 0xa6d, 0x12, 0x0001, 0x0000);
  97         phy_modify_paged(phydev, 0xa6d, 0x14, 0x0010, 0x0000);
  98 }
  99
 100 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp,
 101                                    struct phy_device *phydev)
 102 {
 103         static const struct phy_reg phy_reg_init[] = {
 104                 { 0x1f, 0x0001 },
 105                 { 0x06, 0x006e },
 106                 { 0x08, 0x0708 },
 107                 { 0x15, 0x4000 },
 108                 { 0x18, 0x65c7 },
 109
 110                 { 0x1f, 0x0001 },
 111                 { 0x03, 0x00a1 },
 112                 { 0x02, 0x0008 },
 113                 { 0x01, 0x0120 },
 114                 { 0x00, 0x1000 },
 115                 { 0x04, 0x0800 },
 116                 { 0x04, 0x0000 },
 117
 118                 { 0x03, 0xff41 },
 119                 { 0x02, 0xdf60 },
 120                 { 0x01, 0x0140 },
 121                 { 0x00, 0x0077 },
 122                 { 0x04, 0x7800 },
 123                 { 0x04, 0x7000 },
 124
 125                 { 0x03, 0x802f },
 126                 { 0x02, 0x4f02 },
 127                 { 0x01, 0x0409 },
 128                 { 0x00, 0xf0f9 },
 129                 { 0x04, 0x9800 },
 130                 { 0x04, 0x9000 },
 131
 132                 { 0x03, 0xdf01 },
 133                 { 0x02, 0xdf20 },
 134                 { 0x01, 0xff95 },
 135                 { 0x00, 0xba00 },
 136                 { 0x04, 0xa800 },
 137                 { 0x04, 0xa000 },
 138
 139                 { 0x03, 0xff41 },
 140                 { 0x02, 0xdf20 },
 141                 { 0x01, 0x0140 },
 142                 { 0x00, 0x00bb },
 143                 { 0x04, 0xb800 },
 144                 { 0x04, 0xb000 },
 145
 146                 { 0x03, 0xdf41 },
 147                 { 0x02, 0xdc60 },
 148                 { 0x01, 0x6340 },
 149                 { 0x00, 0x007d },
 150                 { 0x04, 0xd800 },
 151                 { 0x04, 0xd000 },
 152
 153                 { 0x03, 0xdf01 },
 154                 { 0x02, 0xdf20 },
 155                 { 0x01, 0x100a },
 156                 { 0x00, 0xa0ff },
 157                 { 0x04, 0xf800 },
 158                 { 0x04, 0xf000 },
 159
 160                 { 0x1f, 0x0000 },
 161                 { 0x0b, 0x0000 },
 162                 { 0x00, 0x9200 }
 163         };
 164
 165         rtl_writephy_batch(phydev, phy_reg_init);
 166 }
 167
 168 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp,
 169                                     struct phy_device *phydev)
 170 {
 171         phy_write_paged(phydev, 0x0002, 0x01, 0x90d0);
 172 }
 173
 174 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp,
 175                                      struct phy_device *phydev)
 176 {
 177         static const struct phy_reg phy_reg_init[] = {
 178                 { 0x1f, 0x0001 },
 179                 { 0x04, 0x0000 },
 180                 { 0x03, 0x00a1 },
 181                 { 0x02, 0x0008 },
 182                 { 0x01, 0x0120 },
 183                 { 0x00, 0x1000 },
 184                 { 0x04, 0x0800 },
 185                 { 0x04, 0x9000 },
 186                 { 0x03, 0x802f },
 187                 { 0x02, 0x4f02 },
 188                 { 0x01, 0x0409 },
 189                 { 0x00, 0xf099 },
 190                 { 0x04, 0x9800 },
 191                 { 0x04, 0xa000 },
 192                 { 0x03, 0xdf01 },
 193                 { 0x02, 0xdf20 },
 194                 { 0x01, 0xff95 },
 195                 { 0x00, 0xba00 },
 196                 { 0x04, 0xa800 },
 197                 { 0x04, 0xf000 },
 198                 { 0x03, 0xdf01 },
 199                 { 0x02, 0xdf20 },
 200                 { 0x01, 0x101a },
 201                 { 0x00, 0xa0ff },
 202                 { 0x04, 0xf800 },
 203                 { 0x04, 0x0000 },
 204                 { 0x1f, 0x0000 },
 205
 206                 { 0x1f, 0x0001 },
 207                 { 0x10, 0xf41b },
 208                 { 0x14, 0xfb54 },
 209                 { 0x18, 0xf5c7 },
 210                 { 0x1f, 0x0000 },
 211
 212                 { 0x1f, 0x0001 },
 213                 { 0x17, 0x0cc0 },
 214                 { 0x1f, 0x0000 }
 215         };
 216
 217         rtl_writephy_batch(phydev, phy_reg_init);
 218 }
 219
 220 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp,
 221                                      struct phy_device *phydev)
 222 {
 223         static const struct phy_reg phy_reg_init[] = {
 224                 { 0x1f, 0x0001 },
 225                 { 0x04, 0x0000 },
 226                 { 0x03, 0x00a1 },
 227                 { 0x02, 0x0008 },
 228                 { 0x01, 0x0120 },
 229                 { 0x00, 0x1000 },
 230                 { 0x04, 0x0800 },
 231                 { 0x04, 0x9000 },
 232                 { 0x03, 0x802f },
 233                 { 0x02, 0x4f02 },
 234                 { 0x01, 0x0409 },
 235                 { 0x00, 0xf099 },
 236                 { 0x04, 0x9800 },
 237                 { 0x04, 0xa000 },
 238                 { 0x03, 0xdf01 },
 239                 { 0x02, 0xdf20 },
 240                 { 0x01, 0xff95 },
 241                 { 0x00, 0xba00 },
 242                 { 0x04, 0xa800 },
 243                 { 0x04, 0xf000 },
 244                 { 0x03, 0xdf01 },
 245                 { 0x02, 0xdf20 },
 246                 { 0x01, 0x101a },
 247                 { 0x00, 0xa0ff },
 248                 { 0x04, 0xf800 },
 249                 { 0x04, 0x0000 },
 250                 { 0x1f, 0x0000 },
 251
 252                 { 0x1f, 0x0001 },
 253                 { 0x0b, 0x8480 },
 254                 { 0x1f, 0x0000 },
 255
 256                 { 0x1f, 0x0001 },
 257                 { 0x18, 0x67c7 },
 258                 { 0x04, 0x2000 },
 259                 { 0x03, 0x002f },
 260                 { 0x02, 0x4360 },
 261                 { 0x01, 0x0109 },
 262                 { 0x00, 0x3022 },
 263                 { 0x04, 0x2800 },
 264                 { 0x1f, 0x0000 },
 265
 266                 { 0x1f, 0x0001 },
 267                 { 0x17, 0x0cc0 },
 268                 { 0x1f, 0x0000 }
 269         };
 270
 271         rtl_writephy_batch(phydev, phy_reg_init);
 272 }
 273
 274 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp,
 275                                     struct phy_device *phydev)
 276 {
 277         phy_write(phydev, 0x1f, 0x0001);
 278         phy_set_bits(phydev, 0x16, BIT(0));
 279         phy_write(phydev, 0x10, 0xf41b);
 280         phy_write(phydev, 0x1f, 0x0000);
 281 }
 282
 283 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp,
 284                                      struct phy_device *phydev)
 285 {
 286         phy_write_paged(phydev, 0x0001, 0x10, 0xf41b);
 287 }
 288
 289 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp,
 290                                       struct phy_device *phydev)
 291 {
 292         phy_write(phydev, 0x1d, 0x0f00);
 293         phy_write_paged(phydev, 0x0002, 0x0c, 0x1ec8);
 294 }
 295
 296 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp,
 297                                       struct phy_device *phydev)
 298 {
 299         phy_set_bits(phydev, 0x14, BIT(5));
 300         phy_set_bits(phydev, 0x0d, BIT(5));
 301         phy_write_paged(phydev, 0x0001, 0x1d, 0x3d98);
 302 }
 303
 304 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp,
 305                                      struct phy_device *phydev)
 306 {
 307         static const struct phy_reg phy_reg_init[] = {
 308                 { 0x1f, 0x0001 },
 309                 { 0x12, 0x2300 },
 310                 { 0x1f, 0x0002 },
 311                 { 0x00, 0x88d4 },
 312                 { 0x01, 0x82b1 },
 313                 { 0x03, 0x7002 },
 314                 { 0x08, 0x9e30 },
 315                 { 0x09, 0x01f0 },
 316                 { 0x0a, 0x5500 },
 317                 { 0x0c, 0x00c8 },
 318                 { 0x1f, 0x0003 },
 319                 { 0x12, 0xc096 },
 320                 { 0x16, 0x000a },
 321                 { 0x1f, 0x0000 },
 322                 { 0x1f, 0x0000 },
 323                 { 0x09, 0x2000 },
 324                 { 0x09, 0x0000 }
 325         };
 326
 327         rtl_writephy_batch(phydev, phy_reg_init);
 328
 329         phy_set_bits(phydev, 0x14, BIT(5));
 330         phy_set_bits(phydev, 0x0d, BIT(5));
 331 }
 332
 333 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp,
 334                                      struct phy_device *phydev)
 335 {
 336         static const struct phy_reg phy_reg_init[] = {
 337                 { 0x1f, 0x0001 },
 338                 { 0x12, 0x2300 },
 339                 { 0x03, 0x802f },
 340                 { 0x02, 0x4f02 },
 341                 { 0x01, 0x0409 },
 342                 { 0x00, 0xf099 },
 343                 { 0x04, 0x9800 },
 344                 { 0x04, 0x9000 },
 345                 { 0x1d, 0x3d98 },
 346                 { 0x1f, 0x0002 },
 347                 { 0x0c, 0x7eb8 },
 348                 { 0x06, 0x0761 },
 349                 { 0x1f, 0x0003 },
 350                 { 0x16, 0x0f0a },
 351                 { 0x1f, 0x0000 }
 352         };
 353
 354         rtl_writephy_batch(phydev, phy_reg_init);
 355
 356         phy_set_bits(phydev, 0x16, BIT(0));
 357         phy_set_bits(phydev, 0x14, BIT(5));
 358         phy_set_bits(phydev, 0x0d, BIT(5));
 359 }
 360
 361 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp,
 362                                      struct phy_device *phydev)
 363 {
 364         static const struct phy_reg phy_reg_init[] = {
 365                 { 0x1f, 0x0001 },
 366                 { 0x12, 0x2300 },
 367                 { 0x1d, 0x3d98 },
 368                 { 0x1f, 0x0002 },
 369                 { 0x0c, 0x7eb8 },
 370                 { 0x06, 0x5461 },
 371                 { 0x1f, 0x0003 },
 372                 { 0x16, 0x0f0a },
 373                 { 0x1f, 0x0000 }
 374         };
 375
 376         rtl_writephy_batch(phydev, phy_reg_init);
 377
 378         phy_set_bits(phydev, 0x16, BIT(0));
 379         phy_set_bits(phydev, 0x14, BIT(5));
 380         phy_set_bits(phydev, 0x0d, BIT(5));
 381 }
 382
 383 static const struct phy_reg rtl8168d_1_phy_reg_init_0[] = {
 384         /* Channel Estimation */
 385         { 0x1f, 0x0001 },
 386         { 0x06, 0x4064 },
 387         { 0x07, 0x2863 },
 388         { 0x08, 0x059c },
 389         { 0x09, 0x26b4 },
 390         { 0x0a, 0x6a19 },
 391         { 0x0b, 0xdcc8 },
 392         { 0x10, 0xf06d },
 393         { 0x14, 0x7f68 },
 394         { 0x18, 0x7fd9 },
 395         { 0x1c, 0xf0ff },
 396         { 0x1d, 0x3d9c },
 397         { 0x1f, 0x0003 },
 398         { 0x12, 0xf49f },
 399         { 0x13, 0x070b },
 400         { 0x1a, 0x05ad },
 401         { 0x14, 0x94c0 },
 402
 403         /*
 404          * Tx Error Issue
 405          * Enhance line driver power
 406          */
 407         { 0x1f, 0x0002 },
 408         { 0x06, 0x5561 },
 409         { 0x1f, 0x0005 },
 410         { 0x05, 0x8332 },
 411         { 0x06, 0x5561 },
 412
 413         /*
 414          * Can not link to 1Gbps with bad cable
 415          * Decrease SNR threshold form 21.07dB to 19.04dB
 416          */
 417         { 0x1f, 0x0001 },
 418         { 0x17, 0x0cc0 },
 419
 420         { 0x1f, 0x0000 },
 421         { 0x0d, 0xf880 }
 422 };
 423
 424 static const struct phy_reg rtl8168d_1_phy_reg_init_1[] = {
 425         { 0x1f, 0x0002 },
 426         { 0x05, 0x669a },
 427         { 0x1f, 0x0005 },
 428         { 0x05, 0x8330 },
 429         { 0x06, 0x669a },
 430         { 0x1f, 0x0002 }
 431 };
 432
 433 static void rtl8168d_apply_firmware_cond(struct rtl8169_private *tp,
 434                                          struct phy_device *phydev,
 435                                          u16 val)
 436 {
 437         u16 reg_val;
 438
 439         phy_write(phydev, 0x1f, 0x0005);
 440         phy_write(phydev, 0x05, 0x001b);
 441         reg_val = phy_read(phydev, 0x06);
 442         phy_write(phydev, 0x1f, 0x0000);
 443
 444         if (reg_val != val)
 445                 phydev_warn(phydev, "chipset not ready for firmware\n");
 446         else
 447                 r8169_apply_firmware(tp);
 448 }
 449
 450 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp,
 451                                      struct phy_device *phydev)
 452 {
 453         rtl_writephy_batch(phydev, rtl8168d_1_phy_reg_init_0);
 454
 455         /*
 456          * Rx Error Issue
 457          * Fine Tune Switching regulator parameter
 458          */
 459         phy_write(phydev, 0x1f, 0x0002);
 460         phy_modify(phydev, 0x0b, 0x00ef, 0x0010);
 461         phy_modify(phydev, 0x0c, 0x5d00, 0xa200);
 462
 463         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
 464                 int val;
 465
 466                 rtl_writephy_batch(phydev, rtl8168d_1_phy_reg_init_1);
 467
 468                 val = phy_read(phydev, 0x0d);
 469
 470                 if ((val & 0x00ff) != 0x006c) {
 471                         static const u32 set[] = {
 472                                 0x0065, 0x0066, 0x0067, 0x0068,
 473                                 0x0069, 0x006a, 0x006b, 0x006c
 474                         };
 475                         int i;
 476
 477                         phy_write(phydev, 0x1f, 0x0002);
 478
 479                         val &= 0xff00;
 480                         for (i = 0; i < ARRAY_SIZE(set); i++)
 481                                 phy_write(phydev, 0x0d, val | set[i]);
 482                 }
 483         } else {
 484                 phy_write_paged(phydev, 0x0002, 0x05, 0x6662);
 485                 r8168d_phy_param(phydev, 0x8330, 0xffff, 0x6662);
 486         }
 487
 488         /* RSET couple improve */
 489         phy_write(phydev, 0x1f, 0x0002);
 490         phy_set_bits(phydev, 0x0d, 0x0300);
 491         phy_set_bits(phydev, 0x0f, 0x0010);
 492
 493         /* Fine tune PLL performance */
 494         phy_write(phydev, 0x1f, 0x0002);
 495         phy_modify(phydev, 0x02, 0x0600, 0x0100);
 496         phy_clear_bits(phydev, 0x03, 0xe000);
 497         phy_write(phydev, 0x1f, 0x0000);
 498
 499         rtl8168d_apply_firmware_cond(tp, phydev, 0xbf00);
 500 }
 501
 502 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp,
 503                                      struct phy_device *phydev)
 504 {
 505         rtl_writephy_batch(phydev, rtl8168d_1_phy_reg_init_0);
 506
 507         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
 508                 int val;
 509
 510                 rtl_writephy_batch(phydev, rtl8168d_1_phy_reg_init_1);
 511
 512                 val = phy_read(phydev, 0x0d);
 513                 if ((val & 0x00ff) != 0x006c) {
 514                         static const u32 set[] = {
 515                                 0x0065, 0x0066, 0x0067, 0x0068,
 516                                 0x0069, 0x006a, 0x006b, 0x006c
 517                         };
 518                         int i;
 519
 520                         phy_write(phydev, 0x1f, 0x0002);
 521
 522                         val &= 0xff00;
 523                         for (i = 0; i < ARRAY_SIZE(set); i++)
 524                                 phy_write(phydev, 0x0d, val | set[i]);
 525                 }
 526         } else {
 527                 phy_write_paged(phydev, 0x0002, 0x05, 0x2642);
 528                 r8168d_phy_param(phydev, 0x8330, 0xffff, 0x2642);
 529         }
 530
 531         /* Fine tune PLL performance */
 532         phy_write(phydev, 0x1f, 0x0002);
 533         phy_modify(phydev, 0x02, 0x0600, 0x0100);
 534         phy_clear_bits(phydev, 0x03, 0xe000);
 535         phy_write(phydev, 0x1f, 0x0000);
 536
 537         /* Switching regulator Slew rate */
 538         phy_modify_paged(phydev, 0x0002, 0x0f, 0x0000, 0x0017);
 539
 540         rtl8168d_apply_firmware_cond(tp, phydev, 0xb300);
 541 }
 542
 543 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp,
 544                                      struct phy_device *phydev)
 545 {
 546         static const struct phy_reg phy_reg_init[] = {
 547                 { 0x1f, 0x0002 },
 548                 { 0x10, 0x0008 },
 549                 { 0x0d, 0x006c },
 550
 551                 { 0x1f, 0x0000 },
 552                 { 0x0d, 0xf880 },
 553
 554                 { 0x1f, 0x0001 },
 555                 { 0x17, 0x0cc0 },
 556
 557                 { 0x1f, 0x0001 },
 558                 { 0x0b, 0xa4d8 },
 559                 { 0x09, 0x281c },
 560                 { 0x07, 0x2883 },
 561                 { 0x0a, 0x6b35 },
 562                 { 0x1d, 0x3da4 },
 563                 { 0x1c, 0xeffd },
 564                 { 0x14, 0x7f52 },
 565                 { 0x18, 0x7fc6 },
 566                 { 0x08, 0x0601 },
 567                 { 0x06, 0x4063 },
 568                 { 0x10, 0xf074 },
 569                 { 0x1f, 0x0003 },
 570                 { 0x13, 0x0789 },
 571                 { 0x12, 0xf4bd },
 572                 { 0x1a, 0x04fd },
 573                 { 0x14, 0x84b0 },
 574                 { 0x1f, 0x0000 },
 575                 { 0x00, 0x9200 },
 576
 577                 { 0x1f, 0x0005 },
 578                 { 0x01, 0x0340 },
 579                 { 0x1f, 0x0001 },
 580                 { 0x04, 0x4000 },
 581                 { 0x03, 0x1d21 },
 582                 { 0x02, 0x0c32 },
 583                 { 0x01, 0x0200 },
 584                 { 0x00, 0x5554 },
 585                 { 0x04, 0x4800 },
 586                 { 0x04, 0x4000 },
 587                 { 0x04, 0xf000 },
 588                 { 0x03, 0xdf01 },
 589                 { 0x02, 0xdf20 },
 590                 { 0x01, 0x101a },
 591                 { 0x00, 0xa0ff },
 592                 { 0x04, 0xf800 },
 593                 { 0x04, 0xf000 },
 594                 { 0x1f, 0x0000 },
 595         };
 596
 597         rtl_writephy_batch(phydev, phy_reg_init);
 598         r8168d_modify_extpage(phydev, 0x0023, 0x16, 0xffff, 0x0000);
 599 }
 600
 601 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp,
 602                                      struct phy_device *phydev)
 603 {
 604         phy_write_paged(phydev, 0x0001, 0x17, 0x0cc0);
 605         r8168d_modify_extpage(phydev, 0x002d, 0x18, 0xffff, 0x0040);
 606         phy_set_bits(phydev, 0x0d, BIT(5));
 607 }
 608
 609 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp,
 610                                      struct phy_device *phydev)
 611 {
 612         static const struct phy_reg phy_reg_init[] = {
 613                 /* Channel estimation fine tune */
 614                 { 0x1f, 0x0001 },
 615                 { 0x0b, 0x6c20 },
 616                 { 0x07, 0x2872 },
 617                 { 0x1c, 0xefff },
 618                 { 0x1f, 0x0003 },
 619                 { 0x14, 0x6420 },
 620                 { 0x1f, 0x0000 },
 621         };
 622
 623         r8169_apply_firmware(tp);
 624
 625         /* Enable Delay cap */
 626         r8168d_phy_param(phydev, 0x8b80, 0xffff, 0xc896);
 627
 628         rtl_writephy_batch(phydev, phy_reg_init);
 629
 630         /* Update PFM & 10M TX idle timer */
 631         r8168d_modify_extpage(phydev, 0x002f, 0x15, 0xffff, 0x1919);
 632
 633         r8168d_modify_extpage(phydev, 0x00ac, 0x18, 0xffff, 0x0006);
 634
 635         /* DCO enable for 10M IDLE Power */
 636         r8168d_modify_extpage(phydev, 0x0023, 0x17, 0x0000, 0x0006);
 637
 638         /* For impedance matching */
 639         phy_modify_paged(phydev, 0x0002, 0x08, 0x7f00, 0x8000);
 640
 641         /* PHY auto speed down */
 642         r8168d_modify_extpage(phydev, 0x002d, 0x18, 0x0000, 0x0050);
 643         phy_set_bits(phydev, 0x14, BIT(15));
 644
 645         r8168d_phy_param(phydev, 0x8b86, 0x0000, 0x0001);
 646         r8168d_phy_param(phydev, 0x8b85, 0x2000, 0x0000);
 647
 648         r8168d_modify_extpage(phydev, 0x0020, 0x15, 0x1100, 0x0000);
 649         phy_write_paged(phydev, 0x0006, 0x00, 0x5a00);
 650
 651         phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0x0000);
 652 }
 653
 654 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp,
 655                                      struct phy_device *phydev)
 656 {
 657         r8169_apply_firmware(tp);
 658
 659         /* Enable Delay cap */
 660         r8168d_modify_extpage(phydev, 0x00ac, 0x18, 0xffff, 0x0006);
 661
 662         /* Channel estimation fine tune */
 663         phy_write_paged(phydev, 0x0003, 0x09, 0xa20f);
 664
 665         /* Green Setting */
 666         r8168d_phy_param(phydev, 0x8b5b, 0xffff, 0x9222);
 667         r8168d_phy_param(phydev, 0x8b6d, 0xffff, 0x8000);
 668         r8168d_phy_param(phydev, 0x8b76, 0xffff, 0x8000);
 669
 670         /* For 4-corner performance improve */
 671         phy_write(phydev, 0x1f, 0x0005);
 672         phy_write(phydev, 0x05, 0x8b80);
 673         phy_set_bits(phydev, 0x17, 0x0006);
 674         phy_write(phydev, 0x1f, 0x0000);
 675
 676         /* PHY auto speed down */
 677         r8168d_modify_extpage(phydev, 0x002d, 0x18, 0x0000, 0x0010);
 678         phy_set_bits(phydev, 0x14, BIT(15));
 679
 680         /* improve 10M EEE waveform */
 681         r8168d_phy_param(phydev, 0x8b86, 0x0000, 0x0001);
 682
 683         /* Improve 2-pair detection performance */
 684         r8168d_phy_param(phydev, 0x8b85, 0x0000, 0x4000);
 685
 686         rtl8168f_config_eee_phy(phydev);
 687
 688         /* Green feature */
 689         phy_write(phydev, 0x1f, 0x0003);
 690         phy_set_bits(phydev, 0x19, BIT(0));
 691         phy_set_bits(phydev, 0x10, BIT(10));
 692         phy_write(phydev, 0x1f, 0x0000);
 693         phy_modify_paged(phydev, 0x0005, 0x01, 0, BIT(8));
 694 }
 695
 696 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp,
 697                                    struct phy_device *phydev)
 698 {
 699         /* For 4-corner performance improve */
 700         r8168d_phy_param(phydev, 0x8b80, 0x0000, 0x0006);
 701
 702         /* PHY auto speed down */
 703         r8168d_modify_extpage(phydev, 0x002d, 0x18, 0x0000, 0x0010);
 704         phy_set_bits(phydev, 0x14, BIT(15));
 705
 706         /* Improve 10M EEE waveform */
 707         r8168d_phy_param(phydev, 0x8b86, 0x0000, 0x0001);
 708
 709         rtl8168f_config_eee_phy(phydev);
 710 }
 711
 712 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp,
 713                                      struct phy_device *phydev)
 714 {
 715         r8169_apply_firmware(tp);
 716
 717         /* Channel estimation fine tune */
 718         phy_write_paged(phydev, 0x0003, 0x09, 0xa20f);
 719
 720         /* Modify green table for giga & fnet */
 721         r8168d_phy_param(phydev, 0x8b55, 0xffff, 0x0000);
 722         r8168d_phy_param(phydev, 0x8b5e, 0xffff, 0x0000);
 723         r8168d_phy_param(phydev, 0x8b67, 0xffff, 0x0000);
 724         r8168d_phy_param(phydev, 0x8b70, 0xffff, 0x0000);
 725         r8168d_modify_extpage(phydev, 0x0078, 0x17, 0xffff, 0x0000);
 726         r8168d_modify_extpage(phydev, 0x0078, 0x19, 0xffff, 0x00fb);
 727
 728         /* Modify green table for 10M */
 729         r8168d_phy_param(phydev, 0x8b79, 0xffff, 0xaa00);
 730
 731         /* Disable hiimpedance detection (RTCT) */
 732         phy_write_paged(phydev, 0x0003, 0x01, 0x328a);
 733
 734         rtl8168f_hw_phy_config(tp, phydev);
 735
 736         /* Improve 2-pair detection performance */
 737         r8168d_phy_param(phydev, 0x8b85, 0x0000, 0x4000);
 738 }
 739
 740 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp,
 741                                      struct phy_device *phydev)
 742 {
 743         r8169_apply_firmware(tp);
 744
 745         rtl8168f_hw_phy_config(tp, phydev);
 746 }
 747
 748 static void rtl8411_hw_phy_config(struct rtl8169_private *tp,
 749                                   struct phy_device *phydev)
 750 {
 751         r8169_apply_firmware(tp);
 752
 753         rtl8168f_hw_phy_config(tp, phydev);
 754
 755         /* Improve 2-pair detection performance */
 756         r8168d_phy_param(phydev, 0x8b85, 0x0000, 0x4000);
 757
 758         /* Channel estimation fine tune */
 759         phy_write_paged(phydev, 0x0003, 0x09, 0xa20f);
 760
 761         /* Modify green table for giga & fnet */
 762         r8168d_phy_param(phydev, 0x8b55, 0xffff, 0x0000);
 763         r8168d_phy_param(phydev, 0x8b5e, 0xffff, 0x0000);
 764         r8168d_phy_param(phydev, 0x8b67, 0xffff, 0x0000);
 765         r8168d_phy_param(phydev, 0x8b70, 0xffff, 0x0000);
 766         r8168d_modify_extpage(phydev, 0x0078, 0x17, 0xffff, 0x0000);
 767         r8168d_modify_extpage(phydev, 0x0078, 0x19, 0xffff, 0x00aa);
 768
 769         /* Modify green table for 10M */
 770         r8168d_phy_param(phydev, 0x8b79, 0xffff, 0xaa00);
 771
 772         /* Disable hiimpedance detection (RTCT) */
 773         phy_write_paged(phydev, 0x0003, 0x01, 0x328a);
 774
 775         /* Modify green table for giga */
 776         r8168d_phy_param(phydev, 0x8b54, 0x0800, 0x0000);
 777         r8168d_phy_param(phydev, 0x8b5d, 0x0800, 0x0000);
 778         r8168d_phy_param(phydev, 0x8a7c, 0x0100, 0x0000);
 779         r8168d_phy_param(phydev, 0x8a7f, 0x0000, 0x0100);
 780         r8168d_phy_param(phydev, 0x8a82, 0x0100, 0x0000);
 781         r8168d_phy_param(phydev, 0x8a85, 0x0100, 0x0000);
 782         r8168d_phy_param(phydev, 0x8a88, 0x0100, 0x0000);
 783
 784         /* uc same-seed solution */
 785         r8168d_phy_param(phydev, 0x8b85, 0x0000, 0x8000);
 786
 787         /* Green feature */
 788         phy_write(phydev, 0x1f, 0x0003);
 789         phy_clear_bits(phydev, 0x19, BIT(0));
 790         phy_clear_bits(phydev, 0x10, BIT(10));
 791         phy_write(phydev, 0x1f, 0x0000);
 792 }
 793
 794 static void rtl8168g_disable_aldps(struct phy_device *phydev)
 795 {
 796         phy_modify_paged(phydev, 0x0a43, 0x10, BIT(2), 0);
 797 }
 798
 799 static void rtl8168g_enable_gphy_10m(struct phy_device *phydev)
 800 {
 801         phy_modify_paged(phydev, 0x0a44, 0x11, 0, BIT(11));
 802 }
 803
 804 static void rtl8168g_phy_adjust_10m_aldps(struct phy_device *phydev)
 805 {
 806         phy_modify_paged(phydev, 0x0bcc, 0x14, BIT(8), 0);
 807         phy_modify_paged(phydev, 0x0a44, 0x11, 0, BIT(7) | BIT(6));
 808         r8168g_phy_param(phydev, 0x8084, 0x6000, 0x0000);
 809         phy_modify_paged(phydev, 0x0a43, 0x10, 0x0000, 0x1003);
 810 }
 811
 812 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp,
 813                                      struct phy_device *phydev)
 814 {
 815         int ret;
 816
 817         r8169_apply_firmware(tp);
 818
 819         ret = phy_read_paged(phydev, 0x0a46, 0x10);
 820         if (ret & BIT(8))
 821                 phy_modify_paged(phydev, 0x0bcc, 0x12, BIT(15), 0);
 822         else
 823                 phy_modify_paged(phydev, 0x0bcc, 0x12, 0, BIT(15));
 824
 825         ret = phy_read_paged(phydev, 0x0a46, 0x13);
 826         if (ret & BIT(8))
 827                 phy_modify_paged(phydev, 0x0c41, 0x15, 0, BIT(1));
 828         else
 829                 phy_modify_paged(phydev, 0x0c41, 0x15, BIT(1), 0);
 830
 831         /* Enable PHY auto speed down */
 832         phy_modify_paged(phydev, 0x0a44, 0x11, 0, BIT(3) | BIT(2));
 833
 834         rtl8168g_phy_adjust_10m_aldps(phydev);
 835
 836         /* EEE auto-fallback function */
 837         phy_modify_paged(phydev, 0x0a4b, 0x11, 0, BIT(2));
 838
 839         /* Enable UC LPF tune function */
 840         r8168g_phy_param(phydev, 0x8012, 0x0000, 0x8000);
 841
 842         phy_modify_paged(phydev, 0x0c42, 0x11, BIT(13), BIT(14));
 843
 844         /* Improve SWR Efficiency */
 845         phy_write(phydev, 0x1f, 0x0bcd);
 846         phy_write(phydev, 0x14, 0x5065);
 847         phy_write(phydev, 0x14, 0xd065);
 848         phy_write(phydev, 0x1f, 0x0bc8);
 849         phy_write(phydev, 0x11, 0x5655);
 850         phy_write(phydev, 0x1f, 0x0bcd);
 851         phy_write(phydev, 0x14, 0x1065);
 852         phy_write(phydev, 0x14, 0x9065);
 853         phy_write(phydev, 0x14, 0x1065);
 854         phy_write(phydev, 0x1f, 0x0000);
 855
 856         rtl8168g_disable_aldps(phydev);
 857         rtl8168g_config_eee_phy(phydev);
 858 }
 859
 860 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp,
 861                                      struct phy_device *phydev)
 862 {
 863         r8169_apply_firmware(tp);
 864         rtl8168g_config_eee_phy(phydev);
 865 }
 866
 867 static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp,
 868                                      struct phy_device *phydev)
 869 {
 870         u16 dout_tapbin;
 871         u32 data;
 872
 873         r8169_apply_firmware(tp);
 874
 875         /* CHN EST parameters adjust - giga master */
 876         r8168g_phy_param(phydev, 0x809b, 0xf800, 0x8000);
 877         r8168g_phy_param(phydev, 0x80a2, 0xff00, 0x8000);
 878         r8168g_phy_param(phydev, 0x80a4, 0xff00, 0x8500);
 879         r8168g_phy_param(phydev, 0x809c, 0xff00, 0xbd00);
 880
 881         /* CHN EST parameters adjust - giga slave */
 882         r8168g_phy_param(phydev, 0x80ad, 0xf800, 0x7000);
 883         r8168g_phy_param(phydev, 0x80b4, 0xff00, 0x5000);
 884         r8168g_phy_param(phydev, 0x80ac, 0xff00, 0x4000);
 885
 886         /* CHN EST parameters adjust - fnet */
 887         r8168g_phy_param(phydev, 0x808e, 0xff00, 0x1200);
 888         r8168g_phy_param(phydev, 0x8090, 0xff00, 0xe500);
 889         r8168g_phy_param(phydev, 0x8092, 0xff00, 0x9f00);
 890
 891         /* enable R-tune & PGA-retune function */
 892         dout_tapbin = 0;
 893         data = phy_read_paged(phydev, 0x0a46, 0x13);
 894         data &= 3;
 895         data <<= 2;
 896         dout_tapbin |= data;
 897         data = phy_read_paged(phydev, 0x0a46, 0x12);
 898         data &= 0xc000;
 899         data >>= 14;
 900         dout_tapbin |= data;
 901         dout_tapbin = ~(dout_tapbin ^ 0x08);
 902         dout_tapbin <<= 12;
 903         dout_tapbin &= 0xf000;
 904
 905         r8168g_phy_param(phydev, 0x827a, 0xf000, dout_tapbin);
 906         r8168g_phy_param(phydev, 0x827b, 0xf000, dout_tapbin);
 907         r8168g_phy_param(phydev, 0x827c, 0xf000, dout_tapbin);
 908         r8168g_phy_param(phydev, 0x827d, 0xf000, dout_tapbin);
 909         r8168g_phy_param(phydev, 0x0811, 0x0000, 0x0800);
 910         phy_modify_paged(phydev, 0x0a42, 0x16, 0x0000, 0x0002);
 911
 912         rtl8168g_enable_gphy_10m(phydev);
 913
 914         /* SAR ADC performance */
 915         phy_modify_paged(phydev, 0x0bca, 0x17, BIT(12) | BIT(13), BIT(14));
 916
 917         r8168g_phy_param(phydev, 0x803f, 0x3000, 0x0000);
 918         r8168g_phy_param(phydev, 0x8047, 0x3000, 0x0000);
 919         r8168g_phy_param(phydev, 0x804f, 0x3000, 0x0000);
 920         r8168g_phy_param(phydev, 0x8057, 0x3000, 0x0000);
 921         r8168g_phy_param(phydev, 0x805f, 0x3000, 0x0000);
 922         r8168g_phy_param(phydev, 0x8067, 0x3000, 0x0000);
 923         r8168g_phy_param(phydev, 0x806f, 0x3000, 0x0000);
 924
 925         /* disable phy pfm mode */
 926         phy_modify_paged(phydev, 0x0a44, 0x11, BIT(7), 0);
 927
 928         rtl8168g_disable_aldps(phydev);
 929         rtl8168h_config_eee_phy(phydev);
 930 }
 931
 932 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp,
 933                                      struct phy_device *phydev)
 934 {
 935         u16 ioffset, rlen;
 936         u32 data;
 937
 938         r8169_apply_firmware(tp);
 939
 940         /* CHIN EST parameter update */
 941         r8168g_phy_param(phydev, 0x808a, 0x003f, 0x000a);
 942
 943         /* enable R-tune & PGA-retune function */
 944         r8168g_phy_param(phydev, 0x0811, 0x0000, 0x0800);
 945         phy_modify_paged(phydev, 0x0a42, 0x16, 0x0000, 0x0002);
 946
 947         rtl8168g_enable_gphy_10m(phydev);
 948
 949         ioffset = rtl8168h_2_get_adc_bias_ioffset(tp);
 950         if (ioffset != 0xffff)
 951                 phy_write_paged(phydev, 0x0bcf, 0x16, ioffset);
 952
 953         /* Modify rlen (TX LPF corner frequency) level */
 954         data = phy_read_paged(phydev, 0x0bcd, 0x16);
 955         data &= 0x000f;
 956         rlen = 0;
 957         if (data > 3)
 958                 rlen = data - 3;
 959         data = rlen | (rlen << 4) | (rlen << 8) | (rlen << 12);
 960         phy_write_paged(phydev, 0x0bcd, 0x17, data);
 961
 962         /* disable phy pfm mode */
 963         phy_modify_paged(phydev, 0x0a44, 0x11, BIT(7), 0);
 964
 965         rtl8168g_disable_aldps(phydev);
 966         rtl8168g_config_eee_phy(phydev);
 967 }
 968
 969 static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp,
 970                                       struct phy_device *phydev)
 971 {
 972         /* Enable PHY auto speed down */
 973         phy_modify_paged(phydev, 0x0a44, 0x11, 0, BIT(3) | BIT(2));
 974
 975         rtl8168g_phy_adjust_10m_aldps(phydev);
 976
 977         /* Enable EEE auto-fallback function */
 978         phy_modify_paged(phydev, 0x0a4b, 0x11, 0, BIT(2));
 979
 980         /* Enable UC LPF tune function */
 981         r8168g_phy_param(phydev, 0x8012, 0x0000, 0x8000);
 982
 983         /* set rg_sel_sdm_rate */
 984         phy_modify_paged(phydev, 0x0c42, 0x11, BIT(13), BIT(14));
 985
 986         rtl8168g_disable_aldps(phydev);
 987         rtl8168g_config_eee_phy(phydev);
 988 }
 989
 990 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp,
 991                                       struct phy_device *phydev)
 992 {
 993         rtl8168g_phy_adjust_10m_aldps(phydev);
 994
 995         /* Enable UC LPF tune function */
 996         r8168g_phy_param(phydev, 0x8012, 0x0000, 0x8000);
 997
 998         /* Set rg_sel_sdm_rate */
 999         phy_modify_paged(phydev, 0x0c42, 0x11, BIT(13), BIT(14));
1000
1001         /* Channel estimation parameters */
1002         r8168g_phy_param(phydev, 0x80f3, 0xff00, 0x8b00);
1003         r8168g_phy_param(phydev, 0x80f0, 0xff00, 0x3a00);
1004         r8168g_phy_param(phydev, 0x80ef, 0xff00, 0x0500);
1005         r8168g_phy_param(phydev, 0x80f6, 0xff00, 0x6e00);
1006         r8168g_phy_param(phydev, 0x80ec, 0xff00, 0x6800);
1007         r8168g_phy_param(phydev, 0x80ed, 0xff00, 0x7c00);
1008         r8168g_phy_param(phydev, 0x80f2, 0xff00, 0xf400);
1009         r8168g_phy_param(phydev, 0x80f4, 0xff00, 0x8500);
1010         r8168g_phy_param(phydev, 0x8110, 0xff00, 0xa800);
1011         r8168g_phy_param(phydev, 0x810f, 0xff00, 0x1d00);
1012         r8168g_phy_param(phydev, 0x8111, 0xff00, 0xf500);
1013         r8168g_phy_param(phydev, 0x8113, 0xff00, 0x6100);
1014         r8168g_phy_param(phydev, 0x8115, 0xff00, 0x9200);
1015         r8168g_phy_param(phydev, 0x810e, 0xff00, 0x0400);
1016         r8168g_phy_param(phydev, 0x810c, 0xff00, 0x7c00);
1017         r8168g_phy_param(phydev, 0x810b, 0xff00, 0x5a00);
1018         r8168g_phy_param(phydev, 0x80d1, 0xff00, 0xff00);
1019         r8168g_phy_param(phydev, 0x80cd, 0xff00, 0x9e00);
1020         r8168g_phy_param(phydev, 0x80d3, 0xff00, 0x0e00);
1021         r8168g_phy_param(phydev, 0x80d5, 0xff00, 0xca00);
1022         r8168g_phy_param(phydev, 0x80d7, 0xff00, 0x8400);
1023
1024         /* Force PWM-mode */
1025         phy_write(phydev, 0x1f, 0x0bcd);
1026         phy_write(phydev, 0x14, 0x5065);
1027         phy_write(phydev, 0x14, 0xd065);
1028         phy_write(phydev, 0x1f, 0x0bc8);
1029         phy_write(phydev, 0x12, 0x00ed);
1030         phy_write(phydev, 0x1f, 0x0bcd);
1031         phy_write(phydev, 0x14, 0x1065);
1032         phy_write(phydev, 0x14, 0x9065);
1033         phy_write(phydev, 0x14, 0x1065);
1034         phy_write(phydev, 0x1f, 0x0000);
1035
1036         rtl8168g_disable_aldps(phydev);
1037         rtl8168g_config_eee_phy(phydev);
1038 }
1039
1040 static void rtl8117_hw_phy_config(struct rtl8169_private *tp,
1041                                   struct phy_device *phydev)
1042 {
1043         /* CHN EST parameters adjust - fnet */
1044         r8168g_phy_param(phydev, 0x808e, 0xff00, 0x4800);
1045         r8168g_phy_param(phydev, 0x8090, 0xff00, 0xcc00);
1046         r8168g_phy_param(phydev, 0x8092, 0xff00, 0xb000);
1047
1048         r8168g_phy_param(phydev, 0x8088, 0xff00, 0x6000);
1049         r8168g_phy_param(phydev, 0x808b, 0x3f00, 0x0b00);
1050         r8168g_phy_param(phydev, 0x808d, 0x1f00, 0x0600);
1051         r8168g_phy_param(phydev, 0x808c, 0xff00, 0xb000);
1052         r8168g_phy_param(phydev, 0x80a0, 0xff00, 0x2800);
1053         r8168g_phy_param(phydev, 0x80a2, 0xff00, 0x5000);
1054         r8168g_phy_param(phydev, 0x809b, 0xf800, 0xb000);
1055         r8168g_phy_param(phydev, 0x809a, 0xff00, 0x4b00);
1056         r8168g_phy_param(phydev, 0x809d, 0x3f00, 0x0800);
1057         r8168g_phy_param(phydev, 0x80a1, 0xff00, 0x7000);
1058         r8168g_phy_param(phydev, 0x809f, 0x1f00, 0x0300);
1059         r8168g_phy_param(phydev, 0x809e, 0xff00, 0x8800);
1060         r8168g_phy_param(phydev, 0x80b2, 0xff00, 0x2200);
1061         r8168g_phy_param(phydev, 0x80ad, 0xf800, 0x9800);
1062         r8168g_phy_param(phydev, 0x80af, 0x3f00, 0x0800);
1063         r8168g_phy_param(phydev, 0x80b3, 0xff00, 0x6f00);
1064         r8168g_phy_param(phydev, 0x80b1, 0x1f00, 0x0300);
1065         r8168g_phy_param(phydev, 0x80b0, 0xff00, 0x9300);
1066
1067         r8168g_phy_param(phydev, 0x8011, 0x0000, 0x0800);
1068
1069         rtl8168g_enable_gphy_10m(phydev);
1070
1071         r8168g_phy_param(phydev, 0x8016, 0x0000, 0x0400);
1072
1073         rtl8168g_disable_aldps(phydev);
1074         rtl8168h_config_eee_phy(phydev);
1075 }
1076
1077 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp,
1078                                    struct phy_device *phydev)
1079 {
1080         static const struct phy_reg phy_reg_init[] = {
1081                 { 0x1f, 0x0003 },
1082                 { 0x08, 0x441d },
1083                 { 0x01, 0x9100 },
1084                 { 0x1f, 0x0000 }
1085         };
1086
1087         phy_set_bits(phydev, 0x11, BIT(12));
1088         phy_set_bits(phydev, 0x19, BIT(13));
1089         phy_set_bits(phydev, 0x10, BIT(15));
1090
1091         rtl_writephy_batch(phydev, phy_reg_init);
1092 }
1093
1094 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp,
1095                                    struct phy_device *phydev)
1096 {
1097         /* Disable ALDPS before ram code */
1098         phy_write(phydev, 0x18, 0x0310);
1099         msleep(100);
1100
1101         r8169_apply_firmware(tp);
1102
1103         phy_write_paged(phydev, 0x0005, 0x1a, 0x0000);
1104         phy_write_paged(phydev, 0x0004, 0x1c, 0x0000);
1105         phy_write_paged(phydev, 0x0001, 0x15, 0x7701);
1106 }
1107
1108 static void rtl8402_hw_phy_config(struct rtl8169_private *tp,
1109                                   struct phy_device *phydev)
1110 {
1111         /* Disable ALDPS before setting firmware */
1112         phy_write(phydev, 0x18, 0x0310);
1113         msleep(20);
1114
1115         r8169_apply_firmware(tp);
1116
1117         /* EEE setting */
1118         phy_write(phydev, 0x1f, 0x0004);
1119         phy_write(phydev, 0x10, 0x401f);
1120         phy_write(phydev, 0x19, 0x7030);
1121         phy_write(phydev, 0x1f, 0x0000);
1122 }
1123
1124 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp,
1125                                    struct phy_device *phydev)
1126 {
1127         static const struct phy_reg phy_reg_init[] = {
1128                 { 0x1f, 0x0004 },
1129                 { 0x10, 0xc07f },
1130                 { 0x19, 0x7030 },
1131                 { 0x1f, 0x0000 }
1132         };
1133
1134         /* Disable ALDPS before ram code */
1135         phy_write(phydev, 0x18, 0x0310);
1136         msleep(100);
1137
1138         r8169_apply_firmware(tp);
1139
1140         rtl_writephy_batch(phydev, phy_reg_init);
1141 }
1142
1143 static void rtl8125a_1_hw_phy_config(struct rtl8169_private *tp,
1144                                      struct phy_device *phydev)
1145 {
1146         phy_modify_paged(phydev, 0xad4, 0x10, 0x03ff, 0x0084);
1147         phy_modify_paged(phydev, 0xad4, 0x17, 0x0000, 0x0010);
1148         phy_modify_paged(phydev, 0xad1, 0x13, 0x03ff, 0x0006);
1149         phy_modify_paged(phydev, 0xad3, 0x11, 0x003f, 0x0006);
1150         phy_modify_paged(phydev, 0xac0, 0x14, 0x0000, 0x1100);
1151         phy_modify_paged(phydev, 0xac8, 0x15, 0xf000, 0x7000);
1152         phy_modify_paged(phydev, 0xad1, 0x14, 0x0000, 0x0400);
1153         phy_modify_paged(phydev, 0xad1, 0x15, 0x0000, 0x03ff);
1154         phy_modify_paged(phydev, 0xad1, 0x16, 0x0000, 0x03ff);
1155
1156         r8168g_phy_param(phydev, 0x80ea, 0xff00, 0xc400);
1157         r8168g_phy_param(phydev, 0x80eb, 0x0700, 0x0300);
1158         r8168g_phy_param(phydev, 0x80f8, 0xff00, 0x1c00);
1159         r8168g_phy_param(phydev, 0x80f1, 0xff00, 0x3000);
1160         r8168g_phy_param(phydev, 0x80fe, 0xff00, 0xa500);
1161         r8168g_phy_param(phydev, 0x8102, 0xff00, 0x5000);
1162         r8168g_phy_param(phydev, 0x8105, 0xff00, 0x3300);
1163         r8168g_phy_param(phydev, 0x8100, 0xff00, 0x7000);
1164         r8168g_phy_param(phydev, 0x8104, 0xff00, 0xf000);
1165         r8168g_phy_param(phydev, 0x8106, 0xff00, 0x6500);
1166         r8168g_phy_param(phydev, 0x80dc, 0xff00, 0xed00);
1167         r8168g_phy_param(phydev, 0x80df, 0x0000, 0x0100);
1168         r8168g_phy_param(phydev, 0x80e1, 0x0100, 0x0000);
1169
1170         phy_modify_paged(phydev, 0xbf0, 0x13, 0x003f, 0x0038);
1171         r8168g_phy_param(phydev, 0x819f, 0xffff, 0xd0b6);
1172
1173         phy_write_paged(phydev, 0xbc3, 0x12, 0x5555);
1174         phy_modify_paged(phydev, 0xbf0, 0x15, 0x0e00, 0x0a00);
1175         phy_modify_paged(phydev, 0xa5c, 0x10, 0x0400, 0x0000);
1176         rtl8168g_enable_gphy_10m(phydev);
1177
1178         rtl8125a_config_eee_phy(phydev);
1179 }
1180
1181 static void rtl8125a_2_hw_phy_config(struct rtl8169_private *tp,
1182                                      struct phy_device *phydev)
1183 {
1184         int i;
1185
1186         phy_modify_paged(phydev, 0xad4, 0x17, 0x0000, 0x0010);
1187         phy_modify_paged(phydev, 0xad1, 0x13, 0x03ff, 0x03ff);
1188         phy_modify_paged(phydev, 0xad3, 0x11, 0x003f, 0x0006);
1189         phy_modify_paged(phydev, 0xac0, 0x14, 0x1100, 0x0000);
1190         phy_modify_paged(phydev, 0xacc, 0x10, 0x0003, 0x0002);
1191         phy_modify_paged(phydev, 0xad4, 0x10, 0x00e7, 0x0044);
1192         phy_modify_paged(phydev, 0xac1, 0x12, 0x0080, 0x0000);
1193         phy_modify_paged(phydev, 0xac8, 0x10, 0x0300, 0x0000);
1194         phy_modify_paged(phydev, 0xac5, 0x17, 0x0007, 0x0002);
1195         phy_write_paged(phydev, 0xad4, 0x16, 0x00a8);
1196         phy_write_paged(phydev, 0xac5, 0x16, 0x01ff);
1197         phy_modify_paged(phydev, 0xac8, 0x15, 0x00f0, 0x0030);
1198
1199         phy_write(phydev, 0x1f, 0x0b87);
1200         phy_write(phydev, 0x16, 0x80a2);
1201         phy_write(phydev, 0x17, 0x0153);
1202         phy_write(phydev, 0x16, 0x809c);
1203         phy_write(phydev, 0x17, 0x0153);
1204         phy_write(phydev, 0x1f, 0x0000);
1205
1206         phy_write(phydev, 0x1f, 0x0a43);
1207         phy_write(phydev, 0x13, 0x81B3);
1208         phy_write(phydev, 0x14, 0x0043);
1209         phy_write(phydev, 0x14, 0x00A7);
1210         phy_write(phydev, 0x14, 0x00D6);
1211         phy_write(phydev, 0x14, 0x00EC);
1212         phy_write(phydev, 0x14, 0x00F6);
1213         phy_write(phydev, 0x14, 0x00FB);
1214         phy_write(phydev, 0x14, 0x00FD);
1215         phy_write(phydev, 0x14, 0x00FF);
1216         phy_write(phydev, 0x14, 0x00BB);
1217         phy_write(phydev, 0x14, 0x0058);
1218         phy_write(phydev, 0x14, 0x0029);
1219         phy_write(phydev, 0x14, 0x0013);
1220         phy_write(phydev, 0x14, 0x0009);
1221         phy_write(phydev, 0x14, 0x0004);
1222         phy_write(phydev, 0x14, 0x0002);
1223         for (i = 0; i < 25; i++)
1224                 phy_write(phydev, 0x14, 0x0000);
1225         phy_write(phydev, 0x1f, 0x0000);
1226
1227         r8168g_phy_param(phydev, 0x8257, 0xffff, 0x020F);
1228         r8168g_phy_param(phydev, 0x80ea, 0xffff, 0x7843);
1229
1230         r8169_apply_firmware(tp);
1231
1232         phy_modify_paged(phydev, 0xd06, 0x14, 0x0000, 0x2000);
1233
1234         r8168g_phy_param(phydev, 0x81a2, 0x0000, 0x0100);
1235
1236         phy_modify_paged(phydev, 0xb54, 0x16, 0xff00, 0xdb00);
1237         phy_modify_paged(phydev, 0xa45, 0x12, 0x0001, 0x0000);
1238         phy_modify_paged(phydev, 0xa5d, 0x12, 0x0000, 0x0020);
1239         phy_modify_paged(phydev, 0xad4, 0x17, 0x0010, 0x0000);
1240         phy_modify_paged(phydev, 0xa86, 0x15, 0x0001, 0x0000);
1241         rtl8168g_enable_gphy_10m(phydev);
1242
1243         rtl8125a_config_eee_phy(phydev);
1244 }
1245
1246 void r8169_hw_phy_config(struct rtl8169_private *tp, struct phy_device *phydev,
1247                          enum mac_version ver)
1248 {
1249         static const rtl_phy_cfg_fct phy_configs[] = {
1250                 /* PCI devices. */
1251                 [RTL_GIGA_MAC_VER_02] = rtl8169s_hw_phy_config,
1252                 [RTL_GIGA_MAC_VER_03] = rtl8169s_hw_phy_config,
1253                 [RTL_GIGA_MAC_VER_04] = rtl8169sb_hw_phy_config,
1254                 [RTL_GIGA_MAC_VER_05] = rtl8169scd_hw_phy_config,
1255                 [RTL_GIGA_MAC_VER_06] = rtl8169sce_hw_phy_config,
1256                 /* PCI-E devices. */
1257                 [RTL_GIGA_MAC_VER_07] = rtl8102e_hw_phy_config,
1258                 [RTL_GIGA_MAC_VER_08] = rtl8102e_hw_phy_config,
1259                 [RTL_GIGA_MAC_VER_09] = rtl8102e_hw_phy_config,
1260                 [RTL_GIGA_MAC_VER_10] = NULL,
1261                 [RTL_GIGA_MAC_VER_11] = rtl8168bb_hw_phy_config,
1262                 [RTL_GIGA_MAC_VER_12] = rtl8168bef_hw_phy_config,
1263                 [RTL_GIGA_MAC_VER_13] = NULL,
1264                 [RTL_GIGA_MAC_VER_14] = NULL,
1265                 [RTL_GIGA_MAC_VER_15] = NULL,
1266                 [RTL_GIGA_MAC_VER_16] = NULL,
1267                 [RTL_GIGA_MAC_VER_17] = rtl8168bef_hw_phy_config,
1268                 [RTL_GIGA_MAC_VER_18] = rtl8168cp_1_hw_phy_config,
1269                 [RTL_GIGA_MAC_VER_19] = rtl8168c_1_hw_phy_config,
1270                 [RTL_GIGA_MAC_VER_20] = rtl8168c_2_hw_phy_config,
1271                 [RTL_GIGA_MAC_VER_21] = rtl8168c_3_hw_phy_config,
1272                 [RTL_GIGA_MAC_VER_22] = rtl8168c_3_hw_phy_config,
1273                 [RTL_GIGA_MAC_VER_23] = rtl8168cp_2_hw_phy_config,
1274                 [RTL_GIGA_MAC_VER_24] = rtl8168cp_2_hw_phy_config,
1275                 [RTL_GIGA_MAC_VER_25] = rtl8168d_1_hw_phy_config,
1276                 [RTL_GIGA_MAC_VER_26] = rtl8168d_2_hw_phy_config,
1277                 [RTL_GIGA_MAC_VER_27] = rtl8168d_3_hw_phy_config,
1278                 [RTL_GIGA_MAC_VER_28] = rtl8168d_4_hw_phy_config,
1279                 [RTL_GIGA_MAC_VER_29] = rtl8105e_hw_phy_config,
1280                 [RTL_GIGA_MAC_VER_30] = rtl8105e_hw_phy_config,
1281                 [RTL_GIGA_MAC_VER_31] = NULL,
1282                 [RTL_GIGA_MAC_VER_32] = rtl8168e_1_hw_phy_config,
1283                 [RTL_GIGA_MAC_VER_33] = rtl8168e_1_hw_phy_config,
1284                 [RTL_GIGA_MAC_VER_34] = rtl8168e_2_hw_phy_config,
1285                 [RTL_GIGA_MAC_VER_35] = rtl8168f_1_hw_phy_config,
1286                 [RTL_GIGA_MAC_VER_36] = rtl8168f_2_hw_phy_config,
1287                 [RTL_GIGA_MAC_VER_37] = rtl8402_hw_phy_config,
1288                 [RTL_GIGA_MAC_VER_38] = rtl8411_hw_phy_config,
1289                 [RTL_GIGA_MAC_VER_39] = rtl8106e_hw_phy_config,
1290                 [RTL_GIGA_MAC_VER_40] = rtl8168g_1_hw_phy_config,
1291                 [RTL_GIGA_MAC_VER_41] = NULL,
1292                 [RTL_GIGA_MAC_VER_42] = rtl8168g_2_hw_phy_config,
1293                 [RTL_GIGA_MAC_VER_43] = rtl8168g_2_hw_phy_config,
1294                 [RTL_GIGA_MAC_VER_44] = rtl8168g_2_hw_phy_config,
1295                 [RTL_GIGA_MAC_VER_45] = rtl8168h_1_hw_phy_config,
1296                 [RTL_GIGA_MAC_VER_46] = rtl8168h_2_hw_phy_config,
1297                 [RTL_GIGA_MAC_VER_47] = rtl8168h_1_hw_phy_config,
1298                 [RTL_GIGA_MAC_VER_48] = rtl8168h_2_hw_phy_config,
1299                 [RTL_GIGA_MAC_VER_49] = rtl8168ep_1_hw_phy_config,
1300                 [RTL_GIGA_MAC_VER_50] = rtl8168ep_2_hw_phy_config,
1301                 [RTL_GIGA_MAC_VER_51] = rtl8168ep_2_hw_phy_config,
1302                 [RTL_GIGA_MAC_VER_52] = rtl8117_hw_phy_config,
1303                 [RTL_GIGA_MAC_VER_60] = rtl8125a_1_hw_phy_config,
1304                 [RTL_GIGA_MAC_VER_61] = rtl8125a_2_hw_phy_config,
1305         };
1306
1307         if (phy_configs[ver])
1308                 phy_configs[ver](tp, phydev);
1309 }