1 // SPDX-License-Identifier: GPL-2.0-only
3 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
7 * Copyright (c) a lot of people too. Please respect their work.
9 * See MAINTAINERS file for support contact information.
12 #include <linux/module.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/clk.h>
17 #include <linux/delay.h>
18 #include <linux/ethtool.h>
19 #include <linux/phy.h>
20 #include <linux/if_vlan.h>
24 #include <linux/tcp.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/bitfield.h>
29 #include <linux/prefetch.h>
30 #include <linux/ipv6.h>
31 #include <asm/unaligned.h>
32 #include <net/ip6_checksum.h>
33 #include <net/netdev_queues.h>
36 #include "r8169_firmware.h"
38 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
39 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
40 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
41 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
42 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
43 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
44 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
45 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
46 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
47 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
48 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
49 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
50 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
51 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
52 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
53 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw"
54 #define FIRMWARE_8168FP_3 "rtl_nic/rtl8168fp-3.fw"
55 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw"
56 #define FIRMWARE_8125A_3 "rtl_nic/rtl8125a-3.fw"
57 #define FIRMWARE_8125B_2 "rtl_nic/rtl8125b-2.fw"
59 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
60 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
62 #define R8169_REGS_SIZE 256
63 #define R8169_RX_BUF_SIZE (SZ_16K - 1)
64 #define NUM_TX_DESC 256 /* Number of Tx descriptor registers */
65 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
66 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
67 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
68 #define R8169_TX_STOP_THRS (MAX_SKB_FRAGS + 1)
69 #define R8169_TX_START_THRS (2 * R8169_TX_STOP_THRS)
71 #define OCP_STD_PHY_BASE 0xa400
73 #define RTL_CFG_NO_GBIT 1
75 /* write/read MMIO register */
76 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg))
77 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
78 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
79 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg))
80 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg))
81 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg))
83 #define JUMBO_4K (4 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
84 #define JUMBO_6K (6 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
85 #define JUMBO_7K (7 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
86 #define JUMBO_9K (9 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
91 } rtl_chip_infos[] = {
93 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" },
94 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" },
95 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" },
96 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" },
97 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" },
99 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" },
100 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" },
101 [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e" },
102 [RTL_GIGA_MAC_VER_10] = {"RTL8101e/RTL8100e" },
103 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" },
104 [RTL_GIGA_MAC_VER_14] = {"RTL8401" },
105 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" },
106 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" },
107 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" },
108 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" },
109 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" },
110 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" },
111 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" },
112 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" },
113 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1},
114 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2},
115 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" },
116 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1},
117 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1},
118 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" },
119 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1},
120 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2},
121 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3},
122 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1},
123 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2},
124 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 },
125 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 },
126 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1},
127 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2},
128 [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu", FIRMWARE_8168G_3},
129 [RTL_GIGA_MAC_VER_43] = {"RTL8106eus", FIRMWARE_8106E_2},
130 [RTL_GIGA_MAC_VER_44] = {"RTL8411b", FIRMWARE_8411_2 },
131 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2},
132 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2},
133 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" },
134 [RTL_GIGA_MAC_VER_52] = {"RTL8168fp/RTL8117", FIRMWARE_8168FP_3},
135 [RTL_GIGA_MAC_VER_53] = {"RTL8168fp/RTL8117", },
136 [RTL_GIGA_MAC_VER_61] = {"RTL8125A", FIRMWARE_8125A_3},
137 /* reserve 62 for CFG_METHOD_4 in the vendor driver */
138 [RTL_GIGA_MAC_VER_63] = {"RTL8125B", FIRMWARE_8125B_2},
141 static const struct pci_device_id rtl8169_pci_tbl[] = {
142 { PCI_VDEVICE(REALTEK, 0x2502) },
143 { PCI_VDEVICE(REALTEK, 0x2600) },
144 { PCI_VDEVICE(REALTEK, 0x8129) },
145 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT },
146 { PCI_VDEVICE(REALTEK, 0x8161) },
147 { PCI_VDEVICE(REALTEK, 0x8162) },
148 { PCI_VDEVICE(REALTEK, 0x8167) },
149 { PCI_VDEVICE(REALTEK, 0x8168) },
150 { PCI_VDEVICE(NCUBE, 0x8168) },
151 { PCI_VDEVICE(REALTEK, 0x8169) },
152 { PCI_VENDOR_ID_DLINK, 0x4300,
153 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 },
154 { PCI_VDEVICE(DLINK, 0x4300) },
155 { PCI_VDEVICE(DLINK, 0x4302) },
156 { PCI_VDEVICE(AT, 0xc107) },
157 { PCI_VDEVICE(USR, 0x0116) },
158 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 },
159 { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 },
160 { PCI_VDEVICE(REALTEK, 0x8125) },
161 { PCI_VDEVICE(REALTEK, 0x3000) },
165 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
168 MAC0 = 0, /* Ethernet hardware address. */
170 MAR0 = 8, /* Multicast filter. */
171 CounterAddrLow = 0x10,
172 CounterAddrHigh = 0x14,
173 TxDescStartAddrLow = 0x20,
174 TxDescStartAddrHigh = 0x24,
175 TxHDescStartAddrLow = 0x28,
176 TxHDescStartAddrHigh = 0x2c,
185 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
186 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
189 #define RX128_INT_EN (1 << 15) /* 8111c and later */
190 #define RX_MULTI_EN (1 << 14) /* 8111c only */
191 #define RXCFG_FIFO_SHIFT 13
192 /* No threshold before first PCI xfer */
193 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
194 #define RX_EARLY_OFF (1 << 11)
195 #define RX_PAUSE_SLOT_ON (1 << 11) /* 8125b and later */
196 #define RXCFG_DMA_SHIFT 8
197 /* Unlimited maximum PCI burst. */
198 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
204 #define PME_SIGNAL (1 << 5) /* 8168c and later */
215 #define RTL_COALESCE_TX_USECS GENMASK(15, 12)
216 #define RTL_COALESCE_TX_FRAMES GENMASK(11, 8)
217 #define RTL_COALESCE_RX_USECS GENMASK(7, 4)
218 #define RTL_COALESCE_RX_FRAMES GENMASK(3, 0)
220 #define RTL_COALESCE_T_MAX 0x0fU
221 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_T_MAX * 4)
223 RxDescAddrLow = 0xe4,
224 RxDescAddrHigh = 0xe8,
225 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
227 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
229 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
231 #define TxPacketMax (8064 >> 7)
232 #define EarlySize 0x27
235 FuncEventMask = 0xf4,
236 FuncPresetState = 0xf8,
241 FuncForceEvent = 0xfc,
244 enum rtl8168_8101_registers {
247 #define CSIAR_FLAG 0x80000000
248 #define CSIAR_WRITE_CMD 0x80000000
249 #define CSIAR_BYTE_ENABLE 0x0000f000
250 #define CSIAR_ADDR_MASK 0x00000fff
252 #define D3COLD_NO_PLL_DOWN BIT(7)
253 #define D3HOT_NO_PLL_DOWN BIT(6)
254 #define D3_NO_PLL_DOWN (BIT(7) | BIT(6))
256 #define EPHYAR_FLAG 0x80000000
257 #define EPHYAR_WRITE_CMD 0x80000000
258 #define EPHYAR_REG_MASK 0x1f
259 #define EPHYAR_REG_SHIFT 16
260 #define EPHYAR_DATA_MASK 0xffff
262 #define PFM_EN (1 << 6)
263 #define TX_10M_PS_EN (1 << 7)
265 #define FIX_NAK_1 (1 << 4)
266 #define FIX_NAK_2 (1 << 3)
269 #define NOW_IS_OOB (1 << 7)
270 #define TX_EMPTY (1 << 5)
271 #define RX_EMPTY (1 << 4)
272 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
273 #define EN_NDP (1 << 3)
274 #define EN_OOB_RESET (1 << 2)
275 #define LINK_LIST_RDY (1 << 1)
277 #define EFUSEAR_FLAG 0x80000000
278 #define EFUSEAR_WRITE_CMD 0x80000000
279 #define EFUSEAR_READ_CMD 0x00000000
280 #define EFUSEAR_REG_MASK 0x03ff
281 #define EFUSEAR_REG_SHIFT 8
282 #define EFUSEAR_DATA_MASK 0xff
284 #define PFM_D3COLD_EN (1 << 6)
287 enum rtl8168_registers {
293 #define ERIAR_FLAG 0x80000000
294 #define ERIAR_WRITE_CMD 0x80000000
295 #define ERIAR_READ_CMD 0x00000000
296 #define ERIAR_ADDR_BYTE_ALIGN 4
297 #define ERIAR_TYPE_SHIFT 16
298 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
299 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
300 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
301 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT)
302 #define ERIAR_MASK_SHIFT 12
303 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
304 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
305 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
306 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
307 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
308 EPHY_RXER_NUM = 0x7c,
309 OCPDR = 0xb0, /* OCP GPHY access */
310 #define OCPDR_WRITE_CMD 0x80000000
311 #define OCPDR_READ_CMD 0x00000000
312 #define OCPDR_REG_MASK 0x7f
313 #define OCPDR_GPHY_REG_SHIFT 16
314 #define OCPDR_DATA_MASK 0xffff
316 #define OCPAR_FLAG 0x80000000
317 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
318 #define OCPAR_GPHY_READ_CMD 0x0000f060
320 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
321 MISC = 0xf0, /* 8168e only. */
322 #define TXPLA_RST (1 << 29)
323 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
324 #define PWM_EN (1 << 22)
325 #define RXDV_GATED_EN (1 << 19)
326 #define EARLY_TALLY_EN (1 << 16)
329 enum rtl8125_registers {
330 IntrMask_8125 = 0x38,
331 IntrStatus_8125 = 0x3c,
334 EEE_TXIDLE_TIMER_8125 = 0x6048,
337 #define RX_VLAN_INNER_8125 BIT(22)
338 #define RX_VLAN_OUTER_8125 BIT(23)
339 #define RX_VLAN_8125 (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125)
341 #define RX_FETCH_DFLT_8125 (8 << 27)
343 enum rtl_register_content {
344 /* InterruptStatusBits */
348 TxDescUnavail = 0x0080,
370 /* TXPoll register p.5 */
371 HPQ = 0x80, /* Poll cmd on the high prio queue */
372 NPQ = 0x40, /* Poll cmd on the low prio queue */
373 FSWInt = 0x01, /* Forced software interrupt */
377 Cfg9346_Unlock = 0xc0,
382 #define RX_CONFIG_ACCEPT_ERR_MASK 0x30
383 AcceptBroadcast = 0x08,
384 AcceptMulticast = 0x04,
386 AcceptAllPhys = 0x01,
387 #define RX_CONFIG_ACCEPT_OK_MASK 0x0f
388 #define RX_CONFIG_ACCEPT_MASK 0x3f
391 TxInterFrameGapShift = 24,
392 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
394 /* Config1 register p.24 */
397 Speed_down = (1 << 4),
401 PMEnable = (1 << 0), /* Power Management Enable */
403 /* Config2 register p. 25 */
404 ClkReqEn = (1 << 7), /* Clock Request Enable */
405 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
406 PCI_Clock_66MHz = 0x01,
407 PCI_Clock_33MHz = 0x00,
409 /* Config3 register p.25 */
410 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
411 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
412 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
413 Rdy_to_L23 = (1 << 1), /* L23 Enable */
414 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
416 /* Config4 register */
417 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
419 /* Config5 register p.27 */
420 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
421 MWF = (1 << 5), /* Accept Multicast wakeup frame */
422 UWF = (1 << 4), /* Accept Unicast wakeup frame */
424 LanWake = (1 << 1), /* LanWake enable/disable */
425 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
426 ASPM_en = (1 << 0), /* ASPM enable */
429 EnableBist = (1 << 15), // 8168 8101
430 Mac_dbgo_oe = (1 << 14), // 8168 8101
431 EnAnaPLL = (1 << 14), // 8169
432 Normal_mode = (1 << 13), // unused
433 Force_half_dup = (1 << 12), // 8168 8101
434 Force_rxflow_en = (1 << 11), // 8168 8101
435 Force_txflow_en = (1 << 10), // 8168 8101
436 Cxpl_dbg_sel = (1 << 9), // 8168 8101
437 ASF = (1 << 8), // 8168 8101
438 PktCntrDisable = (1 << 7), // 8168 8101
439 Mac_dbgo_sel = 0x001c, // 8168
444 #define INTT_MASK GENMASK(1, 0)
445 #define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
447 /* rtl8169_PHYstatus */
457 /* ResetCounterCommand */
460 /* DumpCounterCommand */
463 /* magic enable v2 */
464 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */
468 /* First doubleword. */
469 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
470 RingEnd = (1 << 30), /* End of descriptor ring */
471 FirstFrag = (1 << 29), /* First segment of a packet */
472 LastFrag = (1 << 28), /* Final segment of a packet */
476 enum rtl_tx_desc_bit {
477 /* First doubleword. */
478 TD_LSO = (1 << 27), /* Large Send Offload */
479 #define TD_MSS_MAX 0x07ffu /* MSS value */
481 /* Second doubleword. */
482 TxVlanTag = (1 << 17), /* Add VLAN tag */
485 /* 8169, 8168b and 810x except 8102e. */
486 enum rtl_tx_desc_bit_0 {
487 /* First doubleword. */
488 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
489 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
490 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
491 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
494 /* 8102e, 8168c and beyond. */
495 enum rtl_tx_desc_bit_1 {
496 /* First doubleword. */
497 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */
498 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */
499 #define GTTCPHO_SHIFT 18
500 #define GTTCPHO_MAX 0x7f
502 /* Second doubleword. */
503 #define TCPHO_SHIFT 18
504 #define TCPHO_MAX 0x3ff
505 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
506 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */
507 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */
508 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
509 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
512 enum rtl_rx_desc_bit {
514 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
515 PID0 = (1 << 17), /* Protocol ID bit 0/2 */
517 #define RxProtoUDP (PID1)
518 #define RxProtoTCP (PID0)
519 #define RxProtoIP (PID1 | PID0)
520 #define RxProtoMask RxProtoIP
522 IPFail = (1 << 16), /* IP checksum failed */
523 UDPFail = (1 << 15), /* UDP/IP checksum failed */
524 TCPFail = (1 << 14), /* TCP/IP checksum failed */
526 #define RxCSFailMask (IPFail | UDPFail | TCPFail)
528 RxVlanTag = (1 << 16), /* VLAN tag available */
531 #define RTL_GSO_MAX_SIZE_V1 32000
532 #define RTL_GSO_MAX_SEGS_V1 24
533 #define RTL_GSO_MAX_SIZE_V2 64000
534 #define RTL_GSO_MAX_SEGS_V2 64
553 struct rtl8169_counters {
560 __le32 tx_one_collision;
561 __le32 tx_multi_collision;
569 struct rtl8169_tc_offsets {
572 __le32 tx_multi_collision;
578 RTL_FLAG_TASK_ENABLED = 0,
579 RTL_FLAG_TASK_RESET_PENDING,
580 RTL_FLAG_TASK_RESET_NO_QUEUE_WAKE,
581 RTL_FLAG_TASK_TX_TIMEOUT,
591 struct rtl8169_private {
592 void __iomem *mmio_addr; /* memory map physical address */
593 struct pci_dev *pci_dev;
594 struct net_device *dev;
595 struct phy_device *phydev;
596 struct napi_struct napi;
597 enum mac_version mac_version;
598 enum rtl_dash_type dash_type;
599 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
600 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
602 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
603 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
604 dma_addr_t TxPhyAddr;
605 dma_addr_t RxPhyAddr;
606 struct page *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
607 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
614 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
615 struct work_struct work;
618 raw_spinlock_t config25_lock;
619 raw_spinlock_t mac_ocp_lock;
620 struct mutex led_lock; /* serialize LED ctrl RMW access */
622 raw_spinlock_t cfg9346_usage_lock;
623 int cfg9346_usage_count;
625 unsigned supports_gmii:1;
626 unsigned aspm_manageable:1;
627 unsigned dash_enabled:1;
628 dma_addr_t counters_phys_addr;
629 struct rtl8169_counters *counters;
630 struct rtl8169_tc_offsets tc_offset;
635 struct rtl_fw *rtl_fw;
640 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp);
642 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
643 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
644 MODULE_SOFTDEP("pre: realtek");
645 MODULE_LICENSE("GPL");
646 MODULE_FIRMWARE(FIRMWARE_8168D_1);
647 MODULE_FIRMWARE(FIRMWARE_8168D_2);
648 MODULE_FIRMWARE(FIRMWARE_8168E_1);
649 MODULE_FIRMWARE(FIRMWARE_8168E_2);
650 MODULE_FIRMWARE(FIRMWARE_8168E_3);
651 MODULE_FIRMWARE(FIRMWARE_8105E_1);
652 MODULE_FIRMWARE(FIRMWARE_8168F_1);
653 MODULE_FIRMWARE(FIRMWARE_8168F_2);
654 MODULE_FIRMWARE(FIRMWARE_8402_1);
655 MODULE_FIRMWARE(FIRMWARE_8411_1);
656 MODULE_FIRMWARE(FIRMWARE_8411_2);
657 MODULE_FIRMWARE(FIRMWARE_8106E_1);
658 MODULE_FIRMWARE(FIRMWARE_8106E_2);
659 MODULE_FIRMWARE(FIRMWARE_8168G_2);
660 MODULE_FIRMWARE(FIRMWARE_8168G_3);
661 MODULE_FIRMWARE(FIRMWARE_8168H_2);
662 MODULE_FIRMWARE(FIRMWARE_8168FP_3);
663 MODULE_FIRMWARE(FIRMWARE_8107E_2);
664 MODULE_FIRMWARE(FIRMWARE_8125A_3);
665 MODULE_FIRMWARE(FIRMWARE_8125B_2);
667 static inline struct device *tp_to_dev(struct rtl8169_private *tp)
669 return &tp->pci_dev->dev;
672 static void rtl_lock_config_regs(struct rtl8169_private *tp)
676 raw_spin_lock_irqsave(&tp->cfg9346_usage_lock, flags);
677 if (!--tp->cfg9346_usage_count)
678 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
679 raw_spin_unlock_irqrestore(&tp->cfg9346_usage_lock, flags);
682 static void rtl_unlock_config_regs(struct rtl8169_private *tp)
686 raw_spin_lock_irqsave(&tp->cfg9346_usage_lock, flags);
687 if (!tp->cfg9346_usage_count++)
688 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
689 raw_spin_unlock_irqrestore(&tp->cfg9346_usage_lock, flags);
692 static void rtl_pci_commit(struct rtl8169_private *tp)
694 /* Read an arbitrary register to commit a preceding PCI write */
698 static void rtl_mod_config2(struct rtl8169_private *tp, u8 clear, u8 set)
703 raw_spin_lock_irqsave(&tp->config25_lock, flags);
704 val = RTL_R8(tp, Config2);
705 RTL_W8(tp, Config2, (val & ~clear) | set);
706 raw_spin_unlock_irqrestore(&tp->config25_lock, flags);
709 static void rtl_mod_config5(struct rtl8169_private *tp, u8 clear, u8 set)
714 raw_spin_lock_irqsave(&tp->config25_lock, flags);
715 val = RTL_R8(tp, Config5);
716 RTL_W8(tp, Config5, (val & ~clear) | set);
717 raw_spin_unlock_irqrestore(&tp->config25_lock, flags);
720 static bool rtl_is_8125(struct rtl8169_private *tp)
722 return tp->mac_version >= RTL_GIGA_MAC_VER_61;
725 static bool rtl_is_8168evl_up(struct rtl8169_private *tp)
727 return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
728 tp->mac_version != RTL_GIGA_MAC_VER_39 &&
729 tp->mac_version <= RTL_GIGA_MAC_VER_53;
732 static bool rtl_supports_eee(struct rtl8169_private *tp)
734 return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
735 tp->mac_version != RTL_GIGA_MAC_VER_37 &&
736 tp->mac_version != RTL_GIGA_MAC_VER_39;
739 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg)
743 for (i = 0; i < ETH_ALEN; i++)
744 mac[i] = RTL_R8(tp, reg + i);
748 bool (*check)(struct rtl8169_private *);
752 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
753 unsigned long usecs, int n, bool high)
757 for (i = 0; i < n; i++) {
758 if (c->check(tp) == high)
764 netdev_err(tp->dev, "%s == %d (loop: %d, delay: %lu).\n",
765 c->msg, !high, n, usecs);
769 static bool rtl_loop_wait_high(struct rtl8169_private *tp,
770 const struct rtl_cond *c,
771 unsigned long d, int n)
773 return rtl_loop_wait(tp, c, d, n, true);
776 static bool rtl_loop_wait_low(struct rtl8169_private *tp,
777 const struct rtl_cond *c,
778 unsigned long d, int n)
780 return rtl_loop_wait(tp, c, d, n, false);
783 #define DECLARE_RTL_COND(name) \
784 static bool name ## _check(struct rtl8169_private *); \
786 static const struct rtl_cond name = { \
787 .check = name ## _check, \
791 static bool name ## _check(struct rtl8169_private *tp)
793 int rtl8168_led_mod_ctrl(struct rtl8169_private *tp, u16 mask, u16 val)
795 struct device *dev = tp_to_dev(tp);
798 ret = pm_runtime_resume_and_get(dev);
802 mutex_lock(&tp->led_lock);
803 RTL_W16(tp, LED_CTRL, (RTL_R16(tp, LED_CTRL) & ~mask) | val);
804 mutex_unlock(&tp->led_lock);
806 pm_runtime_put_sync(dev);
811 int rtl8168_get_led_mode(struct rtl8169_private *tp)
813 struct device *dev = tp_to_dev(tp);
816 ret = pm_runtime_resume_and_get(dev);
820 ret = RTL_R16(tp, LED_CTRL);
822 pm_runtime_put_sync(dev);
827 void r8169_get_led_name(struct rtl8169_private *tp, int idx,
828 char *buf, int buf_len)
830 struct pci_dev *pdev = tp->pci_dev;
831 char pdom[8], pfun[8];
834 domain = pci_domain_nr(pdev->bus);
836 snprintf(pdom, sizeof(pdom), "P%d", domain);
840 if (pdev->multifunction)
841 snprintf(pfun, sizeof(pfun), "f%d", PCI_FUNC(pdev->devfn));
845 snprintf(buf, buf_len, "en%sp%ds%d%s-%d::lan", pdom, pdev->bus->number,
846 PCI_SLOT(pdev->devfn), pfun, idx);
849 static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type)
851 /* based on RTL8168FP_OOBMAC_BASE in vendor driver */
852 if (type == ERIAR_OOB &&
853 (tp->mac_version == RTL_GIGA_MAC_VER_52 ||
854 tp->mac_version == RTL_GIGA_MAC_VER_53))
858 DECLARE_RTL_COND(rtl_eriar_cond)
860 return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
863 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
866 u32 cmd = ERIAR_WRITE_CMD | type | mask | addr;
868 if (WARN(addr & 3 || !mask, "addr: 0x%x, mask: 0x%08x\n", addr, mask))
871 RTL_W32(tp, ERIDR, val);
872 r8168fp_adjust_ocp_cmd(tp, &cmd, type);
873 RTL_W32(tp, ERIAR, cmd);
875 rtl_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
878 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
881 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC);
884 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
886 u32 cmd = ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr;
888 r8168fp_adjust_ocp_cmd(tp, &cmd, type);
889 RTL_W32(tp, ERIAR, cmd);
891 return rtl_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
892 RTL_R32(tp, ERIDR) : ~0;
895 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr)
897 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC);
900 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 p, u32 m)
902 u32 val = rtl_eri_read(tp, addr);
904 rtl_eri_write(tp, addr, ERIAR_MASK_1111, (val & ~m) | p);
907 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 p)
909 rtl_w0w1_eri(tp, addr, p, 0);
912 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 m)
914 rtl_w0w1_eri(tp, addr, 0, m);
917 static bool rtl_ocp_reg_failure(u32 reg)
919 return WARN_ONCE(reg & 0xffff0001, "Invalid ocp reg %x!\n", reg);
922 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
924 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
927 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
929 if (rtl_ocp_reg_failure(reg))
932 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
934 rtl_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
937 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
939 if (rtl_ocp_reg_failure(reg))
942 RTL_W32(tp, GPHY_OCP, reg << 15);
944 return rtl_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
945 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT;
948 static void __r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
950 if (rtl_ocp_reg_failure(reg))
953 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
956 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
960 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags);
961 __r8168_mac_ocp_write(tp, reg, data);
962 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags);
965 static u16 __r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
967 if (rtl_ocp_reg_failure(reg))
970 RTL_W32(tp, OCPDR, reg << 15);
972 return RTL_R32(tp, OCPDR);
975 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
980 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags);
981 val = __r8168_mac_ocp_read(tp, reg);
982 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags);
987 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask,
993 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags);
994 data = __r8168_mac_ocp_read(tp, reg);
995 __r8168_mac_ocp_write(tp, reg, (data & ~mask) | set);
996 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags);
999 /* Work around a hw issue with RTL8168g PHY, the quirk disables
1000 * PHY MCU interrupts before PHY power-down.
1002 static void rtl8168g_phy_suspend_quirk(struct rtl8169_private *tp, int value)
1004 switch (tp->mac_version) {
1005 case RTL_GIGA_MAC_VER_40:
1006 if (value & BMCR_RESET || !(value & BMCR_PDOWN))
1007 rtl_eri_set_bits(tp, 0x1a8, 0xfc000000);
1009 rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000);
1016 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
1019 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
1023 if (tp->ocp_base != OCP_STD_PHY_BASE)
1026 if (tp->ocp_base == OCP_STD_PHY_BASE && reg == MII_BMCR)
1027 rtl8168g_phy_suspend_quirk(tp, value);
1029 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
1032 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
1035 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4;
1037 if (tp->ocp_base != OCP_STD_PHY_BASE)
1040 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
1043 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
1046 tp->ocp_base = value << 4;
1050 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
1053 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
1055 return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
1058 DECLARE_RTL_COND(rtl_phyar_cond)
1060 return RTL_R32(tp, PHYAR) & 0x80000000;
1063 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1065 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1067 rtl_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
1069 * According to hardware specs a 20us delay is required after write
1070 * complete indication, but before sending next command.
1075 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1079 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
1081 value = rtl_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1082 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT;
1085 * According to hardware specs a 20us delay is required after read
1086 * complete indication, but before sending next command.
1093 DECLARE_RTL_COND(rtl_ocpar_cond)
1095 return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
1098 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
1100 static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
1102 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1105 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
1107 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1110 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
1112 r8168dp_2_mdio_start(tp);
1114 r8169_mdio_write(tp, reg, value);
1116 r8168dp_2_mdio_stop(tp);
1119 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1123 /* Work around issue with chip reporting wrong PHY ID */
1124 if (reg == MII_PHYSID2)
1127 r8168dp_2_mdio_start(tp);
1129 value = r8169_mdio_read(tp, reg);
1131 r8168dp_2_mdio_stop(tp);
1136 static void rtl_writephy(struct rtl8169_private *tp, int location, int val)
1138 switch (tp->mac_version) {
1139 case RTL_GIGA_MAC_VER_28:
1140 case RTL_GIGA_MAC_VER_31:
1141 r8168dp_2_mdio_write(tp, location, val);
1143 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
1144 r8168g_mdio_write(tp, location, val);
1147 r8169_mdio_write(tp, location, val);
1152 static int rtl_readphy(struct rtl8169_private *tp, int location)
1154 switch (tp->mac_version) {
1155 case RTL_GIGA_MAC_VER_28:
1156 case RTL_GIGA_MAC_VER_31:
1157 return r8168dp_2_mdio_read(tp, location);
1158 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
1159 return r8168g_mdio_read(tp, location);
1161 return r8169_mdio_read(tp, location);
1165 DECLARE_RTL_COND(rtl_ephyar_cond)
1167 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1170 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1172 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1173 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1175 rtl_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1180 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1182 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1184 return rtl_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1185 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1188 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u16 reg)
1190 RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff));
1191 return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1192 RTL_R32(tp, OCPDR) : ~0;
1195 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u16 reg)
1197 return _rtl_eri_read(tp, reg, ERIAR_OOB);
1200 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1203 RTL_W32(tp, OCPDR, data);
1204 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1205 rtl_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1208 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1211 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1215 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd)
1217 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd);
1219 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001);
1222 #define OOB_CMD_RESET 0x00
1223 #define OOB_CMD_DRIVER_START 0x05
1224 #define OOB_CMD_DRIVER_STOP 0x06
1226 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1228 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1231 DECLARE_RTL_COND(rtl_dp_ocp_read_cond)
1235 reg = rtl8168_get_ocp_reg(tp);
1237 return r8168dp_ocp_read(tp, reg) & 0x00000800;
1240 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1242 return r8168ep_ocp_read(tp, 0x124) & 0x00000001;
1245 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1247 return RTL_R8(tp, IBISR0) & 0x20;
1250 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1252 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1253 rtl_loop_wait_high(tp, &rtl_ocp_tx_cond, 50000, 2000);
1254 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1255 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1258 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1260 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START);
1261 rtl_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10000, 10);
1264 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1266 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1267 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01);
1268 rtl_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10000, 30);
1271 static void rtl8168_driver_start(struct rtl8169_private *tp)
1273 if (tp->dash_type == RTL_DASH_DP)
1274 rtl8168dp_driver_start(tp);
1276 rtl8168ep_driver_start(tp);
1279 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1281 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1282 rtl_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10000, 10);
1285 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1287 rtl8168ep_stop_cmac(tp);
1288 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1289 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01);
1290 rtl_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10000, 10);
1293 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1295 if (tp->dash_type == RTL_DASH_DP)
1296 rtl8168dp_driver_stop(tp);
1298 rtl8168ep_driver_stop(tp);
1301 static bool r8168dp_check_dash(struct rtl8169_private *tp)
1303 u16 reg = rtl8168_get_ocp_reg(tp);
1305 return r8168dp_ocp_read(tp, reg) & BIT(15);
1308 static bool r8168ep_check_dash(struct rtl8169_private *tp)
1310 return r8168ep_ocp_read(tp, 0x128) & BIT(0);
1313 static bool rtl_dash_is_enabled(struct rtl8169_private *tp)
1315 switch (tp->dash_type) {
1317 return r8168dp_check_dash(tp);
1319 return r8168ep_check_dash(tp);
1325 static enum rtl_dash_type rtl_get_dash_type(struct rtl8169_private *tp)
1327 switch (tp->mac_version) {
1328 case RTL_GIGA_MAC_VER_28:
1329 case RTL_GIGA_MAC_VER_31:
1331 case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_53:
1334 return RTL_DASH_NONE;
1338 static void rtl_set_d3_pll_down(struct rtl8169_private *tp, bool enable)
1340 switch (tp->mac_version) {
1341 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_26:
1342 case RTL_GIGA_MAC_VER_29 ... RTL_GIGA_MAC_VER_30:
1343 case RTL_GIGA_MAC_VER_32 ... RTL_GIGA_MAC_VER_37:
1344 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63:
1346 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~D3_NO_PLL_DOWN);
1348 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | D3_NO_PLL_DOWN);
1355 static void rtl_reset_packet_filter(struct rtl8169_private *tp)
1357 rtl_eri_clear_bits(tp, 0xdc, BIT(0));
1358 rtl_eri_set_bits(tp, 0xdc, BIT(0));
1361 DECLARE_RTL_COND(rtl_efusear_cond)
1363 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1366 u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1368 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1370 return rtl_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1371 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1374 static u32 rtl_get_events(struct rtl8169_private *tp)
1376 if (rtl_is_8125(tp))
1377 return RTL_R32(tp, IntrStatus_8125);
1379 return RTL_R16(tp, IntrStatus);
1382 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits)
1384 if (rtl_is_8125(tp))
1385 RTL_W32(tp, IntrStatus_8125, bits);
1387 RTL_W16(tp, IntrStatus, bits);
1390 static void rtl_irq_disable(struct rtl8169_private *tp)
1392 if (rtl_is_8125(tp))
1393 RTL_W32(tp, IntrMask_8125, 0);
1395 RTL_W16(tp, IntrMask, 0);
1398 static void rtl_irq_enable(struct rtl8169_private *tp)
1400 if (rtl_is_8125(tp))
1401 RTL_W32(tp, IntrMask_8125, tp->irq_mask);
1403 RTL_W16(tp, IntrMask, tp->irq_mask);
1406 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1408 rtl_irq_disable(tp);
1409 rtl_ack_events(tp, 0xffffffff);
1413 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1415 struct phy_device *phydev = tp->phydev;
1417 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1418 tp->mac_version == RTL_GIGA_MAC_VER_38) {
1419 if (phydev->speed == SPEED_1000) {
1420 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1421 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1422 } else if (phydev->speed == SPEED_100) {
1423 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1424 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1426 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1427 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1429 rtl_reset_packet_filter(tp);
1430 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1431 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1432 if (phydev->speed == SPEED_1000) {
1433 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1434 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1436 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1437 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1439 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1440 if (phydev->speed == SPEED_10) {
1441 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02);
1442 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a);
1444 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
1449 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1451 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1453 struct rtl8169_private *tp = netdev_priv(dev);
1455 wol->supported = WAKE_ANY;
1456 wol->wolopts = tp->saved_wolopts;
1459 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1461 static const struct {
1466 { WAKE_PHY, Config3, LinkUp },
1467 { WAKE_UCAST, Config5, UWF },
1468 { WAKE_BCAST, Config5, BWF },
1469 { WAKE_MCAST, Config5, MWF },
1470 { WAKE_ANY, Config5, LanWake },
1471 { WAKE_MAGIC, Config3, MagicPacket }
1473 unsigned int i, tmp = ARRAY_SIZE(cfg);
1474 unsigned long flags;
1477 rtl_unlock_config_regs(tp);
1479 if (rtl_is_8168evl_up(tp)) {
1481 if (wolopts & WAKE_MAGIC)
1482 rtl_eri_set_bits(tp, 0x0dc, MagicPacket_v2);
1484 rtl_eri_clear_bits(tp, 0x0dc, MagicPacket_v2);
1485 } else if (rtl_is_8125(tp)) {
1487 if (wolopts & WAKE_MAGIC)
1488 r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0));
1490 r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0);
1493 raw_spin_lock_irqsave(&tp->config25_lock, flags);
1494 for (i = 0; i < tmp; i++) {
1495 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
1496 if (wolopts & cfg[i].opt)
1497 options |= cfg[i].mask;
1498 RTL_W8(tp, cfg[i].reg, options);
1500 raw_spin_unlock_irqrestore(&tp->config25_lock, flags);
1502 switch (tp->mac_version) {
1503 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
1504 options = RTL_R8(tp, Config1) & ~PMEnable;
1506 options |= PMEnable;
1507 RTL_W8(tp, Config1, options);
1509 case RTL_GIGA_MAC_VER_34:
1510 case RTL_GIGA_MAC_VER_37:
1511 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63:
1513 rtl_mod_config2(tp, 0, PME_SIGNAL);
1515 rtl_mod_config2(tp, PME_SIGNAL, 0);
1521 rtl_lock_config_regs(tp);
1523 device_set_wakeup_enable(tp_to_dev(tp), wolopts);
1525 if (!tp->dash_enabled) {
1526 rtl_set_d3_pll_down(tp, !wolopts);
1527 tp->dev->wol_enabled = wolopts ? 1 : 0;
1531 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1533 struct rtl8169_private *tp = netdev_priv(dev);
1535 if (wol->wolopts & ~WAKE_ANY)
1538 tp->saved_wolopts = wol->wolopts;
1539 __rtl8169_set_wol(tp, tp->saved_wolopts);
1544 static void rtl8169_get_drvinfo(struct net_device *dev,
1545 struct ethtool_drvinfo *info)
1547 struct rtl8169_private *tp = netdev_priv(dev);
1548 struct rtl_fw *rtl_fw = tp->rtl_fw;
1550 strscpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
1551 strscpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1552 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1554 strscpy(info->fw_version, rtl_fw->version,
1555 sizeof(info->fw_version));
1558 static int rtl8169_get_regs_len(struct net_device *dev)
1560 return R8169_REGS_SIZE;
1563 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1564 netdev_features_t features)
1566 struct rtl8169_private *tp = netdev_priv(dev);
1568 if (dev->mtu > TD_MSS_MAX)
1569 features &= ~NETIF_F_ALL_TSO;
1571 if (dev->mtu > ETH_DATA_LEN &&
1572 tp->mac_version > RTL_GIGA_MAC_VER_06)
1573 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_ALL_TSO);
1578 static void rtl_set_rx_config_features(struct rtl8169_private *tp,
1579 netdev_features_t features)
1581 u32 rx_config = RTL_R32(tp, RxConfig);
1583 if (features & NETIF_F_RXALL)
1584 rx_config |= RX_CONFIG_ACCEPT_ERR_MASK;
1586 rx_config &= ~RX_CONFIG_ACCEPT_ERR_MASK;
1588 if (rtl_is_8125(tp)) {
1589 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1590 rx_config |= RX_VLAN_8125;
1592 rx_config &= ~RX_VLAN_8125;
1595 RTL_W32(tp, RxConfig, rx_config);
1598 static int rtl8169_set_features(struct net_device *dev,
1599 netdev_features_t features)
1601 struct rtl8169_private *tp = netdev_priv(dev);
1603 rtl_set_rx_config_features(tp, features);
1605 if (features & NETIF_F_RXCSUM)
1606 tp->cp_cmd |= RxChkSum;
1608 tp->cp_cmd &= ~RxChkSum;
1610 if (!rtl_is_8125(tp)) {
1611 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1612 tp->cp_cmd |= RxVlan;
1614 tp->cp_cmd &= ~RxVlan;
1617 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1623 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1625 return (skb_vlan_tag_present(skb)) ?
1626 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1629 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1631 u32 opts2 = le32_to_cpu(desc->opts2);
1633 if (opts2 & RxVlanTag)
1634 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1637 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1640 struct rtl8169_private *tp = netdev_priv(dev);
1641 u32 __iomem *data = tp->mmio_addr;
1645 for (i = 0; i < R8169_REGS_SIZE; i += 4)
1646 memcpy_fromio(dw++, data++, 4);
1649 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1656 "tx_single_collisions",
1657 "tx_multi_collisions",
1665 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1669 return ARRAY_SIZE(rtl8169_gstrings);
1675 DECLARE_RTL_COND(rtl_counters_cond)
1677 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
1680 static void rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
1682 u32 cmd = lower_32_bits(tp->counters_phys_addr);
1684 RTL_W32(tp, CounterAddrHigh, upper_32_bits(tp->counters_phys_addr));
1686 RTL_W32(tp, CounterAddrLow, cmd);
1687 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
1689 rtl_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
1692 static void rtl8169_update_counters(struct rtl8169_private *tp)
1694 u8 val = RTL_R8(tp, ChipCmd);
1697 * Some chips are unable to dump tally counters when the receiver
1698 * is disabled. If 0xff chip may be in a PCI power-save state.
1700 if (val & CmdRxEnb && val != 0xff)
1701 rtl8169_do_counters(tp, CounterDump);
1704 static void rtl8169_init_counter_offsets(struct rtl8169_private *tp)
1706 struct rtl8169_counters *counters = tp->counters;
1709 * rtl8169_init_counter_offsets is called from rtl_open. On chip
1710 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1711 * reset by a power cycle, while the counter values collected by the
1712 * driver are reset at every driver unload/load cycle.
1714 * To make sure the HW values returned by @get_stats64 match the SW
1715 * values, we collect the initial values at first open(*) and use them
1716 * as offsets to normalize the values returned by @get_stats64.
1718 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1719 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1720 * set at open time by rtl_hw_start.
1723 if (tp->tc_offset.inited)
1726 if (tp->mac_version >= RTL_GIGA_MAC_VER_19) {
1727 rtl8169_do_counters(tp, CounterReset);
1729 rtl8169_update_counters(tp);
1730 tp->tc_offset.tx_errors = counters->tx_errors;
1731 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1732 tp->tc_offset.tx_aborted = counters->tx_aborted;
1733 tp->tc_offset.rx_missed = counters->rx_missed;
1736 tp->tc_offset.inited = true;
1739 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1740 struct ethtool_stats *stats, u64 *data)
1742 struct rtl8169_private *tp = netdev_priv(dev);
1743 struct rtl8169_counters *counters;
1745 counters = tp->counters;
1746 rtl8169_update_counters(tp);
1748 data[0] = le64_to_cpu(counters->tx_packets);
1749 data[1] = le64_to_cpu(counters->rx_packets);
1750 data[2] = le64_to_cpu(counters->tx_errors);
1751 data[3] = le32_to_cpu(counters->rx_errors);
1752 data[4] = le16_to_cpu(counters->rx_missed);
1753 data[5] = le16_to_cpu(counters->align_errors);
1754 data[6] = le32_to_cpu(counters->tx_one_collision);
1755 data[7] = le32_to_cpu(counters->tx_multi_collision);
1756 data[8] = le64_to_cpu(counters->rx_unicast);
1757 data[9] = le64_to_cpu(counters->rx_broadcast);
1758 data[10] = le32_to_cpu(counters->rx_multicast);
1759 data[11] = le16_to_cpu(counters->tx_aborted);
1760 data[12] = le16_to_cpu(counters->tx_underun);
1763 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1767 memcpy(data, rtl8169_gstrings, sizeof(rtl8169_gstrings));
1773 * Interrupt coalescing
1775 * > 1 - the availability of the IntrMitigate (0xe2) register through the
1776 * > 8169, 8168 and 810x line of chipsets
1778 * 8169, 8168, and 8136(810x) serial chipsets support it.
1780 * > 2 - the Tx timer unit at gigabit speed
1782 * The unit of the timer depends on both the speed and the setting of CPlusCmd
1783 * (0xe0) bit 1 and bit 0.
1786 * bit[1:0] \ speed 1000M 100M 10M
1787 * 0 0 320ns 2.56us 40.96us
1788 * 0 1 2.56us 20.48us 327.7us
1789 * 1 0 5.12us 40.96us 655.4us
1790 * 1 1 10.24us 81.92us 1.31ms
1793 * bit[1:0] \ speed 1000M 100M 10M
1794 * 0 0 5us 2.56us 40.96us
1795 * 0 1 40us 20.48us 327.7us
1796 * 1 0 80us 40.96us 655.4us
1797 * 1 1 160us 81.92us 1.31ms
1800 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
1801 struct rtl_coalesce_info {
1806 /* produce array with base delay *1, *8, *8*2, *8*2*2 */
1807 #define COALESCE_DELAY(d) { (d), 8 * (d), 16 * (d), 32 * (d) }
1809 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1810 { SPEED_1000, COALESCE_DELAY(320) },
1811 { SPEED_100, COALESCE_DELAY(2560) },
1812 { SPEED_10, COALESCE_DELAY(40960) },
1816 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1817 { SPEED_1000, COALESCE_DELAY(5000) },
1818 { SPEED_100, COALESCE_DELAY(2560) },
1819 { SPEED_10, COALESCE_DELAY(40960) },
1822 #undef COALESCE_DELAY
1824 /* get rx/tx scale vector corresponding to current speed */
1825 static const struct rtl_coalesce_info *
1826 rtl_coalesce_info(struct rtl8169_private *tp)
1828 const struct rtl_coalesce_info *ci;
1830 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1831 ci = rtl_coalesce_info_8169;
1833 ci = rtl_coalesce_info_8168_8136;
1835 /* if speed is unknown assume highest one */
1836 if (tp->phydev->speed == SPEED_UNKNOWN)
1839 for (; ci->speed; ci++) {
1840 if (tp->phydev->speed == ci->speed)
1844 return ERR_PTR(-ELNRNG);
1847 static int rtl_get_coalesce(struct net_device *dev,
1848 struct ethtool_coalesce *ec,
1849 struct kernel_ethtool_coalesce *kernel_coal,
1850 struct netlink_ext_ack *extack)
1852 struct rtl8169_private *tp = netdev_priv(dev);
1853 const struct rtl_coalesce_info *ci;
1854 u32 scale, c_us, c_fr;
1857 if (rtl_is_8125(tp))
1860 memset(ec, 0, sizeof(*ec));
1862 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1863 ci = rtl_coalesce_info(tp);
1867 scale = ci->scale_nsecs[tp->cp_cmd & INTT_MASK];
1869 intrmit = RTL_R16(tp, IntrMitigate);
1871 c_us = FIELD_GET(RTL_COALESCE_TX_USECS, intrmit);
1872 ec->tx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000);
1874 c_fr = FIELD_GET(RTL_COALESCE_TX_FRAMES, intrmit);
1875 /* ethtool_coalesce states usecs and max_frames must not both be 0 */
1876 ec->tx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1;
1878 c_us = FIELD_GET(RTL_COALESCE_RX_USECS, intrmit);
1879 ec->rx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000);
1881 c_fr = FIELD_GET(RTL_COALESCE_RX_FRAMES, intrmit);
1882 ec->rx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1;
1887 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, usec) */
1888 static int rtl_coalesce_choose_scale(struct rtl8169_private *tp, u32 usec,
1891 const struct rtl_coalesce_info *ci;
1894 ci = rtl_coalesce_info(tp);
1898 for (i = 0; i < 4; i++) {
1899 if (usec <= ci->scale_nsecs[i] * RTL_COALESCE_T_MAX / 1000U) {
1901 return ci->scale_nsecs[i];
1908 static int rtl_set_coalesce(struct net_device *dev,
1909 struct ethtool_coalesce *ec,
1910 struct kernel_ethtool_coalesce *kernel_coal,
1911 struct netlink_ext_ack *extack)
1913 struct rtl8169_private *tp = netdev_priv(dev);
1914 u32 tx_fr = ec->tx_max_coalesced_frames;
1915 u32 rx_fr = ec->rx_max_coalesced_frames;
1916 u32 coal_usec_max, units;
1917 u16 w = 0, cp01 = 0;
1920 if (rtl_is_8125(tp))
1923 if (rx_fr > RTL_COALESCE_FRAME_MAX || tx_fr > RTL_COALESCE_FRAME_MAX)
1926 coal_usec_max = max(ec->rx_coalesce_usecs, ec->tx_coalesce_usecs);
1927 scale = rtl_coalesce_choose_scale(tp, coal_usec_max, &cp01);
1931 /* Accept max_frames=1 we returned in rtl_get_coalesce. Accept it
1932 * not only when usecs=0 because of e.g. the following scenario:
1934 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
1935 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
1936 * - then user does `ethtool -C eth0 rx-usecs 100`
1938 * Since ethtool sends to kernel whole ethtool_coalesce settings,
1939 * if we want to ignore rx_frames then it has to be set to 0.
1946 /* HW requires time limit to be set if frame limit is set */
1947 if ((tx_fr && !ec->tx_coalesce_usecs) ||
1948 (rx_fr && !ec->rx_coalesce_usecs))
1951 w |= FIELD_PREP(RTL_COALESCE_TX_FRAMES, DIV_ROUND_UP(tx_fr, 4));
1952 w |= FIELD_PREP(RTL_COALESCE_RX_FRAMES, DIV_ROUND_UP(rx_fr, 4));
1954 units = DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000U, scale);
1955 w |= FIELD_PREP(RTL_COALESCE_TX_USECS, units);
1956 units = DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000U, scale);
1957 w |= FIELD_PREP(RTL_COALESCE_RX_USECS, units);
1959 RTL_W16(tp, IntrMitigate, w);
1961 /* Meaning of PktCntrDisable bit changed from RTL8168e-vl */
1962 if (rtl_is_8168evl_up(tp)) {
1963 if (!rx_fr && !tx_fr)
1964 /* disable packet counter */
1965 tp->cp_cmd |= PktCntrDisable;
1967 tp->cp_cmd &= ~PktCntrDisable;
1970 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
1971 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1977 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_keee *data)
1979 struct rtl8169_private *tp = netdev_priv(dev);
1981 if (!rtl_supports_eee(tp))
1984 return phy_ethtool_get_eee(tp->phydev, data);
1987 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_keee *data)
1989 struct rtl8169_private *tp = netdev_priv(dev);
1992 if (!rtl_supports_eee(tp))
1995 ret = phy_ethtool_set_eee(tp->phydev, data);
1998 tp->eee_adv = phy_read_mmd(dev->phydev, MDIO_MMD_AN,
2003 static void rtl8169_get_ringparam(struct net_device *dev,
2004 struct ethtool_ringparam *data,
2005 struct kernel_ethtool_ringparam *kernel_data,
2006 struct netlink_ext_ack *extack)
2008 data->rx_max_pending = NUM_RX_DESC;
2009 data->rx_pending = NUM_RX_DESC;
2010 data->tx_max_pending = NUM_TX_DESC;
2011 data->tx_pending = NUM_TX_DESC;
2014 static void rtl8169_get_pauseparam(struct net_device *dev,
2015 struct ethtool_pauseparam *data)
2017 struct rtl8169_private *tp = netdev_priv(dev);
2018 bool tx_pause, rx_pause;
2020 phy_get_pause(tp->phydev, &tx_pause, &rx_pause);
2022 data->autoneg = tp->phydev->autoneg;
2023 data->tx_pause = tx_pause ? 1 : 0;
2024 data->rx_pause = rx_pause ? 1 : 0;
2027 static int rtl8169_set_pauseparam(struct net_device *dev,
2028 struct ethtool_pauseparam *data)
2030 struct rtl8169_private *tp = netdev_priv(dev);
2032 if (dev->mtu > ETH_DATA_LEN)
2035 phy_set_asym_pause(tp->phydev, data->rx_pause, data->tx_pause);
2040 static const struct ethtool_ops rtl8169_ethtool_ops = {
2041 .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
2042 ETHTOOL_COALESCE_MAX_FRAMES,
2043 .get_drvinfo = rtl8169_get_drvinfo,
2044 .get_regs_len = rtl8169_get_regs_len,
2045 .get_link = ethtool_op_get_link,
2046 .get_coalesce = rtl_get_coalesce,
2047 .set_coalesce = rtl_set_coalesce,
2048 .get_regs = rtl8169_get_regs,
2049 .get_wol = rtl8169_get_wol,
2050 .set_wol = rtl8169_set_wol,
2051 .get_strings = rtl8169_get_strings,
2052 .get_sset_count = rtl8169_get_sset_count,
2053 .get_ethtool_stats = rtl8169_get_ethtool_stats,
2054 .get_ts_info = ethtool_op_get_ts_info,
2055 .nway_reset = phy_ethtool_nway_reset,
2056 .get_eee = rtl8169_get_eee,
2057 .set_eee = rtl8169_set_eee,
2058 .get_link_ksettings = phy_ethtool_get_link_ksettings,
2059 .set_link_ksettings = phy_ethtool_set_link_ksettings,
2060 .get_ringparam = rtl8169_get_ringparam,
2061 .get_pauseparam = rtl8169_get_pauseparam,
2062 .set_pauseparam = rtl8169_set_pauseparam,
2065 static void rtl_enable_eee(struct rtl8169_private *tp)
2067 struct phy_device *phydev = tp->phydev;
2070 /* respect EEE advertisement the user may have set */
2071 if (tp->eee_adv >= 0)
2074 adv = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
2077 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, adv);
2080 static enum mac_version rtl8169_get_mac_version(u16 xid, bool gmii)
2083 * The driver currently handles the 8168Bf and the 8168Be identically
2084 * but they can be identified more specifically through the test below
2087 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2089 * Same thing for the 8101Eb and the 8101Ec:
2091 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2093 static const struct rtl_mac_info {
2096 enum mac_version ver;
2099 { 0x7cf, 0x641, RTL_GIGA_MAC_VER_63 },
2102 { 0x7cf, 0x609, RTL_GIGA_MAC_VER_61 },
2103 /* It seems only XID 609 made it to the mass market.
2104 * { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 },
2105 * { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 },
2109 { 0x7cf, 0x54b, RTL_GIGA_MAC_VER_53 },
2110 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52 },
2112 /* 8168EP family. */
2113 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 },
2114 /* It seems this chip version never made it to
2115 * the wild. Let's disable detection.
2116 * { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 },
2117 * { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 },
2121 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 },
2122 /* It seems this chip version never made it to
2123 * the wild. Let's disable detection.
2124 * { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 },
2128 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 },
2129 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 },
2130 /* It seems this chip version never made it to
2131 * the wild. Let's disable detection.
2132 * { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 },
2134 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 },
2137 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 },
2138 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 },
2139 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 },
2142 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 },
2143 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 },
2144 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 },
2147 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 },
2148 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 },
2150 /* 8168DP family. */
2151 /* It seems this early RTL8168dp version never made it to
2152 * the wild. Support has been removed.
2153 * { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 },
2155 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 },
2156 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 },
2159 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 },
2160 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 },
2161 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 },
2162 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 },
2163 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 },
2164 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 },
2165 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 },
2168 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 },
2169 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 },
2172 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 },
2173 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 },
2174 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 },
2175 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 },
2176 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 },
2177 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 },
2178 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 },
2179 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 },
2180 { 0x7cf, 0x240, RTL_GIGA_MAC_VER_14 },
2181 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 },
2182 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 },
2183 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_10 },
2186 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 },
2187 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 },
2188 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 },
2189 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 },
2190 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 },
2193 { 0x000, 0x000, RTL_GIGA_MAC_NONE }
2195 const struct rtl_mac_info *p = mac_info;
2196 enum mac_version ver;
2198 while ((xid & p->mask) != p->val)
2202 if (ver != RTL_GIGA_MAC_NONE && !gmii) {
2203 if (ver == RTL_GIGA_MAC_VER_42)
2204 ver = RTL_GIGA_MAC_VER_43;
2205 else if (ver == RTL_GIGA_MAC_VER_46)
2206 ver = RTL_GIGA_MAC_VER_48;
2212 static void rtl_release_firmware(struct rtl8169_private *tp)
2215 rtl_fw_release_firmware(tp->rtl_fw);
2221 void r8169_apply_firmware(struct rtl8169_private *tp)
2225 /* TODO: release firmware if rtl_fw_write_firmware signals failure. */
2227 rtl_fw_write_firmware(tp, tp->rtl_fw);
2228 /* At least one firmware doesn't reset tp->ocp_base. */
2229 tp->ocp_base = OCP_STD_PHY_BASE;
2231 /* PHY soft reset may still be in progress */
2232 phy_read_poll_timeout(tp->phydev, MII_BMCR, val,
2233 !(val & BMCR_RESET),
2234 50000, 600000, true);
2238 static void rtl8168_config_eee_mac(struct rtl8169_private *tp)
2240 /* Adjust EEE LED frequency */
2241 if (tp->mac_version != RTL_GIGA_MAC_VER_38)
2242 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
2244 rtl_eri_set_bits(tp, 0x1b0, 0x0003);
2247 static void rtl8125a_config_eee_mac(struct rtl8169_private *tp)
2249 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0));
2250 r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1));
2253 static void rtl8125_set_eee_txidle_timer(struct rtl8169_private *tp)
2255 RTL_W16(tp, EEE_TXIDLE_TIMER_8125, tp->dev->mtu + ETH_HLEN + 0x20);
2258 static void rtl8125b_config_eee_mac(struct rtl8169_private *tp)
2260 rtl8125_set_eee_txidle_timer(tp);
2261 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0));
2264 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, const u8 *addr)
2266 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, get_unaligned_le32(addr));
2267 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, get_unaligned_le16(addr + 4));
2268 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, get_unaligned_le16(addr) << 16);
2269 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, get_unaligned_le32(addr + 2));
2272 u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp)
2274 u16 data1, data2, ioffset;
2276 r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
2277 data1 = r8168_mac_ocp_read(tp, 0xdd02);
2278 data2 = r8168_mac_ocp_read(tp, 0xdd00);
2280 ioffset = (data2 >> 1) & 0x7ff8;
2281 ioffset |= data2 & 0x0007;
2288 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
2290 if (!test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
2293 set_bit(flag, tp->wk.flags);
2294 schedule_work(&tp->wk.work);
2297 static void rtl8169_init_phy(struct rtl8169_private *tp)
2299 r8169_hw_phy_config(tp, tp->phydev, tp->mac_version);
2301 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2302 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2303 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
2304 /* set undocumented MAC Reg C+CR Offset 0x82h */
2305 RTL_W8(tp, 0x82, 0x01);
2308 if (tp->mac_version == RTL_GIGA_MAC_VER_05 &&
2309 tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE &&
2310 tp->pci_dev->subsystem_device == 0xe000)
2311 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b);
2313 /* We may have called phy_speed_down before */
2314 phy_speed_up(tp->phydev);
2316 if (rtl_supports_eee(tp))
2319 genphy_soft_reset(tp->phydev);
2322 static void rtl_rar_set(struct rtl8169_private *tp, const u8 *addr)
2324 rtl_unlock_config_regs(tp);
2326 RTL_W32(tp, MAC4, get_unaligned_le16(addr + 4));
2329 RTL_W32(tp, MAC0, get_unaligned_le32(addr));
2332 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
2333 rtl_rar_exgmac_set(tp, addr);
2335 rtl_lock_config_regs(tp);
2338 static int rtl_set_mac_address(struct net_device *dev, void *p)
2340 struct rtl8169_private *tp = netdev_priv(dev);
2343 ret = eth_mac_addr(dev, p);
2347 rtl_rar_set(tp, dev->dev_addr);
2352 static void rtl_init_rxcfg(struct rtl8169_private *tp)
2354 switch (tp->mac_version) {
2355 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
2356 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
2357 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
2359 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
2360 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
2361 case RTL_GIGA_MAC_VER_38:
2362 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
2364 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53:
2365 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
2367 case RTL_GIGA_MAC_VER_61:
2368 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST);
2370 case RTL_GIGA_MAC_VER_63:
2371 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST |
2375 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
2380 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2382 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
2385 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
2387 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2388 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
2391 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
2393 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2394 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
2397 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
2399 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2402 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
2404 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2407 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
2409 RTL_W8(tp, MaxTxPacketSize, 0x24);
2410 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2411 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
2414 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
2416 RTL_W8(tp, MaxTxPacketSize, 0x3f);
2417 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2418 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
2421 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
2423 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
2426 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
2428 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
2431 static void rtl_jumbo_config(struct rtl8169_private *tp)
2433 bool jumbo = tp->dev->mtu > ETH_DATA_LEN;
2436 rtl_unlock_config_regs(tp);
2437 switch (tp->mac_version) {
2438 case RTL_GIGA_MAC_VER_17:
2441 r8168b_1_hw_jumbo_enable(tp);
2443 r8168b_1_hw_jumbo_disable(tp);
2446 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26:
2449 r8168c_hw_jumbo_enable(tp);
2451 r8168c_hw_jumbo_disable(tp);
2454 case RTL_GIGA_MAC_VER_28:
2456 r8168dp_hw_jumbo_enable(tp);
2458 r8168dp_hw_jumbo_disable(tp);
2460 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33:
2462 r8168e_hw_jumbo_enable(tp);
2464 r8168e_hw_jumbo_disable(tp);
2469 rtl_lock_config_regs(tp);
2471 if (pci_is_pcie(tp->pci_dev) && tp->supports_gmii)
2472 pcie_set_readrq(tp->pci_dev, readrq);
2474 /* Chip doesn't support pause in jumbo mode */
2476 linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT,
2477 tp->phydev->advertising);
2478 linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
2479 tp->phydev->advertising);
2480 phy_start_aneg(tp->phydev);
2484 DECLARE_RTL_COND(rtl_chipcmd_cond)
2486 return RTL_R8(tp, ChipCmd) & CmdReset;
2489 static void rtl_hw_reset(struct rtl8169_private *tp)
2491 RTL_W8(tp, ChipCmd, CmdReset);
2493 rtl_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
2496 static void rtl_request_firmware(struct rtl8169_private *tp)
2498 struct rtl_fw *rtl_fw;
2500 /* firmware loaded already or no firmware available */
2501 if (tp->rtl_fw || !tp->fw_name)
2504 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
2508 rtl_fw->phy_write = rtl_writephy;
2509 rtl_fw->phy_read = rtl_readphy;
2510 rtl_fw->mac_mcu_write = mac_mcu_write;
2511 rtl_fw->mac_mcu_read = mac_mcu_read;
2512 rtl_fw->fw_name = tp->fw_name;
2513 rtl_fw->dev = tp_to_dev(tp);
2515 if (rtl_fw_request_firmware(rtl_fw))
2518 tp->rtl_fw = rtl_fw;
2521 static void rtl_rx_close(struct rtl8169_private *tp)
2523 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
2526 DECLARE_RTL_COND(rtl_npq_cond)
2528 return RTL_R8(tp, TxPoll) & NPQ;
2531 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
2533 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
2536 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
2538 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
2541 DECLARE_RTL_COND(rtl_rxtx_empty_cond_2)
2543 /* IntrMitigate has new functionality on RTL8125 */
2544 return (RTL_R16(tp, IntrMitigate) & 0x0103) == 0x0103;
2547 static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp)
2549 switch (tp->mac_version) {
2550 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53:
2551 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42);
2552 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2554 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_61:
2555 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2557 case RTL_GIGA_MAC_VER_63:
2558 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
2559 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2560 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond_2, 100, 42);
2567 static void rtl_disable_rxdvgate(struct rtl8169_private *tp)
2569 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
2572 static void rtl_enable_rxdvgate(struct rtl8169_private *tp)
2574 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
2576 rtl_wait_txrx_fifo_empty(tp);
2579 static void rtl_wol_enable_rx(struct rtl8169_private *tp)
2581 if (tp->mac_version >= RTL_GIGA_MAC_VER_25)
2582 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
2583 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
2585 if (tp->mac_version >= RTL_GIGA_MAC_VER_40)
2586 rtl_disable_rxdvgate(tp);
2589 static void rtl_prepare_power_down(struct rtl8169_private *tp)
2591 if (tp->dash_enabled)
2594 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
2595 tp->mac_version == RTL_GIGA_MAC_VER_33)
2596 rtl_ephy_write(tp, 0x19, 0xff64);
2598 if (device_may_wakeup(tp_to_dev(tp))) {
2599 phy_speed_down(tp->phydev, false);
2600 rtl_wol_enable_rx(tp);
2604 static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
2606 u32 val = TX_DMA_BURST << TxDMAShift |
2607 InterFrameGap << TxInterFrameGapShift;
2609 if (rtl_is_8168evl_up(tp))
2610 val |= TXCFG_AUTO_FIFO;
2612 RTL_W32(tp, TxConfig, val);
2615 static void rtl_set_rx_max_size(struct rtl8169_private *tp)
2617 /* Low hurts. Let's disable the filtering. */
2618 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
2621 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
2624 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
2625 * register to be written before TxDescAddrLow to work.
2626 * Switching from MMIO to I/O access fixes the issue as well.
2628 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
2629 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
2630 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
2631 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
2634 static void rtl8169_set_magic_reg(struct rtl8169_private *tp)
2638 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
2640 else if (tp->mac_version == RTL_GIGA_MAC_VER_06)
2645 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz)
2648 RTL_W32(tp, 0x7c, val);
2651 static void rtl_set_rx_mode(struct net_device *dev)
2653 u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast;
2654 /* Multicast hash filter */
2655 u32 mc_filter[2] = { 0xffffffff, 0xffffffff };
2656 struct rtl8169_private *tp = netdev_priv(dev);
2659 if (dev->flags & IFF_PROMISC) {
2660 rx_mode |= AcceptAllPhys;
2661 } else if (!(dev->flags & IFF_MULTICAST)) {
2662 rx_mode &= ~AcceptMulticast;
2663 } else if (dev->flags & IFF_ALLMULTI ||
2664 tp->mac_version == RTL_GIGA_MAC_VER_35) {
2665 /* accept all multicasts */
2666 } else if (netdev_mc_empty(dev)) {
2667 rx_mode &= ~AcceptMulticast;
2669 struct netdev_hw_addr *ha;
2671 mc_filter[1] = mc_filter[0] = 0;
2672 netdev_for_each_mc_addr(ha, dev) {
2673 u32 bit_nr = eth_hw_addr_crc(ha) >> 26;
2674 mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31);
2677 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
2679 mc_filter[0] = swab32(mc_filter[1]);
2680 mc_filter[1] = swab32(tmp);
2684 RTL_W32(tp, MAR0 + 4, mc_filter[1]);
2685 RTL_W32(tp, MAR0 + 0, mc_filter[0]);
2687 tmp = RTL_R32(tp, RxConfig);
2688 RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode);
2691 DECLARE_RTL_COND(rtl_csiar_cond)
2693 return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
2696 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
2698 u32 func = PCI_FUNC(tp->pci_dev->devfn);
2700 RTL_W32(tp, CSIDR, value);
2701 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
2702 CSIAR_BYTE_ENABLE | func << 16);
2704 rtl_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
2707 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
2709 u32 func = PCI_FUNC(tp->pci_dev->devfn);
2711 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
2714 return rtl_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
2715 RTL_R32(tp, CSIDR) : ~0;
2718 static void rtl_set_aspm_entry_latency(struct rtl8169_private *tp, u8 val)
2720 struct pci_dev *pdev = tp->pci_dev;
2723 /* According to Realtek the value at config space address 0x070f
2724 * controls the L0s/L1 entrance latency. We try standard ECAM access
2725 * first and if it fails fall back to CSI.
2726 * bit 0..2: L0: 0 = 1us, 1 = 2us .. 6 = 7us, 7 = 7us (no typo)
2727 * bit 3..5: L1: 0 = 1us, 1 = 2us .. 6 = 64us, 7 = 64us
2729 if (pdev->cfg_size > 0x070f &&
2730 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
2733 netdev_notice_once(tp->dev,
2734 "No native access to PCI extended config space, falling back to CSI\n");
2735 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
2736 rtl_csi_write(tp, 0x070c, csi | val << 24);
2739 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
2741 /* L0 7us, L1 16us */
2742 rtl_set_aspm_entry_latency(tp, 0x27);
2746 unsigned int offset;
2751 static void __rtl_ephy_init(struct rtl8169_private *tp,
2752 const struct ephy_info *e, int len)
2757 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
2758 rtl_ephy_write(tp, e->offset, w);
2763 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a))
2765 static void rtl_disable_clock_request(struct rtl8169_private *tp)
2767 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
2768 PCI_EXP_LNKCTL_CLKREQ_EN);
2771 static void rtl_enable_clock_request(struct rtl8169_private *tp)
2773 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
2774 PCI_EXP_LNKCTL_CLKREQ_EN);
2777 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp)
2779 /* work around an issue when PCI reset occurs during L2/L3 state */
2780 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23);
2783 static void rtl_enable_exit_l1(struct rtl8169_private *tp)
2785 /* Bits control which events trigger ASPM L1 exit:
2788 * Bit 10: txdma_poll
2793 switch (tp->mac_version) {
2794 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
2795 rtl_eri_set_bits(tp, 0xd4, 0x1f00);
2797 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_38:
2798 rtl_eri_set_bits(tp, 0xd4, 0x0c00);
2800 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
2801 r8168_mac_ocp_modify(tp, 0xc0ac, 0, 0x1f80);
2808 static void rtl_disable_exit_l1(struct rtl8169_private *tp)
2810 switch (tp->mac_version) {
2811 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
2812 rtl_eri_clear_bits(tp, 0xd4, 0x1f00);
2814 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
2815 r8168_mac_ocp_modify(tp, 0xc0ac, 0x1f80, 0);
2822 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
2824 if (tp->mac_version < RTL_GIGA_MAC_VER_32)
2827 /* Don't enable ASPM in the chip if OS can't control ASPM */
2828 if (enable && tp->aspm_manageable) {
2829 /* On these chip versions ASPM can even harm
2830 * bus communication of other PCI devices.
2832 if (tp->mac_version == RTL_GIGA_MAC_VER_42 ||
2833 tp->mac_version == RTL_GIGA_MAC_VER_43)
2836 rtl_mod_config5(tp, 0, ASPM_en);
2837 rtl_mod_config2(tp, 0, ClkReqEn);
2839 switch (tp->mac_version) {
2840 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48:
2841 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63:
2842 /* reset ephy tx/rx disable timer */
2843 r8168_mac_ocp_modify(tp, 0xe094, 0xff00, 0);
2844 /* chip can trigger L1.2 */
2845 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, BIT(2));
2851 switch (tp->mac_version) {
2852 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48:
2853 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63:
2854 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, 0);
2860 rtl_mod_config2(tp, ClkReqEn, 0);
2861 rtl_mod_config5(tp, ASPM_en, 0);
2865 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat,
2866 u16 tx_stat, u16 rx_dyn, u16 tx_dyn)
2868 /* Usage of dynamic vs. static FIFO is controlled by bit
2869 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known.
2871 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn);
2872 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn);
2875 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp,
2878 /* FIFO thresholds for pause flow control */
2879 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low);
2880 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high);
2883 static void rtl_hw_start_8168b(struct rtl8169_private *tp)
2885 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2888 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
2890 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
2892 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2894 rtl_disable_clock_request(tp);
2897 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
2899 static const struct ephy_info e_info_8168cp[] = {
2900 { 0x01, 0, 0x0001 },
2901 { 0x02, 0x0800, 0x1000 },
2902 { 0x03, 0, 0x0042 },
2903 { 0x06, 0x0080, 0x0000 },
2907 rtl_set_def_aspm_entry_latency(tp);
2909 rtl_ephy_init(tp, e_info_8168cp);
2911 __rtl_hw_start_8168cp(tp);
2914 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
2916 rtl_set_def_aspm_entry_latency(tp);
2918 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2921 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
2923 rtl_set_def_aspm_entry_latency(tp);
2925 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2928 RTL_W8(tp, DBG_REG, 0x20);
2931 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
2933 static const struct ephy_info e_info_8168c_1[] = {
2934 { 0x02, 0x0800, 0x1000 },
2935 { 0x03, 0, 0x0002 },
2936 { 0x06, 0x0080, 0x0000 }
2939 rtl_set_def_aspm_entry_latency(tp);
2941 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
2943 rtl_ephy_init(tp, e_info_8168c_1);
2945 __rtl_hw_start_8168cp(tp);
2948 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
2950 static const struct ephy_info e_info_8168c_2[] = {
2951 { 0x01, 0, 0x0001 },
2952 { 0x03, 0x0400, 0x0020 }
2955 rtl_set_def_aspm_entry_latency(tp);
2957 rtl_ephy_init(tp, e_info_8168c_2);
2959 __rtl_hw_start_8168cp(tp);
2962 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
2964 rtl_set_def_aspm_entry_latency(tp);
2966 __rtl_hw_start_8168cp(tp);
2969 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
2971 rtl_set_def_aspm_entry_latency(tp);
2973 rtl_disable_clock_request(tp);
2976 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
2978 static const struct ephy_info e_info_8168d_4[] = {
2979 { 0x0b, 0x0000, 0x0048 },
2980 { 0x19, 0x0020, 0x0050 },
2981 { 0x0c, 0x0100, 0x0020 },
2982 { 0x10, 0x0004, 0x0000 },
2985 rtl_set_def_aspm_entry_latency(tp);
2987 rtl_ephy_init(tp, e_info_8168d_4);
2989 rtl_enable_clock_request(tp);
2992 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
2994 static const struct ephy_info e_info_8168e_1[] = {
2995 { 0x00, 0x0200, 0x0100 },
2996 { 0x00, 0x0000, 0x0004 },
2997 { 0x06, 0x0002, 0x0001 },
2998 { 0x06, 0x0000, 0x0030 },
2999 { 0x07, 0x0000, 0x2000 },
3000 { 0x00, 0x0000, 0x0020 },
3001 { 0x03, 0x5800, 0x2000 },
3002 { 0x03, 0x0000, 0x0001 },
3003 { 0x01, 0x0800, 0x1000 },
3004 { 0x07, 0x0000, 0x4000 },
3005 { 0x1e, 0x0000, 0x2000 },
3006 { 0x19, 0xffff, 0xfe6c },
3007 { 0x0a, 0x0000, 0x0040 }
3010 rtl_set_def_aspm_entry_latency(tp);
3012 rtl_ephy_init(tp, e_info_8168e_1);
3014 rtl_disable_clock_request(tp);
3016 /* Reset tx FIFO pointer */
3017 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
3018 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
3020 rtl_mod_config5(tp, Spi_en, 0);
3023 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
3025 static const struct ephy_info e_info_8168e_2[] = {
3026 { 0x09, 0x0000, 0x0080 },
3027 { 0x19, 0x0000, 0x0224 },
3028 { 0x00, 0x0000, 0x0004 },
3029 { 0x0c, 0x3df0, 0x0200 },
3032 rtl_set_def_aspm_entry_latency(tp);
3034 rtl_ephy_init(tp, e_info_8168e_2);
3036 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3037 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000);
3038 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
3039 rtl_eri_set_bits(tp, 0x1d0, BIT(1));
3040 rtl_reset_packet_filter(tp);
3041 rtl_eri_set_bits(tp, 0x1b0, BIT(4));
3042 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
3043 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060);
3045 rtl_disable_clock_request(tp);
3047 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
3049 rtl8168_config_eee_mac(tp);
3051 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
3052 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
3053 rtl_mod_config5(tp, Spi_en, 0);
3056 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
3058 rtl_set_def_aspm_entry_latency(tp);
3060 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3061 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000);
3062 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
3063 rtl_reset_packet_filter(tp);
3064 rtl_eri_set_bits(tp, 0x1b0, BIT(4));
3065 rtl_eri_set_bits(tp, 0x1d0, BIT(4) | BIT(1));
3066 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
3067 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060);
3069 rtl_disable_clock_request(tp);
3071 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
3072 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
3073 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
3074 rtl_mod_config5(tp, Spi_en, 0);
3076 rtl8168_config_eee_mac(tp);
3079 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
3081 static const struct ephy_info e_info_8168f_1[] = {
3082 { 0x06, 0x00c0, 0x0020 },
3083 { 0x08, 0x0001, 0x0002 },
3084 { 0x09, 0x0000, 0x0080 },
3085 { 0x19, 0x0000, 0x0224 },
3086 { 0x00, 0x0000, 0x0008 },
3087 { 0x0c, 0x3df0, 0x0200 },
3090 rtl_hw_start_8168f(tp);
3092 rtl_ephy_init(tp, e_info_8168f_1);
3095 static void rtl_hw_start_8411(struct rtl8169_private *tp)
3097 static const struct ephy_info e_info_8168f_1[] = {
3098 { 0x06, 0x00c0, 0x0020 },
3099 { 0x0f, 0xffff, 0x5200 },
3100 { 0x19, 0x0000, 0x0224 },
3101 { 0x00, 0x0000, 0x0008 },
3102 { 0x0c, 0x3df0, 0x0200 },
3105 rtl_hw_start_8168f(tp);
3106 rtl_pcie_state_l2l3_disable(tp);
3108 rtl_ephy_init(tp, e_info_8168f_1);
3111 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
3113 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3114 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
3116 rtl_set_def_aspm_entry_latency(tp);
3118 rtl_reset_packet_filter(tp);
3119 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f);
3121 rtl_disable_rxdvgate(tp);
3123 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3124 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3126 rtl8168_config_eee_mac(tp);
3128 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06);
3129 rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
3131 rtl_pcie_state_l2l3_disable(tp);
3134 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
3136 static const struct ephy_info e_info_8168g_1[] = {
3137 { 0x00, 0x0008, 0x0000 },
3138 { 0x0c, 0x3ff0, 0x0820 },
3139 { 0x1e, 0x0000, 0x0001 },
3140 { 0x19, 0x8000, 0x0000 }
3143 rtl_hw_start_8168g(tp);
3144 rtl_ephy_init(tp, e_info_8168g_1);
3147 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
3149 static const struct ephy_info e_info_8168g_2[] = {
3150 { 0x00, 0x0008, 0x0000 },
3151 { 0x0c, 0x3ff0, 0x0820 },
3152 { 0x19, 0xffff, 0x7c00 },
3153 { 0x1e, 0xffff, 0x20eb },
3154 { 0x0d, 0xffff, 0x1666 },
3155 { 0x00, 0xffff, 0x10a3 },
3156 { 0x06, 0xffff, 0xf050 },
3157 { 0x04, 0x0000, 0x0010 },
3158 { 0x1d, 0x4000, 0x0000 },
3161 rtl_hw_start_8168g(tp);
3162 rtl_ephy_init(tp, e_info_8168g_2);
3165 static void rtl8411b_fix_phy_down(struct rtl8169_private *tp)
3167 static const u16 fix_data[] = {
3168 /* 0xf800 */ 0xe008, 0xe00a, 0xe00c, 0xe00e, 0xe027, 0xe04f, 0xe05e, 0xe065,
3169 /* 0xf810 */ 0xc602, 0xbe00, 0x0000, 0xc502, 0xbd00, 0x074c, 0xc302, 0xbb00,
3170 /* 0xf820 */ 0x080a, 0x6420, 0x48c2, 0x8c20, 0xc516, 0x64a4, 0x49c0, 0xf009,
3171 /* 0xf830 */ 0x74a2, 0x8ca5, 0x74a0, 0xc50e, 0x9ca2, 0x1c11, 0x9ca0, 0xe006,
3172 /* 0xf840 */ 0x74f8, 0x48c4, 0x8cf8, 0xc404, 0xbc00, 0xc403, 0xbc00, 0x0bf2,
3173 /* 0xf850 */ 0x0c0a, 0xe434, 0xd3c0, 0x49d9, 0xf01f, 0xc526, 0x64a5, 0x1400,
3174 /* 0xf860 */ 0xf007, 0x0c01, 0x8ca5, 0x1c15, 0xc51b, 0x9ca0, 0xe013, 0xc519,
3175 /* 0xf870 */ 0x74a0, 0x48c4, 0x8ca0, 0xc516, 0x74a4, 0x48c8, 0x48ca, 0x9ca4,
3176 /* 0xf880 */ 0xc512, 0x1b00, 0x9ba0, 0x1b1c, 0x483f, 0x9ba2, 0x1b04, 0xc508,
3177 /* 0xf890 */ 0x9ba0, 0xc505, 0xbd00, 0xc502, 0xbd00, 0x0300, 0x051e, 0xe434,
3178 /* 0xf8a0 */ 0xe018, 0xe092, 0xde20, 0xd3c0, 0xc50f, 0x76a4, 0x49e3, 0xf007,
3179 /* 0xf8b0 */ 0x49c0, 0xf103, 0xc607, 0xbe00, 0xc606, 0xbe00, 0xc602, 0xbe00,
3180 /* 0xf8c0 */ 0x0c4c, 0x0c28, 0x0c2c, 0xdc00, 0xc707, 0x1d00, 0x8de2, 0x48c1,
3181 /* 0xf8d0 */ 0xc502, 0xbd00, 0x00aa, 0xe0c0, 0xc502, 0xbd00, 0x0132
3183 unsigned long flags;
3186 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags);
3187 for (i = 0; i < ARRAY_SIZE(fix_data); i++)
3188 __r8168_mac_ocp_write(tp, 0xf800 + 2 * i, fix_data[i]);
3189 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags);
3192 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
3194 static const struct ephy_info e_info_8411_2[] = {
3195 { 0x00, 0x0008, 0x0000 },
3196 { 0x0c, 0x37d0, 0x0820 },
3197 { 0x1e, 0x0000, 0x0001 },
3198 { 0x19, 0x8021, 0x0000 },
3199 { 0x1e, 0x0000, 0x2000 },
3200 { 0x0d, 0x0100, 0x0200 },
3201 { 0x00, 0x0000, 0x0080 },
3202 { 0x06, 0x0000, 0x0010 },
3203 { 0x04, 0x0000, 0x0010 },
3204 { 0x1d, 0x0000, 0x4000 },
3207 rtl_hw_start_8168g(tp);
3209 rtl_ephy_init(tp, e_info_8411_2);
3211 /* The following Realtek-provided magic fixes an issue with the RX unit
3212 * getting confused after the PHY having been powered-down.
3214 r8168_mac_ocp_write(tp, 0xFC28, 0x0000);
3215 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000);
3216 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000);
3217 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000);
3218 r8168_mac_ocp_write(tp, 0xFC30, 0x0000);
3219 r8168_mac_ocp_write(tp, 0xFC32, 0x0000);
3220 r8168_mac_ocp_write(tp, 0xFC34, 0x0000);
3221 r8168_mac_ocp_write(tp, 0xFC36, 0x0000);
3223 r8168_mac_ocp_write(tp, 0xFC26, 0x0000);
3225 rtl8411b_fix_phy_down(tp);
3227 r8168_mac_ocp_write(tp, 0xFC26, 0x8000);
3229 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743);
3230 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801);
3231 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9);
3232 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD);
3233 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25);
3234 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9);
3235 r8168_mac_ocp_write(tp, 0xFC36, 0x012D);
3238 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
3240 static const struct ephy_info e_info_8168h_1[] = {
3241 { 0x1e, 0x0800, 0x0001 },
3242 { 0x1d, 0x0000, 0x0800 },
3243 { 0x05, 0xffff, 0x2089 },
3244 { 0x06, 0xffff, 0x5881 },
3245 { 0x04, 0xffff, 0x854a },
3246 { 0x01, 0xffff, 0x068b }
3250 rtl_ephy_init(tp, e_info_8168h_1);
3252 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3253 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
3255 rtl_set_def_aspm_entry_latency(tp);
3257 rtl_reset_packet_filter(tp);
3259 rtl_eri_set_bits(tp, 0xdc, 0x001c);
3261 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3263 rtl_disable_rxdvgate(tp);
3265 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3266 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3268 rtl8168_config_eee_mac(tp);
3270 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3271 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3273 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3275 rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
3277 rtl_pcie_state_l2l3_disable(tp);
3279 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff;
3280 if (rg_saw_cnt > 0) {
3283 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
3284 sw_cnt_1ms_ini &= 0x0fff;
3285 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);
3288 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);
3289 r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008);
3290 r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f);
3291 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);
3293 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
3294 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
3295 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
3296 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
3299 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
3301 rtl8168ep_stop_cmac(tp);
3303 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3304 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
3306 rtl_set_def_aspm_entry_latency(tp);
3308 rtl_reset_packet_filter(tp);
3310 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3312 rtl_disable_rxdvgate(tp);
3314 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3315 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3317 rtl8168_config_eee_mac(tp);
3319 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06);
3321 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3323 rtl_pcie_state_l2l3_disable(tp);
3326 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
3328 static const struct ephy_info e_info_8168ep_3[] = {
3329 { 0x00, 0x0000, 0x0080 },
3330 { 0x0d, 0x0100, 0x0200 },
3331 { 0x19, 0x8021, 0x0000 },
3332 { 0x1e, 0x0000, 0x2000 },
3335 rtl_ephy_init(tp, e_info_8168ep_3);
3337 rtl_hw_start_8168ep(tp);
3339 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3340 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3342 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271);
3343 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
3344 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);
3347 static void rtl_hw_start_8117(struct rtl8169_private *tp)
3349 static const struct ephy_info e_info_8117[] = {
3350 { 0x19, 0x0040, 0x1100 },
3351 { 0x59, 0x0040, 0x1100 },
3355 rtl8168ep_stop_cmac(tp);
3356 rtl_ephy_init(tp, e_info_8117);
3358 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3359 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
3361 rtl_set_def_aspm_entry_latency(tp);
3363 rtl_reset_packet_filter(tp);
3365 rtl_eri_set_bits(tp, 0xd4, 0x0010);
3367 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3369 rtl_disable_rxdvgate(tp);
3371 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3372 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3374 rtl8168_config_eee_mac(tp);
3376 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3377 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3379 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3381 rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
3383 rtl_pcie_state_l2l3_disable(tp);
3385 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff;
3386 if (rg_saw_cnt > 0) {
3389 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff;
3390 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);
3393 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);
3394 r8168_mac_ocp_write(tp, 0xea80, 0x0003);
3395 r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009);
3396 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);
3398 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
3399 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
3400 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
3401 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
3403 /* firmware is for MAC only */
3404 r8169_apply_firmware(tp);
3407 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
3409 static const struct ephy_info e_info_8102e_1[] = {
3410 { 0x01, 0, 0x6e65 },
3411 { 0x02, 0, 0x091f },
3412 { 0x03, 0, 0xc2f9 },
3413 { 0x06, 0, 0xafb5 },
3414 { 0x07, 0, 0x0e00 },
3415 { 0x19, 0, 0xec80 },
3416 { 0x01, 0, 0x2e65 },
3421 rtl_set_def_aspm_entry_latency(tp);
3423 RTL_W8(tp, DBG_REG, FIX_NAK_1);
3426 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
3427 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3429 cfg1 = RTL_R8(tp, Config1);
3430 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
3431 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
3433 rtl_ephy_init(tp, e_info_8102e_1);
3436 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
3438 rtl_set_def_aspm_entry_latency(tp);
3440 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
3441 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3444 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
3446 rtl_hw_start_8102e_2(tp);
3448 rtl_ephy_write(tp, 0x03, 0xc2f9);
3451 static void rtl_hw_start_8401(struct rtl8169_private *tp)
3453 static const struct ephy_info e_info_8401[] = {
3454 { 0x01, 0xffff, 0x6fe5 },
3455 { 0x03, 0xffff, 0x0599 },
3456 { 0x06, 0xffff, 0xaf25 },
3457 { 0x07, 0xffff, 0x8e68 },
3460 rtl_ephy_init(tp, e_info_8401);
3461 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3464 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
3466 static const struct ephy_info e_info_8105e_1[] = {
3467 { 0x07, 0, 0x4000 },
3468 { 0x19, 0, 0x0200 },
3469 { 0x19, 0, 0x0020 },
3470 { 0x1e, 0, 0x2000 },
3471 { 0x03, 0, 0x0001 },
3472 { 0x19, 0, 0x0100 },
3473 { 0x19, 0, 0x0004 },
3477 /* Force LAN exit from ASPM if Rx/Tx are not idle */
3478 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3480 /* Disable Early Tally Counter */
3481 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
3483 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
3484 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
3486 rtl_ephy_init(tp, e_info_8105e_1);
3488 rtl_pcie_state_l2l3_disable(tp);
3491 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
3493 rtl_hw_start_8105e_1(tp);
3494 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
3497 static void rtl_hw_start_8402(struct rtl8169_private *tp)
3499 static const struct ephy_info e_info_8402[] = {
3500 { 0x19, 0xffff, 0xff64 },
3504 rtl_set_def_aspm_entry_latency(tp);
3506 /* Force LAN exit from ASPM if Rx/Tx are not idle */
3507 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3509 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
3511 rtl_ephy_init(tp, e_info_8402);
3513 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06);
3514 rtl_reset_packet_filter(tp);
3515 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3516 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3517 rtl_w0w1_eri(tp, 0x0d4, 0x0e00, 0xff00);
3520 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3522 rtl_pcie_state_l2l3_disable(tp);
3525 static void rtl_hw_start_8106(struct rtl8169_private *tp)
3527 /* Force LAN exit from ASPM if Rx/Tx are not idle */
3528 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3530 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
3531 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
3532 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3534 /* L0 7us, L1 32us - needed to avoid issues with link-up detection */
3535 rtl_set_aspm_entry_latency(tp, 0x2f);
3537 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
3540 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3542 rtl_pcie_state_l2l3_disable(tp);
3545 DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond)
3547 return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13);
3550 static void rtl_hw_start_8125_common(struct rtl8169_private *tp)
3552 rtl_pcie_state_l2l3_disable(tp);
3554 RTL_W16(tp, 0x382, 0x221b);
3555 RTL_W8(tp, 0x4500, 0);
3556 RTL_W16(tp, 0x4800, 0);
3559 r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000);
3561 RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10);
3563 r8168_mac_ocp_write(tp, 0xc140, 0xffff);
3564 r8168_mac_ocp_write(tp, 0xc142, 0xffff);
3566 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9);
3567 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
3568 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);
3570 /* disable new tx descriptor format */
3571 r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000);
3573 if (tp->mac_version == RTL_GIGA_MAC_VER_63)
3574 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200);
3576 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400);
3578 if (tp->mac_version == RTL_GIGA_MAC_VER_63)
3579 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0000);
3581 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020);
3583 r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c);
3584 r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033);
3585 r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040);
3586 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030);
3587 r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000);
3588 r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001);
3589 r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403);
3590 r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0068);
3591 r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f);
3593 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000);
3594 r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001);
3596 r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000);
3597 RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030);
3599 r8168_mac_ocp_write(tp, 0xe098, 0xc302);
3601 rtl_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10);
3603 if (tp->mac_version == RTL_GIGA_MAC_VER_63)
3604 rtl8125b_config_eee_mac(tp);
3606 rtl8125a_config_eee_mac(tp);
3608 rtl_disable_rxdvgate(tp);
3611 static void rtl_hw_start_8125a_2(struct rtl8169_private *tp)
3613 static const struct ephy_info e_info_8125a_2[] = {
3614 { 0x04, 0xffff, 0xd000 },
3615 { 0x0a, 0xffff, 0x8653 },
3616 { 0x23, 0xffff, 0xab66 },
3617 { 0x20, 0xffff, 0x9455 },
3618 { 0x21, 0xffff, 0x99ff },
3619 { 0x29, 0xffff, 0xfe04 },
3621 { 0x44, 0xffff, 0xd000 },
3622 { 0x4a, 0xffff, 0x8653 },
3623 { 0x63, 0xffff, 0xab66 },
3624 { 0x60, 0xffff, 0x9455 },
3625 { 0x61, 0xffff, 0x99ff },
3626 { 0x69, 0xffff, 0xfe04 },
3629 rtl_set_def_aspm_entry_latency(tp);
3630 rtl_ephy_init(tp, e_info_8125a_2);
3631 rtl_hw_start_8125_common(tp);
3634 static void rtl_hw_start_8125b(struct rtl8169_private *tp)
3636 static const struct ephy_info e_info_8125b[] = {
3637 { 0x0b, 0xffff, 0xa908 },
3638 { 0x1e, 0xffff, 0x20eb },
3639 { 0x4b, 0xffff, 0xa908 },
3640 { 0x5e, 0xffff, 0x20eb },
3641 { 0x22, 0x0030, 0x0020 },
3642 { 0x62, 0x0030, 0x0020 },
3645 rtl_set_def_aspm_entry_latency(tp);
3646 rtl_ephy_init(tp, e_info_8125b);
3647 rtl_hw_start_8125_common(tp);
3650 static void rtl_hw_config(struct rtl8169_private *tp)
3652 static const rtl_generic_fct hw_configs[] = {
3653 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1,
3654 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3,
3655 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2,
3656 [RTL_GIGA_MAC_VER_10] = NULL,
3657 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168b,
3658 [RTL_GIGA_MAC_VER_14] = rtl_hw_start_8401,
3659 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b,
3660 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1,
3661 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1,
3662 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2,
3663 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_2,
3664 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4,
3665 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2,
3666 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3,
3667 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d,
3668 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d,
3669 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4,
3670 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1,
3671 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2,
3672 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168d,
3673 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1,
3674 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1,
3675 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2,
3676 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1,
3677 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1,
3678 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402,
3679 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411,
3680 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106,
3681 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1,
3682 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2,
3683 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2,
3684 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2,
3685 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1,
3686 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1,
3687 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3,
3688 [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117,
3689 [RTL_GIGA_MAC_VER_53] = rtl_hw_start_8117,
3690 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2,
3691 [RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b,
3694 if (hw_configs[tp->mac_version])
3695 hw_configs[tp->mac_version](tp);
3698 static void rtl_hw_start_8125(struct rtl8169_private *tp)
3702 /* disable interrupt coalescing */
3703 for (i = 0xa00; i < 0xb00; i += 4)
3709 static void rtl_hw_start_8168(struct rtl8169_private *tp)
3711 if (rtl_is_8168evl_up(tp))
3712 RTL_W8(tp, MaxTxPacketSize, EarlySize);
3714 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
3718 /* disable interrupt coalescing */
3719 RTL_W16(tp, IntrMitigate, 0x0000);
3722 static void rtl_hw_start_8169(struct rtl8169_private *tp)
3724 RTL_W8(tp, EarlyTxThres, NoEarlyTx);
3726 tp->cp_cmd |= PCIMulRW;
3728 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3729 tp->mac_version == RTL_GIGA_MAC_VER_03)
3730 tp->cp_cmd |= EnAnaPLL;
3732 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
3734 rtl8169_set_magic_reg(tp);
3736 /* disable interrupt coalescing */
3737 RTL_W16(tp, IntrMitigate, 0x0000);
3740 static void rtl_hw_start(struct rtl8169_private *tp)
3742 rtl_unlock_config_regs(tp);
3743 /* disable aspm and clock request before ephy access */
3744 rtl_hw_aspm_clkreq_enable(tp, false);
3745 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
3747 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3748 rtl_hw_start_8169(tp);
3749 else if (rtl_is_8125(tp))
3750 rtl_hw_start_8125(tp);
3752 rtl_hw_start_8168(tp);
3754 rtl_enable_exit_l1(tp);
3755 rtl_hw_aspm_clkreq_enable(tp, true);
3756 rtl_set_rx_max_size(tp);
3757 rtl_set_rx_tx_desc_registers(tp);
3758 rtl_lock_config_regs(tp);
3760 rtl_jumbo_config(tp);
3762 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3765 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
3767 rtl_set_tx_config_registers(tp);
3768 rtl_set_rx_config_features(tp, tp->dev->features);
3769 rtl_set_rx_mode(tp->dev);
3773 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
3775 struct rtl8169_private *tp = netdev_priv(dev);
3778 netdev_update_features(dev);
3779 rtl_jumbo_config(tp);
3781 switch (tp->mac_version) {
3782 case RTL_GIGA_MAC_VER_61:
3783 case RTL_GIGA_MAC_VER_63:
3784 rtl8125_set_eee_txidle_timer(tp);
3793 static void rtl8169_mark_to_asic(struct RxDesc *desc)
3795 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
3798 /* Force memory writes to complete before releasing descriptor */
3800 WRITE_ONCE(desc->opts1, cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE));
3803 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
3804 struct RxDesc *desc)
3806 struct device *d = tp_to_dev(tp);
3807 int node = dev_to_node(d);
3811 data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE));
3815 mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
3816 if (unlikely(dma_mapping_error(d, mapping))) {
3817 netdev_err(tp->dev, "Failed to map RX DMA!\n");
3818 __free_pages(data, get_order(R8169_RX_BUF_SIZE));
3822 desc->addr = cpu_to_le64(mapping);
3823 rtl8169_mark_to_asic(desc);
3828 static void rtl8169_rx_clear(struct rtl8169_private *tp)
3832 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) {
3833 dma_unmap_page(tp_to_dev(tp),
3834 le64_to_cpu(tp->RxDescArray[i].addr),
3835 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
3836 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE));
3837 tp->Rx_databuff[i] = NULL;
3838 tp->RxDescArray[i].addr = 0;
3839 tp->RxDescArray[i].opts1 = 0;
3843 static int rtl8169_rx_fill(struct rtl8169_private *tp)
3847 for (i = 0; i < NUM_RX_DESC; i++) {
3850 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
3852 rtl8169_rx_clear(tp);
3855 tp->Rx_databuff[i] = data;
3858 /* mark as last descriptor in the ring */
3859 tp->RxDescArray[NUM_RX_DESC - 1].opts1 |= cpu_to_le32(RingEnd);
3864 static int rtl8169_init_ring(struct rtl8169_private *tp)
3866 rtl8169_init_ring_indexes(tp);
3868 memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
3869 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
3871 return rtl8169_rx_fill(tp);
3874 static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int entry)
3876 struct ring_info *tx_skb = tp->tx_skb + entry;
3877 struct TxDesc *desc = tp->TxDescArray + entry;
3879 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), tx_skb->len,
3881 memset(desc, 0, sizeof(*desc));
3882 memset(tx_skb, 0, sizeof(*tx_skb));
3885 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
3890 for (i = 0; i < n; i++) {
3891 unsigned int entry = (start + i) % NUM_TX_DESC;
3892 struct ring_info *tx_skb = tp->tx_skb + entry;
3893 unsigned int len = tx_skb->len;
3896 struct sk_buff *skb = tx_skb->skb;
3898 rtl8169_unmap_tx_skb(tp, entry);
3900 dev_consume_skb_any(skb);
3905 static void rtl8169_tx_clear(struct rtl8169_private *tp)
3907 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
3908 netdev_reset_queue(tp->dev);
3911 static void rtl8169_cleanup(struct rtl8169_private *tp)
3913 napi_disable(&tp->napi);
3915 /* Give a racing hard_start_xmit a few cycles to complete. */
3918 /* Disable interrupts */
3919 rtl8169_irq_mask_and_ack(tp);
3923 switch (tp->mac_version) {
3924 case RTL_GIGA_MAC_VER_28:
3925 case RTL_GIGA_MAC_VER_31:
3926 rtl_loop_wait_low(tp, &rtl_npq_cond, 20, 2000);
3928 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
3929 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
3930 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
3932 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
3933 rtl_enable_rxdvgate(tp);
3937 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
3944 rtl8169_tx_clear(tp);
3945 rtl8169_init_ring_indexes(tp);
3948 static void rtl_reset_work(struct rtl8169_private *tp)
3952 netif_stop_queue(tp->dev);
3954 rtl8169_cleanup(tp);
3956 for (i = 0; i < NUM_RX_DESC; i++)
3957 rtl8169_mark_to_asic(tp->RxDescArray + i);
3959 napi_enable(&tp->napi);
3963 static void rtl8169_tx_timeout(struct net_device *dev, unsigned int txqueue)
3965 struct rtl8169_private *tp = netdev_priv(dev);
3967 rtl_schedule_task(tp, RTL_FLAG_TASK_TX_TIMEOUT);
3970 static int rtl8169_tx_map(struct rtl8169_private *tp, const u32 *opts, u32 len,
3971 void *addr, unsigned int entry, bool desc_own)
3973 struct TxDesc *txd = tp->TxDescArray + entry;
3974 struct device *d = tp_to_dev(tp);
3979 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
3980 ret = dma_mapping_error(d, mapping);
3981 if (unlikely(ret)) {
3982 if (net_ratelimit())
3983 netdev_err(tp->dev, "Failed to map TX data!\n");
3987 txd->addr = cpu_to_le64(mapping);
3988 txd->opts2 = cpu_to_le32(opts[1]);
3990 opts1 = opts[0] | len;
3991 if (entry == NUM_TX_DESC - 1)
3995 txd->opts1 = cpu_to_le32(opts1);
3997 tp->tx_skb[entry].len = len;
4002 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4003 const u32 *opts, unsigned int entry)
4005 struct skb_shared_info *info = skb_shinfo(skb);
4006 unsigned int cur_frag;
4008 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4009 const skb_frag_t *frag = info->frags + cur_frag;
4010 void *addr = skb_frag_address(frag);
4011 u32 len = skb_frag_size(frag);
4013 entry = (entry + 1) % NUM_TX_DESC;
4015 if (unlikely(rtl8169_tx_map(tp, opts, len, addr, entry, true)))
4022 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
4026 static bool rtl_skb_is_udp(struct sk_buff *skb)
4028 int no = skb_network_offset(skb);
4029 struct ipv6hdr *i6h, _i6h;
4030 struct iphdr *ih, _ih;
4032 switch (vlan_get_protocol(skb)) {
4033 case htons(ETH_P_IP):
4034 ih = skb_header_pointer(skb, no, sizeof(_ih), &_ih);
4035 return ih && ih->protocol == IPPROTO_UDP;
4036 case htons(ETH_P_IPV6):
4037 i6h = skb_header_pointer(skb, no, sizeof(_i6h), &_i6h);
4038 return i6h && i6h->nexthdr == IPPROTO_UDP;
4044 #define RTL_MIN_PATCH_LEN 47
4046 /* see rtl8125_get_patch_pad_len() in r8125 vendor driver */
4047 static unsigned int rtl8125_quirk_udp_padto(struct rtl8169_private *tp,
4048 struct sk_buff *skb)
4050 unsigned int padto = 0, len = skb->len;
4052 if (rtl_is_8125(tp) && len < 128 + RTL_MIN_PATCH_LEN &&
4053 rtl_skb_is_udp(skb) && skb_transport_header_was_set(skb)) {
4054 unsigned int trans_data_len = skb_tail_pointer(skb) -
4055 skb_transport_header(skb);
4057 if (trans_data_len >= offsetof(struct udphdr, len) &&
4058 trans_data_len < RTL_MIN_PATCH_LEN) {
4059 u16 dest = ntohs(udp_hdr(skb)->dest);
4061 /* dest is a standard PTP port */
4062 if (dest == 319 || dest == 320)
4063 padto = len + RTL_MIN_PATCH_LEN - trans_data_len;
4066 if (trans_data_len < sizeof(struct udphdr))
4067 padto = max_t(unsigned int, padto,
4068 len + sizeof(struct udphdr) - trans_data_len);
4074 static unsigned int rtl_quirk_packet_padto(struct rtl8169_private *tp,
4075 struct sk_buff *skb)
4079 padto = rtl8125_quirk_udp_padto(tp, skb);
4081 switch (tp->mac_version) {
4082 case RTL_GIGA_MAC_VER_34:
4083 case RTL_GIGA_MAC_VER_61:
4084 case RTL_GIGA_MAC_VER_63:
4085 padto = max_t(unsigned int, padto, ETH_ZLEN);
4094 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts)
4096 u32 mss = skb_shinfo(skb)->gso_size;
4100 opts[0] |= mss << TD0_MSS_SHIFT;
4101 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4102 const struct iphdr *ip = ip_hdr(skb);
4104 if (ip->protocol == IPPROTO_TCP)
4105 opts[0] |= TD0_IP_CS | TD0_TCP_CS;
4106 else if (ip->protocol == IPPROTO_UDP)
4107 opts[0] |= TD0_IP_CS | TD0_UDP_CS;
4113 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
4114 struct sk_buff *skb, u32 *opts)
4116 struct skb_shared_info *shinfo = skb_shinfo(skb);
4117 u32 mss = shinfo->gso_size;
4120 if (shinfo->gso_type & SKB_GSO_TCPV4) {
4121 opts[0] |= TD1_GTSENV4;
4122 } else if (shinfo->gso_type & SKB_GSO_TCPV6) {
4123 if (skb_cow_head(skb, 0))
4126 tcp_v6_gso_csum_prep(skb);
4127 opts[0] |= TD1_GTSENV6;
4132 opts[0] |= skb_transport_offset(skb) << GTTCPHO_SHIFT;
4133 opts[1] |= mss << TD1_MSS_SHIFT;
4134 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4137 switch (vlan_get_protocol(skb)) {
4138 case htons(ETH_P_IP):
4139 opts[1] |= TD1_IPv4_CS;
4140 ip_protocol = ip_hdr(skb)->protocol;
4143 case htons(ETH_P_IPV6):
4144 opts[1] |= TD1_IPv6_CS;
4145 ip_protocol = ipv6_hdr(skb)->nexthdr;
4149 ip_protocol = IPPROTO_RAW;
4153 if (ip_protocol == IPPROTO_TCP)
4154 opts[1] |= TD1_TCP_CS;
4155 else if (ip_protocol == IPPROTO_UDP)
4156 opts[1] |= TD1_UDP_CS;
4160 opts[1] |= skb_transport_offset(skb) << TCPHO_SHIFT;
4162 unsigned int padto = rtl_quirk_packet_padto(tp, skb);
4164 /* skb_padto would free the skb on error */
4165 return !__skb_put_padto(skb, padto, false);
4171 static unsigned int rtl_tx_slots_avail(struct rtl8169_private *tp)
4173 return READ_ONCE(tp->dirty_tx) + NUM_TX_DESC - READ_ONCE(tp->cur_tx);
4176 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */
4177 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
4179 switch (tp->mac_version) {
4180 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
4181 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
4188 static void rtl8169_doorbell(struct rtl8169_private *tp)
4190 if (rtl_is_8125(tp))
4191 RTL_W16(tp, TxPoll_8125, BIT(0));
4193 RTL_W8(tp, TxPoll, NPQ);
4196 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4197 struct net_device *dev)
4199 unsigned int frags = skb_shinfo(skb)->nr_frags;
4200 struct rtl8169_private *tp = netdev_priv(dev);
4201 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
4202 struct TxDesc *txd_first, *txd_last;
4203 bool stop_queue, door_bell;
4206 if (unlikely(!rtl_tx_slots_avail(tp))) {
4207 if (net_ratelimit())
4208 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
4212 opts[1] = rtl8169_tx_vlan_tag(skb);
4215 if (!rtl_chip_supports_csum_v2(tp))
4216 rtl8169_tso_csum_v1(skb, opts);
4217 else if (!rtl8169_tso_csum_v2(tp, skb, opts))
4220 if (unlikely(rtl8169_tx_map(tp, opts, skb_headlen(skb), skb->data,
4224 txd_first = tp->TxDescArray + entry;
4227 if (rtl8169_xmit_frags(tp, skb, opts, entry))
4229 entry = (entry + frags) % NUM_TX_DESC;
4232 txd_last = tp->TxDescArray + entry;
4233 txd_last->opts1 |= cpu_to_le32(LastFrag);
4234 tp->tx_skb[entry].skb = skb;
4236 skb_tx_timestamp(skb);
4238 /* Force memory writes to complete before releasing descriptor */
4241 door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more());
4243 txd_first->opts1 |= cpu_to_le32(DescOwn | FirstFrag);
4245 /* rtl_tx needs to see descriptor changes before updated tp->cur_tx */
4248 WRITE_ONCE(tp->cur_tx, tp->cur_tx + frags + 1);
4250 stop_queue = !netif_subqueue_maybe_stop(dev, 0, rtl_tx_slots_avail(tp),
4252 R8169_TX_START_THRS);
4253 if (door_bell || stop_queue)
4254 rtl8169_doorbell(tp);
4256 return NETDEV_TX_OK;
4259 rtl8169_unmap_tx_skb(tp, entry);
4261 dev_kfree_skb_any(skb);
4262 dev->stats.tx_dropped++;
4263 return NETDEV_TX_OK;
4266 netif_stop_queue(dev);
4267 dev->stats.tx_dropped++;
4268 return NETDEV_TX_BUSY;
4271 static unsigned int rtl_last_frag_len(struct sk_buff *skb)
4273 struct skb_shared_info *info = skb_shinfo(skb);
4274 unsigned int nr_frags = info->nr_frags;
4279 return skb_frag_size(info->frags + nr_frags - 1);
4282 /* Workaround for hw issues with TSO on RTL8168evl */
4283 static netdev_features_t rtl8168evl_fix_tso(struct sk_buff *skb,
4284 netdev_features_t features)
4286 /* IPv4 header has options field */
4287 if (vlan_get_protocol(skb) == htons(ETH_P_IP) &&
4288 ip_hdrlen(skb) > sizeof(struct iphdr))
4289 features &= ~NETIF_F_ALL_TSO;
4291 /* IPv4 TCP header has options field */
4292 else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4 &&
4293 tcp_hdrlen(skb) > sizeof(struct tcphdr))
4294 features &= ~NETIF_F_ALL_TSO;
4296 else if (rtl_last_frag_len(skb) <= 6)
4297 features &= ~NETIF_F_ALL_TSO;
4302 static netdev_features_t rtl8169_features_check(struct sk_buff *skb,
4303 struct net_device *dev,
4304 netdev_features_t features)
4306 struct rtl8169_private *tp = netdev_priv(dev);
4308 if (skb_is_gso(skb)) {
4309 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4310 features = rtl8168evl_fix_tso(skb, features);
4312 if (skb_transport_offset(skb) > GTTCPHO_MAX &&
4313 rtl_chip_supports_csum_v2(tp))
4314 features &= ~NETIF_F_ALL_TSO;
4315 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4316 /* work around hw bug on some chip versions */
4317 if (skb->len < ETH_ZLEN)
4318 features &= ~NETIF_F_CSUM_MASK;
4320 if (rtl_quirk_packet_padto(tp, skb))
4321 features &= ~NETIF_F_CSUM_MASK;
4323 if (skb_transport_offset(skb) > TCPHO_MAX &&
4324 rtl_chip_supports_csum_v2(tp))
4325 features &= ~NETIF_F_CSUM_MASK;
4328 return vlan_features_check(skb, features);
4331 static void rtl8169_pcierr_interrupt(struct net_device *dev)
4333 struct rtl8169_private *tp = netdev_priv(dev);
4334 struct pci_dev *pdev = tp->pci_dev;
4335 int pci_status_errs;
4338 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4340 pci_status_errs = pci_status_get_and_clear_errors(pdev);
4342 if (net_ratelimit())
4343 netdev_err(dev, "PCI error (cmd = 0x%04x, status_errs = 0x%04x)\n",
4344 pci_cmd, pci_status_errs);
4346 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
4349 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp,
4352 unsigned int dirty_tx, bytes_compl = 0, pkts_compl = 0;
4353 struct sk_buff *skb;
4355 dirty_tx = tp->dirty_tx;
4357 while (READ_ONCE(tp->cur_tx) != dirty_tx) {
4358 unsigned int entry = dirty_tx % NUM_TX_DESC;
4361 status = le32_to_cpu(READ_ONCE(tp->TxDescArray[entry].opts1));
4362 if (status & DescOwn)
4365 skb = tp->tx_skb[entry].skb;
4366 rtl8169_unmap_tx_skb(tp, entry);
4370 bytes_compl += skb->len;
4371 napi_consume_skb(skb, budget);
4376 if (tp->dirty_tx != dirty_tx) {
4377 dev_sw_netstats_tx_add(dev, pkts_compl, bytes_compl);
4378 WRITE_ONCE(tp->dirty_tx, dirty_tx);
4380 netif_subqueue_completed_wake(dev, 0, pkts_compl, bytes_compl,
4381 rtl_tx_slots_avail(tp),
4382 R8169_TX_START_THRS);
4384 * 8168 hack: TxPoll requests are lost when the Tx packets are
4385 * too close. Let's kick an extra TxPoll request when a burst
4386 * of start_xmit activity is detected (if it is not detected,
4387 * it is slow enough). -- FR
4388 * If skb is NULL then we come here again once a tx irq is
4389 * triggered after the last fragment is marked transmitted.
4391 if (READ_ONCE(tp->cur_tx) != dirty_tx && skb)
4392 rtl8169_doorbell(tp);
4396 static inline int rtl8169_fragmented_frame(u32 status)
4398 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4401 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
4403 u32 status = opts1 & (RxProtoMask | RxCSFailMask);
4405 if (status == RxProtoTCP || status == RxProtoUDP)
4406 skb->ip_summed = CHECKSUM_UNNECESSARY;
4408 skb_checksum_none_assert(skb);
4411 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, int budget)
4413 struct device *d = tp_to_dev(tp);
4416 for (count = 0; count < budget; count++, tp->cur_rx++) {
4417 unsigned int pkt_size, entry = tp->cur_rx % NUM_RX_DESC;
4418 struct RxDesc *desc = tp->RxDescArray + entry;
4419 struct sk_buff *skb;
4424 status = le32_to_cpu(READ_ONCE(desc->opts1));
4425 if (status & DescOwn)
4428 /* This barrier is needed to keep us from reading
4429 * any other fields out of the Rx descriptor until
4430 * we know the status of DescOwn
4434 if (unlikely(status & RxRES)) {
4435 if (net_ratelimit())
4436 netdev_warn(dev, "Rx ERROR. status = %08x\n",
4438 dev->stats.rx_errors++;
4439 if (status & (RxRWT | RxRUNT))
4440 dev->stats.rx_length_errors++;
4442 dev->stats.rx_crc_errors++;
4444 if (!(dev->features & NETIF_F_RXALL))
4445 goto release_descriptor;
4446 else if (status & RxRWT || !(status & (RxRUNT | RxCRC)))
4447 goto release_descriptor;
4450 pkt_size = status & GENMASK(13, 0);
4451 if (likely(!(dev->features & NETIF_F_RXFCS)))
4452 pkt_size -= ETH_FCS_LEN;
4454 /* The driver does not support incoming fragmented frames.
4455 * They are seen as a symptom of over-mtu sized frames.
4457 if (unlikely(rtl8169_fragmented_frame(status))) {
4458 dev->stats.rx_dropped++;
4459 dev->stats.rx_length_errors++;
4460 goto release_descriptor;
4463 skb = napi_alloc_skb(&tp->napi, pkt_size);
4464 if (unlikely(!skb)) {
4465 dev->stats.rx_dropped++;
4466 goto release_descriptor;
4469 addr = le64_to_cpu(desc->addr);
4470 rx_buf = page_address(tp->Rx_databuff[entry]);
4472 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
4474 skb_copy_to_linear_data(skb, rx_buf, pkt_size);
4475 skb->tail += pkt_size;
4476 skb->len = pkt_size;
4477 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
4479 rtl8169_rx_csum(skb, status);
4480 skb->protocol = eth_type_trans(skb, dev);
4482 rtl8169_rx_vlan_tag(desc, skb);
4484 if (skb->pkt_type == PACKET_MULTICAST)
4485 dev->stats.multicast++;
4487 napi_gro_receive(&tp->napi, skb);
4489 dev_sw_netstats_rx_add(dev, pkt_size);
4491 rtl8169_mark_to_asic(desc);
4497 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
4499 struct rtl8169_private *tp = dev_instance;
4500 u32 status = rtl_get_events(tp);
4502 if ((status & 0xffff) == 0xffff || !(status & tp->irq_mask))
4505 if (unlikely(status & SYSErr)) {
4506 rtl8169_pcierr_interrupt(tp->dev);
4510 if (status & LinkChg)
4511 phy_mac_interrupt(tp->phydev);
4513 if (unlikely(status & RxFIFOOver &&
4514 tp->mac_version == RTL_GIGA_MAC_VER_11)) {
4515 netif_stop_queue(tp->dev);
4516 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
4519 if (napi_schedule_prep(&tp->napi)) {
4520 rtl_irq_disable(tp);
4521 __napi_schedule(&tp->napi);
4524 rtl_ack_events(tp, status);
4529 static void rtl_task(struct work_struct *work)
4531 struct rtl8169_private *tp =
4532 container_of(work, struct rtl8169_private, wk.work);
4537 if (!test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
4540 if (test_and_clear_bit(RTL_FLAG_TASK_TX_TIMEOUT, tp->wk.flags)) {
4541 /* if chip isn't accessible, reset bus to revive it */
4542 if (RTL_R32(tp, TxConfig) == ~0) {
4543 ret = pci_reset_bus(tp->pci_dev);
4545 netdev_err(tp->dev, "Can't reset secondary PCI bus, detach NIC\n");
4546 netif_device_detach(tp->dev);
4551 /* ASPM compatibility issues are a typical reason for tx timeouts */
4552 ret = pci_disable_link_state(tp->pci_dev, PCIE_LINK_STATE_L1 |
4553 PCIE_LINK_STATE_L0S);
4555 netdev_warn_once(tp->dev, "ASPM disabled on Tx timeout\n");
4559 if (test_and_clear_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags)) {
4562 netif_wake_queue(tp->dev);
4563 } else if (test_and_clear_bit(RTL_FLAG_TASK_RESET_NO_QUEUE_WAKE, tp->wk.flags)) {
4570 static int rtl8169_poll(struct napi_struct *napi, int budget)
4572 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
4573 struct net_device *dev = tp->dev;
4576 rtl_tx(dev, tp, budget);
4578 work_done = rtl_rx(dev, tp, budget);
4580 if (work_done < budget && napi_complete_done(napi, work_done))
4586 static void r8169_phylink_handler(struct net_device *ndev)
4588 struct rtl8169_private *tp = netdev_priv(ndev);
4589 struct device *d = tp_to_dev(tp);
4591 if (netif_carrier_ok(ndev)) {
4592 rtl_link_chg_patch(tp);
4593 pm_request_resume(d);
4594 netif_wake_queue(tp->dev);
4596 /* In few cases rx is broken after link-down otherwise */
4597 if (rtl_is_8125(tp))
4598 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_NO_QUEUE_WAKE);
4602 phy_print_status(tp->phydev);
4605 static int r8169_phy_connect(struct rtl8169_private *tp)
4607 struct phy_device *phydev = tp->phydev;
4608 phy_interface_t phy_mode;
4611 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
4612 PHY_INTERFACE_MODE_MII;
4614 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
4619 if (!tp->supports_gmii)
4620 phy_set_max_speed(phydev, SPEED_100);
4622 phy_attached_info(phydev);
4627 static void rtl8169_down(struct rtl8169_private *tp)
4629 /* Clear all task flags */
4630 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
4632 phy_stop(tp->phydev);
4634 rtl8169_update_counters(tp);
4636 pci_clear_master(tp->pci_dev);
4639 rtl8169_cleanup(tp);
4640 rtl_disable_exit_l1(tp);
4641 rtl_prepare_power_down(tp);
4643 if (tp->dash_type != RTL_DASH_NONE)
4644 rtl8168_driver_stop(tp);
4647 static void rtl8169_up(struct rtl8169_private *tp)
4649 if (tp->dash_type != RTL_DASH_NONE)
4650 rtl8168_driver_start(tp);
4652 pci_set_master(tp->pci_dev);
4653 phy_init_hw(tp->phydev);
4654 phy_resume(tp->phydev);
4655 rtl8169_init_phy(tp);
4656 napi_enable(&tp->napi);
4657 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
4660 phy_start(tp->phydev);
4663 static int rtl8169_close(struct net_device *dev)
4665 struct rtl8169_private *tp = netdev_priv(dev);
4666 struct pci_dev *pdev = tp->pci_dev;
4668 pm_runtime_get_sync(&pdev->dev);
4670 netif_stop_queue(dev);
4672 rtl8169_rx_clear(tp);
4674 cancel_work(&tp->wk.work);
4676 free_irq(tp->irq, tp);
4678 phy_disconnect(tp->phydev);
4680 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4682 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4684 tp->TxDescArray = NULL;
4685 tp->RxDescArray = NULL;
4687 pm_runtime_put_sync(&pdev->dev);
4692 #ifdef CONFIG_NET_POLL_CONTROLLER
4693 static void rtl8169_netpoll(struct net_device *dev)
4695 struct rtl8169_private *tp = netdev_priv(dev);
4697 rtl8169_interrupt(tp->irq, tp);
4701 static int rtl_open(struct net_device *dev)
4703 struct rtl8169_private *tp = netdev_priv(dev);
4704 struct pci_dev *pdev = tp->pci_dev;
4705 unsigned long irqflags;
4706 int retval = -ENOMEM;
4708 pm_runtime_get_sync(&pdev->dev);
4711 * Rx and Tx descriptors needs 256 bytes alignment.
4712 * dma_alloc_coherent provides more.
4714 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
4715 &tp->TxPhyAddr, GFP_KERNEL);
4716 if (!tp->TxDescArray)
4719 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
4720 &tp->RxPhyAddr, GFP_KERNEL);
4721 if (!tp->RxDescArray)
4724 retval = rtl8169_init_ring(tp);
4728 rtl_request_firmware(tp);
4730 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_NO_THREAD : IRQF_SHARED;
4731 retval = request_irq(tp->irq, rtl8169_interrupt, irqflags, dev->name, tp);
4733 goto err_release_fw_2;
4735 retval = r8169_phy_connect(tp);
4740 rtl8169_init_counter_offsets(tp);
4741 netif_start_queue(dev);
4743 pm_runtime_put_sync(&pdev->dev);
4748 free_irq(tp->irq, tp);
4750 rtl_release_firmware(tp);
4751 rtl8169_rx_clear(tp);
4753 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4755 tp->RxDescArray = NULL;
4757 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4759 tp->TxDescArray = NULL;
4764 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
4766 struct rtl8169_private *tp = netdev_priv(dev);
4767 struct pci_dev *pdev = tp->pci_dev;
4768 struct rtl8169_counters *counters = tp->counters;
4770 pm_runtime_get_noresume(&pdev->dev);
4772 netdev_stats_to_stats64(stats, &dev->stats);
4773 dev_fetch_sw_netstats(stats, dev->tstats);
4776 * Fetch additional counter values missing in stats collected by driver
4777 * from tally counters.
4779 if (pm_runtime_active(&pdev->dev))
4780 rtl8169_update_counters(tp);
4783 * Subtract values fetched during initalization.
4784 * See rtl8169_init_counter_offsets for a description why we do that.
4786 stats->tx_errors = le64_to_cpu(counters->tx_errors) -
4787 le64_to_cpu(tp->tc_offset.tx_errors);
4788 stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
4789 le32_to_cpu(tp->tc_offset.tx_multi_collision);
4790 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
4791 le16_to_cpu(tp->tc_offset.tx_aborted);
4792 stats->rx_missed_errors = le16_to_cpu(counters->rx_missed) -
4793 le16_to_cpu(tp->tc_offset.rx_missed);
4795 pm_runtime_put_noidle(&pdev->dev);
4798 static void rtl8169_net_suspend(struct rtl8169_private *tp)
4800 netif_device_detach(tp->dev);
4802 if (netif_running(tp->dev))
4806 static int rtl8169_runtime_resume(struct device *dev)
4808 struct rtl8169_private *tp = dev_get_drvdata(dev);
4810 rtl_rar_set(tp, tp->dev->dev_addr);
4811 __rtl8169_set_wol(tp, tp->saved_wolopts);
4813 if (tp->TxDescArray)
4816 netif_device_attach(tp->dev);
4821 static int rtl8169_suspend(struct device *device)
4823 struct rtl8169_private *tp = dev_get_drvdata(device);
4826 rtl8169_net_suspend(tp);
4827 if (!device_may_wakeup(tp_to_dev(tp)))
4828 clk_disable_unprepare(tp->clk);
4834 static int rtl8169_resume(struct device *device)
4836 struct rtl8169_private *tp = dev_get_drvdata(device);
4838 if (!device_may_wakeup(tp_to_dev(tp)))
4839 clk_prepare_enable(tp->clk);
4841 /* Reportedly at least Asus X453MA truncates packets otherwise */
4842 if (tp->mac_version == RTL_GIGA_MAC_VER_37)
4845 return rtl8169_runtime_resume(device);
4848 static int rtl8169_runtime_suspend(struct device *device)
4850 struct rtl8169_private *tp = dev_get_drvdata(device);
4852 if (!tp->TxDescArray) {
4853 netif_device_detach(tp->dev);
4858 __rtl8169_set_wol(tp, WAKE_PHY);
4859 rtl8169_net_suspend(tp);
4865 static int rtl8169_runtime_idle(struct device *device)
4867 struct rtl8169_private *tp = dev_get_drvdata(device);
4869 if (tp->dash_enabled)
4872 if (!netif_running(tp->dev) || !netif_carrier_ok(tp->dev))
4873 pm_schedule_suspend(device, 10000);
4878 static const struct dev_pm_ops rtl8169_pm_ops = {
4879 SYSTEM_SLEEP_PM_OPS(rtl8169_suspend, rtl8169_resume)
4880 RUNTIME_PM_OPS(rtl8169_runtime_suspend, rtl8169_runtime_resume,
4881 rtl8169_runtime_idle)
4884 static void rtl_shutdown(struct pci_dev *pdev)
4886 struct rtl8169_private *tp = pci_get_drvdata(pdev);
4889 rtl8169_net_suspend(tp);
4892 /* Restore original MAC address */
4893 rtl_rar_set(tp, tp->dev->perm_addr);
4895 if (system_state == SYSTEM_POWER_OFF && !tp->dash_enabled) {
4896 pci_wake_from_d3(pdev, tp->saved_wolopts);
4897 pci_set_power_state(pdev, PCI_D3hot);
4901 static void rtl_remove_one(struct pci_dev *pdev)
4903 struct rtl8169_private *tp = pci_get_drvdata(pdev);
4905 if (pci_dev_run_wake(pdev))
4906 pm_runtime_get_noresume(&pdev->dev);
4908 cancel_work_sync(&tp->wk.work);
4910 unregister_netdev(tp->dev);
4912 if (tp->dash_type != RTL_DASH_NONE)
4913 rtl8168_driver_stop(tp);
4915 rtl_release_firmware(tp);
4917 /* restore original MAC address */
4918 rtl_rar_set(tp, tp->dev->perm_addr);
4921 static const struct net_device_ops rtl_netdev_ops = {
4922 .ndo_open = rtl_open,
4923 .ndo_stop = rtl8169_close,
4924 .ndo_get_stats64 = rtl8169_get_stats64,
4925 .ndo_start_xmit = rtl8169_start_xmit,
4926 .ndo_features_check = rtl8169_features_check,
4927 .ndo_tx_timeout = rtl8169_tx_timeout,
4928 .ndo_validate_addr = eth_validate_addr,
4929 .ndo_change_mtu = rtl8169_change_mtu,
4930 .ndo_fix_features = rtl8169_fix_features,
4931 .ndo_set_features = rtl8169_set_features,
4932 .ndo_set_mac_address = rtl_set_mac_address,
4933 .ndo_eth_ioctl = phy_do_ioctl_running,
4934 .ndo_set_rx_mode = rtl_set_rx_mode,
4935 #ifdef CONFIG_NET_POLL_CONTROLLER
4936 .ndo_poll_controller = rtl8169_netpoll,
4941 static void rtl_set_irq_mask(struct rtl8169_private *tp)
4943 tp->irq_mask = RxOK | RxErr | TxOK | TxErr | LinkChg;
4945 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
4946 tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver;
4947 else if (tp->mac_version == RTL_GIGA_MAC_VER_11)
4948 /* special workaround needed */
4949 tp->irq_mask |= RxFIFOOver;
4951 tp->irq_mask |= RxOverflow;
4954 static int rtl_alloc_irq(struct rtl8169_private *tp)
4958 switch (tp->mac_version) {
4959 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
4960 rtl_unlock_config_regs(tp);
4961 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
4962 rtl_lock_config_regs(tp);
4964 case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_17:
4965 flags = PCI_IRQ_LEGACY;
4968 flags = PCI_IRQ_ALL_TYPES;
4972 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
4975 static void rtl_read_mac_address(struct rtl8169_private *tp,
4976 u8 mac_addr[ETH_ALEN])
4978 /* Get MAC address */
4979 if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) {
4982 value = rtl_eri_read(tp, 0xe0);
4983 put_unaligned_le32(value, mac_addr);
4984 value = rtl_eri_read(tp, 0xe4);
4985 put_unaligned_le16(value, mac_addr + 4);
4986 } else if (rtl_is_8125(tp)) {
4987 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP);
4991 DECLARE_RTL_COND(rtl_link_list_ready_cond)
4993 return RTL_R8(tp, MCU) & LINK_LIST_RDY;
4996 static void r8168g_wait_ll_share_fifo_ready(struct rtl8169_private *tp)
4998 rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42);
5001 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
5003 struct rtl8169_private *tp = mii_bus->priv;
5008 return rtl_readphy(tp, phyreg);
5011 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
5012 int phyreg, u16 val)
5014 struct rtl8169_private *tp = mii_bus->priv;
5019 rtl_writephy(tp, phyreg, val);
5024 static int r8169_mdio_register(struct rtl8169_private *tp)
5026 struct pci_dev *pdev = tp->pci_dev;
5027 struct mii_bus *new_bus;
5030 new_bus = devm_mdiobus_alloc(&pdev->dev);
5034 new_bus->name = "r8169";
5036 new_bus->parent = &pdev->dev;
5037 new_bus->irq[0] = PHY_MAC_INTERRUPT;
5038 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x-%x",
5039 pci_domain_nr(pdev->bus), pci_dev_id(pdev));
5041 new_bus->read = r8169_mdio_read_reg;
5042 new_bus->write = r8169_mdio_write_reg;
5044 ret = devm_mdiobus_register(&pdev->dev, new_bus);
5048 tp->phydev = mdiobus_get_phy(new_bus, 0);
5051 } else if (!tp->phydev->drv) {
5052 /* Most chip versions fail with the genphy driver.
5053 * Therefore ensure that the dedicated PHY driver is loaded.
5055 dev_err(&pdev->dev, "no dedicated PHY driver found for PHY ID 0x%08x, maybe realtek.ko needs to be added to initramfs?\n",
5056 tp->phydev->phy_id);
5060 tp->phydev->mac_managed_pm = true;
5062 phy_support_asym_pause(tp->phydev);
5064 /* PHY will be woken up in rtl_open() */
5065 phy_suspend(tp->phydev);
5070 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
5072 rtl_enable_rxdvgate(tp);
5074 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
5076 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5078 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
5079 r8168g_wait_ll_share_fifo_ready(tp);
5081 r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15));
5082 r8168g_wait_ll_share_fifo_ready(tp);
5085 static void rtl_hw_init_8125(struct rtl8169_private *tp)
5087 rtl_enable_rxdvgate(tp);
5089 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
5091 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5093 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
5094 r8168g_wait_ll_share_fifo_ready(tp);
5096 r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0);
5097 r8168_mac_ocp_write(tp, 0xc0a6, 0x0150);
5098 r8168_mac_ocp_write(tp, 0xc01e, 0x5555);
5099 r8168g_wait_ll_share_fifo_ready(tp);
5102 static void rtl_hw_initialize(struct rtl8169_private *tp)
5104 switch (tp->mac_version) {
5105 case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_53:
5106 rtl8168ep_stop_cmac(tp);
5108 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
5109 rtl_hw_init_8168g(tp);
5111 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63:
5112 rtl_hw_init_8125(tp);
5119 static int rtl_jumbo_max(struct rtl8169_private *tp)
5121 /* Non-GBit versions don't support jumbo frames */
5122 if (!tp->supports_gmii)
5125 switch (tp->mac_version) {
5127 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
5130 case RTL_GIGA_MAC_VER_11:
5131 case RTL_GIGA_MAC_VER_17:
5134 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
5141 static void rtl_init_mac_address(struct rtl8169_private *tp)
5143 u8 mac_addr[ETH_ALEN] __aligned(2) = {};
5144 struct net_device *dev = tp->dev;
5147 rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr);
5151 rtl_read_mac_address(tp, mac_addr);
5152 if (is_valid_ether_addr(mac_addr))
5155 rtl_read_mac_from_reg(tp, mac_addr, MAC0);
5156 if (is_valid_ether_addr(mac_addr))
5159 eth_random_addr(mac_addr);
5160 dev->addr_assign_type = NET_ADDR_RANDOM;
5161 dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n");
5163 eth_hw_addr_set(dev, mac_addr);
5164 rtl_rar_set(tp, mac_addr);
5167 /* register is set if system vendor successfully tested ASPM 1.2 */
5168 static bool rtl_aspm_is_safe(struct rtl8169_private *tp)
5170 if (tp->mac_version >= RTL_GIGA_MAC_VER_61 &&
5171 r8168_mac_ocp_read(tp, 0xc0b2) & 0xf)
5177 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
5179 struct rtl8169_private *tp;
5180 int jumbo_max, region, rc;
5181 enum mac_version chipset;
5182 struct net_device *dev;
5186 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
5190 SET_NETDEV_DEV(dev, &pdev->dev);
5191 dev->netdev_ops = &rtl_netdev_ops;
5192 tp = netdev_priv(dev);
5195 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1;
5197 tp->ocp_base = OCP_STD_PHY_BASE;
5199 raw_spin_lock_init(&tp->cfg9346_usage_lock);
5200 raw_spin_lock_init(&tp->config25_lock);
5201 raw_spin_lock_init(&tp->mac_ocp_lock);
5202 mutex_init(&tp->led_lock);
5204 dev->tstats = devm_netdev_alloc_pcpu_stats(&pdev->dev,
5205 struct pcpu_sw_netstats);
5209 /* Get the *optional* external "ether_clk" used on some boards */
5210 tp->clk = devm_clk_get_optional_enabled(&pdev->dev, "ether_clk");
5211 if (IS_ERR(tp->clk))
5212 return dev_err_probe(&pdev->dev, PTR_ERR(tp->clk), "failed to get ether_clk\n");
5214 /* enable device (incl. PCI PM wakeup and hotplug setup) */
5215 rc = pcim_enable_device(pdev);
5217 return dev_err_probe(&pdev->dev, rc, "enable failure\n");
5219 if (pcim_set_mwi(pdev) < 0)
5220 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
5222 /* use first MMIO region */
5223 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
5225 return dev_err_probe(&pdev->dev, -ENODEV, "no MMIO resource found\n");
5227 rc = pcim_iomap_regions(pdev, BIT(region), KBUILD_MODNAME);
5229 return dev_err_probe(&pdev->dev, rc, "cannot remap MMIO, aborting\n");
5231 tp->mmio_addr = pcim_iomap_table(pdev)[region];
5233 txconfig = RTL_R32(tp, TxConfig);
5234 if (txconfig == ~0U)
5235 return dev_err_probe(&pdev->dev, -EIO, "PCI read failed\n");
5237 xid = (txconfig >> 20) & 0xfcf;
5239 /* Identify chip attached to board */
5240 chipset = rtl8169_get_mac_version(xid, tp->supports_gmii);
5241 if (chipset == RTL_GIGA_MAC_NONE)
5242 return dev_err_probe(&pdev->dev, -ENODEV,
5243 "unknown chip XID %03x, contact r8169 maintainers (see MAINTAINERS file)\n",
5245 tp->mac_version = chipset;
5247 /* Disable ASPM L1 as that cause random device stop working
5248 * problems as well as full system hangs for some PCIe devices users.
5250 if (rtl_aspm_is_safe(tp))
5253 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L1);
5254 tp->aspm_manageable = !rc;
5256 tp->dash_type = rtl_get_dash_type(tp);
5257 tp->dash_enabled = rtl_dash_is_enabled(tp);
5259 tp->cp_cmd = RTL_R16(tp, CPlusCmd) & CPCMD_MASK;
5261 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 &&
5262 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)))
5263 dev->features |= NETIF_F_HIGHDMA;
5267 rtl8169_irq_mask_and_ack(tp);
5269 rtl_hw_initialize(tp);
5273 rc = rtl_alloc_irq(tp);
5275 return dev_err_probe(&pdev->dev, rc, "Can't allocate interrupt\n");
5277 tp->irq = pci_irq_vector(pdev, 0);
5279 INIT_WORK(&tp->wk.work, rtl_task);
5281 rtl_init_mac_address(tp);
5283 dev->ethtool_ops = &rtl8169_ethtool_ops;
5285 netif_napi_add(dev, &tp->napi, rtl8169_poll);
5287 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
5288 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
5289 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO;
5290 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
5293 * Pretend we are using VLANs; This bypasses a nasty bug where
5294 * Interrupts stop flowing on high load on 8110SCd controllers.
5296 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
5297 /* Disallow toggling */
5298 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
5300 if (rtl_chip_supports_csum_v2(tp))
5301 dev->hw_features |= NETIF_F_IPV6_CSUM;
5303 dev->features |= dev->hw_features;
5305 /* There has been a number of reports that using SG/TSO results in
5306 * tx timeouts. However for a lot of people SG/TSO works fine.
5307 * Therefore disable both features by default, but allow users to
5308 * enable them. Use at own risk!
5310 if (rtl_chip_supports_csum_v2(tp)) {
5311 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6;
5312 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V2);
5313 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V2);
5315 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO;
5316 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V1);
5317 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V1);
5320 dev->hw_features |= NETIF_F_RXALL;
5321 dev->hw_features |= NETIF_F_RXFCS;
5323 netdev_sw_irq_coalesce_default_on(dev);
5325 /* configure chip for default features */
5326 rtl8169_set_features(dev, dev->features);
5328 if (!tp->dash_enabled) {
5329 rtl_set_d3_pll_down(tp, true);
5331 rtl_set_d3_pll_down(tp, false);
5332 dev->wol_enabled = 1;
5335 jumbo_max = rtl_jumbo_max(tp);
5337 dev->max_mtu = jumbo_max;
5339 rtl_set_irq_mask(tp);
5341 tp->fw_name = rtl_chip_infos[chipset].fw_name;
5343 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
5344 &tp->counters_phys_addr,
5349 pci_set_drvdata(pdev, tp);
5351 rc = r8169_mdio_register(tp);
5355 rc = register_netdev(dev);
5359 if (IS_ENABLED(CONFIG_R8169_LEDS) &&
5360 tp->mac_version > RTL_GIGA_MAC_VER_06 &&
5361 tp->mac_version < RTL_GIGA_MAC_VER_61)
5362 rtl8168_init_leds(dev);
5364 netdev_info(dev, "%s, %pM, XID %03x, IRQ %d\n",
5365 rtl_chip_infos[chipset].name, dev->dev_addr, xid, tp->irq);
5368 netdev_info(dev, "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
5369 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?
5372 if (tp->dash_type != RTL_DASH_NONE) {
5373 netdev_info(dev, "DASH %s\n",
5374 tp->dash_enabled ? "enabled" : "disabled");
5375 rtl8168_driver_start(tp);
5378 if (pci_dev_run_wake(pdev))
5379 pm_runtime_put_sync(&pdev->dev);
5384 static struct pci_driver rtl8169_pci_driver = {
5385 .name = KBUILD_MODNAME,
5386 .id_table = rtl8169_pci_tbl,
5387 .probe = rtl_init_one,
5388 .remove = rtl_remove_one,
5389 .shutdown = rtl_shutdown,
5390 .driver.pm = pm_ptr(&rtl8169_pm_ops),
5393 module_pci_driver(rtl8169_pci_driver);