drivers/net/ethernet/realtek/r8169_main.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   4  *
   5  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   6  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   7  * Copyright (c) a lot of people too. Please respect their work.
   8  *
   9  * See MAINTAINERS file for support contact information.
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/clk.h>
  17 #include <linux/delay.h>
  18 #include <linux/ethtool.h>
  19 #include <linux/phy.h>
  20 #include <linux/if_vlan.h>
  21 #include <linux/in.h>
  22 #include <linux/io.h>
  23 #include <linux/ip.h>
  24 #include <linux/tcp.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/pm_runtime.h>
  28 #include <linux/bitfield.h>
  29 #include <linux/prefetch.h>
  30 #include <linux/ipv6.h>
  31 #include <asm/unaligned.h>
  32 #include <net/ip6_checksum.h>
  33
  34 #include "r8169.h"
  35 #include "r8169_firmware.h"
  36
  37 #define MODULENAME "r8169"
  38
  39 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  40 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  41 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  42 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  43 #define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
  44 #define FIRMWARE_8168F_1        "rtl_nic/rtl8168f-1.fw"
  45 #define FIRMWARE_8168F_2        "rtl_nic/rtl8168f-2.fw"
  46 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  47 #define FIRMWARE_8402_1         "rtl_nic/rtl8402-1.fw"
  48 #define FIRMWARE_8411_1         "rtl_nic/rtl8411-1.fw"
  49 #define FIRMWARE_8411_2         "rtl_nic/rtl8411-2.fw"
  50 #define FIRMWARE_8106E_1        "rtl_nic/rtl8106e-1.fw"
  51 #define FIRMWARE_8106E_2        "rtl_nic/rtl8106e-2.fw"
  52 #define FIRMWARE_8168G_2        "rtl_nic/rtl8168g-2.fw"
  53 #define FIRMWARE_8168G_3        "rtl_nic/rtl8168g-3.fw"
  54 #define FIRMWARE_8168H_1        "rtl_nic/rtl8168h-1.fw"
  55 #define FIRMWARE_8168H_2        "rtl_nic/rtl8168h-2.fw"
  56 #define FIRMWARE_8168FP_3       "rtl_nic/rtl8168fp-3.fw"
  57 #define FIRMWARE_8107E_1        "rtl_nic/rtl8107e-1.fw"
  58 #define FIRMWARE_8107E_2        "rtl_nic/rtl8107e-2.fw"
  59 #define FIRMWARE_8125A_3        "rtl_nic/rtl8125a-3.fw"
  60 #define FIRMWARE_8125B_2        "rtl_nic/rtl8125b-2.fw"
  61
  62 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  63    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  64 #define MC_FILTER_LIMIT 32
  65
  66 #define TX_DMA_BURST    7       /* Maximum PCI burst, '7' is unlimited */
  67 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  68
  69 #define R8169_REGS_SIZE         256
  70 #define R8169_RX_BUF_SIZE       (SZ_16K - 1)
  71 #define NUM_TX_DESC     256     /* Number of Tx descriptor registers */
  72 #define NUM_RX_DESC     256     /* Number of Rx descriptor registers */
  73 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  74 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  75
  76 #define OCP_STD_PHY_BASE        0xa400
  77
  78 #define RTL_CFG_NO_GBIT 1
  79
  80 /* write/read MMIO register */
  81 #define RTL_W8(tp, reg, val8)   writeb((val8), tp->mmio_addr + (reg))
  82 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
  83 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
  84 #define RTL_R8(tp, reg)         readb(tp->mmio_addr + (reg))
  85 #define RTL_R16(tp, reg)                readw(tp->mmio_addr + (reg))
  86 #define RTL_R32(tp, reg)                readl(tp->mmio_addr + (reg))
  87
  88 #define JUMBO_4K        (4 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
  89 #define JUMBO_6K        (6 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
  90 #define JUMBO_7K        (7 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
  91 #define JUMBO_9K        (9 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
  92
  93 static const struct {
  94         const char *name;
  95         const char *fw_name;
  96 } rtl_chip_infos[] = {
  97         /* PCI devices. */
  98         [RTL_GIGA_MAC_VER_02] = {"RTL8169s"                             },
  99         [RTL_GIGA_MAC_VER_03] = {"RTL8110s"                             },
 100         [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb"                     },
 101         [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc"                     },
 102         [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc"                     },
 103         /* PCI-E devices. */
 104         [RTL_GIGA_MAC_VER_07] = {"RTL8102e"                             },
 105         [RTL_GIGA_MAC_VER_08] = {"RTL8102e"                             },
 106         [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e"                    },
 107         [RTL_GIGA_MAC_VER_10] = {"RTL8101e"                             },
 108         [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b"                       },
 109         [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b"                       },
 110         [RTL_GIGA_MAC_VER_13] = {"RTL8101e/RTL8100e"                    },
 111         [RTL_GIGA_MAC_VER_14] = {"RTL8401"                              },
 112         [RTL_GIGA_MAC_VER_16] = {"RTL8101e"                             },
 113         [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b"                       },
 114         [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp"                     },
 115         [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c"                       },
 116         [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c"                       },
 117         [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c"                       },
 118         [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c"                       },
 119         [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp"                     },
 120         [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp"                     },
 121         [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d",      FIRMWARE_8168D_1},
 122         [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d",      FIRMWARE_8168D_2},
 123         [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp"                     },
 124         [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp"                     },
 125         [RTL_GIGA_MAC_VER_29] = {"RTL8105e",            FIRMWARE_8105E_1},
 126         [RTL_GIGA_MAC_VER_30] = {"RTL8105e",            FIRMWARE_8105E_1},
 127         [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp"                     },
 128         [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e",      FIRMWARE_8168E_1},
 129         [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e",      FIRMWARE_8168E_2},
 130         [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl",  FIRMWARE_8168E_3},
 131         [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f",      FIRMWARE_8168F_1},
 132         [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f",      FIRMWARE_8168F_2},
 133         [RTL_GIGA_MAC_VER_37] = {"RTL8402",             FIRMWARE_8402_1 },
 134         [RTL_GIGA_MAC_VER_38] = {"RTL8411",             FIRMWARE_8411_1 },
 135         [RTL_GIGA_MAC_VER_39] = {"RTL8106e",            FIRMWARE_8106E_1},
 136         [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g",      FIRMWARE_8168G_2},
 137         [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g"                       },
 138         [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu",    FIRMWARE_8168G_3},
 139         [RTL_GIGA_MAC_VER_43] = {"RTL8106eus",          FIRMWARE_8106E_2},
 140         [RTL_GIGA_MAC_VER_44] = {"RTL8411b",            FIRMWARE_8411_2 },
 141         [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h",      FIRMWARE_8168H_1},
 142         [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h",      FIRMWARE_8168H_2},
 143         [RTL_GIGA_MAC_VER_47] = {"RTL8107e",            FIRMWARE_8107E_1},
 144         [RTL_GIGA_MAC_VER_48] = {"RTL8107e",            FIRMWARE_8107E_2},
 145         [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep"                     },
 146         [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep"                     },
 147         [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep"                     },
 148         [RTL_GIGA_MAC_VER_52] = {"RTL8168fp/RTL8117",  FIRMWARE_8168FP_3},
 149         [RTL_GIGA_MAC_VER_60] = {"RTL8125A"                             },
 150         [RTL_GIGA_MAC_VER_61] = {"RTL8125A",            FIRMWARE_8125A_3},
 151         /* reserve 62 for CFG_METHOD_4 in the vendor driver */
 152         [RTL_GIGA_MAC_VER_63] = {"RTL8125B",            FIRMWARE_8125B_2},
 153 };
 154
 155 static const struct pci_device_id rtl8169_pci_tbl[] = {
 156         { PCI_VDEVICE(REALTEK,  0x2502) },
 157         { PCI_VDEVICE(REALTEK,  0x2600) },
 158         { PCI_VDEVICE(REALTEK,  0x8129) },
 159         { PCI_VDEVICE(REALTEK,  0x8136), RTL_CFG_NO_GBIT },
 160         { PCI_VDEVICE(REALTEK,  0x8161) },
 161         { PCI_VDEVICE(REALTEK,  0x8167) },
 162         { PCI_VDEVICE(REALTEK,  0x8168) },
 163         { PCI_VDEVICE(NCUBE,    0x8168) },
 164         { PCI_VDEVICE(REALTEK,  0x8169) },
 165         { PCI_VENDOR_ID_DLINK,  0x4300,
 166                 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 },
 167         { PCI_VDEVICE(DLINK,    0x4300) },
 168         { PCI_VDEVICE(DLINK,    0x4302) },
 169         { PCI_VDEVICE(AT,       0xc107) },
 170         { PCI_VDEVICE(USR,      0x0116) },
 171         { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 },
 172         { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 },
 173         { PCI_VDEVICE(REALTEK,  0x8125) },
 174         { PCI_VDEVICE(REALTEK,  0x3000) },
 175         {}
 176 };
 177
 178 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 179
 180 enum rtl_registers {
 181         MAC0            = 0,    /* Ethernet hardware address. */
 182         MAC4            = 4,
 183         MAR0            = 8,    /* Multicast filter. */
 184         CounterAddrLow          = 0x10,
 185         CounterAddrHigh         = 0x14,
 186         TxDescStartAddrLow      = 0x20,
 187         TxDescStartAddrHigh     = 0x24,
 188         TxHDescStartAddrLow     = 0x28,
 189         TxHDescStartAddrHigh    = 0x2c,
 190         FLASH           = 0x30,
 191         ERSR            = 0x36,
 192         ChipCmd         = 0x37,
 193         TxPoll          = 0x38,
 194         IntrMask        = 0x3c,
 195         IntrStatus      = 0x3e,
 196
 197         TxConfig        = 0x40,
 198 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 199 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 200
 201         RxConfig        = 0x44,
 202 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 203 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 204 #define RXCFG_FIFO_SHIFT                13
 205                                         /* No threshold before first PCI xfer */
 206 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 207 #define RX_EARLY_OFF                    (1 << 11)
 208 #define RXCFG_DMA_SHIFT                 8
 209                                         /* Unlimited maximum PCI burst. */
 210 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 211
 212         Cfg9346         = 0x50,
 213         Config0         = 0x51,
 214         Config1         = 0x52,
 215         Config2         = 0x53,
 216 #define PME_SIGNAL                      (1 << 5)        /* 8168c and later */
 217
 218         Config3         = 0x54,
 219         Config4         = 0x55,
 220         Config5         = 0x56,
 221         PHYAR           = 0x60,
 222         PHYstatus       = 0x6c,
 223         RxMaxSize       = 0xda,
 224         CPlusCmd        = 0xe0,
 225         IntrMitigate    = 0xe2,
 226
 227 #define RTL_COALESCE_TX_USECS   GENMASK(15, 12)
 228 #define RTL_COALESCE_TX_FRAMES  GENMASK(11, 8)
 229 #define RTL_COALESCE_RX_USECS   GENMASK(7, 4)
 230 #define RTL_COALESCE_RX_FRAMES  GENMASK(3, 0)
 231
 232 #define RTL_COALESCE_T_MAX      0x0fU
 233 #define RTL_COALESCE_FRAME_MAX  (RTL_COALESCE_T_MAX * 4)
 234
 235         RxDescAddrLow   = 0xe4,
 236         RxDescAddrHigh  = 0xe8,
 237         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 238
 239 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 240
 241         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 242
 243 #define TxPacketMax     (8064 >> 7)
 244 #define EarlySize       0x27
 245
 246         FuncEvent       = 0xf0,
 247         FuncEventMask   = 0xf4,
 248         FuncPresetState = 0xf8,
 249         IBCR0           = 0xf8,
 250         IBCR2           = 0xf9,
 251         IBIMR0          = 0xfa,
 252         IBISR0          = 0xfb,
 253         FuncForceEvent  = 0xfc,
 254 };
 255
 256 enum rtl8168_8101_registers {
 257         CSIDR                   = 0x64,
 258         CSIAR                   = 0x68,
 259 #define CSIAR_FLAG                      0x80000000
 260 #define CSIAR_WRITE_CMD                 0x80000000
 261 #define CSIAR_BYTE_ENABLE               0x0000f000
 262 #define CSIAR_ADDR_MASK                 0x00000fff
 263         PMCH                    = 0x6f,
 264 #define D3COLD_NO_PLL_DOWN              BIT(7)
 265 #define D3HOT_NO_PLL_DOWN               BIT(6)
 266 #define D3_NO_PLL_DOWN                  (BIT(7) | BIT(6))
 267         EPHYAR                  = 0x80,
 268 #define EPHYAR_FLAG                     0x80000000
 269 #define EPHYAR_WRITE_CMD                0x80000000
 270 #define EPHYAR_REG_MASK                 0x1f
 271 #define EPHYAR_REG_SHIFT                16
 272 #define EPHYAR_DATA_MASK                0xffff
 273         DLLPR                   = 0xd0,
 274 #define PFM_EN                          (1 << 6)
 275 #define TX_10M_PS_EN                    (1 << 7)
 276         DBG_REG                 = 0xd1,
 277 #define FIX_NAK_1                       (1 << 4)
 278 #define FIX_NAK_2                       (1 << 3)
 279         TWSI                    = 0xd2,
 280         MCU                     = 0xd3,
 281 #define NOW_IS_OOB                      (1 << 7)
 282 #define TX_EMPTY                        (1 << 5)
 283 #define RX_EMPTY                        (1 << 4)
 284 #define RXTX_EMPTY                      (TX_EMPTY | RX_EMPTY)
 285 #define EN_NDP                          (1 << 3)
 286 #define EN_OOB_RESET                    (1 << 2)
 287 #define LINK_LIST_RDY                   (1 << 1)
 288         EFUSEAR                 = 0xdc,
 289 #define EFUSEAR_FLAG                    0x80000000
 290 #define EFUSEAR_WRITE_CMD               0x80000000
 291 #define EFUSEAR_READ_CMD                0x00000000
 292 #define EFUSEAR_REG_MASK                0x03ff
 293 #define EFUSEAR_REG_SHIFT               8
 294 #define EFUSEAR_DATA_MASK               0xff
 295         MISC_1                  = 0xf2,
 296 #define PFM_D3COLD_EN                   (1 << 6)
 297 };
 298
 299 enum rtl8168_registers {
 300         LED_FREQ                = 0x1a,
 301         EEE_LED                 = 0x1b,
 302         ERIDR                   = 0x70,
 303         ERIAR                   = 0x74,
 304 #define ERIAR_FLAG                      0x80000000
 305 #define ERIAR_WRITE_CMD                 0x80000000
 306 #define ERIAR_READ_CMD                  0x00000000
 307 #define ERIAR_ADDR_BYTE_ALIGN           4
 308 #define ERIAR_TYPE_SHIFT                16
 309 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 310 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 311 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 312 #define ERIAR_OOB                       (0x02 << ERIAR_TYPE_SHIFT)
 313 #define ERIAR_MASK_SHIFT                12
 314 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 315 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 316 #define ERIAR_MASK_0100                 (0x4 << ERIAR_MASK_SHIFT)
 317 #define ERIAR_MASK_0101                 (0x5 << ERIAR_MASK_SHIFT)
 318 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 319         EPHY_RXER_NUM           = 0x7c,
 320         OCPDR                   = 0xb0, /* OCP GPHY access */
 321 #define OCPDR_WRITE_CMD                 0x80000000
 322 #define OCPDR_READ_CMD                  0x00000000
 323 #define OCPDR_REG_MASK                  0x7f
 324 #define OCPDR_GPHY_REG_SHIFT            16
 325 #define OCPDR_DATA_MASK                 0xffff
 326         OCPAR                   = 0xb4,
 327 #define OCPAR_FLAG                      0x80000000
 328 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 329 #define OCPAR_GPHY_READ_CMD             0x0000f060
 330         GPHY_OCP                = 0xb8,
 331         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 332         MISC                    = 0xf0, /* 8168e only. */
 333 #define TXPLA_RST                       (1 << 29)
 334 #define DISABLE_LAN_EN                  (1 << 23) /* Enable GPIO pin */
 335 #define PWM_EN                          (1 << 22)
 336 #define RXDV_GATED_EN                   (1 << 19)
 337 #define EARLY_TALLY_EN                  (1 << 16)
 338 };
 339
 340 enum rtl8125_registers {
 341         IntrMask_8125           = 0x38,
 342         IntrStatus_8125         = 0x3c,
 343         TxPoll_8125             = 0x90,
 344         MAC0_BKP                = 0x19e0,
 345         EEE_TXIDLE_TIMER_8125   = 0x6048,
 346 };
 347
 348 #define RX_VLAN_INNER_8125      BIT(22)
 349 #define RX_VLAN_OUTER_8125      BIT(23)
 350 #define RX_VLAN_8125            (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125)
 351
 352 #define RX_FETCH_DFLT_8125      (8 << 27)
 353
 354 enum rtl_register_content {
 355         /* InterruptStatusBits */
 356         SYSErr          = 0x8000,
 357         PCSTimeout      = 0x4000,
 358         SWInt           = 0x0100,
 359         TxDescUnavail   = 0x0080,
 360         RxFIFOOver      = 0x0040,
 361         LinkChg         = 0x0020,
 362         RxOverflow      = 0x0010,
 363         TxErr           = 0x0008,
 364         TxOK            = 0x0004,
 365         RxErr           = 0x0002,
 366         RxOK            = 0x0001,
 367
 368         /* RxStatusDesc */
 369         RxRWT   = (1 << 22),
 370         RxRES   = (1 << 21),
 371         RxRUNT  = (1 << 20),
 372         RxCRC   = (1 << 19),
 373
 374         /* ChipCmdBits */
 375         StopReq         = 0x80,
 376         CmdReset        = 0x10,
 377         CmdRxEnb        = 0x08,
 378         CmdTxEnb        = 0x04,
 379         RxBufEmpty      = 0x01,
 380
 381         /* TXPoll register p.5 */
 382         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 383         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 384         FSWInt          = 0x01,         /* Forced software interrupt */
 385
 386         /* Cfg9346Bits */
 387         Cfg9346_Lock    = 0x00,
 388         Cfg9346_Unlock  = 0xc0,
 389
 390         /* rx_mode_bits */
 391         AcceptErr       = 0x20,
 392         AcceptRunt      = 0x10,
 393 #define RX_CONFIG_ACCEPT_ERR_MASK       0x30
 394         AcceptBroadcast = 0x08,
 395         AcceptMulticast = 0x04,
 396         AcceptMyPhys    = 0x02,
 397         AcceptAllPhys   = 0x01,
 398 #define RX_CONFIG_ACCEPT_OK_MASK        0x0f
 399 #define RX_CONFIG_ACCEPT_MASK           0x3f
 400
 401         /* TxConfigBits */
 402         TxInterFrameGapShift = 24,
 403         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 404
 405         /* Config1 register p.24 */
 406         LEDS1           = (1 << 7),
 407         LEDS0           = (1 << 6),
 408         Speed_down      = (1 << 4),
 409         MEMMAP          = (1 << 3),
 410         IOMAP           = (1 << 2),
 411         VPD             = (1 << 1),
 412         PMEnable        = (1 << 0),     /* Power Management Enable */
 413
 414         /* Config2 register p. 25 */
 415         ClkReqEn        = (1 << 7),     /* Clock Request Enable */
 416         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
 417         PCI_Clock_66MHz = 0x01,
 418         PCI_Clock_33MHz = 0x00,
 419
 420         /* Config3 register p.25 */
 421         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 422         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 423         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
 424         Rdy_to_L23      = (1 << 1),     /* L23 Enable */
 425         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 426
 427         /* Config4 register */
 428         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
 429
 430         /* Config5 register p.27 */
 431         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 432         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 433         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 434         Spi_en          = (1 << 3),
 435         LanWake         = (1 << 1),     /* LanWake enable/disable */
 436         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 437         ASPM_en         = (1 << 0),     /* ASPM enable */
 438
 439         /* CPlusCmd p.31 */
 440         EnableBist      = (1 << 15),    // 8168 8101
 441         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 442         EnAnaPLL        = (1 << 14),    // 8169
 443         Normal_mode     = (1 << 13),    // unused
 444         Force_half_dup  = (1 << 12),    // 8168 8101
 445         Force_rxflow_en = (1 << 11),    // 8168 8101
 446         Force_txflow_en = (1 << 10),    // 8168 8101
 447         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 448         ASF             = (1 << 8),     // 8168 8101
 449         PktCntrDisable  = (1 << 7),     // 8168 8101
 450         Mac_dbgo_sel    = 0x001c,       // 8168
 451         RxVlan          = (1 << 6),
 452         RxChkSum        = (1 << 5),
 453         PCIDAC          = (1 << 4),
 454         PCIMulRW        = (1 << 3),
 455 #define INTT_MASK       GENMASK(1, 0)
 456 #define CPCMD_MASK      (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
 457
 458         /* rtl8169_PHYstatus */
 459         TBI_Enable      = 0x80,
 460         TxFlowCtrl      = 0x40,
 461         RxFlowCtrl      = 0x20,
 462         _1000bpsF       = 0x10,
 463         _100bps         = 0x08,
 464         _10bps          = 0x04,
 465         LinkStatus      = 0x02,
 466         FullDup         = 0x01,
 467
 468         /* ResetCounterCommand */
 469         CounterReset    = 0x1,
 470
 471         /* DumpCounterCommand */
 472         CounterDump     = 0x8,
 473
 474         /* magic enable v2 */
 475         MagicPacket_v2  = (1 << 16),    /* Wake up when receives a Magic Packet */
 476 };
 477
 478 enum rtl_desc_bit {
 479         /* First doubleword. */
 480         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 481         RingEnd         = (1 << 30), /* End of descriptor ring */
 482         FirstFrag       = (1 << 29), /* First segment of a packet */
 483         LastFrag        = (1 << 28), /* Final segment of a packet */
 484 };
 485
 486 /* Generic case. */
 487 enum rtl_tx_desc_bit {
 488         /* First doubleword. */
 489         TD_LSO          = (1 << 27),            /* Large Send Offload */
 490 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 491
 492         /* Second doubleword. */
 493         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 494 };
 495
 496 /* 8169, 8168b and 810x except 8102e. */
 497 enum rtl_tx_desc_bit_0 {
 498         /* First doubleword. */
 499 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 500         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 501         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 502         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 503 };
 504
 505 /* 8102e, 8168c and beyond. */
 506 enum rtl_tx_desc_bit_1 {
 507         /* First doubleword. */
 508         TD1_GTSENV4     = (1 << 26),            /* Giant Send for IPv4 */
 509         TD1_GTSENV6     = (1 << 25),            /* Giant Send for IPv6 */
 510 #define GTTCPHO_SHIFT                   18
 511 #define GTTCPHO_MAX                     0x7f
 512
 513         /* Second doubleword. */
 514 #define TCPHO_SHIFT                     18
 515 #define TCPHO_MAX                       0x3ff
 516 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 517         TD1_IPv6_CS     = (1 << 28),            /* Calculate IPv6 checksum */
 518         TD1_IPv4_CS     = (1 << 29),            /* Calculate IPv4 checksum */
 519         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 520         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 521 };
 522
 523 enum rtl_rx_desc_bit {
 524         /* Rx private */
 525         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 526         PID0            = (1 << 17), /* Protocol ID bit 0/2 */
 527
 528 #define RxProtoUDP      (PID1)
 529 #define RxProtoTCP      (PID0)
 530 #define RxProtoIP       (PID1 | PID0)
 531 #define RxProtoMask     RxProtoIP
 532
 533         IPFail          = (1 << 16), /* IP checksum failed */
 534         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 535         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 536
 537 #define RxCSFailMask    (IPFail | UDPFail | TCPFail)
 538
 539         RxVlanTag       = (1 << 16), /* VLAN tag available */
 540 };
 541
 542 #define RTL_GSO_MAX_SIZE_V1     32000
 543 #define RTL_GSO_MAX_SEGS_V1     24
 544 #define RTL_GSO_MAX_SIZE_V2     64000
 545 #define RTL_GSO_MAX_SEGS_V2     64
 546
 547 struct TxDesc {
 548         __le32 opts1;
 549         __le32 opts2;
 550         __le64 addr;
 551 };
 552
 553 struct RxDesc {
 554         __le32 opts1;
 555         __le32 opts2;
 556         __le64 addr;
 557 };
 558
 559 struct ring_info {
 560         struct sk_buff  *skb;
 561         u32             len;
 562 };
 563
 564 struct rtl8169_counters {
 565         __le64  tx_packets;
 566         __le64  rx_packets;
 567         __le64  tx_errors;
 568         __le32  rx_errors;
 569         __le16  rx_missed;
 570         __le16  align_errors;
 571         __le32  tx_one_collision;
 572         __le32  tx_multi_collision;
 573         __le64  rx_unicast;
 574         __le64  rx_broadcast;
 575         __le32  rx_multicast;
 576         __le16  tx_aborted;
 577         __le16  tx_underun;
 578 };
 579
 580 struct rtl8169_tc_offsets {
 581         bool    inited;
 582         __le64  tx_errors;
 583         __le32  tx_multi_collision;
 584         __le16  tx_aborted;
 585         __le16  rx_missed;
 586 };
 587
 588 enum rtl_flag {
 589         RTL_FLAG_TASK_ENABLED = 0,
 590         RTL_FLAG_TASK_RESET_PENDING,
 591         RTL_FLAG_MAX
 592 };
 593
 594 enum rtl_dash_type {
 595         RTL_DASH_NONE,
 596         RTL_DASH_DP,
 597         RTL_DASH_EP,
 598 };
 599
 600 struct rtl8169_private {
 601         void __iomem *mmio_addr;        /* memory map physical address */
 602         struct pci_dev *pci_dev;
 603         struct net_device *dev;
 604         struct phy_device *phydev;
 605         struct napi_struct napi;
 606         enum mac_version mac_version;
 607         enum rtl_dash_type dash_type;
 608         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 609         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 610         u32 dirty_tx;
 611         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 612         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 613         dma_addr_t TxPhyAddr;
 614         dma_addr_t RxPhyAddr;
 615         struct page *Rx_databuff[NUM_RX_DESC];  /* Rx data buffers */
 616         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 617         u16 cp_cmd;
 618         u32 irq_mask;
 619         struct clk *clk;
 620
 621         struct {
 622                 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
 623                 struct work_struct work;
 624         } wk;
 625
 626         unsigned supports_gmii:1;
 627         unsigned aspm_manageable:1;
 628         dma_addr_t counters_phys_addr;
 629         struct rtl8169_counters *counters;
 630         struct rtl8169_tc_offsets tc_offset;
 631         u32 saved_wolopts;
 632         int eee_adv;
 633
 634         const char *fw_name;
 635         struct rtl_fw *rtl_fw;
 636
 637         u32 ocp_base;
 638 };
 639
 640 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp);
 641
 642 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 643 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 644 MODULE_SOFTDEP("pre: realtek");
 645 MODULE_LICENSE("GPL");
 646 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 647 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 648 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 649 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 650 MODULE_FIRMWARE(FIRMWARE_8168E_3);
 651 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 652 MODULE_FIRMWARE(FIRMWARE_8168F_1);
 653 MODULE_FIRMWARE(FIRMWARE_8168F_2);
 654 MODULE_FIRMWARE(FIRMWARE_8402_1);
 655 MODULE_FIRMWARE(FIRMWARE_8411_1);
 656 MODULE_FIRMWARE(FIRMWARE_8411_2);
 657 MODULE_FIRMWARE(FIRMWARE_8106E_1);
 658 MODULE_FIRMWARE(FIRMWARE_8106E_2);
 659 MODULE_FIRMWARE(FIRMWARE_8168G_2);
 660 MODULE_FIRMWARE(FIRMWARE_8168G_3);
 661 MODULE_FIRMWARE(FIRMWARE_8168H_1);
 662 MODULE_FIRMWARE(FIRMWARE_8168H_2);
 663 MODULE_FIRMWARE(FIRMWARE_8168FP_3);
 664 MODULE_FIRMWARE(FIRMWARE_8107E_1);
 665 MODULE_FIRMWARE(FIRMWARE_8107E_2);
 666 MODULE_FIRMWARE(FIRMWARE_8125A_3);
 667 MODULE_FIRMWARE(FIRMWARE_8125B_2);
 668
 669 static inline struct device *tp_to_dev(struct rtl8169_private *tp)
 670 {
 671         return &tp->pci_dev->dev;
 672 }
 673
 674 static void rtl_lock_config_regs(struct rtl8169_private *tp)
 675 {
 676         RTL_W8(tp, Cfg9346, Cfg9346_Lock);
 677 }
 678
 679 static void rtl_unlock_config_regs(struct rtl8169_private *tp)
 680 {
 681         RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
 682 }
 683
 684 static void rtl_pci_commit(struct rtl8169_private *tp)
 685 {
 686         /* Read an arbitrary register to commit a preceding PCI write */
 687         RTL_R8(tp, ChipCmd);
 688 }
 689
 690 static bool rtl_is_8125(struct rtl8169_private *tp)
 691 {
 692         return tp->mac_version >= RTL_GIGA_MAC_VER_60;
 693 }
 694
 695 static bool rtl_is_8168evl_up(struct rtl8169_private *tp)
 696 {
 697         return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
 698                tp->mac_version != RTL_GIGA_MAC_VER_39 &&
 699                tp->mac_version <= RTL_GIGA_MAC_VER_52;
 700 }
 701
 702 static bool rtl_supports_eee(struct rtl8169_private *tp)
 703 {
 704         return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
 705                tp->mac_version != RTL_GIGA_MAC_VER_37 &&
 706                tp->mac_version != RTL_GIGA_MAC_VER_39;
 707 }
 708
 709 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg)
 710 {
 711         int i;
 712
 713         for (i = 0; i < ETH_ALEN; i++)
 714                 mac[i] = RTL_R8(tp, reg + i);
 715 }
 716
 717 struct rtl_cond {
 718         bool (*check)(struct rtl8169_private *);
 719         const char *msg;
 720 };
 721
 722 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
 723                           unsigned long usecs, int n, bool high)
 724 {
 725         int i;
 726
 727         for (i = 0; i < n; i++) {
 728                 if (c->check(tp) == high)
 729                         return true;
 730                 fsleep(usecs);
 731         }
 732
 733         if (net_ratelimit())
 734                 netdev_err(tp->dev, "%s == %d (loop: %d, delay: %lu).\n",
 735                            c->msg, !high, n, usecs);
 736         return false;
 737 }
 738
 739 static bool rtl_loop_wait_high(struct rtl8169_private *tp,
 740                                const struct rtl_cond *c,
 741                                unsigned long d, int n)
 742 {
 743         return rtl_loop_wait(tp, c, d, n, true);
 744 }
 745
 746 static bool rtl_loop_wait_low(struct rtl8169_private *tp,
 747                               const struct rtl_cond *c,
 748                               unsigned long d, int n)
 749 {
 750         return rtl_loop_wait(tp, c, d, n, false);
 751 }
 752
 753 #define DECLARE_RTL_COND(name)                          \
 754 static bool name ## _check(struct rtl8169_private *);   \
 755                                                         \
 756 static const struct rtl_cond name = {                   \
 757         .check  = name ## _check,                       \
 758         .msg    = #name                                 \
 759 };                                                      \
 760                                                         \
 761 static bool name ## _check(struct rtl8169_private *tp)
 762
 763 static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type)
 764 {
 765         /* based on RTL8168FP_OOBMAC_BASE in vendor driver */
 766         if (tp->mac_version == RTL_GIGA_MAC_VER_52 && type == ERIAR_OOB)
 767                 *cmd |= 0x7f0 << 18;
 768 }
 769
 770 DECLARE_RTL_COND(rtl_eriar_cond)
 771 {
 772         return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
 773 }
 774
 775 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
 776                            u32 val, int type)
 777 {
 778         u32 cmd = ERIAR_WRITE_CMD | type | mask | addr;
 779
 780         if (WARN(addr & 3 || !mask, "addr: 0x%x, mask: 0x%08x\n", addr, mask))
 781                 return;
 782
 783         RTL_W32(tp, ERIDR, val);
 784         r8168fp_adjust_ocp_cmd(tp, &cmd, type);
 785         RTL_W32(tp, ERIAR, cmd);
 786
 787         rtl_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
 788 }
 789
 790 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
 791                           u32 val)
 792 {
 793         _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC);
 794 }
 795
 796 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
 797 {
 798         u32 cmd = ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr;
 799
 800         r8168fp_adjust_ocp_cmd(tp, &cmd, type);
 801         RTL_W32(tp, ERIAR, cmd);
 802
 803         return rtl_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
 804                 RTL_R32(tp, ERIDR) : ~0;
 805 }
 806
 807 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr)
 808 {
 809         return _rtl_eri_read(tp, addr, ERIAR_EXGMAC);
 810 }
 811
 812 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 p, u32 m)
 813 {
 814         u32 val = rtl_eri_read(tp, addr);
 815
 816         rtl_eri_write(tp, addr, ERIAR_MASK_1111, (val & ~m) | p);
 817 }
 818
 819 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 p)
 820 {
 821         rtl_w0w1_eri(tp, addr, p, 0);
 822 }
 823
 824 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 m)
 825 {
 826         rtl_w0w1_eri(tp, addr, 0, m);
 827 }
 828
 829 static bool rtl_ocp_reg_failure(u32 reg)
 830 {
 831         return WARN_ONCE(reg & 0xffff0001, "Invalid ocp reg %x!\n", reg);
 832 }
 833
 834 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
 835 {
 836         return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
 837 }
 838
 839 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 840 {
 841         if (rtl_ocp_reg_failure(reg))
 842                 return;
 843
 844         RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
 845
 846         rtl_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
 847 }
 848
 849 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
 850 {
 851         if (rtl_ocp_reg_failure(reg))
 852                 return 0;
 853
 854         RTL_W32(tp, GPHY_OCP, reg << 15);
 855
 856         return rtl_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
 857                 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT;
 858 }
 859
 860 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 861 {
 862         if (rtl_ocp_reg_failure(reg))
 863                 return;
 864
 865         RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
 866 }
 867
 868 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
 869 {
 870         if (rtl_ocp_reg_failure(reg))
 871                 return 0;
 872
 873         RTL_W32(tp, OCPDR, reg << 15);
 874
 875         return RTL_R32(tp, OCPDR);
 876 }
 877
 878 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask,
 879                                  u16 set)
 880 {
 881         u16 data = r8168_mac_ocp_read(tp, reg);
 882
 883         r8168_mac_ocp_write(tp, reg, (data & ~mask) | set);
 884 }
 885
 886 /* Work around a hw issue with RTL8168g PHY, the quirk disables
 887  * PHY MCU interrupts before PHY power-down.
 888  */
 889 static void rtl8168g_phy_suspend_quirk(struct rtl8169_private *tp, int value)
 890 {
 891         switch (tp->mac_version) {
 892         case RTL_GIGA_MAC_VER_40:
 893         case RTL_GIGA_MAC_VER_41:
 894         case RTL_GIGA_MAC_VER_49:
 895                 if (value & BMCR_RESET || !(value & BMCR_PDOWN))
 896                         rtl_eri_set_bits(tp, 0x1a8, 0xfc000000);
 897                 else
 898                         rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000);
 899                 break;
 900         default:
 901                 break;
 902         }
 903 };
 904
 905 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
 906 {
 907         if (reg == 0x1f) {
 908                 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
 909                 return;
 910         }
 911
 912         if (tp->ocp_base != OCP_STD_PHY_BASE)
 913                 reg -= 0x10;
 914
 915         if (tp->ocp_base == OCP_STD_PHY_BASE && reg == MII_BMCR)
 916                 rtl8168g_phy_suspend_quirk(tp, value);
 917
 918         r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
 919 }
 920
 921 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
 922 {
 923         if (reg == 0x1f)
 924                 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4;
 925
 926         if (tp->ocp_base != OCP_STD_PHY_BASE)
 927                 reg -= 0x10;
 928
 929         return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
 930 }
 931
 932 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
 933 {
 934         if (reg == 0x1f) {
 935                 tp->ocp_base = value << 4;
 936                 return;
 937         }
 938
 939         r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
 940 }
 941
 942 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
 943 {
 944         return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
 945 }
 946
 947 DECLARE_RTL_COND(rtl_phyar_cond)
 948 {
 949         return RTL_R32(tp, PHYAR) & 0x80000000;
 950 }
 951
 952 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
 953 {
 954         RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
 955
 956         rtl_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
 957         /*
 958          * According to hardware specs a 20us delay is required after write
 959          * complete indication, but before sending next command.
 960          */
 961         udelay(20);
 962 }
 963
 964 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
 965 {
 966         int value;
 967
 968         RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
 969
 970         value = rtl_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
 971                 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT;
 972
 973         /*
 974          * According to hardware specs a 20us delay is required after read
 975          * complete indication, but before sending next command.
 976          */
 977         udelay(20);
 978
 979         return value;
 980 }
 981
 982 DECLARE_RTL_COND(rtl_ocpar_cond)
 983 {
 984         return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
 985 }
 986
 987 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
 988 {
 989         RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
 990         RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
 991         RTL_W32(tp, EPHY_RXER_NUM, 0);
 992
 993         rtl_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
 994 }
 995
 996 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
 997 {
 998         r8168dp_1_mdio_access(tp, reg,
 999                               OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
1000 }
1001
1002 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
1003 {
1004         r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
1005
1006         mdelay(1);
1007         RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
1008         RTL_W32(tp, EPHY_RXER_NUM, 0);
1009
1010         return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1011                 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : -ETIMEDOUT;
1012 }
1013
1014 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
1015
1016 static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
1017 {
1018         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1019 }
1020
1021 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
1022 {
1023         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1024 }
1025
1026 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
1027 {
1028         r8168dp_2_mdio_start(tp);
1029
1030         r8169_mdio_write(tp, reg, value);
1031
1032         r8168dp_2_mdio_stop(tp);
1033 }
1034
1035 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1036 {
1037         int value;
1038
1039         /* Work around issue with chip reporting wrong PHY ID */
1040         if (reg == MII_PHYSID2)
1041                 return 0xc912;
1042
1043         r8168dp_2_mdio_start(tp);
1044
1045         value = r8169_mdio_read(tp, reg);
1046
1047         r8168dp_2_mdio_stop(tp);
1048
1049         return value;
1050 }
1051
1052 static void rtl_writephy(struct rtl8169_private *tp, int location, int val)
1053 {
1054         switch (tp->mac_version) {
1055         case RTL_GIGA_MAC_VER_27:
1056                 r8168dp_1_mdio_write(tp, location, val);
1057                 break;
1058         case RTL_GIGA_MAC_VER_28:
1059         case RTL_GIGA_MAC_VER_31:
1060                 r8168dp_2_mdio_write(tp, location, val);
1061                 break;
1062         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
1063                 r8168g_mdio_write(tp, location, val);
1064                 break;
1065         default:
1066                 r8169_mdio_write(tp, location, val);
1067                 break;
1068         }
1069 }
1070
1071 static int rtl_readphy(struct rtl8169_private *tp, int location)
1072 {
1073         switch (tp->mac_version) {
1074         case RTL_GIGA_MAC_VER_27:
1075                 return r8168dp_1_mdio_read(tp, location);
1076         case RTL_GIGA_MAC_VER_28:
1077         case RTL_GIGA_MAC_VER_31:
1078                 return r8168dp_2_mdio_read(tp, location);
1079         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
1080                 return r8168g_mdio_read(tp, location);
1081         default:
1082                 return r8169_mdio_read(tp, location);
1083         }
1084 }
1085
1086 DECLARE_RTL_COND(rtl_ephyar_cond)
1087 {
1088         return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1089 }
1090
1091 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1092 {
1093         RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1094                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1095
1096         rtl_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1097
1098         udelay(10);
1099 }
1100
1101 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1102 {
1103         RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1104
1105         return rtl_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1106                 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1107 }
1108
1109 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u16 reg)
1110 {
1111         RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff));
1112         return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1113                 RTL_R32(tp, OCPDR) : ~0;
1114 }
1115
1116 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u16 reg)
1117 {
1118         return _rtl_eri_read(tp, reg, ERIAR_OOB);
1119 }
1120
1121 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1122                               u32 data)
1123 {
1124         RTL_W32(tp, OCPDR, data);
1125         RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1126         rtl_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1127 }
1128
1129 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1130                               u32 data)
1131 {
1132         _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1133                        data, ERIAR_OOB);
1134 }
1135
1136 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd)
1137 {
1138         rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd);
1139
1140         r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001);
1141 }
1142
1143 #define OOB_CMD_RESET           0x00
1144 #define OOB_CMD_DRIVER_START    0x05
1145 #define OOB_CMD_DRIVER_STOP     0x06
1146
1147 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1148 {
1149         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1150 }
1151
1152 DECLARE_RTL_COND(rtl_dp_ocp_read_cond)
1153 {
1154         u16 reg;
1155
1156         reg = rtl8168_get_ocp_reg(tp);
1157
1158         return r8168dp_ocp_read(tp, reg) & 0x00000800;
1159 }
1160
1161 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1162 {
1163         return r8168ep_ocp_read(tp, 0x124) & 0x00000001;
1164 }
1165
1166 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1167 {
1168         return RTL_R8(tp, IBISR0) & 0x20;
1169 }
1170
1171 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1172 {
1173         RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1174         rtl_loop_wait_high(tp, &rtl_ocp_tx_cond, 50000, 2000);
1175         RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1176         RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1177 }
1178
1179 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1180 {
1181         r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START);
1182         rtl_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10000, 10);
1183 }
1184
1185 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1186 {
1187         r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1188         r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01);
1189         rtl_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10000, 10);
1190 }
1191
1192 static void rtl8168_driver_start(struct rtl8169_private *tp)
1193 {
1194         if (tp->dash_type == RTL_DASH_DP)
1195                 rtl8168dp_driver_start(tp);
1196         else
1197                 rtl8168ep_driver_start(tp);
1198 }
1199
1200 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1201 {
1202         r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1203         rtl_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10000, 10);
1204 }
1205
1206 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1207 {
1208         rtl8168ep_stop_cmac(tp);
1209         r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1210         r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01);
1211         rtl_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10000, 10);
1212 }
1213
1214 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1215 {
1216         if (tp->dash_type == RTL_DASH_DP)
1217                 rtl8168dp_driver_stop(tp);
1218         else
1219                 rtl8168ep_driver_stop(tp);
1220 }
1221
1222 static bool r8168dp_check_dash(struct rtl8169_private *tp)
1223 {
1224         u16 reg = rtl8168_get_ocp_reg(tp);
1225
1226         return r8168dp_ocp_read(tp, reg) & BIT(15);
1227 }
1228
1229 static bool r8168ep_check_dash(struct rtl8169_private *tp)
1230 {
1231         return r8168ep_ocp_read(tp, 0x128) & BIT(0);
1232 }
1233
1234 static enum rtl_dash_type rtl_check_dash(struct rtl8169_private *tp)
1235 {
1236         switch (tp->mac_version) {
1237         case RTL_GIGA_MAC_VER_27:
1238         case RTL_GIGA_MAC_VER_28:
1239         case RTL_GIGA_MAC_VER_31:
1240                 return r8168dp_check_dash(tp) ? RTL_DASH_DP : RTL_DASH_NONE;
1241         case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52:
1242                 return r8168ep_check_dash(tp) ? RTL_DASH_EP : RTL_DASH_NONE;
1243         default:
1244                 return RTL_DASH_NONE;
1245         }
1246 }
1247
1248 static void rtl_set_d3_pll_down(struct rtl8169_private *tp, bool enable)
1249 {
1250         switch (tp->mac_version) {
1251         case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_26:
1252         case RTL_GIGA_MAC_VER_32 ... RTL_GIGA_MAC_VER_37:
1253         case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63:
1254                 if (enable)
1255                         RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~D3_NO_PLL_DOWN);
1256                 else
1257                         RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | D3_NO_PLL_DOWN);
1258                 break;
1259         default:
1260                 break;
1261         }
1262 }
1263
1264 static void rtl_reset_packet_filter(struct rtl8169_private *tp)
1265 {
1266         rtl_eri_clear_bits(tp, 0xdc, BIT(0));
1267         rtl_eri_set_bits(tp, 0xdc, BIT(0));
1268 }
1269
1270 DECLARE_RTL_COND(rtl_efusear_cond)
1271 {
1272         return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1273 }
1274
1275 u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1276 {
1277         RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1278
1279         return rtl_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1280                 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1281 }
1282
1283 static u32 rtl_get_events(struct rtl8169_private *tp)
1284 {
1285         if (rtl_is_8125(tp))
1286                 return RTL_R32(tp, IntrStatus_8125);
1287         else
1288                 return RTL_R16(tp, IntrStatus);
1289 }
1290
1291 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits)
1292 {
1293         if (rtl_is_8125(tp))
1294                 RTL_W32(tp, IntrStatus_8125, bits);
1295         else
1296                 RTL_W16(tp, IntrStatus, bits);
1297 }
1298
1299 static void rtl_irq_disable(struct rtl8169_private *tp)
1300 {
1301         if (rtl_is_8125(tp))
1302                 RTL_W32(tp, IntrMask_8125, 0);
1303         else
1304                 RTL_W16(tp, IntrMask, 0);
1305 }
1306
1307 static void rtl_irq_enable(struct rtl8169_private *tp)
1308 {
1309         if (rtl_is_8125(tp))
1310                 RTL_W32(tp, IntrMask_8125, tp->irq_mask);
1311         else
1312                 RTL_W16(tp, IntrMask, tp->irq_mask);
1313 }
1314
1315 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1316 {
1317         rtl_irq_disable(tp);
1318         rtl_ack_events(tp, 0xffffffff);
1319         rtl_pci_commit(tp);
1320 }
1321
1322 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1323 {
1324         struct phy_device *phydev = tp->phydev;
1325
1326         if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1327             tp->mac_version == RTL_GIGA_MAC_VER_38) {
1328                 if (phydev->speed == SPEED_1000) {
1329                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1330                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1331                 } else if (phydev->speed == SPEED_100) {
1332                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1333                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1334                 } else {
1335                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1336                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1337                 }
1338                 rtl_reset_packet_filter(tp);
1339         } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1340                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
1341                 if (phydev->speed == SPEED_1000) {
1342                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1343                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1344                 } else {
1345                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1346                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1347                 }
1348         } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1349                 if (phydev->speed == SPEED_10) {
1350                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02);
1351                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a);
1352                 } else {
1353                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
1354                 }
1355         }
1356 }
1357
1358 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1359
1360 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1361 {
1362         struct rtl8169_private *tp = netdev_priv(dev);
1363
1364         wol->supported = WAKE_ANY;
1365         wol->wolopts = tp->saved_wolopts;
1366 }
1367
1368 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1369 {
1370         static const struct {
1371                 u32 opt;
1372                 u16 reg;
1373                 u8  mask;
1374         } cfg[] = {
1375                 { WAKE_PHY,   Config3, LinkUp },
1376                 { WAKE_UCAST, Config5, UWF },
1377                 { WAKE_BCAST, Config5, BWF },
1378                 { WAKE_MCAST, Config5, MWF },
1379                 { WAKE_ANY,   Config5, LanWake },
1380                 { WAKE_MAGIC, Config3, MagicPacket }
1381         };
1382         unsigned int i, tmp = ARRAY_SIZE(cfg);
1383         u8 options;
1384
1385         rtl_unlock_config_regs(tp);
1386
1387         if (rtl_is_8168evl_up(tp)) {
1388                 tmp--;
1389                 if (wolopts & WAKE_MAGIC)
1390                         rtl_eri_set_bits(tp, 0x0dc, MagicPacket_v2);
1391                 else
1392                         rtl_eri_clear_bits(tp, 0x0dc, MagicPacket_v2);
1393         } else if (rtl_is_8125(tp)) {
1394                 tmp--;
1395                 if (wolopts & WAKE_MAGIC)
1396                         r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0));
1397                 else
1398                         r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0);
1399         }
1400
1401         for (i = 0; i < tmp; i++) {
1402                 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
1403                 if (wolopts & cfg[i].opt)
1404                         options |= cfg[i].mask;
1405                 RTL_W8(tp, cfg[i].reg, options);
1406         }
1407
1408         switch (tp->mac_version) {
1409         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
1410                 options = RTL_R8(tp, Config1) & ~PMEnable;
1411                 if (wolopts)
1412                         options |= PMEnable;
1413                 RTL_W8(tp, Config1, options);
1414                 break;
1415         case RTL_GIGA_MAC_VER_34:
1416         case RTL_GIGA_MAC_VER_37:
1417         case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63:
1418                 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
1419                 if (wolopts)
1420                         options |= PME_SIGNAL;
1421                 RTL_W8(tp, Config2, options);
1422                 break;
1423         default:
1424                 break;
1425         }
1426
1427         rtl_lock_config_regs(tp);
1428
1429         device_set_wakeup_enable(tp_to_dev(tp), wolopts);
1430         rtl_set_d3_pll_down(tp, !wolopts);
1431         tp->dev->wol_enabled = wolopts ? 1 : 0;
1432 }
1433
1434 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1435 {
1436         struct rtl8169_private *tp = netdev_priv(dev);
1437
1438         if (wol->wolopts & ~WAKE_ANY)
1439                 return -EINVAL;
1440
1441         tp->saved_wolopts = wol->wolopts;
1442         __rtl8169_set_wol(tp, tp->saved_wolopts);
1443
1444         return 0;
1445 }
1446
1447 static void rtl8169_get_drvinfo(struct net_device *dev,
1448                                 struct ethtool_drvinfo *info)
1449 {
1450         struct rtl8169_private *tp = netdev_priv(dev);
1451         struct rtl_fw *rtl_fw = tp->rtl_fw;
1452
1453         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1454         strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1455         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1456         if (rtl_fw)
1457                 strlcpy(info->fw_version, rtl_fw->version,
1458                         sizeof(info->fw_version));
1459 }
1460
1461 static int rtl8169_get_regs_len(struct net_device *dev)
1462 {
1463         return R8169_REGS_SIZE;
1464 }
1465
1466 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1467         netdev_features_t features)
1468 {
1469         struct rtl8169_private *tp = netdev_priv(dev);
1470
1471         if (dev->mtu > TD_MSS_MAX)
1472                 features &= ~NETIF_F_ALL_TSO;
1473
1474         if (dev->mtu > ETH_DATA_LEN &&
1475             tp->mac_version > RTL_GIGA_MAC_VER_06)
1476                 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_ALL_TSO);
1477
1478         return features;
1479 }
1480
1481 static void rtl_set_rx_config_features(struct rtl8169_private *tp,
1482                                        netdev_features_t features)
1483 {
1484         u32 rx_config = RTL_R32(tp, RxConfig);
1485
1486         if (features & NETIF_F_RXALL)
1487                 rx_config |= RX_CONFIG_ACCEPT_ERR_MASK;
1488         else
1489                 rx_config &= ~RX_CONFIG_ACCEPT_ERR_MASK;
1490
1491         if (rtl_is_8125(tp)) {
1492                 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1493                         rx_config |= RX_VLAN_8125;
1494                 else
1495                         rx_config &= ~RX_VLAN_8125;
1496         }
1497
1498         RTL_W32(tp, RxConfig, rx_config);
1499 }
1500
1501 static int rtl8169_set_features(struct net_device *dev,
1502                                 netdev_features_t features)
1503 {
1504         struct rtl8169_private *tp = netdev_priv(dev);
1505
1506         rtl_set_rx_config_features(tp, features);
1507
1508         if (features & NETIF_F_RXCSUM)
1509                 tp->cp_cmd |= RxChkSum;
1510         else
1511                 tp->cp_cmd &= ~RxChkSum;
1512
1513         if (!rtl_is_8125(tp)) {
1514                 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1515                         tp->cp_cmd |= RxVlan;
1516                 else
1517                         tp->cp_cmd &= ~RxVlan;
1518         }
1519
1520         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1521         rtl_pci_commit(tp);
1522
1523         return 0;
1524 }
1525
1526 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1527 {
1528         return (skb_vlan_tag_present(skb)) ?
1529                 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1530 }
1531
1532 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1533 {
1534         u32 opts2 = le32_to_cpu(desc->opts2);
1535
1536         if (opts2 & RxVlanTag)
1537                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1538 }
1539
1540 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1541                              void *p)
1542 {
1543         struct rtl8169_private *tp = netdev_priv(dev);
1544         u32 __iomem *data = tp->mmio_addr;
1545         u32 *dw = p;
1546         int i;
1547
1548         for (i = 0; i < R8169_REGS_SIZE; i += 4)
1549                 memcpy_fromio(dw++, data++, 4);
1550 }
1551
1552 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1553         "tx_packets",
1554         "rx_packets",
1555         "tx_errors",
1556         "rx_errors",
1557         "rx_missed",
1558         "align_errors",
1559         "tx_single_collisions",
1560         "tx_multi_collisions",
1561         "unicast",
1562         "broadcast",
1563         "multicast",
1564         "tx_aborted",
1565         "tx_underrun",
1566 };
1567
1568 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1569 {
1570         switch (sset) {
1571         case ETH_SS_STATS:
1572                 return ARRAY_SIZE(rtl8169_gstrings);
1573         default:
1574                 return -EOPNOTSUPP;
1575         }
1576 }
1577
1578 DECLARE_RTL_COND(rtl_counters_cond)
1579 {
1580         return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
1581 }
1582
1583 static void rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
1584 {
1585         dma_addr_t paddr = tp->counters_phys_addr;
1586         u32 cmd;
1587
1588         RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
1589         rtl_pci_commit(tp);
1590         cmd = (u64)paddr & DMA_BIT_MASK(32);
1591         RTL_W32(tp, CounterAddrLow, cmd);
1592         RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
1593
1594         rtl_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
1595 }
1596
1597 static void rtl8169_update_counters(struct rtl8169_private *tp)
1598 {
1599         u8 val = RTL_R8(tp, ChipCmd);
1600
1601         /*
1602          * Some chips are unable to dump tally counters when the receiver
1603          * is disabled. If 0xff chip may be in a PCI power-save state.
1604          */
1605         if (val & CmdRxEnb && val != 0xff)
1606                 rtl8169_do_counters(tp, CounterDump);
1607 }
1608
1609 static void rtl8169_init_counter_offsets(struct rtl8169_private *tp)
1610 {
1611         struct rtl8169_counters *counters = tp->counters;
1612
1613         /*
1614          * rtl8169_init_counter_offsets is called from rtl_open.  On chip
1615          * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1616          * reset by a power cycle, while the counter values collected by the
1617          * driver are reset at every driver unload/load cycle.
1618          *
1619          * To make sure the HW values returned by @get_stats64 match the SW
1620          * values, we collect the initial values at first open(*) and use them
1621          * as offsets to normalize the values returned by @get_stats64.
1622          *
1623          * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1624          * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1625          * set at open time by rtl_hw_start.
1626          */
1627
1628         if (tp->tc_offset.inited)
1629                 return;
1630
1631         if (tp->mac_version >= RTL_GIGA_MAC_VER_19) {
1632                 rtl8169_do_counters(tp, CounterReset);
1633         } else {
1634                 rtl8169_update_counters(tp);
1635                 tp->tc_offset.tx_errors = counters->tx_errors;
1636                 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1637                 tp->tc_offset.tx_aborted = counters->tx_aborted;
1638                 tp->tc_offset.rx_missed = counters->rx_missed;
1639         }
1640
1641         tp->tc_offset.inited = true;
1642 }
1643
1644 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1645                                       struct ethtool_stats *stats, u64 *data)
1646 {
1647         struct rtl8169_private *tp = netdev_priv(dev);
1648         struct rtl8169_counters *counters;
1649
1650         counters = tp->counters;
1651         rtl8169_update_counters(tp);
1652
1653         data[0] = le64_to_cpu(counters->tx_packets);
1654         data[1] = le64_to_cpu(counters->rx_packets);
1655         data[2] = le64_to_cpu(counters->tx_errors);
1656         data[3] = le32_to_cpu(counters->rx_errors);
1657         data[4] = le16_to_cpu(counters->rx_missed);
1658         data[5] = le16_to_cpu(counters->align_errors);
1659         data[6] = le32_to_cpu(counters->tx_one_collision);
1660         data[7] = le32_to_cpu(counters->tx_multi_collision);
1661         data[8] = le64_to_cpu(counters->rx_unicast);
1662         data[9] = le64_to_cpu(counters->rx_broadcast);
1663         data[10] = le32_to_cpu(counters->rx_multicast);
1664         data[11] = le16_to_cpu(counters->tx_aborted);
1665         data[12] = le16_to_cpu(counters->tx_underun);
1666 }
1667
1668 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1669 {
1670         switch(stringset) {
1671         case ETH_SS_STATS:
1672                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1673                 break;
1674         }
1675 }
1676
1677 /*
1678  * Interrupt coalescing
1679  *
1680  * > 1 - the availability of the IntrMitigate (0xe2) register through the
1681  * >     8169, 8168 and 810x line of chipsets
1682  *
1683  * 8169, 8168, and 8136(810x) serial chipsets support it.
1684  *
1685  * > 2 - the Tx timer unit at gigabit speed
1686  *
1687  * The unit of the timer depends on both the speed and the setting of CPlusCmd
1688  * (0xe0) bit 1 and bit 0.
1689  *
1690  * For 8169
1691  * bit[1:0] \ speed        1000M           100M            10M
1692  * 0 0                     320ns           2.56us          40.96us
1693  * 0 1                     2.56us          20.48us         327.7us
1694  * 1 0                     5.12us          40.96us         655.4us
1695  * 1 1                     10.24us         81.92us         1.31ms
1696  *
1697  * For the other
1698  * bit[1:0] \ speed        1000M           100M            10M
1699  * 0 0                     5us             2.56us          40.96us
1700  * 0 1                     40us            20.48us         327.7us
1701  * 1 0                     80us            40.96us         655.4us
1702  * 1 1                     160us           81.92us         1.31ms
1703  */
1704
1705 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
1706 struct rtl_coalesce_info {
1707         u32 speed;
1708         u32 scale_nsecs[4];
1709 };
1710
1711 /* produce array with base delay *1, *8, *8*2, *8*2*2 */
1712 #define COALESCE_DELAY(d) { (d), 8 * (d), 16 * (d), 32 * (d) }
1713
1714 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1715         { SPEED_1000,   COALESCE_DELAY(320) },
1716         { SPEED_100,    COALESCE_DELAY(2560) },
1717         { SPEED_10,     COALESCE_DELAY(40960) },
1718         { 0 },
1719 };
1720
1721 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1722         { SPEED_1000,   COALESCE_DELAY(5000) },
1723         { SPEED_100,    COALESCE_DELAY(2560) },
1724         { SPEED_10,     COALESCE_DELAY(40960) },
1725         { 0 },
1726 };
1727 #undef COALESCE_DELAY
1728
1729 /* get rx/tx scale vector corresponding to current speed */
1730 static const struct rtl_coalesce_info *
1731 rtl_coalesce_info(struct rtl8169_private *tp)
1732 {
1733         const struct rtl_coalesce_info *ci;
1734
1735         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1736                 ci = rtl_coalesce_info_8169;
1737         else
1738                 ci = rtl_coalesce_info_8168_8136;
1739
1740         /* if speed is unknown assume highest one */
1741         if (tp->phydev->speed == SPEED_UNKNOWN)
1742                 return ci;
1743
1744         for (; ci->speed; ci++) {
1745                 if (tp->phydev->speed == ci->speed)
1746                         return ci;
1747         }
1748
1749         return ERR_PTR(-ELNRNG);
1750 }
1751
1752 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1753 {
1754         struct rtl8169_private *tp = netdev_priv(dev);
1755         const struct rtl_coalesce_info *ci;
1756         u32 scale, c_us, c_fr;
1757         u16 intrmit;
1758
1759         if (rtl_is_8125(tp))
1760                 return -EOPNOTSUPP;
1761
1762         memset(ec, 0, sizeof(*ec));
1763
1764         /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1765         ci = rtl_coalesce_info(tp);
1766         if (IS_ERR(ci))
1767                 return PTR_ERR(ci);
1768
1769         scale = ci->scale_nsecs[tp->cp_cmd & INTT_MASK];
1770
1771         intrmit = RTL_R16(tp, IntrMitigate);
1772
1773         c_us = FIELD_GET(RTL_COALESCE_TX_USECS, intrmit);
1774         ec->tx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000);
1775
1776         c_fr = FIELD_GET(RTL_COALESCE_TX_FRAMES, intrmit);
1777         /* ethtool_coalesce states usecs and max_frames must not both be 0 */
1778         ec->tx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1;
1779
1780         c_us = FIELD_GET(RTL_COALESCE_RX_USECS, intrmit);
1781         ec->rx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000);
1782
1783         c_fr = FIELD_GET(RTL_COALESCE_RX_FRAMES, intrmit);
1784         ec->rx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1;
1785
1786         return 0;
1787 }
1788
1789 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, usec) */
1790 static int rtl_coalesce_choose_scale(struct rtl8169_private *tp, u32 usec,
1791                                      u16 *cp01)
1792 {
1793         const struct rtl_coalesce_info *ci;
1794         u16 i;
1795
1796         ci = rtl_coalesce_info(tp);
1797         if (IS_ERR(ci))
1798                 return PTR_ERR(ci);
1799
1800         for (i = 0; i < 4; i++) {
1801                 if (usec <= ci->scale_nsecs[i] * RTL_COALESCE_T_MAX / 1000U) {
1802                         *cp01 = i;
1803                         return ci->scale_nsecs[i];
1804                 }
1805         }
1806
1807         return -ERANGE;
1808 }
1809
1810 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1811 {
1812         struct rtl8169_private *tp = netdev_priv(dev);
1813         u32 tx_fr = ec->tx_max_coalesced_frames;
1814         u32 rx_fr = ec->rx_max_coalesced_frames;
1815         u32 coal_usec_max, units;
1816         u16 w = 0, cp01 = 0;
1817         int scale;
1818
1819         if (rtl_is_8125(tp))
1820                 return -EOPNOTSUPP;
1821
1822         if (rx_fr > RTL_COALESCE_FRAME_MAX || tx_fr > RTL_COALESCE_FRAME_MAX)
1823                 return -ERANGE;
1824
1825         coal_usec_max = max(ec->rx_coalesce_usecs, ec->tx_coalesce_usecs);
1826         scale = rtl_coalesce_choose_scale(tp, coal_usec_max, &cp01);
1827         if (scale < 0)
1828                 return scale;
1829
1830         /* Accept max_frames=1 we returned in rtl_get_coalesce. Accept it
1831          * not only when usecs=0 because of e.g. the following scenario:
1832          *
1833          * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
1834          * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
1835          * - then user does `ethtool -C eth0 rx-usecs 100`
1836          *
1837          * Since ethtool sends to kernel whole ethtool_coalesce settings,
1838          * if we want to ignore rx_frames then it has to be set to 0.
1839          */
1840         if (rx_fr == 1)
1841                 rx_fr = 0;
1842         if (tx_fr == 1)
1843                 tx_fr = 0;
1844
1845         /* HW requires time limit to be set if frame limit is set */
1846         if ((tx_fr && !ec->tx_coalesce_usecs) ||
1847             (rx_fr && !ec->rx_coalesce_usecs))
1848                 return -EINVAL;
1849
1850         w |= FIELD_PREP(RTL_COALESCE_TX_FRAMES, DIV_ROUND_UP(tx_fr, 4));
1851         w |= FIELD_PREP(RTL_COALESCE_RX_FRAMES, DIV_ROUND_UP(rx_fr, 4));
1852
1853         units = DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000U, scale);
1854         w |= FIELD_PREP(RTL_COALESCE_TX_USECS, units);
1855         units = DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000U, scale);
1856         w |= FIELD_PREP(RTL_COALESCE_RX_USECS, units);
1857
1858         RTL_W16(tp, IntrMitigate, w);
1859
1860         /* Meaning of PktCntrDisable bit changed from RTL8168e-vl */
1861         if (rtl_is_8168evl_up(tp)) {
1862                 if (!rx_fr && !tx_fr)
1863                         /* disable packet counter */
1864                         tp->cp_cmd |= PktCntrDisable;
1865                 else
1866                         tp->cp_cmd &= ~PktCntrDisable;
1867         }
1868
1869         tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
1870         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1871         rtl_pci_commit(tp);
1872
1873         return 0;
1874 }
1875
1876 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data)
1877 {
1878         struct rtl8169_private *tp = netdev_priv(dev);
1879
1880         if (!rtl_supports_eee(tp))
1881                 return -EOPNOTSUPP;
1882
1883         return phy_ethtool_get_eee(tp->phydev, data);
1884 }
1885
1886 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data)
1887 {
1888         struct rtl8169_private *tp = netdev_priv(dev);
1889         int ret;
1890
1891         if (!rtl_supports_eee(tp))
1892                 return -EOPNOTSUPP;
1893
1894         ret = phy_ethtool_set_eee(tp->phydev, data);
1895
1896         if (!ret)
1897                 tp->eee_adv = phy_read_mmd(dev->phydev, MDIO_MMD_AN,
1898                                            MDIO_AN_EEE_ADV);
1899         return ret;
1900 }
1901
1902 static const struct ethtool_ops rtl8169_ethtool_ops = {
1903         .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
1904                                      ETHTOOL_COALESCE_MAX_FRAMES,
1905         .get_drvinfo            = rtl8169_get_drvinfo,
1906         .get_regs_len           = rtl8169_get_regs_len,
1907         .get_link               = ethtool_op_get_link,
1908         .get_coalesce           = rtl_get_coalesce,
1909         .set_coalesce           = rtl_set_coalesce,
1910         .get_regs               = rtl8169_get_regs,
1911         .get_wol                = rtl8169_get_wol,
1912         .set_wol                = rtl8169_set_wol,
1913         .get_strings            = rtl8169_get_strings,
1914         .get_sset_count         = rtl8169_get_sset_count,
1915         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
1916         .get_ts_info            = ethtool_op_get_ts_info,
1917         .nway_reset             = phy_ethtool_nway_reset,
1918         .get_eee                = rtl8169_get_eee,
1919         .set_eee                = rtl8169_set_eee,
1920         .get_link_ksettings     = phy_ethtool_get_link_ksettings,
1921         .set_link_ksettings     = phy_ethtool_set_link_ksettings,
1922 };
1923
1924 static void rtl_enable_eee(struct rtl8169_private *tp)
1925 {
1926         struct phy_device *phydev = tp->phydev;
1927         int adv;
1928
1929         /* respect EEE advertisement the user may have set */
1930         if (tp->eee_adv >= 0)
1931                 adv = tp->eee_adv;
1932         else
1933                 adv = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
1934
1935         if (adv >= 0)
1936                 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, adv);
1937 }
1938
1939 static enum mac_version rtl8169_get_mac_version(u16 xid, bool gmii)
1940 {
1941         /*
1942          * The driver currently handles the 8168Bf and the 8168Be identically
1943          * but they can be identified more specifically through the test below
1944          * if needed:
1945          *
1946          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1947          *
1948          * Same thing for the 8101Eb and the 8101Ec:
1949          *
1950          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1951          */
1952         static const struct rtl_mac_info {
1953                 u16 mask;
1954                 u16 val;
1955                 enum mac_version ver;
1956         } mac_info[] = {
1957                 /* 8125B family. */
1958                 { 0x7cf, 0x641, RTL_GIGA_MAC_VER_63 },
1959
1960                 /* 8125A family. */
1961                 { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 },
1962                 { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 },
1963
1964                 /* RTL8117 */
1965                 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52 },
1966
1967                 /* 8168EP family. */
1968                 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 },
1969                 { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 },
1970                 { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 },
1971
1972                 /* 8168H family. */
1973                 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 },
1974                 { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 },
1975
1976                 /* 8168G family. */
1977                 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 },
1978                 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 },
1979                 { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 },
1980                 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 },
1981
1982                 /* 8168F family. */
1983                 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 },
1984                 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 },
1985                 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 },
1986
1987                 /* 8168E family. */
1988                 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 },
1989                 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 },
1990                 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 },
1991
1992                 /* 8168D family. */
1993                 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 },
1994                 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 },
1995
1996                 /* 8168DP family. */
1997                 /* It seems this early RTL8168dp version never made it to
1998                  * the wild. Let's see whether somebody complains, if not
1999                  * we'll remove support for this chip version completely.
2000                  * { 0x7cf, 0x288,      RTL_GIGA_MAC_VER_27 },
2001                  */
2002                 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 },
2003                 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 },
2004
2005                 /* 8168C family. */
2006                 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 },
2007                 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 },
2008                 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 },
2009                 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 },
2010                 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 },
2011                 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 },
2012                 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 },
2013
2014                 /* 8168B family. */
2015                 { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12 },
2016                 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 },
2017                 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 },
2018
2019                 /* 8101 family. */
2020                 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 },
2021                 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 },
2022                 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 },
2023                 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 },
2024                 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 },
2025                 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 },
2026                 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 },
2027                 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 },
2028                 { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13 },
2029                 { 0x7cf, 0x240, RTL_GIGA_MAC_VER_14 },
2030                 { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10 },
2031                 { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16 },
2032                 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 },
2033                 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 },
2034                 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16 },
2035                 /* FIXME: where did these entries come from ? -- FR */
2036                 { 0xfc8, 0x388, RTL_GIGA_MAC_VER_13 },
2037                 { 0xfc8, 0x308, RTL_GIGA_MAC_VER_13 },
2038
2039                 /* 8110 family. */
2040                 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 },
2041                 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 },
2042                 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 },
2043                 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 },
2044                 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 },
2045
2046                 /* Catch-all */
2047                 { 0x000, 0x000, RTL_GIGA_MAC_NONE   }
2048         };
2049         const struct rtl_mac_info *p = mac_info;
2050         enum mac_version ver;
2051
2052         while ((xid & p->mask) != p->val)
2053                 p++;
2054         ver = p->ver;
2055
2056         if (ver != RTL_GIGA_MAC_NONE && !gmii) {
2057                 if (ver == RTL_GIGA_MAC_VER_42)
2058                         ver = RTL_GIGA_MAC_VER_43;
2059                 else if (ver == RTL_GIGA_MAC_VER_45)
2060                         ver = RTL_GIGA_MAC_VER_47;
2061                 else if (ver == RTL_GIGA_MAC_VER_46)
2062                         ver = RTL_GIGA_MAC_VER_48;
2063         }
2064
2065         return ver;
2066 }
2067
2068 static void rtl_release_firmware(struct rtl8169_private *tp)
2069 {
2070         if (tp->rtl_fw) {
2071                 rtl_fw_release_firmware(tp->rtl_fw);
2072                 kfree(tp->rtl_fw);
2073                 tp->rtl_fw = NULL;
2074         }
2075 }
2076
2077 void r8169_apply_firmware(struct rtl8169_private *tp)
2078 {
2079         int val;
2080
2081         /* TODO: release firmware if rtl_fw_write_firmware signals failure. */
2082         if (tp->rtl_fw) {
2083                 rtl_fw_write_firmware(tp, tp->rtl_fw);
2084                 /* At least one firmware doesn't reset tp->ocp_base. */
2085                 tp->ocp_base = OCP_STD_PHY_BASE;
2086
2087                 /* PHY soft reset may still be in progress */
2088                 phy_read_poll_timeout(tp->phydev, MII_BMCR, val,
2089                                       !(val & BMCR_RESET),
2090                                       50000, 600000, true);
2091         }
2092 }
2093
2094 static void rtl8168_config_eee_mac(struct rtl8169_private *tp)
2095 {
2096         /* Adjust EEE LED frequency */
2097         if (tp->mac_version != RTL_GIGA_MAC_VER_38)
2098                 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
2099
2100         rtl_eri_set_bits(tp, 0x1b0, 0x0003);
2101 }
2102
2103 static void rtl8125a_config_eee_mac(struct rtl8169_private *tp)
2104 {
2105         r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0));
2106         r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1));
2107 }
2108
2109 static void rtl8125_set_eee_txidle_timer(struct rtl8169_private *tp)
2110 {
2111         RTL_W16(tp, EEE_TXIDLE_TIMER_8125, tp->dev->mtu + ETH_HLEN + 0x20);
2112 }
2113
2114 static void rtl8125b_config_eee_mac(struct rtl8169_private *tp)
2115 {
2116         rtl8125_set_eee_txidle_timer(tp);
2117         r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0));
2118 }
2119
2120 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, const u8 *addr)
2121 {
2122         rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, get_unaligned_le32(addr));
2123         rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, get_unaligned_le16(addr + 4));
2124         rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, get_unaligned_le16(addr) << 16);
2125         rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, get_unaligned_le32(addr + 2));
2126 }
2127
2128 u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp)
2129 {
2130         u16 data1, data2, ioffset;
2131
2132         r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
2133         data1 = r8168_mac_ocp_read(tp, 0xdd02);
2134         data2 = r8168_mac_ocp_read(tp, 0xdd00);
2135
2136         ioffset = (data2 >> 1) & 0x7ff8;
2137         ioffset |= data2 & 0x0007;
2138         if (data1 & BIT(7))
2139                 ioffset |= BIT(15);
2140
2141         return ioffset;
2142 }
2143
2144 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
2145 {
2146         set_bit(flag, tp->wk.flags);
2147         schedule_work(&tp->wk.work);
2148 }
2149
2150 static void rtl8169_init_phy(struct rtl8169_private *tp)
2151 {
2152         r8169_hw_phy_config(tp, tp->phydev, tp->mac_version);
2153
2154         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2155                 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2156                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
2157                 /* set undocumented MAC Reg C+CR Offset 0x82h */
2158                 RTL_W8(tp, 0x82, 0x01);
2159         }
2160
2161         if (tp->mac_version == RTL_GIGA_MAC_VER_05 &&
2162             tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE &&
2163             tp->pci_dev->subsystem_device == 0xe000)
2164                 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b);
2165
2166         /* We may have called phy_speed_down before */
2167         phy_speed_up(tp->phydev);
2168
2169         if (rtl_supports_eee(tp))
2170                 rtl_enable_eee(tp);
2171
2172         genphy_soft_reset(tp->phydev);
2173 }
2174
2175 static void rtl_rar_set(struct rtl8169_private *tp, const u8 *addr)
2176 {
2177         rtl_unlock_config_regs(tp);
2178
2179         RTL_W32(tp, MAC4, get_unaligned_le16(addr + 4));
2180         rtl_pci_commit(tp);
2181
2182         RTL_W32(tp, MAC0, get_unaligned_le32(addr));
2183         rtl_pci_commit(tp);
2184
2185         if (tp->mac_version == RTL_GIGA_MAC_VER_34)
2186                 rtl_rar_exgmac_set(tp, addr);
2187
2188         rtl_lock_config_regs(tp);
2189 }
2190
2191 static int rtl_set_mac_address(struct net_device *dev, void *p)
2192 {
2193         struct rtl8169_private *tp = netdev_priv(dev);
2194         int ret;
2195
2196         ret = eth_mac_addr(dev, p);
2197         if (ret)
2198                 return ret;
2199
2200         rtl_rar_set(tp, dev->dev_addr);
2201
2202         return 0;
2203 }
2204
2205 static void rtl_wol_enable_rx(struct rtl8169_private *tp)
2206 {
2207         if (tp->mac_version >= RTL_GIGA_MAC_VER_25)
2208                 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
2209                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
2210 }
2211
2212 static void rtl_prepare_power_down(struct rtl8169_private *tp)
2213 {
2214         if (tp->dash_type != RTL_DASH_NONE)
2215                 return;
2216
2217         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
2218             tp->mac_version == RTL_GIGA_MAC_VER_33)
2219                 rtl_ephy_write(tp, 0x19, 0xff64);
2220
2221         if (device_may_wakeup(tp_to_dev(tp))) {
2222                 phy_speed_down(tp->phydev, false);
2223                 rtl_wol_enable_rx(tp);
2224         }
2225 }
2226
2227 static void rtl_init_rxcfg(struct rtl8169_private *tp)
2228 {
2229         switch (tp->mac_version) {
2230         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
2231         case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
2232                 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
2233                 break;
2234         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
2235         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
2236         case RTL_GIGA_MAC_VER_38:
2237                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
2238                 break;
2239         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_52:
2240                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
2241                 break;
2242         case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_63:
2243                 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST);
2244                 break;
2245         default:
2246                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
2247                 break;
2248         }
2249 }
2250
2251 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2252 {
2253         tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
2254 }
2255
2256 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
2257 {
2258         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2259         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
2260 }
2261
2262 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
2263 {
2264         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2265         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
2266 }
2267
2268 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
2269 {
2270         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2271 }
2272
2273 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
2274 {
2275         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2276 }
2277
2278 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
2279 {
2280         RTL_W8(tp, MaxTxPacketSize, 0x3f);
2281         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2282         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
2283 }
2284
2285 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
2286 {
2287         RTL_W8(tp, MaxTxPacketSize, 0x0c);
2288         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2289         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
2290 }
2291
2292 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
2293 {
2294         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
2295 }
2296
2297 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
2298 {
2299         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
2300 }
2301
2302 static void rtl_jumbo_config(struct rtl8169_private *tp)
2303 {
2304         bool jumbo = tp->dev->mtu > ETH_DATA_LEN;
2305         int readrq = 4096;
2306
2307         rtl_unlock_config_regs(tp);
2308         switch (tp->mac_version) {
2309         case RTL_GIGA_MAC_VER_12:
2310         case RTL_GIGA_MAC_VER_17:
2311                 if (jumbo) {
2312                         readrq = 512;
2313                         r8168b_1_hw_jumbo_enable(tp);
2314                 } else {
2315                         r8168b_1_hw_jumbo_disable(tp);
2316                 }
2317                 break;
2318         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26:
2319                 if (jumbo) {
2320                         readrq = 512;
2321                         r8168c_hw_jumbo_enable(tp);
2322                 } else {
2323                         r8168c_hw_jumbo_disable(tp);
2324                 }
2325                 break;
2326         case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28:
2327                 if (jumbo)
2328                         r8168dp_hw_jumbo_enable(tp);
2329                 else
2330                         r8168dp_hw_jumbo_disable(tp);
2331                 break;
2332         case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33:
2333                 if (jumbo)
2334                         r8168e_hw_jumbo_enable(tp);
2335                 else
2336                         r8168e_hw_jumbo_disable(tp);
2337                 break;
2338         default:
2339                 break;
2340         }
2341         rtl_lock_config_regs(tp);
2342
2343         if (pci_is_pcie(tp->pci_dev) && tp->supports_gmii)
2344                 pcie_set_readrq(tp->pci_dev, readrq);
2345 }
2346
2347 DECLARE_RTL_COND(rtl_chipcmd_cond)
2348 {
2349         return RTL_R8(tp, ChipCmd) & CmdReset;
2350 }
2351
2352 static void rtl_hw_reset(struct rtl8169_private *tp)
2353 {
2354         RTL_W8(tp, ChipCmd, CmdReset);
2355
2356         rtl_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
2357 }
2358
2359 static void rtl_request_firmware(struct rtl8169_private *tp)
2360 {
2361         struct rtl_fw *rtl_fw;
2362
2363         /* firmware loaded already or no firmware available */
2364         if (tp->rtl_fw || !tp->fw_name)
2365                 return;
2366
2367         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
2368         if (!rtl_fw)
2369                 return;
2370
2371         rtl_fw->phy_write = rtl_writephy;
2372         rtl_fw->phy_read = rtl_readphy;
2373         rtl_fw->mac_mcu_write = mac_mcu_write;
2374         rtl_fw->mac_mcu_read = mac_mcu_read;
2375         rtl_fw->fw_name = tp->fw_name;
2376         rtl_fw->dev = tp_to_dev(tp);
2377
2378         if (rtl_fw_request_firmware(rtl_fw))
2379                 kfree(rtl_fw);
2380         else
2381                 tp->rtl_fw = rtl_fw;
2382 }
2383
2384 static void rtl_rx_close(struct rtl8169_private *tp)
2385 {
2386         RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
2387 }
2388
2389 DECLARE_RTL_COND(rtl_npq_cond)
2390 {
2391         return RTL_R8(tp, TxPoll) & NPQ;
2392 }
2393
2394 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
2395 {
2396         return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
2397 }
2398
2399 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
2400 {
2401         return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
2402 }
2403
2404 DECLARE_RTL_COND(rtl_rxtx_empty_cond_2)
2405 {
2406         /* IntrMitigate has new functionality on RTL8125 */
2407         return (RTL_R16(tp, IntrMitigate) & 0x0103) == 0x0103;
2408 }
2409
2410 static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp)
2411 {
2412         switch (tp->mac_version) {
2413         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_52:
2414                 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42);
2415                 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2416                 break;
2417         case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_61:
2418                 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2419                 break;
2420         case RTL_GIGA_MAC_VER_63:
2421                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
2422                 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2423                 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond_2, 100, 42);
2424                 break;
2425         default:
2426                 break;
2427         }
2428 }
2429
2430 static void rtl_enable_rxdvgate(struct rtl8169_private *tp)
2431 {
2432         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
2433         fsleep(2000);
2434         rtl_wait_txrx_fifo_empty(tp);
2435 }
2436
2437 static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
2438 {
2439         u32 val = TX_DMA_BURST << TxDMAShift |
2440                   InterFrameGap << TxInterFrameGapShift;
2441
2442         if (rtl_is_8168evl_up(tp))
2443                 val |= TXCFG_AUTO_FIFO;
2444
2445         RTL_W32(tp, TxConfig, val);
2446 }
2447
2448 static void rtl_set_rx_max_size(struct rtl8169_private *tp)
2449 {
2450         /* Low hurts. Let's disable the filtering. */
2451         RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
2452 }
2453
2454 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
2455 {
2456         /*
2457          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
2458          * register to be written before TxDescAddrLow to work.
2459          * Switching from MMIO to I/O access fixes the issue as well.
2460          */
2461         RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
2462         RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
2463         RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
2464         RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
2465 }
2466
2467 static void rtl8169_set_magic_reg(struct rtl8169_private *tp)
2468 {
2469         u32 val;
2470
2471         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
2472                 val = 0x000fff00;
2473         else if (tp->mac_version == RTL_GIGA_MAC_VER_06)
2474                 val = 0x00ffff00;
2475         else
2476                 return;
2477
2478         if (RTL_R8(tp, Config2) & PCI_Clock_66MHz)
2479                 val |= 0xff;
2480
2481         RTL_W32(tp, 0x7c, val);
2482 }
2483
2484 static void rtl_set_rx_mode(struct net_device *dev)
2485 {
2486         u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast;
2487         /* Multicast hash filter */
2488         u32 mc_filter[2] = { 0xffffffff, 0xffffffff };
2489         struct rtl8169_private *tp = netdev_priv(dev);
2490         u32 tmp;
2491
2492         if (dev->flags & IFF_PROMISC) {
2493                 rx_mode |= AcceptAllPhys;
2494         } else if (netdev_mc_count(dev) > MC_FILTER_LIMIT ||
2495                    dev->flags & IFF_ALLMULTI ||
2496                    tp->mac_version == RTL_GIGA_MAC_VER_35) {
2497                 /* accept all multicasts */
2498         } else if (netdev_mc_empty(dev)) {
2499                 rx_mode &= ~AcceptMulticast;
2500         } else {
2501                 struct netdev_hw_addr *ha;
2502
2503                 mc_filter[1] = mc_filter[0] = 0;
2504                 netdev_for_each_mc_addr(ha, dev) {
2505                         u32 bit_nr = eth_hw_addr_crc(ha) >> 26;
2506                         mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31);
2507                 }
2508
2509                 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
2510                         tmp = mc_filter[0];
2511                         mc_filter[0] = swab32(mc_filter[1]);
2512                         mc_filter[1] = swab32(tmp);
2513                 }
2514         }
2515
2516         RTL_W32(tp, MAR0 + 4, mc_filter[1]);
2517         RTL_W32(tp, MAR0 + 0, mc_filter[0]);
2518
2519         tmp = RTL_R32(tp, RxConfig);
2520         RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode);
2521 }
2522
2523 DECLARE_RTL_COND(rtl_csiar_cond)
2524 {
2525         return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
2526 }
2527
2528 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
2529 {
2530         u32 func = PCI_FUNC(tp->pci_dev->devfn);
2531
2532         RTL_W32(tp, CSIDR, value);
2533         RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
2534                 CSIAR_BYTE_ENABLE | func << 16);
2535
2536         rtl_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
2537 }
2538
2539 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
2540 {
2541         u32 func = PCI_FUNC(tp->pci_dev->devfn);
2542
2543         RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
2544                 CSIAR_BYTE_ENABLE);
2545
2546         return rtl_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
2547                 RTL_R32(tp, CSIDR) : ~0;
2548 }
2549
2550 static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val)
2551 {
2552         struct pci_dev *pdev = tp->pci_dev;
2553         u32 csi;
2554
2555         /* According to Realtek the value at config space address 0x070f
2556          * controls the L0s/L1 entrance latency. We try standard ECAM access
2557          * first and if it fails fall back to CSI.
2558          */
2559         if (pdev->cfg_size > 0x070f &&
2560             pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
2561                 return;
2562
2563         netdev_notice_once(tp->dev,
2564                 "No native access to PCI extended config space, falling back to CSI\n");
2565         csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
2566         rtl_csi_write(tp, 0x070c, csi | val << 24);
2567 }
2568
2569 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
2570 {
2571         rtl_csi_access_enable(tp, 0x27);
2572 }
2573
2574 struct ephy_info {
2575         unsigned int offset;
2576         u16 mask;
2577         u16 bits;
2578 };
2579
2580 static void __rtl_ephy_init(struct rtl8169_private *tp,
2581                             const struct ephy_info *e, int len)
2582 {
2583         u16 w;
2584
2585         while (len-- > 0) {
2586                 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
2587                 rtl_ephy_write(tp, e->offset, w);
2588                 e++;
2589         }
2590 }
2591
2592 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a))
2593
2594 static void rtl_disable_clock_request(struct rtl8169_private *tp)
2595 {
2596         pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
2597                                    PCI_EXP_LNKCTL_CLKREQ_EN);
2598 }
2599
2600 static void rtl_enable_clock_request(struct rtl8169_private *tp)
2601 {
2602         pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
2603                                  PCI_EXP_LNKCTL_CLKREQ_EN);
2604 }
2605
2606 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp)
2607 {
2608         /* work around an issue when PCI reset occurs during L2/L3 state */
2609         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23);
2610 }
2611
2612 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
2613 {
2614         /* Don't enable ASPM in the chip if OS can't control ASPM */
2615         if (enable && tp->aspm_manageable) {
2616                 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);
2617                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);
2618         } else {
2619                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
2620                 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
2621         }
2622
2623         udelay(10);
2624 }
2625
2626 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat,
2627                               u16 tx_stat, u16 rx_dyn, u16 tx_dyn)
2628 {
2629         /* Usage of dynamic vs. static FIFO is controlled by bit
2630          * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known.
2631          */
2632         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn);
2633         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn);
2634 }
2635
2636 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp,
2637                                           u8 low, u8 high)
2638 {
2639         /* FIFO thresholds for pause flow control */
2640         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low);
2641         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high);
2642 }
2643
2644 static void rtl_hw_start_8168b(struct rtl8169_private *tp)
2645 {
2646         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2647 }
2648
2649 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
2650 {
2651         RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
2652
2653         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2654
2655         rtl_disable_clock_request(tp);
2656 }
2657
2658 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
2659 {
2660         static const struct ephy_info e_info_8168cp[] = {
2661                 { 0x01, 0,      0x0001 },
2662                 { 0x02, 0x0800, 0x1000 },
2663                 { 0x03, 0,      0x0042 },
2664                 { 0x06, 0x0080, 0x0000 },
2665                 { 0x07, 0,      0x2000 }
2666         };
2667
2668         rtl_set_def_aspm_entry_latency(tp);
2669
2670         rtl_ephy_init(tp, e_info_8168cp);
2671
2672         __rtl_hw_start_8168cp(tp);
2673 }
2674
2675 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
2676 {
2677         rtl_set_def_aspm_entry_latency(tp);
2678
2679         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2680 }
2681
2682 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
2683 {
2684         rtl_set_def_aspm_entry_latency(tp);
2685
2686         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2687
2688         /* Magic. */
2689         RTL_W8(tp, DBG_REG, 0x20);
2690 }
2691
2692 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
2693 {
2694         static const struct ephy_info e_info_8168c_1[] = {
2695                 { 0x02, 0x0800, 0x1000 },
2696                 { 0x03, 0,      0x0002 },
2697                 { 0x06, 0x0080, 0x0000 }
2698         };
2699
2700         rtl_set_def_aspm_entry_latency(tp);
2701
2702         RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
2703
2704         rtl_ephy_init(tp, e_info_8168c_1);
2705
2706         __rtl_hw_start_8168cp(tp);
2707 }
2708
2709 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
2710 {
2711         static const struct ephy_info e_info_8168c_2[] = {
2712                 { 0x01, 0,      0x0001 },
2713                 { 0x03, 0x0400, 0x0020 }
2714         };
2715
2716         rtl_set_def_aspm_entry_latency(tp);
2717
2718         rtl_ephy_init(tp, e_info_8168c_2);
2719
2720         __rtl_hw_start_8168cp(tp);
2721 }
2722
2723 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
2724 {
2725         rtl_hw_start_8168c_2(tp);
2726 }
2727
2728 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
2729 {
2730         rtl_set_def_aspm_entry_latency(tp);
2731
2732         __rtl_hw_start_8168cp(tp);
2733 }
2734
2735 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
2736 {
2737         rtl_set_def_aspm_entry_latency(tp);
2738
2739         rtl_disable_clock_request(tp);
2740 }
2741
2742 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
2743 {
2744         static const struct ephy_info e_info_8168d_4[] = {
2745                 { 0x0b, 0x0000, 0x0048 },
2746                 { 0x19, 0x0020, 0x0050 },
2747                 { 0x0c, 0x0100, 0x0020 },
2748                 { 0x10, 0x0004, 0x0000 },
2749         };
2750
2751         rtl_set_def_aspm_entry_latency(tp);
2752
2753         rtl_ephy_init(tp, e_info_8168d_4);
2754
2755         rtl_enable_clock_request(tp);
2756 }
2757
2758 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
2759 {
2760         static const struct ephy_info e_info_8168e_1[] = {
2761                 { 0x00, 0x0200, 0x0100 },
2762                 { 0x00, 0x0000, 0x0004 },
2763                 { 0x06, 0x0002, 0x0001 },
2764                 { 0x06, 0x0000, 0x0030 },
2765                 { 0x07, 0x0000, 0x2000 },
2766                 { 0x00, 0x0000, 0x0020 },
2767                 { 0x03, 0x5800, 0x2000 },
2768                 { 0x03, 0x0000, 0x0001 },
2769                 { 0x01, 0x0800, 0x1000 },
2770                 { 0x07, 0x0000, 0x4000 },
2771                 { 0x1e, 0x0000, 0x2000 },
2772                 { 0x19, 0xffff, 0xfe6c },
2773                 { 0x0a, 0x0000, 0x0040 }
2774         };
2775
2776         rtl_set_def_aspm_entry_latency(tp);
2777
2778         rtl_ephy_init(tp, e_info_8168e_1);
2779
2780         rtl_disable_clock_request(tp);
2781
2782         /* Reset tx FIFO pointer */
2783         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
2784         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
2785
2786         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
2787 }
2788
2789 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
2790 {
2791         static const struct ephy_info e_info_8168e_2[] = {
2792                 { 0x09, 0x0000, 0x0080 },
2793                 { 0x19, 0x0000, 0x0224 },
2794                 { 0x00, 0x0000, 0x0004 },
2795                 { 0x0c, 0x3df0, 0x0200 },
2796         };
2797
2798         rtl_set_def_aspm_entry_latency(tp);
2799
2800         rtl_ephy_init(tp, e_info_8168e_2);
2801
2802         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
2803         rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000);
2804         rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
2805         rtl_eri_set_bits(tp, 0x0d4, 0x1f00);
2806         rtl_eri_set_bits(tp, 0x1d0, BIT(1));
2807         rtl_reset_packet_filter(tp);
2808         rtl_eri_set_bits(tp, 0x1b0, BIT(4));
2809         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
2810         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060);
2811
2812         rtl_disable_clock_request(tp);
2813
2814         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
2815
2816         rtl8168_config_eee_mac(tp);
2817
2818         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
2819         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
2820         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
2821
2822         rtl_hw_aspm_clkreq_enable(tp, true);
2823 }
2824
2825 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
2826 {
2827         rtl_set_def_aspm_entry_latency(tp);
2828
2829         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
2830         rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000);
2831         rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
2832         rtl_reset_packet_filter(tp);
2833         rtl_eri_set_bits(tp, 0x1b0, BIT(4));
2834         rtl_eri_set_bits(tp, 0x1d0, BIT(4) | BIT(1));
2835         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
2836         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060);
2837
2838         rtl_disable_clock_request(tp);
2839
2840         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
2841         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
2842         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
2843         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
2844
2845         rtl8168_config_eee_mac(tp);
2846 }
2847
2848 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
2849 {
2850         static const struct ephy_info e_info_8168f_1[] = {
2851                 { 0x06, 0x00c0, 0x0020 },
2852                 { 0x08, 0x0001, 0x0002 },
2853                 { 0x09, 0x0000, 0x0080 },
2854                 { 0x19, 0x0000, 0x0224 },
2855                 { 0x00, 0x0000, 0x0008 },
2856                 { 0x0c, 0x3df0, 0x0200 },
2857         };
2858
2859         rtl_hw_start_8168f(tp);
2860
2861         rtl_ephy_init(tp, e_info_8168f_1);
2862
2863         rtl_eri_set_bits(tp, 0x0d4, 0x1f00);
2864 }
2865
2866 static void rtl_hw_start_8411(struct rtl8169_private *tp)
2867 {
2868         static const struct ephy_info e_info_8168f_1[] = {
2869                 { 0x06, 0x00c0, 0x0020 },
2870                 { 0x0f, 0xffff, 0x5200 },
2871                 { 0x19, 0x0000, 0x0224 },
2872                 { 0x00, 0x0000, 0x0008 },
2873                 { 0x0c, 0x3df0, 0x0200 },
2874         };
2875
2876         rtl_hw_start_8168f(tp);
2877         rtl_pcie_state_l2l3_disable(tp);
2878
2879         rtl_ephy_init(tp, e_info_8168f_1);
2880
2881         rtl_eri_set_bits(tp, 0x0d4, 0x0c00);
2882 }
2883
2884 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
2885 {
2886         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
2887         rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
2888
2889         rtl_set_def_aspm_entry_latency(tp);
2890
2891         rtl_reset_packet_filter(tp);
2892         rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f);
2893
2894         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
2895
2896         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
2897         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
2898         rtl_eri_set_bits(tp, 0x0d4, 0x1f80);
2899
2900         rtl8168_config_eee_mac(tp);
2901
2902         rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06);
2903         rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
2904
2905         rtl_pcie_state_l2l3_disable(tp);
2906 }
2907
2908 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
2909 {
2910         static const struct ephy_info e_info_8168g_1[] = {
2911                 { 0x00, 0x0008, 0x0000 },
2912                 { 0x0c, 0x3ff0, 0x0820 },
2913                 { 0x1e, 0x0000, 0x0001 },
2914                 { 0x19, 0x8000, 0x0000 }
2915         };
2916
2917         rtl_hw_start_8168g(tp);
2918
2919         /* disable aspm and clock request before access ephy */
2920         rtl_hw_aspm_clkreq_enable(tp, false);
2921         rtl_ephy_init(tp, e_info_8168g_1);
2922         rtl_hw_aspm_clkreq_enable(tp, true);
2923 }
2924
2925 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
2926 {
2927         static const struct ephy_info e_info_8168g_2[] = {
2928                 { 0x00, 0x0008, 0x0000 },
2929                 { 0x0c, 0x3ff0, 0x0820 },
2930                 { 0x19, 0xffff, 0x7c00 },
2931                 { 0x1e, 0xffff, 0x20eb },
2932                 { 0x0d, 0xffff, 0x1666 },
2933                 { 0x00, 0xffff, 0x10a3 },
2934                 { 0x06, 0xffff, 0xf050 },
2935                 { 0x04, 0x0000, 0x0010 },
2936                 { 0x1d, 0x4000, 0x0000 },
2937         };
2938
2939         rtl_hw_start_8168g(tp);
2940
2941         /* disable aspm and clock request before access ephy */
2942         rtl_hw_aspm_clkreq_enable(tp, false);
2943         rtl_ephy_init(tp, e_info_8168g_2);
2944 }
2945
2946 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
2947 {
2948         static const struct ephy_info e_info_8411_2[] = {
2949                 { 0x00, 0x0008, 0x0000 },
2950                 { 0x0c, 0x37d0, 0x0820 },
2951                 { 0x1e, 0x0000, 0x0001 },
2952                 { 0x19, 0x8021, 0x0000 },
2953                 { 0x1e, 0x0000, 0x2000 },
2954                 { 0x0d, 0x0100, 0x0200 },
2955                 { 0x00, 0x0000, 0x0080 },
2956                 { 0x06, 0x0000, 0x0010 },
2957                 { 0x04, 0x0000, 0x0010 },
2958                 { 0x1d, 0x0000, 0x4000 },
2959         };
2960
2961         rtl_hw_start_8168g(tp);
2962
2963         /* disable aspm and clock request before access ephy */
2964         rtl_hw_aspm_clkreq_enable(tp, false);
2965         rtl_ephy_init(tp, e_info_8411_2);
2966
2967         /* The following Realtek-provided magic fixes an issue with the RX unit
2968          * getting confused after the PHY having been powered-down.
2969          */
2970         r8168_mac_ocp_write(tp, 0xFC28, 0x0000);
2971         r8168_mac_ocp_write(tp, 0xFC2A, 0x0000);
2972         r8168_mac_ocp_write(tp, 0xFC2C, 0x0000);
2973         r8168_mac_ocp_write(tp, 0xFC2E, 0x0000);
2974         r8168_mac_ocp_write(tp, 0xFC30, 0x0000);
2975         r8168_mac_ocp_write(tp, 0xFC32, 0x0000);
2976         r8168_mac_ocp_write(tp, 0xFC34, 0x0000);
2977         r8168_mac_ocp_write(tp, 0xFC36, 0x0000);
2978         mdelay(3);
2979         r8168_mac_ocp_write(tp, 0xFC26, 0x0000);
2980
2981         r8168_mac_ocp_write(tp, 0xF800, 0xE008);
2982         r8168_mac_ocp_write(tp, 0xF802, 0xE00A);
2983         r8168_mac_ocp_write(tp, 0xF804, 0xE00C);
2984         r8168_mac_ocp_write(tp, 0xF806, 0xE00E);
2985         r8168_mac_ocp_write(tp, 0xF808, 0xE027);
2986         r8168_mac_ocp_write(tp, 0xF80A, 0xE04F);
2987         r8168_mac_ocp_write(tp, 0xF80C, 0xE05E);
2988         r8168_mac_ocp_write(tp, 0xF80E, 0xE065);
2989         r8168_mac_ocp_write(tp, 0xF810, 0xC602);
2990         r8168_mac_ocp_write(tp, 0xF812, 0xBE00);
2991         r8168_mac_ocp_write(tp, 0xF814, 0x0000);
2992         r8168_mac_ocp_write(tp, 0xF816, 0xC502);
2993         r8168_mac_ocp_write(tp, 0xF818, 0xBD00);
2994         r8168_mac_ocp_write(tp, 0xF81A, 0x074C);
2995         r8168_mac_ocp_write(tp, 0xF81C, 0xC302);
2996         r8168_mac_ocp_write(tp, 0xF81E, 0xBB00);
2997         r8168_mac_ocp_write(tp, 0xF820, 0x080A);
2998         r8168_mac_ocp_write(tp, 0xF822, 0x6420);
2999         r8168_mac_ocp_write(tp, 0xF824, 0x48C2);
3000         r8168_mac_ocp_write(tp, 0xF826, 0x8C20);
3001         r8168_mac_ocp_write(tp, 0xF828, 0xC516);
3002         r8168_mac_ocp_write(tp, 0xF82A, 0x64A4);
3003         r8168_mac_ocp_write(tp, 0xF82C, 0x49C0);
3004         r8168_mac_ocp_write(tp, 0xF82E, 0xF009);
3005         r8168_mac_ocp_write(tp, 0xF830, 0x74A2);
3006         r8168_mac_ocp_write(tp, 0xF832, 0x8CA5);
3007         r8168_mac_ocp_write(tp, 0xF834, 0x74A0);
3008         r8168_mac_ocp_write(tp, 0xF836, 0xC50E);
3009         r8168_mac_ocp_write(tp, 0xF838, 0x9CA2);
3010         r8168_mac_ocp_write(tp, 0xF83A, 0x1C11);
3011         r8168_mac_ocp_write(tp, 0xF83C, 0x9CA0);
3012         r8168_mac_ocp_write(tp, 0xF83E, 0xE006);
3013         r8168_mac_ocp_write(tp, 0xF840, 0x74F8);
3014         r8168_mac_ocp_write(tp, 0xF842, 0x48C4);
3015         r8168_mac_ocp_write(tp, 0xF844, 0x8CF8);
3016         r8168_mac_ocp_write(tp, 0xF846, 0xC404);
3017         r8168_mac_ocp_write(tp, 0xF848, 0xBC00);
3018         r8168_mac_ocp_write(tp, 0xF84A, 0xC403);
3019         r8168_mac_ocp_write(tp, 0xF84C, 0xBC00);
3020         r8168_mac_ocp_write(tp, 0xF84E, 0x0BF2);
3021         r8168_mac_ocp_write(tp, 0xF850, 0x0C0A);
3022         r8168_mac_ocp_write(tp, 0xF852, 0xE434);
3023         r8168_mac_ocp_write(tp, 0xF854, 0xD3C0);
3024         r8168_mac_ocp_write(tp, 0xF856, 0x49D9);
3025         r8168_mac_ocp_write(tp, 0xF858, 0xF01F);
3026         r8168_mac_ocp_write(tp, 0xF85A, 0xC526);
3027         r8168_mac_ocp_write(tp, 0xF85C, 0x64A5);
3028         r8168_mac_ocp_write(tp, 0xF85E, 0x1400);
3029         r8168_mac_ocp_write(tp, 0xF860, 0xF007);
3030         r8168_mac_ocp_write(tp, 0xF862, 0x0C01);
3031         r8168_mac_ocp_write(tp, 0xF864, 0x8CA5);
3032         r8168_mac_ocp_write(tp, 0xF866, 0x1C15);
3033         r8168_mac_ocp_write(tp, 0xF868, 0xC51B);
3034         r8168_mac_ocp_write(tp, 0xF86A, 0x9CA0);
3035         r8168_mac_ocp_write(tp, 0xF86C, 0xE013);
3036         r8168_mac_ocp_write(tp, 0xF86E, 0xC519);
3037         r8168_mac_ocp_write(tp, 0xF870, 0x74A0);
3038         r8168_mac_ocp_write(tp, 0xF872, 0x48C4);
3039         r8168_mac_ocp_write(tp, 0xF874, 0x8CA0);
3040         r8168_mac_ocp_write(tp, 0xF876, 0xC516);
3041         r8168_mac_ocp_write(tp, 0xF878, 0x74A4);
3042         r8168_mac_ocp_write(tp, 0xF87A, 0x48C8);
3043         r8168_mac_ocp_write(tp, 0xF87C, 0x48CA);
3044         r8168_mac_ocp_write(tp, 0xF87E, 0x9CA4);
3045         r8168_mac_ocp_write(tp, 0xF880, 0xC512);
3046         r8168_mac_ocp_write(tp, 0xF882, 0x1B00);
3047         r8168_mac_ocp_write(tp, 0xF884, 0x9BA0);
3048         r8168_mac_ocp_write(tp, 0xF886, 0x1B1C);
3049         r8168_mac_ocp_write(tp, 0xF888, 0x483F);
3050         r8168_mac_ocp_write(tp, 0xF88A, 0x9BA2);
3051         r8168_mac_ocp_write(tp, 0xF88C, 0x1B04);
3052         r8168_mac_ocp_write(tp, 0xF88E, 0xC508);
3053         r8168_mac_ocp_write(tp, 0xF890, 0x9BA0);
3054         r8168_mac_ocp_write(tp, 0xF892, 0xC505);
3055         r8168_mac_ocp_write(tp, 0xF894, 0xBD00);
3056         r8168_mac_ocp_write(tp, 0xF896, 0xC502);
3057         r8168_mac_ocp_write(tp, 0xF898, 0xBD00);
3058         r8168_mac_ocp_write(tp, 0xF89A, 0x0300);
3059         r8168_mac_ocp_write(tp, 0xF89C, 0x051E);
3060         r8168_mac_ocp_write(tp, 0xF89E, 0xE434);
3061         r8168_mac_ocp_write(tp, 0xF8A0, 0xE018);
3062         r8168_mac_ocp_write(tp, 0xF8A2, 0xE092);
3063         r8168_mac_ocp_write(tp, 0xF8A4, 0xDE20);
3064         r8168_mac_ocp_write(tp, 0xF8A6, 0xD3C0);
3065         r8168_mac_ocp_write(tp, 0xF8A8, 0xC50F);
3066         r8168_mac_ocp_write(tp, 0xF8AA, 0x76A4);
3067         r8168_mac_ocp_write(tp, 0xF8AC, 0x49E3);
3068         r8168_mac_ocp_write(tp, 0xF8AE, 0xF007);
3069         r8168_mac_ocp_write(tp, 0xF8B0, 0x49C0);
3070         r8168_mac_ocp_write(tp, 0xF8B2, 0xF103);
3071         r8168_mac_ocp_write(tp, 0xF8B4, 0xC607);
3072         r8168_mac_ocp_write(tp, 0xF8B6, 0xBE00);
3073         r8168_mac_ocp_write(tp, 0xF8B8, 0xC606);
3074         r8168_mac_ocp_write(tp, 0xF8BA, 0xBE00);
3075         r8168_mac_ocp_write(tp, 0xF8BC, 0xC602);
3076         r8168_mac_ocp_write(tp, 0xF8BE, 0xBE00);
3077         r8168_mac_ocp_write(tp, 0xF8C0, 0x0C4C);
3078         r8168_mac_ocp_write(tp, 0xF8C2, 0x0C28);
3079         r8168_mac_ocp_write(tp, 0xF8C4, 0x0C2C);
3080         r8168_mac_ocp_write(tp, 0xF8C6, 0xDC00);
3081         r8168_mac_ocp_write(tp, 0xF8C8, 0xC707);
3082         r8168_mac_ocp_write(tp, 0xF8CA, 0x1D00);
3083         r8168_mac_ocp_write(tp, 0xF8CC, 0x8DE2);
3084         r8168_mac_ocp_write(tp, 0xF8CE, 0x48C1);
3085         r8168_mac_ocp_write(tp, 0xF8D0, 0xC502);
3086         r8168_mac_ocp_write(tp, 0xF8D2, 0xBD00);
3087         r8168_mac_ocp_write(tp, 0xF8D4, 0x00AA);
3088         r8168_mac_ocp_write(tp, 0xF8D6, 0xE0C0);
3089         r8168_mac_ocp_write(tp, 0xF8D8, 0xC502);
3090         r8168_mac_ocp_write(tp, 0xF8DA, 0xBD00);
3091         r8168_mac_ocp_write(tp, 0xF8DC, 0x0132);
3092
3093         r8168_mac_ocp_write(tp, 0xFC26, 0x8000);
3094
3095         r8168_mac_ocp_write(tp, 0xFC2A, 0x0743);
3096         r8168_mac_ocp_write(tp, 0xFC2C, 0x0801);
3097         r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9);
3098         r8168_mac_ocp_write(tp, 0xFC30, 0x02FD);
3099         r8168_mac_ocp_write(tp, 0xFC32, 0x0C25);
3100         r8168_mac_ocp_write(tp, 0xFC34, 0x00A9);
3101         r8168_mac_ocp_write(tp, 0xFC36, 0x012D);
3102
3103         rtl_hw_aspm_clkreq_enable(tp, true);
3104 }
3105
3106 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
3107 {
3108         static const struct ephy_info e_info_8168h_1[] = {
3109                 { 0x1e, 0x0800, 0x0001 },
3110                 { 0x1d, 0x0000, 0x0800 },
3111                 { 0x05, 0xffff, 0x2089 },
3112                 { 0x06, 0xffff, 0x5881 },
3113                 { 0x04, 0xffff, 0x854a },
3114                 { 0x01, 0xffff, 0x068b }
3115         };
3116         int rg_saw_cnt;
3117
3118         /* disable aspm and clock request before access ephy */
3119         rtl_hw_aspm_clkreq_enable(tp, false);
3120         rtl_ephy_init(tp, e_info_8168h_1);
3121
3122         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3123         rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
3124
3125         rtl_set_def_aspm_entry_latency(tp);
3126
3127         rtl_reset_packet_filter(tp);
3128
3129         rtl_eri_set_bits(tp, 0xd4, 0x1f00);
3130         rtl_eri_set_bits(tp, 0xdc, 0x001c);
3131
3132         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3133
3134         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
3135
3136         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3137         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3138
3139         rtl8168_config_eee_mac(tp);
3140
3141         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3142         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3143
3144         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3145
3146         rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
3147
3148         rtl_pcie_state_l2l3_disable(tp);
3149
3150         rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff;
3151         if (rg_saw_cnt > 0) {
3152                 u16 sw_cnt_1ms_ini;
3153
3154                 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
3155                 sw_cnt_1ms_ini &= 0x0fff;
3156                 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);
3157         }
3158
3159         r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);
3160         r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008);
3161         r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f);
3162         r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);
3163
3164         r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
3165         r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
3166         r8168_mac_ocp_write(tp, 0xc094, 0x0000);
3167         r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
3168
3169         rtl_hw_aspm_clkreq_enable(tp, true);
3170 }
3171
3172 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
3173 {
3174         rtl8168ep_stop_cmac(tp);
3175
3176         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3177         rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
3178
3179         rtl_set_def_aspm_entry_latency(tp);
3180
3181         rtl_reset_packet_filter(tp);
3182
3183         rtl_eri_set_bits(tp, 0xd4, 0x1f80);
3184
3185         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3186
3187         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
3188
3189         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3190         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3191
3192         rtl8168_config_eee_mac(tp);
3193
3194         rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06);
3195
3196         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3197
3198         rtl_pcie_state_l2l3_disable(tp);
3199 }
3200
3201 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
3202 {
3203         static const struct ephy_info e_info_8168ep_1[] = {
3204                 { 0x00, 0xffff, 0x10ab },
3205                 { 0x06, 0xffff, 0xf030 },
3206                 { 0x08, 0xffff, 0x2006 },
3207                 { 0x0d, 0xffff, 0x1666 },
3208                 { 0x0c, 0x3ff0, 0x0000 }
3209         };
3210
3211         /* disable aspm and clock request before access ephy */
3212         rtl_hw_aspm_clkreq_enable(tp, false);
3213         rtl_ephy_init(tp, e_info_8168ep_1);
3214
3215         rtl_hw_start_8168ep(tp);
3216
3217         rtl_hw_aspm_clkreq_enable(tp, true);
3218 }
3219
3220 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
3221 {
3222         static const struct ephy_info e_info_8168ep_2[] = {
3223                 { 0x00, 0xffff, 0x10a3 },
3224                 { 0x19, 0xffff, 0xfc00 },
3225                 { 0x1e, 0xffff, 0x20ea }
3226         };
3227
3228         /* disable aspm and clock request before access ephy */
3229         rtl_hw_aspm_clkreq_enable(tp, false);
3230         rtl_ephy_init(tp, e_info_8168ep_2);
3231
3232         rtl_hw_start_8168ep(tp);
3233
3234         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3235         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3236
3237         rtl_hw_aspm_clkreq_enable(tp, true);
3238 }
3239
3240 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
3241 {
3242         static const struct ephy_info e_info_8168ep_3[] = {
3243                 { 0x00, 0x0000, 0x0080 },
3244                 { 0x0d, 0x0100, 0x0200 },
3245                 { 0x19, 0x8021, 0x0000 },
3246                 { 0x1e, 0x0000, 0x2000 },
3247         };
3248
3249         /* disable aspm and clock request before access ephy */
3250         rtl_hw_aspm_clkreq_enable(tp, false);
3251         rtl_ephy_init(tp, e_info_8168ep_3);
3252
3253         rtl_hw_start_8168ep(tp);
3254
3255         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3256         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3257
3258         r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271);
3259         r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
3260         r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);
3261
3262         rtl_hw_aspm_clkreq_enable(tp, true);
3263 }
3264
3265 static void rtl_hw_start_8117(struct rtl8169_private *tp)
3266 {
3267         static const struct ephy_info e_info_8117[] = {
3268                 { 0x19, 0x0040, 0x1100 },
3269                 { 0x59, 0x0040, 0x1100 },
3270         };
3271         int rg_saw_cnt;
3272
3273         rtl8168ep_stop_cmac(tp);
3274
3275         /* disable aspm and clock request before access ephy */
3276         rtl_hw_aspm_clkreq_enable(tp, false);
3277         rtl_ephy_init(tp, e_info_8117);
3278
3279         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3280         rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
3281
3282         rtl_set_def_aspm_entry_latency(tp);
3283
3284         rtl_reset_packet_filter(tp);
3285
3286         rtl_eri_set_bits(tp, 0xd4, 0x1f90);
3287
3288         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3289
3290         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
3291
3292         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3293         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3294
3295         rtl8168_config_eee_mac(tp);
3296
3297         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3298         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3299
3300         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3301
3302         rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
3303
3304         rtl_pcie_state_l2l3_disable(tp);
3305
3306         rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff;
3307         if (rg_saw_cnt > 0) {
3308                 u16 sw_cnt_1ms_ini;
3309
3310                 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff;
3311                 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);
3312         }
3313
3314         r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);
3315         r8168_mac_ocp_write(tp, 0xea80, 0x0003);
3316         r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009);
3317         r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);
3318
3319         r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
3320         r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
3321         r8168_mac_ocp_write(tp, 0xc094, 0x0000);
3322         r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
3323
3324         /* firmware is for MAC only */
3325         r8169_apply_firmware(tp);
3326
3327         rtl_hw_aspm_clkreq_enable(tp, true);
3328 }
3329
3330 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
3331 {
3332         static const struct ephy_info e_info_8102e_1[] = {
3333                 { 0x01, 0, 0x6e65 },
3334                 { 0x02, 0, 0x091f },
3335                 { 0x03, 0, 0xc2f9 },
3336                 { 0x06, 0, 0xafb5 },
3337                 { 0x07, 0, 0x0e00 },
3338                 { 0x19, 0, 0xec80 },
3339                 { 0x01, 0, 0x2e65 },
3340                 { 0x01, 0, 0x6e65 }
3341         };
3342         u8 cfg1;
3343
3344         rtl_set_def_aspm_entry_latency(tp);
3345
3346         RTL_W8(tp, DBG_REG, FIX_NAK_1);
3347
3348         RTL_W8(tp, Config1,
3349                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
3350         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3351
3352         cfg1 = RTL_R8(tp, Config1);
3353         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
3354                 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
3355
3356         rtl_ephy_init(tp, e_info_8102e_1);
3357 }
3358
3359 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
3360 {
3361         rtl_set_def_aspm_entry_latency(tp);
3362
3363         RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
3364         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3365 }
3366
3367 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
3368 {
3369         rtl_hw_start_8102e_2(tp);
3370
3371         rtl_ephy_write(tp, 0x03, 0xc2f9);
3372 }
3373
3374 static void rtl_hw_start_8401(struct rtl8169_private *tp)
3375 {
3376         static const struct ephy_info e_info_8401[] = {
3377                 { 0x01, 0xffff, 0x6fe5 },
3378                 { 0x03, 0xffff, 0x0599 },
3379                 { 0x06, 0xffff, 0xaf25 },
3380                 { 0x07, 0xffff, 0x8e68 },
3381         };
3382
3383         rtl_ephy_init(tp, e_info_8401);
3384         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3385 }
3386
3387 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
3388 {
3389         static const struct ephy_info e_info_8105e_1[] = {
3390                 { 0x07, 0, 0x4000 },
3391                 { 0x19, 0, 0x0200 },
3392                 { 0x19, 0, 0x0020 },
3393                 { 0x1e, 0, 0x2000 },
3394                 { 0x03, 0, 0x0001 },
3395                 { 0x19, 0, 0x0100 },
3396                 { 0x19, 0, 0x0004 },
3397                 { 0x0a, 0, 0x0020 }
3398         };
3399
3400         /* Force LAN exit from ASPM if Rx/Tx are not idle */
3401         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3402
3403         /* Disable Early Tally Counter */
3404         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
3405
3406         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
3407         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
3408
3409         rtl_ephy_init(tp, e_info_8105e_1);
3410
3411         rtl_pcie_state_l2l3_disable(tp);
3412 }
3413
3414 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
3415 {
3416         rtl_hw_start_8105e_1(tp);
3417         rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
3418 }
3419
3420 static void rtl_hw_start_8402(struct rtl8169_private *tp)
3421 {
3422         static const struct ephy_info e_info_8402[] = {
3423                 { 0x19, 0xffff, 0xff64 },
3424                 { 0x1e, 0, 0x4000 }
3425         };
3426
3427         rtl_set_def_aspm_entry_latency(tp);
3428
3429         /* Force LAN exit from ASPM if Rx/Tx are not idle */
3430         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3431
3432         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
3433
3434         rtl_ephy_init(tp, e_info_8402);
3435
3436         rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06);
3437         rtl_reset_packet_filter(tp);
3438         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3439         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3440         rtl_w0w1_eri(tp, 0x0d4, 0x0e00, 0xff00);
3441
3442         /* disable EEE */
3443         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3444
3445         rtl_pcie_state_l2l3_disable(tp);
3446 }
3447
3448 static void rtl_hw_start_8106(struct rtl8169_private *tp)
3449 {
3450         rtl_hw_aspm_clkreq_enable(tp, false);
3451
3452         /* Force LAN exit from ASPM if Rx/Tx are not idle */
3453         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3454
3455         RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
3456         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
3457         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3458
3459         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
3460
3461         /* disable EEE */
3462         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3463
3464         rtl_pcie_state_l2l3_disable(tp);
3465         rtl_hw_aspm_clkreq_enable(tp, true);
3466 }
3467
3468 DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond)
3469 {
3470         return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13);
3471 }
3472
3473 static void rtl_hw_start_8125_common(struct rtl8169_private *tp)
3474 {
3475         rtl_pcie_state_l2l3_disable(tp);
3476
3477         RTL_W16(tp, 0x382, 0x221b);
3478         RTL_W8(tp, 0x4500, 0);
3479         RTL_W16(tp, 0x4800, 0);
3480
3481         /* disable UPS */
3482         r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000);
3483
3484         RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10);
3485
3486         r8168_mac_ocp_write(tp, 0xc140, 0xffff);
3487         r8168_mac_ocp_write(tp, 0xc142, 0xffff);
3488
3489         r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9);
3490         r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
3491         r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);
3492
3493         /* disable new tx descriptor format */
3494         r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000);
3495
3496         if (tp->mac_version == RTL_GIGA_MAC_VER_63)
3497                 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200);
3498         else
3499                 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400);
3500
3501         if (tp->mac_version == RTL_GIGA_MAC_VER_63)
3502                 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0000);
3503         else
3504                 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020);
3505
3506         r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c);
3507         r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033);
3508         r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040);
3509         r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030);
3510         r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000);
3511         r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001);
3512         r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403);
3513         r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0068);
3514         r8168_mac_ocp_modify(tp, 0xc0ac, 0x0080, 0x1f00);
3515         r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f);
3516
3517         r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000);
3518         r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001);
3519         udelay(1);
3520         r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000);
3521         RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030);
3522
3523         r8168_mac_ocp_write(tp, 0xe098, 0xc302);
3524
3525         rtl_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10);
3526
3527         if (tp->mac_version == RTL_GIGA_MAC_VER_63)
3528                 rtl8125b_config_eee_mac(tp);
3529         else
3530                 rtl8125a_config_eee_mac(tp);
3531
3532         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
3533         udelay(10);
3534 }
3535
3536 static void rtl_hw_start_8125a_1(struct rtl8169_private *tp)
3537 {
3538         static const struct ephy_info e_info_8125a_1[] = {
3539                 { 0x01, 0xffff, 0xa812 },
3540                 { 0x09, 0xffff, 0x520c },
3541                 { 0x04, 0xffff, 0xd000 },
3542                 { 0x0d, 0xffff, 0xf702 },
3543                 { 0x0a, 0xffff, 0x8653 },
3544                 { 0x06, 0xffff, 0x001e },
3545                 { 0x08, 0xffff, 0x3595 },
3546                 { 0x20, 0xffff, 0x9455 },
3547                 { 0x21, 0xffff, 0x99ff },
3548                 { 0x02, 0xffff, 0x6046 },
3549                 { 0x29, 0xffff, 0xfe00 },
3550                 { 0x23, 0xffff, 0xab62 },
3551
3552                 { 0x41, 0xffff, 0xa80c },
3553                 { 0x49, 0xffff, 0x520c },
3554                 { 0x44, 0xffff, 0xd000 },
3555                 { 0x4d, 0xffff, 0xf702 },
3556                 { 0x4a, 0xffff, 0x8653 },
3557                 { 0x46, 0xffff, 0x001e },
3558                 { 0x48, 0xffff, 0x3595 },
3559                 { 0x60, 0xffff, 0x9455 },
3560                 { 0x61, 0xffff, 0x99ff },
3561                 { 0x42, 0xffff, 0x6046 },
3562                 { 0x69, 0xffff, 0xfe00 },
3563                 { 0x63, 0xffff, 0xab62 },
3564         };
3565
3566         rtl_set_def_aspm_entry_latency(tp);
3567
3568         /* disable aspm and clock request before access ephy */
3569         rtl_hw_aspm_clkreq_enable(tp, false);
3570         rtl_ephy_init(tp, e_info_8125a_1);
3571
3572         rtl_hw_start_8125_common(tp);
3573         rtl_hw_aspm_clkreq_enable(tp, true);
3574 }
3575
3576 static void rtl_hw_start_8125a_2(struct rtl8169_private *tp)
3577 {
3578         static const struct ephy_info e_info_8125a_2[] = {
3579                 { 0x04, 0xffff, 0xd000 },
3580                 { 0x0a, 0xffff, 0x8653 },
3581                 { 0x23, 0xffff, 0xab66 },
3582                 { 0x20, 0xffff, 0x9455 },
3583                 { 0x21, 0xffff, 0x99ff },
3584                 { 0x29, 0xffff, 0xfe04 },
3585
3586                 { 0x44, 0xffff, 0xd000 },
3587                 { 0x4a, 0xffff, 0x8653 },
3588                 { 0x63, 0xffff, 0xab66 },
3589                 { 0x60, 0xffff, 0x9455 },
3590                 { 0x61, 0xffff, 0x99ff },
3591                 { 0x69, 0xffff, 0xfe04 },
3592         };
3593
3594         rtl_set_def_aspm_entry_latency(tp);
3595
3596         /* disable aspm and clock request before access ephy */
3597         rtl_hw_aspm_clkreq_enable(tp, false);
3598         rtl_ephy_init(tp, e_info_8125a_2);
3599
3600         rtl_hw_start_8125_common(tp);
3601         rtl_hw_aspm_clkreq_enable(tp, true);
3602 }
3603
3604 static void rtl_hw_start_8125b(struct rtl8169_private *tp)
3605 {
3606         static const struct ephy_info e_info_8125b[] = {
3607                 { 0x0b, 0xffff, 0xa908 },
3608                 { 0x1e, 0xffff, 0x20eb },
3609                 { 0x4b, 0xffff, 0xa908 },
3610                 { 0x5e, 0xffff, 0x20eb },
3611                 { 0x22, 0x0030, 0x0020 },
3612                 { 0x62, 0x0030, 0x0020 },
3613         };
3614
3615         rtl_set_def_aspm_entry_latency(tp);
3616         rtl_hw_aspm_clkreq_enable(tp, false);
3617
3618         rtl_ephy_init(tp, e_info_8125b);
3619         rtl_hw_start_8125_common(tp);
3620
3621         rtl_hw_aspm_clkreq_enable(tp, true);
3622 }
3623
3624 static void rtl_hw_config(struct rtl8169_private *tp)
3625 {
3626         static const rtl_generic_fct hw_configs[] = {
3627                 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1,
3628                 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3,
3629                 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2,
3630                 [RTL_GIGA_MAC_VER_10] = NULL,
3631                 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168b,
3632                 [RTL_GIGA_MAC_VER_12] = rtl_hw_start_8168b,
3633                 [RTL_GIGA_MAC_VER_13] = NULL,
3634                 [RTL_GIGA_MAC_VER_14] = rtl_hw_start_8401,
3635                 [RTL_GIGA_MAC_VER_16] = NULL,
3636                 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b,
3637                 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1,
3638                 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1,
3639                 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2,
3640                 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_3,
3641                 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4,
3642                 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2,
3643                 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3,
3644                 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d,
3645                 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d,
3646                 [RTL_GIGA_MAC_VER_27] = rtl_hw_start_8168d,
3647                 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4,
3648                 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1,
3649                 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2,
3650                 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168d,
3651                 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1,
3652                 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1,
3653                 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2,
3654                 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1,
3655                 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1,
3656                 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402,
3657                 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411,
3658                 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106,
3659                 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1,
3660                 [RTL_GIGA_MAC_VER_41] = rtl_hw_start_8168g_1,
3661                 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2,
3662                 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2,
3663                 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2,
3664                 [RTL_GIGA_MAC_VER_45] = rtl_hw_start_8168h_1,
3665                 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1,
3666                 [RTL_GIGA_MAC_VER_47] = rtl_hw_start_8168h_1,
3667                 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1,
3668                 [RTL_GIGA_MAC_VER_49] = rtl_hw_start_8168ep_1,
3669                 [RTL_GIGA_MAC_VER_50] = rtl_hw_start_8168ep_2,
3670                 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3,
3671                 [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117,
3672                 [RTL_GIGA_MAC_VER_60] = rtl_hw_start_8125a_1,
3673                 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2,
3674                 [RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b,
3675         };
3676
3677         if (hw_configs[tp->mac_version])
3678                 hw_configs[tp->mac_version](tp);
3679 }
3680
3681 static void rtl_hw_start_8125(struct rtl8169_private *tp)
3682 {
3683         int i;
3684
3685         /* disable interrupt coalescing */
3686         for (i = 0xa00; i < 0xb00; i += 4)
3687                 RTL_W32(tp, i, 0);
3688
3689         rtl_hw_config(tp);
3690 }
3691
3692 static void rtl_hw_start_8168(struct rtl8169_private *tp)
3693 {
3694         if (rtl_is_8168evl_up(tp))
3695                 RTL_W8(tp, MaxTxPacketSize, EarlySize);
3696         else
3697                 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
3698
3699         rtl_hw_config(tp);
3700
3701         /* disable interrupt coalescing */
3702         RTL_W16(tp, IntrMitigate, 0x0000);
3703 }
3704
3705 static void rtl_hw_start_8169(struct rtl8169_private *tp)
3706 {
3707         RTL_W8(tp, EarlyTxThres, NoEarlyTx);
3708
3709         tp->cp_cmd |= PCIMulRW;
3710
3711         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3712             tp->mac_version == RTL_GIGA_MAC_VER_03)
3713                 tp->cp_cmd |= EnAnaPLL;
3714
3715         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
3716
3717         rtl8169_set_magic_reg(tp);
3718
3719         /* disable interrupt coalescing */
3720         RTL_W16(tp, IntrMitigate, 0x0000);
3721 }
3722
3723 static void rtl_hw_start(struct  rtl8169_private *tp)
3724 {
3725         rtl_unlock_config_regs(tp);
3726
3727         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
3728
3729         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3730                 rtl_hw_start_8169(tp);
3731         else if (rtl_is_8125(tp))
3732                 rtl_hw_start_8125(tp);
3733         else
3734                 rtl_hw_start_8168(tp);
3735
3736         rtl_set_rx_max_size(tp);
3737         rtl_set_rx_tx_desc_registers(tp);
3738         rtl_lock_config_regs(tp);
3739
3740         rtl_jumbo_config(tp);
3741
3742         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3743         rtl_pci_commit(tp);
3744
3745         RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
3746         rtl_init_rxcfg(tp);
3747         rtl_set_tx_config_registers(tp);
3748         rtl_set_rx_config_features(tp, tp->dev->features);
3749         rtl_set_rx_mode(tp->dev);
3750         rtl_irq_enable(tp);
3751 }
3752
3753 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
3754 {
3755         struct rtl8169_private *tp = netdev_priv(dev);
3756
3757         dev->mtu = new_mtu;
3758         netdev_update_features(dev);
3759         rtl_jumbo_config(tp);
3760
3761         switch (tp->mac_version) {
3762         case RTL_GIGA_MAC_VER_61:
3763         case RTL_GIGA_MAC_VER_63:
3764                 rtl8125_set_eee_txidle_timer(tp);
3765                 break;
3766         default:
3767                 break;
3768         }
3769
3770         return 0;
3771 }
3772
3773 static void rtl8169_mark_to_asic(struct RxDesc *desc)
3774 {
3775         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
3776
3777         desc->opts2 = 0;
3778         /* Force memory writes to complete before releasing descriptor */
3779         dma_wmb();
3780         WRITE_ONCE(desc->opts1, cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE));
3781 }
3782
3783 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
3784                                           struct RxDesc *desc)
3785 {
3786         struct device *d = tp_to_dev(tp);
3787         int node = dev_to_node(d);
3788         dma_addr_t mapping;
3789         struct page *data;
3790
3791         data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE));
3792         if (!data)
3793                 return NULL;
3794
3795         mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
3796         if (unlikely(dma_mapping_error(d, mapping))) {
3797                 netdev_err(tp->dev, "Failed to map RX DMA!\n");
3798                 __free_pages(data, get_order(R8169_RX_BUF_SIZE));
3799                 return NULL;
3800         }
3801
3802         desc->addr = cpu_to_le64(mapping);
3803         rtl8169_mark_to_asic(desc);
3804
3805         return data;
3806 }
3807
3808 static void rtl8169_rx_clear(struct rtl8169_private *tp)
3809 {
3810         int i;
3811
3812         for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) {
3813                 dma_unmap_page(tp_to_dev(tp),
3814                                le64_to_cpu(tp->RxDescArray[i].addr),
3815                                R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
3816                 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE));
3817                 tp->Rx_databuff[i] = NULL;
3818                 tp->RxDescArray[i].addr = 0;
3819                 tp->RxDescArray[i].opts1 = 0;
3820         }
3821 }
3822
3823 static int rtl8169_rx_fill(struct rtl8169_private *tp)
3824 {
3825         int i;
3826
3827         for (i = 0; i < NUM_RX_DESC; i++) {
3828                 struct page *data;
3829
3830                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
3831                 if (!data) {
3832                         rtl8169_rx_clear(tp);
3833                         return -ENOMEM;
3834                 }
3835                 tp->Rx_databuff[i] = data;
3836         }
3837
3838         /* mark as last descriptor in the ring */
3839         tp->RxDescArray[NUM_RX_DESC - 1].opts1 |= cpu_to_le32(RingEnd);
3840
3841         return 0;
3842 }
3843
3844 static int rtl8169_init_ring(struct rtl8169_private *tp)
3845 {
3846         rtl8169_init_ring_indexes(tp);
3847
3848         memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
3849         memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
3850
3851         return rtl8169_rx_fill(tp);
3852 }
3853
3854 static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int entry)
3855 {
3856         struct ring_info *tx_skb = tp->tx_skb + entry;
3857         struct TxDesc *desc = tp->TxDescArray + entry;
3858
3859         dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), tx_skb->len,
3860                          DMA_TO_DEVICE);
3861         memset(desc, 0, sizeof(*desc));
3862         memset(tx_skb, 0, sizeof(*tx_skb));
3863 }
3864
3865 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
3866                                    unsigned int n)
3867 {
3868         unsigned int i;
3869
3870         for (i = 0; i < n; i++) {
3871                 unsigned int entry = (start + i) % NUM_TX_DESC;
3872                 struct ring_info *tx_skb = tp->tx_skb + entry;
3873                 unsigned int len = tx_skb->len;
3874
3875                 if (len) {
3876                         struct sk_buff *skb = tx_skb->skb;
3877
3878                         rtl8169_unmap_tx_skb(tp, entry);
3879                         if (skb)
3880                                 dev_consume_skb_any(skb);
3881                 }
3882         }
3883 }
3884
3885 static void rtl8169_tx_clear(struct rtl8169_private *tp)
3886 {
3887         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
3888         netdev_reset_queue(tp->dev);
3889 }
3890
3891 static void rtl8169_cleanup(struct rtl8169_private *tp, bool going_down)
3892 {
3893         napi_disable(&tp->napi);
3894
3895         /* Give a racing hard_start_xmit a few cycles to complete. */
3896         synchronize_net();
3897
3898         /* Disable interrupts */
3899         rtl8169_irq_mask_and_ack(tp);
3900
3901         rtl_rx_close(tp);
3902
3903         if (going_down && tp->dev->wol_enabled)
3904                 goto no_reset;
3905
3906         switch (tp->mac_version) {
3907         case RTL_GIGA_MAC_VER_27:
3908         case RTL_GIGA_MAC_VER_28:
3909         case RTL_GIGA_MAC_VER_31:
3910                 rtl_loop_wait_low(tp, &rtl_npq_cond, 20, 2000);
3911                 break;
3912         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
3913                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
3914                 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
3915                 break;
3916         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
3917                 rtl_enable_rxdvgate(tp);
3918                 fsleep(2000);
3919                 break;
3920         default:
3921                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
3922                 fsleep(100);
3923                 break;
3924         }
3925
3926         rtl_hw_reset(tp);
3927 no_reset:
3928         rtl8169_tx_clear(tp);
3929         rtl8169_init_ring_indexes(tp);
3930 }
3931
3932 static void rtl_reset_work(struct rtl8169_private *tp)
3933 {
3934         int i;
3935
3936         netif_stop_queue(tp->dev);
3937
3938         rtl8169_cleanup(tp, false);
3939
3940         for (i = 0; i < NUM_RX_DESC; i++)
3941                 rtl8169_mark_to_asic(tp->RxDescArray + i);
3942
3943         napi_enable(&tp->napi);
3944         rtl_hw_start(tp);
3945 }
3946
3947 static void rtl8169_tx_timeout(struct net_device *dev, unsigned int txqueue)
3948 {
3949         struct rtl8169_private *tp = netdev_priv(dev);
3950
3951         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
3952 }
3953
3954 static int rtl8169_tx_map(struct rtl8169_private *tp, const u32 *opts, u32 len,
3955                           void *addr, unsigned int entry, bool desc_own)
3956 {
3957         struct TxDesc *txd = tp->TxDescArray + entry;
3958         struct device *d = tp_to_dev(tp);
3959         dma_addr_t mapping;
3960         u32 opts1;
3961         int ret;
3962
3963         mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
3964         ret = dma_mapping_error(d, mapping);
3965         if (unlikely(ret)) {
3966                 if (net_ratelimit())
3967                         netdev_err(tp->dev, "Failed to map TX data!\n");
3968                 return ret;
3969         }
3970
3971         txd->addr = cpu_to_le64(mapping);
3972         txd->opts2 = cpu_to_le32(opts[1]);
3973
3974         opts1 = opts[0] | len;
3975         if (entry == NUM_TX_DESC - 1)
3976                 opts1 |= RingEnd;
3977         if (desc_own)
3978                 opts1 |= DescOwn;
3979         txd->opts1 = cpu_to_le32(opts1);
3980
3981         tp->tx_skb[entry].len = len;
3982
3983         return 0;
3984 }
3985
3986 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
3987                               const u32 *opts, unsigned int entry)
3988 {
3989         struct skb_shared_info *info = skb_shinfo(skb);
3990         unsigned int cur_frag;
3991
3992         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
3993                 const skb_frag_t *frag = info->frags + cur_frag;
3994                 void *addr = skb_frag_address(frag);
3995                 u32 len = skb_frag_size(frag);
3996
3997                 entry = (entry + 1) % NUM_TX_DESC;
3998
3999                 if (unlikely(rtl8169_tx_map(tp, opts, len, addr, entry, true)))
4000                         goto err_out;
4001         }
4002
4003         return 0;
4004
4005 err_out:
4006         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
4007         return -EIO;
4008 }
4009
4010 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp)
4011 {
4012         switch (tp->mac_version) {
4013         case RTL_GIGA_MAC_VER_34:
4014         case RTL_GIGA_MAC_VER_60:
4015         case RTL_GIGA_MAC_VER_61:
4016         case RTL_GIGA_MAC_VER_63:
4017                 return true;
4018         default:
4019                 return false;
4020         }
4021 }
4022
4023 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts)
4024 {
4025         u32 mss = skb_shinfo(skb)->gso_size;
4026
4027         if (mss) {
4028                 opts[0] |= TD_LSO;
4029                 opts[0] |= mss << TD0_MSS_SHIFT;
4030         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4031                 const struct iphdr *ip = ip_hdr(skb);
4032
4033                 if (ip->protocol == IPPROTO_TCP)
4034                         opts[0] |= TD0_IP_CS | TD0_TCP_CS;
4035                 else if (ip->protocol == IPPROTO_UDP)
4036                         opts[0] |= TD0_IP_CS | TD0_UDP_CS;
4037                 else
4038                         WARN_ON_ONCE(1);
4039         }
4040 }
4041
4042 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
4043                                 struct sk_buff *skb, u32 *opts)
4044 {
4045         u32 transport_offset = (u32)skb_transport_offset(skb);
4046         struct skb_shared_info *shinfo = skb_shinfo(skb);
4047         u32 mss = shinfo->gso_size;
4048
4049         if (mss) {
4050                 if (shinfo->gso_type & SKB_GSO_TCPV4) {
4051                         opts[0] |= TD1_GTSENV4;
4052                 } else if (shinfo->gso_type & SKB_GSO_TCPV6) {
4053                         if (skb_cow_head(skb, 0))
4054                                 return false;
4055
4056                         tcp_v6_gso_csum_prep(skb);
4057                         opts[0] |= TD1_GTSENV6;
4058                 } else {
4059                         WARN_ON_ONCE(1);
4060                 }
4061
4062                 opts[0] |= transport_offset << GTTCPHO_SHIFT;
4063                 opts[1] |= mss << TD1_MSS_SHIFT;
4064         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4065                 u8 ip_protocol;
4066
4067                 switch (vlan_get_protocol(skb)) {
4068                 case htons(ETH_P_IP):
4069                         opts[1] |= TD1_IPv4_CS;
4070                         ip_protocol = ip_hdr(skb)->protocol;
4071                         break;
4072
4073                 case htons(ETH_P_IPV6):
4074                         opts[1] |= TD1_IPv6_CS;
4075                         ip_protocol = ipv6_hdr(skb)->nexthdr;
4076                         break;
4077
4078                 default:
4079                         ip_protocol = IPPROTO_RAW;
4080                         break;
4081                 }
4082
4083                 if (ip_protocol == IPPROTO_TCP)
4084                         opts[1] |= TD1_TCP_CS;
4085                 else if (ip_protocol == IPPROTO_UDP)
4086                         opts[1] |= TD1_UDP_CS;
4087                 else
4088                         WARN_ON_ONCE(1);
4089
4090                 opts[1] |= transport_offset << TCPHO_SHIFT;
4091         } else {
4092                 if (unlikely(skb->len < ETH_ZLEN && rtl_test_hw_pad_bug(tp)))
4093                         /* eth_skb_pad would free the skb on error */
4094                         return !__skb_put_padto(skb, ETH_ZLEN, false);
4095         }
4096
4097         return true;
4098 }
4099
4100 static bool rtl_tx_slots_avail(struct rtl8169_private *tp)
4101 {
4102         unsigned int slots_avail = READ_ONCE(tp->dirty_tx) + NUM_TX_DESC
4103                                         - READ_ONCE(tp->cur_tx);
4104
4105         /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
4106         return slots_avail > MAX_SKB_FRAGS;
4107 }
4108
4109 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */
4110 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
4111 {
4112         switch (tp->mac_version) {
4113         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
4114         case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
4115                 return false;
4116         default:
4117                 return true;
4118         }
4119 }
4120
4121 static void rtl8169_doorbell(struct rtl8169_private *tp)
4122 {
4123         if (rtl_is_8125(tp))
4124                 RTL_W16(tp, TxPoll_8125, BIT(0));
4125         else
4126                 RTL_W8(tp, TxPoll, NPQ);
4127 }
4128
4129 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4130                                       struct net_device *dev)
4131 {
4132         unsigned int frags = skb_shinfo(skb)->nr_frags;
4133         struct rtl8169_private *tp = netdev_priv(dev);
4134         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
4135         struct TxDesc *txd_first, *txd_last;
4136         bool stop_queue, door_bell;
4137         u32 opts[2];
4138
4139         if (unlikely(!rtl_tx_slots_avail(tp))) {
4140                 if (net_ratelimit())
4141                         netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
4142                 goto err_stop_0;
4143         }
4144
4145         opts[1] = rtl8169_tx_vlan_tag(skb);
4146         opts[0] = 0;
4147
4148         if (!rtl_chip_supports_csum_v2(tp))
4149                 rtl8169_tso_csum_v1(skb, opts);
4150         else if (!rtl8169_tso_csum_v2(tp, skb, opts))
4151                 goto err_dma_0;
4152
4153         if (unlikely(rtl8169_tx_map(tp, opts, skb_headlen(skb), skb->data,
4154                                     entry, false)))
4155                 goto err_dma_0;
4156
4157         txd_first = tp->TxDescArray + entry;
4158
4159         if (frags) {
4160                 if (rtl8169_xmit_frags(tp, skb, opts, entry))
4161                         goto err_dma_1;
4162                 entry = (entry + frags) % NUM_TX_DESC;
4163         }
4164
4165         txd_last = tp->TxDescArray + entry;
4166         txd_last->opts1 |= cpu_to_le32(LastFrag);
4167         tp->tx_skb[entry].skb = skb;
4168
4169         skb_tx_timestamp(skb);
4170
4171         /* Force memory writes to complete before releasing descriptor */
4172         dma_wmb();
4173
4174         door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more());
4175
4176         txd_first->opts1 |= cpu_to_le32(DescOwn | FirstFrag);
4177
4178         /* rtl_tx needs to see descriptor changes before updated tp->cur_tx */
4179         smp_wmb();
4180
4181         WRITE_ONCE(tp->cur_tx, tp->cur_tx + frags + 1);
4182
4183         stop_queue = !rtl_tx_slots_avail(tp);
4184         if (unlikely(stop_queue)) {
4185                 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
4186                  * not miss a ring update when it notices a stopped queue.
4187                  */
4188                 smp_wmb();
4189                 netif_stop_queue(dev);
4190                 /* Sync with rtl_tx:
4191                  * - publish queue status and cur_tx ring index (write barrier)
4192                  * - refresh dirty_tx ring index (read barrier).
4193                  * May the current thread have a pessimistic view of the ring
4194                  * status and forget to wake up queue, a racing rtl_tx thread
4195                  * can't.
4196                  */
4197                 smp_mb__after_atomic();
4198                 if (rtl_tx_slots_avail(tp))
4199                         netif_start_queue(dev);
4200                 door_bell = true;
4201         }
4202
4203         if (door_bell)
4204                 rtl8169_doorbell(tp);
4205
4206         return NETDEV_TX_OK;
4207
4208 err_dma_1:
4209         rtl8169_unmap_tx_skb(tp, entry);
4210 err_dma_0:
4211         dev_kfree_skb_any(skb);
4212         dev->stats.tx_dropped++;
4213         return NETDEV_TX_OK;
4214
4215 err_stop_0:
4216         netif_stop_queue(dev);
4217         dev->stats.tx_dropped++;
4218         return NETDEV_TX_BUSY;
4219 }
4220
4221 static unsigned int rtl_last_frag_len(struct sk_buff *skb)
4222 {
4223         struct skb_shared_info *info = skb_shinfo(skb);
4224         unsigned int nr_frags = info->nr_frags;
4225
4226         if (!nr_frags)
4227                 return UINT_MAX;
4228
4229         return skb_frag_size(info->frags + nr_frags - 1);
4230 }
4231
4232 /* Workaround for hw issues with TSO on RTL8168evl */
4233 static netdev_features_t rtl8168evl_fix_tso(struct sk_buff *skb,
4234                                             netdev_features_t features)
4235 {
4236         /* IPv4 header has options field */
4237         if (vlan_get_protocol(skb) == htons(ETH_P_IP) &&
4238             ip_hdrlen(skb) > sizeof(struct iphdr))
4239                 features &= ~NETIF_F_ALL_TSO;
4240
4241         /* IPv4 TCP header has options field */
4242         else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4 &&
4243                  tcp_hdrlen(skb) > sizeof(struct tcphdr))
4244                 features &= ~NETIF_F_ALL_TSO;
4245
4246         else if (rtl_last_frag_len(skb) <= 6)
4247                 features &= ~NETIF_F_ALL_TSO;
4248
4249         return features;
4250 }
4251
4252 static netdev_features_t rtl8169_features_check(struct sk_buff *skb,
4253                                                 struct net_device *dev,
4254                                                 netdev_features_t features)
4255 {
4256         int transport_offset = skb_transport_offset(skb);
4257         struct rtl8169_private *tp = netdev_priv(dev);
4258
4259         if (skb_is_gso(skb)) {
4260                 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4261                         features = rtl8168evl_fix_tso(skb, features);
4262
4263                 if (transport_offset > GTTCPHO_MAX &&
4264                     rtl_chip_supports_csum_v2(tp))
4265                         features &= ~NETIF_F_ALL_TSO;
4266         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4267                 /* work around hw bug on some chip versions */
4268                 if (skb->len < ETH_ZLEN)
4269                         features &= ~NETIF_F_CSUM_MASK;
4270
4271                 if (transport_offset > TCPHO_MAX &&
4272                     rtl_chip_supports_csum_v2(tp))
4273                         features &= ~NETIF_F_CSUM_MASK;
4274         }
4275
4276         return vlan_features_check(skb, features);
4277 }
4278
4279 static void rtl8169_pcierr_interrupt(struct net_device *dev)
4280 {
4281         struct rtl8169_private *tp = netdev_priv(dev);
4282         struct pci_dev *pdev = tp->pci_dev;
4283         int pci_status_errs;
4284         u16 pci_cmd;
4285
4286         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4287
4288         pci_status_errs = pci_status_get_and_clear_errors(pdev);
4289
4290         if (net_ratelimit())
4291                 netdev_err(dev, "PCI error (cmd = 0x%04x, status_errs = 0x%04x)\n",
4292                            pci_cmd, pci_status_errs);
4293         /*
4294          * The recovery sequence below admits a very elaborated explanation:
4295          * - it seems to work;
4296          * - I did not see what else could be done;
4297          * - it makes iop3xx happy.
4298          *
4299          * Feel free to adjust to your needs.
4300          */
4301         if (pdev->broken_parity_status)
4302                 pci_cmd &= ~PCI_COMMAND_PARITY;
4303         else
4304                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
4305
4306         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
4307
4308         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
4309 }
4310
4311 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp,
4312                    int budget)
4313 {
4314         unsigned int dirty_tx, bytes_compl = 0, pkts_compl = 0;
4315         struct sk_buff *skb;
4316
4317         dirty_tx = tp->dirty_tx;
4318
4319         while (READ_ONCE(tp->cur_tx) != dirty_tx) {
4320                 unsigned int entry = dirty_tx % NUM_TX_DESC;
4321                 u32 status;
4322
4323                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
4324                 if (status & DescOwn)
4325                         break;
4326
4327                 skb = tp->tx_skb[entry].skb;
4328                 rtl8169_unmap_tx_skb(tp, entry);
4329
4330                 if (skb) {
4331                         pkts_compl++;
4332                         bytes_compl += skb->len;
4333                         napi_consume_skb(skb, budget);
4334                 }
4335                 dirty_tx++;
4336         }
4337
4338         if (tp->dirty_tx != dirty_tx) {
4339                 netdev_completed_queue(dev, pkts_compl, bytes_compl);
4340                 dev_sw_netstats_tx_add(dev, pkts_compl, bytes_compl);
4341
4342                 /* Sync with rtl8169_start_xmit:
4343                  * - publish dirty_tx ring index (write barrier)
4344                  * - refresh cur_tx ring index and queue status (read barrier)
4345                  * May the current thread miss the stopped queue condition,
4346                  * a racing xmit thread can only have a right view of the
4347                  * ring status.
4348                  */
4349                 smp_store_mb(tp->dirty_tx, dirty_tx);
4350                 if (netif_queue_stopped(dev) && rtl_tx_slots_avail(tp))
4351                         netif_wake_queue(dev);
4352                 /*
4353                  * 8168 hack: TxPoll requests are lost when the Tx packets are
4354                  * too close. Let's kick an extra TxPoll request when a burst
4355                  * of start_xmit activity is detected (if it is not detected,
4356                  * it is slow enough). -- FR
4357                  * If skb is NULL then we come here again once a tx irq is
4358                  * triggered after the last fragment is marked transmitted.
4359                  */
4360                 if (tp->cur_tx != dirty_tx && skb)
4361                         rtl8169_doorbell(tp);
4362         }
4363 }
4364
4365 static inline int rtl8169_fragmented_frame(u32 status)
4366 {
4367         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4368 }
4369
4370 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
4371 {
4372         u32 status = opts1 & (RxProtoMask | RxCSFailMask);
4373
4374         if (status == RxProtoTCP || status == RxProtoUDP)
4375                 skb->ip_summed = CHECKSUM_UNNECESSARY;
4376         else
4377                 skb_checksum_none_assert(skb);
4378 }
4379
4380 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, int budget)
4381 {
4382         struct device *d = tp_to_dev(tp);
4383         int count;
4384
4385         for (count = 0; count < budget; count++, tp->cur_rx++) {
4386                 unsigned int pkt_size, entry = tp->cur_rx % NUM_RX_DESC;
4387                 struct RxDesc *desc = tp->RxDescArray + entry;
4388                 struct sk_buff *skb;
4389                 const void *rx_buf;
4390                 dma_addr_t addr;
4391                 u32 status;
4392
4393                 status = le32_to_cpu(desc->opts1);
4394                 if (status & DescOwn)
4395                         break;
4396
4397                 /* This barrier is needed to keep us from reading
4398                  * any other fields out of the Rx descriptor until
4399                  * we know the status of DescOwn
4400                  */
4401                 dma_rmb();
4402
4403                 if (unlikely(status & RxRES)) {
4404                         if (net_ratelimit())
4405                                 netdev_warn(dev, "Rx ERROR. status = %08x\n",
4406                                             status);
4407                         dev->stats.rx_errors++;
4408                         if (status & (RxRWT | RxRUNT))
4409                                 dev->stats.rx_length_errors++;
4410                         if (status & RxCRC)
4411                                 dev->stats.rx_crc_errors++;
4412
4413                         if (!(dev->features & NETIF_F_RXALL))
4414                                 goto release_descriptor;
4415                         else if (status & RxRWT || !(status & (RxRUNT | RxCRC)))
4416                                 goto release_descriptor;
4417                 }
4418
4419                 pkt_size = status & GENMASK(13, 0);
4420                 if (likely(!(dev->features & NETIF_F_RXFCS)))
4421                         pkt_size -= ETH_FCS_LEN;
4422
4423                 /* The driver does not support incoming fragmented frames.
4424                  * They are seen as a symptom of over-mtu sized frames.
4425                  */
4426                 if (unlikely(rtl8169_fragmented_frame(status))) {
4427                         dev->stats.rx_dropped++;
4428                         dev->stats.rx_length_errors++;
4429                         goto release_descriptor;
4430                 }
4431
4432                 skb = napi_alloc_skb(&tp->napi, pkt_size);
4433                 if (unlikely(!skb)) {
4434                         dev->stats.rx_dropped++;
4435                         goto release_descriptor;
4436                 }
4437
4438                 addr = le64_to_cpu(desc->addr);
4439                 rx_buf = page_address(tp->Rx_databuff[entry]);
4440
4441                 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
4442                 prefetch(rx_buf);
4443                 skb_copy_to_linear_data(skb, rx_buf, pkt_size);
4444                 skb->tail += pkt_size;
4445                 skb->len = pkt_size;
4446                 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
4447
4448                 rtl8169_rx_csum(skb, status);
4449                 skb->protocol = eth_type_trans(skb, dev);
4450
4451                 rtl8169_rx_vlan_tag(desc, skb);
4452
4453                 if (skb->pkt_type == PACKET_MULTICAST)
4454                         dev->stats.multicast++;
4455
4456                 napi_gro_receive(&tp->napi, skb);
4457
4458                 dev_sw_netstats_rx_add(dev, pkt_size);
4459 release_descriptor:
4460                 rtl8169_mark_to_asic(desc);
4461         }
4462
4463         return count;
4464 }
4465
4466 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
4467 {
4468         struct rtl8169_private *tp = dev_instance;
4469         u32 status = rtl_get_events(tp);
4470
4471         if ((status & 0xffff) == 0xffff || !(status & tp->irq_mask))
4472                 return IRQ_NONE;
4473
4474         if (unlikely(status & SYSErr)) {
4475                 rtl8169_pcierr_interrupt(tp->dev);
4476                 goto out;
4477         }
4478
4479         if (status & LinkChg)
4480                 phy_mac_interrupt(tp->phydev);
4481
4482         if (unlikely(status & RxFIFOOver &&
4483             tp->mac_version == RTL_GIGA_MAC_VER_11)) {
4484                 netif_stop_queue(tp->dev);
4485                 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
4486         }
4487
4488         rtl_irq_disable(tp);
4489         napi_schedule(&tp->napi);
4490 out:
4491         rtl_ack_events(tp, status);
4492
4493         return IRQ_HANDLED;
4494 }
4495
4496 static void rtl_task(struct work_struct *work)
4497 {
4498         struct rtl8169_private *tp =
4499                 container_of(work, struct rtl8169_private, wk.work);
4500
4501         rtnl_lock();
4502
4503         if (!netif_running(tp->dev) ||
4504             !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
4505                 goto out_unlock;
4506
4507         if (test_and_clear_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags)) {
4508                 rtl_reset_work(tp);
4509                 netif_wake_queue(tp->dev);
4510         }
4511 out_unlock:
4512         rtnl_unlock();
4513 }
4514
4515 static int rtl8169_poll(struct napi_struct *napi, int budget)
4516 {
4517         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
4518         struct net_device *dev = tp->dev;
4519         int work_done;
4520
4521         work_done = rtl_rx(dev, tp, budget);
4522
4523         rtl_tx(dev, tp, budget);
4524
4525         if (work_done < budget && napi_complete_done(napi, work_done))
4526                 rtl_irq_enable(tp);
4527
4528         return work_done;
4529 }
4530
4531 static void r8169_phylink_handler(struct net_device *ndev)
4532 {
4533         struct rtl8169_private *tp = netdev_priv(ndev);
4534
4535         if (netif_carrier_ok(ndev)) {
4536                 rtl_link_chg_patch(tp);
4537                 pm_request_resume(&tp->pci_dev->dev);
4538         } else {
4539                 pm_runtime_idle(&tp->pci_dev->dev);
4540         }
4541
4542         if (net_ratelimit())
4543                 phy_print_status(tp->phydev);
4544 }
4545
4546 static int r8169_phy_connect(struct rtl8169_private *tp)
4547 {
4548         struct phy_device *phydev = tp->phydev;
4549         phy_interface_t phy_mode;
4550         int ret;
4551
4552         phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
4553                    PHY_INTERFACE_MODE_MII;
4554
4555         ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
4556                                  phy_mode);
4557         if (ret)
4558                 return ret;
4559
4560         if (!tp->supports_gmii)
4561                 phy_set_max_speed(phydev, SPEED_100);
4562
4563         phy_support_asym_pause(phydev);
4564
4565         phy_attached_info(phydev);
4566
4567         return 0;
4568 }
4569
4570 static void rtl8169_down(struct rtl8169_private *tp)
4571 {
4572         /* Clear all task flags */
4573         bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
4574
4575         phy_stop(tp->phydev);
4576
4577         rtl8169_update_counters(tp);
4578
4579         rtl8169_cleanup(tp, true);
4580
4581         rtl_prepare_power_down(tp);
4582 }
4583
4584 static void rtl8169_up(struct rtl8169_private *tp)
4585 {
4586         phy_resume(tp->phydev);
4587         rtl8169_init_phy(tp);
4588         napi_enable(&tp->napi);
4589         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
4590         rtl_reset_work(tp);
4591
4592         phy_start(tp->phydev);
4593 }
4594
4595 static int rtl8169_close(struct net_device *dev)
4596 {
4597         struct rtl8169_private *tp = netdev_priv(dev);
4598         struct pci_dev *pdev = tp->pci_dev;
4599
4600         pm_runtime_get_sync(&pdev->dev);
4601
4602         netif_stop_queue(dev);
4603         rtl8169_down(tp);
4604         rtl8169_rx_clear(tp);
4605
4606         cancel_work_sync(&tp->wk.work);
4607
4608         phy_disconnect(tp->phydev);
4609
4610         free_irq(pci_irq_vector(pdev, 0), tp);
4611
4612         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4613                           tp->RxPhyAddr);
4614         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4615                           tp->TxPhyAddr);
4616         tp->TxDescArray = NULL;
4617         tp->RxDescArray = NULL;
4618
4619         pm_runtime_put_sync(&pdev->dev);
4620
4621         return 0;
4622 }
4623
4624 #ifdef CONFIG_NET_POLL_CONTROLLER
4625 static void rtl8169_netpoll(struct net_device *dev)
4626 {
4627         struct rtl8169_private *tp = netdev_priv(dev);
4628
4629         rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp);
4630 }
4631 #endif
4632
4633 static int rtl_open(struct net_device *dev)
4634 {
4635         struct rtl8169_private *tp = netdev_priv(dev);
4636         struct pci_dev *pdev = tp->pci_dev;
4637         unsigned long irqflags;
4638         int retval = -ENOMEM;
4639
4640         pm_runtime_get_sync(&pdev->dev);
4641
4642         /*
4643          * Rx and Tx descriptors needs 256 bytes alignment.
4644          * dma_alloc_coherent provides more.
4645          */
4646         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
4647                                              &tp->TxPhyAddr, GFP_KERNEL);
4648         if (!tp->TxDescArray)
4649                 goto out;
4650
4651         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
4652                                              &tp->RxPhyAddr, GFP_KERNEL);
4653         if (!tp->RxDescArray)
4654                 goto err_free_tx_0;
4655
4656         retval = rtl8169_init_ring(tp);
4657         if (retval < 0)
4658                 goto err_free_rx_1;
4659
4660         rtl_request_firmware(tp);
4661
4662         irqflags = pci_dev_msi_enabled(pdev) ? IRQF_NO_THREAD : IRQF_SHARED;
4663         retval = request_irq(pci_irq_vector(pdev, 0), rtl8169_interrupt,
4664                              irqflags, dev->name, tp);
4665         if (retval < 0)
4666                 goto err_release_fw_2;
4667
4668         retval = r8169_phy_connect(tp);
4669         if (retval)
4670                 goto err_free_irq;
4671
4672         rtl8169_up(tp);
4673         rtl8169_init_counter_offsets(tp);
4674         netif_start_queue(dev);
4675 out:
4676         pm_runtime_put_sync(&pdev->dev);
4677
4678         return retval;
4679
4680 err_free_irq:
4681         free_irq(pci_irq_vector(pdev, 0), tp);
4682 err_release_fw_2:
4683         rtl_release_firmware(tp);
4684         rtl8169_rx_clear(tp);
4685 err_free_rx_1:
4686         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4687                           tp->RxPhyAddr);
4688         tp->RxDescArray = NULL;
4689 err_free_tx_0:
4690         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4691                           tp->TxPhyAddr);
4692         tp->TxDescArray = NULL;
4693         goto out;
4694 }
4695
4696 static void
4697 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
4698 {
4699         struct rtl8169_private *tp = netdev_priv(dev);
4700         struct pci_dev *pdev = tp->pci_dev;
4701         struct rtl8169_counters *counters = tp->counters;
4702
4703         pm_runtime_get_noresume(&pdev->dev);
4704
4705         netdev_stats_to_stats64(stats, &dev->stats);
4706         dev_fetch_sw_netstats(stats, dev->tstats);
4707
4708         /*
4709          * Fetch additional counter values missing in stats collected by driver
4710          * from tally counters.
4711          */
4712         if (pm_runtime_active(&pdev->dev))
4713                 rtl8169_update_counters(tp);
4714
4715         /*
4716          * Subtract values fetched during initalization.
4717          * See rtl8169_init_counter_offsets for a description why we do that.
4718          */
4719         stats->tx_errors = le64_to_cpu(counters->tx_errors) -
4720                 le64_to_cpu(tp->tc_offset.tx_errors);
4721         stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
4722                 le32_to_cpu(tp->tc_offset.tx_multi_collision);
4723         stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
4724                 le16_to_cpu(tp->tc_offset.tx_aborted);
4725         stats->rx_missed_errors = le16_to_cpu(counters->rx_missed) -
4726                 le16_to_cpu(tp->tc_offset.rx_missed);
4727
4728         pm_runtime_put_noidle(&pdev->dev);
4729 }
4730
4731 static void rtl8169_net_suspend(struct rtl8169_private *tp)
4732 {
4733         netif_device_detach(tp->dev);
4734
4735         if (netif_running(tp->dev))
4736                 rtl8169_down(tp);
4737 }
4738
4739 #ifdef CONFIG_PM
4740
4741 static int rtl8169_net_resume(struct rtl8169_private *tp)
4742 {
4743         rtl_rar_set(tp, tp->dev->dev_addr);
4744
4745         if (tp->TxDescArray)
4746                 rtl8169_up(tp);
4747
4748         netif_device_attach(tp->dev);
4749
4750         return 0;
4751 }
4752
4753 static int __maybe_unused rtl8169_suspend(struct device *device)
4754 {
4755         struct rtl8169_private *tp = dev_get_drvdata(device);
4756
4757         rtnl_lock();
4758         rtl8169_net_suspend(tp);
4759         if (!device_may_wakeup(tp_to_dev(tp)))
4760                 clk_disable_unprepare(tp->clk);
4761         rtnl_unlock();
4762
4763         return 0;
4764 }
4765
4766 static int __maybe_unused rtl8169_resume(struct device *device)
4767 {
4768         struct rtl8169_private *tp = dev_get_drvdata(device);
4769
4770         if (!device_may_wakeup(tp_to_dev(tp)))
4771                 clk_prepare_enable(tp->clk);
4772
4773         /* Reportedly at least Asus X453MA truncates packets otherwise */
4774         if (tp->mac_version == RTL_GIGA_MAC_VER_37)
4775                 rtl_init_rxcfg(tp);
4776
4777         return rtl8169_net_resume(tp);
4778 }
4779
4780 static int rtl8169_runtime_suspend(struct device *device)
4781 {
4782         struct rtl8169_private *tp = dev_get_drvdata(device);
4783
4784         if (!tp->TxDescArray) {
4785                 netif_device_detach(tp->dev);
4786                 return 0;
4787         }
4788
4789         rtnl_lock();
4790         __rtl8169_set_wol(tp, WAKE_PHY);
4791         rtl8169_net_suspend(tp);
4792         rtnl_unlock();
4793
4794         return 0;
4795 }
4796
4797 static int rtl8169_runtime_resume(struct device *device)
4798 {
4799         struct rtl8169_private *tp = dev_get_drvdata(device);
4800
4801         __rtl8169_set_wol(tp, tp->saved_wolopts);
4802
4803         return rtl8169_net_resume(tp);
4804 }
4805
4806 static int rtl8169_runtime_idle(struct device *device)
4807 {
4808         struct rtl8169_private *tp = dev_get_drvdata(device);
4809
4810         if (!netif_running(tp->dev) || !netif_carrier_ok(tp->dev))
4811                 pm_schedule_suspend(device, 10000);
4812
4813         return -EBUSY;
4814 }
4815
4816 static const struct dev_pm_ops rtl8169_pm_ops = {
4817         SET_SYSTEM_SLEEP_PM_OPS(rtl8169_suspend, rtl8169_resume)
4818         SET_RUNTIME_PM_OPS(rtl8169_runtime_suspend, rtl8169_runtime_resume,
4819                            rtl8169_runtime_idle)
4820 };
4821
4822 #endif /* CONFIG_PM */
4823
4824 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
4825 {
4826         /* WoL fails with 8168b when the receiver is disabled. */
4827         switch (tp->mac_version) {
4828         case RTL_GIGA_MAC_VER_11:
4829         case RTL_GIGA_MAC_VER_12:
4830         case RTL_GIGA_MAC_VER_17:
4831                 pci_clear_master(tp->pci_dev);
4832
4833                 RTL_W8(tp, ChipCmd, CmdRxEnb);
4834                 rtl_pci_commit(tp);
4835                 break;
4836         default:
4837                 break;
4838         }
4839 }
4840
4841 static void rtl_shutdown(struct pci_dev *pdev)
4842 {
4843         struct rtl8169_private *tp = pci_get_drvdata(pdev);
4844
4845         rtnl_lock();
4846         rtl8169_net_suspend(tp);
4847         rtnl_unlock();
4848
4849         /* Restore original MAC address */
4850         rtl_rar_set(tp, tp->dev->perm_addr);
4851
4852         if (system_state == SYSTEM_POWER_OFF) {
4853                 if (tp->saved_wolopts) {
4854                         rtl_wol_enable_rx(tp);
4855                         rtl_wol_shutdown_quirk(tp);
4856                 }
4857
4858                 pci_wake_from_d3(pdev, tp->saved_wolopts);
4859                 pci_set_power_state(pdev, PCI_D3hot);
4860         }
4861 }
4862
4863 static void rtl_remove_one(struct pci_dev *pdev)
4864 {
4865         struct rtl8169_private *tp = pci_get_drvdata(pdev);
4866
4867         if (pci_dev_run_wake(pdev))
4868                 pm_runtime_get_noresume(&pdev->dev);
4869
4870         unregister_netdev(tp->dev);
4871
4872         if (tp->dash_type != RTL_DASH_NONE)
4873                 rtl8168_driver_stop(tp);
4874
4875         rtl_release_firmware(tp);
4876
4877         /* restore original MAC address */
4878         rtl_rar_set(tp, tp->dev->perm_addr);
4879 }
4880
4881 static const struct net_device_ops rtl_netdev_ops = {
4882         .ndo_open               = rtl_open,
4883         .ndo_stop               = rtl8169_close,
4884         .ndo_get_stats64        = rtl8169_get_stats64,
4885         .ndo_start_xmit         = rtl8169_start_xmit,
4886         .ndo_features_check     = rtl8169_features_check,
4887         .ndo_tx_timeout         = rtl8169_tx_timeout,
4888         .ndo_validate_addr      = eth_validate_addr,
4889         .ndo_change_mtu         = rtl8169_change_mtu,
4890         .ndo_fix_features       = rtl8169_fix_features,
4891         .ndo_set_features       = rtl8169_set_features,
4892         .ndo_set_mac_address    = rtl_set_mac_address,
4893         .ndo_do_ioctl           = phy_do_ioctl_running,
4894         .ndo_set_rx_mode        = rtl_set_rx_mode,
4895 #ifdef CONFIG_NET_POLL_CONTROLLER
4896         .ndo_poll_controller    = rtl8169_netpoll,
4897 #endif
4898
4899 };
4900
4901 static void rtl_set_irq_mask(struct rtl8169_private *tp)
4902 {
4903         tp->irq_mask = RxOK | RxErr | TxOK | TxErr | LinkChg;
4904
4905         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
4906                 tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver;
4907         else if (tp->mac_version == RTL_GIGA_MAC_VER_11)
4908                 /* special workaround needed */
4909                 tp->irq_mask |= RxFIFOOver;
4910         else
4911                 tp->irq_mask |= RxOverflow;
4912 }
4913
4914 static int rtl_alloc_irq(struct rtl8169_private *tp)
4915 {
4916         unsigned int flags;
4917
4918         switch (tp->mac_version) {
4919         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
4920                 rtl_unlock_config_regs(tp);
4921                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
4922                 rtl_lock_config_regs(tp);
4923                 fallthrough;
4924         case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_17:
4925                 flags = PCI_IRQ_LEGACY;
4926                 break;
4927         default:
4928                 flags = PCI_IRQ_ALL_TYPES;
4929                 break;
4930         }
4931
4932         return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
4933 }
4934
4935 static void rtl_read_mac_address(struct rtl8169_private *tp,
4936                                  u8 mac_addr[ETH_ALEN])
4937 {
4938         /* Get MAC address */
4939         if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) {
4940                 u32 value;
4941
4942                 value = rtl_eri_read(tp, 0xe0);
4943                 put_unaligned_le32(value, mac_addr);
4944                 value = rtl_eri_read(tp, 0xe4);
4945                 put_unaligned_le16(value, mac_addr + 4);
4946         } else if (rtl_is_8125(tp)) {
4947                 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP);
4948         }
4949 }
4950
4951 DECLARE_RTL_COND(rtl_link_list_ready_cond)
4952 {
4953         return RTL_R8(tp, MCU) & LINK_LIST_RDY;
4954 }
4955
4956 static void r8168g_wait_ll_share_fifo_ready(struct rtl8169_private *tp)
4957 {
4958         rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42);
4959 }
4960
4961 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
4962 {
4963         struct rtl8169_private *tp = mii_bus->priv;
4964
4965         if (phyaddr > 0)
4966                 return -ENODEV;
4967
4968         return rtl_readphy(tp, phyreg);
4969 }
4970
4971 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
4972                                 int phyreg, u16 val)
4973 {
4974         struct rtl8169_private *tp = mii_bus->priv;
4975
4976         if (phyaddr > 0)
4977                 return -ENODEV;
4978
4979         rtl_writephy(tp, phyreg, val);
4980
4981         return 0;
4982 }
4983
4984 static int r8169_mdio_register(struct rtl8169_private *tp)
4985 {
4986         struct pci_dev *pdev = tp->pci_dev;
4987         struct mii_bus *new_bus;
4988         int ret;
4989
4990         new_bus = devm_mdiobus_alloc(&pdev->dev);
4991         if (!new_bus)
4992                 return -ENOMEM;
4993
4994         new_bus->name = "r8169";
4995         new_bus->priv = tp;
4996         new_bus->parent = &pdev->dev;
4997         new_bus->irq[0] = PHY_IGNORE_INTERRUPT;
4998         snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x", pci_dev_id(pdev));
4999
5000         new_bus->read = r8169_mdio_read_reg;
5001         new_bus->write = r8169_mdio_write_reg;
5002
5003         ret = devm_mdiobus_register(&pdev->dev, new_bus);
5004         if (ret)
5005                 return ret;
5006
5007         tp->phydev = mdiobus_get_phy(new_bus, 0);
5008         if (!tp->phydev) {
5009                 return -ENODEV;
5010         } else if (!tp->phydev->drv) {
5011                 /* Most chip versions fail with the genphy driver.
5012                  * Therefore ensure that the dedicated PHY driver is loaded.
5013                  */
5014                 dev_err(&pdev->dev, "no dedicated PHY driver found for PHY ID 0x%08x, maybe realtek.ko needs to be added to initramfs?\n",
5015                         tp->phydev->phy_id);
5016                 return -EUNATCH;
5017         }
5018
5019         /* PHY will be woken up in rtl_open() */
5020         phy_suspend(tp->phydev);
5021
5022         return 0;
5023 }
5024
5025 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
5026 {
5027         rtl_enable_rxdvgate(tp);
5028
5029         RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
5030         msleep(1);
5031         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5032
5033         r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
5034         r8168g_wait_ll_share_fifo_ready(tp);
5035
5036         r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15));
5037         r8168g_wait_ll_share_fifo_ready(tp);
5038 }
5039
5040 static void rtl_hw_init_8125(struct rtl8169_private *tp)
5041 {
5042         rtl_enable_rxdvgate(tp);
5043
5044         RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
5045         msleep(1);
5046         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5047
5048         r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
5049         r8168g_wait_ll_share_fifo_ready(tp);
5050
5051         r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0);
5052         r8168_mac_ocp_write(tp, 0xc0a6, 0x0150);
5053         r8168_mac_ocp_write(tp, 0xc01e, 0x5555);
5054         r8168g_wait_ll_share_fifo_ready(tp);
5055 }
5056
5057 static void rtl_hw_initialize(struct rtl8169_private *tp)
5058 {
5059         switch (tp->mac_version) {
5060         case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52:
5061                 rtl8168ep_stop_cmac(tp);
5062                 fallthrough;
5063         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
5064                 rtl_hw_init_8168g(tp);
5065                 break;
5066         case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_63:
5067                 rtl_hw_init_8125(tp);
5068                 break;
5069         default:
5070                 break;
5071         }
5072 }
5073
5074 static int rtl_jumbo_max(struct rtl8169_private *tp)
5075 {
5076         /* Non-GBit versions don't support jumbo frames */
5077         if (!tp->supports_gmii)
5078                 return 0;
5079
5080         switch (tp->mac_version) {
5081         /* RTL8169 */
5082         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
5083                 return JUMBO_7K;
5084         /* RTL8168b */
5085         case RTL_GIGA_MAC_VER_11:
5086         case RTL_GIGA_MAC_VER_12:
5087         case RTL_GIGA_MAC_VER_17:
5088                 return JUMBO_4K;
5089         /* RTL8168c */
5090         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
5091                 return JUMBO_6K;
5092         default:
5093                 return JUMBO_9K;
5094         }
5095 }
5096
5097 static void rtl_disable_clk(void *data)
5098 {
5099         clk_disable_unprepare(data);
5100 }
5101
5102 static int rtl_get_ether_clk(struct rtl8169_private *tp)
5103 {
5104         struct device *d = tp_to_dev(tp);
5105         struct clk *clk;
5106         int rc;
5107
5108         clk = devm_clk_get(d, "ether_clk");
5109         if (IS_ERR(clk)) {
5110                 rc = PTR_ERR(clk);
5111                 if (rc == -ENOENT)
5112                         /* clk-core allows NULL (for suspend / resume) */
5113                         rc = 0;
5114                 else
5115                         dev_err_probe(d, rc, "failed to get clk\n");
5116         } else {
5117                 tp->clk = clk;
5118                 rc = clk_prepare_enable(clk);
5119                 if (rc)
5120                         dev_err(d, "failed to enable clk: %d\n", rc);
5121                 else
5122                         rc = devm_add_action_or_reset(d, rtl_disable_clk, clk);
5123         }
5124
5125         return rc;
5126 }
5127
5128 static void rtl_init_mac_address(struct rtl8169_private *tp)
5129 {
5130         struct net_device *dev = tp->dev;
5131         u8 *mac_addr = dev->dev_addr;
5132         int rc;
5133
5134         rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr);
5135         if (!rc)
5136                 goto done;
5137
5138         rtl_read_mac_address(tp, mac_addr);
5139         if (is_valid_ether_addr(mac_addr))
5140                 goto done;
5141
5142         rtl_read_mac_from_reg(tp, mac_addr, MAC0);
5143         if (is_valid_ether_addr(mac_addr))
5144                 goto done;
5145
5146         eth_hw_addr_random(dev);
5147         dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n");
5148 done:
5149         rtl_rar_set(tp, mac_addr);
5150 }
5151
5152 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
5153 {
5154         struct rtl8169_private *tp;
5155         int jumbo_max, region, rc;
5156         enum mac_version chipset;
5157         struct net_device *dev;
5158         u16 xid;
5159
5160         dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
5161         if (!dev)
5162                 return -ENOMEM;
5163
5164         SET_NETDEV_DEV(dev, &pdev->dev);
5165         dev->netdev_ops = &rtl_netdev_ops;
5166         tp = netdev_priv(dev);
5167         tp->dev = dev;
5168         tp->pci_dev = pdev;
5169         tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1;
5170         tp->eee_adv = -1;
5171         tp->ocp_base = OCP_STD_PHY_BASE;
5172
5173         dev->tstats = devm_netdev_alloc_pcpu_stats(&pdev->dev,
5174                                                    struct pcpu_sw_netstats);
5175         if (!dev->tstats)
5176                 return -ENOMEM;
5177
5178         /* Get the *optional* external "ether_clk" used on some boards */
5179         rc = rtl_get_ether_clk(tp);
5180         if (rc)
5181                 return rc;
5182
5183         /* Disable ASPM completely as that cause random device stop working
5184          * problems as well as full system hangs for some PCIe devices users.
5185          */
5186         rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
5187                                           PCIE_LINK_STATE_L1);
5188         tp->aspm_manageable = !rc;
5189
5190         /* enable device (incl. PCI PM wakeup and hotplug setup) */
5191         rc = pcim_enable_device(pdev);
5192         if (rc < 0) {
5193                 dev_err(&pdev->dev, "enable failure\n");
5194                 return rc;
5195         }
5196
5197         if (pcim_set_mwi(pdev) < 0)
5198                 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
5199
5200         /* use first MMIO region */
5201         region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
5202         if (region < 0) {
5203                 dev_err(&pdev->dev, "no MMIO resource found\n");
5204                 return -ENODEV;
5205         }
5206
5207         /* check for weird/broken PCI region reporting */
5208         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
5209                 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
5210                 return -ENODEV;
5211         }
5212
5213         rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME);
5214         if (rc < 0) {
5215                 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
5216                 return rc;
5217         }
5218
5219         tp->mmio_addr = pcim_iomap_table(pdev)[region];
5220
5221         xid = (RTL_R32(tp, TxConfig) >> 20) & 0xfcf;
5222
5223         /* Identify chip attached to board */
5224         chipset = rtl8169_get_mac_version(xid, tp->supports_gmii);
5225         if (chipset == RTL_GIGA_MAC_NONE) {
5226                 dev_err(&pdev->dev, "unknown chip XID %03x, contact r8169 maintainers (see MAINTAINERS file)\n", xid);
5227                 return -ENODEV;
5228         }
5229
5230         tp->mac_version = chipset;
5231
5232         tp->dash_type = rtl_check_dash(tp);
5233
5234         tp->cp_cmd = RTL_R16(tp, CPlusCmd) & CPCMD_MASK;
5235
5236         if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 &&
5237             !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)))
5238                 dev->features |= NETIF_F_HIGHDMA;
5239
5240         rtl_init_rxcfg(tp);
5241
5242         rtl8169_irq_mask_and_ack(tp);
5243
5244         rtl_hw_initialize(tp);
5245
5246         rtl_hw_reset(tp);
5247
5248         pci_set_master(pdev);
5249
5250         rc = rtl_alloc_irq(tp);
5251         if (rc < 0) {
5252                 dev_err(&pdev->dev, "Can't allocate interrupt\n");
5253                 return rc;
5254         }
5255
5256         INIT_WORK(&tp->wk.work, rtl_task);
5257
5258         rtl_init_mac_address(tp);
5259
5260         dev->ethtool_ops = &rtl8169_ethtool_ops;
5261
5262         netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT);
5263
5264         dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
5265                            NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
5266         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO;
5267         dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
5268
5269         /*
5270          * Pretend we are using VLANs; This bypasses a nasty bug where
5271          * Interrupts stop flowing on high load on 8110SCd controllers.
5272          */
5273         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
5274                 /* Disallow toggling */
5275                 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
5276
5277         if (rtl_chip_supports_csum_v2(tp))
5278                 dev->hw_features |= NETIF_F_IPV6_CSUM;
5279
5280         dev->features |= dev->hw_features;
5281
5282         /* There has been a number of reports that using SG/TSO results in
5283          * tx timeouts. However for a lot of people SG/TSO works fine.
5284          * Therefore disable both features by default, but allow users to
5285          * enable them. Use at own risk!
5286          */
5287         if (rtl_chip_supports_csum_v2(tp)) {
5288                 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6;
5289                 dev->gso_max_size = RTL_GSO_MAX_SIZE_V2;
5290                 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V2;
5291         } else {
5292                 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO;
5293                 dev->gso_max_size = RTL_GSO_MAX_SIZE_V1;
5294                 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V1;
5295         }
5296
5297         dev->hw_features |= NETIF_F_RXALL;
5298         dev->hw_features |= NETIF_F_RXFCS;
5299
5300         /* configure chip for default features */
5301         rtl8169_set_features(dev, dev->features);
5302
5303         rtl_set_d3_pll_down(tp, true);
5304
5305         jumbo_max = rtl_jumbo_max(tp);
5306         if (jumbo_max)
5307                 dev->max_mtu = jumbo_max;
5308
5309         rtl_set_irq_mask(tp);
5310
5311         tp->fw_name = rtl_chip_infos[chipset].fw_name;
5312
5313         tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
5314                                             &tp->counters_phys_addr,
5315                                             GFP_KERNEL);
5316         if (!tp->counters)
5317                 return -ENOMEM;
5318
5319         pci_set_drvdata(pdev, tp);
5320
5321         rc = r8169_mdio_register(tp);
5322         if (rc)
5323                 return rc;
5324
5325         rc = register_netdev(dev);
5326         if (rc)
5327                 return rc;
5328
5329         netdev_info(dev, "%s, %pM, XID %03x, IRQ %d\n",
5330                     rtl_chip_infos[chipset].name, dev->dev_addr, xid,
5331                     pci_irq_vector(pdev, 0));
5332
5333         if (jumbo_max)
5334                 netdev_info(dev, "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
5335                             jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?
5336                             "ok" : "ko");
5337
5338         if (tp->dash_type != RTL_DASH_NONE) {
5339                 netdev_info(dev, "DASH enabled\n");
5340                 rtl8168_driver_start(tp);
5341         }
5342
5343         if (pci_dev_run_wake(pdev))
5344                 pm_runtime_put_sync(&pdev->dev);
5345
5346         return 0;
5347 }
5348
5349 static struct pci_driver rtl8169_pci_driver = {
5350         .name           = MODULENAME,
5351         .id_table       = rtl8169_pci_tbl,
5352         .probe          = rtl_init_one,
5353         .remove         = rtl_remove_one,
5354         .shutdown       = rtl_shutdown,
5355 #ifdef CONFIG_PM
5356         .driver.pm      = &rtl8169_pm_ops,
5357 #endif
5358 };
5359
5360 module_pci_driver(rtl8169_pci_driver);