drivers/net/ethernet/realtek/r8169_main.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   4  *
   5  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   6  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   7  * Copyright (c) a lot of people too. Please respect their work.
   8  *
   9  * See MAINTAINERS file for support contact information.
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/clk.h>
  17 #include <linux/delay.h>
  18 #include <linux/ethtool.h>
  19 #include <linux/phy.h>
  20 #include <linux/if_vlan.h>
  21 #include <linux/in.h>
  22 #include <linux/io.h>
  23 #include <linux/ip.h>
  24 #include <linux/tcp.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/pm_runtime.h>
  28 #include <linux/bitfield.h>
  29 #include <linux/prefetch.h>
  30 #include <linux/ipv6.h>
  31 #include <asm/unaligned.h>
  32 #include <net/ip6_checksum.h>
  33 #include <net/netdev_queues.h>
  34
  35 #include "r8169.h"
  36 #include "r8169_firmware.h"
  37
  38 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  39 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  40 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  41 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  42 #define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
  43 #define FIRMWARE_8168F_1        "rtl_nic/rtl8168f-1.fw"
  44 #define FIRMWARE_8168F_2        "rtl_nic/rtl8168f-2.fw"
  45 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  46 #define FIRMWARE_8402_1         "rtl_nic/rtl8402-1.fw"
  47 #define FIRMWARE_8411_1         "rtl_nic/rtl8411-1.fw"
  48 #define FIRMWARE_8411_2         "rtl_nic/rtl8411-2.fw"
  49 #define FIRMWARE_8106E_1        "rtl_nic/rtl8106e-1.fw"
  50 #define FIRMWARE_8106E_2        "rtl_nic/rtl8106e-2.fw"
  51 #define FIRMWARE_8168G_2        "rtl_nic/rtl8168g-2.fw"
  52 #define FIRMWARE_8168G_3        "rtl_nic/rtl8168g-3.fw"
  53 #define FIRMWARE_8168H_2        "rtl_nic/rtl8168h-2.fw"
  54 #define FIRMWARE_8168FP_3       "rtl_nic/rtl8168fp-3.fw"
  55 #define FIRMWARE_8107E_2        "rtl_nic/rtl8107e-2.fw"
  56 #define FIRMWARE_8125A_3        "rtl_nic/rtl8125a-3.fw"
  57 #define FIRMWARE_8125B_2        "rtl_nic/rtl8125b-2.fw"
  58 #define FIRMWARE_8126A_2        "rtl_nic/rtl8126a-2.fw"
  59
  60 #define TX_DMA_BURST    7       /* Maximum PCI burst, '7' is unlimited */
  61 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  62
  63 #define R8169_REGS_SIZE         256
  64 #define R8169_RX_BUF_SIZE       (SZ_16K - 1)
  65 #define NUM_TX_DESC     256     /* Number of Tx descriptor registers */
  66 #define NUM_RX_DESC     256     /* Number of Rx descriptor registers */
  67 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  68 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  69 #define R8169_TX_STOP_THRS      (MAX_SKB_FRAGS + 1)
  70 #define R8169_TX_START_THRS     (2 * R8169_TX_STOP_THRS)
  71
  72 #define OCP_STD_PHY_BASE        0xa400
  73
  74 #define RTL_CFG_NO_GBIT 1
  75
  76 /* write/read MMIO register */
  77 #define RTL_W8(tp, reg, val8)   writeb((val8), tp->mmio_addr + (reg))
  78 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
  79 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
  80 #define RTL_R8(tp, reg)         readb(tp->mmio_addr + (reg))
  81 #define RTL_R16(tp, reg)                readw(tp->mmio_addr + (reg))
  82 #define RTL_R32(tp, reg)                readl(tp->mmio_addr + (reg))
  83
  84 #define JUMBO_4K        (4 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
  85 #define JUMBO_6K        (6 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
  86 #define JUMBO_7K        (7 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
  87 #define JUMBO_9K        (9 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
  88
  89 static const struct {
  90         const char *name;
  91         const char *fw_name;
  92 } rtl_chip_infos[] = {
  93         /* PCI devices. */
  94         [RTL_GIGA_MAC_VER_02] = {"RTL8169s"                             },
  95         [RTL_GIGA_MAC_VER_03] = {"RTL8110s"                             },
  96         [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb"                     },
  97         [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc"                     },
  98         [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc"                     },
  99         /* PCI-E devices. */
 100         [RTL_GIGA_MAC_VER_07] = {"RTL8102e"                             },
 101         [RTL_GIGA_MAC_VER_08] = {"RTL8102e"                             },
 102         [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e"                    },
 103         [RTL_GIGA_MAC_VER_10] = {"RTL8101e/RTL8100e"                    },
 104         [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b"                       },
 105         [RTL_GIGA_MAC_VER_14] = {"RTL8401"                              },
 106         [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b"                       },
 107         [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp"                     },
 108         [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c"                       },
 109         [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c"                       },
 110         [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c"                       },
 111         [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c"                       },
 112         [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp"                     },
 113         [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp"                     },
 114         [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d",      FIRMWARE_8168D_1},
 115         [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d",      FIRMWARE_8168D_2},
 116         [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp"                     },
 117         [RTL_GIGA_MAC_VER_29] = {"RTL8105e",            FIRMWARE_8105E_1},
 118         [RTL_GIGA_MAC_VER_30] = {"RTL8105e",            FIRMWARE_8105E_1},
 119         [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp"                     },
 120         [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e",      FIRMWARE_8168E_1},
 121         [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e",      FIRMWARE_8168E_2},
 122         [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl",  FIRMWARE_8168E_3},
 123         [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f",      FIRMWARE_8168F_1},
 124         [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f",      FIRMWARE_8168F_2},
 125         [RTL_GIGA_MAC_VER_37] = {"RTL8402",             FIRMWARE_8402_1 },
 126         [RTL_GIGA_MAC_VER_38] = {"RTL8411",             FIRMWARE_8411_1 },
 127         [RTL_GIGA_MAC_VER_39] = {"RTL8106e",            FIRMWARE_8106E_1},
 128         [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g",      FIRMWARE_8168G_2},
 129         [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu",    FIRMWARE_8168G_3},
 130         [RTL_GIGA_MAC_VER_43] = {"RTL8106eus",          FIRMWARE_8106E_2},
 131         [RTL_GIGA_MAC_VER_44] = {"RTL8411b",            FIRMWARE_8411_2 },
 132         [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h",      FIRMWARE_8168H_2},
 133         [RTL_GIGA_MAC_VER_48] = {"RTL8107e",            FIRMWARE_8107E_2},
 134         [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep"                     },
 135         [RTL_GIGA_MAC_VER_52] = {"RTL8168fp/RTL8117",  FIRMWARE_8168FP_3},
 136         [RTL_GIGA_MAC_VER_53] = {"RTL8168fp/RTL8117",                   },
 137         [RTL_GIGA_MAC_VER_61] = {"RTL8125A",            FIRMWARE_8125A_3},
 138         /* reserve 62 for CFG_METHOD_4 in the vendor driver */
 139         [RTL_GIGA_MAC_VER_63] = {"RTL8125B",            FIRMWARE_8125B_2},
 140         [RTL_GIGA_MAC_VER_65] = {"RTL8126A",            FIRMWARE_8126A_2},
 141 };
 142
 143 static const struct pci_device_id rtl8169_pci_tbl[] = {
 144         { PCI_VDEVICE(REALTEK,  0x2502) },
 145         { PCI_VDEVICE(REALTEK,  0x2600) },
 146         { PCI_VDEVICE(REALTEK,  0x8129) },
 147         { PCI_VDEVICE(REALTEK,  0x8136), RTL_CFG_NO_GBIT },
 148         { PCI_VDEVICE(REALTEK,  0x8161) },
 149         { PCI_VDEVICE(REALTEK,  0x8162) },
 150         { PCI_VDEVICE(REALTEK,  0x8167) },
 151         { PCI_VDEVICE(REALTEK,  0x8168) },
 152         { PCI_VDEVICE(NCUBE,    0x8168) },
 153         { PCI_VDEVICE(REALTEK,  0x8169) },
 154         { PCI_VENDOR_ID_DLINK,  0x4300,
 155                 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 },
 156         { PCI_VDEVICE(DLINK,    0x4300) },
 157         { PCI_VDEVICE(DLINK,    0x4302) },
 158         { PCI_VDEVICE(AT,       0xc107) },
 159         { PCI_VDEVICE(USR,      0x0116) },
 160         { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 },
 161         { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 },
 162         { PCI_VDEVICE(REALTEK,  0x8125) },
 163         { PCI_VDEVICE(REALTEK,  0x8126) },
 164         { PCI_VDEVICE(REALTEK,  0x3000) },
 165         {}
 166 };
 167
 168 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 169
 170 enum rtl_registers {
 171         MAC0            = 0,    /* Ethernet hardware address. */
 172         MAC4            = 4,
 173         MAR0            = 8,    /* Multicast filter. */
 174         CounterAddrLow          = 0x10,
 175         CounterAddrHigh         = 0x14,
 176         TxDescStartAddrLow      = 0x20,
 177         TxDescStartAddrHigh     = 0x24,
 178         TxHDescStartAddrLow     = 0x28,
 179         TxHDescStartAddrHigh    = 0x2c,
 180         FLASH           = 0x30,
 181         ERSR            = 0x36,
 182         ChipCmd         = 0x37,
 183         TxPoll          = 0x38,
 184         IntrMask        = 0x3c,
 185         IntrStatus      = 0x3e,
 186
 187         TxConfig        = 0x40,
 188 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 189 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 190
 191         RxConfig        = 0x44,
 192 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 193 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 194 #define RXCFG_FIFO_SHIFT                13
 195                                         /* No threshold before first PCI xfer */
 196 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 197 #define RX_EARLY_OFF                    (1 << 11)
 198 #define RX_PAUSE_SLOT_ON                (1 << 11)       /* 8125b and later */
 199 #define RXCFG_DMA_SHIFT                 8
 200                                         /* Unlimited maximum PCI burst. */
 201 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 202
 203         Cfg9346         = 0x50,
 204         Config0         = 0x51,
 205         Config1         = 0x52,
 206         Config2         = 0x53,
 207 #define PME_SIGNAL                      (1 << 5)        /* 8168c and later */
 208
 209         Config3         = 0x54,
 210         Config4         = 0x55,
 211         Config5         = 0x56,
 212         PHYAR           = 0x60,
 213         PHYstatus       = 0x6c,
 214         RxMaxSize       = 0xda,
 215         CPlusCmd        = 0xe0,
 216         IntrMitigate    = 0xe2,
 217
 218 #define RTL_COALESCE_TX_USECS   GENMASK(15, 12)
 219 #define RTL_COALESCE_TX_FRAMES  GENMASK(11, 8)
 220 #define RTL_COALESCE_RX_USECS   GENMASK(7, 4)
 221 #define RTL_COALESCE_RX_FRAMES  GENMASK(3, 0)
 222
 223 #define RTL_COALESCE_T_MAX      0x0fU
 224 #define RTL_COALESCE_FRAME_MAX  (RTL_COALESCE_T_MAX * 4)
 225
 226         RxDescAddrLow   = 0xe4,
 227         RxDescAddrHigh  = 0xe8,
 228         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 229
 230 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 231
 232         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 233
 234 #define TxPacketMax     (8064 >> 7)
 235 #define EarlySize       0x27
 236
 237         FuncEvent       = 0xf0,
 238         FuncEventMask   = 0xf4,
 239         FuncPresetState = 0xf8,
 240         IBCR0           = 0xf8,
 241         IBCR2           = 0xf9,
 242         IBIMR0          = 0xfa,
 243         IBISR0          = 0xfb,
 244         FuncForceEvent  = 0xfc,
 245 };
 246
 247 enum rtl8168_8101_registers {
 248         CSIDR                   = 0x64,
 249         CSIAR                   = 0x68,
 250 #define CSIAR_FLAG                      0x80000000
 251 #define CSIAR_WRITE_CMD                 0x80000000
 252 #define CSIAR_BYTE_ENABLE               0x0000f000
 253 #define CSIAR_ADDR_MASK                 0x00000fff
 254         PMCH                    = 0x6f,
 255 #define D3COLD_NO_PLL_DOWN              BIT(7)
 256 #define D3HOT_NO_PLL_DOWN               BIT(6)
 257 #define D3_NO_PLL_DOWN                  (BIT(7) | BIT(6))
 258         EPHYAR                  = 0x80,
 259 #define EPHYAR_FLAG                     0x80000000
 260 #define EPHYAR_WRITE_CMD                0x80000000
 261 #define EPHYAR_REG_MASK                 0x1f
 262 #define EPHYAR_REG_SHIFT                16
 263 #define EPHYAR_DATA_MASK                0xffff
 264         DLLPR                   = 0xd0,
 265 #define PFM_EN                          (1 << 6)
 266 #define TX_10M_PS_EN                    (1 << 7)
 267         DBG_REG                 = 0xd1,
 268 #define FIX_NAK_1                       (1 << 4)
 269 #define FIX_NAK_2                       (1 << 3)
 270         TWSI                    = 0xd2,
 271         MCU                     = 0xd3,
 272 #define NOW_IS_OOB                      (1 << 7)
 273 #define TX_EMPTY                        (1 << 5)
 274 #define RX_EMPTY                        (1 << 4)
 275 #define RXTX_EMPTY                      (TX_EMPTY | RX_EMPTY)
 276 #define EN_NDP                          (1 << 3)
 277 #define EN_OOB_RESET                    (1 << 2)
 278 #define LINK_LIST_RDY                   (1 << 1)
 279         EFUSEAR                 = 0xdc,
 280 #define EFUSEAR_FLAG                    0x80000000
 281 #define EFUSEAR_WRITE_CMD               0x80000000
 282 #define EFUSEAR_READ_CMD                0x00000000
 283 #define EFUSEAR_REG_MASK                0x03ff
 284 #define EFUSEAR_REG_SHIFT               8
 285 #define EFUSEAR_DATA_MASK               0xff
 286         MISC_1                  = 0xf2,
 287 #define PFM_D3COLD_EN                   (1 << 6)
 288 };
 289
 290 enum rtl8168_registers {
 291         LED_CTRL                = 0x18,
 292         LED_FREQ                = 0x1a,
 293         EEE_LED                 = 0x1b,
 294         ERIDR                   = 0x70,
 295         ERIAR                   = 0x74,
 296 #define ERIAR_FLAG                      0x80000000
 297 #define ERIAR_WRITE_CMD                 0x80000000
 298 #define ERIAR_READ_CMD                  0x00000000
 299 #define ERIAR_ADDR_BYTE_ALIGN           4
 300 #define ERIAR_TYPE_SHIFT                16
 301 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 302 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 303 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 304 #define ERIAR_OOB                       (0x02 << ERIAR_TYPE_SHIFT)
 305 #define ERIAR_MASK_SHIFT                12
 306 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 307 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 308 #define ERIAR_MASK_0100                 (0x4 << ERIAR_MASK_SHIFT)
 309 #define ERIAR_MASK_0101                 (0x5 << ERIAR_MASK_SHIFT)
 310 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 311         EPHY_RXER_NUM           = 0x7c,
 312         OCPDR                   = 0xb0, /* OCP GPHY access */
 313 #define OCPDR_WRITE_CMD                 0x80000000
 314 #define OCPDR_READ_CMD                  0x00000000
 315 #define OCPDR_REG_MASK                  0x7f
 316 #define OCPDR_GPHY_REG_SHIFT            16
 317 #define OCPDR_DATA_MASK                 0xffff
 318         OCPAR                   = 0xb4,
 319 #define OCPAR_FLAG                      0x80000000
 320 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 321 #define OCPAR_GPHY_READ_CMD             0x0000f060
 322         GPHY_OCP                = 0xb8,
 323         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 324         MISC                    = 0xf0, /* 8168e only. */
 325 #define TXPLA_RST                       (1 << 29)
 326 #define DISABLE_LAN_EN                  (1 << 23) /* Enable GPIO pin */
 327 #define PWM_EN                          (1 << 22)
 328 #define RXDV_GATED_EN                   (1 << 19)
 329 #define EARLY_TALLY_EN                  (1 << 16)
 330 };
 331
 332 enum rtl8125_registers {
 333         LEDSEL0                 = 0x18,
 334         INT_CFG0_8125           = 0x34,
 335 #define INT_CFG0_ENABLE_8125            BIT(0)
 336 #define INT_CFG0_CLKREQEN               BIT(3)
 337         IntrMask_8125           = 0x38,
 338         IntrStatus_8125         = 0x3c,
 339         INT_CFG1_8125           = 0x7a,
 340         LEDSEL2                 = 0x84,
 341         LEDSEL1                 = 0x86,
 342         TxPoll_8125             = 0x90,
 343         LEDSEL3                 = 0x96,
 344         MAC0_BKP                = 0x19e0,
 345         EEE_TXIDLE_TIMER_8125   = 0x6048,
 346 };
 347
 348 #define LEDSEL_MASK_8125        0x23f
 349
 350 #define RX_VLAN_INNER_8125      BIT(22)
 351 #define RX_VLAN_OUTER_8125      BIT(23)
 352 #define RX_VLAN_8125            (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125)
 353
 354 #define RX_FETCH_DFLT_8125      (8 << 27)
 355
 356 enum rtl_register_content {
 357         /* InterruptStatusBits */
 358         SYSErr          = 0x8000,
 359         PCSTimeout      = 0x4000,
 360         SWInt           = 0x0100,
 361         TxDescUnavail   = 0x0080,
 362         RxFIFOOver      = 0x0040,
 363         LinkChg         = 0x0020,
 364         RxOverflow      = 0x0010,
 365         TxErr           = 0x0008,
 366         TxOK            = 0x0004,
 367         RxErr           = 0x0002,
 368         RxOK            = 0x0001,
 369
 370         /* RxStatusDesc */
 371         RxRWT   = (1 << 22),
 372         RxRES   = (1 << 21),
 373         RxRUNT  = (1 << 20),
 374         RxCRC   = (1 << 19),
 375
 376         /* ChipCmdBits */
 377         StopReq         = 0x80,
 378         CmdReset        = 0x10,
 379         CmdRxEnb        = 0x08,
 380         CmdTxEnb        = 0x04,
 381         RxBufEmpty      = 0x01,
 382
 383         /* TXPoll register p.5 */
 384         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 385         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 386         FSWInt          = 0x01,         /* Forced software interrupt */
 387
 388         /* Cfg9346Bits */
 389         Cfg9346_Lock    = 0x00,
 390         Cfg9346_Unlock  = 0xc0,
 391
 392         /* rx_mode_bits */
 393         AcceptErr       = 0x20,
 394         AcceptRunt      = 0x10,
 395 #define RX_CONFIG_ACCEPT_ERR_MASK       0x30
 396         AcceptBroadcast = 0x08,
 397         AcceptMulticast = 0x04,
 398         AcceptMyPhys    = 0x02,
 399         AcceptAllPhys   = 0x01,
 400 #define RX_CONFIG_ACCEPT_OK_MASK        0x0f
 401 #define RX_CONFIG_ACCEPT_MASK           0x3f
 402
 403         /* TxConfigBits */
 404         TxInterFrameGapShift = 24,
 405         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 406
 407         /* Config1 register p.24 */
 408         LEDS1           = (1 << 7),
 409         LEDS0           = (1 << 6),
 410         Speed_down      = (1 << 4),
 411         MEMMAP          = (1 << 3),
 412         IOMAP           = (1 << 2),
 413         VPD             = (1 << 1),
 414         PMEnable        = (1 << 0),     /* Power Management Enable */
 415
 416         /* Config2 register p. 25 */
 417         ClkReqEn        = (1 << 7),     /* Clock Request Enable */
 418         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
 419         PCI_Clock_66MHz = 0x01,
 420         PCI_Clock_33MHz = 0x00,
 421
 422         /* Config3 register p.25 */
 423         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 424         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 425         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
 426         Rdy_to_L23      = (1 << 1),     /* L23 Enable */
 427         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 428
 429         /* Config4 register */
 430         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
 431
 432         /* Config5 register p.27 */
 433         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 434         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 435         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 436         Spi_en          = (1 << 3),
 437         LanWake         = (1 << 1),     /* LanWake enable/disable */
 438         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 439         ASPM_en         = (1 << 0),     /* ASPM enable */
 440
 441         /* CPlusCmd p.31 */
 442         EnableBist      = (1 << 15),    // 8168 8101
 443         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 444         EnAnaPLL        = (1 << 14),    // 8169
 445         Normal_mode     = (1 << 13),    // unused
 446         Force_half_dup  = (1 << 12),    // 8168 8101
 447         Force_rxflow_en = (1 << 11),    // 8168 8101
 448         Force_txflow_en = (1 << 10),    // 8168 8101
 449         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 450         ASF             = (1 << 8),     // 8168 8101
 451         PktCntrDisable  = (1 << 7),     // 8168 8101
 452         Mac_dbgo_sel    = 0x001c,       // 8168
 453         RxVlan          = (1 << 6),
 454         RxChkSum        = (1 << 5),
 455         PCIDAC          = (1 << 4),
 456         PCIMulRW        = (1 << 3),
 457 #define INTT_MASK       GENMASK(1, 0)
 458 #define CPCMD_MASK      (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
 459
 460         /* rtl8169_PHYstatus */
 461         TBI_Enable      = 0x80,
 462         TxFlowCtrl      = 0x40,
 463         RxFlowCtrl      = 0x20,
 464         _1000bpsF       = 0x10,
 465         _100bps         = 0x08,
 466         _10bps          = 0x04,
 467         LinkStatus      = 0x02,
 468         FullDup         = 0x01,
 469
 470         /* ResetCounterCommand */
 471         CounterReset    = 0x1,
 472
 473         /* DumpCounterCommand */
 474         CounterDump     = 0x8,
 475
 476         /* magic enable v2 */
 477         MagicPacket_v2  = (1 << 16),    /* Wake up when receives a Magic Packet */
 478 };
 479
 480 enum rtl_desc_bit {
 481         /* First doubleword. */
 482         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 483         RingEnd         = (1 << 30), /* End of descriptor ring */
 484         FirstFrag       = (1 << 29), /* First segment of a packet */
 485         LastFrag        = (1 << 28), /* Final segment of a packet */
 486 };
 487
 488 /* Generic case. */
 489 enum rtl_tx_desc_bit {
 490         /* First doubleword. */
 491         TD_LSO          = (1 << 27),            /* Large Send Offload */
 492 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 493
 494         /* Second doubleword. */
 495         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 496 };
 497
 498 /* 8169, 8168b and 810x except 8102e. */
 499 enum rtl_tx_desc_bit_0 {
 500         /* First doubleword. */
 501 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 502         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 503         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 504         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 505 };
 506
 507 /* 8102e, 8168c and beyond. */
 508 enum rtl_tx_desc_bit_1 {
 509         /* First doubleword. */
 510         TD1_GTSENV4     = (1 << 26),            /* Giant Send for IPv4 */
 511         TD1_GTSENV6     = (1 << 25),            /* Giant Send for IPv6 */
 512 #define GTTCPHO_SHIFT                   18
 513 #define GTTCPHO_MAX                     0x7f
 514
 515         /* Second doubleword. */
 516 #define TCPHO_SHIFT                     18
 517 #define TCPHO_MAX                       0x3ff
 518 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 519         TD1_IPv6_CS     = (1 << 28),            /* Calculate IPv6 checksum */
 520         TD1_IPv4_CS     = (1 << 29),            /* Calculate IPv4 checksum */
 521         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 522         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 523 };
 524
 525 enum rtl_rx_desc_bit {
 526         /* Rx private */
 527         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 528         PID0            = (1 << 17), /* Protocol ID bit 0/2 */
 529
 530 #define RxProtoUDP      (PID1)
 531 #define RxProtoTCP      (PID0)
 532 #define RxProtoIP       (PID1 | PID0)
 533 #define RxProtoMask     RxProtoIP
 534
 535         IPFail          = (1 << 16), /* IP checksum failed */
 536         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 537         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 538
 539 #define RxCSFailMask    (IPFail | UDPFail | TCPFail)
 540
 541         RxVlanTag       = (1 << 16), /* VLAN tag available */
 542 };
 543
 544 #define RTL_GSO_MAX_SIZE_V1     32000
 545 #define RTL_GSO_MAX_SEGS_V1     24
 546 #define RTL_GSO_MAX_SIZE_V2     64000
 547 #define RTL_GSO_MAX_SEGS_V2     64
 548
 549 struct TxDesc {
 550         __le32 opts1;
 551         __le32 opts2;
 552         __le64 addr;
 553 };
 554
 555 struct RxDesc {
 556         __le32 opts1;
 557         __le32 opts2;
 558         __le64 addr;
 559 };
 560
 561 struct ring_info {
 562         struct sk_buff  *skb;
 563         u32             len;
 564 };
 565
 566 struct rtl8169_counters {
 567         __le64  tx_packets;
 568         __le64  rx_packets;
 569         __le64  tx_errors;
 570         __le32  rx_errors;
 571         __le16  rx_missed;
 572         __le16  align_errors;
 573         __le32  tx_one_collision;
 574         __le32  tx_multi_collision;
 575         __le64  rx_unicast;
 576         __le64  rx_broadcast;
 577         __le32  rx_multicast;
 578         __le16  tx_aborted;
 579         __le16  tx_underun;
 580 };
 581
 582 struct rtl8169_tc_offsets {
 583         bool    inited;
 584         __le64  tx_errors;
 585         __le32  tx_multi_collision;
 586         __le16  tx_aborted;
 587         __le16  rx_missed;
 588 };
 589
 590 enum rtl_flag {
 591         RTL_FLAG_TASK_ENABLED = 0,
 592         RTL_FLAG_TASK_RESET_PENDING,
 593         RTL_FLAG_TASK_RESET_NO_QUEUE_WAKE,
 594         RTL_FLAG_TASK_TX_TIMEOUT,
 595         RTL_FLAG_MAX
 596 };
 597
 598 enum rtl_dash_type {
 599         RTL_DASH_NONE,
 600         RTL_DASH_DP,
 601         RTL_DASH_EP,
 602 };
 603
 604 struct rtl8169_private {
 605         void __iomem *mmio_addr;        /* memory map physical address */
 606         struct pci_dev *pci_dev;
 607         struct net_device *dev;
 608         struct phy_device *phydev;
 609         struct napi_struct napi;
 610         enum mac_version mac_version;
 611         enum rtl_dash_type dash_type;
 612         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 613         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 614         u32 dirty_tx;
 615         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 616         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 617         dma_addr_t TxPhyAddr;
 618         dma_addr_t RxPhyAddr;
 619         struct page *Rx_databuff[NUM_RX_DESC];  /* Rx data buffers */
 620         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 621         u16 cp_cmd;
 622         u16 tx_lpi_timer;
 623         u32 irq_mask;
 624         int irq;
 625         struct clk *clk;
 626
 627         struct {
 628                 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
 629                 struct work_struct work;
 630         } wk;
 631
 632         raw_spinlock_t config25_lock;
 633         raw_spinlock_t mac_ocp_lock;
 634         struct mutex led_lock;  /* serialize LED ctrl RMW access */
 635
 636         raw_spinlock_t cfg9346_usage_lock;
 637         int cfg9346_usage_count;
 638
 639         unsigned supports_gmii:1;
 640         unsigned aspm_manageable:1;
 641         unsigned dash_enabled:1;
 642         dma_addr_t counters_phys_addr;
 643         struct rtl8169_counters *counters;
 644         struct rtl8169_tc_offsets tc_offset;
 645         u32 saved_wolopts;
 646
 647         const char *fw_name;
 648         struct rtl_fw *rtl_fw;
 649
 650         u32 ocp_base;
 651 };
 652
 653 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp);
 654
 655 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 656 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 657 MODULE_SOFTDEP("pre: realtek");
 658 MODULE_LICENSE("GPL");
 659 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 660 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 661 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 662 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 663 MODULE_FIRMWARE(FIRMWARE_8168E_3);
 664 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 665 MODULE_FIRMWARE(FIRMWARE_8168F_1);
 666 MODULE_FIRMWARE(FIRMWARE_8168F_2);
 667 MODULE_FIRMWARE(FIRMWARE_8402_1);
 668 MODULE_FIRMWARE(FIRMWARE_8411_1);
 669 MODULE_FIRMWARE(FIRMWARE_8411_2);
 670 MODULE_FIRMWARE(FIRMWARE_8106E_1);
 671 MODULE_FIRMWARE(FIRMWARE_8106E_2);
 672 MODULE_FIRMWARE(FIRMWARE_8168G_2);
 673 MODULE_FIRMWARE(FIRMWARE_8168G_3);
 674 MODULE_FIRMWARE(FIRMWARE_8168H_2);
 675 MODULE_FIRMWARE(FIRMWARE_8168FP_3);
 676 MODULE_FIRMWARE(FIRMWARE_8107E_2);
 677 MODULE_FIRMWARE(FIRMWARE_8125A_3);
 678 MODULE_FIRMWARE(FIRMWARE_8125B_2);
 679
 680 static inline struct device *tp_to_dev(struct rtl8169_private *tp)
 681 {
 682         return &tp->pci_dev->dev;
 683 }
 684
 685 static void rtl_lock_config_regs(struct rtl8169_private *tp)
 686 {
 687         unsigned long flags;
 688
 689         raw_spin_lock_irqsave(&tp->cfg9346_usage_lock, flags);
 690         if (!--tp->cfg9346_usage_count)
 691                 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
 692         raw_spin_unlock_irqrestore(&tp->cfg9346_usage_lock, flags);
 693 }
 694
 695 static void rtl_unlock_config_regs(struct rtl8169_private *tp)
 696 {
 697         unsigned long flags;
 698
 699         raw_spin_lock_irqsave(&tp->cfg9346_usage_lock, flags);
 700         if (!tp->cfg9346_usage_count++)
 701                 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
 702         raw_spin_unlock_irqrestore(&tp->cfg9346_usage_lock, flags);
 703 }
 704
 705 static void rtl_pci_commit(struct rtl8169_private *tp)
 706 {
 707         /* Read an arbitrary register to commit a preceding PCI write */
 708         RTL_R8(tp, ChipCmd);
 709 }
 710
 711 static void rtl_mod_config2(struct rtl8169_private *tp, u8 clear, u8 set)
 712 {
 713         unsigned long flags;
 714         u8 val;
 715
 716         raw_spin_lock_irqsave(&tp->config25_lock, flags);
 717         val = RTL_R8(tp, Config2);
 718         RTL_W8(tp, Config2, (val & ~clear) | set);
 719         raw_spin_unlock_irqrestore(&tp->config25_lock, flags);
 720 }
 721
 722 static void rtl_mod_config5(struct rtl8169_private *tp, u8 clear, u8 set)
 723 {
 724         unsigned long flags;
 725         u8 val;
 726
 727         raw_spin_lock_irqsave(&tp->config25_lock, flags);
 728         val = RTL_R8(tp, Config5);
 729         RTL_W8(tp, Config5, (val & ~clear) | set);
 730         raw_spin_unlock_irqrestore(&tp->config25_lock, flags);
 731 }
 732
 733 static bool rtl_is_8125(struct rtl8169_private *tp)
 734 {
 735         return tp->mac_version >= RTL_GIGA_MAC_VER_61;
 736 }
 737
 738 static bool rtl_is_8168evl_up(struct rtl8169_private *tp)
 739 {
 740         return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
 741                tp->mac_version != RTL_GIGA_MAC_VER_39 &&
 742                tp->mac_version <= RTL_GIGA_MAC_VER_53;
 743 }
 744
 745 static bool rtl_supports_eee(struct rtl8169_private *tp)
 746 {
 747         return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
 748                tp->mac_version != RTL_GIGA_MAC_VER_37 &&
 749                tp->mac_version != RTL_GIGA_MAC_VER_39;
 750 }
 751
 752 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg)
 753 {
 754         int i;
 755
 756         for (i = 0; i < ETH_ALEN; i++)
 757                 mac[i] = RTL_R8(tp, reg + i);
 758 }
 759
 760 struct rtl_cond {
 761         bool (*check)(struct rtl8169_private *);
 762         const char *msg;
 763 };
 764
 765 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
 766                           unsigned long usecs, int n, bool high)
 767 {
 768         int i;
 769
 770         for (i = 0; i < n; i++) {
 771                 if (c->check(tp) == high)
 772                         return true;
 773                 fsleep(usecs);
 774         }
 775
 776         if (net_ratelimit())
 777                 netdev_err(tp->dev, "%s == %d (loop: %d, delay: %lu).\n",
 778                            c->msg, !high, n, usecs);
 779         return false;
 780 }
 781
 782 static bool rtl_loop_wait_high(struct rtl8169_private *tp,
 783                                const struct rtl_cond *c,
 784                                unsigned long d, int n)
 785 {
 786         return rtl_loop_wait(tp, c, d, n, true);
 787 }
 788
 789 static bool rtl_loop_wait_low(struct rtl8169_private *tp,
 790                               const struct rtl_cond *c,
 791                               unsigned long d, int n)
 792 {
 793         return rtl_loop_wait(tp, c, d, n, false);
 794 }
 795
 796 #define DECLARE_RTL_COND(name)                          \
 797 static bool name ## _check(struct rtl8169_private *);   \
 798                                                         \
 799 static const struct rtl_cond name = {                   \
 800         .check  = name ## _check,                       \
 801         .msg    = #name                                 \
 802 };                                                      \
 803                                                         \
 804 static bool name ## _check(struct rtl8169_private *tp)
 805
 806 int rtl8168_led_mod_ctrl(struct rtl8169_private *tp, u16 mask, u16 val)
 807 {
 808         struct device *dev = tp_to_dev(tp);
 809         int ret;
 810
 811         ret = pm_runtime_resume_and_get(dev);
 812         if (ret < 0)
 813                 return ret;
 814
 815         mutex_lock(&tp->led_lock);
 816         RTL_W16(tp, LED_CTRL, (RTL_R16(tp, LED_CTRL) & ~mask) | val);
 817         mutex_unlock(&tp->led_lock);
 818
 819         pm_runtime_put_sync(dev);
 820
 821         return 0;
 822 }
 823
 824 int rtl8168_get_led_mode(struct rtl8169_private *tp)
 825 {
 826         struct device *dev = tp_to_dev(tp);
 827         int ret;
 828
 829         ret = pm_runtime_resume_and_get(dev);
 830         if (ret < 0)
 831                 return ret;
 832
 833         ret = RTL_R16(tp, LED_CTRL);
 834
 835         pm_runtime_put_sync(dev);
 836
 837         return ret;
 838 }
 839
 840 static int rtl8125_get_led_reg(int index)
 841 {
 842         static const int led_regs[] = { LEDSEL0, LEDSEL1, LEDSEL2, LEDSEL3 };
 843
 844         return led_regs[index];
 845 }
 846
 847 int rtl8125_set_led_mode(struct rtl8169_private *tp, int index, u16 mode)
 848 {
 849         int reg = rtl8125_get_led_reg(index);
 850         struct device *dev = tp_to_dev(tp);
 851         int ret;
 852         u16 val;
 853
 854         ret = pm_runtime_resume_and_get(dev);
 855         if (ret < 0)
 856                 return ret;
 857
 858         mutex_lock(&tp->led_lock);
 859         val = RTL_R16(tp, reg) & ~LEDSEL_MASK_8125;
 860         RTL_W16(tp, reg, val | mode);
 861         mutex_unlock(&tp->led_lock);
 862
 863         pm_runtime_put_sync(dev);
 864
 865         return 0;
 866 }
 867
 868 int rtl8125_get_led_mode(struct rtl8169_private *tp, int index)
 869 {
 870         int reg = rtl8125_get_led_reg(index);
 871         struct device *dev = tp_to_dev(tp);
 872         int ret;
 873
 874         ret = pm_runtime_resume_and_get(dev);
 875         if (ret < 0)
 876                 return ret;
 877
 878         ret = RTL_R16(tp, reg);
 879
 880         pm_runtime_put_sync(dev);
 881
 882         return ret;
 883 }
 884
 885 void r8169_get_led_name(struct rtl8169_private *tp, int idx,
 886                         char *buf, int buf_len)
 887 {
 888         struct pci_dev *pdev = tp->pci_dev;
 889         char pdom[8], pfun[8];
 890         int domain;
 891
 892         domain = pci_domain_nr(pdev->bus);
 893         if (domain)
 894                 snprintf(pdom, sizeof(pdom), "P%d", domain);
 895         else
 896                 pdom[0] = '\0';
 897
 898         if (pdev->multifunction)
 899                 snprintf(pfun, sizeof(pfun), "f%d", PCI_FUNC(pdev->devfn));
 900         else
 901                 pfun[0] = '\0';
 902
 903         snprintf(buf, buf_len, "en%sp%ds%d%s-%d::lan", pdom, pdev->bus->number,
 904                  PCI_SLOT(pdev->devfn), pfun, idx);
 905 }
 906
 907 static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type)
 908 {
 909         /* based on RTL8168FP_OOBMAC_BASE in vendor driver */
 910         if (type == ERIAR_OOB &&
 911             (tp->mac_version == RTL_GIGA_MAC_VER_52 ||
 912              tp->mac_version == RTL_GIGA_MAC_VER_53))
 913                 *cmd |= 0xf70 << 18;
 914 }
 915
 916 DECLARE_RTL_COND(rtl_eriar_cond)
 917 {
 918         return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
 919 }
 920
 921 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
 922                            u32 val, int type)
 923 {
 924         u32 cmd = ERIAR_WRITE_CMD | type | mask | addr;
 925
 926         if (WARN(addr & 3 || !mask, "addr: 0x%x, mask: 0x%08x\n", addr, mask))
 927                 return;
 928
 929         RTL_W32(tp, ERIDR, val);
 930         r8168fp_adjust_ocp_cmd(tp, &cmd, type);
 931         RTL_W32(tp, ERIAR, cmd);
 932
 933         rtl_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
 934 }
 935
 936 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
 937                           u32 val)
 938 {
 939         _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC);
 940 }
 941
 942 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
 943 {
 944         u32 cmd = ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr;
 945
 946         r8168fp_adjust_ocp_cmd(tp, &cmd, type);
 947         RTL_W32(tp, ERIAR, cmd);
 948
 949         return rtl_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
 950                 RTL_R32(tp, ERIDR) : ~0;
 951 }
 952
 953 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr)
 954 {
 955         return _rtl_eri_read(tp, addr, ERIAR_EXGMAC);
 956 }
 957
 958 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 p, u32 m)
 959 {
 960         u32 val = rtl_eri_read(tp, addr);
 961
 962         rtl_eri_write(tp, addr, ERIAR_MASK_1111, (val & ~m) | p);
 963 }
 964
 965 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 p)
 966 {
 967         rtl_w0w1_eri(tp, addr, p, 0);
 968 }
 969
 970 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 m)
 971 {
 972         rtl_w0w1_eri(tp, addr, 0, m);
 973 }
 974
 975 static bool rtl_ocp_reg_failure(u32 reg)
 976 {
 977         return WARN_ONCE(reg & 0xffff0001, "Invalid ocp reg %x!\n", reg);
 978 }
 979
 980 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
 981 {
 982         return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
 983 }
 984
 985 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 986 {
 987         if (rtl_ocp_reg_failure(reg))
 988                 return;
 989
 990         RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
 991
 992         rtl_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
 993 }
 994
 995 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
 996 {
 997         if (rtl_ocp_reg_failure(reg))
 998                 return 0;
 999
1000         RTL_W32(tp, GPHY_OCP, reg << 15);
1001
1002         return rtl_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
1003                 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT;
1004 }
1005
1006 static void __r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1007 {
1008         if (rtl_ocp_reg_failure(reg))
1009                 return;
1010
1011         RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
1012 }
1013
1014 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1015 {
1016         unsigned long flags;
1017
1018         raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags);
1019         __r8168_mac_ocp_write(tp, reg, data);
1020         raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags);
1021 }
1022
1023 static u16 __r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
1024 {
1025         if (rtl_ocp_reg_failure(reg))
1026                 return 0;
1027
1028         RTL_W32(tp, OCPDR, reg << 15);
1029
1030         return RTL_R32(tp, OCPDR);
1031 }
1032
1033 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
1034 {
1035         unsigned long flags;
1036         u16 val;
1037
1038         raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags);
1039         val = __r8168_mac_ocp_read(tp, reg);
1040         raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags);
1041
1042         return val;
1043 }
1044
1045 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask,
1046                                  u16 set)
1047 {
1048         unsigned long flags;
1049         u16 data;
1050
1051         raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags);
1052         data = __r8168_mac_ocp_read(tp, reg);
1053         __r8168_mac_ocp_write(tp, reg, (data & ~mask) | set);
1054         raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags);
1055 }
1056
1057 /* Work around a hw issue with RTL8168g PHY, the quirk disables
1058  * PHY MCU interrupts before PHY power-down.
1059  */
1060 static void rtl8168g_phy_suspend_quirk(struct rtl8169_private *tp, int value)
1061 {
1062         switch (tp->mac_version) {
1063         case RTL_GIGA_MAC_VER_40:
1064                 if (value & BMCR_RESET || !(value & BMCR_PDOWN))
1065                         rtl_eri_set_bits(tp, 0x1a8, 0xfc000000);
1066                 else
1067                         rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000);
1068                 break;
1069         default:
1070                 break;
1071         }
1072 };
1073
1074 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
1075 {
1076         if (reg == 0x1f) {
1077                 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
1078                 return;
1079         }
1080
1081         if (tp->ocp_base != OCP_STD_PHY_BASE)
1082                 reg -= 0x10;
1083
1084         if (tp->ocp_base == OCP_STD_PHY_BASE && reg == MII_BMCR)
1085                 rtl8168g_phy_suspend_quirk(tp, value);
1086
1087         r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
1088 }
1089
1090 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
1091 {
1092         if (reg == 0x1f)
1093                 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4;
1094
1095         if (tp->ocp_base != OCP_STD_PHY_BASE)
1096                 reg -= 0x10;
1097
1098         return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
1099 }
1100
1101 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
1102 {
1103         if (reg == 0x1f) {
1104                 tp->ocp_base = value << 4;
1105                 return;
1106         }
1107
1108         r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
1109 }
1110
1111 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
1112 {
1113         return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
1114 }
1115
1116 DECLARE_RTL_COND(rtl_phyar_cond)
1117 {
1118         return RTL_R32(tp, PHYAR) & 0x80000000;
1119 }
1120
1121 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1122 {
1123         RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1124
1125         rtl_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
1126         /*
1127          * According to hardware specs a 20us delay is required after write
1128          * complete indication, but before sending next command.
1129          */
1130         udelay(20);
1131 }
1132
1133 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1134 {
1135         int value;
1136
1137         RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
1138
1139         value = rtl_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1140                 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT;
1141
1142         /*
1143          * According to hardware specs a 20us delay is required after read
1144          * complete indication, but before sending next command.
1145          */
1146         udelay(20);
1147
1148         return value;
1149 }
1150
1151 DECLARE_RTL_COND(rtl_ocpar_cond)
1152 {
1153         return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
1154 }
1155
1156 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
1157
1158 static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
1159 {
1160         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1161 }
1162
1163 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
1164 {
1165         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1166 }
1167
1168 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
1169 {
1170         r8168dp_2_mdio_start(tp);
1171
1172         r8169_mdio_write(tp, reg, value);
1173
1174         r8168dp_2_mdio_stop(tp);
1175 }
1176
1177 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1178 {
1179         int value;
1180
1181         /* Work around issue with chip reporting wrong PHY ID */
1182         if (reg == MII_PHYSID2)
1183                 return 0xc912;
1184
1185         r8168dp_2_mdio_start(tp);
1186
1187         value = r8169_mdio_read(tp, reg);
1188
1189         r8168dp_2_mdio_stop(tp);
1190
1191         return value;
1192 }
1193
1194 static void rtl_writephy(struct rtl8169_private *tp, int location, int val)
1195 {
1196         switch (tp->mac_version) {
1197         case RTL_GIGA_MAC_VER_28:
1198         case RTL_GIGA_MAC_VER_31:
1199                 r8168dp_2_mdio_write(tp, location, val);
1200                 break;
1201         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_65:
1202                 r8168g_mdio_write(tp, location, val);
1203                 break;
1204         default:
1205                 r8169_mdio_write(tp, location, val);
1206                 break;
1207         }
1208 }
1209
1210 static int rtl_readphy(struct rtl8169_private *tp, int location)
1211 {
1212         switch (tp->mac_version) {
1213         case RTL_GIGA_MAC_VER_28:
1214         case RTL_GIGA_MAC_VER_31:
1215                 return r8168dp_2_mdio_read(tp, location);
1216         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_65:
1217                 return r8168g_mdio_read(tp, location);
1218         default:
1219                 return r8169_mdio_read(tp, location);
1220         }
1221 }
1222
1223 DECLARE_RTL_COND(rtl_ephyar_cond)
1224 {
1225         return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1226 }
1227
1228 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1229 {
1230         RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1231                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1232
1233         rtl_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1234
1235         udelay(10);
1236 }
1237
1238 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1239 {
1240         RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1241
1242         return rtl_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1243                 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1244 }
1245
1246 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u16 reg)
1247 {
1248         RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff));
1249         return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1250                 RTL_R32(tp, OCPDR) : ~0;
1251 }
1252
1253 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u16 reg)
1254 {
1255         return _rtl_eri_read(tp, reg, ERIAR_OOB);
1256 }
1257
1258 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1259                               u32 data)
1260 {
1261         RTL_W32(tp, OCPDR, data);
1262         RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1263         rtl_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1264 }
1265
1266 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1267                               u32 data)
1268 {
1269         _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1270                        data, ERIAR_OOB);
1271 }
1272
1273 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd)
1274 {
1275         rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd);
1276
1277         r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001);
1278 }
1279
1280 #define OOB_CMD_RESET           0x00
1281 #define OOB_CMD_DRIVER_START    0x05
1282 #define OOB_CMD_DRIVER_STOP     0x06
1283
1284 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1285 {
1286         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1287 }
1288
1289 DECLARE_RTL_COND(rtl_dp_ocp_read_cond)
1290 {
1291         u16 reg;
1292
1293         reg = rtl8168_get_ocp_reg(tp);
1294
1295         return r8168dp_ocp_read(tp, reg) & 0x00000800;
1296 }
1297
1298 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1299 {
1300         return r8168ep_ocp_read(tp, 0x124) & 0x00000001;
1301 }
1302
1303 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1304 {
1305         return RTL_R8(tp, IBISR0) & 0x20;
1306 }
1307
1308 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1309 {
1310         RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1311         rtl_loop_wait_high(tp, &rtl_ocp_tx_cond, 50000, 2000);
1312         RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1313         RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1314 }
1315
1316 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1317 {
1318         r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START);
1319         rtl_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10000, 10);
1320 }
1321
1322 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1323 {
1324         r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1325         r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01);
1326         rtl_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10000, 30);
1327 }
1328
1329 static void rtl8168_driver_start(struct rtl8169_private *tp)
1330 {
1331         if (tp->dash_type == RTL_DASH_DP)
1332                 rtl8168dp_driver_start(tp);
1333         else
1334                 rtl8168ep_driver_start(tp);
1335 }
1336
1337 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1338 {
1339         r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1340         rtl_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10000, 10);
1341 }
1342
1343 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1344 {
1345         rtl8168ep_stop_cmac(tp);
1346         r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1347         r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01);
1348         rtl_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10000, 10);
1349 }
1350
1351 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1352 {
1353         if (tp->dash_type == RTL_DASH_DP)
1354                 rtl8168dp_driver_stop(tp);
1355         else
1356                 rtl8168ep_driver_stop(tp);
1357 }
1358
1359 static bool r8168dp_check_dash(struct rtl8169_private *tp)
1360 {
1361         u16 reg = rtl8168_get_ocp_reg(tp);
1362
1363         return r8168dp_ocp_read(tp, reg) & BIT(15);
1364 }
1365
1366 static bool r8168ep_check_dash(struct rtl8169_private *tp)
1367 {
1368         return r8168ep_ocp_read(tp, 0x128) & BIT(0);
1369 }
1370
1371 static bool rtl_dash_is_enabled(struct rtl8169_private *tp)
1372 {
1373         switch (tp->dash_type) {
1374         case RTL_DASH_DP:
1375                 return r8168dp_check_dash(tp);
1376         case RTL_DASH_EP:
1377                 return r8168ep_check_dash(tp);
1378         default:
1379                 return false;
1380         }
1381 }
1382
1383 static enum rtl_dash_type rtl_get_dash_type(struct rtl8169_private *tp)
1384 {
1385         switch (tp->mac_version) {
1386         case RTL_GIGA_MAC_VER_28:
1387         case RTL_GIGA_MAC_VER_31:
1388                 return RTL_DASH_DP;
1389         case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_53:
1390                 return RTL_DASH_EP;
1391         default:
1392                 return RTL_DASH_NONE;
1393         }
1394 }
1395
1396 static void rtl_set_d3_pll_down(struct rtl8169_private *tp, bool enable)
1397 {
1398         switch (tp->mac_version) {
1399         case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_26:
1400         case RTL_GIGA_MAC_VER_29 ... RTL_GIGA_MAC_VER_30:
1401         case RTL_GIGA_MAC_VER_32 ... RTL_GIGA_MAC_VER_37:
1402         case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_65:
1403                 if (enable)
1404                         RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~D3_NO_PLL_DOWN);
1405                 else
1406                         RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | D3_NO_PLL_DOWN);
1407                 break;
1408         default:
1409                 break;
1410         }
1411 }
1412
1413 static void rtl_reset_packet_filter(struct rtl8169_private *tp)
1414 {
1415         rtl_eri_clear_bits(tp, 0xdc, BIT(0));
1416         rtl_eri_set_bits(tp, 0xdc, BIT(0));
1417 }
1418
1419 DECLARE_RTL_COND(rtl_efusear_cond)
1420 {
1421         return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1422 }
1423
1424 u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1425 {
1426         RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1427
1428         return rtl_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1429                 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1430 }
1431
1432 static u32 rtl_get_events(struct rtl8169_private *tp)
1433 {
1434         if (rtl_is_8125(tp))
1435                 return RTL_R32(tp, IntrStatus_8125);
1436         else
1437                 return RTL_R16(tp, IntrStatus);
1438 }
1439
1440 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits)
1441 {
1442         if (rtl_is_8125(tp))
1443                 RTL_W32(tp, IntrStatus_8125, bits);
1444         else
1445                 RTL_W16(tp, IntrStatus, bits);
1446 }
1447
1448 static void rtl_irq_disable(struct rtl8169_private *tp)
1449 {
1450         if (rtl_is_8125(tp))
1451                 RTL_W32(tp, IntrMask_8125, 0);
1452         else
1453                 RTL_W16(tp, IntrMask, 0);
1454 }
1455
1456 static void rtl_irq_enable(struct rtl8169_private *tp)
1457 {
1458         if (rtl_is_8125(tp))
1459                 RTL_W32(tp, IntrMask_8125, tp->irq_mask);
1460         else
1461                 RTL_W16(tp, IntrMask, tp->irq_mask);
1462 }
1463
1464 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1465 {
1466         rtl_irq_disable(tp);
1467         rtl_ack_events(tp, 0xffffffff);
1468         rtl_pci_commit(tp);
1469 }
1470
1471 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1472 {
1473         struct phy_device *phydev = tp->phydev;
1474
1475         if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1476             tp->mac_version == RTL_GIGA_MAC_VER_38) {
1477                 if (phydev->speed == SPEED_1000) {
1478                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1479                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1480                 } else if (phydev->speed == SPEED_100) {
1481                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1482                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1483                 } else {
1484                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1485                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1486                 }
1487                 rtl_reset_packet_filter(tp);
1488         } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1489                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
1490                 if (phydev->speed == SPEED_1000) {
1491                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1492                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1493                 } else {
1494                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1495                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1496                 }
1497         } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1498                 if (phydev->speed == SPEED_10) {
1499                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02);
1500                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a);
1501                 } else {
1502                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
1503                 }
1504         }
1505 }
1506
1507 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1508
1509 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1510 {
1511         struct rtl8169_private *tp = netdev_priv(dev);
1512
1513         wol->supported = WAKE_ANY;
1514         wol->wolopts = tp->saved_wolopts;
1515 }
1516
1517 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1518 {
1519         static const struct {
1520                 u32 opt;
1521                 u16 reg;
1522                 u8  mask;
1523         } cfg[] = {
1524                 { WAKE_PHY,   Config3, LinkUp },
1525                 { WAKE_UCAST, Config5, UWF },
1526                 { WAKE_BCAST, Config5, BWF },
1527                 { WAKE_MCAST, Config5, MWF },
1528                 { WAKE_ANY,   Config5, LanWake },
1529                 { WAKE_MAGIC, Config3, MagicPacket }
1530         };
1531         unsigned int i, tmp = ARRAY_SIZE(cfg);
1532         unsigned long flags;
1533         u8 options;
1534
1535         rtl_unlock_config_regs(tp);
1536
1537         if (rtl_is_8168evl_up(tp)) {
1538                 tmp--;
1539                 if (wolopts & WAKE_MAGIC)
1540                         rtl_eri_set_bits(tp, 0x0dc, MagicPacket_v2);
1541                 else
1542                         rtl_eri_clear_bits(tp, 0x0dc, MagicPacket_v2);
1543         } else if (rtl_is_8125(tp)) {
1544                 tmp--;
1545                 if (wolopts & WAKE_MAGIC)
1546                         r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0));
1547                 else
1548                         r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0);
1549         }
1550
1551         raw_spin_lock_irqsave(&tp->config25_lock, flags);
1552         for (i = 0; i < tmp; i++) {
1553                 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
1554                 if (wolopts & cfg[i].opt)
1555                         options |= cfg[i].mask;
1556                 RTL_W8(tp, cfg[i].reg, options);
1557         }
1558         raw_spin_unlock_irqrestore(&tp->config25_lock, flags);
1559
1560         switch (tp->mac_version) {
1561         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
1562                 options = RTL_R8(tp, Config1) & ~PMEnable;
1563                 if (wolopts)
1564                         options |= PMEnable;
1565                 RTL_W8(tp, Config1, options);
1566                 break;
1567         case RTL_GIGA_MAC_VER_34:
1568         case RTL_GIGA_MAC_VER_37:
1569         case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_65:
1570                 if (wolopts)
1571                         rtl_mod_config2(tp, 0, PME_SIGNAL);
1572                 else
1573                         rtl_mod_config2(tp, PME_SIGNAL, 0);
1574                 break;
1575         default:
1576                 break;
1577         }
1578
1579         rtl_lock_config_regs(tp);
1580
1581         device_set_wakeup_enable(tp_to_dev(tp), wolopts);
1582
1583         if (!tp->dash_enabled) {
1584                 rtl_set_d3_pll_down(tp, !wolopts);
1585                 tp->dev->wol_enabled = wolopts ? 1 : 0;
1586         }
1587 }
1588
1589 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1590 {
1591         struct rtl8169_private *tp = netdev_priv(dev);
1592
1593         if (wol->wolopts & ~WAKE_ANY)
1594                 return -EINVAL;
1595
1596         tp->saved_wolopts = wol->wolopts;
1597         __rtl8169_set_wol(tp, tp->saved_wolopts);
1598
1599         return 0;
1600 }
1601
1602 static void rtl8169_get_drvinfo(struct net_device *dev,
1603                                 struct ethtool_drvinfo *info)
1604 {
1605         struct rtl8169_private *tp = netdev_priv(dev);
1606         struct rtl_fw *rtl_fw = tp->rtl_fw;
1607
1608         strscpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
1609         strscpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1610         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1611         if (rtl_fw)
1612                 strscpy(info->fw_version, rtl_fw->version,
1613                         sizeof(info->fw_version));
1614 }
1615
1616 static int rtl8169_get_regs_len(struct net_device *dev)
1617 {
1618         return R8169_REGS_SIZE;
1619 }
1620
1621 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1622         netdev_features_t features)
1623 {
1624         struct rtl8169_private *tp = netdev_priv(dev);
1625
1626         if (dev->mtu > TD_MSS_MAX)
1627                 features &= ~NETIF_F_ALL_TSO;
1628
1629         if (dev->mtu > ETH_DATA_LEN &&
1630             tp->mac_version > RTL_GIGA_MAC_VER_06)
1631                 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_ALL_TSO);
1632
1633         return features;
1634 }
1635
1636 static void rtl_set_rx_config_features(struct rtl8169_private *tp,
1637                                        netdev_features_t features)
1638 {
1639         u32 rx_config = RTL_R32(tp, RxConfig);
1640
1641         if (features & NETIF_F_RXALL)
1642                 rx_config |= RX_CONFIG_ACCEPT_ERR_MASK;
1643         else
1644                 rx_config &= ~RX_CONFIG_ACCEPT_ERR_MASK;
1645
1646         if (rtl_is_8125(tp)) {
1647                 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1648                         rx_config |= RX_VLAN_8125;
1649                 else
1650                         rx_config &= ~RX_VLAN_8125;
1651         }
1652
1653         RTL_W32(tp, RxConfig, rx_config);
1654 }
1655
1656 static int rtl8169_set_features(struct net_device *dev,
1657                                 netdev_features_t features)
1658 {
1659         struct rtl8169_private *tp = netdev_priv(dev);
1660
1661         rtl_set_rx_config_features(tp, features);
1662
1663         if (features & NETIF_F_RXCSUM)
1664                 tp->cp_cmd |= RxChkSum;
1665         else
1666                 tp->cp_cmd &= ~RxChkSum;
1667
1668         if (!rtl_is_8125(tp)) {
1669                 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1670                         tp->cp_cmd |= RxVlan;
1671                 else
1672                         tp->cp_cmd &= ~RxVlan;
1673         }
1674
1675         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1676         rtl_pci_commit(tp);
1677
1678         return 0;
1679 }
1680
1681 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1682 {
1683         return (skb_vlan_tag_present(skb)) ?
1684                 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1685 }
1686
1687 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1688 {
1689         u32 opts2 = le32_to_cpu(desc->opts2);
1690
1691         if (opts2 & RxVlanTag)
1692                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1693 }
1694
1695 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1696                              void *p)
1697 {
1698         struct rtl8169_private *tp = netdev_priv(dev);
1699         u32 __iomem *data = tp->mmio_addr;
1700         u32 *dw = p;
1701         int i;
1702
1703         for (i = 0; i < R8169_REGS_SIZE; i += 4)
1704                 memcpy_fromio(dw++, data++, 4);
1705 }
1706
1707 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1708         "tx_packets",
1709         "rx_packets",
1710         "tx_errors",
1711         "rx_errors",
1712         "rx_missed",
1713         "align_errors",
1714         "tx_single_collisions",
1715         "tx_multi_collisions",
1716         "unicast",
1717         "broadcast",
1718         "multicast",
1719         "tx_aborted",
1720         "tx_underrun",
1721 };
1722
1723 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1724 {
1725         switch (sset) {
1726         case ETH_SS_STATS:
1727                 return ARRAY_SIZE(rtl8169_gstrings);
1728         default:
1729                 return -EOPNOTSUPP;
1730         }
1731 }
1732
1733 DECLARE_RTL_COND(rtl_counters_cond)
1734 {
1735         return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
1736 }
1737
1738 static void rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
1739 {
1740         u32 cmd = lower_32_bits(tp->counters_phys_addr);
1741
1742         RTL_W32(tp, CounterAddrHigh, upper_32_bits(tp->counters_phys_addr));
1743         rtl_pci_commit(tp);
1744         RTL_W32(tp, CounterAddrLow, cmd);
1745         RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
1746
1747         rtl_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
1748 }
1749
1750 static void rtl8169_update_counters(struct rtl8169_private *tp)
1751 {
1752         u8 val = RTL_R8(tp, ChipCmd);
1753
1754         /*
1755          * Some chips are unable to dump tally counters when the receiver
1756          * is disabled. If 0xff chip may be in a PCI power-save state.
1757          */
1758         if (val & CmdRxEnb && val != 0xff)
1759                 rtl8169_do_counters(tp, CounterDump);
1760 }
1761
1762 static void rtl8169_init_counter_offsets(struct rtl8169_private *tp)
1763 {
1764         struct rtl8169_counters *counters = tp->counters;
1765
1766         /*
1767          * rtl8169_init_counter_offsets is called from rtl_open.  On chip
1768          * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1769          * reset by a power cycle, while the counter values collected by the
1770          * driver are reset at every driver unload/load cycle.
1771          *
1772          * To make sure the HW values returned by @get_stats64 match the SW
1773          * values, we collect the initial values at first open(*) and use them
1774          * as offsets to normalize the values returned by @get_stats64.
1775          *
1776          * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1777          * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1778          * set at open time by rtl_hw_start.
1779          */
1780
1781         if (tp->tc_offset.inited)
1782                 return;
1783
1784         if (tp->mac_version >= RTL_GIGA_MAC_VER_19) {
1785                 rtl8169_do_counters(tp, CounterReset);
1786         } else {
1787                 rtl8169_update_counters(tp);
1788                 tp->tc_offset.tx_errors = counters->tx_errors;
1789                 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1790                 tp->tc_offset.tx_aborted = counters->tx_aborted;
1791                 tp->tc_offset.rx_missed = counters->rx_missed;
1792         }
1793
1794         tp->tc_offset.inited = true;
1795 }
1796
1797 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1798                                       struct ethtool_stats *stats, u64 *data)
1799 {
1800         struct rtl8169_private *tp = netdev_priv(dev);
1801         struct rtl8169_counters *counters;
1802
1803         counters = tp->counters;
1804         rtl8169_update_counters(tp);
1805
1806         data[0] = le64_to_cpu(counters->tx_packets);
1807         data[1] = le64_to_cpu(counters->rx_packets);
1808         data[2] = le64_to_cpu(counters->tx_errors);
1809         data[3] = le32_to_cpu(counters->rx_errors);
1810         data[4] = le16_to_cpu(counters->rx_missed);
1811         data[5] = le16_to_cpu(counters->align_errors);
1812         data[6] = le32_to_cpu(counters->tx_one_collision);
1813         data[7] = le32_to_cpu(counters->tx_multi_collision);
1814         data[8] = le64_to_cpu(counters->rx_unicast);
1815         data[9] = le64_to_cpu(counters->rx_broadcast);
1816         data[10] = le32_to_cpu(counters->rx_multicast);
1817         data[11] = le16_to_cpu(counters->tx_aborted);
1818         data[12] = le16_to_cpu(counters->tx_underun);
1819 }
1820
1821 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1822 {
1823         switch(stringset) {
1824         case ETH_SS_STATS:
1825                 memcpy(data, rtl8169_gstrings, sizeof(rtl8169_gstrings));
1826                 break;
1827         }
1828 }
1829
1830 /*
1831  * Interrupt coalescing
1832  *
1833  * > 1 - the availability of the IntrMitigate (0xe2) register through the
1834  * >     8169, 8168 and 810x line of chipsets
1835  *
1836  * 8169, 8168, and 8136(810x) serial chipsets support it.
1837  *
1838  * > 2 - the Tx timer unit at gigabit speed
1839  *
1840  * The unit of the timer depends on both the speed and the setting of CPlusCmd
1841  * (0xe0) bit 1 and bit 0.
1842  *
1843  * For 8169
1844  * bit[1:0] \ speed        1000M           100M            10M
1845  * 0 0                     320ns           2.56us          40.96us
1846  * 0 1                     2.56us          20.48us         327.7us
1847  * 1 0                     5.12us          40.96us         655.4us
1848  * 1 1                     10.24us         81.92us         1.31ms
1849  *
1850  * For the other
1851  * bit[1:0] \ speed        1000M           100M            10M
1852  * 0 0                     5us             2.56us          40.96us
1853  * 0 1                     40us            20.48us         327.7us
1854  * 1 0                     80us            40.96us         655.4us
1855  * 1 1                     160us           81.92us         1.31ms
1856  */
1857
1858 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
1859 struct rtl_coalesce_info {
1860         u32 speed;
1861         u32 scale_nsecs[4];
1862 };
1863
1864 /* produce array with base delay *1, *8, *8*2, *8*2*2 */
1865 #define COALESCE_DELAY(d) { (d), 8 * (d), 16 * (d), 32 * (d) }
1866
1867 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1868         { SPEED_1000,   COALESCE_DELAY(320) },
1869         { SPEED_100,    COALESCE_DELAY(2560) },
1870         { SPEED_10,     COALESCE_DELAY(40960) },
1871         { 0 },
1872 };
1873
1874 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1875         { SPEED_1000,   COALESCE_DELAY(5000) },
1876         { SPEED_100,    COALESCE_DELAY(2560) },
1877         { SPEED_10,     COALESCE_DELAY(40960) },
1878         { 0 },
1879 };
1880 #undef COALESCE_DELAY
1881
1882 /* get rx/tx scale vector corresponding to current speed */
1883 static const struct rtl_coalesce_info *
1884 rtl_coalesce_info(struct rtl8169_private *tp)
1885 {
1886         const struct rtl_coalesce_info *ci;
1887
1888         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1889                 ci = rtl_coalesce_info_8169;
1890         else
1891                 ci = rtl_coalesce_info_8168_8136;
1892
1893         /* if speed is unknown assume highest one */
1894         if (tp->phydev->speed == SPEED_UNKNOWN)
1895                 return ci;
1896
1897         for (; ci->speed; ci++) {
1898                 if (tp->phydev->speed == ci->speed)
1899                         return ci;
1900         }
1901
1902         return ERR_PTR(-ELNRNG);
1903 }
1904
1905 static int rtl_get_coalesce(struct net_device *dev,
1906                             struct ethtool_coalesce *ec,
1907                             struct kernel_ethtool_coalesce *kernel_coal,
1908                             struct netlink_ext_ack *extack)
1909 {
1910         struct rtl8169_private *tp = netdev_priv(dev);
1911         const struct rtl_coalesce_info *ci;
1912         u32 scale, c_us, c_fr;
1913         u16 intrmit;
1914
1915         if (rtl_is_8125(tp))
1916                 return -EOPNOTSUPP;
1917
1918         memset(ec, 0, sizeof(*ec));
1919
1920         /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1921         ci = rtl_coalesce_info(tp);
1922         if (IS_ERR(ci))
1923                 return PTR_ERR(ci);
1924
1925         scale = ci->scale_nsecs[tp->cp_cmd & INTT_MASK];
1926
1927         intrmit = RTL_R16(tp, IntrMitigate);
1928
1929         c_us = FIELD_GET(RTL_COALESCE_TX_USECS, intrmit);
1930         ec->tx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000);
1931
1932         c_fr = FIELD_GET(RTL_COALESCE_TX_FRAMES, intrmit);
1933         /* ethtool_coalesce states usecs and max_frames must not both be 0 */
1934         ec->tx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1;
1935
1936         c_us = FIELD_GET(RTL_COALESCE_RX_USECS, intrmit);
1937         ec->rx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000);
1938
1939         c_fr = FIELD_GET(RTL_COALESCE_RX_FRAMES, intrmit);
1940         ec->rx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1;
1941
1942         return 0;
1943 }
1944
1945 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, usec) */
1946 static int rtl_coalesce_choose_scale(struct rtl8169_private *tp, u32 usec,
1947                                      u16 *cp01)
1948 {
1949         const struct rtl_coalesce_info *ci;
1950         u16 i;
1951
1952         ci = rtl_coalesce_info(tp);
1953         if (IS_ERR(ci))
1954                 return PTR_ERR(ci);
1955
1956         for (i = 0; i < 4; i++) {
1957                 if (usec <= ci->scale_nsecs[i] * RTL_COALESCE_T_MAX / 1000U) {
1958                         *cp01 = i;
1959                         return ci->scale_nsecs[i];
1960                 }
1961         }
1962
1963         return -ERANGE;
1964 }
1965
1966 static int rtl_set_coalesce(struct net_device *dev,
1967                             struct ethtool_coalesce *ec,
1968                             struct kernel_ethtool_coalesce *kernel_coal,
1969                             struct netlink_ext_ack *extack)
1970 {
1971         struct rtl8169_private *tp = netdev_priv(dev);
1972         u32 tx_fr = ec->tx_max_coalesced_frames;
1973         u32 rx_fr = ec->rx_max_coalesced_frames;
1974         u32 coal_usec_max, units;
1975         u16 w = 0, cp01 = 0;
1976         int scale;
1977
1978         if (rtl_is_8125(tp))
1979                 return -EOPNOTSUPP;
1980
1981         if (rx_fr > RTL_COALESCE_FRAME_MAX || tx_fr > RTL_COALESCE_FRAME_MAX)
1982                 return -ERANGE;
1983
1984         coal_usec_max = max(ec->rx_coalesce_usecs, ec->tx_coalesce_usecs);
1985         scale = rtl_coalesce_choose_scale(tp, coal_usec_max, &cp01);
1986         if (scale < 0)
1987                 return scale;
1988
1989         /* Accept max_frames=1 we returned in rtl_get_coalesce. Accept it
1990          * not only when usecs=0 because of e.g. the following scenario:
1991          *
1992          * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
1993          * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
1994          * - then user does `ethtool -C eth0 rx-usecs 100`
1995          *
1996          * Since ethtool sends to kernel whole ethtool_coalesce settings,
1997          * if we want to ignore rx_frames then it has to be set to 0.
1998          */
1999         if (rx_fr == 1)
2000                 rx_fr = 0;
2001         if (tx_fr == 1)
2002                 tx_fr = 0;
2003
2004         /* HW requires time limit to be set if frame limit is set */
2005         if ((tx_fr && !ec->tx_coalesce_usecs) ||
2006             (rx_fr && !ec->rx_coalesce_usecs))
2007                 return -EINVAL;
2008
2009         w |= FIELD_PREP(RTL_COALESCE_TX_FRAMES, DIV_ROUND_UP(tx_fr, 4));
2010         w |= FIELD_PREP(RTL_COALESCE_RX_FRAMES, DIV_ROUND_UP(rx_fr, 4));
2011
2012         units = DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000U, scale);
2013         w |= FIELD_PREP(RTL_COALESCE_TX_USECS, units);
2014         units = DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000U, scale);
2015         w |= FIELD_PREP(RTL_COALESCE_RX_USECS, units);
2016
2017         RTL_W16(tp, IntrMitigate, w);
2018
2019         /* Meaning of PktCntrDisable bit changed from RTL8168e-vl */
2020         if (rtl_is_8168evl_up(tp)) {
2021                 if (!rx_fr && !tx_fr)
2022                         /* disable packet counter */
2023                         tp->cp_cmd |= PktCntrDisable;
2024                 else
2025                         tp->cp_cmd &= ~PktCntrDisable;
2026         }
2027
2028         tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
2029         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
2030         rtl_pci_commit(tp);
2031
2032         return 0;
2033 }
2034
2035 static void rtl_set_eee_txidle_timer(struct rtl8169_private *tp)
2036 {
2037         unsigned int timer_val = READ_ONCE(tp->dev->mtu) + ETH_HLEN + 0x20;
2038
2039         switch (tp->mac_version) {
2040         case RTL_GIGA_MAC_VER_61:
2041         case RTL_GIGA_MAC_VER_63:
2042         case RTL_GIGA_MAC_VER_65:
2043                 tp->tx_lpi_timer = timer_val;
2044                 RTL_W16(tp, EEE_TXIDLE_TIMER_8125, timer_val);
2045                 break;
2046         default:
2047                 break;
2048         }
2049 }
2050
2051 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_keee *data)
2052 {
2053         struct rtl8169_private *tp = netdev_priv(dev);
2054
2055         if (!rtl_supports_eee(tp))
2056                 return -EOPNOTSUPP;
2057
2058         return phy_ethtool_get_eee(tp->phydev, data);
2059 }
2060
2061 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_keee *data)
2062 {
2063         struct rtl8169_private *tp = netdev_priv(dev);
2064
2065         if (!rtl_supports_eee(tp))
2066                 return -EOPNOTSUPP;
2067
2068         return phy_ethtool_set_eee(tp->phydev, data);
2069 }
2070
2071 static void rtl8169_get_ringparam(struct net_device *dev,
2072                                   struct ethtool_ringparam *data,
2073                                   struct kernel_ethtool_ringparam *kernel_data,
2074                                   struct netlink_ext_ack *extack)
2075 {
2076         data->rx_max_pending = NUM_RX_DESC;
2077         data->rx_pending = NUM_RX_DESC;
2078         data->tx_max_pending = NUM_TX_DESC;
2079         data->tx_pending = NUM_TX_DESC;
2080 }
2081
2082 static void rtl8169_get_pauseparam(struct net_device *dev,
2083                                    struct ethtool_pauseparam *data)
2084 {
2085         struct rtl8169_private *tp = netdev_priv(dev);
2086         bool tx_pause, rx_pause;
2087
2088         phy_get_pause(tp->phydev, &tx_pause, &rx_pause);
2089
2090         data->autoneg = tp->phydev->autoneg;
2091         data->tx_pause = tx_pause ? 1 : 0;
2092         data->rx_pause = rx_pause ? 1 : 0;
2093 }
2094
2095 static int rtl8169_set_pauseparam(struct net_device *dev,
2096                                   struct ethtool_pauseparam *data)
2097 {
2098         struct rtl8169_private *tp = netdev_priv(dev);
2099
2100         if (dev->mtu > ETH_DATA_LEN)
2101                 return -EOPNOTSUPP;
2102
2103         phy_set_asym_pause(tp->phydev, data->rx_pause, data->tx_pause);
2104
2105         return 0;
2106 }
2107
2108 static const struct ethtool_ops rtl8169_ethtool_ops = {
2109         .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
2110                                      ETHTOOL_COALESCE_MAX_FRAMES,
2111         .get_drvinfo            = rtl8169_get_drvinfo,
2112         .get_regs_len           = rtl8169_get_regs_len,
2113         .get_link               = ethtool_op_get_link,
2114         .get_coalesce           = rtl_get_coalesce,
2115         .set_coalesce           = rtl_set_coalesce,
2116         .get_regs               = rtl8169_get_regs,
2117         .get_wol                = rtl8169_get_wol,
2118         .set_wol                = rtl8169_set_wol,
2119         .get_strings            = rtl8169_get_strings,
2120         .get_sset_count         = rtl8169_get_sset_count,
2121         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
2122         .get_ts_info            = ethtool_op_get_ts_info,
2123         .nway_reset             = phy_ethtool_nway_reset,
2124         .get_eee                = rtl8169_get_eee,
2125         .set_eee                = rtl8169_set_eee,
2126         .get_link_ksettings     = phy_ethtool_get_link_ksettings,
2127         .set_link_ksettings     = phy_ethtool_set_link_ksettings,
2128         .get_ringparam          = rtl8169_get_ringparam,
2129         .get_pauseparam         = rtl8169_get_pauseparam,
2130         .set_pauseparam         = rtl8169_set_pauseparam,
2131 };
2132
2133 static enum mac_version rtl8169_get_mac_version(u16 xid, bool gmii)
2134 {
2135         /*
2136          * The driver currently handles the 8168Bf and the 8168Be identically
2137          * but they can be identified more specifically through the test below
2138          * if needed:
2139          *
2140          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2141          *
2142          * Same thing for the 8101Eb and the 8101Ec:
2143          *
2144          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2145          */
2146         static const struct rtl_mac_info {
2147                 u16 mask;
2148                 u16 val;
2149                 enum mac_version ver;
2150         } mac_info[] = {
2151                 /* 8126A family. */
2152                 { 0x7cf, 0x649, RTL_GIGA_MAC_VER_65 },
2153
2154                 /* 8125B family. */
2155                 { 0x7cf, 0x641, RTL_GIGA_MAC_VER_63 },
2156
2157                 /* 8125A family. */
2158                 { 0x7cf, 0x609, RTL_GIGA_MAC_VER_61 },
2159                 /* It seems only XID 609 made it to the mass market.
2160                  * { 0x7cf, 0x608,      RTL_GIGA_MAC_VER_60 },
2161                  * { 0x7c8, 0x608,      RTL_GIGA_MAC_VER_61 },
2162                  */
2163
2164                 /* RTL8117 */
2165                 { 0x7cf, 0x54b, RTL_GIGA_MAC_VER_53 },
2166                 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52 },
2167
2168                 /* 8168EP family. */
2169                 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 },
2170                 /* It seems this chip version never made it to
2171                  * the wild. Let's disable detection.
2172                  * { 0x7cf, 0x501,      RTL_GIGA_MAC_VER_50 },
2173                  * { 0x7cf, 0x500,      RTL_GIGA_MAC_VER_49 },
2174                  */
2175
2176                 /* 8168H family. */
2177                 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 },
2178                 /* It seems this chip version never made it to
2179                  * the wild. Let's disable detection.
2180                  * { 0x7cf, 0x540,      RTL_GIGA_MAC_VER_45 },
2181                  */
2182
2183                 /* 8168G family. */
2184                 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 },
2185                 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 },
2186                 /* It seems this chip version never made it to
2187                  * the wild. Let's disable detection.
2188                  * { 0x7cf, 0x4c1,      RTL_GIGA_MAC_VER_41 },
2189                  */
2190                 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 },
2191
2192                 /* 8168F family. */
2193                 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 },
2194                 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 },
2195                 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 },
2196
2197                 /* 8168E family. */
2198                 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 },
2199                 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 },
2200                 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 },
2201
2202                 /* 8168D family. */
2203                 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 },
2204                 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 },
2205
2206                 /* 8168DP family. */
2207                 /* It seems this early RTL8168dp version never made it to
2208                  * the wild. Support has been removed.
2209                  * { 0x7cf, 0x288,      RTL_GIGA_MAC_VER_27 },
2210                  */
2211                 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 },
2212                 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 },
2213
2214                 /* 8168C family. */
2215                 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 },
2216                 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 },
2217                 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 },
2218                 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 },
2219                 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 },
2220                 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 },
2221                 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 },
2222
2223                 /* 8168B family. */
2224                 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 },
2225                 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 },
2226
2227                 /* 8101 family. */
2228                 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 },
2229                 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 },
2230                 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 },
2231                 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 },
2232                 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 },
2233                 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 },
2234                 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 },
2235                 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 },
2236                 { 0x7cf, 0x240, RTL_GIGA_MAC_VER_14 },
2237                 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 },
2238                 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 },
2239                 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_10 },
2240
2241                 /* 8110 family. */
2242                 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 },
2243                 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 },
2244                 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 },
2245                 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 },
2246                 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 },
2247
2248                 /* Catch-all */
2249                 { 0x000, 0x000, RTL_GIGA_MAC_NONE   }
2250         };
2251         const struct rtl_mac_info *p = mac_info;
2252         enum mac_version ver;
2253
2254         while ((xid & p->mask) != p->val)
2255                 p++;
2256         ver = p->ver;
2257
2258         if (ver != RTL_GIGA_MAC_NONE && !gmii) {
2259                 if (ver == RTL_GIGA_MAC_VER_42)
2260                         ver = RTL_GIGA_MAC_VER_43;
2261                 else if (ver == RTL_GIGA_MAC_VER_46)
2262                         ver = RTL_GIGA_MAC_VER_48;
2263         }
2264
2265         return ver;
2266 }
2267
2268 static void rtl_release_firmware(struct rtl8169_private *tp)
2269 {
2270         if (tp->rtl_fw) {
2271                 rtl_fw_release_firmware(tp->rtl_fw);
2272                 kfree(tp->rtl_fw);
2273                 tp->rtl_fw = NULL;
2274         }
2275 }
2276
2277 void r8169_apply_firmware(struct rtl8169_private *tp)
2278 {
2279         int val;
2280
2281         /* TODO: release firmware if rtl_fw_write_firmware signals failure. */
2282         if (tp->rtl_fw) {
2283                 rtl_fw_write_firmware(tp, tp->rtl_fw);
2284                 /* At least one firmware doesn't reset tp->ocp_base. */
2285                 tp->ocp_base = OCP_STD_PHY_BASE;
2286
2287                 /* PHY soft reset may still be in progress */
2288                 phy_read_poll_timeout(tp->phydev, MII_BMCR, val,
2289                                       !(val & BMCR_RESET),
2290                                       50000, 600000, true);
2291         }
2292 }
2293
2294 static void rtl8168_config_eee_mac(struct rtl8169_private *tp)
2295 {
2296         /* Adjust EEE LED frequency */
2297         if (tp->mac_version != RTL_GIGA_MAC_VER_38)
2298                 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
2299
2300         rtl_eri_set_bits(tp, 0x1b0, 0x0003);
2301 }
2302
2303 static void rtl8125a_config_eee_mac(struct rtl8169_private *tp)
2304 {
2305         r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0));
2306         r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1));
2307 }
2308
2309 static void rtl8125b_config_eee_mac(struct rtl8169_private *tp)
2310 {
2311         r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0));
2312 }
2313
2314 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, const u8 *addr)
2315 {
2316         rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, get_unaligned_le32(addr));
2317         rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, get_unaligned_le16(addr + 4));
2318         rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, get_unaligned_le16(addr) << 16);
2319         rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, get_unaligned_le32(addr + 2));
2320 }
2321
2322 u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp)
2323 {
2324         u16 data1, data2, ioffset;
2325
2326         r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
2327         data1 = r8168_mac_ocp_read(tp, 0xdd02);
2328         data2 = r8168_mac_ocp_read(tp, 0xdd00);
2329
2330         ioffset = (data2 >> 1) & 0x7ff8;
2331         ioffset |= data2 & 0x0007;
2332         if (data1 & BIT(7))
2333                 ioffset |= BIT(15);
2334
2335         return ioffset;
2336 }
2337
2338 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
2339 {
2340         if (!test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
2341                 return;
2342
2343         set_bit(flag, tp->wk.flags);
2344         schedule_work(&tp->wk.work);
2345 }
2346
2347 static void rtl8169_init_phy(struct rtl8169_private *tp)
2348 {
2349         r8169_hw_phy_config(tp, tp->phydev, tp->mac_version);
2350
2351         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2352                 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2353                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
2354                 /* set undocumented MAC Reg C+CR Offset 0x82h */
2355                 RTL_W8(tp, 0x82, 0x01);
2356         }
2357
2358         if (tp->mac_version == RTL_GIGA_MAC_VER_05 &&
2359             tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE &&
2360             tp->pci_dev->subsystem_device == 0xe000)
2361                 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b);
2362
2363         /* We may have called phy_speed_down before */
2364         phy_speed_up(tp->phydev);
2365
2366         genphy_soft_reset(tp->phydev);
2367 }
2368
2369 static void rtl_rar_set(struct rtl8169_private *tp, const u8 *addr)
2370 {
2371         rtl_unlock_config_regs(tp);
2372
2373         RTL_W32(tp, MAC4, get_unaligned_le16(addr + 4));
2374         rtl_pci_commit(tp);
2375
2376         RTL_W32(tp, MAC0, get_unaligned_le32(addr));
2377         rtl_pci_commit(tp);
2378
2379         if (tp->mac_version == RTL_GIGA_MAC_VER_34)
2380                 rtl_rar_exgmac_set(tp, addr);
2381
2382         rtl_lock_config_regs(tp);
2383 }
2384
2385 static int rtl_set_mac_address(struct net_device *dev, void *p)
2386 {
2387         struct rtl8169_private *tp = netdev_priv(dev);
2388         int ret;
2389
2390         ret = eth_mac_addr(dev, p);
2391         if (ret)
2392                 return ret;
2393
2394         rtl_rar_set(tp, dev->dev_addr);
2395
2396         return 0;
2397 }
2398
2399 static void rtl_init_rxcfg(struct rtl8169_private *tp)
2400 {
2401         switch (tp->mac_version) {
2402         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
2403         case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
2404                 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
2405                 break;
2406         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
2407         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
2408         case RTL_GIGA_MAC_VER_38:
2409                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
2410                 break;
2411         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53:
2412                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
2413                 break;
2414         case RTL_GIGA_MAC_VER_61:
2415                 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST);
2416                 break;
2417         case RTL_GIGA_MAC_VER_63:
2418         case RTL_GIGA_MAC_VER_65:
2419                 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST |
2420                         RX_PAUSE_SLOT_ON);
2421                 break;
2422         default:
2423                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
2424                 break;
2425         }
2426 }
2427
2428 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2429 {
2430         tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
2431 }
2432
2433 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
2434 {
2435         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2436         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
2437 }
2438
2439 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
2440 {
2441         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2442         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
2443 }
2444
2445 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
2446 {
2447         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2448 }
2449
2450 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
2451 {
2452         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2453 }
2454
2455 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
2456 {
2457         RTL_W8(tp, MaxTxPacketSize, 0x24);
2458         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2459         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
2460 }
2461
2462 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
2463 {
2464         RTL_W8(tp, MaxTxPacketSize, 0x3f);
2465         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2466         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
2467 }
2468
2469 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
2470 {
2471         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
2472 }
2473
2474 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
2475 {
2476         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
2477 }
2478
2479 static void rtl_jumbo_config(struct rtl8169_private *tp)
2480 {
2481         bool jumbo = tp->dev->mtu > ETH_DATA_LEN;
2482         int readrq = 4096;
2483
2484         rtl_unlock_config_regs(tp);
2485         switch (tp->mac_version) {
2486         case RTL_GIGA_MAC_VER_17:
2487                 if (jumbo) {
2488                         readrq = 512;
2489                         r8168b_1_hw_jumbo_enable(tp);
2490                 } else {
2491                         r8168b_1_hw_jumbo_disable(tp);
2492                 }
2493                 break;
2494         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26:
2495                 if (jumbo) {
2496                         readrq = 512;
2497                         r8168c_hw_jumbo_enable(tp);
2498                 } else {
2499                         r8168c_hw_jumbo_disable(tp);
2500                 }
2501                 break;
2502         case RTL_GIGA_MAC_VER_28:
2503                 if (jumbo)
2504                         r8168dp_hw_jumbo_enable(tp);
2505                 else
2506                         r8168dp_hw_jumbo_disable(tp);
2507                 break;
2508         case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33:
2509                 if (jumbo)
2510                         r8168e_hw_jumbo_enable(tp);
2511                 else
2512                         r8168e_hw_jumbo_disable(tp);
2513                 break;
2514         default:
2515                 break;
2516         }
2517         rtl_lock_config_regs(tp);
2518
2519         if (pci_is_pcie(tp->pci_dev) && tp->supports_gmii)
2520                 pcie_set_readrq(tp->pci_dev, readrq);
2521
2522         /* Chip doesn't support pause in jumbo mode */
2523         if (jumbo) {
2524                 linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT,
2525                                    tp->phydev->advertising);
2526                 linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
2527                                    tp->phydev->advertising);
2528                 phy_start_aneg(tp->phydev);
2529         }
2530 }
2531
2532 DECLARE_RTL_COND(rtl_chipcmd_cond)
2533 {
2534         return RTL_R8(tp, ChipCmd) & CmdReset;
2535 }
2536
2537 static void rtl_hw_reset(struct rtl8169_private *tp)
2538 {
2539         RTL_W8(tp, ChipCmd, CmdReset);
2540
2541         rtl_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
2542 }
2543
2544 static void rtl_request_firmware(struct rtl8169_private *tp)
2545 {
2546         struct rtl_fw *rtl_fw;
2547
2548         /* firmware loaded already or no firmware available */
2549         if (tp->rtl_fw || !tp->fw_name)
2550                 return;
2551
2552         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
2553         if (!rtl_fw)
2554                 return;
2555
2556         rtl_fw->phy_write = rtl_writephy;
2557         rtl_fw->phy_read = rtl_readphy;
2558         rtl_fw->mac_mcu_write = mac_mcu_write;
2559         rtl_fw->mac_mcu_read = mac_mcu_read;
2560         rtl_fw->fw_name = tp->fw_name;
2561         rtl_fw->dev = tp_to_dev(tp);
2562
2563         if (rtl_fw_request_firmware(rtl_fw))
2564                 kfree(rtl_fw);
2565         else
2566                 tp->rtl_fw = rtl_fw;
2567 }
2568
2569 static void rtl_rx_close(struct rtl8169_private *tp)
2570 {
2571         RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
2572 }
2573
2574 DECLARE_RTL_COND(rtl_npq_cond)
2575 {
2576         return RTL_R8(tp, TxPoll) & NPQ;
2577 }
2578
2579 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
2580 {
2581         return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
2582 }
2583
2584 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
2585 {
2586         return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
2587 }
2588
2589 DECLARE_RTL_COND(rtl_rxtx_empty_cond_2)
2590 {
2591         /* IntrMitigate has new functionality on RTL8125 */
2592         return (RTL_R16(tp, IntrMitigate) & 0x0103) == 0x0103;
2593 }
2594
2595 static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp)
2596 {
2597         switch (tp->mac_version) {
2598         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53:
2599                 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42);
2600                 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2601                 break;
2602         case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_61:
2603                 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2604                 break;
2605         case RTL_GIGA_MAC_VER_63 ... RTL_GIGA_MAC_VER_65:
2606                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
2607                 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2608                 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond_2, 100, 42);
2609                 break;
2610         default:
2611                 break;
2612         }
2613 }
2614
2615 static void rtl_disable_rxdvgate(struct rtl8169_private *tp)
2616 {
2617         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
2618 }
2619
2620 static void rtl_enable_rxdvgate(struct rtl8169_private *tp)
2621 {
2622         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
2623         fsleep(2000);
2624         rtl_wait_txrx_fifo_empty(tp);
2625 }
2626
2627 static void rtl_wol_enable_rx(struct rtl8169_private *tp)
2628 {
2629         if (tp->mac_version >= RTL_GIGA_MAC_VER_25)
2630                 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
2631                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
2632
2633         if (tp->mac_version >= RTL_GIGA_MAC_VER_40)
2634                 rtl_disable_rxdvgate(tp);
2635 }
2636
2637 static void rtl_prepare_power_down(struct rtl8169_private *tp)
2638 {
2639         if (tp->dash_enabled)
2640                 return;
2641
2642         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
2643             tp->mac_version == RTL_GIGA_MAC_VER_33)
2644                 rtl_ephy_write(tp, 0x19, 0xff64);
2645
2646         if (device_may_wakeup(tp_to_dev(tp))) {
2647                 phy_speed_down(tp->phydev, false);
2648                 rtl_wol_enable_rx(tp);
2649         }
2650 }
2651
2652 static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
2653 {
2654         u32 val = TX_DMA_BURST << TxDMAShift |
2655                   InterFrameGap << TxInterFrameGapShift;
2656
2657         if (rtl_is_8168evl_up(tp))
2658                 val |= TXCFG_AUTO_FIFO;
2659
2660         RTL_W32(tp, TxConfig, val);
2661 }
2662
2663 static void rtl_set_rx_max_size(struct rtl8169_private *tp)
2664 {
2665         /* Low hurts. Let's disable the filtering. */
2666         RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
2667 }
2668
2669 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
2670 {
2671         /*
2672          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
2673          * register to be written before TxDescAddrLow to work.
2674          * Switching from MMIO to I/O access fixes the issue as well.
2675          */
2676         RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
2677         RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
2678         RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
2679         RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
2680 }
2681
2682 static void rtl8169_set_magic_reg(struct rtl8169_private *tp)
2683 {
2684         u32 val;
2685
2686         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
2687                 val = 0x000fff00;
2688         else if (tp->mac_version == RTL_GIGA_MAC_VER_06)
2689                 val = 0x00ffff00;
2690         else
2691                 return;
2692
2693         if (RTL_R8(tp, Config2) & PCI_Clock_66MHz)
2694                 val |= 0xff;
2695
2696         RTL_W32(tp, 0x7c, val);
2697 }
2698
2699 static void rtl_set_rx_mode(struct net_device *dev)
2700 {
2701         u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast;
2702         /* Multicast hash filter */
2703         u32 mc_filter[2] = { 0xffffffff, 0xffffffff };
2704         struct rtl8169_private *tp = netdev_priv(dev);
2705         u32 tmp;
2706
2707         if (dev->flags & IFF_PROMISC) {
2708                 rx_mode |= AcceptAllPhys;
2709         } else if (!(dev->flags & IFF_MULTICAST)) {
2710                 rx_mode &= ~AcceptMulticast;
2711         } else if (dev->flags & IFF_ALLMULTI ||
2712                    tp->mac_version == RTL_GIGA_MAC_VER_35) {
2713                 /* accept all multicasts */
2714         } else if (netdev_mc_empty(dev)) {
2715                 rx_mode &= ~AcceptMulticast;
2716         } else {
2717                 struct netdev_hw_addr *ha;
2718
2719                 mc_filter[1] = mc_filter[0] = 0;
2720                 netdev_for_each_mc_addr(ha, dev) {
2721                         u32 bit_nr = eth_hw_addr_crc(ha) >> 26;
2722                         mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31);
2723                 }
2724
2725                 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
2726                         tmp = mc_filter[0];
2727                         mc_filter[0] = swab32(mc_filter[1]);
2728                         mc_filter[1] = swab32(tmp);
2729                 }
2730         }
2731
2732         RTL_W32(tp, MAR0 + 4, mc_filter[1]);
2733         RTL_W32(tp, MAR0 + 0, mc_filter[0]);
2734
2735         tmp = RTL_R32(tp, RxConfig);
2736         RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode);
2737 }
2738
2739 DECLARE_RTL_COND(rtl_csiar_cond)
2740 {
2741         return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
2742 }
2743
2744 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
2745 {
2746         u32 func = PCI_FUNC(tp->pci_dev->devfn);
2747
2748         RTL_W32(tp, CSIDR, value);
2749         RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
2750                 CSIAR_BYTE_ENABLE | func << 16);
2751
2752         rtl_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
2753 }
2754
2755 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
2756 {
2757         u32 func = PCI_FUNC(tp->pci_dev->devfn);
2758
2759         RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
2760                 CSIAR_BYTE_ENABLE);
2761
2762         return rtl_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
2763                 RTL_R32(tp, CSIDR) : ~0;
2764 }
2765
2766 static void rtl_set_aspm_entry_latency(struct rtl8169_private *tp, u8 val)
2767 {
2768         struct pci_dev *pdev = tp->pci_dev;
2769         u32 csi;
2770
2771         /* According to Realtek the value at config space address 0x070f
2772          * controls the L0s/L1 entrance latency. We try standard ECAM access
2773          * first and if it fails fall back to CSI.
2774          * bit 0..2: L0: 0 = 1us, 1 = 2us .. 6 = 7us, 7 = 7us (no typo)
2775          * bit 3..5: L1: 0 = 1us, 1 = 2us .. 6 = 64us, 7 = 64us
2776          */
2777         if (pdev->cfg_size > 0x070f &&
2778             pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
2779                 return;
2780
2781         netdev_notice_once(tp->dev,
2782                 "No native access to PCI extended config space, falling back to CSI\n");
2783         csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
2784         rtl_csi_write(tp, 0x070c, csi | val << 24);
2785 }
2786
2787 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
2788 {
2789         /* L0 7us, L1 16us */
2790         rtl_set_aspm_entry_latency(tp, 0x27);
2791 }
2792
2793 struct ephy_info {
2794         unsigned int offset;
2795         u16 mask;
2796         u16 bits;
2797 };
2798
2799 static void __rtl_ephy_init(struct rtl8169_private *tp,
2800                             const struct ephy_info *e, int len)
2801 {
2802         u16 w;
2803
2804         while (len-- > 0) {
2805                 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
2806                 rtl_ephy_write(tp, e->offset, w);
2807                 e++;
2808         }
2809 }
2810
2811 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a))
2812
2813 static void rtl_disable_clock_request(struct rtl8169_private *tp)
2814 {
2815         pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
2816                                    PCI_EXP_LNKCTL_CLKREQ_EN);
2817 }
2818
2819 static void rtl_enable_clock_request(struct rtl8169_private *tp)
2820 {
2821         pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
2822                                  PCI_EXP_LNKCTL_CLKREQ_EN);
2823 }
2824
2825 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp)
2826 {
2827         /* work around an issue when PCI reset occurs during L2/L3 state */
2828         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23);
2829 }
2830
2831 static void rtl_enable_exit_l1(struct rtl8169_private *tp)
2832 {
2833         /* Bits control which events trigger ASPM L1 exit:
2834          * Bit 12: rxdv
2835          * Bit 11: ltr_msg
2836          * Bit 10: txdma_poll
2837          * Bit  9: xadm
2838          * Bit  8: pktavi
2839          * Bit  7: txpla
2840          */
2841         switch (tp->mac_version) {
2842         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
2843                 rtl_eri_set_bits(tp, 0xd4, 0x1f00);
2844                 break;
2845         case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_38:
2846                 rtl_eri_set_bits(tp, 0xd4, 0x0c00);
2847                 break;
2848         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_65:
2849                 r8168_mac_ocp_modify(tp, 0xc0ac, 0, 0x1f80);
2850                 break;
2851         default:
2852                 break;
2853         }
2854 }
2855
2856 static void rtl_disable_exit_l1(struct rtl8169_private *tp)
2857 {
2858         switch (tp->mac_version) {
2859         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
2860                 rtl_eri_clear_bits(tp, 0xd4, 0x1f00);
2861                 break;
2862         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_65:
2863                 r8168_mac_ocp_modify(tp, 0xc0ac, 0x1f80, 0);
2864                 break;
2865         default:
2866                 break;
2867         }
2868 }
2869
2870 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
2871 {
2872         u8 val8;
2873
2874         if (tp->mac_version < RTL_GIGA_MAC_VER_32)
2875                 return;
2876
2877         /* Don't enable ASPM in the chip if OS can't control ASPM */
2878         if (enable && tp->aspm_manageable) {
2879                 /* On these chip versions ASPM can even harm
2880                  * bus communication of other PCI devices.
2881                  */
2882                 if (tp->mac_version == RTL_GIGA_MAC_VER_42 ||
2883                     tp->mac_version == RTL_GIGA_MAC_VER_43)
2884                         return;
2885
2886                 rtl_mod_config5(tp, 0, ASPM_en);
2887                 switch (tp->mac_version) {
2888                 case RTL_GIGA_MAC_VER_65:
2889                         val8 = RTL_R8(tp, INT_CFG0_8125) | INT_CFG0_CLKREQEN;
2890                         RTL_W8(tp, INT_CFG0_8125, val8);
2891                         break;
2892                 default:
2893                         rtl_mod_config2(tp, 0, ClkReqEn);
2894                         break;
2895                 }
2896
2897                 switch (tp->mac_version) {
2898                 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48:
2899                 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_65:
2900                         /* reset ephy tx/rx disable timer */
2901                         r8168_mac_ocp_modify(tp, 0xe094, 0xff00, 0);
2902                         /* chip can trigger L1.2 */
2903                         r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, BIT(2));
2904                         break;
2905                 default:
2906                         break;
2907                 }
2908         } else {
2909                 switch (tp->mac_version) {
2910                 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48:
2911                 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_65:
2912                         r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, 0);
2913                         break;
2914                 default:
2915                         break;
2916                 }
2917
2918                 switch (tp->mac_version) {
2919                 case RTL_GIGA_MAC_VER_65:
2920                         val8 = RTL_R8(tp, INT_CFG0_8125) & ~INT_CFG0_CLKREQEN;
2921                         RTL_W8(tp, INT_CFG0_8125, val8);
2922                         break;
2923                 default:
2924                         rtl_mod_config2(tp, ClkReqEn, 0);
2925                         break;
2926                 }
2927                 rtl_mod_config5(tp, ASPM_en, 0);
2928         }
2929 }
2930
2931 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat,
2932                               u16 tx_stat, u16 rx_dyn, u16 tx_dyn)
2933 {
2934         /* Usage of dynamic vs. static FIFO is controlled by bit
2935          * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known.
2936          */
2937         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn);
2938         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn);
2939 }
2940
2941 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp,
2942                                           u8 low, u8 high)
2943 {
2944         /* FIFO thresholds for pause flow control */
2945         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low);
2946         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high);
2947 }
2948
2949 static void rtl_hw_start_8168b(struct rtl8169_private *tp)
2950 {
2951         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2952 }
2953
2954 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
2955 {
2956         RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
2957
2958         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2959
2960         rtl_disable_clock_request(tp);
2961 }
2962
2963 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
2964 {
2965         static const struct ephy_info e_info_8168cp[] = {
2966                 { 0x01, 0,      0x0001 },
2967                 { 0x02, 0x0800, 0x1000 },
2968                 { 0x03, 0,      0x0042 },
2969                 { 0x06, 0x0080, 0x0000 },
2970                 { 0x07, 0,      0x2000 }
2971         };
2972
2973         rtl_set_def_aspm_entry_latency(tp);
2974
2975         rtl_ephy_init(tp, e_info_8168cp);
2976
2977         __rtl_hw_start_8168cp(tp);
2978 }
2979
2980 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
2981 {
2982         rtl_set_def_aspm_entry_latency(tp);
2983
2984         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2985 }
2986
2987 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
2988 {
2989         rtl_set_def_aspm_entry_latency(tp);
2990
2991         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2992
2993         /* Magic. */
2994         RTL_W8(tp, DBG_REG, 0x20);
2995 }
2996
2997 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
2998 {
2999         static const struct ephy_info e_info_8168c_1[] = {
3000                 { 0x02, 0x0800, 0x1000 },
3001                 { 0x03, 0,      0x0002 },
3002                 { 0x06, 0x0080, 0x0000 }
3003         };
3004
3005         rtl_set_def_aspm_entry_latency(tp);
3006
3007         RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
3008
3009         rtl_ephy_init(tp, e_info_8168c_1);
3010
3011         __rtl_hw_start_8168cp(tp);
3012 }
3013
3014 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
3015 {
3016         static const struct ephy_info e_info_8168c_2[] = {
3017                 { 0x01, 0,      0x0001 },
3018                 { 0x03, 0x0400, 0x0020 }
3019         };
3020
3021         rtl_set_def_aspm_entry_latency(tp);
3022
3023         rtl_ephy_init(tp, e_info_8168c_2);
3024
3025         __rtl_hw_start_8168cp(tp);
3026 }
3027
3028 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
3029 {
3030         rtl_set_def_aspm_entry_latency(tp);
3031
3032         __rtl_hw_start_8168cp(tp);
3033 }
3034
3035 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
3036 {
3037         rtl_set_def_aspm_entry_latency(tp);
3038
3039         rtl_disable_clock_request(tp);
3040 }
3041
3042 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
3043 {
3044         static const struct ephy_info e_info_8168d_4[] = {
3045                 { 0x0b, 0x0000, 0x0048 },
3046                 { 0x19, 0x0020, 0x0050 },
3047                 { 0x0c, 0x0100, 0x0020 },
3048                 { 0x10, 0x0004, 0x0000 },
3049         };
3050
3051         rtl_set_def_aspm_entry_latency(tp);
3052
3053         rtl_ephy_init(tp, e_info_8168d_4);
3054
3055         rtl_enable_clock_request(tp);
3056 }
3057
3058 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
3059 {
3060         static const struct ephy_info e_info_8168e_1[] = {
3061                 { 0x00, 0x0200, 0x0100 },
3062                 { 0x00, 0x0000, 0x0004 },
3063                 { 0x06, 0x0002, 0x0001 },
3064                 { 0x06, 0x0000, 0x0030 },
3065                 { 0x07, 0x0000, 0x2000 },
3066                 { 0x00, 0x0000, 0x0020 },
3067                 { 0x03, 0x5800, 0x2000 },
3068                 { 0x03, 0x0000, 0x0001 },
3069                 { 0x01, 0x0800, 0x1000 },
3070                 { 0x07, 0x0000, 0x4000 },
3071                 { 0x1e, 0x0000, 0x2000 },
3072                 { 0x19, 0xffff, 0xfe6c },
3073                 { 0x0a, 0x0000, 0x0040 }
3074         };
3075
3076         rtl_set_def_aspm_entry_latency(tp);
3077
3078         rtl_ephy_init(tp, e_info_8168e_1);
3079
3080         rtl_disable_clock_request(tp);
3081
3082         /* Reset tx FIFO pointer */
3083         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
3084         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
3085
3086         rtl_mod_config5(tp, Spi_en, 0);
3087 }
3088
3089 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
3090 {
3091         static const struct ephy_info e_info_8168e_2[] = {
3092                 { 0x09, 0x0000, 0x0080 },
3093                 { 0x19, 0x0000, 0x0224 },
3094                 { 0x00, 0x0000, 0x0004 },
3095                 { 0x0c, 0x3df0, 0x0200 },
3096         };
3097
3098         rtl_set_def_aspm_entry_latency(tp);
3099
3100         rtl_ephy_init(tp, e_info_8168e_2);
3101
3102         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3103         rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000);
3104         rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
3105         rtl_eri_set_bits(tp, 0x1d0, BIT(1));
3106         rtl_reset_packet_filter(tp);
3107         rtl_eri_set_bits(tp, 0x1b0, BIT(4));
3108         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
3109         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060);
3110
3111         rtl_disable_clock_request(tp);
3112
3113         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
3114
3115         rtl8168_config_eee_mac(tp);
3116
3117         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
3118         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
3119         rtl_mod_config5(tp, Spi_en, 0);
3120 }
3121
3122 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
3123 {
3124         rtl_set_def_aspm_entry_latency(tp);
3125
3126         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3127         rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000);
3128         rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
3129         rtl_reset_packet_filter(tp);
3130         rtl_eri_set_bits(tp, 0x1b0, BIT(4));
3131         rtl_eri_set_bits(tp, 0x1d0, BIT(4) | BIT(1));
3132         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
3133         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060);
3134
3135         rtl_disable_clock_request(tp);
3136
3137         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
3138         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
3139         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
3140         rtl_mod_config5(tp, Spi_en, 0);
3141
3142         rtl8168_config_eee_mac(tp);
3143 }
3144
3145 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
3146 {
3147         static const struct ephy_info e_info_8168f_1[] = {
3148                 { 0x06, 0x00c0, 0x0020 },
3149                 { 0x08, 0x0001, 0x0002 },
3150                 { 0x09, 0x0000, 0x0080 },
3151                 { 0x19, 0x0000, 0x0224 },
3152                 { 0x00, 0x0000, 0x0008 },
3153                 { 0x0c, 0x3df0, 0x0200 },
3154         };
3155
3156         rtl_hw_start_8168f(tp);
3157
3158         rtl_ephy_init(tp, e_info_8168f_1);
3159 }
3160
3161 static void rtl_hw_start_8411(struct rtl8169_private *tp)
3162 {
3163         static const struct ephy_info e_info_8168f_1[] = {
3164                 { 0x06, 0x00c0, 0x0020 },
3165                 { 0x0f, 0xffff, 0x5200 },
3166                 { 0x19, 0x0000, 0x0224 },
3167                 { 0x00, 0x0000, 0x0008 },
3168                 { 0x0c, 0x3df0, 0x0200 },
3169         };
3170
3171         rtl_hw_start_8168f(tp);
3172         rtl_pcie_state_l2l3_disable(tp);
3173
3174         rtl_ephy_init(tp, e_info_8168f_1);
3175 }
3176
3177 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
3178 {
3179         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3180         rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
3181
3182         rtl_set_def_aspm_entry_latency(tp);
3183
3184         rtl_reset_packet_filter(tp);
3185         rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f);
3186
3187         rtl_disable_rxdvgate(tp);
3188
3189         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3190         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3191
3192         rtl8168_config_eee_mac(tp);
3193
3194         rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06);
3195         rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
3196
3197         rtl_pcie_state_l2l3_disable(tp);
3198 }
3199
3200 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
3201 {
3202         static const struct ephy_info e_info_8168g_1[] = {
3203                 { 0x00, 0x0008, 0x0000 },
3204                 { 0x0c, 0x3ff0, 0x0820 },
3205                 { 0x1e, 0x0000, 0x0001 },
3206                 { 0x19, 0x8000, 0x0000 }
3207         };
3208
3209         rtl_hw_start_8168g(tp);
3210         rtl_ephy_init(tp, e_info_8168g_1);
3211 }
3212
3213 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
3214 {
3215         static const struct ephy_info e_info_8168g_2[] = {
3216                 { 0x00, 0x0008, 0x0000 },
3217                 { 0x0c, 0x3ff0, 0x0820 },
3218                 { 0x19, 0xffff, 0x7c00 },
3219                 { 0x1e, 0xffff, 0x20eb },
3220                 { 0x0d, 0xffff, 0x1666 },
3221                 { 0x00, 0xffff, 0x10a3 },
3222                 { 0x06, 0xffff, 0xf050 },
3223                 { 0x04, 0x0000, 0x0010 },
3224                 { 0x1d, 0x4000, 0x0000 },
3225         };
3226
3227         rtl_hw_start_8168g(tp);
3228         rtl_ephy_init(tp, e_info_8168g_2);
3229 }
3230
3231 static void rtl8411b_fix_phy_down(struct rtl8169_private *tp)
3232 {
3233         static const u16 fix_data[] = {
3234 /* 0xf800 */ 0xe008, 0xe00a, 0xe00c, 0xe00e, 0xe027, 0xe04f, 0xe05e, 0xe065,
3235 /* 0xf810 */ 0xc602, 0xbe00, 0x0000, 0xc502, 0xbd00, 0x074c, 0xc302, 0xbb00,
3236 /* 0xf820 */ 0x080a, 0x6420, 0x48c2, 0x8c20, 0xc516, 0x64a4, 0x49c0, 0xf009,
3237 /* 0xf830 */ 0x74a2, 0x8ca5, 0x74a0, 0xc50e, 0x9ca2, 0x1c11, 0x9ca0, 0xe006,
3238 /* 0xf840 */ 0x74f8, 0x48c4, 0x8cf8, 0xc404, 0xbc00, 0xc403, 0xbc00, 0x0bf2,
3239 /* 0xf850 */ 0x0c0a, 0xe434, 0xd3c0, 0x49d9, 0xf01f, 0xc526, 0x64a5, 0x1400,
3240 /* 0xf860 */ 0xf007, 0x0c01, 0x8ca5, 0x1c15, 0xc51b, 0x9ca0, 0xe013, 0xc519,
3241 /* 0xf870 */ 0x74a0, 0x48c4, 0x8ca0, 0xc516, 0x74a4, 0x48c8, 0x48ca, 0x9ca4,
3242 /* 0xf880 */ 0xc512, 0x1b00, 0x9ba0, 0x1b1c, 0x483f, 0x9ba2, 0x1b04, 0xc508,
3243 /* 0xf890 */ 0x9ba0, 0xc505, 0xbd00, 0xc502, 0xbd00, 0x0300, 0x051e, 0xe434,
3244 /* 0xf8a0 */ 0xe018, 0xe092, 0xde20, 0xd3c0, 0xc50f, 0x76a4, 0x49e3, 0xf007,
3245 /* 0xf8b0 */ 0x49c0, 0xf103, 0xc607, 0xbe00, 0xc606, 0xbe00, 0xc602, 0xbe00,
3246 /* 0xf8c0 */ 0x0c4c, 0x0c28, 0x0c2c, 0xdc00, 0xc707, 0x1d00, 0x8de2, 0x48c1,
3247 /* 0xf8d0 */ 0xc502, 0xbd00, 0x00aa, 0xe0c0, 0xc502, 0xbd00, 0x0132
3248         };
3249         unsigned long flags;
3250         int i;
3251
3252         raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags);
3253         for (i = 0; i < ARRAY_SIZE(fix_data); i++)
3254                 __r8168_mac_ocp_write(tp, 0xf800 + 2 * i, fix_data[i]);
3255         raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags);
3256 }
3257
3258 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
3259 {
3260         static const struct ephy_info e_info_8411_2[] = {
3261                 { 0x00, 0x0008, 0x0000 },
3262                 { 0x0c, 0x37d0, 0x0820 },
3263                 { 0x1e, 0x0000, 0x0001 },
3264                 { 0x19, 0x8021, 0x0000 },
3265                 { 0x1e, 0x0000, 0x2000 },
3266                 { 0x0d, 0x0100, 0x0200 },
3267                 { 0x00, 0x0000, 0x0080 },
3268                 { 0x06, 0x0000, 0x0010 },
3269                 { 0x04, 0x0000, 0x0010 },
3270                 { 0x1d, 0x0000, 0x4000 },
3271         };
3272
3273         rtl_hw_start_8168g(tp);
3274
3275         rtl_ephy_init(tp, e_info_8411_2);
3276
3277         /* The following Realtek-provided magic fixes an issue with the RX unit
3278          * getting confused after the PHY having been powered-down.
3279          */
3280         r8168_mac_ocp_write(tp, 0xFC28, 0x0000);
3281         r8168_mac_ocp_write(tp, 0xFC2A, 0x0000);
3282         r8168_mac_ocp_write(tp, 0xFC2C, 0x0000);
3283         r8168_mac_ocp_write(tp, 0xFC2E, 0x0000);
3284         r8168_mac_ocp_write(tp, 0xFC30, 0x0000);
3285         r8168_mac_ocp_write(tp, 0xFC32, 0x0000);
3286         r8168_mac_ocp_write(tp, 0xFC34, 0x0000);
3287         r8168_mac_ocp_write(tp, 0xFC36, 0x0000);
3288         mdelay(3);
3289         r8168_mac_ocp_write(tp, 0xFC26, 0x0000);
3290
3291         rtl8411b_fix_phy_down(tp);
3292
3293         r8168_mac_ocp_write(tp, 0xFC26, 0x8000);
3294
3295         r8168_mac_ocp_write(tp, 0xFC2A, 0x0743);
3296         r8168_mac_ocp_write(tp, 0xFC2C, 0x0801);
3297         r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9);
3298         r8168_mac_ocp_write(tp, 0xFC30, 0x02FD);
3299         r8168_mac_ocp_write(tp, 0xFC32, 0x0C25);
3300         r8168_mac_ocp_write(tp, 0xFC34, 0x00A9);
3301         r8168_mac_ocp_write(tp, 0xFC36, 0x012D);
3302 }
3303
3304 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
3305 {
3306         static const struct ephy_info e_info_8168h_1[] = {
3307                 { 0x1e, 0x0800, 0x0001 },
3308                 { 0x1d, 0x0000, 0x0800 },
3309                 { 0x05, 0xffff, 0x2089 },
3310                 { 0x06, 0xffff, 0x5881 },
3311                 { 0x04, 0xffff, 0x854a },
3312                 { 0x01, 0xffff, 0x068b }
3313         };
3314         int rg_saw_cnt;
3315
3316         rtl_ephy_init(tp, e_info_8168h_1);
3317
3318         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3319         rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
3320
3321         rtl_set_def_aspm_entry_latency(tp);
3322
3323         rtl_reset_packet_filter(tp);
3324
3325         rtl_eri_set_bits(tp, 0xdc, 0x001c);
3326
3327         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3328
3329         rtl_disable_rxdvgate(tp);
3330
3331         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3332         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3333
3334         rtl8168_config_eee_mac(tp);
3335
3336         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3337         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3338
3339         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3340
3341         rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
3342
3343         rtl_pcie_state_l2l3_disable(tp);
3344
3345         rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff;
3346         if (rg_saw_cnt > 0) {
3347                 u16 sw_cnt_1ms_ini;
3348
3349                 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
3350                 sw_cnt_1ms_ini &= 0x0fff;
3351                 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);
3352         }
3353
3354         r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);
3355         r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008);
3356         r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f);
3357         r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);
3358
3359         r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
3360         r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
3361         r8168_mac_ocp_write(tp, 0xc094, 0x0000);
3362         r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
3363 }
3364
3365 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
3366 {
3367         rtl8168ep_stop_cmac(tp);
3368
3369         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3370         rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
3371
3372         rtl_set_def_aspm_entry_latency(tp);
3373
3374         rtl_reset_packet_filter(tp);
3375
3376         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3377
3378         rtl_disable_rxdvgate(tp);
3379
3380         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3381         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3382
3383         rtl8168_config_eee_mac(tp);
3384
3385         rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06);
3386
3387         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3388
3389         rtl_pcie_state_l2l3_disable(tp);
3390 }
3391
3392 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
3393 {
3394         static const struct ephy_info e_info_8168ep_3[] = {
3395                 { 0x00, 0x0000, 0x0080 },
3396                 { 0x0d, 0x0100, 0x0200 },
3397                 { 0x19, 0x8021, 0x0000 },
3398                 { 0x1e, 0x0000, 0x2000 },
3399         };
3400
3401         rtl_ephy_init(tp, e_info_8168ep_3);
3402
3403         rtl_hw_start_8168ep(tp);
3404
3405         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3406         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3407
3408         r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271);
3409         r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
3410         r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);
3411 }
3412
3413 static void rtl_hw_start_8117(struct rtl8169_private *tp)
3414 {
3415         static const struct ephy_info e_info_8117[] = {
3416                 { 0x19, 0x0040, 0x1100 },
3417                 { 0x59, 0x0040, 0x1100 },
3418         };
3419         int rg_saw_cnt;
3420
3421         rtl8168ep_stop_cmac(tp);
3422         rtl_ephy_init(tp, e_info_8117);
3423
3424         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3425         rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
3426
3427         rtl_set_def_aspm_entry_latency(tp);
3428
3429         rtl_reset_packet_filter(tp);
3430
3431         rtl_eri_set_bits(tp, 0xd4, 0x0010);
3432
3433         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3434
3435         rtl_disable_rxdvgate(tp);
3436
3437         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3438         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3439
3440         rtl8168_config_eee_mac(tp);
3441
3442         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3443         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3444
3445         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3446
3447         rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
3448
3449         rtl_pcie_state_l2l3_disable(tp);
3450
3451         rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff;
3452         if (rg_saw_cnt > 0) {
3453                 u16 sw_cnt_1ms_ini;
3454
3455                 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff;
3456                 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);
3457         }
3458
3459         r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);
3460         r8168_mac_ocp_write(tp, 0xea80, 0x0003);
3461         r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009);
3462         r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);
3463
3464         r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
3465         r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
3466         r8168_mac_ocp_write(tp, 0xc094, 0x0000);
3467         r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
3468
3469         /* firmware is for MAC only */
3470         r8169_apply_firmware(tp);
3471 }
3472
3473 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
3474 {
3475         static const struct ephy_info e_info_8102e_1[] = {
3476                 { 0x01, 0, 0x6e65 },
3477                 { 0x02, 0, 0x091f },
3478                 { 0x03, 0, 0xc2f9 },
3479                 { 0x06, 0, 0xafb5 },
3480                 { 0x07, 0, 0x0e00 },
3481                 { 0x19, 0, 0xec80 },
3482                 { 0x01, 0, 0x2e65 },
3483                 { 0x01, 0, 0x6e65 }
3484         };
3485         u8 cfg1;
3486
3487         rtl_set_def_aspm_entry_latency(tp);
3488
3489         RTL_W8(tp, DBG_REG, FIX_NAK_1);
3490
3491         RTL_W8(tp, Config1,
3492                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
3493         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3494
3495         cfg1 = RTL_R8(tp, Config1);
3496         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
3497                 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
3498
3499         rtl_ephy_init(tp, e_info_8102e_1);
3500 }
3501
3502 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
3503 {
3504         rtl_set_def_aspm_entry_latency(tp);
3505
3506         RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
3507         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3508 }
3509
3510 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
3511 {
3512         rtl_hw_start_8102e_2(tp);
3513
3514         rtl_ephy_write(tp, 0x03, 0xc2f9);
3515 }
3516
3517 static void rtl_hw_start_8401(struct rtl8169_private *tp)
3518 {
3519         static const struct ephy_info e_info_8401[] = {
3520                 { 0x01, 0xffff, 0x6fe5 },
3521                 { 0x03, 0xffff, 0x0599 },
3522                 { 0x06, 0xffff, 0xaf25 },
3523                 { 0x07, 0xffff, 0x8e68 },
3524         };
3525
3526         rtl_ephy_init(tp, e_info_8401);
3527         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3528 }
3529
3530 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
3531 {
3532         static const struct ephy_info e_info_8105e_1[] = {
3533                 { 0x07, 0, 0x4000 },
3534                 { 0x19, 0, 0x0200 },
3535                 { 0x19, 0, 0x0020 },
3536                 { 0x1e, 0, 0x2000 },
3537                 { 0x03, 0, 0x0001 },
3538                 { 0x19, 0, 0x0100 },
3539                 { 0x19, 0, 0x0004 },
3540                 { 0x0a, 0, 0x0020 }
3541         };
3542
3543         /* Force LAN exit from ASPM if Rx/Tx are not idle */
3544         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3545
3546         /* Disable Early Tally Counter */
3547         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
3548
3549         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
3550         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
3551
3552         rtl_ephy_init(tp, e_info_8105e_1);
3553
3554         rtl_pcie_state_l2l3_disable(tp);
3555 }
3556
3557 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
3558 {
3559         rtl_hw_start_8105e_1(tp);
3560         rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
3561 }
3562
3563 static void rtl_hw_start_8402(struct rtl8169_private *tp)
3564 {
3565         static const struct ephy_info e_info_8402[] = {
3566                 { 0x19, 0xffff, 0xff64 },
3567                 { 0x1e, 0, 0x4000 }
3568         };
3569
3570         rtl_set_def_aspm_entry_latency(tp);
3571
3572         /* Force LAN exit from ASPM if Rx/Tx are not idle */
3573         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3574
3575         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
3576
3577         rtl_ephy_init(tp, e_info_8402);
3578
3579         rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06);
3580         rtl_reset_packet_filter(tp);
3581         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3582         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3583         rtl_w0w1_eri(tp, 0x0d4, 0x0e00, 0xff00);
3584
3585         /* disable EEE */
3586         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3587
3588         rtl_pcie_state_l2l3_disable(tp);
3589 }
3590
3591 static void rtl_hw_start_8106(struct rtl8169_private *tp)
3592 {
3593         /* Force LAN exit from ASPM if Rx/Tx are not idle */
3594         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3595
3596         RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
3597         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
3598         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3599
3600         /* L0 7us, L1 32us - needed to avoid issues with link-up detection */
3601         rtl_set_aspm_entry_latency(tp, 0x2f);
3602
3603         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
3604
3605         /* disable EEE */
3606         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3607
3608         rtl_pcie_state_l2l3_disable(tp);
3609 }
3610
3611 DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond)
3612 {
3613         return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13);
3614 }
3615
3616 static void rtl_hw_start_8125_common(struct rtl8169_private *tp)
3617 {
3618         rtl_pcie_state_l2l3_disable(tp);
3619
3620         RTL_W16(tp, 0x382, 0x221b);
3621         RTL_W8(tp, 0x4500, 0);
3622         RTL_W16(tp, 0x4800, 0);
3623
3624         /* disable UPS */
3625         r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000);
3626
3627         RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10);
3628
3629         r8168_mac_ocp_write(tp, 0xc140, 0xffff);
3630         r8168_mac_ocp_write(tp, 0xc142, 0xffff);
3631
3632         r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9);
3633         r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
3634         r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);
3635
3636         /* disable new tx descriptor format */
3637         r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000);
3638
3639         if (tp->mac_version == RTL_GIGA_MAC_VER_65)
3640                 RTL_W8(tp, 0xD8, RTL_R8(tp, 0xD8) & ~0x02);
3641
3642         if (tp->mac_version == RTL_GIGA_MAC_VER_65)
3643                 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400);
3644         else if (tp->mac_version == RTL_GIGA_MAC_VER_63)
3645                 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200);
3646         else
3647                 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0300);
3648
3649         if (tp->mac_version == RTL_GIGA_MAC_VER_63)
3650                 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0000);
3651         else
3652                 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020);
3653
3654         r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c);
3655         r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033);
3656         r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040);
3657         r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030);
3658         r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000);
3659         r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001);
3660         if (tp->mac_version == RTL_GIGA_MAC_VER_65)
3661                 r8168_mac_ocp_modify(tp, 0xea1c, 0x0300, 0x0000);
3662         else
3663                 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000);
3664         r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403);
3665         r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0068);
3666         r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f);
3667
3668         r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000);
3669         r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001);
3670         udelay(1);
3671         r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000);
3672         RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030);
3673
3674         r8168_mac_ocp_write(tp, 0xe098, 0xc302);
3675
3676         rtl_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10);
3677
3678         if (tp->mac_version == RTL_GIGA_MAC_VER_61)
3679                 rtl8125a_config_eee_mac(tp);
3680         else
3681                 rtl8125b_config_eee_mac(tp);
3682
3683         rtl_disable_rxdvgate(tp);
3684 }
3685
3686 static void rtl_hw_start_8125a_2(struct rtl8169_private *tp)
3687 {
3688         static const struct ephy_info e_info_8125a_2[] = {
3689                 { 0x04, 0xffff, 0xd000 },
3690                 { 0x0a, 0xffff, 0x8653 },
3691                 { 0x23, 0xffff, 0xab66 },
3692                 { 0x20, 0xffff, 0x9455 },
3693                 { 0x21, 0xffff, 0x99ff },
3694                 { 0x29, 0xffff, 0xfe04 },
3695
3696                 { 0x44, 0xffff, 0xd000 },
3697                 { 0x4a, 0xffff, 0x8653 },
3698                 { 0x63, 0xffff, 0xab66 },
3699                 { 0x60, 0xffff, 0x9455 },
3700                 { 0x61, 0xffff, 0x99ff },
3701                 { 0x69, 0xffff, 0xfe04 },
3702         };
3703
3704         rtl_set_def_aspm_entry_latency(tp);
3705         rtl_ephy_init(tp, e_info_8125a_2);
3706         rtl_hw_start_8125_common(tp);
3707 }
3708
3709 static void rtl_hw_start_8125b(struct rtl8169_private *tp)
3710 {
3711         static const struct ephy_info e_info_8125b[] = {
3712                 { 0x0b, 0xffff, 0xa908 },
3713                 { 0x1e, 0xffff, 0x20eb },
3714                 { 0x4b, 0xffff, 0xa908 },
3715                 { 0x5e, 0xffff, 0x20eb },
3716                 { 0x22, 0x0030, 0x0020 },
3717                 { 0x62, 0x0030, 0x0020 },
3718         };
3719
3720         rtl_set_def_aspm_entry_latency(tp);
3721         rtl_ephy_init(tp, e_info_8125b);
3722         rtl_hw_start_8125_common(tp);
3723 }
3724
3725 static void rtl_hw_start_8126a(struct rtl8169_private *tp)
3726 {
3727         rtl_set_def_aspm_entry_latency(tp);
3728         rtl_hw_start_8125_common(tp);
3729 }
3730
3731 static void rtl_hw_config(struct rtl8169_private *tp)
3732 {
3733         static const rtl_generic_fct hw_configs[] = {
3734                 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1,
3735                 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3,
3736                 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2,
3737                 [RTL_GIGA_MAC_VER_10] = NULL,
3738                 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168b,
3739                 [RTL_GIGA_MAC_VER_14] = rtl_hw_start_8401,
3740                 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b,
3741                 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1,
3742                 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1,
3743                 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2,
3744                 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_2,
3745                 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4,
3746                 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2,
3747                 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3,
3748                 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d,
3749                 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d,
3750                 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4,
3751                 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1,
3752                 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2,
3753                 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168d,
3754                 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1,
3755                 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1,
3756                 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2,
3757                 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1,
3758                 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1,
3759                 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402,
3760                 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411,
3761                 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106,
3762                 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1,
3763                 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2,
3764                 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2,
3765                 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2,
3766                 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1,
3767                 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1,
3768                 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3,
3769                 [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117,
3770                 [RTL_GIGA_MAC_VER_53] = rtl_hw_start_8117,
3771                 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2,
3772                 [RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b,
3773                 [RTL_GIGA_MAC_VER_65] = rtl_hw_start_8126a,
3774         };
3775
3776         if (hw_configs[tp->mac_version])
3777                 hw_configs[tp->mac_version](tp);
3778 }
3779
3780 static void rtl_hw_start_8125(struct rtl8169_private *tp)
3781 {
3782         int i;
3783
3784         RTL_W8(tp, INT_CFG0_8125, 0x00);
3785
3786         /* disable interrupt coalescing */
3787         switch (tp->mac_version) {
3788         case RTL_GIGA_MAC_VER_61:
3789                 for (i = 0xa00; i < 0xb00; i += 4)
3790                         RTL_W32(tp, i, 0);
3791                 break;
3792         case RTL_GIGA_MAC_VER_63:
3793         case RTL_GIGA_MAC_VER_65:
3794                 for (i = 0xa00; i < 0xa80; i += 4)
3795                         RTL_W32(tp, i, 0);
3796                 RTL_W16(tp, INT_CFG1_8125, 0x0000);
3797                 break;
3798         default:
3799                 break;
3800         }
3801
3802         rtl_hw_config(tp);
3803 }
3804
3805 static void rtl_hw_start_8168(struct rtl8169_private *tp)
3806 {
3807         if (rtl_is_8168evl_up(tp))
3808                 RTL_W8(tp, MaxTxPacketSize, EarlySize);
3809         else
3810                 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
3811
3812         rtl_hw_config(tp);
3813
3814         /* disable interrupt coalescing */
3815         RTL_W16(tp, IntrMitigate, 0x0000);
3816 }
3817
3818 static void rtl_hw_start_8169(struct rtl8169_private *tp)
3819 {
3820         RTL_W8(tp, EarlyTxThres, NoEarlyTx);
3821
3822         tp->cp_cmd |= PCIMulRW;
3823
3824         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3825             tp->mac_version == RTL_GIGA_MAC_VER_03)
3826                 tp->cp_cmd |= EnAnaPLL;
3827
3828         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
3829
3830         rtl8169_set_magic_reg(tp);
3831
3832         /* disable interrupt coalescing */
3833         RTL_W16(tp, IntrMitigate, 0x0000);
3834 }
3835
3836 static void rtl_hw_start(struct  rtl8169_private *tp)
3837 {
3838         rtl_unlock_config_regs(tp);
3839         /* disable aspm and clock request before ephy access */
3840         rtl_hw_aspm_clkreq_enable(tp, false);
3841         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
3842
3843         rtl_set_eee_txidle_timer(tp);
3844
3845         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3846                 rtl_hw_start_8169(tp);
3847         else if (rtl_is_8125(tp))
3848                 rtl_hw_start_8125(tp);
3849         else
3850                 rtl_hw_start_8168(tp);
3851
3852         rtl_enable_exit_l1(tp);
3853         rtl_hw_aspm_clkreq_enable(tp, true);
3854         rtl_set_rx_max_size(tp);
3855         rtl_set_rx_tx_desc_registers(tp);
3856         rtl_lock_config_regs(tp);
3857
3858         rtl_jumbo_config(tp);
3859
3860         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3861         rtl_pci_commit(tp);
3862
3863         RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
3864         rtl_init_rxcfg(tp);
3865         rtl_set_tx_config_registers(tp);
3866         rtl_set_rx_config_features(tp, tp->dev->features);
3867         rtl_set_rx_mode(tp->dev);
3868         rtl_irq_enable(tp);
3869 }
3870
3871 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
3872 {
3873         struct rtl8169_private *tp = netdev_priv(dev);
3874
3875         dev->mtu = new_mtu;
3876         netdev_update_features(dev);
3877         rtl_jumbo_config(tp);
3878         rtl_set_eee_txidle_timer(tp);
3879
3880         return 0;
3881 }
3882
3883 static void rtl8169_mark_to_asic(struct RxDesc *desc)
3884 {
3885         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
3886
3887         desc->opts2 = 0;
3888         /* Force memory writes to complete before releasing descriptor */
3889         dma_wmb();
3890         WRITE_ONCE(desc->opts1, cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE));
3891 }
3892
3893 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
3894                                           struct RxDesc *desc)
3895 {
3896         struct device *d = tp_to_dev(tp);
3897         int node = dev_to_node(d);
3898         dma_addr_t mapping;
3899         struct page *data;
3900
3901         data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE));
3902         if (!data)
3903                 return NULL;
3904
3905         mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
3906         if (unlikely(dma_mapping_error(d, mapping))) {
3907                 netdev_err(tp->dev, "Failed to map RX DMA!\n");
3908                 __free_pages(data, get_order(R8169_RX_BUF_SIZE));
3909                 return NULL;
3910         }
3911
3912         desc->addr = cpu_to_le64(mapping);
3913         rtl8169_mark_to_asic(desc);
3914
3915         return data;
3916 }
3917
3918 static void rtl8169_rx_clear(struct rtl8169_private *tp)
3919 {
3920         int i;
3921
3922         for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) {
3923                 dma_unmap_page(tp_to_dev(tp),
3924                                le64_to_cpu(tp->RxDescArray[i].addr),
3925                                R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
3926                 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE));
3927                 tp->Rx_databuff[i] = NULL;
3928                 tp->RxDescArray[i].addr = 0;
3929                 tp->RxDescArray[i].opts1 = 0;
3930         }
3931 }
3932
3933 static int rtl8169_rx_fill(struct rtl8169_private *tp)
3934 {
3935         int i;
3936
3937         for (i = 0; i < NUM_RX_DESC; i++) {
3938                 struct page *data;
3939
3940                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
3941                 if (!data) {
3942                         rtl8169_rx_clear(tp);
3943                         return -ENOMEM;
3944                 }
3945                 tp->Rx_databuff[i] = data;
3946         }
3947
3948         /* mark as last descriptor in the ring */
3949         tp->RxDescArray[NUM_RX_DESC - 1].opts1 |= cpu_to_le32(RingEnd);
3950
3951         return 0;
3952 }
3953
3954 static int rtl8169_init_ring(struct rtl8169_private *tp)
3955 {
3956         rtl8169_init_ring_indexes(tp);
3957
3958         memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
3959         memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
3960
3961         return rtl8169_rx_fill(tp);
3962 }
3963
3964 static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int entry)
3965 {
3966         struct ring_info *tx_skb = tp->tx_skb + entry;
3967         struct TxDesc *desc = tp->TxDescArray + entry;
3968
3969         dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), tx_skb->len,
3970                          DMA_TO_DEVICE);
3971         memset(desc, 0, sizeof(*desc));
3972         memset(tx_skb, 0, sizeof(*tx_skb));
3973 }
3974
3975 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
3976                                    unsigned int n)
3977 {
3978         unsigned int i;
3979
3980         for (i = 0; i < n; i++) {
3981                 unsigned int entry = (start + i) % NUM_TX_DESC;
3982                 struct ring_info *tx_skb = tp->tx_skb + entry;
3983                 unsigned int len = tx_skb->len;
3984
3985                 if (len) {
3986                         struct sk_buff *skb = tx_skb->skb;
3987
3988                         rtl8169_unmap_tx_skb(tp, entry);
3989                         if (skb)
3990                                 dev_consume_skb_any(skb);
3991                 }
3992         }
3993 }
3994
3995 static void rtl8169_tx_clear(struct rtl8169_private *tp)
3996 {
3997         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
3998         netdev_reset_queue(tp->dev);
3999 }
4000
4001 static void rtl8169_cleanup(struct rtl8169_private *tp)
4002 {
4003         napi_disable(&tp->napi);
4004
4005         /* Give a racing hard_start_xmit a few cycles to complete. */
4006         synchronize_net();
4007
4008         /* Disable interrupts */
4009         rtl8169_irq_mask_and_ack(tp);
4010
4011         rtl_rx_close(tp);
4012
4013         switch (tp->mac_version) {
4014         case RTL_GIGA_MAC_VER_28:
4015         case RTL_GIGA_MAC_VER_31:
4016                 rtl_loop_wait_low(tp, &rtl_npq_cond, 20, 2000);
4017                 break;
4018         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
4019                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4020                 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
4021                 break;
4022         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_65:
4023                 rtl_enable_rxdvgate(tp);
4024                 fsleep(2000);
4025                 break;
4026         default:
4027                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4028                 fsleep(100);
4029                 break;
4030         }
4031
4032         rtl_hw_reset(tp);
4033
4034         rtl8169_tx_clear(tp);
4035         rtl8169_init_ring_indexes(tp);
4036 }
4037
4038 static void rtl_reset_work(struct rtl8169_private *tp)
4039 {
4040         int i;
4041
4042         netif_stop_queue(tp->dev);
4043
4044         rtl8169_cleanup(tp);
4045
4046         for (i = 0; i < NUM_RX_DESC; i++)
4047                 rtl8169_mark_to_asic(tp->RxDescArray + i);
4048
4049         napi_enable(&tp->napi);
4050         rtl_hw_start(tp);
4051 }
4052
4053 static void rtl8169_tx_timeout(struct net_device *dev, unsigned int txqueue)
4054 {
4055         struct rtl8169_private *tp = netdev_priv(dev);
4056
4057         rtl_schedule_task(tp, RTL_FLAG_TASK_TX_TIMEOUT);
4058 }
4059
4060 static int rtl8169_tx_map(struct rtl8169_private *tp, const u32 *opts, u32 len,
4061                           void *addr, unsigned int entry, bool desc_own)
4062 {
4063         struct TxDesc *txd = tp->TxDescArray + entry;
4064         struct device *d = tp_to_dev(tp);
4065         dma_addr_t mapping;
4066         u32 opts1;
4067         int ret;
4068
4069         mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
4070         ret = dma_mapping_error(d, mapping);
4071         if (unlikely(ret)) {
4072                 if (net_ratelimit())
4073                         netdev_err(tp->dev, "Failed to map TX data!\n");
4074                 return ret;
4075         }
4076
4077         txd->addr = cpu_to_le64(mapping);
4078         txd->opts2 = cpu_to_le32(opts[1]);
4079
4080         opts1 = opts[0] | len;
4081         if (entry == NUM_TX_DESC - 1)
4082                 opts1 |= RingEnd;
4083         if (desc_own)
4084                 opts1 |= DescOwn;
4085         txd->opts1 = cpu_to_le32(opts1);
4086
4087         tp->tx_skb[entry].len = len;
4088
4089         return 0;
4090 }
4091
4092 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4093                               const u32 *opts, unsigned int entry)
4094 {
4095         struct skb_shared_info *info = skb_shinfo(skb);
4096         unsigned int cur_frag;
4097
4098         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4099                 const skb_frag_t *frag = info->frags + cur_frag;
4100                 void *addr = skb_frag_address(frag);
4101                 u32 len = skb_frag_size(frag);
4102
4103                 entry = (entry + 1) % NUM_TX_DESC;
4104
4105                 if (unlikely(rtl8169_tx_map(tp, opts, len, addr, entry, true)))
4106                         goto err_out;
4107         }
4108
4109         return 0;
4110
4111 err_out:
4112         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
4113         return -EIO;
4114 }
4115
4116 static bool rtl_skb_is_udp(struct sk_buff *skb)
4117 {
4118         int no = skb_network_offset(skb);
4119         struct ipv6hdr *i6h, _i6h;
4120         struct iphdr *ih, _ih;
4121
4122         switch (vlan_get_protocol(skb)) {
4123         case htons(ETH_P_IP):
4124                 ih = skb_header_pointer(skb, no, sizeof(_ih), &_ih);
4125                 return ih && ih->protocol == IPPROTO_UDP;
4126         case htons(ETH_P_IPV6):
4127                 i6h = skb_header_pointer(skb, no, sizeof(_i6h), &_i6h);
4128                 return i6h && i6h->nexthdr == IPPROTO_UDP;
4129         default:
4130                 return false;
4131         }
4132 }
4133
4134 #define RTL_MIN_PATCH_LEN       47
4135
4136 /* see rtl8125_get_patch_pad_len() in r8125 vendor driver */
4137 static unsigned int rtl8125_quirk_udp_padto(struct rtl8169_private *tp,
4138                                             struct sk_buff *skb)
4139 {
4140         unsigned int padto = 0, len = skb->len;
4141
4142         if (rtl_is_8125(tp) && len < 128 + RTL_MIN_PATCH_LEN &&
4143             rtl_skb_is_udp(skb) && skb_transport_header_was_set(skb)) {
4144                 unsigned int trans_data_len = skb_tail_pointer(skb) -
4145                                               skb_transport_header(skb);
4146
4147                 if (trans_data_len >= offsetof(struct udphdr, len) &&
4148                     trans_data_len < RTL_MIN_PATCH_LEN) {
4149                         u16 dest = ntohs(udp_hdr(skb)->dest);
4150
4151                         /* dest is a standard PTP port */
4152                         if (dest == 319 || dest == 320)
4153                                 padto = len + RTL_MIN_PATCH_LEN - trans_data_len;
4154                 }
4155
4156                 if (trans_data_len < sizeof(struct udphdr))
4157                         padto = max_t(unsigned int, padto,
4158                                       len + sizeof(struct udphdr) - trans_data_len);
4159         }
4160
4161         return padto;
4162 }
4163
4164 static unsigned int rtl_quirk_packet_padto(struct rtl8169_private *tp,
4165                                            struct sk_buff *skb)
4166 {
4167         unsigned int padto;
4168
4169         padto = rtl8125_quirk_udp_padto(tp, skb);
4170
4171         switch (tp->mac_version) {
4172         case RTL_GIGA_MAC_VER_34:
4173         case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_65:
4174                 padto = max_t(unsigned int, padto, ETH_ZLEN);
4175                 break;
4176         default:
4177                 break;
4178         }
4179
4180         return padto;
4181 }
4182
4183 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts)
4184 {
4185         u32 mss = skb_shinfo(skb)->gso_size;
4186
4187         if (mss) {
4188                 opts[0] |= TD_LSO;
4189                 opts[0] |= mss << TD0_MSS_SHIFT;
4190         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4191                 const struct iphdr *ip = ip_hdr(skb);
4192
4193                 if (ip->protocol == IPPROTO_TCP)
4194                         opts[0] |= TD0_IP_CS | TD0_TCP_CS;
4195                 else if (ip->protocol == IPPROTO_UDP)
4196                         opts[0] |= TD0_IP_CS | TD0_UDP_CS;
4197                 else
4198                         WARN_ON_ONCE(1);
4199         }
4200 }
4201
4202 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
4203                                 struct sk_buff *skb, u32 *opts)
4204 {
4205         struct skb_shared_info *shinfo = skb_shinfo(skb);
4206         u32 mss = shinfo->gso_size;
4207
4208         if (mss) {
4209                 if (shinfo->gso_type & SKB_GSO_TCPV4) {
4210                         opts[0] |= TD1_GTSENV4;
4211                 } else if (shinfo->gso_type & SKB_GSO_TCPV6) {
4212                         if (skb_cow_head(skb, 0))
4213                                 return false;
4214
4215                         tcp_v6_gso_csum_prep(skb);
4216                         opts[0] |= TD1_GTSENV6;
4217                 } else {
4218                         WARN_ON_ONCE(1);
4219                 }
4220
4221                 opts[0] |= skb_transport_offset(skb) << GTTCPHO_SHIFT;
4222                 opts[1] |= mss << TD1_MSS_SHIFT;
4223         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4224                 u8 ip_protocol;
4225
4226                 switch (vlan_get_protocol(skb)) {
4227                 case htons(ETH_P_IP):
4228                         opts[1] |= TD1_IPv4_CS;
4229                         ip_protocol = ip_hdr(skb)->protocol;
4230                         break;
4231
4232                 case htons(ETH_P_IPV6):
4233                         opts[1] |= TD1_IPv6_CS;
4234                         ip_protocol = ipv6_hdr(skb)->nexthdr;
4235                         break;
4236
4237                 default:
4238                         ip_protocol = IPPROTO_RAW;
4239                         break;
4240                 }
4241
4242                 if (ip_protocol == IPPROTO_TCP)
4243                         opts[1] |= TD1_TCP_CS;
4244                 else if (ip_protocol == IPPROTO_UDP)
4245                         opts[1] |= TD1_UDP_CS;
4246                 else
4247                         WARN_ON_ONCE(1);
4248
4249                 opts[1] |= skb_transport_offset(skb) << TCPHO_SHIFT;
4250         } else {
4251                 unsigned int padto = rtl_quirk_packet_padto(tp, skb);
4252
4253                 /* skb_padto would free the skb on error */
4254                 return !__skb_put_padto(skb, padto, false);
4255         }
4256
4257         return true;
4258 }
4259
4260 static unsigned int rtl_tx_slots_avail(struct rtl8169_private *tp)
4261 {
4262         return READ_ONCE(tp->dirty_tx) + NUM_TX_DESC - READ_ONCE(tp->cur_tx);
4263 }
4264
4265 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */
4266 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
4267 {
4268         switch (tp->mac_version) {
4269         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
4270         case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
4271                 return false;
4272         default:
4273                 return true;
4274         }
4275 }
4276
4277 static void rtl8169_doorbell(struct rtl8169_private *tp)
4278 {
4279         if (rtl_is_8125(tp))
4280                 RTL_W16(tp, TxPoll_8125, BIT(0));
4281         else
4282                 RTL_W8(tp, TxPoll, NPQ);
4283 }
4284
4285 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4286                                       struct net_device *dev)
4287 {
4288         unsigned int frags = skb_shinfo(skb)->nr_frags;
4289         struct rtl8169_private *tp = netdev_priv(dev);
4290         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
4291         struct TxDesc *txd_first, *txd_last;
4292         bool stop_queue, door_bell;
4293         u32 opts[2];
4294
4295         if (unlikely(!rtl_tx_slots_avail(tp))) {
4296                 if (net_ratelimit())
4297                         netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
4298                 goto err_stop_0;
4299         }
4300
4301         opts[1] = rtl8169_tx_vlan_tag(skb);
4302         opts[0] = 0;
4303
4304         if (!rtl_chip_supports_csum_v2(tp))
4305                 rtl8169_tso_csum_v1(skb, opts);
4306         else if (!rtl8169_tso_csum_v2(tp, skb, opts))
4307                 goto err_dma_0;
4308
4309         if (unlikely(rtl8169_tx_map(tp, opts, skb_headlen(skb), skb->data,
4310                                     entry, false)))
4311                 goto err_dma_0;
4312
4313         txd_first = tp->TxDescArray + entry;
4314
4315         if (frags) {
4316                 if (rtl8169_xmit_frags(tp, skb, opts, entry))
4317                         goto err_dma_1;
4318                 entry = (entry + frags) % NUM_TX_DESC;
4319         }
4320
4321         txd_last = tp->TxDescArray + entry;
4322         txd_last->opts1 |= cpu_to_le32(LastFrag);
4323         tp->tx_skb[entry].skb = skb;
4324
4325         skb_tx_timestamp(skb);
4326
4327         /* Force memory writes to complete before releasing descriptor */
4328         dma_wmb();
4329
4330         door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more());
4331
4332         txd_first->opts1 |= cpu_to_le32(DescOwn | FirstFrag);
4333
4334         /* rtl_tx needs to see descriptor changes before updated tp->cur_tx */
4335         smp_wmb();
4336
4337         WRITE_ONCE(tp->cur_tx, tp->cur_tx + frags + 1);
4338
4339         stop_queue = !netif_subqueue_maybe_stop(dev, 0, rtl_tx_slots_avail(tp),
4340                                                 R8169_TX_STOP_THRS,
4341                                                 R8169_TX_START_THRS);
4342         if (door_bell || stop_queue)
4343                 rtl8169_doorbell(tp);
4344
4345         return NETDEV_TX_OK;
4346
4347 err_dma_1:
4348         rtl8169_unmap_tx_skb(tp, entry);
4349 err_dma_0:
4350         dev_kfree_skb_any(skb);
4351         dev->stats.tx_dropped++;
4352         return NETDEV_TX_OK;
4353
4354 err_stop_0:
4355         netif_stop_queue(dev);
4356         dev->stats.tx_dropped++;
4357         return NETDEV_TX_BUSY;
4358 }
4359
4360 static unsigned int rtl_last_frag_len(struct sk_buff *skb)
4361 {
4362         struct skb_shared_info *info = skb_shinfo(skb);
4363         unsigned int nr_frags = info->nr_frags;
4364
4365         if (!nr_frags)
4366                 return UINT_MAX;
4367
4368         return skb_frag_size(info->frags + nr_frags - 1);
4369 }
4370
4371 /* Workaround for hw issues with TSO on RTL8168evl */
4372 static netdev_features_t rtl8168evl_fix_tso(struct sk_buff *skb,
4373                                             netdev_features_t features)
4374 {
4375         /* IPv4 header has options field */
4376         if (vlan_get_protocol(skb) == htons(ETH_P_IP) &&
4377             ip_hdrlen(skb) > sizeof(struct iphdr))
4378                 features &= ~NETIF_F_ALL_TSO;
4379
4380         /* IPv4 TCP header has options field */
4381         else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4 &&
4382                  tcp_hdrlen(skb) > sizeof(struct tcphdr))
4383                 features &= ~NETIF_F_ALL_TSO;
4384
4385         else if (rtl_last_frag_len(skb) <= 6)
4386                 features &= ~NETIF_F_ALL_TSO;
4387
4388         return features;
4389 }
4390
4391 static netdev_features_t rtl8169_features_check(struct sk_buff *skb,
4392                                                 struct net_device *dev,
4393                                                 netdev_features_t features)
4394 {
4395         struct rtl8169_private *tp = netdev_priv(dev);
4396
4397         if (skb_is_gso(skb)) {
4398                 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4399                         features = rtl8168evl_fix_tso(skb, features);
4400
4401                 if (skb_transport_offset(skb) > GTTCPHO_MAX &&
4402                     rtl_chip_supports_csum_v2(tp))
4403                         features &= ~NETIF_F_ALL_TSO;
4404         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4405                 /* work around hw bug on some chip versions */
4406                 if (skb->len < ETH_ZLEN)
4407                         features &= ~NETIF_F_CSUM_MASK;
4408
4409                 if (rtl_quirk_packet_padto(tp, skb))
4410                         features &= ~NETIF_F_CSUM_MASK;
4411
4412                 if (skb_transport_offset(skb) > TCPHO_MAX &&
4413                     rtl_chip_supports_csum_v2(tp))
4414                         features &= ~NETIF_F_CSUM_MASK;
4415         }
4416
4417         return vlan_features_check(skb, features);
4418 }
4419
4420 static void rtl8169_pcierr_interrupt(struct net_device *dev)
4421 {
4422         struct rtl8169_private *tp = netdev_priv(dev);
4423         struct pci_dev *pdev = tp->pci_dev;
4424         int pci_status_errs;
4425         u16 pci_cmd;
4426
4427         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4428
4429         pci_status_errs = pci_status_get_and_clear_errors(pdev);
4430
4431         if (net_ratelimit())
4432                 netdev_err(dev, "PCI error (cmd = 0x%04x, status_errs = 0x%04x)\n",
4433                            pci_cmd, pci_status_errs);
4434
4435         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
4436 }
4437
4438 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp,
4439                    int budget)
4440 {
4441         unsigned int dirty_tx, bytes_compl = 0, pkts_compl = 0;
4442         struct sk_buff *skb;
4443
4444         dirty_tx = tp->dirty_tx;
4445
4446         while (READ_ONCE(tp->cur_tx) != dirty_tx) {
4447                 unsigned int entry = dirty_tx % NUM_TX_DESC;
4448                 u32 status;
4449
4450                 status = le32_to_cpu(READ_ONCE(tp->TxDescArray[entry].opts1));
4451                 if (status & DescOwn)
4452                         break;
4453
4454                 skb = tp->tx_skb[entry].skb;
4455                 rtl8169_unmap_tx_skb(tp, entry);
4456
4457                 if (skb) {
4458                         pkts_compl++;
4459                         bytes_compl += skb->len;
4460                         napi_consume_skb(skb, budget);
4461                 }
4462                 dirty_tx++;
4463         }
4464
4465         if (tp->dirty_tx != dirty_tx) {
4466                 dev_sw_netstats_tx_add(dev, pkts_compl, bytes_compl);
4467                 WRITE_ONCE(tp->dirty_tx, dirty_tx);
4468
4469                 netif_subqueue_completed_wake(dev, 0, pkts_compl, bytes_compl,
4470                                               rtl_tx_slots_avail(tp),
4471                                               R8169_TX_START_THRS);
4472                 /*
4473                  * 8168 hack: TxPoll requests are lost when the Tx packets are
4474                  * too close. Let's kick an extra TxPoll request when a burst
4475                  * of start_xmit activity is detected (if it is not detected,
4476                  * it is slow enough). -- FR
4477                  * If skb is NULL then we come here again once a tx irq is
4478                  * triggered after the last fragment is marked transmitted.
4479                  */
4480                 if (READ_ONCE(tp->cur_tx) != dirty_tx && skb)
4481                         rtl8169_doorbell(tp);
4482         }
4483 }
4484
4485 static inline int rtl8169_fragmented_frame(u32 status)
4486 {
4487         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4488 }
4489
4490 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
4491 {
4492         u32 status = opts1 & (RxProtoMask | RxCSFailMask);
4493
4494         if (status == RxProtoTCP || status == RxProtoUDP)
4495                 skb->ip_summed = CHECKSUM_UNNECESSARY;
4496         else
4497                 skb_checksum_none_assert(skb);
4498 }
4499
4500 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, int budget)
4501 {
4502         struct device *d = tp_to_dev(tp);
4503         int count;
4504
4505         for (count = 0; count < budget; count++, tp->cur_rx++) {
4506                 unsigned int pkt_size, entry = tp->cur_rx % NUM_RX_DESC;
4507                 struct RxDesc *desc = tp->RxDescArray + entry;
4508                 struct sk_buff *skb;
4509                 const void *rx_buf;
4510                 dma_addr_t addr;
4511                 u32 status;
4512
4513                 status = le32_to_cpu(READ_ONCE(desc->opts1));
4514                 if (status & DescOwn)
4515                         break;
4516
4517                 /* This barrier is needed to keep us from reading
4518                  * any other fields out of the Rx descriptor until
4519                  * we know the status of DescOwn
4520                  */
4521                 dma_rmb();
4522
4523                 if (unlikely(status & RxRES)) {
4524                         if (net_ratelimit())
4525                                 netdev_warn(dev, "Rx ERROR. status = %08x\n",
4526                                             status);
4527                         dev->stats.rx_errors++;
4528                         if (status & (RxRWT | RxRUNT))
4529                                 dev->stats.rx_length_errors++;
4530                         if (status & RxCRC)
4531                                 dev->stats.rx_crc_errors++;
4532
4533                         if (!(dev->features & NETIF_F_RXALL))
4534                                 goto release_descriptor;
4535                         else if (status & RxRWT || !(status & (RxRUNT | RxCRC)))
4536                                 goto release_descriptor;
4537                 }
4538
4539                 pkt_size = status & GENMASK(13, 0);
4540                 if (likely(!(dev->features & NETIF_F_RXFCS)))
4541                         pkt_size -= ETH_FCS_LEN;
4542
4543                 /* The driver does not support incoming fragmented frames.
4544                  * They are seen as a symptom of over-mtu sized frames.
4545                  */
4546                 if (unlikely(rtl8169_fragmented_frame(status))) {
4547                         dev->stats.rx_dropped++;
4548                         dev->stats.rx_length_errors++;
4549                         goto release_descriptor;
4550                 }
4551
4552                 skb = napi_alloc_skb(&tp->napi, pkt_size);
4553                 if (unlikely(!skb)) {
4554                         dev->stats.rx_dropped++;
4555                         goto release_descriptor;
4556                 }
4557
4558                 addr = le64_to_cpu(desc->addr);
4559                 rx_buf = page_address(tp->Rx_databuff[entry]);
4560
4561                 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
4562                 prefetch(rx_buf);
4563                 skb_copy_to_linear_data(skb, rx_buf, pkt_size);
4564                 skb->tail += pkt_size;
4565                 skb->len = pkt_size;
4566                 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
4567
4568                 rtl8169_rx_csum(skb, status);
4569                 skb->protocol = eth_type_trans(skb, dev);
4570
4571                 rtl8169_rx_vlan_tag(desc, skb);
4572
4573                 if (skb->pkt_type == PACKET_MULTICAST)
4574                         dev->stats.multicast++;
4575
4576                 napi_gro_receive(&tp->napi, skb);
4577
4578                 dev_sw_netstats_rx_add(dev, pkt_size);
4579 release_descriptor:
4580                 rtl8169_mark_to_asic(desc);
4581         }
4582
4583         return count;
4584 }
4585
4586 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
4587 {
4588         struct rtl8169_private *tp = dev_instance;
4589         u32 status = rtl_get_events(tp);
4590
4591         if ((status & 0xffff) == 0xffff || !(status & tp->irq_mask))
4592                 return IRQ_NONE;
4593
4594         if (unlikely(status & SYSErr)) {
4595                 rtl8169_pcierr_interrupt(tp->dev);
4596                 goto out;
4597         }
4598
4599         if (status & LinkChg)
4600                 phy_mac_interrupt(tp->phydev);
4601
4602         if (unlikely(status & RxFIFOOver &&
4603             tp->mac_version == RTL_GIGA_MAC_VER_11)) {
4604                 netif_stop_queue(tp->dev);
4605                 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
4606         }
4607
4608         if (napi_schedule_prep(&tp->napi)) {
4609                 rtl_irq_disable(tp);
4610                 __napi_schedule(&tp->napi);
4611         }
4612 out:
4613         rtl_ack_events(tp, status);
4614
4615         return IRQ_HANDLED;
4616 }
4617
4618 static void rtl_task(struct work_struct *work)
4619 {
4620         struct rtl8169_private *tp =
4621                 container_of(work, struct rtl8169_private, wk.work);
4622         int ret;
4623
4624         rtnl_lock();
4625
4626         if (!test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
4627                 goto out_unlock;
4628
4629         if (test_and_clear_bit(RTL_FLAG_TASK_TX_TIMEOUT, tp->wk.flags)) {
4630                 /* if chip isn't accessible, reset bus to revive it */
4631                 if (RTL_R32(tp, TxConfig) == ~0) {
4632                         ret = pci_reset_bus(tp->pci_dev);
4633                         if (ret < 0) {
4634                                 netdev_err(tp->dev, "Can't reset secondary PCI bus, detach NIC\n");
4635                                 netif_device_detach(tp->dev);
4636                                 goto out_unlock;
4637                         }
4638                 }
4639
4640                 /* ASPM compatibility issues are a typical reason for tx timeouts */
4641                 ret = pci_disable_link_state(tp->pci_dev, PCIE_LINK_STATE_L1 |
4642                                                           PCIE_LINK_STATE_L0S);
4643                 if (!ret)
4644                         netdev_warn_once(tp->dev, "ASPM disabled on Tx timeout\n");
4645                 goto reset;
4646         }
4647
4648         if (test_and_clear_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags)) {
4649 reset:
4650                 rtl_reset_work(tp);
4651                 netif_wake_queue(tp->dev);
4652         } else if (test_and_clear_bit(RTL_FLAG_TASK_RESET_NO_QUEUE_WAKE, tp->wk.flags)) {
4653                 rtl_reset_work(tp);
4654         }
4655 out_unlock:
4656         rtnl_unlock();
4657 }
4658
4659 static int rtl8169_poll(struct napi_struct *napi, int budget)
4660 {
4661         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
4662         struct net_device *dev = tp->dev;
4663         int work_done;
4664
4665         rtl_tx(dev, tp, budget);
4666
4667         work_done = rtl_rx(dev, tp, budget);
4668
4669         if (work_done < budget && napi_complete_done(napi, work_done))
4670                 rtl_irq_enable(tp);
4671
4672         return work_done;
4673 }
4674
4675 static void r8169_phylink_handler(struct net_device *ndev)
4676 {
4677         struct rtl8169_private *tp = netdev_priv(ndev);
4678         struct device *d = tp_to_dev(tp);
4679
4680         if (netif_carrier_ok(ndev)) {
4681                 rtl_link_chg_patch(tp);
4682                 pm_request_resume(d);
4683                 netif_wake_queue(tp->dev);
4684         } else {
4685                 /* In few cases rx is broken after link-down otherwise */
4686                 if (rtl_is_8125(tp))
4687                         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_NO_QUEUE_WAKE);
4688                 pm_runtime_idle(d);
4689         }
4690
4691         phy_print_status(tp->phydev);
4692 }
4693
4694 static int r8169_phy_connect(struct rtl8169_private *tp)
4695 {
4696         struct phy_device *phydev = tp->phydev;
4697         phy_interface_t phy_mode;
4698         int ret;
4699
4700         phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
4701                    PHY_INTERFACE_MODE_MII;
4702
4703         ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
4704                                  phy_mode);
4705         if (ret)
4706                 return ret;
4707
4708         if (!tp->supports_gmii)
4709                 phy_set_max_speed(phydev, SPEED_100);
4710
4711         phy_attached_info(phydev);
4712
4713         return 0;
4714 }
4715
4716 static void rtl8169_down(struct rtl8169_private *tp)
4717 {
4718         /* Clear all task flags */
4719         bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
4720
4721         phy_stop(tp->phydev);
4722
4723         rtl8169_update_counters(tp);
4724
4725         pci_clear_master(tp->pci_dev);
4726         rtl_pci_commit(tp);
4727
4728         rtl8169_cleanup(tp);
4729         rtl_disable_exit_l1(tp);
4730         rtl_prepare_power_down(tp);
4731
4732         if (tp->dash_type != RTL_DASH_NONE)
4733                 rtl8168_driver_stop(tp);
4734 }
4735
4736 static void rtl8169_up(struct rtl8169_private *tp)
4737 {
4738         if (tp->dash_type != RTL_DASH_NONE)
4739                 rtl8168_driver_start(tp);
4740
4741         pci_set_master(tp->pci_dev);
4742         phy_init_hw(tp->phydev);
4743         phy_resume(tp->phydev);
4744         rtl8169_init_phy(tp);
4745         napi_enable(&tp->napi);
4746         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
4747         rtl_reset_work(tp);
4748
4749         phy_start(tp->phydev);
4750 }
4751
4752 static int rtl8169_close(struct net_device *dev)
4753 {
4754         struct rtl8169_private *tp = netdev_priv(dev);
4755         struct pci_dev *pdev = tp->pci_dev;
4756
4757         pm_runtime_get_sync(&pdev->dev);
4758
4759         netif_stop_queue(dev);
4760         rtl8169_down(tp);
4761         rtl8169_rx_clear(tp);
4762
4763         cancel_work(&tp->wk.work);
4764
4765         free_irq(tp->irq, tp);
4766
4767         phy_disconnect(tp->phydev);
4768
4769         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4770                           tp->RxPhyAddr);
4771         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4772                           tp->TxPhyAddr);
4773         tp->TxDescArray = NULL;
4774         tp->RxDescArray = NULL;
4775
4776         pm_runtime_put_sync(&pdev->dev);
4777
4778         return 0;
4779 }
4780
4781 #ifdef CONFIG_NET_POLL_CONTROLLER
4782 static void rtl8169_netpoll(struct net_device *dev)
4783 {
4784         struct rtl8169_private *tp = netdev_priv(dev);
4785
4786         rtl8169_interrupt(tp->irq, tp);
4787 }
4788 #endif
4789
4790 static int rtl_open(struct net_device *dev)
4791 {
4792         struct rtl8169_private *tp = netdev_priv(dev);
4793         struct pci_dev *pdev = tp->pci_dev;
4794         unsigned long irqflags;
4795         int retval = -ENOMEM;
4796
4797         pm_runtime_get_sync(&pdev->dev);
4798
4799         /*
4800          * Rx and Tx descriptors needs 256 bytes alignment.
4801          * dma_alloc_coherent provides more.
4802          */
4803         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
4804                                              &tp->TxPhyAddr, GFP_KERNEL);
4805         if (!tp->TxDescArray)
4806                 goto out;
4807
4808         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
4809                                              &tp->RxPhyAddr, GFP_KERNEL);
4810         if (!tp->RxDescArray)
4811                 goto err_free_tx_0;
4812
4813         retval = rtl8169_init_ring(tp);
4814         if (retval < 0)
4815                 goto err_free_rx_1;
4816
4817         rtl_request_firmware(tp);
4818
4819         irqflags = pci_dev_msi_enabled(pdev) ? IRQF_NO_THREAD : IRQF_SHARED;
4820         retval = request_irq(tp->irq, rtl8169_interrupt, irqflags, dev->name, tp);
4821         if (retval < 0)
4822                 goto err_release_fw_2;
4823
4824         retval = r8169_phy_connect(tp);
4825         if (retval)
4826                 goto err_free_irq;
4827
4828         rtl8169_up(tp);
4829         rtl8169_init_counter_offsets(tp);
4830         netif_start_queue(dev);
4831 out:
4832         pm_runtime_put_sync(&pdev->dev);
4833
4834         return retval;
4835
4836 err_free_irq:
4837         free_irq(tp->irq, tp);
4838 err_release_fw_2:
4839         rtl_release_firmware(tp);
4840         rtl8169_rx_clear(tp);
4841 err_free_rx_1:
4842         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4843                           tp->RxPhyAddr);
4844         tp->RxDescArray = NULL;
4845 err_free_tx_0:
4846         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4847                           tp->TxPhyAddr);
4848         tp->TxDescArray = NULL;
4849         goto out;
4850 }
4851
4852 static void
4853 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
4854 {
4855         struct rtl8169_private *tp = netdev_priv(dev);
4856         struct pci_dev *pdev = tp->pci_dev;
4857         struct rtl8169_counters *counters = tp->counters;
4858
4859         pm_runtime_get_noresume(&pdev->dev);
4860
4861         netdev_stats_to_stats64(stats, &dev->stats);
4862         dev_fetch_sw_netstats(stats, dev->tstats);
4863
4864         /*
4865          * Fetch additional counter values missing in stats collected by driver
4866          * from tally counters.
4867          */
4868         if (pm_runtime_active(&pdev->dev))
4869                 rtl8169_update_counters(tp);
4870
4871         /*
4872          * Subtract values fetched during initalization.
4873          * See rtl8169_init_counter_offsets for a description why we do that.
4874          */
4875         stats->tx_errors = le64_to_cpu(counters->tx_errors) -
4876                 le64_to_cpu(tp->tc_offset.tx_errors);
4877         stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
4878                 le32_to_cpu(tp->tc_offset.tx_multi_collision);
4879         stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
4880                 le16_to_cpu(tp->tc_offset.tx_aborted);
4881         stats->rx_missed_errors = le16_to_cpu(counters->rx_missed) -
4882                 le16_to_cpu(tp->tc_offset.rx_missed);
4883
4884         pm_runtime_put_noidle(&pdev->dev);
4885 }
4886
4887 static void rtl8169_net_suspend(struct rtl8169_private *tp)
4888 {
4889         netif_device_detach(tp->dev);
4890
4891         if (netif_running(tp->dev))
4892                 rtl8169_down(tp);
4893 }
4894
4895 static int rtl8169_runtime_resume(struct device *dev)
4896 {
4897         struct rtl8169_private *tp = dev_get_drvdata(dev);
4898
4899         rtl_rar_set(tp, tp->dev->dev_addr);
4900         __rtl8169_set_wol(tp, tp->saved_wolopts);
4901
4902         if (tp->TxDescArray)
4903                 rtl8169_up(tp);
4904
4905         netif_device_attach(tp->dev);
4906
4907         return 0;
4908 }
4909
4910 static int rtl8169_suspend(struct device *device)
4911 {
4912         struct rtl8169_private *tp = dev_get_drvdata(device);
4913
4914         rtnl_lock();
4915         rtl8169_net_suspend(tp);
4916         if (!device_may_wakeup(tp_to_dev(tp)))
4917                 clk_disable_unprepare(tp->clk);
4918         rtnl_unlock();
4919
4920         return 0;
4921 }
4922
4923 static int rtl8169_resume(struct device *device)
4924 {
4925         struct rtl8169_private *tp = dev_get_drvdata(device);
4926
4927         if (!device_may_wakeup(tp_to_dev(tp)))
4928                 clk_prepare_enable(tp->clk);
4929
4930         /* Reportedly at least Asus X453MA truncates packets otherwise */
4931         if (tp->mac_version == RTL_GIGA_MAC_VER_37)
4932                 rtl_init_rxcfg(tp);
4933
4934         return rtl8169_runtime_resume(device);
4935 }
4936
4937 static int rtl8169_runtime_suspend(struct device *device)
4938 {
4939         struct rtl8169_private *tp = dev_get_drvdata(device);
4940
4941         if (!tp->TxDescArray) {
4942                 netif_device_detach(tp->dev);
4943                 return 0;
4944         }
4945
4946         rtnl_lock();
4947         __rtl8169_set_wol(tp, WAKE_PHY);
4948         rtl8169_net_suspend(tp);
4949         rtnl_unlock();
4950
4951         return 0;
4952 }
4953
4954 static int rtl8169_runtime_idle(struct device *device)
4955 {
4956         struct rtl8169_private *tp = dev_get_drvdata(device);
4957
4958         if (tp->dash_enabled)
4959                 return -EBUSY;
4960
4961         if (!netif_running(tp->dev) || !netif_carrier_ok(tp->dev))
4962                 pm_schedule_suspend(device, 10000);
4963
4964         return -EBUSY;
4965 }
4966
4967 static const struct dev_pm_ops rtl8169_pm_ops = {
4968         SYSTEM_SLEEP_PM_OPS(rtl8169_suspend, rtl8169_resume)
4969         RUNTIME_PM_OPS(rtl8169_runtime_suspend, rtl8169_runtime_resume,
4970                        rtl8169_runtime_idle)
4971 };
4972
4973 static void rtl_shutdown(struct pci_dev *pdev)
4974 {
4975         struct rtl8169_private *tp = pci_get_drvdata(pdev);
4976
4977         rtnl_lock();
4978         rtl8169_net_suspend(tp);
4979         rtnl_unlock();
4980
4981         /* Restore original MAC address */
4982         rtl_rar_set(tp, tp->dev->perm_addr);
4983
4984         if (system_state == SYSTEM_POWER_OFF && !tp->dash_enabled) {
4985                 pci_wake_from_d3(pdev, tp->saved_wolopts);
4986                 pci_set_power_state(pdev, PCI_D3hot);
4987         }
4988 }
4989
4990 static void rtl_remove_one(struct pci_dev *pdev)
4991 {
4992         struct rtl8169_private *tp = pci_get_drvdata(pdev);
4993
4994         if (pci_dev_run_wake(pdev))
4995                 pm_runtime_get_noresume(&pdev->dev);
4996
4997         cancel_work_sync(&tp->wk.work);
4998
4999         unregister_netdev(tp->dev);
5000
5001         if (tp->dash_type != RTL_DASH_NONE)
5002                 rtl8168_driver_stop(tp);
5003
5004         rtl_release_firmware(tp);
5005
5006         /* restore original MAC address */
5007         rtl_rar_set(tp, tp->dev->perm_addr);
5008 }
5009
5010 static const struct net_device_ops rtl_netdev_ops = {
5011         .ndo_open               = rtl_open,
5012         .ndo_stop               = rtl8169_close,
5013         .ndo_get_stats64        = rtl8169_get_stats64,
5014         .ndo_start_xmit         = rtl8169_start_xmit,
5015         .ndo_features_check     = rtl8169_features_check,
5016         .ndo_tx_timeout         = rtl8169_tx_timeout,
5017         .ndo_validate_addr      = eth_validate_addr,
5018         .ndo_change_mtu         = rtl8169_change_mtu,
5019         .ndo_fix_features       = rtl8169_fix_features,
5020         .ndo_set_features       = rtl8169_set_features,
5021         .ndo_set_mac_address    = rtl_set_mac_address,
5022         .ndo_eth_ioctl          = phy_do_ioctl_running,
5023         .ndo_set_rx_mode        = rtl_set_rx_mode,
5024 #ifdef CONFIG_NET_POLL_CONTROLLER
5025         .ndo_poll_controller    = rtl8169_netpoll,
5026 #endif
5027
5028 };
5029
5030 static void rtl_set_irq_mask(struct rtl8169_private *tp)
5031 {
5032         tp->irq_mask = RxOK | RxErr | TxOK | TxErr | LinkChg;
5033
5034         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
5035                 tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver;
5036         else if (tp->mac_version == RTL_GIGA_MAC_VER_11)
5037                 /* special workaround needed */
5038                 tp->irq_mask |= RxFIFOOver;
5039         else
5040                 tp->irq_mask |= RxOverflow;
5041 }
5042
5043 static int rtl_alloc_irq(struct rtl8169_private *tp)
5044 {
5045         unsigned int flags;
5046
5047         switch (tp->mac_version) {
5048         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
5049                 rtl_unlock_config_regs(tp);
5050                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
5051                 rtl_lock_config_regs(tp);
5052                 fallthrough;
5053         case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_17:
5054                 flags = PCI_IRQ_LEGACY;
5055                 break;
5056         default:
5057                 flags = PCI_IRQ_ALL_TYPES;
5058                 break;
5059         }
5060
5061         return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
5062 }
5063
5064 static void rtl_read_mac_address(struct rtl8169_private *tp,
5065                                  u8 mac_addr[ETH_ALEN])
5066 {
5067         /* Get MAC address */
5068         if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) {
5069                 u32 value;
5070
5071                 value = rtl_eri_read(tp, 0xe0);
5072                 put_unaligned_le32(value, mac_addr);
5073                 value = rtl_eri_read(tp, 0xe4);
5074                 put_unaligned_le16(value, mac_addr + 4);
5075         } else if (rtl_is_8125(tp)) {
5076                 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP);
5077         }
5078 }
5079
5080 DECLARE_RTL_COND(rtl_link_list_ready_cond)
5081 {
5082         return RTL_R8(tp, MCU) & LINK_LIST_RDY;
5083 }
5084
5085 static void r8168g_wait_ll_share_fifo_ready(struct rtl8169_private *tp)
5086 {
5087         rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42);
5088 }
5089
5090 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
5091 {
5092         struct rtl8169_private *tp = mii_bus->priv;
5093
5094         if (phyaddr > 0)
5095                 return -ENODEV;
5096
5097         return rtl_readphy(tp, phyreg);
5098 }
5099
5100 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
5101                                 int phyreg, u16 val)
5102 {
5103         struct rtl8169_private *tp = mii_bus->priv;
5104
5105         if (phyaddr > 0)
5106                 return -ENODEV;
5107
5108         rtl_writephy(tp, phyreg, val);
5109
5110         return 0;
5111 }
5112
5113 static int r8169_mdio_register(struct rtl8169_private *tp)
5114 {
5115         struct pci_dev *pdev = tp->pci_dev;
5116         struct mii_bus *new_bus;
5117         int ret;
5118
5119         new_bus = devm_mdiobus_alloc(&pdev->dev);
5120         if (!new_bus)
5121                 return -ENOMEM;
5122
5123         new_bus->name = "r8169";
5124         new_bus->priv = tp;
5125         new_bus->parent = &pdev->dev;
5126         new_bus->irq[0] = PHY_MAC_INTERRUPT;
5127         snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x-%x",
5128                  pci_domain_nr(pdev->bus), pci_dev_id(pdev));
5129
5130         new_bus->read = r8169_mdio_read_reg;
5131         new_bus->write = r8169_mdio_write_reg;
5132
5133         ret = devm_mdiobus_register(&pdev->dev, new_bus);
5134         if (ret)
5135                 return ret;
5136
5137         tp->phydev = mdiobus_get_phy(new_bus, 0);
5138         if (!tp->phydev) {
5139                 return -ENODEV;
5140         } else if (!tp->phydev->drv) {
5141                 /* Most chip versions fail with the genphy driver.
5142                  * Therefore ensure that the dedicated PHY driver is loaded.
5143                  */
5144                 dev_err(&pdev->dev, "no dedicated PHY driver found for PHY ID 0x%08x, maybe realtek.ko needs to be added to initramfs?\n",
5145                         tp->phydev->phy_id);
5146                 return -EUNATCH;
5147         }
5148
5149         tp->phydev->mac_managed_pm = true;
5150         if (rtl_supports_eee(tp))
5151                 phy_advertise_eee_all(tp->phydev);
5152         phy_support_asym_pause(tp->phydev);
5153
5154         /* PHY will be woken up in rtl_open() */
5155         phy_suspend(tp->phydev);
5156
5157         return 0;
5158 }
5159
5160 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
5161 {
5162         rtl_enable_rxdvgate(tp);
5163
5164         RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
5165         msleep(1);
5166         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5167
5168         r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
5169         r8168g_wait_ll_share_fifo_ready(tp);
5170
5171         r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15));
5172         r8168g_wait_ll_share_fifo_ready(tp);
5173 }
5174
5175 static void rtl_hw_init_8125(struct rtl8169_private *tp)
5176 {
5177         rtl_enable_rxdvgate(tp);
5178
5179         RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
5180         msleep(1);
5181         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5182
5183         r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
5184         r8168g_wait_ll_share_fifo_ready(tp);
5185
5186         r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0);
5187         r8168_mac_ocp_write(tp, 0xc0a6, 0x0150);
5188         r8168_mac_ocp_write(tp, 0xc01e, 0x5555);
5189         r8168g_wait_ll_share_fifo_ready(tp);
5190 }
5191
5192 static void rtl_hw_initialize(struct rtl8169_private *tp)
5193 {
5194         switch (tp->mac_version) {
5195         case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_53:
5196                 rtl8168ep_stop_cmac(tp);
5197                 fallthrough;
5198         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
5199                 rtl_hw_init_8168g(tp);
5200                 break;
5201         case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_65:
5202                 rtl_hw_init_8125(tp);
5203                 break;
5204         default:
5205                 break;
5206         }
5207 }
5208
5209 static int rtl_jumbo_max(struct rtl8169_private *tp)
5210 {
5211         /* Non-GBit versions don't support jumbo frames */
5212         if (!tp->supports_gmii)
5213                 return 0;
5214
5215         switch (tp->mac_version) {
5216         /* RTL8169 */
5217         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
5218                 return JUMBO_7K;
5219         /* RTL8168b */
5220         case RTL_GIGA_MAC_VER_11:
5221         case RTL_GIGA_MAC_VER_17:
5222                 return JUMBO_4K;
5223         /* RTL8168c */
5224         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
5225                 return JUMBO_6K;
5226         default:
5227                 return JUMBO_9K;
5228         }
5229 }
5230
5231 static void rtl_init_mac_address(struct rtl8169_private *tp)
5232 {
5233         u8 mac_addr[ETH_ALEN] __aligned(2) = {};
5234         struct net_device *dev = tp->dev;
5235         int rc;
5236
5237         rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr);
5238         if (!rc)
5239                 goto done;
5240
5241         rtl_read_mac_address(tp, mac_addr);
5242         if (is_valid_ether_addr(mac_addr))
5243                 goto done;
5244
5245         rtl_read_mac_from_reg(tp, mac_addr, MAC0);
5246         if (is_valid_ether_addr(mac_addr))
5247                 goto done;
5248
5249         eth_random_addr(mac_addr);
5250         dev->addr_assign_type = NET_ADDR_RANDOM;
5251         dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n");
5252 done:
5253         eth_hw_addr_set(dev, mac_addr);
5254         rtl_rar_set(tp, mac_addr);
5255 }
5256
5257 /* register is set if system vendor successfully tested ASPM 1.2 */
5258 static bool rtl_aspm_is_safe(struct rtl8169_private *tp)
5259 {
5260         if (tp->mac_version >= RTL_GIGA_MAC_VER_61 &&
5261             r8168_mac_ocp_read(tp, 0xc0b2) & 0xf)
5262                 return true;
5263
5264         return false;
5265 }
5266
5267 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
5268 {
5269         struct rtl8169_private *tp;
5270         int jumbo_max, region, rc;
5271         enum mac_version chipset;
5272         struct net_device *dev;
5273         u32 txconfig;
5274         u16 xid;
5275
5276         dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
5277         if (!dev)
5278                 return -ENOMEM;
5279
5280         SET_NETDEV_DEV(dev, &pdev->dev);
5281         dev->netdev_ops = &rtl_netdev_ops;
5282         tp = netdev_priv(dev);
5283         tp->dev = dev;
5284         tp->pci_dev = pdev;
5285         tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1;
5286         tp->ocp_base = OCP_STD_PHY_BASE;
5287
5288         raw_spin_lock_init(&tp->cfg9346_usage_lock);
5289         raw_spin_lock_init(&tp->config25_lock);
5290         raw_spin_lock_init(&tp->mac_ocp_lock);
5291         mutex_init(&tp->led_lock);
5292
5293         /* Get the *optional* external "ether_clk" used on some boards */
5294         tp->clk = devm_clk_get_optional_enabled(&pdev->dev, "ether_clk");
5295         if (IS_ERR(tp->clk))
5296                 return dev_err_probe(&pdev->dev, PTR_ERR(tp->clk), "failed to get ether_clk\n");
5297
5298         /* enable device (incl. PCI PM wakeup and hotplug setup) */
5299         rc = pcim_enable_device(pdev);
5300         if (rc < 0)
5301                 return dev_err_probe(&pdev->dev, rc, "enable failure\n");
5302
5303         if (pcim_set_mwi(pdev) < 0)
5304                 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
5305
5306         /* use first MMIO region */
5307         region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
5308         if (region < 0)
5309                 return dev_err_probe(&pdev->dev, -ENODEV, "no MMIO resource found\n");
5310
5311         rc = pcim_iomap_regions(pdev, BIT(region), KBUILD_MODNAME);
5312         if (rc < 0)
5313                 return dev_err_probe(&pdev->dev, rc, "cannot remap MMIO, aborting\n");
5314
5315         tp->mmio_addr = pcim_iomap_table(pdev)[region];
5316
5317         txconfig = RTL_R32(tp, TxConfig);
5318         if (txconfig == ~0U)
5319                 return dev_err_probe(&pdev->dev, -EIO, "PCI read failed\n");
5320
5321         xid = (txconfig >> 20) & 0xfcf;
5322
5323         /* Identify chip attached to board */
5324         chipset = rtl8169_get_mac_version(xid, tp->supports_gmii);
5325         if (chipset == RTL_GIGA_MAC_NONE)
5326                 return dev_err_probe(&pdev->dev, -ENODEV,
5327                                      "unknown chip XID %03x, contact r8169 maintainers (see MAINTAINERS file)\n",
5328                                      xid);
5329         tp->mac_version = chipset;
5330
5331         /* Disable ASPM L1 as that cause random device stop working
5332          * problems as well as full system hangs for some PCIe devices users.
5333          */
5334         if (rtl_aspm_is_safe(tp))
5335                 rc = 0;
5336         else
5337                 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L1);
5338         tp->aspm_manageable = !rc;
5339
5340         tp->dash_type = rtl_get_dash_type(tp);
5341         tp->dash_enabled = rtl_dash_is_enabled(tp);
5342
5343         tp->cp_cmd = RTL_R16(tp, CPlusCmd) & CPCMD_MASK;
5344
5345         if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 &&
5346             !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)))
5347                 dev->features |= NETIF_F_HIGHDMA;
5348
5349         rtl_init_rxcfg(tp);
5350
5351         rtl8169_irq_mask_and_ack(tp);
5352
5353         rtl_hw_initialize(tp);
5354
5355         rtl_hw_reset(tp);
5356
5357         rc = rtl_alloc_irq(tp);
5358         if (rc < 0)
5359                 return dev_err_probe(&pdev->dev, rc, "Can't allocate interrupt\n");
5360
5361         tp->irq = pci_irq_vector(pdev, 0);
5362
5363         INIT_WORK(&tp->wk.work, rtl_task);
5364
5365         rtl_init_mac_address(tp);
5366
5367         dev->ethtool_ops = &rtl8169_ethtool_ops;
5368
5369         netif_napi_add(dev, &tp->napi, rtl8169_poll);
5370
5371         dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
5372                            NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
5373         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO;
5374         dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
5375
5376         /*
5377          * Pretend we are using VLANs; This bypasses a nasty bug where
5378          * Interrupts stop flowing on high load on 8110SCd controllers.
5379          */
5380         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
5381                 /* Disallow toggling */
5382                 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
5383
5384         if (rtl_chip_supports_csum_v2(tp))
5385                 dev->hw_features |= NETIF_F_IPV6_CSUM;
5386
5387         dev->features |= dev->hw_features;
5388
5389         /* There has been a number of reports that using SG/TSO results in
5390          * tx timeouts. However for a lot of people SG/TSO works fine.
5391          * Therefore disable both features by default, but allow users to
5392          * enable them. Use at own risk!
5393          */
5394         if (rtl_chip_supports_csum_v2(tp)) {
5395                 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6;
5396                 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V2);
5397                 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V2);
5398         } else {
5399                 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO;
5400                 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V1);
5401                 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V1);
5402         }
5403
5404         dev->hw_features |= NETIF_F_RXALL;
5405         dev->hw_features |= NETIF_F_RXFCS;
5406
5407         dev->pcpu_stat_type = NETDEV_PCPU_STAT_TSTATS;
5408
5409         netdev_sw_irq_coalesce_default_on(dev);
5410
5411         /* configure chip for default features */
5412         rtl8169_set_features(dev, dev->features);
5413
5414         if (!tp->dash_enabled) {
5415                 rtl_set_d3_pll_down(tp, true);
5416         } else {
5417                 rtl_set_d3_pll_down(tp, false);
5418                 dev->wol_enabled = 1;
5419         }
5420
5421         jumbo_max = rtl_jumbo_max(tp);
5422         if (jumbo_max)
5423                 dev->max_mtu = jumbo_max;
5424
5425         rtl_set_irq_mask(tp);
5426
5427         tp->fw_name = rtl_chip_infos[chipset].fw_name;
5428
5429         tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
5430                                             &tp->counters_phys_addr,
5431                                             GFP_KERNEL);
5432         if (!tp->counters)
5433                 return -ENOMEM;
5434
5435         pci_set_drvdata(pdev, tp);
5436
5437         rc = r8169_mdio_register(tp);
5438         if (rc)
5439                 return rc;
5440
5441         rc = register_netdev(dev);
5442         if (rc)
5443                 return rc;
5444
5445         if (IS_ENABLED(CONFIG_R8169_LEDS)) {
5446                 if (rtl_is_8125(tp))
5447                         rtl8125_init_leds(dev);
5448                 else if (tp->mac_version > RTL_GIGA_MAC_VER_06)
5449                         rtl8168_init_leds(dev);
5450         }
5451
5452         netdev_info(dev, "%s, %pM, XID %03x, IRQ %d\n",
5453                     rtl_chip_infos[chipset].name, dev->dev_addr, xid, tp->irq);
5454
5455         if (jumbo_max)
5456                 netdev_info(dev, "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
5457                             jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?
5458                             "ok" : "ko");
5459
5460         if (tp->dash_type != RTL_DASH_NONE) {
5461                 netdev_info(dev, "DASH %s\n",
5462                             tp->dash_enabled ? "enabled" : "disabled");
5463                 rtl8168_driver_start(tp);
5464         }
5465
5466         if (pci_dev_run_wake(pdev))
5467                 pm_runtime_put_sync(&pdev->dev);
5468
5469         return 0;
5470 }
5471
5472 static struct pci_driver rtl8169_pci_driver = {
5473         .name           = KBUILD_MODNAME,
5474         .id_table       = rtl8169_pci_tbl,
5475         .probe          = rtl_init_one,
5476         .remove         = rtl_remove_one,
5477         .shutdown       = rtl_shutdown,
5478         .driver.pm      = pm_ptr(&rtl8169_pm_ops),
5479 };
5480
5481 module_pci_driver(rtl8169_pci_driver);