drivers/net/ethernet/realtek/r8169_main.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   4  *
   5  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   6  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   7  * Copyright (c) a lot of people too. Please respect their work.
   8  *
   9  * See MAINTAINERS file for support contact information.
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/clk.h>
  17 #include <linux/delay.h>
  18 #include <linux/ethtool.h>
  19 #include <linux/phy.h>
  20 #include <linux/if_vlan.h>
  21 #include <linux/in.h>
  22 #include <linux/io.h>
  23 #include <linux/ip.h>
  24 #include <linux/tcp.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/pm_runtime.h>
  28 #include <linux/bitfield.h>
  29 #include <linux/prefetch.h>
  30 #include <linux/ipv6.h>
  31 #include <asm/unaligned.h>
  32 #include <net/ip6_checksum.h>
  33 #include <net/netdev_queues.h>
  34
  35 #include "r8169.h"
  36 #include "r8169_firmware.h"
  37
  38 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  39 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  40 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  41 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  42 #define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
  43 #define FIRMWARE_8168F_1        "rtl_nic/rtl8168f-1.fw"
  44 #define FIRMWARE_8168F_2        "rtl_nic/rtl8168f-2.fw"
  45 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  46 #define FIRMWARE_8402_1         "rtl_nic/rtl8402-1.fw"
  47 #define FIRMWARE_8411_1         "rtl_nic/rtl8411-1.fw"
  48 #define FIRMWARE_8411_2         "rtl_nic/rtl8411-2.fw"
  49 #define FIRMWARE_8106E_1        "rtl_nic/rtl8106e-1.fw"
  50 #define FIRMWARE_8106E_2        "rtl_nic/rtl8106e-2.fw"
  51 #define FIRMWARE_8168G_2        "rtl_nic/rtl8168g-2.fw"
  52 #define FIRMWARE_8168G_3        "rtl_nic/rtl8168g-3.fw"
  53 #define FIRMWARE_8168H_2        "rtl_nic/rtl8168h-2.fw"
  54 #define FIRMWARE_8168FP_3       "rtl_nic/rtl8168fp-3.fw"
  55 #define FIRMWARE_8107E_2        "rtl_nic/rtl8107e-2.fw"
  56 #define FIRMWARE_8125A_3        "rtl_nic/rtl8125a-3.fw"
  57 #define FIRMWARE_8125B_2        "rtl_nic/rtl8125b-2.fw"
  58
  59 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  60    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  61 #define MC_FILTER_LIMIT 32
  62
  63 #define TX_DMA_BURST    7       /* Maximum PCI burst, '7' is unlimited */
  64 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  65
  66 #define R8169_REGS_SIZE         256
  67 #define R8169_RX_BUF_SIZE       (SZ_16K - 1)
  68 #define NUM_TX_DESC     256     /* Number of Tx descriptor registers */
  69 #define NUM_RX_DESC     256     /* Number of Rx descriptor registers */
  70 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  71 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  72 #define R8169_TX_STOP_THRS      (MAX_SKB_FRAGS + 1)
  73 #define R8169_TX_START_THRS     (2 * R8169_TX_STOP_THRS)
  74
  75 #define OCP_STD_PHY_BASE        0xa400
  76
  77 #define RTL_CFG_NO_GBIT 1
  78
  79 /* write/read MMIO register */
  80 #define RTL_W8(tp, reg, val8)   writeb((val8), tp->mmio_addr + (reg))
  81 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
  82 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
  83 #define RTL_R8(tp, reg)         readb(tp->mmio_addr + (reg))
  84 #define RTL_R16(tp, reg)                readw(tp->mmio_addr + (reg))
  85 #define RTL_R32(tp, reg)                readl(tp->mmio_addr + (reg))
  86
  87 #define JUMBO_4K        (4 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
  88 #define JUMBO_6K        (6 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
  89 #define JUMBO_7K        (7 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
  90 #define JUMBO_9K        (9 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
  91
  92 static const struct {
  93         const char *name;
  94         const char *fw_name;
  95 } rtl_chip_infos[] = {
  96         /* PCI devices. */
  97         [RTL_GIGA_MAC_VER_02] = {"RTL8169s"                             },
  98         [RTL_GIGA_MAC_VER_03] = {"RTL8110s"                             },
  99         [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb"                     },
 100         [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc"                     },
 101         [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc"                     },
 102         /* PCI-E devices. */
 103         [RTL_GIGA_MAC_VER_07] = {"RTL8102e"                             },
 104         [RTL_GIGA_MAC_VER_08] = {"RTL8102e"                             },
 105         [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e"                    },
 106         [RTL_GIGA_MAC_VER_10] = {"RTL8101e/RTL8100e"                    },
 107         [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b"                       },
 108         [RTL_GIGA_MAC_VER_14] = {"RTL8401"                              },
 109         [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b"                       },
 110         [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp"                     },
 111         [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c"                       },
 112         [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c"                       },
 113         [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c"                       },
 114         [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c"                       },
 115         [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp"                     },
 116         [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp"                     },
 117         [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d",      FIRMWARE_8168D_1},
 118         [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d",      FIRMWARE_8168D_2},
 119         [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp"                     },
 120         [RTL_GIGA_MAC_VER_29] = {"RTL8105e",            FIRMWARE_8105E_1},
 121         [RTL_GIGA_MAC_VER_30] = {"RTL8105e",            FIRMWARE_8105E_1},
 122         [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp"                     },
 123         [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e",      FIRMWARE_8168E_1},
 124         [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e",      FIRMWARE_8168E_2},
 125         [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl",  FIRMWARE_8168E_3},
 126         [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f",      FIRMWARE_8168F_1},
 127         [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f",      FIRMWARE_8168F_2},
 128         [RTL_GIGA_MAC_VER_37] = {"RTL8402",             FIRMWARE_8402_1 },
 129         [RTL_GIGA_MAC_VER_38] = {"RTL8411",             FIRMWARE_8411_1 },
 130         [RTL_GIGA_MAC_VER_39] = {"RTL8106e",            FIRMWARE_8106E_1},
 131         [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g",      FIRMWARE_8168G_2},
 132         [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu",    FIRMWARE_8168G_3},
 133         [RTL_GIGA_MAC_VER_43] = {"RTL8106eus",          FIRMWARE_8106E_2},
 134         [RTL_GIGA_MAC_VER_44] = {"RTL8411b",            FIRMWARE_8411_2 },
 135         [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h",      FIRMWARE_8168H_2},
 136         [RTL_GIGA_MAC_VER_48] = {"RTL8107e",            FIRMWARE_8107E_2},
 137         [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep"                     },
 138         [RTL_GIGA_MAC_VER_52] = {"RTL8168fp/RTL8117",  FIRMWARE_8168FP_3},
 139         [RTL_GIGA_MAC_VER_53] = {"RTL8168fp/RTL8117",                   },
 140         [RTL_GIGA_MAC_VER_61] = {"RTL8125A",            FIRMWARE_8125A_3},
 141         /* reserve 62 for CFG_METHOD_4 in the vendor driver */
 142         [RTL_GIGA_MAC_VER_63] = {"RTL8125B",            FIRMWARE_8125B_2},
 143 };
 144
 145 static const struct pci_device_id rtl8169_pci_tbl[] = {
 146         { PCI_VDEVICE(REALTEK,  0x2502) },
 147         { PCI_VDEVICE(REALTEK,  0x2600) },
 148         { PCI_VDEVICE(REALTEK,  0x8129) },
 149         { PCI_VDEVICE(REALTEK,  0x8136), RTL_CFG_NO_GBIT },
 150         { PCI_VDEVICE(REALTEK,  0x8161) },
 151         { PCI_VDEVICE(REALTEK,  0x8162) },
 152         { PCI_VDEVICE(REALTEK,  0x8167) },
 153         { PCI_VDEVICE(REALTEK,  0x8168) },
 154         { PCI_VDEVICE(NCUBE,    0x8168) },
 155         { PCI_VDEVICE(REALTEK,  0x8169) },
 156         { PCI_VENDOR_ID_DLINK,  0x4300,
 157                 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 },
 158         { PCI_VDEVICE(DLINK,    0x4300) },
 159         { PCI_VDEVICE(DLINK,    0x4302) },
 160         { PCI_VDEVICE(AT,       0xc107) },
 161         { PCI_VDEVICE(USR,      0x0116) },
 162         { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 },
 163         { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 },
 164         { PCI_VDEVICE(REALTEK,  0x8125) },
 165         { PCI_VDEVICE(REALTEK,  0x3000) },
 166         {}
 167 };
 168
 169 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 170
 171 enum rtl_registers {
 172         MAC0            = 0,    /* Ethernet hardware address. */
 173         MAC4            = 4,
 174         MAR0            = 8,    /* Multicast filter. */
 175         CounterAddrLow          = 0x10,
 176         CounterAddrHigh         = 0x14,
 177         TxDescStartAddrLow      = 0x20,
 178         TxDescStartAddrHigh     = 0x24,
 179         TxHDescStartAddrLow     = 0x28,
 180         TxHDescStartAddrHigh    = 0x2c,
 181         FLASH           = 0x30,
 182         ERSR            = 0x36,
 183         ChipCmd         = 0x37,
 184         TxPoll          = 0x38,
 185         IntrMask        = 0x3c,
 186         IntrStatus      = 0x3e,
 187
 188         TxConfig        = 0x40,
 189 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 190 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 191
 192         RxConfig        = 0x44,
 193 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 194 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 195 #define RXCFG_FIFO_SHIFT                13
 196                                         /* No threshold before first PCI xfer */
 197 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 198 #define RX_EARLY_OFF                    (1 << 11)
 199 #define RXCFG_DMA_SHIFT                 8
 200                                         /* Unlimited maximum PCI burst. */
 201 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 202
 203         Cfg9346         = 0x50,
 204         Config0         = 0x51,
 205         Config1         = 0x52,
 206         Config2         = 0x53,
 207 #define PME_SIGNAL                      (1 << 5)        /* 8168c and later */
 208
 209         Config3         = 0x54,
 210         Config4         = 0x55,
 211         Config5         = 0x56,
 212         PHYAR           = 0x60,
 213         PHYstatus       = 0x6c,
 214         RxMaxSize       = 0xda,
 215         CPlusCmd        = 0xe0,
 216         IntrMitigate    = 0xe2,
 217
 218 #define RTL_COALESCE_TX_USECS   GENMASK(15, 12)
 219 #define RTL_COALESCE_TX_FRAMES  GENMASK(11, 8)
 220 #define RTL_COALESCE_RX_USECS   GENMASK(7, 4)
 221 #define RTL_COALESCE_RX_FRAMES  GENMASK(3, 0)
 222
 223 #define RTL_COALESCE_T_MAX      0x0fU
 224 #define RTL_COALESCE_FRAME_MAX  (RTL_COALESCE_T_MAX * 4)
 225
 226         RxDescAddrLow   = 0xe4,
 227         RxDescAddrHigh  = 0xe8,
 228         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 229
 230 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 231
 232         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 233
 234 #define TxPacketMax     (8064 >> 7)
 235 #define EarlySize       0x27
 236
 237         FuncEvent       = 0xf0,
 238         FuncEventMask   = 0xf4,
 239         FuncPresetState = 0xf8,
 240         IBCR0           = 0xf8,
 241         IBCR2           = 0xf9,
 242         IBIMR0          = 0xfa,
 243         IBISR0          = 0xfb,
 244         FuncForceEvent  = 0xfc,
 245 };
 246
 247 enum rtl8168_8101_registers {
 248         CSIDR                   = 0x64,
 249         CSIAR                   = 0x68,
 250 #define CSIAR_FLAG                      0x80000000
 251 #define CSIAR_WRITE_CMD                 0x80000000
 252 #define CSIAR_BYTE_ENABLE               0x0000f000
 253 #define CSIAR_ADDR_MASK                 0x00000fff
 254         PMCH                    = 0x6f,
 255 #define D3COLD_NO_PLL_DOWN              BIT(7)
 256 #define D3HOT_NO_PLL_DOWN               BIT(6)
 257 #define D3_NO_PLL_DOWN                  (BIT(7) | BIT(6))
 258         EPHYAR                  = 0x80,
 259 #define EPHYAR_FLAG                     0x80000000
 260 #define EPHYAR_WRITE_CMD                0x80000000
 261 #define EPHYAR_REG_MASK                 0x1f
 262 #define EPHYAR_REG_SHIFT                16
 263 #define EPHYAR_DATA_MASK                0xffff
 264         DLLPR                   = 0xd0,
 265 #define PFM_EN                          (1 << 6)
 266 #define TX_10M_PS_EN                    (1 << 7)
 267         DBG_REG                 = 0xd1,
 268 #define FIX_NAK_1                       (1 << 4)
 269 #define FIX_NAK_2                       (1 << 3)
 270         TWSI                    = 0xd2,
 271         MCU                     = 0xd3,
 272 #define NOW_IS_OOB                      (1 << 7)
 273 #define TX_EMPTY                        (1 << 5)
 274 #define RX_EMPTY                        (1 << 4)
 275 #define RXTX_EMPTY                      (TX_EMPTY | RX_EMPTY)
 276 #define EN_NDP                          (1 << 3)
 277 #define EN_OOB_RESET                    (1 << 2)
 278 #define LINK_LIST_RDY                   (1 << 1)
 279         EFUSEAR                 = 0xdc,
 280 #define EFUSEAR_FLAG                    0x80000000
 281 #define EFUSEAR_WRITE_CMD               0x80000000
 282 #define EFUSEAR_READ_CMD                0x00000000
 283 #define EFUSEAR_REG_MASK                0x03ff
 284 #define EFUSEAR_REG_SHIFT               8
 285 #define EFUSEAR_DATA_MASK               0xff
 286         MISC_1                  = 0xf2,
 287 #define PFM_D3COLD_EN                   (1 << 6)
 288 };
 289
 290 enum rtl8168_registers {
 291         LED_FREQ                = 0x1a,
 292         EEE_LED                 = 0x1b,
 293         ERIDR                   = 0x70,
 294         ERIAR                   = 0x74,
 295 #define ERIAR_FLAG                      0x80000000
 296 #define ERIAR_WRITE_CMD                 0x80000000
 297 #define ERIAR_READ_CMD                  0x00000000
 298 #define ERIAR_ADDR_BYTE_ALIGN           4
 299 #define ERIAR_TYPE_SHIFT                16
 300 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 301 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 302 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 303 #define ERIAR_OOB                       (0x02 << ERIAR_TYPE_SHIFT)
 304 #define ERIAR_MASK_SHIFT                12
 305 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 306 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 307 #define ERIAR_MASK_0100                 (0x4 << ERIAR_MASK_SHIFT)
 308 #define ERIAR_MASK_0101                 (0x5 << ERIAR_MASK_SHIFT)
 309 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 310         EPHY_RXER_NUM           = 0x7c,
 311         OCPDR                   = 0xb0, /* OCP GPHY access */
 312 #define OCPDR_WRITE_CMD                 0x80000000
 313 #define OCPDR_READ_CMD                  0x00000000
 314 #define OCPDR_REG_MASK                  0x7f
 315 #define OCPDR_GPHY_REG_SHIFT            16
 316 #define OCPDR_DATA_MASK                 0xffff
 317         OCPAR                   = 0xb4,
 318 #define OCPAR_FLAG                      0x80000000
 319 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 320 #define OCPAR_GPHY_READ_CMD             0x0000f060
 321         GPHY_OCP                = 0xb8,
 322         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 323         MISC                    = 0xf0, /* 8168e only. */
 324 #define TXPLA_RST                       (1 << 29)
 325 #define DISABLE_LAN_EN                  (1 << 23) /* Enable GPIO pin */
 326 #define PWM_EN                          (1 << 22)
 327 #define RXDV_GATED_EN                   (1 << 19)
 328 #define EARLY_TALLY_EN                  (1 << 16)
 329 };
 330
 331 enum rtl8125_registers {
 332         IntrMask_8125           = 0x38,
 333         IntrStatus_8125         = 0x3c,
 334         TxPoll_8125             = 0x90,
 335         MAC0_BKP                = 0x19e0,
 336         EEE_TXIDLE_TIMER_8125   = 0x6048,
 337 };
 338
 339 #define RX_VLAN_INNER_8125      BIT(22)
 340 #define RX_VLAN_OUTER_8125      BIT(23)
 341 #define RX_VLAN_8125            (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125)
 342
 343 #define RX_FETCH_DFLT_8125      (8 << 27)
 344
 345 enum rtl_register_content {
 346         /* InterruptStatusBits */
 347         SYSErr          = 0x8000,
 348         PCSTimeout      = 0x4000,
 349         SWInt           = 0x0100,
 350         TxDescUnavail   = 0x0080,
 351         RxFIFOOver      = 0x0040,
 352         LinkChg         = 0x0020,
 353         RxOverflow      = 0x0010,
 354         TxErr           = 0x0008,
 355         TxOK            = 0x0004,
 356         RxErr           = 0x0002,
 357         RxOK            = 0x0001,
 358
 359         /* RxStatusDesc */
 360         RxRWT   = (1 << 22),
 361         RxRES   = (1 << 21),
 362         RxRUNT  = (1 << 20),
 363         RxCRC   = (1 << 19),
 364
 365         /* ChipCmdBits */
 366         StopReq         = 0x80,
 367         CmdReset        = 0x10,
 368         CmdRxEnb        = 0x08,
 369         CmdTxEnb        = 0x04,
 370         RxBufEmpty      = 0x01,
 371
 372         /* TXPoll register p.5 */
 373         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 374         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 375         FSWInt          = 0x01,         /* Forced software interrupt */
 376
 377         /* Cfg9346Bits */
 378         Cfg9346_Lock    = 0x00,
 379         Cfg9346_Unlock  = 0xc0,
 380
 381         /* rx_mode_bits */
 382         AcceptErr       = 0x20,
 383         AcceptRunt      = 0x10,
 384 #define RX_CONFIG_ACCEPT_ERR_MASK       0x30
 385         AcceptBroadcast = 0x08,
 386         AcceptMulticast = 0x04,
 387         AcceptMyPhys    = 0x02,
 388         AcceptAllPhys   = 0x01,
 389 #define RX_CONFIG_ACCEPT_OK_MASK        0x0f
 390 #define RX_CONFIG_ACCEPT_MASK           0x3f
 391
 392         /* TxConfigBits */
 393         TxInterFrameGapShift = 24,
 394         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 395
 396         /* Config1 register p.24 */
 397         LEDS1           = (1 << 7),
 398         LEDS0           = (1 << 6),
 399         Speed_down      = (1 << 4),
 400         MEMMAP          = (1 << 3),
 401         IOMAP           = (1 << 2),
 402         VPD             = (1 << 1),
 403         PMEnable        = (1 << 0),     /* Power Management Enable */
 404
 405         /* Config2 register p. 25 */
 406         ClkReqEn        = (1 << 7),     /* Clock Request Enable */
 407         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
 408         PCI_Clock_66MHz = 0x01,
 409         PCI_Clock_33MHz = 0x00,
 410
 411         /* Config3 register p.25 */
 412         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 413         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 414         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
 415         Rdy_to_L23      = (1 << 1),     /* L23 Enable */
 416         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 417
 418         /* Config4 register */
 419         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
 420
 421         /* Config5 register p.27 */
 422         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 423         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 424         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 425         Spi_en          = (1 << 3),
 426         LanWake         = (1 << 1),     /* LanWake enable/disable */
 427         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 428         ASPM_en         = (1 << 0),     /* ASPM enable */
 429
 430         /* CPlusCmd p.31 */
 431         EnableBist      = (1 << 15),    // 8168 8101
 432         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 433         EnAnaPLL        = (1 << 14),    // 8169
 434         Normal_mode     = (1 << 13),    // unused
 435         Force_half_dup  = (1 << 12),    // 8168 8101
 436         Force_rxflow_en = (1 << 11),    // 8168 8101
 437         Force_txflow_en = (1 << 10),    // 8168 8101
 438         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 439         ASF             = (1 << 8),     // 8168 8101
 440         PktCntrDisable  = (1 << 7),     // 8168 8101
 441         Mac_dbgo_sel    = 0x001c,       // 8168
 442         RxVlan          = (1 << 6),
 443         RxChkSum        = (1 << 5),
 444         PCIDAC          = (1 << 4),
 445         PCIMulRW        = (1 << 3),
 446 #define INTT_MASK       GENMASK(1, 0)
 447 #define CPCMD_MASK      (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
 448
 449         /* rtl8169_PHYstatus */
 450         TBI_Enable      = 0x80,
 451         TxFlowCtrl      = 0x40,
 452         RxFlowCtrl      = 0x20,
 453         _1000bpsF       = 0x10,
 454         _100bps         = 0x08,
 455         _10bps          = 0x04,
 456         LinkStatus      = 0x02,
 457         FullDup         = 0x01,
 458
 459         /* ResetCounterCommand */
 460         CounterReset    = 0x1,
 461
 462         /* DumpCounterCommand */
 463         CounterDump     = 0x8,
 464
 465         /* magic enable v2 */
 466         MagicPacket_v2  = (1 << 16),    /* Wake up when receives a Magic Packet */
 467 };
 468
 469 enum rtl_desc_bit {
 470         /* First doubleword. */
 471         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 472         RingEnd         = (1 << 30), /* End of descriptor ring */
 473         FirstFrag       = (1 << 29), /* First segment of a packet */
 474         LastFrag        = (1 << 28), /* Final segment of a packet */
 475 };
 476
 477 /* Generic case. */
 478 enum rtl_tx_desc_bit {
 479         /* First doubleword. */
 480         TD_LSO          = (1 << 27),            /* Large Send Offload */
 481 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 482
 483         /* Second doubleword. */
 484         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 485 };
 486
 487 /* 8169, 8168b and 810x except 8102e. */
 488 enum rtl_tx_desc_bit_0 {
 489         /* First doubleword. */
 490 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 491         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 492         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 493         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 494 };
 495
 496 /* 8102e, 8168c and beyond. */
 497 enum rtl_tx_desc_bit_1 {
 498         /* First doubleword. */
 499         TD1_GTSENV4     = (1 << 26),            /* Giant Send for IPv4 */
 500         TD1_GTSENV6     = (1 << 25),            /* Giant Send for IPv6 */
 501 #define GTTCPHO_SHIFT                   18
 502 #define GTTCPHO_MAX                     0x7f
 503
 504         /* Second doubleword. */
 505 #define TCPHO_SHIFT                     18
 506 #define TCPHO_MAX                       0x3ff
 507 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 508         TD1_IPv6_CS     = (1 << 28),            /* Calculate IPv6 checksum */
 509         TD1_IPv4_CS     = (1 << 29),            /* Calculate IPv4 checksum */
 510         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 511         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 512 };
 513
 514 enum rtl_rx_desc_bit {
 515         /* Rx private */
 516         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 517         PID0            = (1 << 17), /* Protocol ID bit 0/2 */
 518
 519 #define RxProtoUDP      (PID1)
 520 #define RxProtoTCP      (PID0)
 521 #define RxProtoIP       (PID1 | PID0)
 522 #define RxProtoMask     RxProtoIP
 523
 524         IPFail          = (1 << 16), /* IP checksum failed */
 525         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 526         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 527
 528 #define RxCSFailMask    (IPFail | UDPFail | TCPFail)
 529
 530         RxVlanTag       = (1 << 16), /* VLAN tag available */
 531 };
 532
 533 #define RTL_GSO_MAX_SIZE_V1     32000
 534 #define RTL_GSO_MAX_SEGS_V1     24
 535 #define RTL_GSO_MAX_SIZE_V2     64000
 536 #define RTL_GSO_MAX_SEGS_V2     64
 537
 538 struct TxDesc {
 539         __le32 opts1;
 540         __le32 opts2;
 541         __le64 addr;
 542 };
 543
 544 struct RxDesc {
 545         __le32 opts1;
 546         __le32 opts2;
 547         __le64 addr;
 548 };
 549
 550 struct ring_info {
 551         struct sk_buff  *skb;
 552         u32             len;
 553 };
 554
 555 struct rtl8169_counters {
 556         __le64  tx_packets;
 557         __le64  rx_packets;
 558         __le64  tx_errors;
 559         __le32  rx_errors;
 560         __le16  rx_missed;
 561         __le16  align_errors;
 562         __le32  tx_one_collision;
 563         __le32  tx_multi_collision;
 564         __le64  rx_unicast;
 565         __le64  rx_broadcast;
 566         __le32  rx_multicast;
 567         __le16  tx_aborted;
 568         __le16  tx_underun;
 569 };
 570
 571 struct rtl8169_tc_offsets {
 572         bool    inited;
 573         __le64  tx_errors;
 574         __le32  tx_multi_collision;
 575         __le16  tx_aborted;
 576         __le16  rx_missed;
 577 };
 578
 579 enum rtl_flag {
 580         RTL_FLAG_TASK_ENABLED = 0,
 581         RTL_FLAG_TASK_RESET_PENDING,
 582         RTL_FLAG_TASK_TX_TIMEOUT,
 583         RTL_FLAG_MAX
 584 };
 585
 586 enum rtl_dash_type {
 587         RTL_DASH_NONE,
 588         RTL_DASH_DP,
 589         RTL_DASH_EP,
 590 };
 591
 592 struct rtl8169_private {
 593         void __iomem *mmio_addr;        /* memory map physical address */
 594         struct pci_dev *pci_dev;
 595         struct net_device *dev;
 596         struct phy_device *phydev;
 597         struct napi_struct napi;
 598         enum mac_version mac_version;
 599         enum rtl_dash_type dash_type;
 600         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 601         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 602         u32 dirty_tx;
 603         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 604         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 605         dma_addr_t TxPhyAddr;
 606         dma_addr_t RxPhyAddr;
 607         struct page *Rx_databuff[NUM_RX_DESC];  /* Rx data buffers */
 608         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 609         u16 cp_cmd;
 610         u32 irq_mask;
 611         int irq;
 612         struct clk *clk;
 613
 614         struct {
 615                 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
 616                 struct work_struct work;
 617         } wk;
 618
 619         raw_spinlock_t config25_lock;
 620         raw_spinlock_t mac_ocp_lock;
 621
 622         raw_spinlock_t cfg9346_usage_lock;
 623         int cfg9346_usage_count;
 624
 625         unsigned supports_gmii:1;
 626         unsigned aspm_manageable:1;
 627         unsigned dash_enabled:1;
 628         dma_addr_t counters_phys_addr;
 629         struct rtl8169_counters *counters;
 630         struct rtl8169_tc_offsets tc_offset;
 631         u32 saved_wolopts;
 632         int eee_adv;
 633
 634         const char *fw_name;
 635         struct rtl_fw *rtl_fw;
 636
 637         u32 ocp_base;
 638 };
 639
 640 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp);
 641
 642 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 643 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 644 MODULE_SOFTDEP("pre: realtek");
 645 MODULE_LICENSE("GPL");
 646 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 647 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 648 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 649 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 650 MODULE_FIRMWARE(FIRMWARE_8168E_3);
 651 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 652 MODULE_FIRMWARE(FIRMWARE_8168F_1);
 653 MODULE_FIRMWARE(FIRMWARE_8168F_2);
 654 MODULE_FIRMWARE(FIRMWARE_8402_1);
 655 MODULE_FIRMWARE(FIRMWARE_8411_1);
 656 MODULE_FIRMWARE(FIRMWARE_8411_2);
 657 MODULE_FIRMWARE(FIRMWARE_8106E_1);
 658 MODULE_FIRMWARE(FIRMWARE_8106E_2);
 659 MODULE_FIRMWARE(FIRMWARE_8168G_2);
 660 MODULE_FIRMWARE(FIRMWARE_8168G_3);
 661 MODULE_FIRMWARE(FIRMWARE_8168H_2);
 662 MODULE_FIRMWARE(FIRMWARE_8168FP_3);
 663 MODULE_FIRMWARE(FIRMWARE_8107E_2);
 664 MODULE_FIRMWARE(FIRMWARE_8125A_3);
 665 MODULE_FIRMWARE(FIRMWARE_8125B_2);
 666
 667 static inline struct device *tp_to_dev(struct rtl8169_private *tp)
 668 {
 669         return &tp->pci_dev->dev;
 670 }
 671
 672 static void rtl_lock_config_regs(struct rtl8169_private *tp)
 673 {
 674         unsigned long flags;
 675
 676         raw_spin_lock_irqsave(&tp->cfg9346_usage_lock, flags);
 677         if (!--tp->cfg9346_usage_count)
 678                 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
 679         raw_spin_unlock_irqrestore(&tp->cfg9346_usage_lock, flags);
 680 }
 681
 682 static void rtl_unlock_config_regs(struct rtl8169_private *tp)
 683 {
 684         unsigned long flags;
 685
 686         raw_spin_lock_irqsave(&tp->cfg9346_usage_lock, flags);
 687         if (!tp->cfg9346_usage_count++)
 688                 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
 689         raw_spin_unlock_irqrestore(&tp->cfg9346_usage_lock, flags);
 690 }
 691
 692 static void rtl_pci_commit(struct rtl8169_private *tp)
 693 {
 694         /* Read an arbitrary register to commit a preceding PCI write */
 695         RTL_R8(tp, ChipCmd);
 696 }
 697
 698 static void rtl_mod_config2(struct rtl8169_private *tp, u8 clear, u8 set)
 699 {
 700         unsigned long flags;
 701         u8 val;
 702
 703         raw_spin_lock_irqsave(&tp->config25_lock, flags);
 704         val = RTL_R8(tp, Config2);
 705         RTL_W8(tp, Config2, (val & ~clear) | set);
 706         raw_spin_unlock_irqrestore(&tp->config25_lock, flags);
 707 }
 708
 709 static void rtl_mod_config5(struct rtl8169_private *tp, u8 clear, u8 set)
 710 {
 711         unsigned long flags;
 712         u8 val;
 713
 714         raw_spin_lock_irqsave(&tp->config25_lock, flags);
 715         val = RTL_R8(tp, Config5);
 716         RTL_W8(tp, Config5, (val & ~clear) | set);
 717         raw_spin_unlock_irqrestore(&tp->config25_lock, flags);
 718 }
 719
 720 static bool rtl_is_8125(struct rtl8169_private *tp)
 721 {
 722         return tp->mac_version >= RTL_GIGA_MAC_VER_61;
 723 }
 724
 725 static bool rtl_is_8168evl_up(struct rtl8169_private *tp)
 726 {
 727         return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
 728                tp->mac_version != RTL_GIGA_MAC_VER_39 &&
 729                tp->mac_version <= RTL_GIGA_MAC_VER_53;
 730 }
 731
 732 static bool rtl_supports_eee(struct rtl8169_private *tp)
 733 {
 734         return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
 735                tp->mac_version != RTL_GIGA_MAC_VER_37 &&
 736                tp->mac_version != RTL_GIGA_MAC_VER_39;
 737 }
 738
 739 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg)
 740 {
 741         int i;
 742
 743         for (i = 0; i < ETH_ALEN; i++)
 744                 mac[i] = RTL_R8(tp, reg + i);
 745 }
 746
 747 struct rtl_cond {
 748         bool (*check)(struct rtl8169_private *);
 749         const char *msg;
 750 };
 751
 752 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
 753                           unsigned long usecs, int n, bool high)
 754 {
 755         int i;
 756
 757         for (i = 0; i < n; i++) {
 758                 if (c->check(tp) == high)
 759                         return true;
 760                 fsleep(usecs);
 761         }
 762
 763         if (net_ratelimit())
 764                 netdev_err(tp->dev, "%s == %d (loop: %d, delay: %lu).\n",
 765                            c->msg, !high, n, usecs);
 766         return false;
 767 }
 768
 769 static bool rtl_loop_wait_high(struct rtl8169_private *tp,
 770                                const struct rtl_cond *c,
 771                                unsigned long d, int n)
 772 {
 773         return rtl_loop_wait(tp, c, d, n, true);
 774 }
 775
 776 static bool rtl_loop_wait_low(struct rtl8169_private *tp,
 777                               const struct rtl_cond *c,
 778                               unsigned long d, int n)
 779 {
 780         return rtl_loop_wait(tp, c, d, n, false);
 781 }
 782
 783 #define DECLARE_RTL_COND(name)                          \
 784 static bool name ## _check(struct rtl8169_private *);   \
 785                                                         \
 786 static const struct rtl_cond name = {                   \
 787         .check  = name ## _check,                       \
 788         .msg    = #name                                 \
 789 };                                                      \
 790                                                         \
 791 static bool name ## _check(struct rtl8169_private *tp)
 792
 793 static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type)
 794 {
 795         /* based on RTL8168FP_OOBMAC_BASE in vendor driver */
 796         if (type == ERIAR_OOB &&
 797             (tp->mac_version == RTL_GIGA_MAC_VER_52 ||
 798              tp->mac_version == RTL_GIGA_MAC_VER_53))
 799                 *cmd |= 0xf70 << 18;
 800 }
 801
 802 DECLARE_RTL_COND(rtl_eriar_cond)
 803 {
 804         return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
 805 }
 806
 807 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
 808                            u32 val, int type)
 809 {
 810         u32 cmd = ERIAR_WRITE_CMD | type | mask | addr;
 811
 812         if (WARN(addr & 3 || !mask, "addr: 0x%x, mask: 0x%08x\n", addr, mask))
 813                 return;
 814
 815         RTL_W32(tp, ERIDR, val);
 816         r8168fp_adjust_ocp_cmd(tp, &cmd, type);
 817         RTL_W32(tp, ERIAR, cmd);
 818
 819         rtl_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
 820 }
 821
 822 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
 823                           u32 val)
 824 {
 825         _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC);
 826 }
 827
 828 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
 829 {
 830         u32 cmd = ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr;
 831
 832         r8168fp_adjust_ocp_cmd(tp, &cmd, type);
 833         RTL_W32(tp, ERIAR, cmd);
 834
 835         return rtl_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
 836                 RTL_R32(tp, ERIDR) : ~0;
 837 }
 838
 839 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr)
 840 {
 841         return _rtl_eri_read(tp, addr, ERIAR_EXGMAC);
 842 }
 843
 844 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 p, u32 m)
 845 {
 846         u32 val = rtl_eri_read(tp, addr);
 847
 848         rtl_eri_write(tp, addr, ERIAR_MASK_1111, (val & ~m) | p);
 849 }
 850
 851 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 p)
 852 {
 853         rtl_w0w1_eri(tp, addr, p, 0);
 854 }
 855
 856 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 m)
 857 {
 858         rtl_w0w1_eri(tp, addr, 0, m);
 859 }
 860
 861 static bool rtl_ocp_reg_failure(u32 reg)
 862 {
 863         return WARN_ONCE(reg & 0xffff0001, "Invalid ocp reg %x!\n", reg);
 864 }
 865
 866 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
 867 {
 868         return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
 869 }
 870
 871 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 872 {
 873         if (rtl_ocp_reg_failure(reg))
 874                 return;
 875
 876         RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
 877
 878         rtl_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
 879 }
 880
 881 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
 882 {
 883         if (rtl_ocp_reg_failure(reg))
 884                 return 0;
 885
 886         RTL_W32(tp, GPHY_OCP, reg << 15);
 887
 888         return rtl_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
 889                 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT;
 890 }
 891
 892 static void __r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 893 {
 894         if (rtl_ocp_reg_failure(reg))
 895                 return;
 896
 897         RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
 898 }
 899
 900 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 901 {
 902         unsigned long flags;
 903
 904         raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags);
 905         __r8168_mac_ocp_write(tp, reg, data);
 906         raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags);
 907 }
 908
 909 static u16 __r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
 910 {
 911         if (rtl_ocp_reg_failure(reg))
 912                 return 0;
 913
 914         RTL_W32(tp, OCPDR, reg << 15);
 915
 916         return RTL_R32(tp, OCPDR);
 917 }
 918
 919 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
 920 {
 921         unsigned long flags;
 922         u16 val;
 923
 924         raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags);
 925         val = __r8168_mac_ocp_read(tp, reg);
 926         raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags);
 927
 928         return val;
 929 }
 930
 931 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask,
 932                                  u16 set)
 933 {
 934         unsigned long flags;
 935         u16 data;
 936
 937         raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags);
 938         data = __r8168_mac_ocp_read(tp, reg);
 939         __r8168_mac_ocp_write(tp, reg, (data & ~mask) | set);
 940         raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags);
 941 }
 942
 943 /* Work around a hw issue with RTL8168g PHY, the quirk disables
 944  * PHY MCU interrupts before PHY power-down.
 945  */
 946 static void rtl8168g_phy_suspend_quirk(struct rtl8169_private *tp, int value)
 947 {
 948         switch (tp->mac_version) {
 949         case RTL_GIGA_MAC_VER_40:
 950                 if (value & BMCR_RESET || !(value & BMCR_PDOWN))
 951                         rtl_eri_set_bits(tp, 0x1a8, 0xfc000000);
 952                 else
 953                         rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000);
 954                 break;
 955         default:
 956                 break;
 957         }
 958 };
 959
 960 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
 961 {
 962         if (reg == 0x1f) {
 963                 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
 964                 return;
 965         }
 966
 967         if (tp->ocp_base != OCP_STD_PHY_BASE)
 968                 reg -= 0x10;
 969
 970         if (tp->ocp_base == OCP_STD_PHY_BASE && reg == MII_BMCR)
 971                 rtl8168g_phy_suspend_quirk(tp, value);
 972
 973         r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
 974 }
 975
 976 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
 977 {
 978         if (reg == 0x1f)
 979                 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4;
 980
 981         if (tp->ocp_base != OCP_STD_PHY_BASE)
 982                 reg -= 0x10;
 983
 984         return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
 985 }
 986
 987 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
 988 {
 989         if (reg == 0x1f) {
 990                 tp->ocp_base = value << 4;
 991                 return;
 992         }
 993
 994         r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
 995 }
 996
 997 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
 998 {
 999         return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
1000 }
1001
1002 DECLARE_RTL_COND(rtl_phyar_cond)
1003 {
1004         return RTL_R32(tp, PHYAR) & 0x80000000;
1005 }
1006
1007 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1008 {
1009         RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1010
1011         rtl_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
1012         /*
1013          * According to hardware specs a 20us delay is required after write
1014          * complete indication, but before sending next command.
1015          */
1016         udelay(20);
1017 }
1018
1019 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1020 {
1021         int value;
1022
1023         RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
1024
1025         value = rtl_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1026                 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT;
1027
1028         /*
1029          * According to hardware specs a 20us delay is required after read
1030          * complete indication, but before sending next command.
1031          */
1032         udelay(20);
1033
1034         return value;
1035 }
1036
1037 DECLARE_RTL_COND(rtl_ocpar_cond)
1038 {
1039         return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
1040 }
1041
1042 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
1043
1044 static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
1045 {
1046         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1047 }
1048
1049 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
1050 {
1051         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1052 }
1053
1054 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
1055 {
1056         r8168dp_2_mdio_start(tp);
1057
1058         r8169_mdio_write(tp, reg, value);
1059
1060         r8168dp_2_mdio_stop(tp);
1061 }
1062
1063 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1064 {
1065         int value;
1066
1067         /* Work around issue with chip reporting wrong PHY ID */
1068         if (reg == MII_PHYSID2)
1069                 return 0xc912;
1070
1071         r8168dp_2_mdio_start(tp);
1072
1073         value = r8169_mdio_read(tp, reg);
1074
1075         r8168dp_2_mdio_stop(tp);
1076
1077         return value;
1078 }
1079
1080 static void rtl_writephy(struct rtl8169_private *tp, int location, int val)
1081 {
1082         switch (tp->mac_version) {
1083         case RTL_GIGA_MAC_VER_28:
1084         case RTL_GIGA_MAC_VER_31:
1085                 r8168dp_2_mdio_write(tp, location, val);
1086                 break;
1087         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
1088                 r8168g_mdio_write(tp, location, val);
1089                 break;
1090         default:
1091                 r8169_mdio_write(tp, location, val);
1092                 break;
1093         }
1094 }
1095
1096 static int rtl_readphy(struct rtl8169_private *tp, int location)
1097 {
1098         switch (tp->mac_version) {
1099         case RTL_GIGA_MAC_VER_28:
1100         case RTL_GIGA_MAC_VER_31:
1101                 return r8168dp_2_mdio_read(tp, location);
1102         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
1103                 return r8168g_mdio_read(tp, location);
1104         default:
1105                 return r8169_mdio_read(tp, location);
1106         }
1107 }
1108
1109 DECLARE_RTL_COND(rtl_ephyar_cond)
1110 {
1111         return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1112 }
1113
1114 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1115 {
1116         RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1117                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1118
1119         rtl_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1120
1121         udelay(10);
1122 }
1123
1124 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1125 {
1126         RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1127
1128         return rtl_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1129                 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1130 }
1131
1132 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u16 reg)
1133 {
1134         RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff));
1135         return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1136                 RTL_R32(tp, OCPDR) : ~0;
1137 }
1138
1139 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u16 reg)
1140 {
1141         return _rtl_eri_read(tp, reg, ERIAR_OOB);
1142 }
1143
1144 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1145                               u32 data)
1146 {
1147         RTL_W32(tp, OCPDR, data);
1148         RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1149         rtl_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1150 }
1151
1152 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1153                               u32 data)
1154 {
1155         _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1156                        data, ERIAR_OOB);
1157 }
1158
1159 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd)
1160 {
1161         rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd);
1162
1163         r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001);
1164 }
1165
1166 #define OOB_CMD_RESET           0x00
1167 #define OOB_CMD_DRIVER_START    0x05
1168 #define OOB_CMD_DRIVER_STOP     0x06
1169
1170 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1171 {
1172         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1173 }
1174
1175 DECLARE_RTL_COND(rtl_dp_ocp_read_cond)
1176 {
1177         u16 reg;
1178
1179         reg = rtl8168_get_ocp_reg(tp);
1180
1181         return r8168dp_ocp_read(tp, reg) & 0x00000800;
1182 }
1183
1184 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1185 {
1186         return r8168ep_ocp_read(tp, 0x124) & 0x00000001;
1187 }
1188
1189 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1190 {
1191         return RTL_R8(tp, IBISR0) & 0x20;
1192 }
1193
1194 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1195 {
1196         RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1197         rtl_loop_wait_high(tp, &rtl_ocp_tx_cond, 50000, 2000);
1198         RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1199         RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1200 }
1201
1202 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1203 {
1204         r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START);
1205         rtl_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10000, 10);
1206 }
1207
1208 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1209 {
1210         r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1211         r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01);
1212         rtl_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10000, 10);
1213 }
1214
1215 static void rtl8168_driver_start(struct rtl8169_private *tp)
1216 {
1217         if (tp->dash_type == RTL_DASH_DP)
1218                 rtl8168dp_driver_start(tp);
1219         else
1220                 rtl8168ep_driver_start(tp);
1221 }
1222
1223 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1224 {
1225         r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1226         rtl_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10000, 10);
1227 }
1228
1229 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1230 {
1231         rtl8168ep_stop_cmac(tp);
1232         r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1233         r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01);
1234         rtl_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10000, 10);
1235 }
1236
1237 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1238 {
1239         if (tp->dash_type == RTL_DASH_DP)
1240                 rtl8168dp_driver_stop(tp);
1241         else
1242                 rtl8168ep_driver_stop(tp);
1243 }
1244
1245 static bool r8168dp_check_dash(struct rtl8169_private *tp)
1246 {
1247         u16 reg = rtl8168_get_ocp_reg(tp);
1248
1249         return r8168dp_ocp_read(tp, reg) & BIT(15);
1250 }
1251
1252 static bool r8168ep_check_dash(struct rtl8169_private *tp)
1253 {
1254         return r8168ep_ocp_read(tp, 0x128) & BIT(0);
1255 }
1256
1257 static bool rtl_dash_is_enabled(struct rtl8169_private *tp)
1258 {
1259         switch (tp->dash_type) {
1260         case RTL_DASH_DP:
1261                 return r8168dp_check_dash(tp);
1262         case RTL_DASH_EP:
1263                 return r8168ep_check_dash(tp);
1264         default:
1265                 return false;
1266         }
1267 }
1268
1269 static enum rtl_dash_type rtl_get_dash_type(struct rtl8169_private *tp)
1270 {
1271         switch (tp->mac_version) {
1272         case RTL_GIGA_MAC_VER_28:
1273         case RTL_GIGA_MAC_VER_31:
1274                 return RTL_DASH_DP;
1275         case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_53:
1276                 return RTL_DASH_EP;
1277         default:
1278                 return RTL_DASH_NONE;
1279         }
1280 }
1281
1282 static void rtl_set_d3_pll_down(struct rtl8169_private *tp, bool enable)
1283 {
1284         switch (tp->mac_version) {
1285         case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_26:
1286         case RTL_GIGA_MAC_VER_29 ... RTL_GIGA_MAC_VER_30:
1287         case RTL_GIGA_MAC_VER_32 ... RTL_GIGA_MAC_VER_37:
1288         case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63:
1289                 if (enable)
1290                         RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~D3_NO_PLL_DOWN);
1291                 else
1292                         RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | D3_NO_PLL_DOWN);
1293                 break;
1294         default:
1295                 break;
1296         }
1297 }
1298
1299 static void rtl_reset_packet_filter(struct rtl8169_private *tp)
1300 {
1301         rtl_eri_clear_bits(tp, 0xdc, BIT(0));
1302         rtl_eri_set_bits(tp, 0xdc, BIT(0));
1303 }
1304
1305 DECLARE_RTL_COND(rtl_efusear_cond)
1306 {
1307         return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1308 }
1309
1310 u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1311 {
1312         RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1313
1314         return rtl_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1315                 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1316 }
1317
1318 static u32 rtl_get_events(struct rtl8169_private *tp)
1319 {
1320         if (rtl_is_8125(tp))
1321                 return RTL_R32(tp, IntrStatus_8125);
1322         else
1323                 return RTL_R16(tp, IntrStatus);
1324 }
1325
1326 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits)
1327 {
1328         if (rtl_is_8125(tp))
1329                 RTL_W32(tp, IntrStatus_8125, bits);
1330         else
1331                 RTL_W16(tp, IntrStatus, bits);
1332 }
1333
1334 static void rtl_irq_disable(struct rtl8169_private *tp)
1335 {
1336         if (rtl_is_8125(tp))
1337                 RTL_W32(tp, IntrMask_8125, 0);
1338         else
1339                 RTL_W16(tp, IntrMask, 0);
1340 }
1341
1342 static void rtl_irq_enable(struct rtl8169_private *tp)
1343 {
1344         if (rtl_is_8125(tp))
1345                 RTL_W32(tp, IntrMask_8125, tp->irq_mask);
1346         else
1347                 RTL_W16(tp, IntrMask, tp->irq_mask);
1348 }
1349
1350 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1351 {
1352         rtl_irq_disable(tp);
1353         rtl_ack_events(tp, 0xffffffff);
1354         rtl_pci_commit(tp);
1355 }
1356
1357 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1358 {
1359         struct phy_device *phydev = tp->phydev;
1360
1361         if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1362             tp->mac_version == RTL_GIGA_MAC_VER_38) {
1363                 if (phydev->speed == SPEED_1000) {
1364                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1365                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1366                 } else if (phydev->speed == SPEED_100) {
1367                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1368                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1369                 } else {
1370                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1371                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1372                 }
1373                 rtl_reset_packet_filter(tp);
1374         } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1375                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
1376                 if (phydev->speed == SPEED_1000) {
1377                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1378                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1379                 } else {
1380                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1381                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1382                 }
1383         } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1384                 if (phydev->speed == SPEED_10) {
1385                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02);
1386                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a);
1387                 } else {
1388                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
1389                 }
1390         }
1391 }
1392
1393 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1394
1395 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1396 {
1397         struct rtl8169_private *tp = netdev_priv(dev);
1398
1399         wol->supported = WAKE_ANY;
1400         wol->wolopts = tp->saved_wolopts;
1401 }
1402
1403 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1404 {
1405         static const struct {
1406                 u32 opt;
1407                 u16 reg;
1408                 u8  mask;
1409         } cfg[] = {
1410                 { WAKE_PHY,   Config3, LinkUp },
1411                 { WAKE_UCAST, Config5, UWF },
1412                 { WAKE_BCAST, Config5, BWF },
1413                 { WAKE_MCAST, Config5, MWF },
1414                 { WAKE_ANY,   Config5, LanWake },
1415                 { WAKE_MAGIC, Config3, MagicPacket }
1416         };
1417         unsigned int i, tmp = ARRAY_SIZE(cfg);
1418         unsigned long flags;
1419         u8 options;
1420
1421         rtl_unlock_config_regs(tp);
1422
1423         if (rtl_is_8168evl_up(tp)) {
1424                 tmp--;
1425                 if (wolopts & WAKE_MAGIC)
1426                         rtl_eri_set_bits(tp, 0x0dc, MagicPacket_v2);
1427                 else
1428                         rtl_eri_clear_bits(tp, 0x0dc, MagicPacket_v2);
1429         } else if (rtl_is_8125(tp)) {
1430                 tmp--;
1431                 if (wolopts & WAKE_MAGIC)
1432                         r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0));
1433                 else
1434                         r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0);
1435         }
1436
1437         raw_spin_lock_irqsave(&tp->config25_lock, flags);
1438         for (i = 0; i < tmp; i++) {
1439                 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
1440                 if (wolopts & cfg[i].opt)
1441                         options |= cfg[i].mask;
1442                 RTL_W8(tp, cfg[i].reg, options);
1443         }
1444         raw_spin_unlock_irqrestore(&tp->config25_lock, flags);
1445
1446         switch (tp->mac_version) {
1447         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
1448                 options = RTL_R8(tp, Config1) & ~PMEnable;
1449                 if (wolopts)
1450                         options |= PMEnable;
1451                 RTL_W8(tp, Config1, options);
1452                 break;
1453         case RTL_GIGA_MAC_VER_34:
1454         case RTL_GIGA_MAC_VER_37:
1455         case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63:
1456                 if (wolopts)
1457                         rtl_mod_config2(tp, 0, PME_SIGNAL);
1458                 else
1459                         rtl_mod_config2(tp, PME_SIGNAL, 0);
1460                 break;
1461         default:
1462                 break;
1463         }
1464
1465         rtl_lock_config_regs(tp);
1466
1467         device_set_wakeup_enable(tp_to_dev(tp), wolopts);
1468
1469         if (!tp->dash_enabled) {
1470                 rtl_set_d3_pll_down(tp, !wolopts);
1471                 tp->dev->wol_enabled = wolopts ? 1 : 0;
1472         }
1473 }
1474
1475 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1476 {
1477         struct rtl8169_private *tp = netdev_priv(dev);
1478
1479         if (wol->wolopts & ~WAKE_ANY)
1480                 return -EINVAL;
1481
1482         tp->saved_wolopts = wol->wolopts;
1483         __rtl8169_set_wol(tp, tp->saved_wolopts);
1484
1485         return 0;
1486 }
1487
1488 static void rtl8169_get_drvinfo(struct net_device *dev,
1489                                 struct ethtool_drvinfo *info)
1490 {
1491         struct rtl8169_private *tp = netdev_priv(dev);
1492         struct rtl_fw *rtl_fw = tp->rtl_fw;
1493
1494         strscpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
1495         strscpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1496         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1497         if (rtl_fw)
1498                 strscpy(info->fw_version, rtl_fw->version,
1499                         sizeof(info->fw_version));
1500 }
1501
1502 static int rtl8169_get_regs_len(struct net_device *dev)
1503 {
1504         return R8169_REGS_SIZE;
1505 }
1506
1507 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1508         netdev_features_t features)
1509 {
1510         struct rtl8169_private *tp = netdev_priv(dev);
1511
1512         if (dev->mtu > TD_MSS_MAX)
1513                 features &= ~NETIF_F_ALL_TSO;
1514
1515         if (dev->mtu > ETH_DATA_LEN &&
1516             tp->mac_version > RTL_GIGA_MAC_VER_06)
1517                 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_ALL_TSO);
1518
1519         return features;
1520 }
1521
1522 static void rtl_set_rx_config_features(struct rtl8169_private *tp,
1523                                        netdev_features_t features)
1524 {
1525         u32 rx_config = RTL_R32(tp, RxConfig);
1526
1527         if (features & NETIF_F_RXALL)
1528                 rx_config |= RX_CONFIG_ACCEPT_ERR_MASK;
1529         else
1530                 rx_config &= ~RX_CONFIG_ACCEPT_ERR_MASK;
1531
1532         if (rtl_is_8125(tp)) {
1533                 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1534                         rx_config |= RX_VLAN_8125;
1535                 else
1536                         rx_config &= ~RX_VLAN_8125;
1537         }
1538
1539         RTL_W32(tp, RxConfig, rx_config);
1540 }
1541
1542 static int rtl8169_set_features(struct net_device *dev,
1543                                 netdev_features_t features)
1544 {
1545         struct rtl8169_private *tp = netdev_priv(dev);
1546
1547         rtl_set_rx_config_features(tp, features);
1548
1549         if (features & NETIF_F_RXCSUM)
1550                 tp->cp_cmd |= RxChkSum;
1551         else
1552                 tp->cp_cmd &= ~RxChkSum;
1553
1554         if (!rtl_is_8125(tp)) {
1555                 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1556                         tp->cp_cmd |= RxVlan;
1557                 else
1558                         tp->cp_cmd &= ~RxVlan;
1559         }
1560
1561         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1562         rtl_pci_commit(tp);
1563
1564         return 0;
1565 }
1566
1567 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1568 {
1569         return (skb_vlan_tag_present(skb)) ?
1570                 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1571 }
1572
1573 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1574 {
1575         u32 opts2 = le32_to_cpu(desc->opts2);
1576
1577         if (opts2 & RxVlanTag)
1578                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1579 }
1580
1581 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1582                              void *p)
1583 {
1584         struct rtl8169_private *tp = netdev_priv(dev);
1585         u32 __iomem *data = tp->mmio_addr;
1586         u32 *dw = p;
1587         int i;
1588
1589         for (i = 0; i < R8169_REGS_SIZE; i += 4)
1590                 memcpy_fromio(dw++, data++, 4);
1591 }
1592
1593 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1594         "tx_packets",
1595         "rx_packets",
1596         "tx_errors",
1597         "rx_errors",
1598         "rx_missed",
1599         "align_errors",
1600         "tx_single_collisions",
1601         "tx_multi_collisions",
1602         "unicast",
1603         "broadcast",
1604         "multicast",
1605         "tx_aborted",
1606         "tx_underrun",
1607 };
1608
1609 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1610 {
1611         switch (sset) {
1612         case ETH_SS_STATS:
1613                 return ARRAY_SIZE(rtl8169_gstrings);
1614         default:
1615                 return -EOPNOTSUPP;
1616         }
1617 }
1618
1619 DECLARE_RTL_COND(rtl_counters_cond)
1620 {
1621         return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
1622 }
1623
1624 static void rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
1625 {
1626         u32 cmd = lower_32_bits(tp->counters_phys_addr);
1627
1628         RTL_W32(tp, CounterAddrHigh, upper_32_bits(tp->counters_phys_addr));
1629         rtl_pci_commit(tp);
1630         RTL_W32(tp, CounterAddrLow, cmd);
1631         RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
1632
1633         rtl_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
1634 }
1635
1636 static void rtl8169_update_counters(struct rtl8169_private *tp)
1637 {
1638         u8 val = RTL_R8(tp, ChipCmd);
1639
1640         /*
1641          * Some chips are unable to dump tally counters when the receiver
1642          * is disabled. If 0xff chip may be in a PCI power-save state.
1643          */
1644         if (val & CmdRxEnb && val != 0xff)
1645                 rtl8169_do_counters(tp, CounterDump);
1646 }
1647
1648 static void rtl8169_init_counter_offsets(struct rtl8169_private *tp)
1649 {
1650         struct rtl8169_counters *counters = tp->counters;
1651
1652         /*
1653          * rtl8169_init_counter_offsets is called from rtl_open.  On chip
1654          * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1655          * reset by a power cycle, while the counter values collected by the
1656          * driver are reset at every driver unload/load cycle.
1657          *
1658          * To make sure the HW values returned by @get_stats64 match the SW
1659          * values, we collect the initial values at first open(*) and use them
1660          * as offsets to normalize the values returned by @get_stats64.
1661          *
1662          * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1663          * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1664          * set at open time by rtl_hw_start.
1665          */
1666
1667         if (tp->tc_offset.inited)
1668                 return;
1669
1670         if (tp->mac_version >= RTL_GIGA_MAC_VER_19) {
1671                 rtl8169_do_counters(tp, CounterReset);
1672         } else {
1673                 rtl8169_update_counters(tp);
1674                 tp->tc_offset.tx_errors = counters->tx_errors;
1675                 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1676                 tp->tc_offset.tx_aborted = counters->tx_aborted;
1677                 tp->tc_offset.rx_missed = counters->rx_missed;
1678         }
1679
1680         tp->tc_offset.inited = true;
1681 }
1682
1683 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1684                                       struct ethtool_stats *stats, u64 *data)
1685 {
1686         struct rtl8169_private *tp = netdev_priv(dev);
1687         struct rtl8169_counters *counters;
1688
1689         counters = tp->counters;
1690         rtl8169_update_counters(tp);
1691
1692         data[0] = le64_to_cpu(counters->tx_packets);
1693         data[1] = le64_to_cpu(counters->rx_packets);
1694         data[2] = le64_to_cpu(counters->tx_errors);
1695         data[3] = le32_to_cpu(counters->rx_errors);
1696         data[4] = le16_to_cpu(counters->rx_missed);
1697         data[5] = le16_to_cpu(counters->align_errors);
1698         data[6] = le32_to_cpu(counters->tx_one_collision);
1699         data[7] = le32_to_cpu(counters->tx_multi_collision);
1700         data[8] = le64_to_cpu(counters->rx_unicast);
1701         data[9] = le64_to_cpu(counters->rx_broadcast);
1702         data[10] = le32_to_cpu(counters->rx_multicast);
1703         data[11] = le16_to_cpu(counters->tx_aborted);
1704         data[12] = le16_to_cpu(counters->tx_underun);
1705 }
1706
1707 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1708 {
1709         switch(stringset) {
1710         case ETH_SS_STATS:
1711                 memcpy(data, rtl8169_gstrings, sizeof(rtl8169_gstrings));
1712                 break;
1713         }
1714 }
1715
1716 /*
1717  * Interrupt coalescing
1718  *
1719  * > 1 - the availability of the IntrMitigate (0xe2) register through the
1720  * >     8169, 8168 and 810x line of chipsets
1721  *
1722  * 8169, 8168, and 8136(810x) serial chipsets support it.
1723  *
1724  * > 2 - the Tx timer unit at gigabit speed
1725  *
1726  * The unit of the timer depends on both the speed and the setting of CPlusCmd
1727  * (0xe0) bit 1 and bit 0.
1728  *
1729  * For 8169
1730  * bit[1:0] \ speed        1000M           100M            10M
1731  * 0 0                     320ns           2.56us          40.96us
1732  * 0 1                     2.56us          20.48us         327.7us
1733  * 1 0                     5.12us          40.96us         655.4us
1734  * 1 1                     10.24us         81.92us         1.31ms
1735  *
1736  * For the other
1737  * bit[1:0] \ speed        1000M           100M            10M
1738  * 0 0                     5us             2.56us          40.96us
1739  * 0 1                     40us            20.48us         327.7us
1740  * 1 0                     80us            40.96us         655.4us
1741  * 1 1                     160us           81.92us         1.31ms
1742  */
1743
1744 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
1745 struct rtl_coalesce_info {
1746         u32 speed;
1747         u32 scale_nsecs[4];
1748 };
1749
1750 /* produce array with base delay *1, *8, *8*2, *8*2*2 */
1751 #define COALESCE_DELAY(d) { (d), 8 * (d), 16 * (d), 32 * (d) }
1752
1753 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1754         { SPEED_1000,   COALESCE_DELAY(320) },
1755         { SPEED_100,    COALESCE_DELAY(2560) },
1756         { SPEED_10,     COALESCE_DELAY(40960) },
1757         { 0 },
1758 };
1759
1760 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1761         { SPEED_1000,   COALESCE_DELAY(5000) },
1762         { SPEED_100,    COALESCE_DELAY(2560) },
1763         { SPEED_10,     COALESCE_DELAY(40960) },
1764         { 0 },
1765 };
1766 #undef COALESCE_DELAY
1767
1768 /* get rx/tx scale vector corresponding to current speed */
1769 static const struct rtl_coalesce_info *
1770 rtl_coalesce_info(struct rtl8169_private *tp)
1771 {
1772         const struct rtl_coalesce_info *ci;
1773
1774         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1775                 ci = rtl_coalesce_info_8169;
1776         else
1777                 ci = rtl_coalesce_info_8168_8136;
1778
1779         /* if speed is unknown assume highest one */
1780         if (tp->phydev->speed == SPEED_UNKNOWN)
1781                 return ci;
1782
1783         for (; ci->speed; ci++) {
1784                 if (tp->phydev->speed == ci->speed)
1785                         return ci;
1786         }
1787
1788         return ERR_PTR(-ELNRNG);
1789 }
1790
1791 static int rtl_get_coalesce(struct net_device *dev,
1792                             struct ethtool_coalesce *ec,
1793                             struct kernel_ethtool_coalesce *kernel_coal,
1794                             struct netlink_ext_ack *extack)
1795 {
1796         struct rtl8169_private *tp = netdev_priv(dev);
1797         const struct rtl_coalesce_info *ci;
1798         u32 scale, c_us, c_fr;
1799         u16 intrmit;
1800
1801         if (rtl_is_8125(tp))
1802                 return -EOPNOTSUPP;
1803
1804         memset(ec, 0, sizeof(*ec));
1805
1806         /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1807         ci = rtl_coalesce_info(tp);
1808         if (IS_ERR(ci))
1809                 return PTR_ERR(ci);
1810
1811         scale = ci->scale_nsecs[tp->cp_cmd & INTT_MASK];
1812
1813         intrmit = RTL_R16(tp, IntrMitigate);
1814
1815         c_us = FIELD_GET(RTL_COALESCE_TX_USECS, intrmit);
1816         ec->tx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000);
1817
1818         c_fr = FIELD_GET(RTL_COALESCE_TX_FRAMES, intrmit);
1819         /* ethtool_coalesce states usecs and max_frames must not both be 0 */
1820         ec->tx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1;
1821
1822         c_us = FIELD_GET(RTL_COALESCE_RX_USECS, intrmit);
1823         ec->rx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000);
1824
1825         c_fr = FIELD_GET(RTL_COALESCE_RX_FRAMES, intrmit);
1826         ec->rx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1;
1827
1828         return 0;
1829 }
1830
1831 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, usec) */
1832 static int rtl_coalesce_choose_scale(struct rtl8169_private *tp, u32 usec,
1833                                      u16 *cp01)
1834 {
1835         const struct rtl_coalesce_info *ci;
1836         u16 i;
1837
1838         ci = rtl_coalesce_info(tp);
1839         if (IS_ERR(ci))
1840                 return PTR_ERR(ci);
1841
1842         for (i = 0; i < 4; i++) {
1843                 if (usec <= ci->scale_nsecs[i] * RTL_COALESCE_T_MAX / 1000U) {
1844                         *cp01 = i;
1845                         return ci->scale_nsecs[i];
1846                 }
1847         }
1848
1849         return -ERANGE;
1850 }
1851
1852 static int rtl_set_coalesce(struct net_device *dev,
1853                             struct ethtool_coalesce *ec,
1854                             struct kernel_ethtool_coalesce *kernel_coal,
1855                             struct netlink_ext_ack *extack)
1856 {
1857         struct rtl8169_private *tp = netdev_priv(dev);
1858         u32 tx_fr = ec->tx_max_coalesced_frames;
1859         u32 rx_fr = ec->rx_max_coalesced_frames;
1860         u32 coal_usec_max, units;
1861         u16 w = 0, cp01 = 0;
1862         int scale;
1863
1864         if (rtl_is_8125(tp))
1865                 return -EOPNOTSUPP;
1866
1867         if (rx_fr > RTL_COALESCE_FRAME_MAX || tx_fr > RTL_COALESCE_FRAME_MAX)
1868                 return -ERANGE;
1869
1870         coal_usec_max = max(ec->rx_coalesce_usecs, ec->tx_coalesce_usecs);
1871         scale = rtl_coalesce_choose_scale(tp, coal_usec_max, &cp01);
1872         if (scale < 0)
1873                 return scale;
1874
1875         /* Accept max_frames=1 we returned in rtl_get_coalesce. Accept it
1876          * not only when usecs=0 because of e.g. the following scenario:
1877          *
1878          * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
1879          * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
1880          * - then user does `ethtool -C eth0 rx-usecs 100`
1881          *
1882          * Since ethtool sends to kernel whole ethtool_coalesce settings,
1883          * if we want to ignore rx_frames then it has to be set to 0.
1884          */
1885         if (rx_fr == 1)
1886                 rx_fr = 0;
1887         if (tx_fr == 1)
1888                 tx_fr = 0;
1889
1890         /* HW requires time limit to be set if frame limit is set */
1891         if ((tx_fr && !ec->tx_coalesce_usecs) ||
1892             (rx_fr && !ec->rx_coalesce_usecs))
1893                 return -EINVAL;
1894
1895         w |= FIELD_PREP(RTL_COALESCE_TX_FRAMES, DIV_ROUND_UP(tx_fr, 4));
1896         w |= FIELD_PREP(RTL_COALESCE_RX_FRAMES, DIV_ROUND_UP(rx_fr, 4));
1897
1898         units = DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000U, scale);
1899         w |= FIELD_PREP(RTL_COALESCE_TX_USECS, units);
1900         units = DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000U, scale);
1901         w |= FIELD_PREP(RTL_COALESCE_RX_USECS, units);
1902
1903         RTL_W16(tp, IntrMitigate, w);
1904
1905         /* Meaning of PktCntrDisable bit changed from RTL8168e-vl */
1906         if (rtl_is_8168evl_up(tp)) {
1907                 if (!rx_fr && !tx_fr)
1908                         /* disable packet counter */
1909                         tp->cp_cmd |= PktCntrDisable;
1910                 else
1911                         tp->cp_cmd &= ~PktCntrDisable;
1912         }
1913
1914         tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
1915         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1916         rtl_pci_commit(tp);
1917
1918         return 0;
1919 }
1920
1921 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data)
1922 {
1923         struct rtl8169_private *tp = netdev_priv(dev);
1924
1925         if (!rtl_supports_eee(tp))
1926                 return -EOPNOTSUPP;
1927
1928         return phy_ethtool_get_eee(tp->phydev, data);
1929 }
1930
1931 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data)
1932 {
1933         struct rtl8169_private *tp = netdev_priv(dev);
1934         int ret;
1935
1936         if (!rtl_supports_eee(tp))
1937                 return -EOPNOTSUPP;
1938
1939         ret = phy_ethtool_set_eee(tp->phydev, data);
1940
1941         if (!ret)
1942                 tp->eee_adv = phy_read_mmd(dev->phydev, MDIO_MMD_AN,
1943                                            MDIO_AN_EEE_ADV);
1944         return ret;
1945 }
1946
1947 static void rtl8169_get_ringparam(struct net_device *dev,
1948                                   struct ethtool_ringparam *data,
1949                                   struct kernel_ethtool_ringparam *kernel_data,
1950                                   struct netlink_ext_ack *extack)
1951 {
1952         data->rx_max_pending = NUM_RX_DESC;
1953         data->rx_pending = NUM_RX_DESC;
1954         data->tx_max_pending = NUM_TX_DESC;
1955         data->tx_pending = NUM_TX_DESC;
1956 }
1957
1958 static void rtl8169_get_pauseparam(struct net_device *dev,
1959                                    struct ethtool_pauseparam *data)
1960 {
1961         struct rtl8169_private *tp = netdev_priv(dev);
1962         bool tx_pause, rx_pause;
1963
1964         phy_get_pause(tp->phydev, &tx_pause, &rx_pause);
1965
1966         data->autoneg = tp->phydev->autoneg;
1967         data->tx_pause = tx_pause ? 1 : 0;
1968         data->rx_pause = rx_pause ? 1 : 0;
1969 }
1970
1971 static int rtl8169_set_pauseparam(struct net_device *dev,
1972                                   struct ethtool_pauseparam *data)
1973 {
1974         struct rtl8169_private *tp = netdev_priv(dev);
1975
1976         if (dev->mtu > ETH_DATA_LEN)
1977                 return -EOPNOTSUPP;
1978
1979         phy_set_asym_pause(tp->phydev, data->rx_pause, data->tx_pause);
1980
1981         return 0;
1982 }
1983
1984 static const struct ethtool_ops rtl8169_ethtool_ops = {
1985         .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
1986                                      ETHTOOL_COALESCE_MAX_FRAMES,
1987         .get_drvinfo            = rtl8169_get_drvinfo,
1988         .get_regs_len           = rtl8169_get_regs_len,
1989         .get_link               = ethtool_op_get_link,
1990         .get_coalesce           = rtl_get_coalesce,
1991         .set_coalesce           = rtl_set_coalesce,
1992         .get_regs               = rtl8169_get_regs,
1993         .get_wol                = rtl8169_get_wol,
1994         .set_wol                = rtl8169_set_wol,
1995         .get_strings            = rtl8169_get_strings,
1996         .get_sset_count         = rtl8169_get_sset_count,
1997         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
1998         .get_ts_info            = ethtool_op_get_ts_info,
1999         .nway_reset             = phy_ethtool_nway_reset,
2000         .get_eee                = rtl8169_get_eee,
2001         .set_eee                = rtl8169_set_eee,
2002         .get_link_ksettings     = phy_ethtool_get_link_ksettings,
2003         .set_link_ksettings     = phy_ethtool_set_link_ksettings,
2004         .get_ringparam          = rtl8169_get_ringparam,
2005         .get_pauseparam         = rtl8169_get_pauseparam,
2006         .set_pauseparam         = rtl8169_set_pauseparam,
2007 };
2008
2009 static void rtl_enable_eee(struct rtl8169_private *tp)
2010 {
2011         struct phy_device *phydev = tp->phydev;
2012         int adv;
2013
2014         /* respect EEE advertisement the user may have set */
2015         if (tp->eee_adv >= 0)
2016                 adv = tp->eee_adv;
2017         else
2018                 adv = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
2019
2020         if (adv >= 0)
2021                 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, adv);
2022 }
2023
2024 static enum mac_version rtl8169_get_mac_version(u16 xid, bool gmii)
2025 {
2026         /*
2027          * The driver currently handles the 8168Bf and the 8168Be identically
2028          * but they can be identified more specifically through the test below
2029          * if needed:
2030          *
2031          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2032          *
2033          * Same thing for the 8101Eb and the 8101Ec:
2034          *
2035          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2036          */
2037         static const struct rtl_mac_info {
2038                 u16 mask;
2039                 u16 val;
2040                 enum mac_version ver;
2041         } mac_info[] = {
2042                 /* 8125B family. */
2043                 { 0x7cf, 0x641, RTL_GIGA_MAC_VER_63 },
2044
2045                 /* 8125A family. */
2046                 { 0x7cf, 0x609, RTL_GIGA_MAC_VER_61 },
2047                 /* It seems only XID 609 made it to the mass market.
2048                  * { 0x7cf, 0x608,      RTL_GIGA_MAC_VER_60 },
2049                  * { 0x7c8, 0x608,      RTL_GIGA_MAC_VER_61 },
2050                  */
2051
2052                 /* RTL8117 */
2053                 { 0x7cf, 0x54b, RTL_GIGA_MAC_VER_53 },
2054                 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52 },
2055
2056                 /* 8168EP family. */
2057                 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 },
2058                 /* It seems this chip version never made it to
2059                  * the wild. Let's disable detection.
2060                  * { 0x7cf, 0x501,      RTL_GIGA_MAC_VER_50 },
2061                  * { 0x7cf, 0x500,      RTL_GIGA_MAC_VER_49 },
2062                  */
2063
2064                 /* 8168H family. */
2065                 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 },
2066                 /* It seems this chip version never made it to
2067                  * the wild. Let's disable detection.
2068                  * { 0x7cf, 0x540,      RTL_GIGA_MAC_VER_45 },
2069                  */
2070
2071                 /* 8168G family. */
2072                 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 },
2073                 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 },
2074                 /* It seems this chip version never made it to
2075                  * the wild. Let's disable detection.
2076                  * { 0x7cf, 0x4c1,      RTL_GIGA_MAC_VER_41 },
2077                  */
2078                 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 },
2079
2080                 /* 8168F family. */
2081                 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 },
2082                 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 },
2083                 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 },
2084
2085                 /* 8168E family. */
2086                 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 },
2087                 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 },
2088                 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 },
2089
2090                 /* 8168D family. */
2091                 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 },
2092                 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 },
2093
2094                 /* 8168DP family. */
2095                 /* It seems this early RTL8168dp version never made it to
2096                  * the wild. Support has been removed.
2097                  * { 0x7cf, 0x288,      RTL_GIGA_MAC_VER_27 },
2098                  */
2099                 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 },
2100                 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 },
2101
2102                 /* 8168C family. */
2103                 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 },
2104                 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 },
2105                 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 },
2106                 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 },
2107                 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 },
2108                 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 },
2109                 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 },
2110
2111                 /* 8168B family. */
2112                 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 },
2113                 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 },
2114
2115                 /* 8101 family. */
2116                 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 },
2117                 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 },
2118                 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 },
2119                 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 },
2120                 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 },
2121                 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 },
2122                 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 },
2123                 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 },
2124                 { 0x7cf, 0x240, RTL_GIGA_MAC_VER_14 },
2125                 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 },
2126                 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 },
2127                 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_10 },
2128
2129                 /* 8110 family. */
2130                 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 },
2131                 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 },
2132                 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 },
2133                 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 },
2134                 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 },
2135
2136                 /* Catch-all */
2137                 { 0x000, 0x000, RTL_GIGA_MAC_NONE   }
2138         };
2139         const struct rtl_mac_info *p = mac_info;
2140         enum mac_version ver;
2141
2142         while ((xid & p->mask) != p->val)
2143                 p++;
2144         ver = p->ver;
2145
2146         if (ver != RTL_GIGA_MAC_NONE && !gmii) {
2147                 if (ver == RTL_GIGA_MAC_VER_42)
2148                         ver = RTL_GIGA_MAC_VER_43;
2149                 else if (ver == RTL_GIGA_MAC_VER_46)
2150                         ver = RTL_GIGA_MAC_VER_48;
2151         }
2152
2153         return ver;
2154 }
2155
2156 static void rtl_release_firmware(struct rtl8169_private *tp)
2157 {
2158         if (tp->rtl_fw) {
2159                 rtl_fw_release_firmware(tp->rtl_fw);
2160                 kfree(tp->rtl_fw);
2161                 tp->rtl_fw = NULL;
2162         }
2163 }
2164
2165 void r8169_apply_firmware(struct rtl8169_private *tp)
2166 {
2167         int val;
2168
2169         /* TODO: release firmware if rtl_fw_write_firmware signals failure. */
2170         if (tp->rtl_fw) {
2171                 rtl_fw_write_firmware(tp, tp->rtl_fw);
2172                 /* At least one firmware doesn't reset tp->ocp_base. */
2173                 tp->ocp_base = OCP_STD_PHY_BASE;
2174
2175                 /* PHY soft reset may still be in progress */
2176                 phy_read_poll_timeout(tp->phydev, MII_BMCR, val,
2177                                       !(val & BMCR_RESET),
2178                                       50000, 600000, true);
2179         }
2180 }
2181
2182 static void rtl8168_config_eee_mac(struct rtl8169_private *tp)
2183 {
2184         /* Adjust EEE LED frequency */
2185         if (tp->mac_version != RTL_GIGA_MAC_VER_38)
2186                 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
2187
2188         rtl_eri_set_bits(tp, 0x1b0, 0x0003);
2189 }
2190
2191 static void rtl8125a_config_eee_mac(struct rtl8169_private *tp)
2192 {
2193         r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0));
2194         r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1));
2195 }
2196
2197 static void rtl8125_set_eee_txidle_timer(struct rtl8169_private *tp)
2198 {
2199         RTL_W16(tp, EEE_TXIDLE_TIMER_8125, tp->dev->mtu + ETH_HLEN + 0x20);
2200 }
2201
2202 static void rtl8125b_config_eee_mac(struct rtl8169_private *tp)
2203 {
2204         rtl8125_set_eee_txidle_timer(tp);
2205         r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0));
2206 }
2207
2208 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, const u8 *addr)
2209 {
2210         rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, get_unaligned_le32(addr));
2211         rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, get_unaligned_le16(addr + 4));
2212         rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, get_unaligned_le16(addr) << 16);
2213         rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, get_unaligned_le32(addr + 2));
2214 }
2215
2216 u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp)
2217 {
2218         u16 data1, data2, ioffset;
2219
2220         r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
2221         data1 = r8168_mac_ocp_read(tp, 0xdd02);
2222         data2 = r8168_mac_ocp_read(tp, 0xdd00);
2223
2224         ioffset = (data2 >> 1) & 0x7ff8;
2225         ioffset |= data2 & 0x0007;
2226         if (data1 & BIT(7))
2227                 ioffset |= BIT(15);
2228
2229         return ioffset;
2230 }
2231
2232 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
2233 {
2234         set_bit(flag, tp->wk.flags);
2235         schedule_work(&tp->wk.work);
2236 }
2237
2238 static void rtl8169_init_phy(struct rtl8169_private *tp)
2239 {
2240         r8169_hw_phy_config(tp, tp->phydev, tp->mac_version);
2241
2242         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2243                 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2244                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
2245                 /* set undocumented MAC Reg C+CR Offset 0x82h */
2246                 RTL_W8(tp, 0x82, 0x01);
2247         }
2248
2249         if (tp->mac_version == RTL_GIGA_MAC_VER_05 &&
2250             tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE &&
2251             tp->pci_dev->subsystem_device == 0xe000)
2252                 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b);
2253
2254         /* We may have called phy_speed_down before */
2255         phy_speed_up(tp->phydev);
2256
2257         if (rtl_supports_eee(tp))
2258                 rtl_enable_eee(tp);
2259
2260         genphy_soft_reset(tp->phydev);
2261 }
2262
2263 static void rtl_rar_set(struct rtl8169_private *tp, const u8 *addr)
2264 {
2265         rtl_unlock_config_regs(tp);
2266
2267         RTL_W32(tp, MAC4, get_unaligned_le16(addr + 4));
2268         rtl_pci_commit(tp);
2269
2270         RTL_W32(tp, MAC0, get_unaligned_le32(addr));
2271         rtl_pci_commit(tp);
2272
2273         if (tp->mac_version == RTL_GIGA_MAC_VER_34)
2274                 rtl_rar_exgmac_set(tp, addr);
2275
2276         rtl_lock_config_regs(tp);
2277 }
2278
2279 static int rtl_set_mac_address(struct net_device *dev, void *p)
2280 {
2281         struct rtl8169_private *tp = netdev_priv(dev);
2282         int ret;
2283
2284         ret = eth_mac_addr(dev, p);
2285         if (ret)
2286                 return ret;
2287
2288         rtl_rar_set(tp, dev->dev_addr);
2289
2290         return 0;
2291 }
2292
2293 static void rtl_init_rxcfg(struct rtl8169_private *tp)
2294 {
2295         switch (tp->mac_version) {
2296         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
2297         case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
2298                 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
2299                 break;
2300         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
2301         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
2302         case RTL_GIGA_MAC_VER_38:
2303                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
2304                 break;
2305         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53:
2306                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
2307                 break;
2308         case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63:
2309                 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST);
2310                 break;
2311         default:
2312                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
2313                 break;
2314         }
2315 }
2316
2317 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2318 {
2319         tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
2320 }
2321
2322 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
2323 {
2324         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2325         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
2326 }
2327
2328 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
2329 {
2330         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2331         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
2332 }
2333
2334 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
2335 {
2336         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2337 }
2338
2339 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
2340 {
2341         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2342 }
2343
2344 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
2345 {
2346         RTL_W8(tp, MaxTxPacketSize, 0x24);
2347         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2348         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
2349 }
2350
2351 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
2352 {
2353         RTL_W8(tp, MaxTxPacketSize, 0x3f);
2354         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2355         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
2356 }
2357
2358 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
2359 {
2360         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
2361 }
2362
2363 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
2364 {
2365         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
2366 }
2367
2368 static void rtl_jumbo_config(struct rtl8169_private *tp)
2369 {
2370         bool jumbo = tp->dev->mtu > ETH_DATA_LEN;
2371         int readrq = 4096;
2372
2373         rtl_unlock_config_regs(tp);
2374         switch (tp->mac_version) {
2375         case RTL_GIGA_MAC_VER_17:
2376                 if (jumbo) {
2377                         readrq = 512;
2378                         r8168b_1_hw_jumbo_enable(tp);
2379                 } else {
2380                         r8168b_1_hw_jumbo_disable(tp);
2381                 }
2382                 break;
2383         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26:
2384                 if (jumbo) {
2385                         readrq = 512;
2386                         r8168c_hw_jumbo_enable(tp);
2387                 } else {
2388                         r8168c_hw_jumbo_disable(tp);
2389                 }
2390                 break;
2391         case RTL_GIGA_MAC_VER_28:
2392                 if (jumbo)
2393                         r8168dp_hw_jumbo_enable(tp);
2394                 else
2395                         r8168dp_hw_jumbo_disable(tp);
2396                 break;
2397         case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33:
2398                 if (jumbo)
2399                         r8168e_hw_jumbo_enable(tp);
2400                 else
2401                         r8168e_hw_jumbo_disable(tp);
2402                 break;
2403         default:
2404                 break;
2405         }
2406         rtl_lock_config_regs(tp);
2407
2408         if (pci_is_pcie(tp->pci_dev) && tp->supports_gmii)
2409                 pcie_set_readrq(tp->pci_dev, readrq);
2410
2411         /* Chip doesn't support pause in jumbo mode */
2412         if (jumbo) {
2413                 linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT,
2414                                    tp->phydev->advertising);
2415                 linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
2416                                    tp->phydev->advertising);
2417                 phy_start_aneg(tp->phydev);
2418         }
2419 }
2420
2421 DECLARE_RTL_COND(rtl_chipcmd_cond)
2422 {
2423         return RTL_R8(tp, ChipCmd) & CmdReset;
2424 }
2425
2426 static void rtl_hw_reset(struct rtl8169_private *tp)
2427 {
2428         RTL_W8(tp, ChipCmd, CmdReset);
2429
2430         rtl_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
2431 }
2432
2433 static void rtl_request_firmware(struct rtl8169_private *tp)
2434 {
2435         struct rtl_fw *rtl_fw;
2436
2437         /* firmware loaded already or no firmware available */
2438         if (tp->rtl_fw || !tp->fw_name)
2439                 return;
2440
2441         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
2442         if (!rtl_fw)
2443                 return;
2444
2445         rtl_fw->phy_write = rtl_writephy;
2446         rtl_fw->phy_read = rtl_readphy;
2447         rtl_fw->mac_mcu_write = mac_mcu_write;
2448         rtl_fw->mac_mcu_read = mac_mcu_read;
2449         rtl_fw->fw_name = tp->fw_name;
2450         rtl_fw->dev = tp_to_dev(tp);
2451
2452         if (rtl_fw_request_firmware(rtl_fw))
2453                 kfree(rtl_fw);
2454         else
2455                 tp->rtl_fw = rtl_fw;
2456 }
2457
2458 static void rtl_rx_close(struct rtl8169_private *tp)
2459 {
2460         RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
2461 }
2462
2463 DECLARE_RTL_COND(rtl_npq_cond)
2464 {
2465         return RTL_R8(tp, TxPoll) & NPQ;
2466 }
2467
2468 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
2469 {
2470         return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
2471 }
2472
2473 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
2474 {
2475         return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
2476 }
2477
2478 DECLARE_RTL_COND(rtl_rxtx_empty_cond_2)
2479 {
2480         /* IntrMitigate has new functionality on RTL8125 */
2481         return (RTL_R16(tp, IntrMitigate) & 0x0103) == 0x0103;
2482 }
2483
2484 static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp)
2485 {
2486         switch (tp->mac_version) {
2487         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53:
2488                 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42);
2489                 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2490                 break;
2491         case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_61:
2492                 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2493                 break;
2494         case RTL_GIGA_MAC_VER_63:
2495                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
2496                 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2497                 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond_2, 100, 42);
2498                 break;
2499         default:
2500                 break;
2501         }
2502 }
2503
2504 static void rtl_disable_rxdvgate(struct rtl8169_private *tp)
2505 {
2506         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
2507 }
2508
2509 static void rtl_enable_rxdvgate(struct rtl8169_private *tp)
2510 {
2511         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
2512         fsleep(2000);
2513         rtl_wait_txrx_fifo_empty(tp);
2514 }
2515
2516 static void rtl_wol_enable_rx(struct rtl8169_private *tp)
2517 {
2518         if (tp->mac_version >= RTL_GIGA_MAC_VER_25)
2519                 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
2520                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
2521
2522         if (tp->mac_version >= RTL_GIGA_MAC_VER_40)
2523                 rtl_disable_rxdvgate(tp);
2524 }
2525
2526 static void rtl_prepare_power_down(struct rtl8169_private *tp)
2527 {
2528         if (tp->dash_enabled)
2529                 return;
2530
2531         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
2532             tp->mac_version == RTL_GIGA_MAC_VER_33)
2533                 rtl_ephy_write(tp, 0x19, 0xff64);
2534
2535         if (device_may_wakeup(tp_to_dev(tp))) {
2536                 phy_speed_down(tp->phydev, false);
2537                 rtl_wol_enable_rx(tp);
2538         }
2539 }
2540
2541 static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
2542 {
2543         u32 val = TX_DMA_BURST << TxDMAShift |
2544                   InterFrameGap << TxInterFrameGapShift;
2545
2546         if (rtl_is_8168evl_up(tp))
2547                 val |= TXCFG_AUTO_FIFO;
2548
2549         RTL_W32(tp, TxConfig, val);
2550 }
2551
2552 static void rtl_set_rx_max_size(struct rtl8169_private *tp)
2553 {
2554         /* Low hurts. Let's disable the filtering. */
2555         RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
2556 }
2557
2558 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
2559 {
2560         /*
2561          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
2562          * register to be written before TxDescAddrLow to work.
2563          * Switching from MMIO to I/O access fixes the issue as well.
2564          */
2565         RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
2566         RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
2567         RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
2568         RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
2569 }
2570
2571 static void rtl8169_set_magic_reg(struct rtl8169_private *tp)
2572 {
2573         u32 val;
2574
2575         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
2576                 val = 0x000fff00;
2577         else if (tp->mac_version == RTL_GIGA_MAC_VER_06)
2578                 val = 0x00ffff00;
2579         else
2580                 return;
2581
2582         if (RTL_R8(tp, Config2) & PCI_Clock_66MHz)
2583                 val |= 0xff;
2584
2585         RTL_W32(tp, 0x7c, val);
2586 }
2587
2588 static void rtl_set_rx_mode(struct net_device *dev)
2589 {
2590         u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast;
2591         /* Multicast hash filter */
2592         u32 mc_filter[2] = { 0xffffffff, 0xffffffff };
2593         struct rtl8169_private *tp = netdev_priv(dev);
2594         u32 tmp;
2595
2596         if (dev->flags & IFF_PROMISC) {
2597                 rx_mode |= AcceptAllPhys;
2598         } else if (!(dev->flags & IFF_MULTICAST)) {
2599                 rx_mode &= ~AcceptMulticast;
2600         } else if (netdev_mc_count(dev) > MC_FILTER_LIMIT ||
2601                    dev->flags & IFF_ALLMULTI ||
2602                    tp->mac_version == RTL_GIGA_MAC_VER_35 ||
2603                    tp->mac_version == RTL_GIGA_MAC_VER_46 ||
2604                    tp->mac_version == RTL_GIGA_MAC_VER_48) {
2605                 /* accept all multicasts */
2606         } else if (netdev_mc_empty(dev)) {
2607                 rx_mode &= ~AcceptMulticast;
2608         } else {
2609                 struct netdev_hw_addr *ha;
2610
2611                 mc_filter[1] = mc_filter[0] = 0;
2612                 netdev_for_each_mc_addr(ha, dev) {
2613                         u32 bit_nr = eth_hw_addr_crc(ha) >> 26;
2614                         mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31);
2615                 }
2616
2617                 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
2618                         tmp = mc_filter[0];
2619                         mc_filter[0] = swab32(mc_filter[1]);
2620                         mc_filter[1] = swab32(tmp);
2621                 }
2622         }
2623
2624         RTL_W32(tp, MAR0 + 4, mc_filter[1]);
2625         RTL_W32(tp, MAR0 + 0, mc_filter[0]);
2626
2627         tmp = RTL_R32(tp, RxConfig);
2628         RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode);
2629 }
2630
2631 DECLARE_RTL_COND(rtl_csiar_cond)
2632 {
2633         return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
2634 }
2635
2636 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
2637 {
2638         u32 func = PCI_FUNC(tp->pci_dev->devfn);
2639
2640         RTL_W32(tp, CSIDR, value);
2641         RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
2642                 CSIAR_BYTE_ENABLE | func << 16);
2643
2644         rtl_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
2645 }
2646
2647 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
2648 {
2649         u32 func = PCI_FUNC(tp->pci_dev->devfn);
2650
2651         RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
2652                 CSIAR_BYTE_ENABLE);
2653
2654         return rtl_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
2655                 RTL_R32(tp, CSIDR) : ~0;
2656 }
2657
2658 static void rtl_set_aspm_entry_latency(struct rtl8169_private *tp, u8 val)
2659 {
2660         struct pci_dev *pdev = tp->pci_dev;
2661         u32 csi;
2662
2663         /* According to Realtek the value at config space address 0x070f
2664          * controls the L0s/L1 entrance latency. We try standard ECAM access
2665          * first and if it fails fall back to CSI.
2666          * bit 0..2: L0: 0 = 1us, 1 = 2us .. 6 = 7us, 7 = 7us (no typo)
2667          * bit 3..5: L1: 0 = 1us, 1 = 2us .. 6 = 64us, 7 = 64us
2668          */
2669         if (pdev->cfg_size > 0x070f &&
2670             pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
2671                 return;
2672
2673         netdev_notice_once(tp->dev,
2674                 "No native access to PCI extended config space, falling back to CSI\n");
2675         csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
2676         rtl_csi_write(tp, 0x070c, csi | val << 24);
2677 }
2678
2679 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
2680 {
2681         /* L0 7us, L1 16us */
2682         rtl_set_aspm_entry_latency(tp, 0x27);
2683 }
2684
2685 struct ephy_info {
2686         unsigned int offset;
2687         u16 mask;
2688         u16 bits;
2689 };
2690
2691 static void __rtl_ephy_init(struct rtl8169_private *tp,
2692                             const struct ephy_info *e, int len)
2693 {
2694         u16 w;
2695
2696         while (len-- > 0) {
2697                 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
2698                 rtl_ephy_write(tp, e->offset, w);
2699                 e++;
2700         }
2701 }
2702
2703 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a))
2704
2705 static void rtl_disable_clock_request(struct rtl8169_private *tp)
2706 {
2707         pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
2708                                    PCI_EXP_LNKCTL_CLKREQ_EN);
2709 }
2710
2711 static void rtl_enable_clock_request(struct rtl8169_private *tp)
2712 {
2713         pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
2714                                  PCI_EXP_LNKCTL_CLKREQ_EN);
2715 }
2716
2717 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp)
2718 {
2719         /* work around an issue when PCI reset occurs during L2/L3 state */
2720         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23);
2721 }
2722
2723 static void rtl_enable_exit_l1(struct rtl8169_private *tp)
2724 {
2725         /* Bits control which events trigger ASPM L1 exit:
2726          * Bit 12: rxdv
2727          * Bit 11: ltr_msg
2728          * Bit 10: txdma_poll
2729          * Bit  9: xadm
2730          * Bit  8: pktavi
2731          * Bit  7: txpla
2732          */
2733         switch (tp->mac_version) {
2734         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
2735                 rtl_eri_set_bits(tp, 0xd4, 0x1f00);
2736                 break;
2737         case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_38:
2738                 rtl_eri_set_bits(tp, 0xd4, 0x0c00);
2739                 break;
2740         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
2741                 r8168_mac_ocp_modify(tp, 0xc0ac, 0, 0x1f80);
2742                 break;
2743         default:
2744                 break;
2745         }
2746 }
2747
2748 static void rtl_disable_exit_l1(struct rtl8169_private *tp)
2749 {
2750         switch (tp->mac_version) {
2751         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
2752                 rtl_eri_clear_bits(tp, 0xd4, 0x1f00);
2753                 break;
2754         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
2755                 r8168_mac_ocp_modify(tp, 0xc0ac, 0x1f80, 0);
2756                 break;
2757         default:
2758                 break;
2759         }
2760 }
2761
2762 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
2763 {
2764         if (tp->mac_version < RTL_GIGA_MAC_VER_32)
2765                 return;
2766
2767         /* Don't enable ASPM in the chip if OS can't control ASPM */
2768         if (enable && tp->aspm_manageable) {
2769                 /* On these chip versions ASPM can even harm
2770                  * bus communication of other PCI devices.
2771                  */
2772                 if (tp->mac_version == RTL_GIGA_MAC_VER_42 ||
2773                     tp->mac_version == RTL_GIGA_MAC_VER_43)
2774                         return;
2775
2776                 rtl_mod_config5(tp, 0, ASPM_en);
2777                 rtl_mod_config2(tp, 0, ClkReqEn);
2778
2779                 switch (tp->mac_version) {
2780                 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48:
2781                 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63:
2782                         /* reset ephy tx/rx disable timer */
2783                         r8168_mac_ocp_modify(tp, 0xe094, 0xff00, 0);
2784                         /* chip can trigger L1.2 */
2785                         r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, BIT(2));
2786                         break;
2787                 default:
2788                         break;
2789                 }
2790         } else {
2791                 switch (tp->mac_version) {
2792                 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48:
2793                 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63:
2794                         r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, 0);
2795                         break;
2796                 default:
2797                         break;
2798                 }
2799
2800                 rtl_mod_config2(tp, ClkReqEn, 0);
2801                 rtl_mod_config5(tp, ASPM_en, 0);
2802         }
2803 }
2804
2805 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat,
2806                               u16 tx_stat, u16 rx_dyn, u16 tx_dyn)
2807 {
2808         /* Usage of dynamic vs. static FIFO is controlled by bit
2809          * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known.
2810          */
2811         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn);
2812         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn);
2813 }
2814
2815 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp,
2816                                           u8 low, u8 high)
2817 {
2818         /* FIFO thresholds for pause flow control */
2819         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low);
2820         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high);
2821 }
2822
2823 static void rtl_hw_start_8168b(struct rtl8169_private *tp)
2824 {
2825         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2826 }
2827
2828 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
2829 {
2830         RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
2831
2832         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2833
2834         rtl_disable_clock_request(tp);
2835 }
2836
2837 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
2838 {
2839         static const struct ephy_info e_info_8168cp[] = {
2840                 { 0x01, 0,      0x0001 },
2841                 { 0x02, 0x0800, 0x1000 },
2842                 { 0x03, 0,      0x0042 },
2843                 { 0x06, 0x0080, 0x0000 },
2844                 { 0x07, 0,      0x2000 }
2845         };
2846
2847         rtl_set_def_aspm_entry_latency(tp);
2848
2849         rtl_ephy_init(tp, e_info_8168cp);
2850
2851         __rtl_hw_start_8168cp(tp);
2852 }
2853
2854 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
2855 {
2856         rtl_set_def_aspm_entry_latency(tp);
2857
2858         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2859 }
2860
2861 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
2862 {
2863         rtl_set_def_aspm_entry_latency(tp);
2864
2865         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2866
2867         /* Magic. */
2868         RTL_W8(tp, DBG_REG, 0x20);
2869 }
2870
2871 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
2872 {
2873         static const struct ephy_info e_info_8168c_1[] = {
2874                 { 0x02, 0x0800, 0x1000 },
2875                 { 0x03, 0,      0x0002 },
2876                 { 0x06, 0x0080, 0x0000 }
2877         };
2878
2879         rtl_set_def_aspm_entry_latency(tp);
2880
2881         RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
2882
2883         rtl_ephy_init(tp, e_info_8168c_1);
2884
2885         __rtl_hw_start_8168cp(tp);
2886 }
2887
2888 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
2889 {
2890         static const struct ephy_info e_info_8168c_2[] = {
2891                 { 0x01, 0,      0x0001 },
2892                 { 0x03, 0x0400, 0x0020 }
2893         };
2894
2895         rtl_set_def_aspm_entry_latency(tp);
2896
2897         rtl_ephy_init(tp, e_info_8168c_2);
2898
2899         __rtl_hw_start_8168cp(tp);
2900 }
2901
2902 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
2903 {
2904         rtl_set_def_aspm_entry_latency(tp);
2905
2906         __rtl_hw_start_8168cp(tp);
2907 }
2908
2909 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
2910 {
2911         rtl_set_def_aspm_entry_latency(tp);
2912
2913         rtl_disable_clock_request(tp);
2914 }
2915
2916 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
2917 {
2918         static const struct ephy_info e_info_8168d_4[] = {
2919                 { 0x0b, 0x0000, 0x0048 },
2920                 { 0x19, 0x0020, 0x0050 },
2921                 { 0x0c, 0x0100, 0x0020 },
2922                 { 0x10, 0x0004, 0x0000 },
2923         };
2924
2925         rtl_set_def_aspm_entry_latency(tp);
2926
2927         rtl_ephy_init(tp, e_info_8168d_4);
2928
2929         rtl_enable_clock_request(tp);
2930 }
2931
2932 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
2933 {
2934         static const struct ephy_info e_info_8168e_1[] = {
2935                 { 0x00, 0x0200, 0x0100 },
2936                 { 0x00, 0x0000, 0x0004 },
2937                 { 0x06, 0x0002, 0x0001 },
2938                 { 0x06, 0x0000, 0x0030 },
2939                 { 0x07, 0x0000, 0x2000 },
2940                 { 0x00, 0x0000, 0x0020 },
2941                 { 0x03, 0x5800, 0x2000 },
2942                 { 0x03, 0x0000, 0x0001 },
2943                 { 0x01, 0x0800, 0x1000 },
2944                 { 0x07, 0x0000, 0x4000 },
2945                 { 0x1e, 0x0000, 0x2000 },
2946                 { 0x19, 0xffff, 0xfe6c },
2947                 { 0x0a, 0x0000, 0x0040 }
2948         };
2949
2950         rtl_set_def_aspm_entry_latency(tp);
2951
2952         rtl_ephy_init(tp, e_info_8168e_1);
2953
2954         rtl_disable_clock_request(tp);
2955
2956         /* Reset tx FIFO pointer */
2957         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
2958         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
2959
2960         rtl_mod_config5(tp, Spi_en, 0);
2961 }
2962
2963 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
2964 {
2965         static const struct ephy_info e_info_8168e_2[] = {
2966                 { 0x09, 0x0000, 0x0080 },
2967                 { 0x19, 0x0000, 0x0224 },
2968                 { 0x00, 0x0000, 0x0004 },
2969                 { 0x0c, 0x3df0, 0x0200 },
2970         };
2971
2972         rtl_set_def_aspm_entry_latency(tp);
2973
2974         rtl_ephy_init(tp, e_info_8168e_2);
2975
2976         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
2977         rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000);
2978         rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
2979         rtl_eri_set_bits(tp, 0x1d0, BIT(1));
2980         rtl_reset_packet_filter(tp);
2981         rtl_eri_set_bits(tp, 0x1b0, BIT(4));
2982         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
2983         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060);
2984
2985         rtl_disable_clock_request(tp);
2986
2987         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
2988
2989         rtl8168_config_eee_mac(tp);
2990
2991         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
2992         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
2993         rtl_mod_config5(tp, Spi_en, 0);
2994 }
2995
2996 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
2997 {
2998         rtl_set_def_aspm_entry_latency(tp);
2999
3000         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3001         rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000);
3002         rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
3003         rtl_reset_packet_filter(tp);
3004         rtl_eri_set_bits(tp, 0x1b0, BIT(4));
3005         rtl_eri_set_bits(tp, 0x1d0, BIT(4) | BIT(1));
3006         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
3007         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060);
3008
3009         rtl_disable_clock_request(tp);
3010
3011         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
3012         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
3013         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
3014         rtl_mod_config5(tp, Spi_en, 0);
3015
3016         rtl8168_config_eee_mac(tp);
3017 }
3018
3019 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
3020 {
3021         static const struct ephy_info e_info_8168f_1[] = {
3022                 { 0x06, 0x00c0, 0x0020 },
3023                 { 0x08, 0x0001, 0x0002 },
3024                 { 0x09, 0x0000, 0x0080 },
3025                 { 0x19, 0x0000, 0x0224 },
3026                 { 0x00, 0x0000, 0x0008 },
3027                 { 0x0c, 0x3df0, 0x0200 },
3028         };
3029
3030         rtl_hw_start_8168f(tp);
3031
3032         rtl_ephy_init(tp, e_info_8168f_1);
3033 }
3034
3035 static void rtl_hw_start_8411(struct rtl8169_private *tp)
3036 {
3037         static const struct ephy_info e_info_8168f_1[] = {
3038                 { 0x06, 0x00c0, 0x0020 },
3039                 { 0x0f, 0xffff, 0x5200 },
3040                 { 0x19, 0x0000, 0x0224 },
3041                 { 0x00, 0x0000, 0x0008 },
3042                 { 0x0c, 0x3df0, 0x0200 },
3043         };
3044
3045         rtl_hw_start_8168f(tp);
3046         rtl_pcie_state_l2l3_disable(tp);
3047
3048         rtl_ephy_init(tp, e_info_8168f_1);
3049 }
3050
3051 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
3052 {
3053         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3054         rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
3055
3056         rtl_set_def_aspm_entry_latency(tp);
3057
3058         rtl_reset_packet_filter(tp);
3059         rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f);
3060
3061         rtl_disable_rxdvgate(tp);
3062
3063         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3064         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3065
3066         rtl8168_config_eee_mac(tp);
3067
3068         rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06);
3069         rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
3070
3071         rtl_pcie_state_l2l3_disable(tp);
3072 }
3073
3074 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
3075 {
3076         static const struct ephy_info e_info_8168g_1[] = {
3077                 { 0x00, 0x0008, 0x0000 },
3078                 { 0x0c, 0x3ff0, 0x0820 },
3079                 { 0x1e, 0x0000, 0x0001 },
3080                 { 0x19, 0x8000, 0x0000 }
3081         };
3082
3083         rtl_hw_start_8168g(tp);
3084         rtl_ephy_init(tp, e_info_8168g_1);
3085 }
3086
3087 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
3088 {
3089         static const struct ephy_info e_info_8168g_2[] = {
3090                 { 0x00, 0x0008, 0x0000 },
3091                 { 0x0c, 0x3ff0, 0x0820 },
3092                 { 0x19, 0xffff, 0x7c00 },
3093                 { 0x1e, 0xffff, 0x20eb },
3094                 { 0x0d, 0xffff, 0x1666 },
3095                 { 0x00, 0xffff, 0x10a3 },
3096                 { 0x06, 0xffff, 0xf050 },
3097                 { 0x04, 0x0000, 0x0010 },
3098                 { 0x1d, 0x4000, 0x0000 },
3099         };
3100
3101         rtl_hw_start_8168g(tp);
3102         rtl_ephy_init(tp, e_info_8168g_2);
3103 }
3104
3105 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
3106 {
3107         static const struct ephy_info e_info_8411_2[] = {
3108                 { 0x00, 0x0008, 0x0000 },
3109                 { 0x0c, 0x37d0, 0x0820 },
3110                 { 0x1e, 0x0000, 0x0001 },
3111                 { 0x19, 0x8021, 0x0000 },
3112                 { 0x1e, 0x0000, 0x2000 },
3113                 { 0x0d, 0x0100, 0x0200 },
3114                 { 0x00, 0x0000, 0x0080 },
3115                 { 0x06, 0x0000, 0x0010 },
3116                 { 0x04, 0x0000, 0x0010 },
3117                 { 0x1d, 0x0000, 0x4000 },
3118         };
3119
3120         rtl_hw_start_8168g(tp);
3121
3122         rtl_ephy_init(tp, e_info_8411_2);
3123
3124         /* The following Realtek-provided magic fixes an issue with the RX unit
3125          * getting confused after the PHY having been powered-down.
3126          */
3127         r8168_mac_ocp_write(tp, 0xFC28, 0x0000);
3128         r8168_mac_ocp_write(tp, 0xFC2A, 0x0000);
3129         r8168_mac_ocp_write(tp, 0xFC2C, 0x0000);
3130         r8168_mac_ocp_write(tp, 0xFC2E, 0x0000);
3131         r8168_mac_ocp_write(tp, 0xFC30, 0x0000);
3132         r8168_mac_ocp_write(tp, 0xFC32, 0x0000);
3133         r8168_mac_ocp_write(tp, 0xFC34, 0x0000);
3134         r8168_mac_ocp_write(tp, 0xFC36, 0x0000);
3135         mdelay(3);
3136         r8168_mac_ocp_write(tp, 0xFC26, 0x0000);
3137
3138         r8168_mac_ocp_write(tp, 0xF800, 0xE008);
3139         r8168_mac_ocp_write(tp, 0xF802, 0xE00A);
3140         r8168_mac_ocp_write(tp, 0xF804, 0xE00C);
3141         r8168_mac_ocp_write(tp, 0xF806, 0xE00E);
3142         r8168_mac_ocp_write(tp, 0xF808, 0xE027);
3143         r8168_mac_ocp_write(tp, 0xF80A, 0xE04F);
3144         r8168_mac_ocp_write(tp, 0xF80C, 0xE05E);
3145         r8168_mac_ocp_write(tp, 0xF80E, 0xE065);
3146         r8168_mac_ocp_write(tp, 0xF810, 0xC602);
3147         r8168_mac_ocp_write(tp, 0xF812, 0xBE00);
3148         r8168_mac_ocp_write(tp, 0xF814, 0x0000);
3149         r8168_mac_ocp_write(tp, 0xF816, 0xC502);
3150         r8168_mac_ocp_write(tp, 0xF818, 0xBD00);
3151         r8168_mac_ocp_write(tp, 0xF81A, 0x074C);
3152         r8168_mac_ocp_write(tp, 0xF81C, 0xC302);
3153         r8168_mac_ocp_write(tp, 0xF81E, 0xBB00);
3154         r8168_mac_ocp_write(tp, 0xF820, 0x080A);
3155         r8168_mac_ocp_write(tp, 0xF822, 0x6420);
3156         r8168_mac_ocp_write(tp, 0xF824, 0x48C2);
3157         r8168_mac_ocp_write(tp, 0xF826, 0x8C20);
3158         r8168_mac_ocp_write(tp, 0xF828, 0xC516);
3159         r8168_mac_ocp_write(tp, 0xF82A, 0x64A4);
3160         r8168_mac_ocp_write(tp, 0xF82C, 0x49C0);
3161         r8168_mac_ocp_write(tp, 0xF82E, 0xF009);
3162         r8168_mac_ocp_write(tp, 0xF830, 0x74A2);
3163         r8168_mac_ocp_write(tp, 0xF832, 0x8CA5);
3164         r8168_mac_ocp_write(tp, 0xF834, 0x74A0);
3165         r8168_mac_ocp_write(tp, 0xF836, 0xC50E);
3166         r8168_mac_ocp_write(tp, 0xF838, 0x9CA2);
3167         r8168_mac_ocp_write(tp, 0xF83A, 0x1C11);
3168         r8168_mac_ocp_write(tp, 0xF83C, 0x9CA0);
3169         r8168_mac_ocp_write(tp, 0xF83E, 0xE006);
3170         r8168_mac_ocp_write(tp, 0xF840, 0x74F8);
3171         r8168_mac_ocp_write(tp, 0xF842, 0x48C4);
3172         r8168_mac_ocp_write(tp, 0xF844, 0x8CF8);
3173         r8168_mac_ocp_write(tp, 0xF846, 0xC404);
3174         r8168_mac_ocp_write(tp, 0xF848, 0xBC00);
3175         r8168_mac_ocp_write(tp, 0xF84A, 0xC403);
3176         r8168_mac_ocp_write(tp, 0xF84C, 0xBC00);
3177         r8168_mac_ocp_write(tp, 0xF84E, 0x0BF2);
3178         r8168_mac_ocp_write(tp, 0xF850, 0x0C0A);
3179         r8168_mac_ocp_write(tp, 0xF852, 0xE434);
3180         r8168_mac_ocp_write(tp, 0xF854, 0xD3C0);
3181         r8168_mac_ocp_write(tp, 0xF856, 0x49D9);
3182         r8168_mac_ocp_write(tp, 0xF858, 0xF01F);
3183         r8168_mac_ocp_write(tp, 0xF85A, 0xC526);
3184         r8168_mac_ocp_write(tp, 0xF85C, 0x64A5);
3185         r8168_mac_ocp_write(tp, 0xF85E, 0x1400);
3186         r8168_mac_ocp_write(tp, 0xF860, 0xF007);
3187         r8168_mac_ocp_write(tp, 0xF862, 0x0C01);
3188         r8168_mac_ocp_write(tp, 0xF864, 0x8CA5);
3189         r8168_mac_ocp_write(tp, 0xF866, 0x1C15);
3190         r8168_mac_ocp_write(tp, 0xF868, 0xC51B);
3191         r8168_mac_ocp_write(tp, 0xF86A, 0x9CA0);
3192         r8168_mac_ocp_write(tp, 0xF86C, 0xE013);
3193         r8168_mac_ocp_write(tp, 0xF86E, 0xC519);
3194         r8168_mac_ocp_write(tp, 0xF870, 0x74A0);
3195         r8168_mac_ocp_write(tp, 0xF872, 0x48C4);
3196         r8168_mac_ocp_write(tp, 0xF874, 0x8CA0);
3197         r8168_mac_ocp_write(tp, 0xF876, 0xC516);
3198         r8168_mac_ocp_write(tp, 0xF878, 0x74A4);
3199         r8168_mac_ocp_write(tp, 0xF87A, 0x48C8);
3200         r8168_mac_ocp_write(tp, 0xF87C, 0x48CA);
3201         r8168_mac_ocp_write(tp, 0xF87E, 0x9CA4);
3202         r8168_mac_ocp_write(tp, 0xF880, 0xC512);
3203         r8168_mac_ocp_write(tp, 0xF882, 0x1B00);
3204         r8168_mac_ocp_write(tp, 0xF884, 0x9BA0);
3205         r8168_mac_ocp_write(tp, 0xF886, 0x1B1C);
3206         r8168_mac_ocp_write(tp, 0xF888, 0x483F);
3207         r8168_mac_ocp_write(tp, 0xF88A, 0x9BA2);
3208         r8168_mac_ocp_write(tp, 0xF88C, 0x1B04);
3209         r8168_mac_ocp_write(tp, 0xF88E, 0xC508);
3210         r8168_mac_ocp_write(tp, 0xF890, 0x9BA0);
3211         r8168_mac_ocp_write(tp, 0xF892, 0xC505);
3212         r8168_mac_ocp_write(tp, 0xF894, 0xBD00);
3213         r8168_mac_ocp_write(tp, 0xF896, 0xC502);
3214         r8168_mac_ocp_write(tp, 0xF898, 0xBD00);
3215         r8168_mac_ocp_write(tp, 0xF89A, 0x0300);
3216         r8168_mac_ocp_write(tp, 0xF89C, 0x051E);
3217         r8168_mac_ocp_write(tp, 0xF89E, 0xE434);
3218         r8168_mac_ocp_write(tp, 0xF8A0, 0xE018);
3219         r8168_mac_ocp_write(tp, 0xF8A2, 0xE092);
3220         r8168_mac_ocp_write(tp, 0xF8A4, 0xDE20);
3221         r8168_mac_ocp_write(tp, 0xF8A6, 0xD3C0);
3222         r8168_mac_ocp_write(tp, 0xF8A8, 0xC50F);
3223         r8168_mac_ocp_write(tp, 0xF8AA, 0x76A4);
3224         r8168_mac_ocp_write(tp, 0xF8AC, 0x49E3);
3225         r8168_mac_ocp_write(tp, 0xF8AE, 0xF007);
3226         r8168_mac_ocp_write(tp, 0xF8B0, 0x49C0);
3227         r8168_mac_ocp_write(tp, 0xF8B2, 0xF103);
3228         r8168_mac_ocp_write(tp, 0xF8B4, 0xC607);
3229         r8168_mac_ocp_write(tp, 0xF8B6, 0xBE00);
3230         r8168_mac_ocp_write(tp, 0xF8B8, 0xC606);
3231         r8168_mac_ocp_write(tp, 0xF8BA, 0xBE00);
3232         r8168_mac_ocp_write(tp, 0xF8BC, 0xC602);
3233         r8168_mac_ocp_write(tp, 0xF8BE, 0xBE00);
3234         r8168_mac_ocp_write(tp, 0xF8C0, 0x0C4C);
3235         r8168_mac_ocp_write(tp, 0xF8C2, 0x0C28);
3236         r8168_mac_ocp_write(tp, 0xF8C4, 0x0C2C);
3237         r8168_mac_ocp_write(tp, 0xF8C6, 0xDC00);
3238         r8168_mac_ocp_write(tp, 0xF8C8, 0xC707);
3239         r8168_mac_ocp_write(tp, 0xF8CA, 0x1D00);
3240         r8168_mac_ocp_write(tp, 0xF8CC, 0x8DE2);
3241         r8168_mac_ocp_write(tp, 0xF8CE, 0x48C1);
3242         r8168_mac_ocp_write(tp, 0xF8D0, 0xC502);
3243         r8168_mac_ocp_write(tp, 0xF8D2, 0xBD00);
3244         r8168_mac_ocp_write(tp, 0xF8D4, 0x00AA);
3245         r8168_mac_ocp_write(tp, 0xF8D6, 0xE0C0);
3246         r8168_mac_ocp_write(tp, 0xF8D8, 0xC502);
3247         r8168_mac_ocp_write(tp, 0xF8DA, 0xBD00);
3248         r8168_mac_ocp_write(tp, 0xF8DC, 0x0132);
3249
3250         r8168_mac_ocp_write(tp, 0xFC26, 0x8000);
3251
3252         r8168_mac_ocp_write(tp, 0xFC2A, 0x0743);
3253         r8168_mac_ocp_write(tp, 0xFC2C, 0x0801);
3254         r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9);
3255         r8168_mac_ocp_write(tp, 0xFC30, 0x02FD);
3256         r8168_mac_ocp_write(tp, 0xFC32, 0x0C25);
3257         r8168_mac_ocp_write(tp, 0xFC34, 0x00A9);
3258         r8168_mac_ocp_write(tp, 0xFC36, 0x012D);
3259 }
3260
3261 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
3262 {
3263         static const struct ephy_info e_info_8168h_1[] = {
3264                 { 0x1e, 0x0800, 0x0001 },
3265                 { 0x1d, 0x0000, 0x0800 },
3266                 { 0x05, 0xffff, 0x2089 },
3267                 { 0x06, 0xffff, 0x5881 },
3268                 { 0x04, 0xffff, 0x854a },
3269                 { 0x01, 0xffff, 0x068b }
3270         };
3271         int rg_saw_cnt;
3272
3273         rtl_ephy_init(tp, e_info_8168h_1);
3274
3275         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3276         rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
3277
3278         rtl_set_def_aspm_entry_latency(tp);
3279
3280         rtl_reset_packet_filter(tp);
3281
3282         rtl_eri_set_bits(tp, 0xdc, 0x001c);
3283
3284         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3285
3286         rtl_disable_rxdvgate(tp);
3287
3288         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3289         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3290
3291         rtl8168_config_eee_mac(tp);
3292
3293         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3294         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3295
3296         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3297
3298         rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
3299
3300         rtl_pcie_state_l2l3_disable(tp);
3301
3302         rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff;
3303         if (rg_saw_cnt > 0) {
3304                 u16 sw_cnt_1ms_ini;
3305
3306                 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
3307                 sw_cnt_1ms_ini &= 0x0fff;
3308                 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);
3309         }
3310
3311         r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);
3312         r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008);
3313         r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f);
3314         r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);
3315
3316         r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
3317         r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
3318         r8168_mac_ocp_write(tp, 0xc094, 0x0000);
3319         r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
3320 }
3321
3322 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
3323 {
3324         rtl8168ep_stop_cmac(tp);
3325
3326         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3327         rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
3328
3329         rtl_set_def_aspm_entry_latency(tp);
3330
3331         rtl_reset_packet_filter(tp);
3332
3333         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3334
3335         rtl_disable_rxdvgate(tp);
3336
3337         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3338         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3339
3340         rtl8168_config_eee_mac(tp);
3341
3342         rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06);
3343
3344         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3345
3346         rtl_pcie_state_l2l3_disable(tp);
3347 }
3348
3349 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
3350 {
3351         static const struct ephy_info e_info_8168ep_3[] = {
3352                 { 0x00, 0x0000, 0x0080 },
3353                 { 0x0d, 0x0100, 0x0200 },
3354                 { 0x19, 0x8021, 0x0000 },
3355                 { 0x1e, 0x0000, 0x2000 },
3356         };
3357
3358         rtl_ephy_init(tp, e_info_8168ep_3);
3359
3360         rtl_hw_start_8168ep(tp);
3361
3362         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3363         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3364
3365         r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271);
3366         r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
3367         r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);
3368 }
3369
3370 static void rtl_hw_start_8117(struct rtl8169_private *tp)
3371 {
3372         static const struct ephy_info e_info_8117[] = {
3373                 { 0x19, 0x0040, 0x1100 },
3374                 { 0x59, 0x0040, 0x1100 },
3375         };
3376         int rg_saw_cnt;
3377
3378         rtl8168ep_stop_cmac(tp);
3379         rtl_ephy_init(tp, e_info_8117);
3380
3381         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3382         rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
3383
3384         rtl_set_def_aspm_entry_latency(tp);
3385
3386         rtl_reset_packet_filter(tp);
3387
3388         rtl_eri_set_bits(tp, 0xd4, 0x0010);
3389
3390         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3391
3392         rtl_disable_rxdvgate(tp);
3393
3394         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3395         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3396
3397         rtl8168_config_eee_mac(tp);
3398
3399         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3400         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3401
3402         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3403
3404         rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
3405
3406         rtl_pcie_state_l2l3_disable(tp);
3407
3408         rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff;
3409         if (rg_saw_cnt > 0) {
3410                 u16 sw_cnt_1ms_ini;
3411
3412                 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff;
3413                 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);
3414         }
3415
3416         r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);
3417         r8168_mac_ocp_write(tp, 0xea80, 0x0003);
3418         r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009);
3419         r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);
3420
3421         r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
3422         r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
3423         r8168_mac_ocp_write(tp, 0xc094, 0x0000);
3424         r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
3425
3426         /* firmware is for MAC only */
3427         r8169_apply_firmware(tp);
3428 }
3429
3430 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
3431 {
3432         static const struct ephy_info e_info_8102e_1[] = {
3433                 { 0x01, 0, 0x6e65 },
3434                 { 0x02, 0, 0x091f },
3435                 { 0x03, 0, 0xc2f9 },
3436                 { 0x06, 0, 0xafb5 },
3437                 { 0x07, 0, 0x0e00 },
3438                 { 0x19, 0, 0xec80 },
3439                 { 0x01, 0, 0x2e65 },
3440                 { 0x01, 0, 0x6e65 }
3441         };
3442         u8 cfg1;
3443
3444         rtl_set_def_aspm_entry_latency(tp);
3445
3446         RTL_W8(tp, DBG_REG, FIX_NAK_1);
3447
3448         RTL_W8(tp, Config1,
3449                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
3450         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3451
3452         cfg1 = RTL_R8(tp, Config1);
3453         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
3454                 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
3455
3456         rtl_ephy_init(tp, e_info_8102e_1);
3457 }
3458
3459 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
3460 {
3461         rtl_set_def_aspm_entry_latency(tp);
3462
3463         RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
3464         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3465 }
3466
3467 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
3468 {
3469         rtl_hw_start_8102e_2(tp);
3470
3471         rtl_ephy_write(tp, 0x03, 0xc2f9);
3472 }
3473
3474 static void rtl_hw_start_8401(struct rtl8169_private *tp)
3475 {
3476         static const struct ephy_info e_info_8401[] = {
3477                 { 0x01, 0xffff, 0x6fe5 },
3478                 { 0x03, 0xffff, 0x0599 },
3479                 { 0x06, 0xffff, 0xaf25 },
3480                 { 0x07, 0xffff, 0x8e68 },
3481         };
3482
3483         rtl_ephy_init(tp, e_info_8401);
3484         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3485 }
3486
3487 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
3488 {
3489         static const struct ephy_info e_info_8105e_1[] = {
3490                 { 0x07, 0, 0x4000 },
3491                 { 0x19, 0, 0x0200 },
3492                 { 0x19, 0, 0x0020 },
3493                 { 0x1e, 0, 0x2000 },
3494                 { 0x03, 0, 0x0001 },
3495                 { 0x19, 0, 0x0100 },
3496                 { 0x19, 0, 0x0004 },
3497                 { 0x0a, 0, 0x0020 }
3498         };
3499
3500         /* Force LAN exit from ASPM if Rx/Tx are not idle */
3501         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3502
3503         /* Disable Early Tally Counter */
3504         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
3505
3506         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
3507         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
3508
3509         rtl_ephy_init(tp, e_info_8105e_1);
3510
3511         rtl_pcie_state_l2l3_disable(tp);
3512 }
3513
3514 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
3515 {
3516         rtl_hw_start_8105e_1(tp);
3517         rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
3518 }
3519
3520 static void rtl_hw_start_8402(struct rtl8169_private *tp)
3521 {
3522         static const struct ephy_info e_info_8402[] = {
3523                 { 0x19, 0xffff, 0xff64 },
3524                 { 0x1e, 0, 0x4000 }
3525         };
3526
3527         rtl_set_def_aspm_entry_latency(tp);
3528
3529         /* Force LAN exit from ASPM if Rx/Tx are not idle */
3530         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3531
3532         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
3533
3534         rtl_ephy_init(tp, e_info_8402);
3535
3536         rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06);
3537         rtl_reset_packet_filter(tp);
3538         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3539         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3540         rtl_w0w1_eri(tp, 0x0d4, 0x0e00, 0xff00);
3541
3542         /* disable EEE */
3543         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3544
3545         rtl_pcie_state_l2l3_disable(tp);
3546 }
3547
3548 static void rtl_hw_start_8106(struct rtl8169_private *tp)
3549 {
3550         /* Force LAN exit from ASPM if Rx/Tx are not idle */
3551         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3552
3553         RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
3554         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
3555         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3556
3557         /* L0 7us, L1 32us - needed to avoid issues with link-up detection */
3558         rtl_set_aspm_entry_latency(tp, 0x2f);
3559
3560         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
3561
3562         /* disable EEE */
3563         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3564
3565         rtl_pcie_state_l2l3_disable(tp);
3566 }
3567
3568 DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond)
3569 {
3570         return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13);
3571 }
3572
3573 static void rtl_hw_start_8125_common(struct rtl8169_private *tp)
3574 {
3575         rtl_pcie_state_l2l3_disable(tp);
3576
3577         RTL_W16(tp, 0x382, 0x221b);
3578         RTL_W8(tp, 0x4500, 0);
3579         RTL_W16(tp, 0x4800, 0);
3580
3581         /* disable UPS */
3582         r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000);
3583
3584         RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10);
3585
3586         r8168_mac_ocp_write(tp, 0xc140, 0xffff);
3587         r8168_mac_ocp_write(tp, 0xc142, 0xffff);
3588
3589         r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9);
3590         r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
3591         r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);
3592
3593         /* disable new tx descriptor format */
3594         r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000);
3595
3596         if (tp->mac_version == RTL_GIGA_MAC_VER_63)
3597                 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200);
3598         else
3599                 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400);
3600
3601         if (tp->mac_version == RTL_GIGA_MAC_VER_63)
3602                 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0000);
3603         else
3604                 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020);
3605
3606         r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c);
3607         r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033);
3608         r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040);
3609         r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030);
3610         r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000);
3611         r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001);
3612         r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403);
3613         r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0068);
3614         r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f);
3615
3616         r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000);
3617         r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001);
3618         udelay(1);
3619         r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000);
3620         RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030);
3621
3622         r8168_mac_ocp_write(tp, 0xe098, 0xc302);
3623
3624         rtl_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10);
3625
3626         if (tp->mac_version == RTL_GIGA_MAC_VER_63)
3627                 rtl8125b_config_eee_mac(tp);
3628         else
3629                 rtl8125a_config_eee_mac(tp);
3630
3631         rtl_disable_rxdvgate(tp);
3632 }
3633
3634 static void rtl_hw_start_8125a_2(struct rtl8169_private *tp)
3635 {
3636         static const struct ephy_info e_info_8125a_2[] = {
3637                 { 0x04, 0xffff, 0xd000 },
3638                 { 0x0a, 0xffff, 0x8653 },
3639                 { 0x23, 0xffff, 0xab66 },
3640                 { 0x20, 0xffff, 0x9455 },
3641                 { 0x21, 0xffff, 0x99ff },
3642                 { 0x29, 0xffff, 0xfe04 },
3643
3644                 { 0x44, 0xffff, 0xd000 },
3645                 { 0x4a, 0xffff, 0x8653 },
3646                 { 0x63, 0xffff, 0xab66 },
3647                 { 0x60, 0xffff, 0x9455 },
3648                 { 0x61, 0xffff, 0x99ff },
3649                 { 0x69, 0xffff, 0xfe04 },
3650         };
3651
3652         rtl_set_def_aspm_entry_latency(tp);
3653         rtl_ephy_init(tp, e_info_8125a_2);
3654         rtl_hw_start_8125_common(tp);
3655 }
3656
3657 static void rtl_hw_start_8125b(struct rtl8169_private *tp)
3658 {
3659         static const struct ephy_info e_info_8125b[] = {
3660                 { 0x0b, 0xffff, 0xa908 },
3661                 { 0x1e, 0xffff, 0x20eb },
3662                 { 0x4b, 0xffff, 0xa908 },
3663                 { 0x5e, 0xffff, 0x20eb },
3664                 { 0x22, 0x0030, 0x0020 },
3665                 { 0x62, 0x0030, 0x0020 },
3666         };
3667
3668         rtl_set_def_aspm_entry_latency(tp);
3669         rtl_ephy_init(tp, e_info_8125b);
3670         rtl_hw_start_8125_common(tp);
3671 }
3672
3673 static void rtl_hw_config(struct rtl8169_private *tp)
3674 {
3675         static const rtl_generic_fct hw_configs[] = {
3676                 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1,
3677                 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3,
3678                 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2,
3679                 [RTL_GIGA_MAC_VER_10] = NULL,
3680                 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168b,
3681                 [RTL_GIGA_MAC_VER_14] = rtl_hw_start_8401,
3682                 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b,
3683                 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1,
3684                 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1,
3685                 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2,
3686                 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_2,
3687                 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4,
3688                 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2,
3689                 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3,
3690                 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d,
3691                 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d,
3692                 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4,
3693                 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1,
3694                 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2,
3695                 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168d,
3696                 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1,
3697                 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1,
3698                 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2,
3699                 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1,
3700                 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1,
3701                 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402,
3702                 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411,
3703                 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106,
3704                 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1,
3705                 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2,
3706                 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2,
3707                 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2,
3708                 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1,
3709                 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1,
3710                 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3,
3711                 [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117,
3712                 [RTL_GIGA_MAC_VER_53] = rtl_hw_start_8117,
3713                 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2,
3714                 [RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b,
3715         };
3716
3717         if (hw_configs[tp->mac_version])
3718                 hw_configs[tp->mac_version](tp);
3719 }
3720
3721 static void rtl_hw_start_8125(struct rtl8169_private *tp)
3722 {
3723         int i;
3724
3725         /* disable interrupt coalescing */
3726         for (i = 0xa00; i < 0xb00; i += 4)
3727                 RTL_W32(tp, i, 0);
3728
3729         rtl_hw_config(tp);
3730 }
3731
3732 static void rtl_hw_start_8168(struct rtl8169_private *tp)
3733 {
3734         if (rtl_is_8168evl_up(tp))
3735                 RTL_W8(tp, MaxTxPacketSize, EarlySize);
3736         else
3737                 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
3738
3739         rtl_hw_config(tp);
3740
3741         /* disable interrupt coalescing */
3742         RTL_W16(tp, IntrMitigate, 0x0000);
3743 }
3744
3745 static void rtl_hw_start_8169(struct rtl8169_private *tp)
3746 {
3747         RTL_W8(tp, EarlyTxThres, NoEarlyTx);
3748
3749         tp->cp_cmd |= PCIMulRW;
3750
3751         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3752             tp->mac_version == RTL_GIGA_MAC_VER_03)
3753                 tp->cp_cmd |= EnAnaPLL;
3754
3755         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
3756
3757         rtl8169_set_magic_reg(tp);
3758
3759         /* disable interrupt coalescing */
3760         RTL_W16(tp, IntrMitigate, 0x0000);
3761 }
3762
3763 static void rtl_hw_start(struct  rtl8169_private *tp)
3764 {
3765         rtl_unlock_config_regs(tp);
3766         /* disable aspm and clock request before ephy access */
3767         rtl_hw_aspm_clkreq_enable(tp, false);
3768         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
3769
3770         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3771                 rtl_hw_start_8169(tp);
3772         else if (rtl_is_8125(tp))
3773                 rtl_hw_start_8125(tp);
3774         else
3775                 rtl_hw_start_8168(tp);
3776
3777         rtl_enable_exit_l1(tp);
3778         rtl_hw_aspm_clkreq_enable(tp, true);
3779         rtl_set_rx_max_size(tp);
3780         rtl_set_rx_tx_desc_registers(tp);
3781         rtl_lock_config_regs(tp);
3782
3783         rtl_jumbo_config(tp);
3784
3785         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3786         rtl_pci_commit(tp);
3787
3788         RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
3789         rtl_init_rxcfg(tp);
3790         rtl_set_tx_config_registers(tp);
3791         rtl_set_rx_config_features(tp, tp->dev->features);
3792         rtl_set_rx_mode(tp->dev);
3793         rtl_irq_enable(tp);
3794 }
3795
3796 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
3797 {
3798         struct rtl8169_private *tp = netdev_priv(dev);
3799
3800         dev->mtu = new_mtu;
3801         netdev_update_features(dev);
3802         rtl_jumbo_config(tp);
3803
3804         switch (tp->mac_version) {
3805         case RTL_GIGA_MAC_VER_61:
3806         case RTL_GIGA_MAC_VER_63:
3807                 rtl8125_set_eee_txidle_timer(tp);
3808                 break;
3809         default:
3810                 break;
3811         }
3812
3813         return 0;
3814 }
3815
3816 static void rtl8169_mark_to_asic(struct RxDesc *desc)
3817 {
3818         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
3819
3820         desc->opts2 = 0;
3821         /* Force memory writes to complete before releasing descriptor */
3822         dma_wmb();
3823         WRITE_ONCE(desc->opts1, cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE));
3824 }
3825
3826 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
3827                                           struct RxDesc *desc)
3828 {
3829         struct device *d = tp_to_dev(tp);
3830         int node = dev_to_node(d);
3831         dma_addr_t mapping;
3832         struct page *data;
3833
3834         data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE));
3835         if (!data)
3836                 return NULL;
3837
3838         mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
3839         if (unlikely(dma_mapping_error(d, mapping))) {
3840                 netdev_err(tp->dev, "Failed to map RX DMA!\n");
3841                 __free_pages(data, get_order(R8169_RX_BUF_SIZE));
3842                 return NULL;
3843         }
3844
3845         desc->addr = cpu_to_le64(mapping);
3846         rtl8169_mark_to_asic(desc);
3847
3848         return data;
3849 }
3850
3851 static void rtl8169_rx_clear(struct rtl8169_private *tp)
3852 {
3853         int i;
3854
3855         for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) {
3856                 dma_unmap_page(tp_to_dev(tp),
3857                                le64_to_cpu(tp->RxDescArray[i].addr),
3858                                R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
3859                 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE));
3860                 tp->Rx_databuff[i] = NULL;
3861                 tp->RxDescArray[i].addr = 0;
3862                 tp->RxDescArray[i].opts1 = 0;
3863         }
3864 }
3865
3866 static int rtl8169_rx_fill(struct rtl8169_private *tp)
3867 {
3868         int i;
3869
3870         for (i = 0; i < NUM_RX_DESC; i++) {
3871                 struct page *data;
3872
3873                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
3874                 if (!data) {
3875                         rtl8169_rx_clear(tp);
3876                         return -ENOMEM;
3877                 }
3878                 tp->Rx_databuff[i] = data;
3879         }
3880
3881         /* mark as last descriptor in the ring */
3882         tp->RxDescArray[NUM_RX_DESC - 1].opts1 |= cpu_to_le32(RingEnd);
3883
3884         return 0;
3885 }
3886
3887 static int rtl8169_init_ring(struct rtl8169_private *tp)
3888 {
3889         rtl8169_init_ring_indexes(tp);
3890
3891         memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
3892         memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
3893
3894         return rtl8169_rx_fill(tp);
3895 }
3896
3897 static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int entry)
3898 {
3899         struct ring_info *tx_skb = tp->tx_skb + entry;
3900         struct TxDesc *desc = tp->TxDescArray + entry;
3901
3902         dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), tx_skb->len,
3903                          DMA_TO_DEVICE);
3904         memset(desc, 0, sizeof(*desc));
3905         memset(tx_skb, 0, sizeof(*tx_skb));
3906 }
3907
3908 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
3909                                    unsigned int n)
3910 {
3911         unsigned int i;
3912
3913         for (i = 0; i < n; i++) {
3914                 unsigned int entry = (start + i) % NUM_TX_DESC;
3915                 struct ring_info *tx_skb = tp->tx_skb + entry;
3916                 unsigned int len = tx_skb->len;
3917
3918                 if (len) {
3919                         struct sk_buff *skb = tx_skb->skb;
3920
3921                         rtl8169_unmap_tx_skb(tp, entry);
3922                         if (skb)
3923                                 dev_consume_skb_any(skb);
3924                 }
3925         }
3926 }
3927
3928 static void rtl8169_tx_clear(struct rtl8169_private *tp)
3929 {
3930         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
3931         netdev_reset_queue(tp->dev);
3932 }
3933
3934 static void rtl8169_cleanup(struct rtl8169_private *tp)
3935 {
3936         napi_disable(&tp->napi);
3937
3938         /* Give a racing hard_start_xmit a few cycles to complete. */
3939         synchronize_net();
3940
3941         /* Disable interrupts */
3942         rtl8169_irq_mask_and_ack(tp);
3943
3944         rtl_rx_close(tp);
3945
3946         switch (tp->mac_version) {
3947         case RTL_GIGA_MAC_VER_28:
3948         case RTL_GIGA_MAC_VER_31:
3949                 rtl_loop_wait_low(tp, &rtl_npq_cond, 20, 2000);
3950                 break;
3951         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
3952                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
3953                 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
3954                 break;
3955         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
3956                 rtl_enable_rxdvgate(tp);
3957                 fsleep(2000);
3958                 break;
3959         default:
3960                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
3961                 fsleep(100);
3962                 break;
3963         }
3964
3965         rtl_hw_reset(tp);
3966
3967         rtl8169_tx_clear(tp);
3968         rtl8169_init_ring_indexes(tp);
3969 }
3970
3971 static void rtl_reset_work(struct rtl8169_private *tp)
3972 {
3973         int i;
3974
3975         netif_stop_queue(tp->dev);
3976
3977         rtl8169_cleanup(tp);
3978
3979         for (i = 0; i < NUM_RX_DESC; i++)
3980                 rtl8169_mark_to_asic(tp->RxDescArray + i);
3981
3982         napi_enable(&tp->napi);
3983         rtl_hw_start(tp);
3984 }
3985
3986 static void rtl8169_tx_timeout(struct net_device *dev, unsigned int txqueue)
3987 {
3988         struct rtl8169_private *tp = netdev_priv(dev);
3989
3990         rtl_schedule_task(tp, RTL_FLAG_TASK_TX_TIMEOUT);
3991 }
3992
3993 static int rtl8169_tx_map(struct rtl8169_private *tp, const u32 *opts, u32 len,
3994                           void *addr, unsigned int entry, bool desc_own)
3995 {
3996         struct TxDesc *txd = tp->TxDescArray + entry;
3997         struct device *d = tp_to_dev(tp);
3998         dma_addr_t mapping;
3999         u32 opts1;
4000         int ret;
4001
4002         mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
4003         ret = dma_mapping_error(d, mapping);
4004         if (unlikely(ret)) {
4005                 if (net_ratelimit())
4006                         netdev_err(tp->dev, "Failed to map TX data!\n");
4007                 return ret;
4008         }
4009
4010         txd->addr = cpu_to_le64(mapping);
4011         txd->opts2 = cpu_to_le32(opts[1]);
4012
4013         opts1 = opts[0] | len;
4014         if (entry == NUM_TX_DESC - 1)
4015                 opts1 |= RingEnd;
4016         if (desc_own)
4017                 opts1 |= DescOwn;
4018         txd->opts1 = cpu_to_le32(opts1);
4019
4020         tp->tx_skb[entry].len = len;
4021
4022         return 0;
4023 }
4024
4025 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4026                               const u32 *opts, unsigned int entry)
4027 {
4028         struct skb_shared_info *info = skb_shinfo(skb);
4029         unsigned int cur_frag;
4030
4031         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4032                 const skb_frag_t *frag = info->frags + cur_frag;
4033                 void *addr = skb_frag_address(frag);
4034                 u32 len = skb_frag_size(frag);
4035
4036                 entry = (entry + 1) % NUM_TX_DESC;
4037
4038                 if (unlikely(rtl8169_tx_map(tp, opts, len, addr, entry, true)))
4039                         goto err_out;
4040         }
4041
4042         return 0;
4043
4044 err_out:
4045         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
4046         return -EIO;
4047 }
4048
4049 static bool rtl_skb_is_udp(struct sk_buff *skb)
4050 {
4051         int no = skb_network_offset(skb);
4052         struct ipv6hdr *i6h, _i6h;
4053         struct iphdr *ih, _ih;
4054
4055         switch (vlan_get_protocol(skb)) {
4056         case htons(ETH_P_IP):
4057                 ih = skb_header_pointer(skb, no, sizeof(_ih), &_ih);
4058                 return ih && ih->protocol == IPPROTO_UDP;
4059         case htons(ETH_P_IPV6):
4060                 i6h = skb_header_pointer(skb, no, sizeof(_i6h), &_i6h);
4061                 return i6h && i6h->nexthdr == IPPROTO_UDP;
4062         default:
4063                 return false;
4064         }
4065 }
4066
4067 #define RTL_MIN_PATCH_LEN       47
4068
4069 /* see rtl8125_get_patch_pad_len() in r8125 vendor driver */
4070 static unsigned int rtl8125_quirk_udp_padto(struct rtl8169_private *tp,
4071                                             struct sk_buff *skb)
4072 {
4073         unsigned int padto = 0, len = skb->len;
4074
4075         if (rtl_is_8125(tp) && len < 128 + RTL_MIN_PATCH_LEN &&
4076             rtl_skb_is_udp(skb) && skb_transport_header_was_set(skb)) {
4077                 unsigned int trans_data_len = skb_tail_pointer(skb) -
4078                                               skb_transport_header(skb);
4079
4080                 if (trans_data_len >= offsetof(struct udphdr, len) &&
4081                     trans_data_len < RTL_MIN_PATCH_LEN) {
4082                         u16 dest = ntohs(udp_hdr(skb)->dest);
4083
4084                         /* dest is a standard PTP port */
4085                         if (dest == 319 || dest == 320)
4086                                 padto = len + RTL_MIN_PATCH_LEN - trans_data_len;
4087                 }
4088
4089                 if (trans_data_len < sizeof(struct udphdr))
4090                         padto = max_t(unsigned int, padto,
4091                                       len + sizeof(struct udphdr) - trans_data_len);
4092         }
4093
4094         return padto;
4095 }
4096
4097 static unsigned int rtl_quirk_packet_padto(struct rtl8169_private *tp,
4098                                            struct sk_buff *skb)
4099 {
4100         unsigned int padto;
4101
4102         padto = rtl8125_quirk_udp_padto(tp, skb);
4103
4104         switch (tp->mac_version) {
4105         case RTL_GIGA_MAC_VER_34:
4106         case RTL_GIGA_MAC_VER_61:
4107         case RTL_GIGA_MAC_VER_63:
4108                 padto = max_t(unsigned int, padto, ETH_ZLEN);
4109                 break;
4110         default:
4111                 break;
4112         }
4113
4114         return padto;
4115 }
4116
4117 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts)
4118 {
4119         u32 mss = skb_shinfo(skb)->gso_size;
4120
4121         if (mss) {
4122                 opts[0] |= TD_LSO;
4123                 opts[0] |= mss << TD0_MSS_SHIFT;
4124         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4125                 const struct iphdr *ip = ip_hdr(skb);
4126
4127                 if (ip->protocol == IPPROTO_TCP)
4128                         opts[0] |= TD0_IP_CS | TD0_TCP_CS;
4129                 else if (ip->protocol == IPPROTO_UDP)
4130                         opts[0] |= TD0_IP_CS | TD0_UDP_CS;
4131                 else
4132                         WARN_ON_ONCE(1);
4133         }
4134 }
4135
4136 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
4137                                 struct sk_buff *skb, u32 *opts)
4138 {
4139         struct skb_shared_info *shinfo = skb_shinfo(skb);
4140         u32 mss = shinfo->gso_size;
4141
4142         if (mss) {
4143                 if (shinfo->gso_type & SKB_GSO_TCPV4) {
4144                         opts[0] |= TD1_GTSENV4;
4145                 } else if (shinfo->gso_type & SKB_GSO_TCPV6) {
4146                         if (skb_cow_head(skb, 0))
4147                                 return false;
4148
4149                         tcp_v6_gso_csum_prep(skb);
4150                         opts[0] |= TD1_GTSENV6;
4151                 } else {
4152                         WARN_ON_ONCE(1);
4153                 }
4154
4155                 opts[0] |= skb_transport_offset(skb) << GTTCPHO_SHIFT;
4156                 opts[1] |= mss << TD1_MSS_SHIFT;
4157         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4158                 u8 ip_protocol;
4159
4160                 switch (vlan_get_protocol(skb)) {
4161                 case htons(ETH_P_IP):
4162                         opts[1] |= TD1_IPv4_CS;
4163                         ip_protocol = ip_hdr(skb)->protocol;
4164                         break;
4165
4166                 case htons(ETH_P_IPV6):
4167                         opts[1] |= TD1_IPv6_CS;
4168                         ip_protocol = ipv6_hdr(skb)->nexthdr;
4169                         break;
4170
4171                 default:
4172                         ip_protocol = IPPROTO_RAW;
4173                         break;
4174                 }
4175
4176                 if (ip_protocol == IPPROTO_TCP)
4177                         opts[1] |= TD1_TCP_CS;
4178                 else if (ip_protocol == IPPROTO_UDP)
4179                         opts[1] |= TD1_UDP_CS;
4180                 else
4181                         WARN_ON_ONCE(1);
4182
4183                 opts[1] |= skb_transport_offset(skb) << TCPHO_SHIFT;
4184         } else {
4185                 unsigned int padto = rtl_quirk_packet_padto(tp, skb);
4186
4187                 /* skb_padto would free the skb on error */
4188                 return !__skb_put_padto(skb, padto, false);
4189         }
4190
4191         return true;
4192 }
4193
4194 static unsigned int rtl_tx_slots_avail(struct rtl8169_private *tp)
4195 {
4196         return READ_ONCE(tp->dirty_tx) + NUM_TX_DESC - READ_ONCE(tp->cur_tx);
4197 }
4198
4199 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */
4200 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
4201 {
4202         switch (tp->mac_version) {
4203         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
4204         case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
4205                 return false;
4206         default:
4207                 return true;
4208         }
4209 }
4210
4211 static void rtl8169_doorbell(struct rtl8169_private *tp)
4212 {
4213         if (rtl_is_8125(tp))
4214                 RTL_W16(tp, TxPoll_8125, BIT(0));
4215         else
4216                 RTL_W8(tp, TxPoll, NPQ);
4217 }
4218
4219 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4220                                       struct net_device *dev)
4221 {
4222         unsigned int frags = skb_shinfo(skb)->nr_frags;
4223         struct rtl8169_private *tp = netdev_priv(dev);
4224         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
4225         struct TxDesc *txd_first, *txd_last;
4226         bool stop_queue, door_bell;
4227         u32 opts[2];
4228
4229         if (unlikely(!rtl_tx_slots_avail(tp))) {
4230                 if (net_ratelimit())
4231                         netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
4232                 goto err_stop_0;
4233         }
4234
4235         opts[1] = rtl8169_tx_vlan_tag(skb);
4236         opts[0] = 0;
4237
4238         if (!rtl_chip_supports_csum_v2(tp))
4239                 rtl8169_tso_csum_v1(skb, opts);
4240         else if (!rtl8169_tso_csum_v2(tp, skb, opts))
4241                 goto err_dma_0;
4242
4243         if (unlikely(rtl8169_tx_map(tp, opts, skb_headlen(skb), skb->data,
4244                                     entry, false)))
4245                 goto err_dma_0;
4246
4247         txd_first = tp->TxDescArray + entry;
4248
4249         if (frags) {
4250                 if (rtl8169_xmit_frags(tp, skb, opts, entry))
4251                         goto err_dma_1;
4252                 entry = (entry + frags) % NUM_TX_DESC;
4253         }
4254
4255         txd_last = tp->TxDescArray + entry;
4256         txd_last->opts1 |= cpu_to_le32(LastFrag);
4257         tp->tx_skb[entry].skb = skb;
4258
4259         skb_tx_timestamp(skb);
4260
4261         /* Force memory writes to complete before releasing descriptor */
4262         dma_wmb();
4263
4264         door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more());
4265
4266         txd_first->opts1 |= cpu_to_le32(DescOwn | FirstFrag);
4267
4268         /* rtl_tx needs to see descriptor changes before updated tp->cur_tx */
4269         smp_wmb();
4270
4271         WRITE_ONCE(tp->cur_tx, tp->cur_tx + frags + 1);
4272
4273         stop_queue = !netif_subqueue_maybe_stop(dev, 0, rtl_tx_slots_avail(tp),
4274                                                 R8169_TX_STOP_THRS,
4275                                                 R8169_TX_START_THRS);
4276         if (door_bell || stop_queue)
4277                 rtl8169_doorbell(tp);
4278
4279         return NETDEV_TX_OK;
4280
4281 err_dma_1:
4282         rtl8169_unmap_tx_skb(tp, entry);
4283 err_dma_0:
4284         dev_kfree_skb_any(skb);
4285         dev->stats.tx_dropped++;
4286         return NETDEV_TX_OK;
4287
4288 err_stop_0:
4289         netif_stop_queue(dev);
4290         dev->stats.tx_dropped++;
4291         return NETDEV_TX_BUSY;
4292 }
4293
4294 static unsigned int rtl_last_frag_len(struct sk_buff *skb)
4295 {
4296         struct skb_shared_info *info = skb_shinfo(skb);
4297         unsigned int nr_frags = info->nr_frags;
4298
4299         if (!nr_frags)
4300                 return UINT_MAX;
4301
4302         return skb_frag_size(info->frags + nr_frags - 1);
4303 }
4304
4305 /* Workaround for hw issues with TSO on RTL8168evl */
4306 static netdev_features_t rtl8168evl_fix_tso(struct sk_buff *skb,
4307                                             netdev_features_t features)
4308 {
4309         /* IPv4 header has options field */
4310         if (vlan_get_protocol(skb) == htons(ETH_P_IP) &&
4311             ip_hdrlen(skb) > sizeof(struct iphdr))
4312                 features &= ~NETIF_F_ALL_TSO;
4313
4314         /* IPv4 TCP header has options field */
4315         else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4 &&
4316                  tcp_hdrlen(skb) > sizeof(struct tcphdr))
4317                 features &= ~NETIF_F_ALL_TSO;
4318
4319         else if (rtl_last_frag_len(skb) <= 6)
4320                 features &= ~NETIF_F_ALL_TSO;
4321
4322         return features;
4323 }
4324
4325 static netdev_features_t rtl8169_features_check(struct sk_buff *skb,
4326                                                 struct net_device *dev,
4327                                                 netdev_features_t features)
4328 {
4329         struct rtl8169_private *tp = netdev_priv(dev);
4330
4331         if (skb_is_gso(skb)) {
4332                 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4333                         features = rtl8168evl_fix_tso(skb, features);
4334
4335                 if (skb_transport_offset(skb) > GTTCPHO_MAX &&
4336                     rtl_chip_supports_csum_v2(tp))
4337                         features &= ~NETIF_F_ALL_TSO;
4338         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4339                 /* work around hw bug on some chip versions */
4340                 if (skb->len < ETH_ZLEN)
4341                         features &= ~NETIF_F_CSUM_MASK;
4342
4343                 if (rtl_quirk_packet_padto(tp, skb))
4344                         features &= ~NETIF_F_CSUM_MASK;
4345
4346                 if (skb_transport_offset(skb) > TCPHO_MAX &&
4347                     rtl_chip_supports_csum_v2(tp))
4348                         features &= ~NETIF_F_CSUM_MASK;
4349         }
4350
4351         return vlan_features_check(skb, features);
4352 }
4353
4354 static void rtl8169_pcierr_interrupt(struct net_device *dev)
4355 {
4356         struct rtl8169_private *tp = netdev_priv(dev);
4357         struct pci_dev *pdev = tp->pci_dev;
4358         int pci_status_errs;
4359         u16 pci_cmd;
4360
4361         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4362
4363         pci_status_errs = pci_status_get_and_clear_errors(pdev);
4364
4365         if (net_ratelimit())
4366                 netdev_err(dev, "PCI error (cmd = 0x%04x, status_errs = 0x%04x)\n",
4367                            pci_cmd, pci_status_errs);
4368
4369         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
4370 }
4371
4372 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp,
4373                    int budget)
4374 {
4375         unsigned int dirty_tx, bytes_compl = 0, pkts_compl = 0;
4376         struct sk_buff *skb;
4377
4378         dirty_tx = tp->dirty_tx;
4379
4380         while (READ_ONCE(tp->cur_tx) != dirty_tx) {
4381                 unsigned int entry = dirty_tx % NUM_TX_DESC;
4382                 u32 status;
4383
4384                 status = le32_to_cpu(READ_ONCE(tp->TxDescArray[entry].opts1));
4385                 if (status & DescOwn)
4386                         break;
4387
4388                 skb = tp->tx_skb[entry].skb;
4389                 rtl8169_unmap_tx_skb(tp, entry);
4390
4391                 if (skb) {
4392                         pkts_compl++;
4393                         bytes_compl += skb->len;
4394                         napi_consume_skb(skb, budget);
4395                 }
4396                 dirty_tx++;
4397         }
4398
4399         if (tp->dirty_tx != dirty_tx) {
4400                 dev_sw_netstats_tx_add(dev, pkts_compl, bytes_compl);
4401                 WRITE_ONCE(tp->dirty_tx, dirty_tx);
4402
4403                 netif_subqueue_completed_wake(dev, 0, pkts_compl, bytes_compl,
4404                                               rtl_tx_slots_avail(tp),
4405                                               R8169_TX_START_THRS);
4406                 /*
4407                  * 8168 hack: TxPoll requests are lost when the Tx packets are
4408                  * too close. Let's kick an extra TxPoll request when a burst
4409                  * of start_xmit activity is detected (if it is not detected,
4410                  * it is slow enough). -- FR
4411                  * If skb is NULL then we come here again once a tx irq is
4412                  * triggered after the last fragment is marked transmitted.
4413                  */
4414                 if (READ_ONCE(tp->cur_tx) != dirty_tx && skb)
4415                         rtl8169_doorbell(tp);
4416         }
4417 }
4418
4419 static inline int rtl8169_fragmented_frame(u32 status)
4420 {
4421         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4422 }
4423
4424 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
4425 {
4426         u32 status = opts1 & (RxProtoMask | RxCSFailMask);
4427
4428         if (status == RxProtoTCP || status == RxProtoUDP)
4429                 skb->ip_summed = CHECKSUM_UNNECESSARY;
4430         else
4431                 skb_checksum_none_assert(skb);
4432 }
4433
4434 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, int budget)
4435 {
4436         struct device *d = tp_to_dev(tp);
4437         int count;
4438
4439         for (count = 0; count < budget; count++, tp->cur_rx++) {
4440                 unsigned int pkt_size, entry = tp->cur_rx % NUM_RX_DESC;
4441                 struct RxDesc *desc = tp->RxDescArray + entry;
4442                 struct sk_buff *skb;
4443                 const void *rx_buf;
4444                 dma_addr_t addr;
4445                 u32 status;
4446
4447                 status = le32_to_cpu(READ_ONCE(desc->opts1));
4448                 if (status & DescOwn)
4449                         break;
4450
4451                 /* This barrier is needed to keep us from reading
4452                  * any other fields out of the Rx descriptor until
4453                  * we know the status of DescOwn
4454                  */
4455                 dma_rmb();
4456
4457                 if (unlikely(status & RxRES)) {
4458                         if (net_ratelimit())
4459                                 netdev_warn(dev, "Rx ERROR. status = %08x\n",
4460                                             status);
4461                         dev->stats.rx_errors++;
4462                         if (status & (RxRWT | RxRUNT))
4463                                 dev->stats.rx_length_errors++;
4464                         if (status & RxCRC)
4465                                 dev->stats.rx_crc_errors++;
4466
4467                         if (!(dev->features & NETIF_F_RXALL))
4468                                 goto release_descriptor;
4469                         else if (status & RxRWT || !(status & (RxRUNT | RxCRC)))
4470                                 goto release_descriptor;
4471                 }
4472
4473                 pkt_size = status & GENMASK(13, 0);
4474                 if (likely(!(dev->features & NETIF_F_RXFCS)))
4475                         pkt_size -= ETH_FCS_LEN;
4476
4477                 /* The driver does not support incoming fragmented frames.
4478                  * They are seen as a symptom of over-mtu sized frames.
4479                  */
4480                 if (unlikely(rtl8169_fragmented_frame(status))) {
4481                         dev->stats.rx_dropped++;
4482                         dev->stats.rx_length_errors++;
4483                         goto release_descriptor;
4484                 }
4485
4486                 skb = napi_alloc_skb(&tp->napi, pkt_size);
4487                 if (unlikely(!skb)) {
4488                         dev->stats.rx_dropped++;
4489                         goto release_descriptor;
4490                 }
4491
4492                 addr = le64_to_cpu(desc->addr);
4493                 rx_buf = page_address(tp->Rx_databuff[entry]);
4494
4495                 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
4496                 prefetch(rx_buf);
4497                 skb_copy_to_linear_data(skb, rx_buf, pkt_size);
4498                 skb->tail += pkt_size;
4499                 skb->len = pkt_size;
4500                 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
4501
4502                 rtl8169_rx_csum(skb, status);
4503                 skb->protocol = eth_type_trans(skb, dev);
4504
4505                 rtl8169_rx_vlan_tag(desc, skb);
4506
4507                 if (skb->pkt_type == PACKET_MULTICAST)
4508                         dev->stats.multicast++;
4509
4510                 napi_gro_receive(&tp->napi, skb);
4511
4512                 dev_sw_netstats_rx_add(dev, pkt_size);
4513 release_descriptor:
4514                 rtl8169_mark_to_asic(desc);
4515         }
4516
4517         return count;
4518 }
4519
4520 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
4521 {
4522         struct rtl8169_private *tp = dev_instance;
4523         u32 status = rtl_get_events(tp);
4524
4525         if ((status & 0xffff) == 0xffff || !(status & tp->irq_mask))
4526                 return IRQ_NONE;
4527
4528         if (unlikely(status & SYSErr)) {
4529                 rtl8169_pcierr_interrupt(tp->dev);
4530                 goto out;
4531         }
4532
4533         if (status & LinkChg)
4534                 phy_mac_interrupt(tp->phydev);
4535
4536         if (unlikely(status & RxFIFOOver &&
4537             tp->mac_version == RTL_GIGA_MAC_VER_11)) {
4538                 netif_stop_queue(tp->dev);
4539                 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
4540         }
4541
4542         if (napi_schedule_prep(&tp->napi)) {
4543                 rtl_irq_disable(tp);
4544                 __napi_schedule(&tp->napi);
4545         }
4546 out:
4547         rtl_ack_events(tp, status);
4548
4549         return IRQ_HANDLED;
4550 }
4551
4552 static void rtl_task(struct work_struct *work)
4553 {
4554         struct rtl8169_private *tp =
4555                 container_of(work, struct rtl8169_private, wk.work);
4556         int ret;
4557
4558         rtnl_lock();
4559
4560         if (!netif_running(tp->dev) ||
4561             !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
4562                 goto out_unlock;
4563
4564         if (test_and_clear_bit(RTL_FLAG_TASK_TX_TIMEOUT, tp->wk.flags)) {
4565                 /* if chip isn't accessible, reset bus to revive it */
4566                 if (RTL_R32(tp, TxConfig) == ~0) {
4567                         ret = pci_reset_bus(tp->pci_dev);
4568                         if (ret < 0) {
4569                                 netdev_err(tp->dev, "Can't reset secondary PCI bus, detach NIC\n");
4570                                 netif_device_detach(tp->dev);
4571                                 goto out_unlock;
4572                         }
4573                 }
4574
4575                 /* ASPM compatibility issues are a typical reason for tx timeouts */
4576                 ret = pci_disable_link_state(tp->pci_dev, PCIE_LINK_STATE_L1 |
4577                                                           PCIE_LINK_STATE_L0S);
4578                 if (!ret)
4579                         netdev_warn_once(tp->dev, "ASPM disabled on Tx timeout\n");
4580                 goto reset;
4581         }
4582
4583         if (test_and_clear_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags)) {
4584 reset:
4585                 rtl_reset_work(tp);
4586                 netif_wake_queue(tp->dev);
4587         }
4588 out_unlock:
4589         rtnl_unlock();
4590 }
4591
4592 static int rtl8169_poll(struct napi_struct *napi, int budget)
4593 {
4594         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
4595         struct net_device *dev = tp->dev;
4596         int work_done;
4597
4598         rtl_tx(dev, tp, budget);
4599
4600         work_done = rtl_rx(dev, tp, budget);
4601
4602         if (work_done < budget && napi_complete_done(napi, work_done))
4603                 rtl_irq_enable(tp);
4604
4605         return work_done;
4606 }
4607
4608 static void r8169_phylink_handler(struct net_device *ndev)
4609 {
4610         struct rtl8169_private *tp = netdev_priv(ndev);
4611         struct device *d = tp_to_dev(tp);
4612
4613         if (netif_carrier_ok(ndev)) {
4614                 rtl_link_chg_patch(tp);
4615                 pm_request_resume(d);
4616                 netif_wake_queue(tp->dev);
4617         } else {
4618                 /* In few cases rx is broken after link-down otherwise */
4619                 if (rtl_is_8125(tp))
4620                         rtl_reset_work(tp);
4621                 pm_runtime_idle(d);
4622         }
4623
4624         phy_print_status(tp->phydev);
4625 }
4626
4627 static int r8169_phy_connect(struct rtl8169_private *tp)
4628 {
4629         struct phy_device *phydev = tp->phydev;
4630         phy_interface_t phy_mode;
4631         int ret;
4632
4633         phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
4634                    PHY_INTERFACE_MODE_MII;
4635
4636         ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
4637                                  phy_mode);
4638         if (ret)
4639                 return ret;
4640
4641         if (!tp->supports_gmii)
4642                 phy_set_max_speed(phydev, SPEED_100);
4643
4644         phy_attached_info(phydev);
4645
4646         return 0;
4647 }
4648
4649 static void rtl8169_down(struct rtl8169_private *tp)
4650 {
4651         /* Clear all task flags */
4652         bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
4653
4654         phy_stop(tp->phydev);
4655
4656         rtl8169_update_counters(tp);
4657
4658         pci_clear_master(tp->pci_dev);
4659         rtl_pci_commit(tp);
4660
4661         rtl8169_cleanup(tp);
4662         rtl_disable_exit_l1(tp);
4663         rtl_prepare_power_down(tp);
4664
4665         if (tp->dash_type != RTL_DASH_NONE)
4666                 rtl8168_driver_stop(tp);
4667 }
4668
4669 static void rtl8169_up(struct rtl8169_private *tp)
4670 {
4671         if (tp->dash_type != RTL_DASH_NONE)
4672                 rtl8168_driver_start(tp);
4673
4674         pci_set_master(tp->pci_dev);
4675         phy_init_hw(tp->phydev);
4676         phy_resume(tp->phydev);
4677         rtl8169_init_phy(tp);
4678         napi_enable(&tp->napi);
4679         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
4680         rtl_reset_work(tp);
4681
4682         phy_start(tp->phydev);
4683 }
4684
4685 static int rtl8169_close(struct net_device *dev)
4686 {
4687         struct rtl8169_private *tp = netdev_priv(dev);
4688         struct pci_dev *pdev = tp->pci_dev;
4689
4690         pm_runtime_get_sync(&pdev->dev);
4691
4692         netif_stop_queue(dev);
4693         rtl8169_down(tp);
4694         rtl8169_rx_clear(tp);
4695
4696         cancel_work_sync(&tp->wk.work);
4697
4698         free_irq(tp->irq, tp);
4699
4700         phy_disconnect(tp->phydev);
4701
4702         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4703                           tp->RxPhyAddr);
4704         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4705                           tp->TxPhyAddr);
4706         tp->TxDescArray = NULL;
4707         tp->RxDescArray = NULL;
4708
4709         pm_runtime_put_sync(&pdev->dev);
4710
4711         return 0;
4712 }
4713
4714 #ifdef CONFIG_NET_POLL_CONTROLLER
4715 static void rtl8169_netpoll(struct net_device *dev)
4716 {
4717         struct rtl8169_private *tp = netdev_priv(dev);
4718
4719         rtl8169_interrupt(tp->irq, tp);
4720 }
4721 #endif
4722
4723 static int rtl_open(struct net_device *dev)
4724 {
4725         struct rtl8169_private *tp = netdev_priv(dev);
4726         struct pci_dev *pdev = tp->pci_dev;
4727         unsigned long irqflags;
4728         int retval = -ENOMEM;
4729
4730         pm_runtime_get_sync(&pdev->dev);
4731
4732         /*
4733          * Rx and Tx descriptors needs 256 bytes alignment.
4734          * dma_alloc_coherent provides more.
4735          */
4736         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
4737                                              &tp->TxPhyAddr, GFP_KERNEL);
4738         if (!tp->TxDescArray)
4739                 goto out;
4740
4741         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
4742                                              &tp->RxPhyAddr, GFP_KERNEL);
4743         if (!tp->RxDescArray)
4744                 goto err_free_tx_0;
4745
4746         retval = rtl8169_init_ring(tp);
4747         if (retval < 0)
4748                 goto err_free_rx_1;
4749
4750         rtl_request_firmware(tp);
4751
4752         irqflags = pci_dev_msi_enabled(pdev) ? IRQF_NO_THREAD : IRQF_SHARED;
4753         retval = request_irq(tp->irq, rtl8169_interrupt, irqflags, dev->name, tp);
4754         if (retval < 0)
4755                 goto err_release_fw_2;
4756
4757         retval = r8169_phy_connect(tp);
4758         if (retval)
4759                 goto err_free_irq;
4760
4761         rtl8169_up(tp);
4762         rtl8169_init_counter_offsets(tp);
4763         netif_start_queue(dev);
4764 out:
4765         pm_runtime_put_sync(&pdev->dev);
4766
4767         return retval;
4768
4769 err_free_irq:
4770         free_irq(tp->irq, tp);
4771 err_release_fw_2:
4772         rtl_release_firmware(tp);
4773         rtl8169_rx_clear(tp);
4774 err_free_rx_1:
4775         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4776                           tp->RxPhyAddr);
4777         tp->RxDescArray = NULL;
4778 err_free_tx_0:
4779         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4780                           tp->TxPhyAddr);
4781         tp->TxDescArray = NULL;
4782         goto out;
4783 }
4784
4785 static void
4786 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
4787 {
4788         struct rtl8169_private *tp = netdev_priv(dev);
4789         struct pci_dev *pdev = tp->pci_dev;
4790         struct rtl8169_counters *counters = tp->counters;
4791
4792         pm_runtime_get_noresume(&pdev->dev);
4793
4794         netdev_stats_to_stats64(stats, &dev->stats);
4795         dev_fetch_sw_netstats(stats, dev->tstats);
4796
4797         /*
4798          * Fetch additional counter values missing in stats collected by driver
4799          * from tally counters.
4800          */
4801         if (pm_runtime_active(&pdev->dev))
4802                 rtl8169_update_counters(tp);
4803
4804         /*
4805          * Subtract values fetched during initalization.
4806          * See rtl8169_init_counter_offsets for a description why we do that.
4807          */
4808         stats->tx_errors = le64_to_cpu(counters->tx_errors) -
4809                 le64_to_cpu(tp->tc_offset.tx_errors);
4810         stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
4811                 le32_to_cpu(tp->tc_offset.tx_multi_collision);
4812         stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
4813                 le16_to_cpu(tp->tc_offset.tx_aborted);
4814         stats->rx_missed_errors = le16_to_cpu(counters->rx_missed) -
4815                 le16_to_cpu(tp->tc_offset.rx_missed);
4816
4817         pm_runtime_put_noidle(&pdev->dev);
4818 }
4819
4820 static void rtl8169_net_suspend(struct rtl8169_private *tp)
4821 {
4822         netif_device_detach(tp->dev);
4823
4824         if (netif_running(tp->dev))
4825                 rtl8169_down(tp);
4826 }
4827
4828 static int rtl8169_runtime_resume(struct device *dev)
4829 {
4830         struct rtl8169_private *tp = dev_get_drvdata(dev);
4831
4832         rtl_rar_set(tp, tp->dev->dev_addr);
4833         __rtl8169_set_wol(tp, tp->saved_wolopts);
4834
4835         if (tp->TxDescArray)
4836                 rtl8169_up(tp);
4837
4838         netif_device_attach(tp->dev);
4839
4840         return 0;
4841 }
4842
4843 static int rtl8169_suspend(struct device *device)
4844 {
4845         struct rtl8169_private *tp = dev_get_drvdata(device);
4846
4847         rtnl_lock();
4848         rtl8169_net_suspend(tp);
4849         if (!device_may_wakeup(tp_to_dev(tp)))
4850                 clk_disable_unprepare(tp->clk);
4851         rtnl_unlock();
4852
4853         return 0;
4854 }
4855
4856 static int rtl8169_resume(struct device *device)
4857 {
4858         struct rtl8169_private *tp = dev_get_drvdata(device);
4859
4860         if (!device_may_wakeup(tp_to_dev(tp)))
4861                 clk_prepare_enable(tp->clk);
4862
4863         /* Reportedly at least Asus X453MA truncates packets otherwise */
4864         if (tp->mac_version == RTL_GIGA_MAC_VER_37)
4865                 rtl_init_rxcfg(tp);
4866
4867         return rtl8169_runtime_resume(device);
4868 }
4869
4870 static int rtl8169_runtime_suspend(struct device *device)
4871 {
4872         struct rtl8169_private *tp = dev_get_drvdata(device);
4873
4874         if (!tp->TxDescArray) {
4875                 netif_device_detach(tp->dev);
4876                 return 0;
4877         }
4878
4879         rtnl_lock();
4880         __rtl8169_set_wol(tp, WAKE_PHY);
4881         rtl8169_net_suspend(tp);
4882         rtnl_unlock();
4883
4884         return 0;
4885 }
4886
4887 static int rtl8169_runtime_idle(struct device *device)
4888 {
4889         struct rtl8169_private *tp = dev_get_drvdata(device);
4890
4891         if (tp->dash_enabled)
4892                 return -EBUSY;
4893
4894         if (!netif_running(tp->dev) || !netif_carrier_ok(tp->dev))
4895                 pm_schedule_suspend(device, 10000);
4896
4897         return -EBUSY;
4898 }
4899
4900 static const struct dev_pm_ops rtl8169_pm_ops = {
4901         SYSTEM_SLEEP_PM_OPS(rtl8169_suspend, rtl8169_resume)
4902         RUNTIME_PM_OPS(rtl8169_runtime_suspend, rtl8169_runtime_resume,
4903                        rtl8169_runtime_idle)
4904 };
4905
4906 static void rtl_shutdown(struct pci_dev *pdev)
4907 {
4908         struct rtl8169_private *tp = pci_get_drvdata(pdev);
4909
4910         rtnl_lock();
4911         rtl8169_net_suspend(tp);
4912         rtnl_unlock();
4913
4914         /* Restore original MAC address */
4915         rtl_rar_set(tp, tp->dev->perm_addr);
4916
4917         if (system_state == SYSTEM_POWER_OFF && !tp->dash_enabled) {
4918                 pci_wake_from_d3(pdev, tp->saved_wolopts);
4919                 pci_set_power_state(pdev, PCI_D3hot);
4920         }
4921 }
4922
4923 static void rtl_remove_one(struct pci_dev *pdev)
4924 {
4925         struct rtl8169_private *tp = pci_get_drvdata(pdev);
4926
4927         if (pci_dev_run_wake(pdev))
4928                 pm_runtime_get_noresume(&pdev->dev);
4929
4930         unregister_netdev(tp->dev);
4931
4932         if (tp->dash_type != RTL_DASH_NONE)
4933                 rtl8168_driver_stop(tp);
4934
4935         rtl_release_firmware(tp);
4936
4937         /* restore original MAC address */
4938         rtl_rar_set(tp, tp->dev->perm_addr);
4939 }
4940
4941 static const struct net_device_ops rtl_netdev_ops = {
4942         .ndo_open               = rtl_open,
4943         .ndo_stop               = rtl8169_close,
4944         .ndo_get_stats64        = rtl8169_get_stats64,
4945         .ndo_start_xmit         = rtl8169_start_xmit,
4946         .ndo_features_check     = rtl8169_features_check,
4947         .ndo_tx_timeout         = rtl8169_tx_timeout,
4948         .ndo_validate_addr      = eth_validate_addr,
4949         .ndo_change_mtu         = rtl8169_change_mtu,
4950         .ndo_fix_features       = rtl8169_fix_features,
4951         .ndo_set_features       = rtl8169_set_features,
4952         .ndo_set_mac_address    = rtl_set_mac_address,
4953         .ndo_eth_ioctl          = phy_do_ioctl_running,
4954         .ndo_set_rx_mode        = rtl_set_rx_mode,
4955 #ifdef CONFIG_NET_POLL_CONTROLLER
4956         .ndo_poll_controller    = rtl8169_netpoll,
4957 #endif
4958
4959 };
4960
4961 static void rtl_set_irq_mask(struct rtl8169_private *tp)
4962 {
4963         tp->irq_mask = RxOK | RxErr | TxOK | TxErr | LinkChg;
4964
4965         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
4966                 tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver;
4967         else if (tp->mac_version == RTL_GIGA_MAC_VER_11)
4968                 /* special workaround needed */
4969                 tp->irq_mask |= RxFIFOOver;
4970         else
4971                 tp->irq_mask |= RxOverflow;
4972 }
4973
4974 static int rtl_alloc_irq(struct rtl8169_private *tp)
4975 {
4976         unsigned int flags;
4977
4978         switch (tp->mac_version) {
4979         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
4980                 rtl_unlock_config_regs(tp);
4981                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
4982                 rtl_lock_config_regs(tp);
4983                 fallthrough;
4984         case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_17:
4985                 flags = PCI_IRQ_LEGACY;
4986                 break;
4987         default:
4988                 flags = PCI_IRQ_ALL_TYPES;
4989                 break;
4990         }
4991
4992         return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
4993 }
4994
4995 static void rtl_read_mac_address(struct rtl8169_private *tp,
4996                                  u8 mac_addr[ETH_ALEN])
4997 {
4998         /* Get MAC address */
4999         if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) {
5000                 u32 value;
5001
5002                 value = rtl_eri_read(tp, 0xe0);
5003                 put_unaligned_le32(value, mac_addr);
5004                 value = rtl_eri_read(tp, 0xe4);
5005                 put_unaligned_le16(value, mac_addr + 4);
5006         } else if (rtl_is_8125(tp)) {
5007                 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP);
5008         }
5009 }
5010
5011 DECLARE_RTL_COND(rtl_link_list_ready_cond)
5012 {
5013         return RTL_R8(tp, MCU) & LINK_LIST_RDY;
5014 }
5015
5016 static void r8168g_wait_ll_share_fifo_ready(struct rtl8169_private *tp)
5017 {
5018         rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42);
5019 }
5020
5021 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
5022 {
5023         struct rtl8169_private *tp = mii_bus->priv;
5024
5025         if (phyaddr > 0)
5026                 return -ENODEV;
5027
5028         return rtl_readphy(tp, phyreg);
5029 }
5030
5031 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
5032                                 int phyreg, u16 val)
5033 {
5034         struct rtl8169_private *tp = mii_bus->priv;
5035
5036         if (phyaddr > 0)
5037                 return -ENODEV;
5038
5039         rtl_writephy(tp, phyreg, val);
5040
5041         return 0;
5042 }
5043
5044 static int r8169_mdio_register(struct rtl8169_private *tp)
5045 {
5046         struct pci_dev *pdev = tp->pci_dev;
5047         struct mii_bus *new_bus;
5048         int ret;
5049
5050         new_bus = devm_mdiobus_alloc(&pdev->dev);
5051         if (!new_bus)
5052                 return -ENOMEM;
5053
5054         new_bus->name = "r8169";
5055         new_bus->priv = tp;
5056         new_bus->parent = &pdev->dev;
5057         new_bus->irq[0] = PHY_MAC_INTERRUPT;
5058         snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x-%x",
5059                  pci_domain_nr(pdev->bus), pci_dev_id(pdev));
5060
5061         new_bus->read = r8169_mdio_read_reg;
5062         new_bus->write = r8169_mdio_write_reg;
5063
5064         ret = devm_mdiobus_register(&pdev->dev, new_bus);
5065         if (ret)
5066                 return ret;
5067
5068         tp->phydev = mdiobus_get_phy(new_bus, 0);
5069         if (!tp->phydev) {
5070                 return -ENODEV;
5071         } else if (!tp->phydev->drv) {
5072                 /* Most chip versions fail with the genphy driver.
5073                  * Therefore ensure that the dedicated PHY driver is loaded.
5074                  */
5075                 dev_err(&pdev->dev, "no dedicated PHY driver found for PHY ID 0x%08x, maybe realtek.ko needs to be added to initramfs?\n",
5076                         tp->phydev->phy_id);
5077                 return -EUNATCH;
5078         }
5079
5080         tp->phydev->mac_managed_pm = true;
5081
5082         phy_support_asym_pause(tp->phydev);
5083
5084         /* PHY will be woken up in rtl_open() */
5085         phy_suspend(tp->phydev);
5086
5087         return 0;
5088 }
5089
5090 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
5091 {
5092         rtl_enable_rxdvgate(tp);
5093
5094         RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
5095         msleep(1);
5096         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5097
5098         r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
5099         r8168g_wait_ll_share_fifo_ready(tp);
5100
5101         r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15));
5102         r8168g_wait_ll_share_fifo_ready(tp);
5103 }
5104
5105 static void rtl_hw_init_8125(struct rtl8169_private *tp)
5106 {
5107         rtl_enable_rxdvgate(tp);
5108
5109         RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
5110         msleep(1);
5111         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5112
5113         r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
5114         r8168g_wait_ll_share_fifo_ready(tp);
5115
5116         r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0);
5117         r8168_mac_ocp_write(tp, 0xc0a6, 0x0150);
5118         r8168_mac_ocp_write(tp, 0xc01e, 0x5555);
5119         r8168g_wait_ll_share_fifo_ready(tp);
5120 }
5121
5122 static void rtl_hw_initialize(struct rtl8169_private *tp)
5123 {
5124         switch (tp->mac_version) {
5125         case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_53:
5126                 rtl8168ep_stop_cmac(tp);
5127                 fallthrough;
5128         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
5129                 rtl_hw_init_8168g(tp);
5130                 break;
5131         case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63:
5132                 rtl_hw_init_8125(tp);
5133                 break;
5134         default:
5135                 break;
5136         }
5137 }
5138
5139 static int rtl_jumbo_max(struct rtl8169_private *tp)
5140 {
5141         /* Non-GBit versions don't support jumbo frames */
5142         if (!tp->supports_gmii)
5143                 return 0;
5144
5145         switch (tp->mac_version) {
5146         /* RTL8169 */
5147         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
5148                 return JUMBO_7K;
5149         /* RTL8168b */
5150         case RTL_GIGA_MAC_VER_11:
5151         case RTL_GIGA_MAC_VER_17:
5152                 return JUMBO_4K;
5153         /* RTL8168c */
5154         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
5155                 return JUMBO_6K;
5156         default:
5157                 return JUMBO_9K;
5158         }
5159 }
5160
5161 static void rtl_init_mac_address(struct rtl8169_private *tp)
5162 {
5163         u8 mac_addr[ETH_ALEN] __aligned(2) = {};
5164         struct net_device *dev = tp->dev;
5165         int rc;
5166
5167         rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr);
5168         if (!rc)
5169                 goto done;
5170
5171         rtl_read_mac_address(tp, mac_addr);
5172         if (is_valid_ether_addr(mac_addr))
5173                 goto done;
5174
5175         rtl_read_mac_from_reg(tp, mac_addr, MAC0);
5176         if (is_valid_ether_addr(mac_addr))
5177                 goto done;
5178
5179         eth_random_addr(mac_addr);
5180         dev->addr_assign_type = NET_ADDR_RANDOM;
5181         dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n");
5182 done:
5183         eth_hw_addr_set(dev, mac_addr);
5184         rtl_rar_set(tp, mac_addr);
5185 }
5186
5187 /* register is set if system vendor successfully tested ASPM 1.2 */
5188 static bool rtl_aspm_is_safe(struct rtl8169_private *tp)
5189 {
5190         if (tp->mac_version >= RTL_GIGA_MAC_VER_61 &&
5191             r8168_mac_ocp_read(tp, 0xc0b2) & 0xf)
5192                 return true;
5193
5194         return false;
5195 }
5196
5197 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
5198 {
5199         struct rtl8169_private *tp;
5200         int jumbo_max, region, rc;
5201         enum mac_version chipset;
5202         struct net_device *dev;
5203         u32 txconfig;
5204         u16 xid;
5205
5206         dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
5207         if (!dev)
5208                 return -ENOMEM;
5209
5210         SET_NETDEV_DEV(dev, &pdev->dev);
5211         dev->netdev_ops = &rtl_netdev_ops;
5212         tp = netdev_priv(dev);
5213         tp->dev = dev;
5214         tp->pci_dev = pdev;
5215         tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1;
5216         tp->eee_adv = -1;
5217         tp->ocp_base = OCP_STD_PHY_BASE;
5218
5219         raw_spin_lock_init(&tp->cfg9346_usage_lock);
5220         raw_spin_lock_init(&tp->config25_lock);
5221         raw_spin_lock_init(&tp->mac_ocp_lock);
5222
5223         dev->tstats = devm_netdev_alloc_pcpu_stats(&pdev->dev,
5224                                                    struct pcpu_sw_netstats);
5225         if (!dev->tstats)
5226                 return -ENOMEM;
5227
5228         /* Get the *optional* external "ether_clk" used on some boards */
5229         tp->clk = devm_clk_get_optional_enabled(&pdev->dev, "ether_clk");
5230         if (IS_ERR(tp->clk))
5231                 return dev_err_probe(&pdev->dev, PTR_ERR(tp->clk), "failed to get ether_clk\n");
5232
5233         /* enable device (incl. PCI PM wakeup and hotplug setup) */
5234         rc = pcim_enable_device(pdev);
5235         if (rc < 0)
5236                 return dev_err_probe(&pdev->dev, rc, "enable failure\n");
5237
5238         if (pcim_set_mwi(pdev) < 0)
5239                 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
5240
5241         /* use first MMIO region */
5242         region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
5243         if (region < 0)
5244                 return dev_err_probe(&pdev->dev, -ENODEV, "no MMIO resource found\n");
5245
5246         rc = pcim_iomap_regions(pdev, BIT(region), KBUILD_MODNAME);
5247         if (rc < 0)
5248                 return dev_err_probe(&pdev->dev, rc, "cannot remap MMIO, aborting\n");
5249
5250         tp->mmio_addr = pcim_iomap_table(pdev)[region];
5251
5252         txconfig = RTL_R32(tp, TxConfig);
5253         if (txconfig == ~0U)
5254                 return dev_err_probe(&pdev->dev, -EIO, "PCI read failed\n");
5255
5256         xid = (txconfig >> 20) & 0xfcf;
5257
5258         /* Identify chip attached to board */
5259         chipset = rtl8169_get_mac_version(xid, tp->supports_gmii);
5260         if (chipset == RTL_GIGA_MAC_NONE)
5261                 return dev_err_probe(&pdev->dev, -ENODEV,
5262                                      "unknown chip XID %03x, contact r8169 maintainers (see MAINTAINERS file)\n",
5263                                      xid);
5264         tp->mac_version = chipset;
5265
5266         /* Disable ASPM L1 as that cause random device stop working
5267          * problems as well as full system hangs for some PCIe devices users.
5268          */
5269         if (rtl_aspm_is_safe(tp))
5270                 rc = 0;
5271         else
5272                 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L1);
5273         tp->aspm_manageable = !rc;
5274
5275         tp->dash_type = rtl_get_dash_type(tp);
5276         tp->dash_enabled = rtl_dash_is_enabled(tp);
5277
5278         tp->cp_cmd = RTL_R16(tp, CPlusCmd) & CPCMD_MASK;
5279
5280         if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 &&
5281             !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)))
5282                 dev->features |= NETIF_F_HIGHDMA;
5283
5284         rtl_init_rxcfg(tp);
5285
5286         rtl8169_irq_mask_and_ack(tp);
5287
5288         rtl_hw_initialize(tp);
5289
5290         rtl_hw_reset(tp);
5291
5292         rc = rtl_alloc_irq(tp);
5293         if (rc < 0)
5294                 return dev_err_probe(&pdev->dev, rc, "Can't allocate interrupt\n");
5295
5296         tp->irq = pci_irq_vector(pdev, 0);
5297
5298         INIT_WORK(&tp->wk.work, rtl_task);
5299
5300         rtl_init_mac_address(tp);
5301
5302         dev->ethtool_ops = &rtl8169_ethtool_ops;
5303
5304         netif_napi_add(dev, &tp->napi, rtl8169_poll);
5305
5306         dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
5307                            NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
5308         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO;
5309         dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
5310
5311         /*
5312          * Pretend we are using VLANs; This bypasses a nasty bug where
5313          * Interrupts stop flowing on high load on 8110SCd controllers.
5314          */
5315         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
5316                 /* Disallow toggling */
5317                 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
5318
5319         if (rtl_chip_supports_csum_v2(tp))
5320                 dev->hw_features |= NETIF_F_IPV6_CSUM;
5321
5322         dev->features |= dev->hw_features;
5323
5324         /* There has been a number of reports that using SG/TSO results in
5325          * tx timeouts. However for a lot of people SG/TSO works fine.
5326          * Therefore disable both features by default, but allow users to
5327          * enable them. Use at own risk!
5328          */
5329         if (rtl_chip_supports_csum_v2(tp)) {
5330                 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6;
5331                 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V2);
5332                 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V2);
5333         } else {
5334                 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO;
5335                 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V1);
5336                 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V1);
5337         }
5338
5339         dev->hw_features |= NETIF_F_RXALL;
5340         dev->hw_features |= NETIF_F_RXFCS;
5341
5342         netdev_sw_irq_coalesce_default_on(dev);
5343
5344         /* configure chip for default features */
5345         rtl8169_set_features(dev, dev->features);
5346
5347         if (!tp->dash_enabled) {
5348                 rtl_set_d3_pll_down(tp, true);
5349         } else {
5350                 rtl_set_d3_pll_down(tp, false);
5351                 dev->wol_enabled = 1;
5352         }
5353
5354         jumbo_max = rtl_jumbo_max(tp);
5355         if (jumbo_max)
5356                 dev->max_mtu = jumbo_max;
5357
5358         rtl_set_irq_mask(tp);
5359
5360         tp->fw_name = rtl_chip_infos[chipset].fw_name;
5361
5362         tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
5363                                             &tp->counters_phys_addr,
5364                                             GFP_KERNEL);
5365         if (!tp->counters)
5366                 return -ENOMEM;
5367
5368         pci_set_drvdata(pdev, tp);
5369
5370         rc = r8169_mdio_register(tp);
5371         if (rc)
5372                 return rc;
5373
5374         rc = register_netdev(dev);
5375         if (rc)
5376                 return rc;
5377
5378         netdev_info(dev, "%s, %pM, XID %03x, IRQ %d\n",
5379                     rtl_chip_infos[chipset].name, dev->dev_addr, xid, tp->irq);
5380
5381         if (jumbo_max)
5382                 netdev_info(dev, "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
5383                             jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?
5384                             "ok" : "ko");
5385
5386         if (tp->dash_type != RTL_DASH_NONE) {
5387                 netdev_info(dev, "DASH %s\n",
5388                             tp->dash_enabled ? "enabled" : "disabled");
5389                 rtl8168_driver_start(tp);
5390         }
5391
5392         if (pci_dev_run_wake(pdev))
5393                 pm_runtime_put_sync(&pdev->dev);
5394
5395         return 0;
5396 }
5397
5398 static struct pci_driver rtl8169_pci_driver = {
5399         .name           = KBUILD_MODNAME,
5400         .id_table       = rtl8169_pci_tbl,
5401         .probe          = rtl_init_one,
5402         .remove         = rtl_remove_one,
5403         .shutdown       = rtl_shutdown,
5404         .driver.pm      = pm_ptr(&rtl8169_pm_ops),
5405 };
5406
5407 module_pci_driver(rtl8169_pci_driver);