1 // SPDX-License-Identifier: GPL-2.0-only
3 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
7 * Copyright (c) a lot of people too. Please respect their work.
9 * See MAINTAINERS file for support contact information.
12 #include <linux/module.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/clk.h>
17 #include <linux/delay.h>
18 #include <linux/ethtool.h>
19 #include <linux/phy.h>
20 #include <linux/if_vlan.h>
24 #include <linux/tcp.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/bitfield.h>
29 #include <linux/prefetch.h>
30 #include <linux/ipv6.h>
31 #include <asm/unaligned.h>
32 #include <net/ip6_checksum.h>
35 #include "r8169_firmware.h"
37 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
38 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
39 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
40 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
41 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
42 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
43 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
44 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
45 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
46 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
47 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
48 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
49 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
50 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
51 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
52 #define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw"
53 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw"
54 #define FIRMWARE_8168FP_3 "rtl_nic/rtl8168fp-3.fw"
55 #define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw"
56 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw"
57 #define FIRMWARE_8125A_3 "rtl_nic/rtl8125a-3.fw"
58 #define FIRMWARE_8125B_2 "rtl_nic/rtl8125b-2.fw"
60 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
61 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
62 #define MC_FILTER_LIMIT 32
64 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
65 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
67 #define R8169_REGS_SIZE 256
68 #define R8169_RX_BUF_SIZE (SZ_16K - 1)
69 #define NUM_TX_DESC 256 /* Number of Tx descriptor registers */
70 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
71 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
72 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
74 #define OCP_STD_PHY_BASE 0xa400
76 #define RTL_CFG_NO_GBIT 1
78 /* write/read MMIO register */
79 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg))
80 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
81 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
82 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg))
83 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg))
84 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg))
86 #define JUMBO_4K (4 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
87 #define JUMBO_6K (6 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
88 #define JUMBO_7K (7 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
89 #define JUMBO_9K (9 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
94 } rtl_chip_infos[] = {
96 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" },
97 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" },
98 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" },
99 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" },
100 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" },
102 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" },
103 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" },
104 [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e" },
105 [RTL_GIGA_MAC_VER_10] = {"RTL8101e" },
106 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" },
107 [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b" },
108 [RTL_GIGA_MAC_VER_13] = {"RTL8101e/RTL8100e" },
109 [RTL_GIGA_MAC_VER_14] = {"RTL8401" },
110 [RTL_GIGA_MAC_VER_16] = {"RTL8101e" },
111 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" },
112 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" },
113 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" },
114 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" },
115 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" },
116 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" },
117 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" },
118 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" },
119 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1},
120 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2},
121 [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp" },
122 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" },
123 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1},
124 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1},
125 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" },
126 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1},
127 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2},
128 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3},
129 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1},
130 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2},
131 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 },
132 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 },
133 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1},
134 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2},
135 [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g" },
136 [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu", FIRMWARE_8168G_3},
137 [RTL_GIGA_MAC_VER_43] = {"RTL8106eus", FIRMWARE_8106E_2},
138 [RTL_GIGA_MAC_VER_44] = {"RTL8411b", FIRMWARE_8411_2 },
139 [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h", FIRMWARE_8168H_1},
140 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2},
141 [RTL_GIGA_MAC_VER_47] = {"RTL8107e", FIRMWARE_8107E_1},
142 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2},
143 [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep" },
144 [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep" },
145 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" },
146 [RTL_GIGA_MAC_VER_52] = {"RTL8168fp/RTL8117", FIRMWARE_8168FP_3},
147 [RTL_GIGA_MAC_VER_53] = {"RTL8168fp/RTL8117", },
148 [RTL_GIGA_MAC_VER_60] = {"RTL8125A" },
149 [RTL_GIGA_MAC_VER_61] = {"RTL8125A", FIRMWARE_8125A_3},
150 /* reserve 62 for CFG_METHOD_4 in the vendor driver */
151 [RTL_GIGA_MAC_VER_63] = {"RTL8125B", FIRMWARE_8125B_2},
154 static const struct pci_device_id rtl8169_pci_tbl[] = {
155 { PCI_VDEVICE(REALTEK, 0x2502) },
156 { PCI_VDEVICE(REALTEK, 0x2600) },
157 { PCI_VDEVICE(REALTEK, 0x8129) },
158 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT },
159 { PCI_VDEVICE(REALTEK, 0x8161) },
160 { PCI_VDEVICE(REALTEK, 0x8167) },
161 { PCI_VDEVICE(REALTEK, 0x8168) },
162 { PCI_VDEVICE(NCUBE, 0x8168) },
163 { PCI_VDEVICE(REALTEK, 0x8169) },
164 { PCI_VENDOR_ID_DLINK, 0x4300,
165 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 },
166 { PCI_VDEVICE(DLINK, 0x4300) },
167 { PCI_VDEVICE(DLINK, 0x4302) },
168 { PCI_VDEVICE(AT, 0xc107) },
169 { PCI_VDEVICE(USR, 0x0116) },
170 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 },
171 { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 },
172 { PCI_VDEVICE(REALTEK, 0x8125) },
173 { PCI_VDEVICE(REALTEK, 0x3000) },
177 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
180 MAC0 = 0, /* Ethernet hardware address. */
182 MAR0 = 8, /* Multicast filter. */
183 CounterAddrLow = 0x10,
184 CounterAddrHigh = 0x14,
185 TxDescStartAddrLow = 0x20,
186 TxDescStartAddrHigh = 0x24,
187 TxHDescStartAddrLow = 0x28,
188 TxHDescStartAddrHigh = 0x2c,
197 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
198 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
201 #define RX128_INT_EN (1 << 15) /* 8111c and later */
202 #define RX_MULTI_EN (1 << 14) /* 8111c only */
203 #define RXCFG_FIFO_SHIFT 13
204 /* No threshold before first PCI xfer */
205 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
206 #define RX_EARLY_OFF (1 << 11)
207 #define RXCFG_DMA_SHIFT 8
208 /* Unlimited maximum PCI burst. */
209 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
215 #define PME_SIGNAL (1 << 5) /* 8168c and later */
226 #define RTL_COALESCE_TX_USECS GENMASK(15, 12)
227 #define RTL_COALESCE_TX_FRAMES GENMASK(11, 8)
228 #define RTL_COALESCE_RX_USECS GENMASK(7, 4)
229 #define RTL_COALESCE_RX_FRAMES GENMASK(3, 0)
231 #define RTL_COALESCE_T_MAX 0x0fU
232 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_T_MAX * 4)
234 RxDescAddrLow = 0xe4,
235 RxDescAddrHigh = 0xe8,
236 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
238 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
240 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
242 #define TxPacketMax (8064 >> 7)
243 #define EarlySize 0x27
246 FuncEventMask = 0xf4,
247 FuncPresetState = 0xf8,
252 FuncForceEvent = 0xfc,
255 enum rtl8168_8101_registers {
258 #define CSIAR_FLAG 0x80000000
259 #define CSIAR_WRITE_CMD 0x80000000
260 #define CSIAR_BYTE_ENABLE 0x0000f000
261 #define CSIAR_ADDR_MASK 0x00000fff
263 #define D3COLD_NO_PLL_DOWN BIT(7)
264 #define D3HOT_NO_PLL_DOWN BIT(6)
265 #define D3_NO_PLL_DOWN (BIT(7) | BIT(6))
267 #define EPHYAR_FLAG 0x80000000
268 #define EPHYAR_WRITE_CMD 0x80000000
269 #define EPHYAR_REG_MASK 0x1f
270 #define EPHYAR_REG_SHIFT 16
271 #define EPHYAR_DATA_MASK 0xffff
273 #define PFM_EN (1 << 6)
274 #define TX_10M_PS_EN (1 << 7)
276 #define FIX_NAK_1 (1 << 4)
277 #define FIX_NAK_2 (1 << 3)
280 #define NOW_IS_OOB (1 << 7)
281 #define TX_EMPTY (1 << 5)
282 #define RX_EMPTY (1 << 4)
283 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
284 #define EN_NDP (1 << 3)
285 #define EN_OOB_RESET (1 << 2)
286 #define LINK_LIST_RDY (1 << 1)
288 #define EFUSEAR_FLAG 0x80000000
289 #define EFUSEAR_WRITE_CMD 0x80000000
290 #define EFUSEAR_READ_CMD 0x00000000
291 #define EFUSEAR_REG_MASK 0x03ff
292 #define EFUSEAR_REG_SHIFT 8
293 #define EFUSEAR_DATA_MASK 0xff
295 #define PFM_D3COLD_EN (1 << 6)
298 enum rtl8168_registers {
303 #define ERIAR_FLAG 0x80000000
304 #define ERIAR_WRITE_CMD 0x80000000
305 #define ERIAR_READ_CMD 0x00000000
306 #define ERIAR_ADDR_BYTE_ALIGN 4
307 #define ERIAR_TYPE_SHIFT 16
308 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
309 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
310 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
311 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT)
312 #define ERIAR_MASK_SHIFT 12
313 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
314 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
315 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
316 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
317 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
318 EPHY_RXER_NUM = 0x7c,
319 OCPDR = 0xb0, /* OCP GPHY access */
320 #define OCPDR_WRITE_CMD 0x80000000
321 #define OCPDR_READ_CMD 0x00000000
322 #define OCPDR_REG_MASK 0x7f
323 #define OCPDR_GPHY_REG_SHIFT 16
324 #define OCPDR_DATA_MASK 0xffff
326 #define OCPAR_FLAG 0x80000000
327 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
328 #define OCPAR_GPHY_READ_CMD 0x0000f060
330 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
331 MISC = 0xf0, /* 8168e only. */
332 #define TXPLA_RST (1 << 29)
333 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
334 #define PWM_EN (1 << 22)
335 #define RXDV_GATED_EN (1 << 19)
336 #define EARLY_TALLY_EN (1 << 16)
339 enum rtl8125_registers {
340 IntrMask_8125 = 0x38,
341 IntrStatus_8125 = 0x3c,
344 EEE_TXIDLE_TIMER_8125 = 0x6048,
347 #define RX_VLAN_INNER_8125 BIT(22)
348 #define RX_VLAN_OUTER_8125 BIT(23)
349 #define RX_VLAN_8125 (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125)
351 #define RX_FETCH_DFLT_8125 (8 << 27)
353 enum rtl_register_content {
354 /* InterruptStatusBits */
358 TxDescUnavail = 0x0080,
380 /* TXPoll register p.5 */
381 HPQ = 0x80, /* Poll cmd on the high prio queue */
382 NPQ = 0x40, /* Poll cmd on the low prio queue */
383 FSWInt = 0x01, /* Forced software interrupt */
387 Cfg9346_Unlock = 0xc0,
392 #define RX_CONFIG_ACCEPT_ERR_MASK 0x30
393 AcceptBroadcast = 0x08,
394 AcceptMulticast = 0x04,
396 AcceptAllPhys = 0x01,
397 #define RX_CONFIG_ACCEPT_OK_MASK 0x0f
398 #define RX_CONFIG_ACCEPT_MASK 0x3f
401 TxInterFrameGapShift = 24,
402 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
404 /* Config1 register p.24 */
407 Speed_down = (1 << 4),
411 PMEnable = (1 << 0), /* Power Management Enable */
413 /* Config2 register p. 25 */
414 ClkReqEn = (1 << 7), /* Clock Request Enable */
415 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
416 PCI_Clock_66MHz = 0x01,
417 PCI_Clock_33MHz = 0x00,
419 /* Config3 register p.25 */
420 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
421 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
422 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
423 Rdy_to_L23 = (1 << 1), /* L23 Enable */
424 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
426 /* Config4 register */
427 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
429 /* Config5 register p.27 */
430 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
431 MWF = (1 << 5), /* Accept Multicast wakeup frame */
432 UWF = (1 << 4), /* Accept Unicast wakeup frame */
434 LanWake = (1 << 1), /* LanWake enable/disable */
435 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
436 ASPM_en = (1 << 0), /* ASPM enable */
439 EnableBist = (1 << 15), // 8168 8101
440 Mac_dbgo_oe = (1 << 14), // 8168 8101
441 EnAnaPLL = (1 << 14), // 8169
442 Normal_mode = (1 << 13), // unused
443 Force_half_dup = (1 << 12), // 8168 8101
444 Force_rxflow_en = (1 << 11), // 8168 8101
445 Force_txflow_en = (1 << 10), // 8168 8101
446 Cxpl_dbg_sel = (1 << 9), // 8168 8101
447 ASF = (1 << 8), // 8168 8101
448 PktCntrDisable = (1 << 7), // 8168 8101
449 Mac_dbgo_sel = 0x001c, // 8168
454 #define INTT_MASK GENMASK(1, 0)
455 #define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
457 /* rtl8169_PHYstatus */
467 /* ResetCounterCommand */
470 /* DumpCounterCommand */
473 /* magic enable v2 */
474 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */
478 /* First doubleword. */
479 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
480 RingEnd = (1 << 30), /* End of descriptor ring */
481 FirstFrag = (1 << 29), /* First segment of a packet */
482 LastFrag = (1 << 28), /* Final segment of a packet */
486 enum rtl_tx_desc_bit {
487 /* First doubleword. */
488 TD_LSO = (1 << 27), /* Large Send Offload */
489 #define TD_MSS_MAX 0x07ffu /* MSS value */
491 /* Second doubleword. */
492 TxVlanTag = (1 << 17), /* Add VLAN tag */
495 /* 8169, 8168b and 810x except 8102e. */
496 enum rtl_tx_desc_bit_0 {
497 /* First doubleword. */
498 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
499 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
500 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
501 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
504 /* 8102e, 8168c and beyond. */
505 enum rtl_tx_desc_bit_1 {
506 /* First doubleword. */
507 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */
508 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */
509 #define GTTCPHO_SHIFT 18
510 #define GTTCPHO_MAX 0x7f
512 /* Second doubleword. */
513 #define TCPHO_SHIFT 18
514 #define TCPHO_MAX 0x3ff
515 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
516 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */
517 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */
518 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
519 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
522 enum rtl_rx_desc_bit {
524 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
525 PID0 = (1 << 17), /* Protocol ID bit 0/2 */
527 #define RxProtoUDP (PID1)
528 #define RxProtoTCP (PID0)
529 #define RxProtoIP (PID1 | PID0)
530 #define RxProtoMask RxProtoIP
532 IPFail = (1 << 16), /* IP checksum failed */
533 UDPFail = (1 << 15), /* UDP/IP checksum failed */
534 TCPFail = (1 << 14), /* TCP/IP checksum failed */
536 #define RxCSFailMask (IPFail | UDPFail | TCPFail)
538 RxVlanTag = (1 << 16), /* VLAN tag available */
541 #define RTL_GSO_MAX_SIZE_V1 32000
542 #define RTL_GSO_MAX_SEGS_V1 24
543 #define RTL_GSO_MAX_SIZE_V2 64000
544 #define RTL_GSO_MAX_SEGS_V2 64
563 struct rtl8169_counters {
570 __le32 tx_one_collision;
571 __le32 tx_multi_collision;
579 struct rtl8169_tc_offsets {
582 __le32 tx_multi_collision;
588 RTL_FLAG_TASK_ENABLED = 0,
589 RTL_FLAG_TASK_RESET_PENDING,
599 struct rtl8169_private {
600 void __iomem *mmio_addr; /* memory map physical address */
601 struct pci_dev *pci_dev;
602 struct net_device *dev;
603 struct phy_device *phydev;
604 struct napi_struct napi;
605 enum mac_version mac_version;
606 enum rtl_dash_type dash_type;
607 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
608 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
610 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
611 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
612 dma_addr_t TxPhyAddr;
613 dma_addr_t RxPhyAddr;
614 struct page *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
615 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
621 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
622 struct work_struct work;
625 unsigned supports_gmii:1;
626 unsigned aspm_manageable:1;
627 dma_addr_t counters_phys_addr;
628 struct rtl8169_counters *counters;
629 struct rtl8169_tc_offsets tc_offset;
634 struct rtl_fw *rtl_fw;
639 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp);
641 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
642 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
643 MODULE_SOFTDEP("pre: realtek");
644 MODULE_LICENSE("GPL");
645 MODULE_FIRMWARE(FIRMWARE_8168D_1);
646 MODULE_FIRMWARE(FIRMWARE_8168D_2);
647 MODULE_FIRMWARE(FIRMWARE_8168E_1);
648 MODULE_FIRMWARE(FIRMWARE_8168E_2);
649 MODULE_FIRMWARE(FIRMWARE_8168E_3);
650 MODULE_FIRMWARE(FIRMWARE_8105E_1);
651 MODULE_FIRMWARE(FIRMWARE_8168F_1);
652 MODULE_FIRMWARE(FIRMWARE_8168F_2);
653 MODULE_FIRMWARE(FIRMWARE_8402_1);
654 MODULE_FIRMWARE(FIRMWARE_8411_1);
655 MODULE_FIRMWARE(FIRMWARE_8411_2);
656 MODULE_FIRMWARE(FIRMWARE_8106E_1);
657 MODULE_FIRMWARE(FIRMWARE_8106E_2);
658 MODULE_FIRMWARE(FIRMWARE_8168G_2);
659 MODULE_FIRMWARE(FIRMWARE_8168G_3);
660 MODULE_FIRMWARE(FIRMWARE_8168H_1);
661 MODULE_FIRMWARE(FIRMWARE_8168H_2);
662 MODULE_FIRMWARE(FIRMWARE_8168FP_3);
663 MODULE_FIRMWARE(FIRMWARE_8107E_1);
664 MODULE_FIRMWARE(FIRMWARE_8107E_2);
665 MODULE_FIRMWARE(FIRMWARE_8125A_3);
666 MODULE_FIRMWARE(FIRMWARE_8125B_2);
668 static inline struct device *tp_to_dev(struct rtl8169_private *tp)
670 return &tp->pci_dev->dev;
673 static void rtl_lock_config_regs(struct rtl8169_private *tp)
675 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
678 static void rtl_unlock_config_regs(struct rtl8169_private *tp)
680 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
683 static void rtl_pci_commit(struct rtl8169_private *tp)
685 /* Read an arbitrary register to commit a preceding PCI write */
689 static bool rtl_is_8125(struct rtl8169_private *tp)
691 return tp->mac_version >= RTL_GIGA_MAC_VER_60;
694 static bool rtl_is_8168evl_up(struct rtl8169_private *tp)
696 return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
697 tp->mac_version != RTL_GIGA_MAC_VER_39 &&
698 tp->mac_version <= RTL_GIGA_MAC_VER_53;
701 static bool rtl_supports_eee(struct rtl8169_private *tp)
703 return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
704 tp->mac_version != RTL_GIGA_MAC_VER_37 &&
705 tp->mac_version != RTL_GIGA_MAC_VER_39;
708 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg)
712 for (i = 0; i < ETH_ALEN; i++)
713 mac[i] = RTL_R8(tp, reg + i);
717 bool (*check)(struct rtl8169_private *);
721 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
722 unsigned long usecs, int n, bool high)
726 for (i = 0; i < n; i++) {
727 if (c->check(tp) == high)
733 netdev_err(tp->dev, "%s == %d (loop: %d, delay: %lu).\n",
734 c->msg, !high, n, usecs);
738 static bool rtl_loop_wait_high(struct rtl8169_private *tp,
739 const struct rtl_cond *c,
740 unsigned long d, int n)
742 return rtl_loop_wait(tp, c, d, n, true);
745 static bool rtl_loop_wait_low(struct rtl8169_private *tp,
746 const struct rtl_cond *c,
747 unsigned long d, int n)
749 return rtl_loop_wait(tp, c, d, n, false);
752 #define DECLARE_RTL_COND(name) \
753 static bool name ## _check(struct rtl8169_private *); \
755 static const struct rtl_cond name = { \
756 .check = name ## _check, \
760 static bool name ## _check(struct rtl8169_private *tp)
762 static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type)
764 /* based on RTL8168FP_OOBMAC_BASE in vendor driver */
765 if (type == ERIAR_OOB &&
766 (tp->mac_version == RTL_GIGA_MAC_VER_52 ||
767 tp->mac_version == RTL_GIGA_MAC_VER_53))
771 DECLARE_RTL_COND(rtl_eriar_cond)
773 return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
776 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
779 u32 cmd = ERIAR_WRITE_CMD | type | mask | addr;
781 if (WARN(addr & 3 || !mask, "addr: 0x%x, mask: 0x%08x\n", addr, mask))
784 RTL_W32(tp, ERIDR, val);
785 r8168fp_adjust_ocp_cmd(tp, &cmd, type);
786 RTL_W32(tp, ERIAR, cmd);
788 rtl_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
791 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
794 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC);
797 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
799 u32 cmd = ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr;
801 r8168fp_adjust_ocp_cmd(tp, &cmd, type);
802 RTL_W32(tp, ERIAR, cmd);
804 return rtl_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
805 RTL_R32(tp, ERIDR) : ~0;
808 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr)
810 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC);
813 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 p, u32 m)
815 u32 val = rtl_eri_read(tp, addr);
817 rtl_eri_write(tp, addr, ERIAR_MASK_1111, (val & ~m) | p);
820 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 p)
822 rtl_w0w1_eri(tp, addr, p, 0);
825 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 m)
827 rtl_w0w1_eri(tp, addr, 0, m);
830 static bool rtl_ocp_reg_failure(u32 reg)
832 return WARN_ONCE(reg & 0xffff0001, "Invalid ocp reg %x!\n", reg);
835 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
837 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
840 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
842 if (rtl_ocp_reg_failure(reg))
845 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
847 rtl_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
850 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
852 if (rtl_ocp_reg_failure(reg))
855 RTL_W32(tp, GPHY_OCP, reg << 15);
857 return rtl_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
858 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT;
861 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
863 if (rtl_ocp_reg_failure(reg))
866 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
869 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
871 if (rtl_ocp_reg_failure(reg))
874 RTL_W32(tp, OCPDR, reg << 15);
876 return RTL_R32(tp, OCPDR);
879 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask,
882 u16 data = r8168_mac_ocp_read(tp, reg);
884 r8168_mac_ocp_write(tp, reg, (data & ~mask) | set);
887 /* Work around a hw issue with RTL8168g PHY, the quirk disables
888 * PHY MCU interrupts before PHY power-down.
890 static void rtl8168g_phy_suspend_quirk(struct rtl8169_private *tp, int value)
892 switch (tp->mac_version) {
893 case RTL_GIGA_MAC_VER_40:
894 case RTL_GIGA_MAC_VER_41:
895 case RTL_GIGA_MAC_VER_49:
896 if (value & BMCR_RESET || !(value & BMCR_PDOWN))
897 rtl_eri_set_bits(tp, 0x1a8, 0xfc000000);
899 rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000);
906 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
909 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
913 if (tp->ocp_base != OCP_STD_PHY_BASE)
916 if (tp->ocp_base == OCP_STD_PHY_BASE && reg == MII_BMCR)
917 rtl8168g_phy_suspend_quirk(tp, value);
919 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
922 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
925 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4;
927 if (tp->ocp_base != OCP_STD_PHY_BASE)
930 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
933 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
936 tp->ocp_base = value << 4;
940 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
943 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
945 return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
948 DECLARE_RTL_COND(rtl_phyar_cond)
950 return RTL_R32(tp, PHYAR) & 0x80000000;
953 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
955 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
957 rtl_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
959 * According to hardware specs a 20us delay is required after write
960 * complete indication, but before sending next command.
965 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
969 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
971 value = rtl_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
972 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT;
975 * According to hardware specs a 20us delay is required after read
976 * complete indication, but before sending next command.
983 DECLARE_RTL_COND(rtl_ocpar_cond)
985 return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
988 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
990 RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
991 RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
992 RTL_W32(tp, EPHY_RXER_NUM, 0);
994 rtl_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
997 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
999 r8168dp_1_mdio_access(tp, reg,
1000 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
1003 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
1005 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
1008 RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
1009 RTL_W32(tp, EPHY_RXER_NUM, 0);
1011 return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1012 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : -ETIMEDOUT;
1015 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
1017 static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
1019 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1022 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
1024 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1027 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
1029 r8168dp_2_mdio_start(tp);
1031 r8169_mdio_write(tp, reg, value);
1033 r8168dp_2_mdio_stop(tp);
1036 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1040 /* Work around issue with chip reporting wrong PHY ID */
1041 if (reg == MII_PHYSID2)
1044 r8168dp_2_mdio_start(tp);
1046 value = r8169_mdio_read(tp, reg);
1048 r8168dp_2_mdio_stop(tp);
1053 static void rtl_writephy(struct rtl8169_private *tp, int location, int val)
1055 switch (tp->mac_version) {
1056 case RTL_GIGA_MAC_VER_27:
1057 r8168dp_1_mdio_write(tp, location, val);
1059 case RTL_GIGA_MAC_VER_28:
1060 case RTL_GIGA_MAC_VER_31:
1061 r8168dp_2_mdio_write(tp, location, val);
1063 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
1064 r8168g_mdio_write(tp, location, val);
1067 r8169_mdio_write(tp, location, val);
1072 static int rtl_readphy(struct rtl8169_private *tp, int location)
1074 switch (tp->mac_version) {
1075 case RTL_GIGA_MAC_VER_27:
1076 return r8168dp_1_mdio_read(tp, location);
1077 case RTL_GIGA_MAC_VER_28:
1078 case RTL_GIGA_MAC_VER_31:
1079 return r8168dp_2_mdio_read(tp, location);
1080 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
1081 return r8168g_mdio_read(tp, location);
1083 return r8169_mdio_read(tp, location);
1087 DECLARE_RTL_COND(rtl_ephyar_cond)
1089 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1092 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1094 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1095 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1097 rtl_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1102 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1104 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1106 return rtl_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1107 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1110 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u16 reg)
1112 RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff));
1113 return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1114 RTL_R32(tp, OCPDR) : ~0;
1117 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u16 reg)
1119 return _rtl_eri_read(tp, reg, ERIAR_OOB);
1122 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1125 RTL_W32(tp, OCPDR, data);
1126 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1127 rtl_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1130 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1133 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1137 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd)
1139 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd);
1141 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001);
1144 #define OOB_CMD_RESET 0x00
1145 #define OOB_CMD_DRIVER_START 0x05
1146 #define OOB_CMD_DRIVER_STOP 0x06
1148 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1150 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1153 DECLARE_RTL_COND(rtl_dp_ocp_read_cond)
1157 reg = rtl8168_get_ocp_reg(tp);
1159 return r8168dp_ocp_read(tp, reg) & 0x00000800;
1162 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1164 return r8168ep_ocp_read(tp, 0x124) & 0x00000001;
1167 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1169 return RTL_R8(tp, IBISR0) & 0x20;
1172 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1174 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1175 rtl_loop_wait_high(tp, &rtl_ocp_tx_cond, 50000, 2000);
1176 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1177 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1180 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1182 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START);
1183 rtl_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10000, 10);
1186 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1188 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1189 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01);
1190 rtl_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10000, 10);
1193 static void rtl8168_driver_start(struct rtl8169_private *tp)
1195 if (tp->dash_type == RTL_DASH_DP)
1196 rtl8168dp_driver_start(tp);
1198 rtl8168ep_driver_start(tp);
1201 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1203 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1204 rtl_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10000, 10);
1207 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1209 rtl8168ep_stop_cmac(tp);
1210 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1211 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01);
1212 rtl_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10000, 10);
1215 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1217 if (tp->dash_type == RTL_DASH_DP)
1218 rtl8168dp_driver_stop(tp);
1220 rtl8168ep_driver_stop(tp);
1223 static bool r8168dp_check_dash(struct rtl8169_private *tp)
1225 u16 reg = rtl8168_get_ocp_reg(tp);
1227 return r8168dp_ocp_read(tp, reg) & BIT(15);
1230 static bool r8168ep_check_dash(struct rtl8169_private *tp)
1232 return r8168ep_ocp_read(tp, 0x128) & BIT(0);
1235 static enum rtl_dash_type rtl_check_dash(struct rtl8169_private *tp)
1237 switch (tp->mac_version) {
1238 case RTL_GIGA_MAC_VER_27:
1239 case RTL_GIGA_MAC_VER_28:
1240 case RTL_GIGA_MAC_VER_31:
1241 return r8168dp_check_dash(tp) ? RTL_DASH_DP : RTL_DASH_NONE;
1242 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_53:
1243 return r8168ep_check_dash(tp) ? RTL_DASH_EP : RTL_DASH_NONE;
1245 return RTL_DASH_NONE;
1249 static void rtl_set_d3_pll_down(struct rtl8169_private *tp, bool enable)
1251 switch (tp->mac_version) {
1252 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_26:
1253 case RTL_GIGA_MAC_VER_29 ... RTL_GIGA_MAC_VER_30:
1254 case RTL_GIGA_MAC_VER_32 ... RTL_GIGA_MAC_VER_37:
1255 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63:
1257 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~D3_NO_PLL_DOWN);
1259 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | D3_NO_PLL_DOWN);
1266 static void rtl_reset_packet_filter(struct rtl8169_private *tp)
1268 rtl_eri_clear_bits(tp, 0xdc, BIT(0));
1269 rtl_eri_set_bits(tp, 0xdc, BIT(0));
1272 DECLARE_RTL_COND(rtl_efusear_cond)
1274 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1277 u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1279 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1281 return rtl_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1282 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1285 static u32 rtl_get_events(struct rtl8169_private *tp)
1287 if (rtl_is_8125(tp))
1288 return RTL_R32(tp, IntrStatus_8125);
1290 return RTL_R16(tp, IntrStatus);
1293 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits)
1295 if (rtl_is_8125(tp))
1296 RTL_W32(tp, IntrStatus_8125, bits);
1298 RTL_W16(tp, IntrStatus, bits);
1301 static void rtl_irq_disable(struct rtl8169_private *tp)
1303 if (rtl_is_8125(tp))
1304 RTL_W32(tp, IntrMask_8125, 0);
1306 RTL_W16(tp, IntrMask, 0);
1309 static void rtl_irq_enable(struct rtl8169_private *tp)
1311 if (rtl_is_8125(tp))
1312 RTL_W32(tp, IntrMask_8125, tp->irq_mask);
1314 RTL_W16(tp, IntrMask, tp->irq_mask);
1317 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1319 rtl_irq_disable(tp);
1320 rtl_ack_events(tp, 0xffffffff);
1324 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1326 struct phy_device *phydev = tp->phydev;
1328 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1329 tp->mac_version == RTL_GIGA_MAC_VER_38) {
1330 if (phydev->speed == SPEED_1000) {
1331 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1332 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1333 } else if (phydev->speed == SPEED_100) {
1334 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1335 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1337 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1338 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1340 rtl_reset_packet_filter(tp);
1341 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1342 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1343 if (phydev->speed == SPEED_1000) {
1344 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1345 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1347 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1348 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1350 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1351 if (phydev->speed == SPEED_10) {
1352 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02);
1353 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a);
1355 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
1360 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1362 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1364 struct rtl8169_private *tp = netdev_priv(dev);
1366 wol->supported = WAKE_ANY;
1367 wol->wolopts = tp->saved_wolopts;
1370 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1372 static const struct {
1377 { WAKE_PHY, Config3, LinkUp },
1378 { WAKE_UCAST, Config5, UWF },
1379 { WAKE_BCAST, Config5, BWF },
1380 { WAKE_MCAST, Config5, MWF },
1381 { WAKE_ANY, Config5, LanWake },
1382 { WAKE_MAGIC, Config3, MagicPacket }
1384 unsigned int i, tmp = ARRAY_SIZE(cfg);
1387 rtl_unlock_config_regs(tp);
1389 if (rtl_is_8168evl_up(tp)) {
1391 if (wolopts & WAKE_MAGIC)
1392 rtl_eri_set_bits(tp, 0x0dc, MagicPacket_v2);
1394 rtl_eri_clear_bits(tp, 0x0dc, MagicPacket_v2);
1395 } else if (rtl_is_8125(tp)) {
1397 if (wolopts & WAKE_MAGIC)
1398 r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0));
1400 r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0);
1403 for (i = 0; i < tmp; i++) {
1404 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
1405 if (wolopts & cfg[i].opt)
1406 options |= cfg[i].mask;
1407 RTL_W8(tp, cfg[i].reg, options);
1410 switch (tp->mac_version) {
1411 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
1412 options = RTL_R8(tp, Config1) & ~PMEnable;
1414 options |= PMEnable;
1415 RTL_W8(tp, Config1, options);
1417 case RTL_GIGA_MAC_VER_34:
1418 case RTL_GIGA_MAC_VER_37:
1419 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63:
1420 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
1422 options |= PME_SIGNAL;
1423 RTL_W8(tp, Config2, options);
1429 rtl_lock_config_regs(tp);
1431 device_set_wakeup_enable(tp_to_dev(tp), wolopts);
1432 rtl_set_d3_pll_down(tp, !wolopts);
1433 tp->dev->wol_enabled = wolopts ? 1 : 0;
1436 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1438 struct rtl8169_private *tp = netdev_priv(dev);
1440 if (wol->wolopts & ~WAKE_ANY)
1443 tp->saved_wolopts = wol->wolopts;
1444 __rtl8169_set_wol(tp, tp->saved_wolopts);
1449 static void rtl8169_get_drvinfo(struct net_device *dev,
1450 struct ethtool_drvinfo *info)
1452 struct rtl8169_private *tp = netdev_priv(dev);
1453 struct rtl_fw *rtl_fw = tp->rtl_fw;
1455 strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
1456 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1457 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1459 strlcpy(info->fw_version, rtl_fw->version,
1460 sizeof(info->fw_version));
1463 static int rtl8169_get_regs_len(struct net_device *dev)
1465 return R8169_REGS_SIZE;
1468 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1469 netdev_features_t features)
1471 struct rtl8169_private *tp = netdev_priv(dev);
1473 if (dev->mtu > TD_MSS_MAX)
1474 features &= ~NETIF_F_ALL_TSO;
1476 if (dev->mtu > ETH_DATA_LEN &&
1477 tp->mac_version > RTL_GIGA_MAC_VER_06)
1478 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_ALL_TSO);
1483 static void rtl_set_rx_config_features(struct rtl8169_private *tp,
1484 netdev_features_t features)
1486 u32 rx_config = RTL_R32(tp, RxConfig);
1488 if (features & NETIF_F_RXALL)
1489 rx_config |= RX_CONFIG_ACCEPT_ERR_MASK;
1491 rx_config &= ~RX_CONFIG_ACCEPT_ERR_MASK;
1493 if (rtl_is_8125(tp)) {
1494 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1495 rx_config |= RX_VLAN_8125;
1497 rx_config &= ~RX_VLAN_8125;
1500 RTL_W32(tp, RxConfig, rx_config);
1503 static int rtl8169_set_features(struct net_device *dev,
1504 netdev_features_t features)
1506 struct rtl8169_private *tp = netdev_priv(dev);
1508 rtl_set_rx_config_features(tp, features);
1510 if (features & NETIF_F_RXCSUM)
1511 tp->cp_cmd |= RxChkSum;
1513 tp->cp_cmd &= ~RxChkSum;
1515 if (!rtl_is_8125(tp)) {
1516 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1517 tp->cp_cmd |= RxVlan;
1519 tp->cp_cmd &= ~RxVlan;
1522 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1528 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1530 return (skb_vlan_tag_present(skb)) ?
1531 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1534 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1536 u32 opts2 = le32_to_cpu(desc->opts2);
1538 if (opts2 & RxVlanTag)
1539 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1542 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1545 struct rtl8169_private *tp = netdev_priv(dev);
1546 u32 __iomem *data = tp->mmio_addr;
1550 for (i = 0; i < R8169_REGS_SIZE; i += 4)
1551 memcpy_fromio(dw++, data++, 4);
1554 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1561 "tx_single_collisions",
1562 "tx_multi_collisions",
1570 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1574 return ARRAY_SIZE(rtl8169_gstrings);
1580 DECLARE_RTL_COND(rtl_counters_cond)
1582 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
1585 static void rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
1587 u32 cmd = lower_32_bits(tp->counters_phys_addr);
1589 RTL_W32(tp, CounterAddrHigh, upper_32_bits(tp->counters_phys_addr));
1591 RTL_W32(tp, CounterAddrLow, cmd);
1592 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
1594 rtl_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
1597 static void rtl8169_update_counters(struct rtl8169_private *tp)
1599 u8 val = RTL_R8(tp, ChipCmd);
1602 * Some chips are unable to dump tally counters when the receiver
1603 * is disabled. If 0xff chip may be in a PCI power-save state.
1605 if (val & CmdRxEnb && val != 0xff)
1606 rtl8169_do_counters(tp, CounterDump);
1609 static void rtl8169_init_counter_offsets(struct rtl8169_private *tp)
1611 struct rtl8169_counters *counters = tp->counters;
1614 * rtl8169_init_counter_offsets is called from rtl_open. On chip
1615 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1616 * reset by a power cycle, while the counter values collected by the
1617 * driver are reset at every driver unload/load cycle.
1619 * To make sure the HW values returned by @get_stats64 match the SW
1620 * values, we collect the initial values at first open(*) and use them
1621 * as offsets to normalize the values returned by @get_stats64.
1623 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1624 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1625 * set at open time by rtl_hw_start.
1628 if (tp->tc_offset.inited)
1631 if (tp->mac_version >= RTL_GIGA_MAC_VER_19) {
1632 rtl8169_do_counters(tp, CounterReset);
1634 rtl8169_update_counters(tp);
1635 tp->tc_offset.tx_errors = counters->tx_errors;
1636 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1637 tp->tc_offset.tx_aborted = counters->tx_aborted;
1638 tp->tc_offset.rx_missed = counters->rx_missed;
1641 tp->tc_offset.inited = true;
1644 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1645 struct ethtool_stats *stats, u64 *data)
1647 struct rtl8169_private *tp = netdev_priv(dev);
1648 struct rtl8169_counters *counters;
1650 counters = tp->counters;
1651 rtl8169_update_counters(tp);
1653 data[0] = le64_to_cpu(counters->tx_packets);
1654 data[1] = le64_to_cpu(counters->rx_packets);
1655 data[2] = le64_to_cpu(counters->tx_errors);
1656 data[3] = le32_to_cpu(counters->rx_errors);
1657 data[4] = le16_to_cpu(counters->rx_missed);
1658 data[5] = le16_to_cpu(counters->align_errors);
1659 data[6] = le32_to_cpu(counters->tx_one_collision);
1660 data[7] = le32_to_cpu(counters->tx_multi_collision);
1661 data[8] = le64_to_cpu(counters->rx_unicast);
1662 data[9] = le64_to_cpu(counters->rx_broadcast);
1663 data[10] = le32_to_cpu(counters->rx_multicast);
1664 data[11] = le16_to_cpu(counters->tx_aborted);
1665 data[12] = le16_to_cpu(counters->tx_underun);
1668 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1672 memcpy(data, rtl8169_gstrings, sizeof(rtl8169_gstrings));
1678 * Interrupt coalescing
1680 * > 1 - the availability of the IntrMitigate (0xe2) register through the
1681 * > 8169, 8168 and 810x line of chipsets
1683 * 8169, 8168, and 8136(810x) serial chipsets support it.
1685 * > 2 - the Tx timer unit at gigabit speed
1687 * The unit of the timer depends on both the speed and the setting of CPlusCmd
1688 * (0xe0) bit 1 and bit 0.
1691 * bit[1:0] \ speed 1000M 100M 10M
1692 * 0 0 320ns 2.56us 40.96us
1693 * 0 1 2.56us 20.48us 327.7us
1694 * 1 0 5.12us 40.96us 655.4us
1695 * 1 1 10.24us 81.92us 1.31ms
1698 * bit[1:0] \ speed 1000M 100M 10M
1699 * 0 0 5us 2.56us 40.96us
1700 * 0 1 40us 20.48us 327.7us
1701 * 1 0 80us 40.96us 655.4us
1702 * 1 1 160us 81.92us 1.31ms
1705 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
1706 struct rtl_coalesce_info {
1711 /* produce array with base delay *1, *8, *8*2, *8*2*2 */
1712 #define COALESCE_DELAY(d) { (d), 8 * (d), 16 * (d), 32 * (d) }
1714 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1715 { SPEED_1000, COALESCE_DELAY(320) },
1716 { SPEED_100, COALESCE_DELAY(2560) },
1717 { SPEED_10, COALESCE_DELAY(40960) },
1721 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1722 { SPEED_1000, COALESCE_DELAY(5000) },
1723 { SPEED_100, COALESCE_DELAY(2560) },
1724 { SPEED_10, COALESCE_DELAY(40960) },
1727 #undef COALESCE_DELAY
1729 /* get rx/tx scale vector corresponding to current speed */
1730 static const struct rtl_coalesce_info *
1731 rtl_coalesce_info(struct rtl8169_private *tp)
1733 const struct rtl_coalesce_info *ci;
1735 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1736 ci = rtl_coalesce_info_8169;
1738 ci = rtl_coalesce_info_8168_8136;
1740 /* if speed is unknown assume highest one */
1741 if (tp->phydev->speed == SPEED_UNKNOWN)
1744 for (; ci->speed; ci++) {
1745 if (tp->phydev->speed == ci->speed)
1749 return ERR_PTR(-ELNRNG);
1752 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1754 struct rtl8169_private *tp = netdev_priv(dev);
1755 const struct rtl_coalesce_info *ci;
1756 u32 scale, c_us, c_fr;
1759 if (rtl_is_8125(tp))
1762 memset(ec, 0, sizeof(*ec));
1764 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1765 ci = rtl_coalesce_info(tp);
1769 scale = ci->scale_nsecs[tp->cp_cmd & INTT_MASK];
1771 intrmit = RTL_R16(tp, IntrMitigate);
1773 c_us = FIELD_GET(RTL_COALESCE_TX_USECS, intrmit);
1774 ec->tx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000);
1776 c_fr = FIELD_GET(RTL_COALESCE_TX_FRAMES, intrmit);
1777 /* ethtool_coalesce states usecs and max_frames must not both be 0 */
1778 ec->tx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1;
1780 c_us = FIELD_GET(RTL_COALESCE_RX_USECS, intrmit);
1781 ec->rx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000);
1783 c_fr = FIELD_GET(RTL_COALESCE_RX_FRAMES, intrmit);
1784 ec->rx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1;
1789 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, usec) */
1790 static int rtl_coalesce_choose_scale(struct rtl8169_private *tp, u32 usec,
1793 const struct rtl_coalesce_info *ci;
1796 ci = rtl_coalesce_info(tp);
1800 for (i = 0; i < 4; i++) {
1801 if (usec <= ci->scale_nsecs[i] * RTL_COALESCE_T_MAX / 1000U) {
1803 return ci->scale_nsecs[i];
1810 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1812 struct rtl8169_private *tp = netdev_priv(dev);
1813 u32 tx_fr = ec->tx_max_coalesced_frames;
1814 u32 rx_fr = ec->rx_max_coalesced_frames;
1815 u32 coal_usec_max, units;
1816 u16 w = 0, cp01 = 0;
1819 if (rtl_is_8125(tp))
1822 if (rx_fr > RTL_COALESCE_FRAME_MAX || tx_fr > RTL_COALESCE_FRAME_MAX)
1825 coal_usec_max = max(ec->rx_coalesce_usecs, ec->tx_coalesce_usecs);
1826 scale = rtl_coalesce_choose_scale(tp, coal_usec_max, &cp01);
1830 /* Accept max_frames=1 we returned in rtl_get_coalesce. Accept it
1831 * not only when usecs=0 because of e.g. the following scenario:
1833 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
1834 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
1835 * - then user does `ethtool -C eth0 rx-usecs 100`
1837 * Since ethtool sends to kernel whole ethtool_coalesce settings,
1838 * if we want to ignore rx_frames then it has to be set to 0.
1845 /* HW requires time limit to be set if frame limit is set */
1846 if ((tx_fr && !ec->tx_coalesce_usecs) ||
1847 (rx_fr && !ec->rx_coalesce_usecs))
1850 w |= FIELD_PREP(RTL_COALESCE_TX_FRAMES, DIV_ROUND_UP(tx_fr, 4));
1851 w |= FIELD_PREP(RTL_COALESCE_RX_FRAMES, DIV_ROUND_UP(rx_fr, 4));
1853 units = DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000U, scale);
1854 w |= FIELD_PREP(RTL_COALESCE_TX_USECS, units);
1855 units = DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000U, scale);
1856 w |= FIELD_PREP(RTL_COALESCE_RX_USECS, units);
1858 RTL_W16(tp, IntrMitigate, w);
1860 /* Meaning of PktCntrDisable bit changed from RTL8168e-vl */
1861 if (rtl_is_8168evl_up(tp)) {
1862 if (!rx_fr && !tx_fr)
1863 /* disable packet counter */
1864 tp->cp_cmd |= PktCntrDisable;
1866 tp->cp_cmd &= ~PktCntrDisable;
1869 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
1870 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1876 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data)
1878 struct rtl8169_private *tp = netdev_priv(dev);
1880 if (!rtl_supports_eee(tp))
1883 return phy_ethtool_get_eee(tp->phydev, data);
1886 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data)
1888 struct rtl8169_private *tp = netdev_priv(dev);
1891 if (!rtl_supports_eee(tp))
1894 ret = phy_ethtool_set_eee(tp->phydev, data);
1897 tp->eee_adv = phy_read_mmd(dev->phydev, MDIO_MMD_AN,
1902 static void rtl8169_get_ringparam(struct net_device *dev,
1903 struct ethtool_ringparam *data)
1905 data->rx_max_pending = NUM_RX_DESC;
1906 data->rx_pending = NUM_RX_DESC;
1907 data->tx_max_pending = NUM_TX_DESC;
1908 data->tx_pending = NUM_TX_DESC;
1911 static void rtl8169_get_pauseparam(struct net_device *dev,
1912 struct ethtool_pauseparam *data)
1914 struct rtl8169_private *tp = netdev_priv(dev);
1915 bool tx_pause, rx_pause;
1917 phy_get_pause(tp->phydev, &tx_pause, &rx_pause);
1919 data->autoneg = tp->phydev->autoneg;
1920 data->tx_pause = tx_pause ? 1 : 0;
1921 data->rx_pause = rx_pause ? 1 : 0;
1924 static int rtl8169_set_pauseparam(struct net_device *dev,
1925 struct ethtool_pauseparam *data)
1927 struct rtl8169_private *tp = netdev_priv(dev);
1929 if (dev->mtu > ETH_DATA_LEN)
1932 phy_set_asym_pause(tp->phydev, data->rx_pause, data->tx_pause);
1937 static const struct ethtool_ops rtl8169_ethtool_ops = {
1938 .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
1939 ETHTOOL_COALESCE_MAX_FRAMES,
1940 .get_drvinfo = rtl8169_get_drvinfo,
1941 .get_regs_len = rtl8169_get_regs_len,
1942 .get_link = ethtool_op_get_link,
1943 .get_coalesce = rtl_get_coalesce,
1944 .set_coalesce = rtl_set_coalesce,
1945 .get_regs = rtl8169_get_regs,
1946 .get_wol = rtl8169_get_wol,
1947 .set_wol = rtl8169_set_wol,
1948 .get_strings = rtl8169_get_strings,
1949 .get_sset_count = rtl8169_get_sset_count,
1950 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1951 .get_ts_info = ethtool_op_get_ts_info,
1952 .nway_reset = phy_ethtool_nway_reset,
1953 .get_eee = rtl8169_get_eee,
1954 .set_eee = rtl8169_set_eee,
1955 .get_link_ksettings = phy_ethtool_get_link_ksettings,
1956 .set_link_ksettings = phy_ethtool_set_link_ksettings,
1957 .get_ringparam = rtl8169_get_ringparam,
1958 .get_pauseparam = rtl8169_get_pauseparam,
1959 .set_pauseparam = rtl8169_set_pauseparam,
1962 static void rtl_enable_eee(struct rtl8169_private *tp)
1964 struct phy_device *phydev = tp->phydev;
1967 /* respect EEE advertisement the user may have set */
1968 if (tp->eee_adv >= 0)
1971 adv = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
1974 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, adv);
1977 static enum mac_version rtl8169_get_mac_version(u16 xid, bool gmii)
1980 * The driver currently handles the 8168Bf and the 8168Be identically
1981 * but they can be identified more specifically through the test below
1984 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1986 * Same thing for the 8101Eb and the 8101Ec:
1988 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1990 static const struct rtl_mac_info {
1993 enum mac_version ver;
1996 { 0x7cf, 0x641, RTL_GIGA_MAC_VER_63 },
1999 { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 },
2000 { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 },
2003 { 0x7cf, 0x54b, RTL_GIGA_MAC_VER_53 },
2004 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52 },
2006 /* 8168EP family. */
2007 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 },
2008 { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 },
2009 { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 },
2012 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 },
2013 { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 },
2016 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 },
2017 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 },
2018 { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 },
2019 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 },
2022 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 },
2023 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 },
2024 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 },
2027 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 },
2028 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 },
2029 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 },
2032 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 },
2033 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 },
2035 /* 8168DP family. */
2036 /* It seems this early RTL8168dp version never made it to
2037 * the wild. Let's see whether somebody complains, if not
2038 * we'll remove support for this chip version completely.
2039 * { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 },
2041 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 },
2042 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 },
2045 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 },
2046 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 },
2047 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 },
2048 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 },
2049 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 },
2050 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 },
2051 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 },
2054 { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12 },
2055 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 },
2056 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 },
2059 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 },
2060 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 },
2061 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 },
2062 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 },
2063 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 },
2064 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 },
2065 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 },
2066 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 },
2067 { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13 },
2068 { 0x7cf, 0x240, RTL_GIGA_MAC_VER_14 },
2069 { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10 },
2070 { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16 },
2071 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 },
2072 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 },
2073 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16 },
2074 /* FIXME: where did these entries come from ? -- FR
2075 * Not even r8101 vendor driver knows these id's,
2076 * so let's disable detection for now. -- HK
2077 * { 0xfc8, 0x388, RTL_GIGA_MAC_VER_13 },
2078 * { 0xfc8, 0x308, RTL_GIGA_MAC_VER_13 },
2082 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 },
2083 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 },
2084 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 },
2085 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 },
2086 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 },
2089 { 0x000, 0x000, RTL_GIGA_MAC_NONE }
2091 const struct rtl_mac_info *p = mac_info;
2092 enum mac_version ver;
2094 while ((xid & p->mask) != p->val)
2098 if (ver != RTL_GIGA_MAC_NONE && !gmii) {
2099 if (ver == RTL_GIGA_MAC_VER_42)
2100 ver = RTL_GIGA_MAC_VER_43;
2101 else if (ver == RTL_GIGA_MAC_VER_45)
2102 ver = RTL_GIGA_MAC_VER_47;
2103 else if (ver == RTL_GIGA_MAC_VER_46)
2104 ver = RTL_GIGA_MAC_VER_48;
2110 static void rtl_release_firmware(struct rtl8169_private *tp)
2113 rtl_fw_release_firmware(tp->rtl_fw);
2119 void r8169_apply_firmware(struct rtl8169_private *tp)
2123 /* TODO: release firmware if rtl_fw_write_firmware signals failure. */
2125 rtl_fw_write_firmware(tp, tp->rtl_fw);
2126 /* At least one firmware doesn't reset tp->ocp_base. */
2127 tp->ocp_base = OCP_STD_PHY_BASE;
2129 /* PHY soft reset may still be in progress */
2130 phy_read_poll_timeout(tp->phydev, MII_BMCR, val,
2131 !(val & BMCR_RESET),
2132 50000, 600000, true);
2136 static void rtl8168_config_eee_mac(struct rtl8169_private *tp)
2138 /* Adjust EEE LED frequency */
2139 if (tp->mac_version != RTL_GIGA_MAC_VER_38)
2140 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
2142 rtl_eri_set_bits(tp, 0x1b0, 0x0003);
2145 static void rtl8125a_config_eee_mac(struct rtl8169_private *tp)
2147 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0));
2148 r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1));
2151 static void rtl8125_set_eee_txidle_timer(struct rtl8169_private *tp)
2153 RTL_W16(tp, EEE_TXIDLE_TIMER_8125, tp->dev->mtu + ETH_HLEN + 0x20);
2156 static void rtl8125b_config_eee_mac(struct rtl8169_private *tp)
2158 rtl8125_set_eee_txidle_timer(tp);
2159 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0));
2162 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, const u8 *addr)
2164 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, get_unaligned_le32(addr));
2165 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, get_unaligned_le16(addr + 4));
2166 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, get_unaligned_le16(addr) << 16);
2167 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, get_unaligned_le32(addr + 2));
2170 u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp)
2172 u16 data1, data2, ioffset;
2174 r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
2175 data1 = r8168_mac_ocp_read(tp, 0xdd02);
2176 data2 = r8168_mac_ocp_read(tp, 0xdd00);
2178 ioffset = (data2 >> 1) & 0x7ff8;
2179 ioffset |= data2 & 0x0007;
2186 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
2188 set_bit(flag, tp->wk.flags);
2189 schedule_work(&tp->wk.work);
2192 static void rtl8169_init_phy(struct rtl8169_private *tp)
2194 r8169_hw_phy_config(tp, tp->phydev, tp->mac_version);
2196 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2197 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2198 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
2199 /* set undocumented MAC Reg C+CR Offset 0x82h */
2200 RTL_W8(tp, 0x82, 0x01);
2203 if (tp->mac_version == RTL_GIGA_MAC_VER_05 &&
2204 tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE &&
2205 tp->pci_dev->subsystem_device == 0xe000)
2206 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b);
2208 /* We may have called phy_speed_down before */
2209 phy_speed_up(tp->phydev);
2211 if (rtl_supports_eee(tp))
2214 genphy_soft_reset(tp->phydev);
2217 static void rtl_rar_set(struct rtl8169_private *tp, const u8 *addr)
2219 rtl_unlock_config_regs(tp);
2221 RTL_W32(tp, MAC4, get_unaligned_le16(addr + 4));
2224 RTL_W32(tp, MAC0, get_unaligned_le32(addr));
2227 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
2228 rtl_rar_exgmac_set(tp, addr);
2230 rtl_lock_config_regs(tp);
2233 static int rtl_set_mac_address(struct net_device *dev, void *p)
2235 struct rtl8169_private *tp = netdev_priv(dev);
2238 ret = eth_mac_addr(dev, p);
2242 rtl_rar_set(tp, dev->dev_addr);
2247 static void rtl_wol_enable_rx(struct rtl8169_private *tp)
2249 if (tp->mac_version >= RTL_GIGA_MAC_VER_25)
2250 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
2251 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
2254 static void rtl_prepare_power_down(struct rtl8169_private *tp)
2256 if (tp->dash_type != RTL_DASH_NONE)
2259 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
2260 tp->mac_version == RTL_GIGA_MAC_VER_33)
2261 rtl_ephy_write(tp, 0x19, 0xff64);
2263 if (device_may_wakeup(tp_to_dev(tp))) {
2264 phy_speed_down(tp->phydev, false);
2265 rtl_wol_enable_rx(tp);
2269 static void rtl_init_rxcfg(struct rtl8169_private *tp)
2271 switch (tp->mac_version) {
2272 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
2273 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
2274 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
2276 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
2277 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
2278 case RTL_GIGA_MAC_VER_38:
2279 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
2281 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53:
2282 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
2284 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_63:
2285 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST);
2288 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
2293 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2295 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
2298 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
2300 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2301 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
2304 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
2306 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2307 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
2310 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
2312 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2315 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
2317 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2320 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
2322 RTL_W8(tp, MaxTxPacketSize, 0x24);
2323 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2324 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
2327 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
2329 RTL_W8(tp, MaxTxPacketSize, 0x3f);
2330 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2331 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
2334 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
2336 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
2339 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
2341 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
2344 static void rtl_jumbo_config(struct rtl8169_private *tp)
2346 bool jumbo = tp->dev->mtu > ETH_DATA_LEN;
2349 rtl_unlock_config_regs(tp);
2350 switch (tp->mac_version) {
2351 case RTL_GIGA_MAC_VER_12:
2352 case RTL_GIGA_MAC_VER_17:
2355 r8168b_1_hw_jumbo_enable(tp);
2357 r8168b_1_hw_jumbo_disable(tp);
2360 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26:
2363 r8168c_hw_jumbo_enable(tp);
2365 r8168c_hw_jumbo_disable(tp);
2368 case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28:
2370 r8168dp_hw_jumbo_enable(tp);
2372 r8168dp_hw_jumbo_disable(tp);
2374 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33:
2376 r8168e_hw_jumbo_enable(tp);
2378 r8168e_hw_jumbo_disable(tp);
2383 rtl_lock_config_regs(tp);
2385 if (pci_is_pcie(tp->pci_dev) && tp->supports_gmii)
2386 pcie_set_readrq(tp->pci_dev, readrq);
2388 /* Chip doesn't support pause in jumbo mode */
2390 linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT,
2391 tp->phydev->advertising);
2392 linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
2393 tp->phydev->advertising);
2394 phy_start_aneg(tp->phydev);
2398 DECLARE_RTL_COND(rtl_chipcmd_cond)
2400 return RTL_R8(tp, ChipCmd) & CmdReset;
2403 static void rtl_hw_reset(struct rtl8169_private *tp)
2405 RTL_W8(tp, ChipCmd, CmdReset);
2407 rtl_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
2410 static void rtl_request_firmware(struct rtl8169_private *tp)
2412 struct rtl_fw *rtl_fw;
2414 /* firmware loaded already or no firmware available */
2415 if (tp->rtl_fw || !tp->fw_name)
2418 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
2422 rtl_fw->phy_write = rtl_writephy;
2423 rtl_fw->phy_read = rtl_readphy;
2424 rtl_fw->mac_mcu_write = mac_mcu_write;
2425 rtl_fw->mac_mcu_read = mac_mcu_read;
2426 rtl_fw->fw_name = tp->fw_name;
2427 rtl_fw->dev = tp_to_dev(tp);
2429 if (rtl_fw_request_firmware(rtl_fw))
2432 tp->rtl_fw = rtl_fw;
2435 static void rtl_rx_close(struct rtl8169_private *tp)
2437 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
2440 DECLARE_RTL_COND(rtl_npq_cond)
2442 return RTL_R8(tp, TxPoll) & NPQ;
2445 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
2447 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
2450 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
2452 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
2455 DECLARE_RTL_COND(rtl_rxtx_empty_cond_2)
2457 /* IntrMitigate has new functionality on RTL8125 */
2458 return (RTL_R16(tp, IntrMitigate) & 0x0103) == 0x0103;
2461 static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp)
2463 switch (tp->mac_version) {
2464 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53:
2465 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42);
2466 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2468 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_61:
2469 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2471 case RTL_GIGA_MAC_VER_63:
2472 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
2473 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2474 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond_2, 100, 42);
2481 static void rtl_enable_rxdvgate(struct rtl8169_private *tp)
2483 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
2485 rtl_wait_txrx_fifo_empty(tp);
2488 static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
2490 u32 val = TX_DMA_BURST << TxDMAShift |
2491 InterFrameGap << TxInterFrameGapShift;
2493 if (rtl_is_8168evl_up(tp))
2494 val |= TXCFG_AUTO_FIFO;
2496 RTL_W32(tp, TxConfig, val);
2499 static void rtl_set_rx_max_size(struct rtl8169_private *tp)
2501 /* Low hurts. Let's disable the filtering. */
2502 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
2505 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
2508 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
2509 * register to be written before TxDescAddrLow to work.
2510 * Switching from MMIO to I/O access fixes the issue as well.
2512 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
2513 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
2514 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
2515 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
2518 static void rtl8169_set_magic_reg(struct rtl8169_private *tp)
2522 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
2524 else if (tp->mac_version == RTL_GIGA_MAC_VER_06)
2529 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz)
2532 RTL_W32(tp, 0x7c, val);
2535 static void rtl_set_rx_mode(struct net_device *dev)
2537 u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast;
2538 /* Multicast hash filter */
2539 u32 mc_filter[2] = { 0xffffffff, 0xffffffff };
2540 struct rtl8169_private *tp = netdev_priv(dev);
2543 if (dev->flags & IFF_PROMISC) {
2544 rx_mode |= AcceptAllPhys;
2545 } else if (netdev_mc_count(dev) > MC_FILTER_LIMIT ||
2546 dev->flags & IFF_ALLMULTI ||
2547 tp->mac_version == RTL_GIGA_MAC_VER_35) {
2548 /* accept all multicasts */
2549 } else if (netdev_mc_empty(dev)) {
2550 rx_mode &= ~AcceptMulticast;
2552 struct netdev_hw_addr *ha;
2554 mc_filter[1] = mc_filter[0] = 0;
2555 netdev_for_each_mc_addr(ha, dev) {
2556 u32 bit_nr = eth_hw_addr_crc(ha) >> 26;
2557 mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31);
2560 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
2562 mc_filter[0] = swab32(mc_filter[1]);
2563 mc_filter[1] = swab32(tmp);
2567 RTL_W32(tp, MAR0 + 4, mc_filter[1]);
2568 RTL_W32(tp, MAR0 + 0, mc_filter[0]);
2570 tmp = RTL_R32(tp, RxConfig);
2571 RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode);
2574 DECLARE_RTL_COND(rtl_csiar_cond)
2576 return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
2579 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
2581 u32 func = PCI_FUNC(tp->pci_dev->devfn);
2583 RTL_W32(tp, CSIDR, value);
2584 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
2585 CSIAR_BYTE_ENABLE | func << 16);
2587 rtl_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
2590 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
2592 u32 func = PCI_FUNC(tp->pci_dev->devfn);
2594 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
2597 return rtl_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
2598 RTL_R32(tp, CSIDR) : ~0;
2601 static void rtl_set_aspm_entry_latency(struct rtl8169_private *tp, u8 val)
2603 struct pci_dev *pdev = tp->pci_dev;
2606 /* According to Realtek the value at config space address 0x070f
2607 * controls the L0s/L1 entrance latency. We try standard ECAM access
2608 * first and if it fails fall back to CSI.
2609 * bit 0..2: L0: 0 = 1us, 1 = 2us .. 6 = 7us, 7 = 7us (no typo)
2610 * bit 3..5: L1: 0 = 1us, 1 = 2us .. 6 = 64us, 7 = 64us
2612 if (pdev->cfg_size > 0x070f &&
2613 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
2616 netdev_notice_once(tp->dev,
2617 "No native access to PCI extended config space, falling back to CSI\n");
2618 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
2619 rtl_csi_write(tp, 0x070c, csi | val << 24);
2622 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
2624 /* L0 7us, L1 16us */
2625 rtl_set_aspm_entry_latency(tp, 0x27);
2629 unsigned int offset;
2634 static void __rtl_ephy_init(struct rtl8169_private *tp,
2635 const struct ephy_info *e, int len)
2640 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
2641 rtl_ephy_write(tp, e->offset, w);
2646 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a))
2648 static void rtl_disable_clock_request(struct rtl8169_private *tp)
2650 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
2651 PCI_EXP_LNKCTL_CLKREQ_EN);
2654 static void rtl_enable_clock_request(struct rtl8169_private *tp)
2656 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
2657 PCI_EXP_LNKCTL_CLKREQ_EN);
2660 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp)
2662 /* work around an issue when PCI reset occurs during L2/L3 state */
2663 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23);
2666 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
2668 /* Don't enable ASPM in the chip if OS can't control ASPM */
2669 if (enable && tp->aspm_manageable) {
2670 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);
2671 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);
2673 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
2674 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
2680 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat,
2681 u16 tx_stat, u16 rx_dyn, u16 tx_dyn)
2683 /* Usage of dynamic vs. static FIFO is controlled by bit
2684 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known.
2686 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn);
2687 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn);
2690 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp,
2693 /* FIFO thresholds for pause flow control */
2694 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low);
2695 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high);
2698 static void rtl_hw_start_8168b(struct rtl8169_private *tp)
2700 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2703 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
2705 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
2707 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2709 rtl_disable_clock_request(tp);
2712 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
2714 static const struct ephy_info e_info_8168cp[] = {
2715 { 0x01, 0, 0x0001 },
2716 { 0x02, 0x0800, 0x1000 },
2717 { 0x03, 0, 0x0042 },
2718 { 0x06, 0x0080, 0x0000 },
2722 rtl_set_def_aspm_entry_latency(tp);
2724 rtl_ephy_init(tp, e_info_8168cp);
2726 __rtl_hw_start_8168cp(tp);
2729 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
2731 rtl_set_def_aspm_entry_latency(tp);
2733 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2736 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
2738 rtl_set_def_aspm_entry_latency(tp);
2740 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2743 RTL_W8(tp, DBG_REG, 0x20);
2746 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
2748 static const struct ephy_info e_info_8168c_1[] = {
2749 { 0x02, 0x0800, 0x1000 },
2750 { 0x03, 0, 0x0002 },
2751 { 0x06, 0x0080, 0x0000 }
2754 rtl_set_def_aspm_entry_latency(tp);
2756 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
2758 rtl_ephy_init(tp, e_info_8168c_1);
2760 __rtl_hw_start_8168cp(tp);
2763 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
2765 static const struct ephy_info e_info_8168c_2[] = {
2766 { 0x01, 0, 0x0001 },
2767 { 0x03, 0x0400, 0x0020 }
2770 rtl_set_def_aspm_entry_latency(tp);
2772 rtl_ephy_init(tp, e_info_8168c_2);
2774 __rtl_hw_start_8168cp(tp);
2777 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
2779 rtl_set_def_aspm_entry_latency(tp);
2781 __rtl_hw_start_8168cp(tp);
2784 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
2786 rtl_set_def_aspm_entry_latency(tp);
2788 rtl_disable_clock_request(tp);
2791 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
2793 static const struct ephy_info e_info_8168d_4[] = {
2794 { 0x0b, 0x0000, 0x0048 },
2795 { 0x19, 0x0020, 0x0050 },
2796 { 0x0c, 0x0100, 0x0020 },
2797 { 0x10, 0x0004, 0x0000 },
2800 rtl_set_def_aspm_entry_latency(tp);
2802 rtl_ephy_init(tp, e_info_8168d_4);
2804 rtl_enable_clock_request(tp);
2807 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
2809 static const struct ephy_info e_info_8168e_1[] = {
2810 { 0x00, 0x0200, 0x0100 },
2811 { 0x00, 0x0000, 0x0004 },
2812 { 0x06, 0x0002, 0x0001 },
2813 { 0x06, 0x0000, 0x0030 },
2814 { 0x07, 0x0000, 0x2000 },
2815 { 0x00, 0x0000, 0x0020 },
2816 { 0x03, 0x5800, 0x2000 },
2817 { 0x03, 0x0000, 0x0001 },
2818 { 0x01, 0x0800, 0x1000 },
2819 { 0x07, 0x0000, 0x4000 },
2820 { 0x1e, 0x0000, 0x2000 },
2821 { 0x19, 0xffff, 0xfe6c },
2822 { 0x0a, 0x0000, 0x0040 }
2825 rtl_set_def_aspm_entry_latency(tp);
2827 rtl_ephy_init(tp, e_info_8168e_1);
2829 rtl_disable_clock_request(tp);
2831 /* Reset tx FIFO pointer */
2832 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
2833 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
2835 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
2838 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
2840 static const struct ephy_info e_info_8168e_2[] = {
2841 { 0x09, 0x0000, 0x0080 },
2842 { 0x19, 0x0000, 0x0224 },
2843 { 0x00, 0x0000, 0x0004 },
2844 { 0x0c, 0x3df0, 0x0200 },
2847 rtl_set_def_aspm_entry_latency(tp);
2849 rtl_ephy_init(tp, e_info_8168e_2);
2851 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
2852 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000);
2853 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
2854 rtl_eri_set_bits(tp, 0x0d4, 0x1f00);
2855 rtl_eri_set_bits(tp, 0x1d0, BIT(1));
2856 rtl_reset_packet_filter(tp);
2857 rtl_eri_set_bits(tp, 0x1b0, BIT(4));
2858 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
2859 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060);
2861 rtl_disable_clock_request(tp);
2863 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
2865 rtl8168_config_eee_mac(tp);
2867 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
2868 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
2869 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
2871 rtl_hw_aspm_clkreq_enable(tp, true);
2874 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
2876 rtl_set_def_aspm_entry_latency(tp);
2878 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
2879 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000);
2880 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
2881 rtl_reset_packet_filter(tp);
2882 rtl_eri_set_bits(tp, 0x1b0, BIT(4));
2883 rtl_eri_set_bits(tp, 0x1d0, BIT(4) | BIT(1));
2884 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
2885 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060);
2887 rtl_disable_clock_request(tp);
2889 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
2890 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
2891 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
2892 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
2894 rtl8168_config_eee_mac(tp);
2897 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
2899 static const struct ephy_info e_info_8168f_1[] = {
2900 { 0x06, 0x00c0, 0x0020 },
2901 { 0x08, 0x0001, 0x0002 },
2902 { 0x09, 0x0000, 0x0080 },
2903 { 0x19, 0x0000, 0x0224 },
2904 { 0x00, 0x0000, 0x0008 },
2905 { 0x0c, 0x3df0, 0x0200 },
2908 rtl_hw_start_8168f(tp);
2910 rtl_ephy_init(tp, e_info_8168f_1);
2912 rtl_eri_set_bits(tp, 0x0d4, 0x1f00);
2915 static void rtl_hw_start_8411(struct rtl8169_private *tp)
2917 static const struct ephy_info e_info_8168f_1[] = {
2918 { 0x06, 0x00c0, 0x0020 },
2919 { 0x0f, 0xffff, 0x5200 },
2920 { 0x19, 0x0000, 0x0224 },
2921 { 0x00, 0x0000, 0x0008 },
2922 { 0x0c, 0x3df0, 0x0200 },
2925 rtl_hw_start_8168f(tp);
2926 rtl_pcie_state_l2l3_disable(tp);
2928 rtl_ephy_init(tp, e_info_8168f_1);
2930 rtl_eri_set_bits(tp, 0x0d4, 0x0c00);
2933 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
2935 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
2936 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
2938 rtl_set_def_aspm_entry_latency(tp);
2940 rtl_reset_packet_filter(tp);
2941 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f);
2943 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
2945 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
2946 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
2947 rtl_eri_set_bits(tp, 0x0d4, 0x1f80);
2949 rtl8168_config_eee_mac(tp);
2951 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06);
2952 rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
2954 rtl_pcie_state_l2l3_disable(tp);
2957 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
2959 static const struct ephy_info e_info_8168g_1[] = {
2960 { 0x00, 0x0008, 0x0000 },
2961 { 0x0c, 0x3ff0, 0x0820 },
2962 { 0x1e, 0x0000, 0x0001 },
2963 { 0x19, 0x8000, 0x0000 }
2966 rtl_hw_start_8168g(tp);
2968 /* disable aspm and clock request before access ephy */
2969 rtl_hw_aspm_clkreq_enable(tp, false);
2970 rtl_ephy_init(tp, e_info_8168g_1);
2971 rtl_hw_aspm_clkreq_enable(tp, true);
2974 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
2976 static const struct ephy_info e_info_8168g_2[] = {
2977 { 0x00, 0x0008, 0x0000 },
2978 { 0x0c, 0x3ff0, 0x0820 },
2979 { 0x19, 0xffff, 0x7c00 },
2980 { 0x1e, 0xffff, 0x20eb },
2981 { 0x0d, 0xffff, 0x1666 },
2982 { 0x00, 0xffff, 0x10a3 },
2983 { 0x06, 0xffff, 0xf050 },
2984 { 0x04, 0x0000, 0x0010 },
2985 { 0x1d, 0x4000, 0x0000 },
2988 rtl_hw_start_8168g(tp);
2990 /* disable aspm and clock request before access ephy */
2991 rtl_hw_aspm_clkreq_enable(tp, false);
2992 rtl_ephy_init(tp, e_info_8168g_2);
2995 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
2997 static const struct ephy_info e_info_8411_2[] = {
2998 { 0x00, 0x0008, 0x0000 },
2999 { 0x0c, 0x37d0, 0x0820 },
3000 { 0x1e, 0x0000, 0x0001 },
3001 { 0x19, 0x8021, 0x0000 },
3002 { 0x1e, 0x0000, 0x2000 },
3003 { 0x0d, 0x0100, 0x0200 },
3004 { 0x00, 0x0000, 0x0080 },
3005 { 0x06, 0x0000, 0x0010 },
3006 { 0x04, 0x0000, 0x0010 },
3007 { 0x1d, 0x0000, 0x4000 },
3010 rtl_hw_start_8168g(tp);
3012 /* disable aspm and clock request before access ephy */
3013 rtl_hw_aspm_clkreq_enable(tp, false);
3014 rtl_ephy_init(tp, e_info_8411_2);
3016 /* The following Realtek-provided magic fixes an issue with the RX unit
3017 * getting confused after the PHY having been powered-down.
3019 r8168_mac_ocp_write(tp, 0xFC28, 0x0000);
3020 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000);
3021 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000);
3022 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000);
3023 r8168_mac_ocp_write(tp, 0xFC30, 0x0000);
3024 r8168_mac_ocp_write(tp, 0xFC32, 0x0000);
3025 r8168_mac_ocp_write(tp, 0xFC34, 0x0000);
3026 r8168_mac_ocp_write(tp, 0xFC36, 0x0000);
3028 r8168_mac_ocp_write(tp, 0xFC26, 0x0000);
3030 r8168_mac_ocp_write(tp, 0xF800, 0xE008);
3031 r8168_mac_ocp_write(tp, 0xF802, 0xE00A);
3032 r8168_mac_ocp_write(tp, 0xF804, 0xE00C);
3033 r8168_mac_ocp_write(tp, 0xF806, 0xE00E);
3034 r8168_mac_ocp_write(tp, 0xF808, 0xE027);
3035 r8168_mac_ocp_write(tp, 0xF80A, 0xE04F);
3036 r8168_mac_ocp_write(tp, 0xF80C, 0xE05E);
3037 r8168_mac_ocp_write(tp, 0xF80E, 0xE065);
3038 r8168_mac_ocp_write(tp, 0xF810, 0xC602);
3039 r8168_mac_ocp_write(tp, 0xF812, 0xBE00);
3040 r8168_mac_ocp_write(tp, 0xF814, 0x0000);
3041 r8168_mac_ocp_write(tp, 0xF816, 0xC502);
3042 r8168_mac_ocp_write(tp, 0xF818, 0xBD00);
3043 r8168_mac_ocp_write(tp, 0xF81A, 0x074C);
3044 r8168_mac_ocp_write(tp, 0xF81C, 0xC302);
3045 r8168_mac_ocp_write(tp, 0xF81E, 0xBB00);
3046 r8168_mac_ocp_write(tp, 0xF820, 0x080A);
3047 r8168_mac_ocp_write(tp, 0xF822, 0x6420);
3048 r8168_mac_ocp_write(tp, 0xF824, 0x48C2);
3049 r8168_mac_ocp_write(tp, 0xF826, 0x8C20);
3050 r8168_mac_ocp_write(tp, 0xF828, 0xC516);
3051 r8168_mac_ocp_write(tp, 0xF82A, 0x64A4);
3052 r8168_mac_ocp_write(tp, 0xF82C, 0x49C0);
3053 r8168_mac_ocp_write(tp, 0xF82E, 0xF009);
3054 r8168_mac_ocp_write(tp, 0xF830, 0x74A2);
3055 r8168_mac_ocp_write(tp, 0xF832, 0x8CA5);
3056 r8168_mac_ocp_write(tp, 0xF834, 0x74A0);
3057 r8168_mac_ocp_write(tp, 0xF836, 0xC50E);
3058 r8168_mac_ocp_write(tp, 0xF838, 0x9CA2);
3059 r8168_mac_ocp_write(tp, 0xF83A, 0x1C11);
3060 r8168_mac_ocp_write(tp, 0xF83C, 0x9CA0);
3061 r8168_mac_ocp_write(tp, 0xF83E, 0xE006);
3062 r8168_mac_ocp_write(tp, 0xF840, 0x74F8);
3063 r8168_mac_ocp_write(tp, 0xF842, 0x48C4);
3064 r8168_mac_ocp_write(tp, 0xF844, 0x8CF8);
3065 r8168_mac_ocp_write(tp, 0xF846, 0xC404);
3066 r8168_mac_ocp_write(tp, 0xF848, 0xBC00);
3067 r8168_mac_ocp_write(tp, 0xF84A, 0xC403);
3068 r8168_mac_ocp_write(tp, 0xF84C, 0xBC00);
3069 r8168_mac_ocp_write(tp, 0xF84E, 0x0BF2);
3070 r8168_mac_ocp_write(tp, 0xF850, 0x0C0A);
3071 r8168_mac_ocp_write(tp, 0xF852, 0xE434);
3072 r8168_mac_ocp_write(tp, 0xF854, 0xD3C0);
3073 r8168_mac_ocp_write(tp, 0xF856, 0x49D9);
3074 r8168_mac_ocp_write(tp, 0xF858, 0xF01F);
3075 r8168_mac_ocp_write(tp, 0xF85A, 0xC526);
3076 r8168_mac_ocp_write(tp, 0xF85C, 0x64A5);
3077 r8168_mac_ocp_write(tp, 0xF85E, 0x1400);
3078 r8168_mac_ocp_write(tp, 0xF860, 0xF007);
3079 r8168_mac_ocp_write(tp, 0xF862, 0x0C01);
3080 r8168_mac_ocp_write(tp, 0xF864, 0x8CA5);
3081 r8168_mac_ocp_write(tp, 0xF866, 0x1C15);
3082 r8168_mac_ocp_write(tp, 0xF868, 0xC51B);
3083 r8168_mac_ocp_write(tp, 0xF86A, 0x9CA0);
3084 r8168_mac_ocp_write(tp, 0xF86C, 0xE013);
3085 r8168_mac_ocp_write(tp, 0xF86E, 0xC519);
3086 r8168_mac_ocp_write(tp, 0xF870, 0x74A0);
3087 r8168_mac_ocp_write(tp, 0xF872, 0x48C4);
3088 r8168_mac_ocp_write(tp, 0xF874, 0x8CA0);
3089 r8168_mac_ocp_write(tp, 0xF876, 0xC516);
3090 r8168_mac_ocp_write(tp, 0xF878, 0x74A4);
3091 r8168_mac_ocp_write(tp, 0xF87A, 0x48C8);
3092 r8168_mac_ocp_write(tp, 0xF87C, 0x48CA);
3093 r8168_mac_ocp_write(tp, 0xF87E, 0x9CA4);
3094 r8168_mac_ocp_write(tp, 0xF880, 0xC512);
3095 r8168_mac_ocp_write(tp, 0xF882, 0x1B00);
3096 r8168_mac_ocp_write(tp, 0xF884, 0x9BA0);
3097 r8168_mac_ocp_write(tp, 0xF886, 0x1B1C);
3098 r8168_mac_ocp_write(tp, 0xF888, 0x483F);
3099 r8168_mac_ocp_write(tp, 0xF88A, 0x9BA2);
3100 r8168_mac_ocp_write(tp, 0xF88C, 0x1B04);
3101 r8168_mac_ocp_write(tp, 0xF88E, 0xC508);
3102 r8168_mac_ocp_write(tp, 0xF890, 0x9BA0);
3103 r8168_mac_ocp_write(tp, 0xF892, 0xC505);
3104 r8168_mac_ocp_write(tp, 0xF894, 0xBD00);
3105 r8168_mac_ocp_write(tp, 0xF896, 0xC502);
3106 r8168_mac_ocp_write(tp, 0xF898, 0xBD00);
3107 r8168_mac_ocp_write(tp, 0xF89A, 0x0300);
3108 r8168_mac_ocp_write(tp, 0xF89C, 0x051E);
3109 r8168_mac_ocp_write(tp, 0xF89E, 0xE434);
3110 r8168_mac_ocp_write(tp, 0xF8A0, 0xE018);
3111 r8168_mac_ocp_write(tp, 0xF8A2, 0xE092);
3112 r8168_mac_ocp_write(tp, 0xF8A4, 0xDE20);
3113 r8168_mac_ocp_write(tp, 0xF8A6, 0xD3C0);
3114 r8168_mac_ocp_write(tp, 0xF8A8, 0xC50F);
3115 r8168_mac_ocp_write(tp, 0xF8AA, 0x76A4);
3116 r8168_mac_ocp_write(tp, 0xF8AC, 0x49E3);
3117 r8168_mac_ocp_write(tp, 0xF8AE, 0xF007);
3118 r8168_mac_ocp_write(tp, 0xF8B0, 0x49C0);
3119 r8168_mac_ocp_write(tp, 0xF8B2, 0xF103);
3120 r8168_mac_ocp_write(tp, 0xF8B4, 0xC607);
3121 r8168_mac_ocp_write(tp, 0xF8B6, 0xBE00);
3122 r8168_mac_ocp_write(tp, 0xF8B8, 0xC606);
3123 r8168_mac_ocp_write(tp, 0xF8BA, 0xBE00);
3124 r8168_mac_ocp_write(tp, 0xF8BC, 0xC602);
3125 r8168_mac_ocp_write(tp, 0xF8BE, 0xBE00);
3126 r8168_mac_ocp_write(tp, 0xF8C0, 0x0C4C);
3127 r8168_mac_ocp_write(tp, 0xF8C2, 0x0C28);
3128 r8168_mac_ocp_write(tp, 0xF8C4, 0x0C2C);
3129 r8168_mac_ocp_write(tp, 0xF8C6, 0xDC00);
3130 r8168_mac_ocp_write(tp, 0xF8C8, 0xC707);
3131 r8168_mac_ocp_write(tp, 0xF8CA, 0x1D00);
3132 r8168_mac_ocp_write(tp, 0xF8CC, 0x8DE2);
3133 r8168_mac_ocp_write(tp, 0xF8CE, 0x48C1);
3134 r8168_mac_ocp_write(tp, 0xF8D0, 0xC502);
3135 r8168_mac_ocp_write(tp, 0xF8D2, 0xBD00);
3136 r8168_mac_ocp_write(tp, 0xF8D4, 0x00AA);
3137 r8168_mac_ocp_write(tp, 0xF8D6, 0xE0C0);
3138 r8168_mac_ocp_write(tp, 0xF8D8, 0xC502);
3139 r8168_mac_ocp_write(tp, 0xF8DA, 0xBD00);
3140 r8168_mac_ocp_write(tp, 0xF8DC, 0x0132);
3142 r8168_mac_ocp_write(tp, 0xFC26, 0x8000);
3144 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743);
3145 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801);
3146 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9);
3147 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD);
3148 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25);
3149 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9);
3150 r8168_mac_ocp_write(tp, 0xFC36, 0x012D);
3152 rtl_hw_aspm_clkreq_enable(tp, true);
3155 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
3157 static const struct ephy_info e_info_8168h_1[] = {
3158 { 0x1e, 0x0800, 0x0001 },
3159 { 0x1d, 0x0000, 0x0800 },
3160 { 0x05, 0xffff, 0x2089 },
3161 { 0x06, 0xffff, 0x5881 },
3162 { 0x04, 0xffff, 0x854a },
3163 { 0x01, 0xffff, 0x068b }
3167 /* disable aspm and clock request before access ephy */
3168 rtl_hw_aspm_clkreq_enable(tp, false);
3169 rtl_ephy_init(tp, e_info_8168h_1);
3171 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3172 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
3174 rtl_set_def_aspm_entry_latency(tp);
3176 rtl_reset_packet_filter(tp);
3178 rtl_eri_set_bits(tp, 0xd4, 0x1f00);
3179 rtl_eri_set_bits(tp, 0xdc, 0x001c);
3181 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3183 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
3185 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3186 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3188 rtl8168_config_eee_mac(tp);
3190 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3191 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3193 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3195 rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
3197 rtl_pcie_state_l2l3_disable(tp);
3199 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff;
3200 if (rg_saw_cnt > 0) {
3203 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
3204 sw_cnt_1ms_ini &= 0x0fff;
3205 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);
3208 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);
3209 r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008);
3210 r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f);
3211 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);
3213 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
3214 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
3215 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
3216 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
3218 rtl_hw_aspm_clkreq_enable(tp, true);
3221 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
3223 rtl8168ep_stop_cmac(tp);
3225 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3226 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
3228 rtl_set_def_aspm_entry_latency(tp);
3230 rtl_reset_packet_filter(tp);
3232 rtl_eri_set_bits(tp, 0xd4, 0x1f80);
3234 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3236 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
3238 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3239 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3241 rtl8168_config_eee_mac(tp);
3243 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06);
3245 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3247 rtl_pcie_state_l2l3_disable(tp);
3250 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
3252 static const struct ephy_info e_info_8168ep_1[] = {
3253 { 0x00, 0xffff, 0x10ab },
3254 { 0x06, 0xffff, 0xf030 },
3255 { 0x08, 0xffff, 0x2006 },
3256 { 0x0d, 0xffff, 0x1666 },
3257 { 0x0c, 0x3ff0, 0x0000 }
3260 /* disable aspm and clock request before access ephy */
3261 rtl_hw_aspm_clkreq_enable(tp, false);
3262 rtl_ephy_init(tp, e_info_8168ep_1);
3264 rtl_hw_start_8168ep(tp);
3266 rtl_hw_aspm_clkreq_enable(tp, true);
3269 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
3271 static const struct ephy_info e_info_8168ep_2[] = {
3272 { 0x00, 0xffff, 0x10a3 },
3273 { 0x19, 0xffff, 0xfc00 },
3274 { 0x1e, 0xffff, 0x20ea }
3277 /* disable aspm and clock request before access ephy */
3278 rtl_hw_aspm_clkreq_enable(tp, false);
3279 rtl_ephy_init(tp, e_info_8168ep_2);
3281 rtl_hw_start_8168ep(tp);
3283 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3284 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3286 rtl_hw_aspm_clkreq_enable(tp, true);
3289 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
3291 static const struct ephy_info e_info_8168ep_3[] = {
3292 { 0x00, 0x0000, 0x0080 },
3293 { 0x0d, 0x0100, 0x0200 },
3294 { 0x19, 0x8021, 0x0000 },
3295 { 0x1e, 0x0000, 0x2000 },
3298 /* disable aspm and clock request before access ephy */
3299 rtl_hw_aspm_clkreq_enable(tp, false);
3300 rtl_ephy_init(tp, e_info_8168ep_3);
3302 rtl_hw_start_8168ep(tp);
3304 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3305 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3307 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271);
3308 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
3309 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);
3311 rtl_hw_aspm_clkreq_enable(tp, true);
3314 static void rtl_hw_start_8117(struct rtl8169_private *tp)
3316 static const struct ephy_info e_info_8117[] = {
3317 { 0x19, 0x0040, 0x1100 },
3318 { 0x59, 0x0040, 0x1100 },
3322 rtl8168ep_stop_cmac(tp);
3324 /* disable aspm and clock request before access ephy */
3325 rtl_hw_aspm_clkreq_enable(tp, false);
3326 rtl_ephy_init(tp, e_info_8117);
3328 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3329 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
3331 rtl_set_def_aspm_entry_latency(tp);
3333 rtl_reset_packet_filter(tp);
3335 rtl_eri_set_bits(tp, 0xd4, 0x1f90);
3337 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3339 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
3341 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3342 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3344 rtl8168_config_eee_mac(tp);
3346 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3347 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3349 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3351 rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
3353 rtl_pcie_state_l2l3_disable(tp);
3355 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff;
3356 if (rg_saw_cnt > 0) {
3359 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff;
3360 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);
3363 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);
3364 r8168_mac_ocp_write(tp, 0xea80, 0x0003);
3365 r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009);
3366 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);
3368 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
3369 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
3370 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
3371 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
3373 /* firmware is for MAC only */
3374 r8169_apply_firmware(tp);
3376 rtl_hw_aspm_clkreq_enable(tp, true);
3379 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
3381 static const struct ephy_info e_info_8102e_1[] = {
3382 { 0x01, 0, 0x6e65 },
3383 { 0x02, 0, 0x091f },
3384 { 0x03, 0, 0xc2f9 },
3385 { 0x06, 0, 0xafb5 },
3386 { 0x07, 0, 0x0e00 },
3387 { 0x19, 0, 0xec80 },
3388 { 0x01, 0, 0x2e65 },
3393 rtl_set_def_aspm_entry_latency(tp);
3395 RTL_W8(tp, DBG_REG, FIX_NAK_1);
3398 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
3399 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3401 cfg1 = RTL_R8(tp, Config1);
3402 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
3403 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
3405 rtl_ephy_init(tp, e_info_8102e_1);
3408 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
3410 rtl_set_def_aspm_entry_latency(tp);
3412 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
3413 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3416 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
3418 rtl_hw_start_8102e_2(tp);
3420 rtl_ephy_write(tp, 0x03, 0xc2f9);
3423 static void rtl_hw_start_8401(struct rtl8169_private *tp)
3425 static const struct ephy_info e_info_8401[] = {
3426 { 0x01, 0xffff, 0x6fe5 },
3427 { 0x03, 0xffff, 0x0599 },
3428 { 0x06, 0xffff, 0xaf25 },
3429 { 0x07, 0xffff, 0x8e68 },
3432 rtl_ephy_init(tp, e_info_8401);
3433 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3436 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
3438 static const struct ephy_info e_info_8105e_1[] = {
3439 { 0x07, 0, 0x4000 },
3440 { 0x19, 0, 0x0200 },
3441 { 0x19, 0, 0x0020 },
3442 { 0x1e, 0, 0x2000 },
3443 { 0x03, 0, 0x0001 },
3444 { 0x19, 0, 0x0100 },
3445 { 0x19, 0, 0x0004 },
3449 /* Force LAN exit from ASPM if Rx/Tx are not idle */
3450 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3452 /* Disable Early Tally Counter */
3453 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
3455 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
3456 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
3458 rtl_ephy_init(tp, e_info_8105e_1);
3460 rtl_pcie_state_l2l3_disable(tp);
3463 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
3465 rtl_hw_start_8105e_1(tp);
3466 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
3469 static void rtl_hw_start_8402(struct rtl8169_private *tp)
3471 static const struct ephy_info e_info_8402[] = {
3472 { 0x19, 0xffff, 0xff64 },
3476 rtl_set_def_aspm_entry_latency(tp);
3478 /* Force LAN exit from ASPM if Rx/Tx are not idle */
3479 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3481 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
3483 rtl_ephy_init(tp, e_info_8402);
3485 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06);
3486 rtl_reset_packet_filter(tp);
3487 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3488 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3489 rtl_w0w1_eri(tp, 0x0d4, 0x0e00, 0xff00);
3492 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3494 rtl_pcie_state_l2l3_disable(tp);
3497 static void rtl_hw_start_8106(struct rtl8169_private *tp)
3499 rtl_hw_aspm_clkreq_enable(tp, false);
3501 /* Force LAN exit from ASPM if Rx/Tx are not idle */
3502 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3504 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
3505 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
3506 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3508 /* L0 7us, L1 32us - needed to avoid issues with link-up detection */
3509 rtl_set_aspm_entry_latency(tp, 0x2f);
3511 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
3514 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3516 rtl_pcie_state_l2l3_disable(tp);
3517 rtl_hw_aspm_clkreq_enable(tp, true);
3520 DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond)
3522 return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13);
3525 static void rtl_hw_start_8125_common(struct rtl8169_private *tp)
3527 rtl_pcie_state_l2l3_disable(tp);
3529 RTL_W16(tp, 0x382, 0x221b);
3530 RTL_W8(tp, 0x4500, 0);
3531 RTL_W16(tp, 0x4800, 0);
3534 r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000);
3536 RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10);
3538 r8168_mac_ocp_write(tp, 0xc140, 0xffff);
3539 r8168_mac_ocp_write(tp, 0xc142, 0xffff);
3541 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9);
3542 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
3543 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);
3545 /* disable new tx descriptor format */
3546 r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000);
3548 if (tp->mac_version == RTL_GIGA_MAC_VER_63)
3549 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200);
3551 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400);
3553 if (tp->mac_version == RTL_GIGA_MAC_VER_63)
3554 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0000);
3556 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020);
3558 r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c);
3559 r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033);
3560 r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040);
3561 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030);
3562 r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000);
3563 r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001);
3564 r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403);
3565 r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0068);
3566 r8168_mac_ocp_modify(tp, 0xc0ac, 0x0080, 0x1f00);
3567 r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f);
3569 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000);
3570 r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001);
3572 r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000);
3573 RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030);
3575 r8168_mac_ocp_write(tp, 0xe098, 0xc302);
3577 rtl_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10);
3579 if (tp->mac_version == RTL_GIGA_MAC_VER_63)
3580 rtl8125b_config_eee_mac(tp);
3582 rtl8125a_config_eee_mac(tp);
3584 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
3588 static void rtl_hw_start_8125a_1(struct rtl8169_private *tp)
3590 static const struct ephy_info e_info_8125a_1[] = {
3591 { 0x01, 0xffff, 0xa812 },
3592 { 0x09, 0xffff, 0x520c },
3593 { 0x04, 0xffff, 0xd000 },
3594 { 0x0d, 0xffff, 0xf702 },
3595 { 0x0a, 0xffff, 0x8653 },
3596 { 0x06, 0xffff, 0x001e },
3597 { 0x08, 0xffff, 0x3595 },
3598 { 0x20, 0xffff, 0x9455 },
3599 { 0x21, 0xffff, 0x99ff },
3600 { 0x02, 0xffff, 0x6046 },
3601 { 0x29, 0xffff, 0xfe00 },
3602 { 0x23, 0xffff, 0xab62 },
3604 { 0x41, 0xffff, 0xa80c },
3605 { 0x49, 0xffff, 0x520c },
3606 { 0x44, 0xffff, 0xd000 },
3607 { 0x4d, 0xffff, 0xf702 },
3608 { 0x4a, 0xffff, 0x8653 },
3609 { 0x46, 0xffff, 0x001e },
3610 { 0x48, 0xffff, 0x3595 },
3611 { 0x60, 0xffff, 0x9455 },
3612 { 0x61, 0xffff, 0x99ff },
3613 { 0x42, 0xffff, 0x6046 },
3614 { 0x69, 0xffff, 0xfe00 },
3615 { 0x63, 0xffff, 0xab62 },
3618 rtl_set_def_aspm_entry_latency(tp);
3620 /* disable aspm and clock request before access ephy */
3621 rtl_hw_aspm_clkreq_enable(tp, false);
3622 rtl_ephy_init(tp, e_info_8125a_1);
3624 rtl_hw_start_8125_common(tp);
3625 rtl_hw_aspm_clkreq_enable(tp, true);
3628 static void rtl_hw_start_8125a_2(struct rtl8169_private *tp)
3630 static const struct ephy_info e_info_8125a_2[] = {
3631 { 0x04, 0xffff, 0xd000 },
3632 { 0x0a, 0xffff, 0x8653 },
3633 { 0x23, 0xffff, 0xab66 },
3634 { 0x20, 0xffff, 0x9455 },
3635 { 0x21, 0xffff, 0x99ff },
3636 { 0x29, 0xffff, 0xfe04 },
3638 { 0x44, 0xffff, 0xd000 },
3639 { 0x4a, 0xffff, 0x8653 },
3640 { 0x63, 0xffff, 0xab66 },
3641 { 0x60, 0xffff, 0x9455 },
3642 { 0x61, 0xffff, 0x99ff },
3643 { 0x69, 0xffff, 0xfe04 },
3646 rtl_set_def_aspm_entry_latency(tp);
3648 /* disable aspm and clock request before access ephy */
3649 rtl_hw_aspm_clkreq_enable(tp, false);
3650 rtl_ephy_init(tp, e_info_8125a_2);
3652 rtl_hw_start_8125_common(tp);
3653 rtl_hw_aspm_clkreq_enable(tp, true);
3656 static void rtl_hw_start_8125b(struct rtl8169_private *tp)
3658 static const struct ephy_info e_info_8125b[] = {
3659 { 0x0b, 0xffff, 0xa908 },
3660 { 0x1e, 0xffff, 0x20eb },
3661 { 0x4b, 0xffff, 0xa908 },
3662 { 0x5e, 0xffff, 0x20eb },
3663 { 0x22, 0x0030, 0x0020 },
3664 { 0x62, 0x0030, 0x0020 },
3667 rtl_set_def_aspm_entry_latency(tp);
3668 rtl_hw_aspm_clkreq_enable(tp, false);
3670 rtl_ephy_init(tp, e_info_8125b);
3671 rtl_hw_start_8125_common(tp);
3673 rtl_hw_aspm_clkreq_enable(tp, true);
3676 static void rtl_hw_config(struct rtl8169_private *tp)
3678 static const rtl_generic_fct hw_configs[] = {
3679 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1,
3680 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3,
3681 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2,
3682 [RTL_GIGA_MAC_VER_10] = NULL,
3683 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168b,
3684 [RTL_GIGA_MAC_VER_12] = rtl_hw_start_8168b,
3685 [RTL_GIGA_MAC_VER_13] = NULL,
3686 [RTL_GIGA_MAC_VER_14] = rtl_hw_start_8401,
3687 [RTL_GIGA_MAC_VER_16] = NULL,
3688 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b,
3689 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1,
3690 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1,
3691 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2,
3692 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_2,
3693 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4,
3694 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2,
3695 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3,
3696 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d,
3697 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d,
3698 [RTL_GIGA_MAC_VER_27] = rtl_hw_start_8168d,
3699 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4,
3700 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1,
3701 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2,
3702 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168d,
3703 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1,
3704 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1,
3705 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2,
3706 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1,
3707 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1,
3708 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402,
3709 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411,
3710 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106,
3711 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1,
3712 [RTL_GIGA_MAC_VER_41] = rtl_hw_start_8168g_1,
3713 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2,
3714 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2,
3715 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2,
3716 [RTL_GIGA_MAC_VER_45] = rtl_hw_start_8168h_1,
3717 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1,
3718 [RTL_GIGA_MAC_VER_47] = rtl_hw_start_8168h_1,
3719 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1,
3720 [RTL_GIGA_MAC_VER_49] = rtl_hw_start_8168ep_1,
3721 [RTL_GIGA_MAC_VER_50] = rtl_hw_start_8168ep_2,
3722 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3,
3723 [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117,
3724 [RTL_GIGA_MAC_VER_53] = rtl_hw_start_8117,
3725 [RTL_GIGA_MAC_VER_60] = rtl_hw_start_8125a_1,
3726 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2,
3727 [RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b,
3730 if (hw_configs[tp->mac_version])
3731 hw_configs[tp->mac_version](tp);
3734 static void rtl_hw_start_8125(struct rtl8169_private *tp)
3738 /* disable interrupt coalescing */
3739 for (i = 0xa00; i < 0xb00; i += 4)
3745 static void rtl_hw_start_8168(struct rtl8169_private *tp)
3747 if (rtl_is_8168evl_up(tp))
3748 RTL_W8(tp, MaxTxPacketSize, EarlySize);
3750 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
3754 /* disable interrupt coalescing */
3755 RTL_W16(tp, IntrMitigate, 0x0000);
3758 static void rtl_hw_start_8169(struct rtl8169_private *tp)
3760 RTL_W8(tp, EarlyTxThres, NoEarlyTx);
3762 tp->cp_cmd |= PCIMulRW;
3764 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3765 tp->mac_version == RTL_GIGA_MAC_VER_03)
3766 tp->cp_cmd |= EnAnaPLL;
3768 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
3770 rtl8169_set_magic_reg(tp);
3772 /* disable interrupt coalescing */
3773 RTL_W16(tp, IntrMitigate, 0x0000);
3776 static void rtl_hw_start(struct rtl8169_private *tp)
3778 rtl_unlock_config_regs(tp);
3780 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
3782 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3783 rtl_hw_start_8169(tp);
3784 else if (rtl_is_8125(tp))
3785 rtl_hw_start_8125(tp);
3787 rtl_hw_start_8168(tp);
3789 rtl_set_rx_max_size(tp);
3790 rtl_set_rx_tx_desc_registers(tp);
3791 rtl_lock_config_regs(tp);
3793 rtl_jumbo_config(tp);
3795 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3798 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
3800 rtl_set_tx_config_registers(tp);
3801 rtl_set_rx_config_features(tp, tp->dev->features);
3802 rtl_set_rx_mode(tp->dev);
3806 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
3808 struct rtl8169_private *tp = netdev_priv(dev);
3811 netdev_update_features(dev);
3812 rtl_jumbo_config(tp);
3814 switch (tp->mac_version) {
3815 case RTL_GIGA_MAC_VER_61:
3816 case RTL_GIGA_MAC_VER_63:
3817 rtl8125_set_eee_txidle_timer(tp);
3826 static void rtl8169_mark_to_asic(struct RxDesc *desc)
3828 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
3831 /* Force memory writes to complete before releasing descriptor */
3833 WRITE_ONCE(desc->opts1, cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE));
3836 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
3837 struct RxDesc *desc)
3839 struct device *d = tp_to_dev(tp);
3840 int node = dev_to_node(d);
3844 data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE));
3848 mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
3849 if (unlikely(dma_mapping_error(d, mapping))) {
3850 netdev_err(tp->dev, "Failed to map RX DMA!\n");
3851 __free_pages(data, get_order(R8169_RX_BUF_SIZE));
3855 desc->addr = cpu_to_le64(mapping);
3856 rtl8169_mark_to_asic(desc);
3861 static void rtl8169_rx_clear(struct rtl8169_private *tp)
3865 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) {
3866 dma_unmap_page(tp_to_dev(tp),
3867 le64_to_cpu(tp->RxDescArray[i].addr),
3868 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
3869 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE));
3870 tp->Rx_databuff[i] = NULL;
3871 tp->RxDescArray[i].addr = 0;
3872 tp->RxDescArray[i].opts1 = 0;
3876 static int rtl8169_rx_fill(struct rtl8169_private *tp)
3880 for (i = 0; i < NUM_RX_DESC; i++) {
3883 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
3885 rtl8169_rx_clear(tp);
3888 tp->Rx_databuff[i] = data;
3891 /* mark as last descriptor in the ring */
3892 tp->RxDescArray[NUM_RX_DESC - 1].opts1 |= cpu_to_le32(RingEnd);
3897 static int rtl8169_init_ring(struct rtl8169_private *tp)
3899 rtl8169_init_ring_indexes(tp);
3901 memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
3902 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
3904 return rtl8169_rx_fill(tp);
3907 static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int entry)
3909 struct ring_info *tx_skb = tp->tx_skb + entry;
3910 struct TxDesc *desc = tp->TxDescArray + entry;
3912 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), tx_skb->len,
3914 memset(desc, 0, sizeof(*desc));
3915 memset(tx_skb, 0, sizeof(*tx_skb));
3918 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
3923 for (i = 0; i < n; i++) {
3924 unsigned int entry = (start + i) % NUM_TX_DESC;
3925 struct ring_info *tx_skb = tp->tx_skb + entry;
3926 unsigned int len = tx_skb->len;
3929 struct sk_buff *skb = tx_skb->skb;
3931 rtl8169_unmap_tx_skb(tp, entry);
3933 dev_consume_skb_any(skb);
3938 static void rtl8169_tx_clear(struct rtl8169_private *tp)
3940 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
3941 netdev_reset_queue(tp->dev);
3944 static void rtl8169_cleanup(struct rtl8169_private *tp, bool going_down)
3946 napi_disable(&tp->napi);
3948 /* Give a racing hard_start_xmit a few cycles to complete. */
3951 /* Disable interrupts */
3952 rtl8169_irq_mask_and_ack(tp);
3956 if (going_down && tp->dev->wol_enabled)
3959 switch (tp->mac_version) {
3960 case RTL_GIGA_MAC_VER_27:
3961 case RTL_GIGA_MAC_VER_28:
3962 case RTL_GIGA_MAC_VER_31:
3963 rtl_loop_wait_low(tp, &rtl_npq_cond, 20, 2000);
3965 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
3966 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
3967 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
3969 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
3970 rtl_enable_rxdvgate(tp);
3974 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
3981 rtl8169_tx_clear(tp);
3982 rtl8169_init_ring_indexes(tp);
3985 static void rtl_reset_work(struct rtl8169_private *tp)
3989 netif_stop_queue(tp->dev);
3991 rtl8169_cleanup(tp, false);
3993 for (i = 0; i < NUM_RX_DESC; i++)
3994 rtl8169_mark_to_asic(tp->RxDescArray + i);
3996 napi_enable(&tp->napi);
4000 static void rtl8169_tx_timeout(struct net_device *dev, unsigned int txqueue)
4002 struct rtl8169_private *tp = netdev_priv(dev);
4004 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
4007 static int rtl8169_tx_map(struct rtl8169_private *tp, const u32 *opts, u32 len,
4008 void *addr, unsigned int entry, bool desc_own)
4010 struct TxDesc *txd = tp->TxDescArray + entry;
4011 struct device *d = tp_to_dev(tp);
4016 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
4017 ret = dma_mapping_error(d, mapping);
4018 if (unlikely(ret)) {
4019 if (net_ratelimit())
4020 netdev_err(tp->dev, "Failed to map TX data!\n");
4024 txd->addr = cpu_to_le64(mapping);
4025 txd->opts2 = cpu_to_le32(opts[1]);
4027 opts1 = opts[0] | len;
4028 if (entry == NUM_TX_DESC - 1)
4032 txd->opts1 = cpu_to_le32(opts1);
4034 tp->tx_skb[entry].len = len;
4039 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4040 const u32 *opts, unsigned int entry)
4042 struct skb_shared_info *info = skb_shinfo(skb);
4043 unsigned int cur_frag;
4045 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4046 const skb_frag_t *frag = info->frags + cur_frag;
4047 void *addr = skb_frag_address(frag);
4048 u32 len = skb_frag_size(frag);
4050 entry = (entry + 1) % NUM_TX_DESC;
4052 if (unlikely(rtl8169_tx_map(tp, opts, len, addr, entry, true)))
4059 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
4063 static bool rtl_skb_is_udp(struct sk_buff *skb)
4065 int no = skb_network_offset(skb);
4066 struct ipv6hdr *i6h, _i6h;
4067 struct iphdr *ih, _ih;
4069 switch (vlan_get_protocol(skb)) {
4070 case htons(ETH_P_IP):
4071 ih = skb_header_pointer(skb, no, sizeof(_ih), &_ih);
4072 return ih && ih->protocol == IPPROTO_UDP;
4073 case htons(ETH_P_IPV6):
4074 i6h = skb_header_pointer(skb, no, sizeof(_i6h), &_i6h);
4075 return i6h && i6h->nexthdr == IPPROTO_UDP;
4081 #define RTL_MIN_PATCH_LEN 47
4083 /* see rtl8125_get_patch_pad_len() in r8125 vendor driver */
4084 static unsigned int rtl8125_quirk_udp_padto(struct rtl8169_private *tp,
4085 struct sk_buff *skb)
4087 unsigned int padto = 0, len = skb->len;
4089 if (rtl_is_8125(tp) && len < 128 + RTL_MIN_PATCH_LEN &&
4090 rtl_skb_is_udp(skb) && skb_transport_header_was_set(skb)) {
4091 unsigned int trans_data_len = skb_tail_pointer(skb) -
4092 skb_transport_header(skb);
4094 if (trans_data_len >= offsetof(struct udphdr, len) &&
4095 trans_data_len < RTL_MIN_PATCH_LEN) {
4096 u16 dest = ntohs(udp_hdr(skb)->dest);
4098 /* dest is a standard PTP port */
4099 if (dest == 319 || dest == 320)
4100 padto = len + RTL_MIN_PATCH_LEN - trans_data_len;
4103 if (trans_data_len < sizeof(struct udphdr))
4104 padto = max_t(unsigned int, padto,
4105 len + sizeof(struct udphdr) - trans_data_len);
4111 static unsigned int rtl_quirk_packet_padto(struct rtl8169_private *tp,
4112 struct sk_buff *skb)
4116 padto = rtl8125_quirk_udp_padto(tp, skb);
4118 switch (tp->mac_version) {
4119 case RTL_GIGA_MAC_VER_34:
4120 case RTL_GIGA_MAC_VER_60:
4121 case RTL_GIGA_MAC_VER_61:
4122 case RTL_GIGA_MAC_VER_63:
4123 padto = max_t(unsigned int, padto, ETH_ZLEN);
4132 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts)
4134 u32 mss = skb_shinfo(skb)->gso_size;
4138 opts[0] |= mss << TD0_MSS_SHIFT;
4139 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4140 const struct iphdr *ip = ip_hdr(skb);
4142 if (ip->protocol == IPPROTO_TCP)
4143 opts[0] |= TD0_IP_CS | TD0_TCP_CS;
4144 else if (ip->protocol == IPPROTO_UDP)
4145 opts[0] |= TD0_IP_CS | TD0_UDP_CS;
4151 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
4152 struct sk_buff *skb, u32 *opts)
4154 u32 transport_offset = (u32)skb_transport_offset(skb);
4155 struct skb_shared_info *shinfo = skb_shinfo(skb);
4156 u32 mss = shinfo->gso_size;
4159 if (shinfo->gso_type & SKB_GSO_TCPV4) {
4160 opts[0] |= TD1_GTSENV4;
4161 } else if (shinfo->gso_type & SKB_GSO_TCPV6) {
4162 if (skb_cow_head(skb, 0))
4165 tcp_v6_gso_csum_prep(skb);
4166 opts[0] |= TD1_GTSENV6;
4171 opts[0] |= transport_offset << GTTCPHO_SHIFT;
4172 opts[1] |= mss << TD1_MSS_SHIFT;
4173 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4176 switch (vlan_get_protocol(skb)) {
4177 case htons(ETH_P_IP):
4178 opts[1] |= TD1_IPv4_CS;
4179 ip_protocol = ip_hdr(skb)->protocol;
4182 case htons(ETH_P_IPV6):
4183 opts[1] |= TD1_IPv6_CS;
4184 ip_protocol = ipv6_hdr(skb)->nexthdr;
4188 ip_protocol = IPPROTO_RAW;
4192 if (ip_protocol == IPPROTO_TCP)
4193 opts[1] |= TD1_TCP_CS;
4194 else if (ip_protocol == IPPROTO_UDP)
4195 opts[1] |= TD1_UDP_CS;
4199 opts[1] |= transport_offset << TCPHO_SHIFT;
4201 unsigned int padto = rtl_quirk_packet_padto(tp, skb);
4203 /* skb_padto would free the skb on error */
4204 return !__skb_put_padto(skb, padto, false);
4210 static bool rtl_tx_slots_avail(struct rtl8169_private *tp)
4212 unsigned int slots_avail = READ_ONCE(tp->dirty_tx) + NUM_TX_DESC
4213 - READ_ONCE(tp->cur_tx);
4215 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
4216 return slots_avail > MAX_SKB_FRAGS;
4219 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */
4220 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
4222 switch (tp->mac_version) {
4223 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
4224 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
4231 static void rtl8169_doorbell(struct rtl8169_private *tp)
4233 if (rtl_is_8125(tp))
4234 RTL_W16(tp, TxPoll_8125, BIT(0));
4236 RTL_W8(tp, TxPoll, NPQ);
4239 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4240 struct net_device *dev)
4242 unsigned int frags = skb_shinfo(skb)->nr_frags;
4243 struct rtl8169_private *tp = netdev_priv(dev);
4244 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
4245 struct TxDesc *txd_first, *txd_last;
4246 bool stop_queue, door_bell;
4249 if (unlikely(!rtl_tx_slots_avail(tp))) {
4250 if (net_ratelimit())
4251 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
4255 opts[1] = rtl8169_tx_vlan_tag(skb);
4258 if (!rtl_chip_supports_csum_v2(tp))
4259 rtl8169_tso_csum_v1(skb, opts);
4260 else if (!rtl8169_tso_csum_v2(tp, skb, opts))
4263 if (unlikely(rtl8169_tx_map(tp, opts, skb_headlen(skb), skb->data,
4267 txd_first = tp->TxDescArray + entry;
4270 if (rtl8169_xmit_frags(tp, skb, opts, entry))
4272 entry = (entry + frags) % NUM_TX_DESC;
4275 txd_last = tp->TxDescArray + entry;
4276 txd_last->opts1 |= cpu_to_le32(LastFrag);
4277 tp->tx_skb[entry].skb = skb;
4279 skb_tx_timestamp(skb);
4281 /* Force memory writes to complete before releasing descriptor */
4284 door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more());
4286 txd_first->opts1 |= cpu_to_le32(DescOwn | FirstFrag);
4288 /* rtl_tx needs to see descriptor changes before updated tp->cur_tx */
4291 WRITE_ONCE(tp->cur_tx, tp->cur_tx + frags + 1);
4293 stop_queue = !rtl_tx_slots_avail(tp);
4294 if (unlikely(stop_queue)) {
4295 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
4296 * not miss a ring update when it notices a stopped queue.
4299 netif_stop_queue(dev);
4300 /* Sync with rtl_tx:
4301 * - publish queue status and cur_tx ring index (write barrier)
4302 * - refresh dirty_tx ring index (read barrier).
4303 * May the current thread have a pessimistic view of the ring
4304 * status and forget to wake up queue, a racing rtl_tx thread
4307 smp_mb__after_atomic();
4308 if (rtl_tx_slots_avail(tp))
4309 netif_start_queue(dev);
4314 rtl8169_doorbell(tp);
4316 return NETDEV_TX_OK;
4319 rtl8169_unmap_tx_skb(tp, entry);
4321 dev_kfree_skb_any(skb);
4322 dev->stats.tx_dropped++;
4323 return NETDEV_TX_OK;
4326 netif_stop_queue(dev);
4327 dev->stats.tx_dropped++;
4328 return NETDEV_TX_BUSY;
4331 static unsigned int rtl_last_frag_len(struct sk_buff *skb)
4333 struct skb_shared_info *info = skb_shinfo(skb);
4334 unsigned int nr_frags = info->nr_frags;
4339 return skb_frag_size(info->frags + nr_frags - 1);
4342 /* Workaround for hw issues with TSO on RTL8168evl */
4343 static netdev_features_t rtl8168evl_fix_tso(struct sk_buff *skb,
4344 netdev_features_t features)
4346 /* IPv4 header has options field */
4347 if (vlan_get_protocol(skb) == htons(ETH_P_IP) &&
4348 ip_hdrlen(skb) > sizeof(struct iphdr))
4349 features &= ~NETIF_F_ALL_TSO;
4351 /* IPv4 TCP header has options field */
4352 else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4 &&
4353 tcp_hdrlen(skb) > sizeof(struct tcphdr))
4354 features &= ~NETIF_F_ALL_TSO;
4356 else if (rtl_last_frag_len(skb) <= 6)
4357 features &= ~NETIF_F_ALL_TSO;
4362 static netdev_features_t rtl8169_features_check(struct sk_buff *skb,
4363 struct net_device *dev,
4364 netdev_features_t features)
4366 int transport_offset = skb_transport_offset(skb);
4367 struct rtl8169_private *tp = netdev_priv(dev);
4369 if (skb_is_gso(skb)) {
4370 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4371 features = rtl8168evl_fix_tso(skb, features);
4373 if (transport_offset > GTTCPHO_MAX &&
4374 rtl_chip_supports_csum_v2(tp))
4375 features &= ~NETIF_F_ALL_TSO;
4376 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4377 /* work around hw bug on some chip versions */
4378 if (skb->len < ETH_ZLEN)
4379 features &= ~NETIF_F_CSUM_MASK;
4381 if (rtl_quirk_packet_padto(tp, skb))
4382 features &= ~NETIF_F_CSUM_MASK;
4384 if (transport_offset > TCPHO_MAX &&
4385 rtl_chip_supports_csum_v2(tp))
4386 features &= ~NETIF_F_CSUM_MASK;
4389 return vlan_features_check(skb, features);
4392 static void rtl8169_pcierr_interrupt(struct net_device *dev)
4394 struct rtl8169_private *tp = netdev_priv(dev);
4395 struct pci_dev *pdev = tp->pci_dev;
4396 int pci_status_errs;
4399 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4401 pci_status_errs = pci_status_get_and_clear_errors(pdev);
4403 if (net_ratelimit())
4404 netdev_err(dev, "PCI error (cmd = 0x%04x, status_errs = 0x%04x)\n",
4405 pci_cmd, pci_status_errs);
4407 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
4410 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp,
4413 unsigned int dirty_tx, bytes_compl = 0, pkts_compl = 0;
4414 struct sk_buff *skb;
4416 dirty_tx = tp->dirty_tx;
4418 while (READ_ONCE(tp->cur_tx) != dirty_tx) {
4419 unsigned int entry = dirty_tx % NUM_TX_DESC;
4422 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
4423 if (status & DescOwn)
4426 skb = tp->tx_skb[entry].skb;
4427 rtl8169_unmap_tx_skb(tp, entry);
4431 bytes_compl += skb->len;
4432 napi_consume_skb(skb, budget);
4437 if (tp->dirty_tx != dirty_tx) {
4438 netdev_completed_queue(dev, pkts_compl, bytes_compl);
4439 dev_sw_netstats_tx_add(dev, pkts_compl, bytes_compl);
4441 /* Sync with rtl8169_start_xmit:
4442 * - publish dirty_tx ring index (write barrier)
4443 * - refresh cur_tx ring index and queue status (read barrier)
4444 * May the current thread miss the stopped queue condition,
4445 * a racing xmit thread can only have a right view of the
4448 smp_store_mb(tp->dirty_tx, dirty_tx);
4449 if (netif_queue_stopped(dev) && rtl_tx_slots_avail(tp))
4450 netif_wake_queue(dev);
4452 * 8168 hack: TxPoll requests are lost when the Tx packets are
4453 * too close. Let's kick an extra TxPoll request when a burst
4454 * of start_xmit activity is detected (if it is not detected,
4455 * it is slow enough). -- FR
4456 * If skb is NULL then we come here again once a tx irq is
4457 * triggered after the last fragment is marked transmitted.
4459 if (tp->cur_tx != dirty_tx && skb)
4460 rtl8169_doorbell(tp);
4464 static inline int rtl8169_fragmented_frame(u32 status)
4466 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4469 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
4471 u32 status = opts1 & (RxProtoMask | RxCSFailMask);
4473 if (status == RxProtoTCP || status == RxProtoUDP)
4474 skb->ip_summed = CHECKSUM_UNNECESSARY;
4476 skb_checksum_none_assert(skb);
4479 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, int budget)
4481 struct device *d = tp_to_dev(tp);
4484 for (count = 0; count < budget; count++, tp->cur_rx++) {
4485 unsigned int pkt_size, entry = tp->cur_rx % NUM_RX_DESC;
4486 struct RxDesc *desc = tp->RxDescArray + entry;
4487 struct sk_buff *skb;
4492 status = le32_to_cpu(desc->opts1);
4493 if (status & DescOwn)
4496 /* This barrier is needed to keep us from reading
4497 * any other fields out of the Rx descriptor until
4498 * we know the status of DescOwn
4502 if (unlikely(status & RxRES)) {
4503 if (net_ratelimit())
4504 netdev_warn(dev, "Rx ERROR. status = %08x\n",
4506 dev->stats.rx_errors++;
4507 if (status & (RxRWT | RxRUNT))
4508 dev->stats.rx_length_errors++;
4510 dev->stats.rx_crc_errors++;
4512 if (!(dev->features & NETIF_F_RXALL))
4513 goto release_descriptor;
4514 else if (status & RxRWT || !(status & (RxRUNT | RxCRC)))
4515 goto release_descriptor;
4518 pkt_size = status & GENMASK(13, 0);
4519 if (likely(!(dev->features & NETIF_F_RXFCS)))
4520 pkt_size -= ETH_FCS_LEN;
4522 /* The driver does not support incoming fragmented frames.
4523 * They are seen as a symptom of over-mtu sized frames.
4525 if (unlikely(rtl8169_fragmented_frame(status))) {
4526 dev->stats.rx_dropped++;
4527 dev->stats.rx_length_errors++;
4528 goto release_descriptor;
4531 skb = napi_alloc_skb(&tp->napi, pkt_size);
4532 if (unlikely(!skb)) {
4533 dev->stats.rx_dropped++;
4534 goto release_descriptor;
4537 addr = le64_to_cpu(desc->addr);
4538 rx_buf = page_address(tp->Rx_databuff[entry]);
4540 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
4542 skb_copy_to_linear_data(skb, rx_buf, pkt_size);
4543 skb->tail += pkt_size;
4544 skb->len = pkt_size;
4545 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
4547 rtl8169_rx_csum(skb, status);
4548 skb->protocol = eth_type_trans(skb, dev);
4550 rtl8169_rx_vlan_tag(desc, skb);
4552 if (skb->pkt_type == PACKET_MULTICAST)
4553 dev->stats.multicast++;
4555 napi_gro_receive(&tp->napi, skb);
4557 dev_sw_netstats_rx_add(dev, pkt_size);
4559 rtl8169_mark_to_asic(desc);
4565 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
4567 struct rtl8169_private *tp = dev_instance;
4568 u32 status = rtl_get_events(tp);
4570 if ((status & 0xffff) == 0xffff || !(status & tp->irq_mask))
4573 if (unlikely(status & SYSErr)) {
4574 rtl8169_pcierr_interrupt(tp->dev);
4578 if (status & LinkChg)
4579 phy_mac_interrupt(tp->phydev);
4581 if (unlikely(status & RxFIFOOver &&
4582 tp->mac_version == RTL_GIGA_MAC_VER_11)) {
4583 netif_stop_queue(tp->dev);
4584 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
4587 if (napi_schedule_prep(&tp->napi)) {
4588 rtl_irq_disable(tp);
4589 __napi_schedule(&tp->napi);
4592 rtl_ack_events(tp, status);
4597 static void rtl_task(struct work_struct *work)
4599 struct rtl8169_private *tp =
4600 container_of(work, struct rtl8169_private, wk.work);
4604 if (!netif_running(tp->dev) ||
4605 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
4608 if (test_and_clear_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags)) {
4610 netif_wake_queue(tp->dev);
4616 static int rtl8169_poll(struct napi_struct *napi, int budget)
4618 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
4619 struct net_device *dev = tp->dev;
4622 rtl_tx(dev, tp, budget);
4624 work_done = rtl_rx(dev, tp, budget);
4626 if (work_done < budget && napi_complete_done(napi, work_done))
4632 static void r8169_phylink_handler(struct net_device *ndev)
4634 struct rtl8169_private *tp = netdev_priv(ndev);
4636 if (netif_carrier_ok(ndev)) {
4637 rtl_link_chg_patch(tp);
4638 pm_request_resume(&tp->pci_dev->dev);
4640 pm_runtime_idle(&tp->pci_dev->dev);
4643 if (net_ratelimit())
4644 phy_print_status(tp->phydev);
4647 static int r8169_phy_connect(struct rtl8169_private *tp)
4649 struct phy_device *phydev = tp->phydev;
4650 phy_interface_t phy_mode;
4653 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
4654 PHY_INTERFACE_MODE_MII;
4656 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
4661 if (!tp->supports_gmii)
4662 phy_set_max_speed(phydev, SPEED_100);
4664 phy_attached_info(phydev);
4669 static void rtl8169_down(struct rtl8169_private *tp)
4671 /* Clear all task flags */
4672 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
4674 phy_stop(tp->phydev);
4676 rtl8169_update_counters(tp);
4678 pci_clear_master(tp->pci_dev);
4681 rtl8169_cleanup(tp, true);
4683 rtl_prepare_power_down(tp);
4686 static void rtl8169_up(struct rtl8169_private *tp)
4688 pci_set_master(tp->pci_dev);
4689 phy_init_hw(tp->phydev);
4690 phy_resume(tp->phydev);
4691 rtl8169_init_phy(tp);
4692 napi_enable(&tp->napi);
4693 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
4696 phy_start(tp->phydev);
4699 static int rtl8169_close(struct net_device *dev)
4701 struct rtl8169_private *tp = netdev_priv(dev);
4702 struct pci_dev *pdev = tp->pci_dev;
4704 pm_runtime_get_sync(&pdev->dev);
4706 netif_stop_queue(dev);
4708 rtl8169_rx_clear(tp);
4710 cancel_work_sync(&tp->wk.work);
4712 free_irq(pci_irq_vector(pdev, 0), tp);
4714 phy_disconnect(tp->phydev);
4716 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4718 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4720 tp->TxDescArray = NULL;
4721 tp->RxDescArray = NULL;
4723 pm_runtime_put_sync(&pdev->dev);
4728 #ifdef CONFIG_NET_POLL_CONTROLLER
4729 static void rtl8169_netpoll(struct net_device *dev)
4731 struct rtl8169_private *tp = netdev_priv(dev);
4733 rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp);
4737 static int rtl_open(struct net_device *dev)
4739 struct rtl8169_private *tp = netdev_priv(dev);
4740 struct pci_dev *pdev = tp->pci_dev;
4741 unsigned long irqflags;
4742 int retval = -ENOMEM;
4744 pm_runtime_get_sync(&pdev->dev);
4747 * Rx and Tx descriptors needs 256 bytes alignment.
4748 * dma_alloc_coherent provides more.
4750 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
4751 &tp->TxPhyAddr, GFP_KERNEL);
4752 if (!tp->TxDescArray)
4755 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
4756 &tp->RxPhyAddr, GFP_KERNEL);
4757 if (!tp->RxDescArray)
4760 retval = rtl8169_init_ring(tp);
4764 rtl_request_firmware(tp);
4766 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_NO_THREAD : IRQF_SHARED;
4767 retval = request_irq(pci_irq_vector(pdev, 0), rtl8169_interrupt,
4768 irqflags, dev->name, tp);
4770 goto err_release_fw_2;
4772 retval = r8169_phy_connect(tp);
4777 rtl8169_init_counter_offsets(tp);
4778 netif_start_queue(dev);
4780 pm_runtime_put_sync(&pdev->dev);
4785 free_irq(pci_irq_vector(pdev, 0), tp);
4787 rtl_release_firmware(tp);
4788 rtl8169_rx_clear(tp);
4790 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4792 tp->RxDescArray = NULL;
4794 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4796 tp->TxDescArray = NULL;
4801 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
4803 struct rtl8169_private *tp = netdev_priv(dev);
4804 struct pci_dev *pdev = tp->pci_dev;
4805 struct rtl8169_counters *counters = tp->counters;
4807 pm_runtime_get_noresume(&pdev->dev);
4809 netdev_stats_to_stats64(stats, &dev->stats);
4810 dev_fetch_sw_netstats(stats, dev->tstats);
4813 * Fetch additional counter values missing in stats collected by driver
4814 * from tally counters.
4816 if (pm_runtime_active(&pdev->dev))
4817 rtl8169_update_counters(tp);
4820 * Subtract values fetched during initalization.
4821 * See rtl8169_init_counter_offsets for a description why we do that.
4823 stats->tx_errors = le64_to_cpu(counters->tx_errors) -
4824 le64_to_cpu(tp->tc_offset.tx_errors);
4825 stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
4826 le32_to_cpu(tp->tc_offset.tx_multi_collision);
4827 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
4828 le16_to_cpu(tp->tc_offset.tx_aborted);
4829 stats->rx_missed_errors = le16_to_cpu(counters->rx_missed) -
4830 le16_to_cpu(tp->tc_offset.rx_missed);
4832 pm_runtime_put_noidle(&pdev->dev);
4835 static void rtl8169_net_suspend(struct rtl8169_private *tp)
4837 netif_device_detach(tp->dev);
4839 if (netif_running(tp->dev))
4845 static int rtl8169_runtime_resume(struct device *dev)
4847 struct rtl8169_private *tp = dev_get_drvdata(dev);
4849 rtl_rar_set(tp, tp->dev->dev_addr);
4850 __rtl8169_set_wol(tp, tp->saved_wolopts);
4852 if (tp->TxDescArray)
4855 netif_device_attach(tp->dev);
4860 static int __maybe_unused rtl8169_suspend(struct device *device)
4862 struct rtl8169_private *tp = dev_get_drvdata(device);
4865 rtl8169_net_suspend(tp);
4866 if (!device_may_wakeup(tp_to_dev(tp)))
4867 clk_disable_unprepare(tp->clk);
4873 static int __maybe_unused rtl8169_resume(struct device *device)
4875 struct rtl8169_private *tp = dev_get_drvdata(device);
4877 if (!device_may_wakeup(tp_to_dev(tp)))
4878 clk_prepare_enable(tp->clk);
4880 /* Reportedly at least Asus X453MA truncates packets otherwise */
4881 if (tp->mac_version == RTL_GIGA_MAC_VER_37)
4884 return rtl8169_runtime_resume(device);
4887 static int rtl8169_runtime_suspend(struct device *device)
4889 struct rtl8169_private *tp = dev_get_drvdata(device);
4891 if (!tp->TxDescArray) {
4892 netif_device_detach(tp->dev);
4897 __rtl8169_set_wol(tp, WAKE_PHY);
4898 rtl8169_net_suspend(tp);
4904 static int rtl8169_runtime_idle(struct device *device)
4906 struct rtl8169_private *tp = dev_get_drvdata(device);
4908 if (!netif_running(tp->dev) || !netif_carrier_ok(tp->dev))
4909 pm_schedule_suspend(device, 10000);
4914 static const struct dev_pm_ops rtl8169_pm_ops = {
4915 SET_SYSTEM_SLEEP_PM_OPS(rtl8169_suspend, rtl8169_resume)
4916 SET_RUNTIME_PM_OPS(rtl8169_runtime_suspend, rtl8169_runtime_resume,
4917 rtl8169_runtime_idle)
4920 #endif /* CONFIG_PM */
4922 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
4924 /* WoL fails with 8168b when the receiver is disabled. */
4925 switch (tp->mac_version) {
4926 case RTL_GIGA_MAC_VER_11:
4927 case RTL_GIGA_MAC_VER_12:
4928 case RTL_GIGA_MAC_VER_17:
4929 pci_clear_master(tp->pci_dev);
4931 RTL_W8(tp, ChipCmd, CmdRxEnb);
4939 static void rtl_shutdown(struct pci_dev *pdev)
4941 struct rtl8169_private *tp = pci_get_drvdata(pdev);
4944 rtl8169_net_suspend(tp);
4947 /* Restore original MAC address */
4948 rtl_rar_set(tp, tp->dev->perm_addr);
4950 if (system_state == SYSTEM_POWER_OFF) {
4951 if (tp->saved_wolopts)
4952 rtl_wol_shutdown_quirk(tp);
4954 pci_wake_from_d3(pdev, tp->saved_wolopts);
4955 pci_set_power_state(pdev, PCI_D3hot);
4959 static void rtl_remove_one(struct pci_dev *pdev)
4961 struct rtl8169_private *tp = pci_get_drvdata(pdev);
4963 if (pci_dev_run_wake(pdev))
4964 pm_runtime_get_noresume(&pdev->dev);
4966 unregister_netdev(tp->dev);
4968 if (tp->dash_type != RTL_DASH_NONE)
4969 rtl8168_driver_stop(tp);
4971 rtl_release_firmware(tp);
4973 /* restore original MAC address */
4974 rtl_rar_set(tp, tp->dev->perm_addr);
4977 static const struct net_device_ops rtl_netdev_ops = {
4978 .ndo_open = rtl_open,
4979 .ndo_stop = rtl8169_close,
4980 .ndo_get_stats64 = rtl8169_get_stats64,
4981 .ndo_start_xmit = rtl8169_start_xmit,
4982 .ndo_features_check = rtl8169_features_check,
4983 .ndo_tx_timeout = rtl8169_tx_timeout,
4984 .ndo_validate_addr = eth_validate_addr,
4985 .ndo_change_mtu = rtl8169_change_mtu,
4986 .ndo_fix_features = rtl8169_fix_features,
4987 .ndo_set_features = rtl8169_set_features,
4988 .ndo_set_mac_address = rtl_set_mac_address,
4989 .ndo_eth_ioctl = phy_do_ioctl_running,
4990 .ndo_set_rx_mode = rtl_set_rx_mode,
4991 #ifdef CONFIG_NET_POLL_CONTROLLER
4992 .ndo_poll_controller = rtl8169_netpoll,
4997 static void rtl_set_irq_mask(struct rtl8169_private *tp)
4999 tp->irq_mask = RxOK | RxErr | TxOK | TxErr | LinkChg;
5001 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
5002 tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver;
5003 else if (tp->mac_version == RTL_GIGA_MAC_VER_11)
5004 /* special workaround needed */
5005 tp->irq_mask |= RxFIFOOver;
5007 tp->irq_mask |= RxOverflow;
5010 static int rtl_alloc_irq(struct rtl8169_private *tp)
5014 switch (tp->mac_version) {
5015 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
5016 rtl_unlock_config_regs(tp);
5017 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
5018 rtl_lock_config_regs(tp);
5020 case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_17:
5021 flags = PCI_IRQ_LEGACY;
5024 flags = PCI_IRQ_ALL_TYPES;
5028 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
5031 static void rtl_read_mac_address(struct rtl8169_private *tp,
5032 u8 mac_addr[ETH_ALEN])
5034 /* Get MAC address */
5035 if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) {
5038 value = rtl_eri_read(tp, 0xe0);
5039 put_unaligned_le32(value, mac_addr);
5040 value = rtl_eri_read(tp, 0xe4);
5041 put_unaligned_le16(value, mac_addr + 4);
5042 } else if (rtl_is_8125(tp)) {
5043 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP);
5047 DECLARE_RTL_COND(rtl_link_list_ready_cond)
5049 return RTL_R8(tp, MCU) & LINK_LIST_RDY;
5052 static void r8168g_wait_ll_share_fifo_ready(struct rtl8169_private *tp)
5054 rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42);
5057 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
5059 struct rtl8169_private *tp = mii_bus->priv;
5064 return rtl_readphy(tp, phyreg);
5067 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
5068 int phyreg, u16 val)
5070 struct rtl8169_private *tp = mii_bus->priv;
5075 rtl_writephy(tp, phyreg, val);
5080 static int r8169_mdio_register(struct rtl8169_private *tp)
5082 struct pci_dev *pdev = tp->pci_dev;
5083 struct mii_bus *new_bus;
5086 new_bus = devm_mdiobus_alloc(&pdev->dev);
5090 new_bus->name = "r8169";
5092 new_bus->parent = &pdev->dev;
5093 new_bus->irq[0] = PHY_MAC_INTERRUPT;
5094 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x-%x",
5095 pci_domain_nr(pdev->bus), pci_dev_id(pdev));
5097 new_bus->read = r8169_mdio_read_reg;
5098 new_bus->write = r8169_mdio_write_reg;
5100 ret = devm_mdiobus_register(&pdev->dev, new_bus);
5104 tp->phydev = mdiobus_get_phy(new_bus, 0);
5107 } else if (!tp->phydev->drv) {
5108 /* Most chip versions fail with the genphy driver.
5109 * Therefore ensure that the dedicated PHY driver is loaded.
5111 dev_err(&pdev->dev, "no dedicated PHY driver found for PHY ID 0x%08x, maybe realtek.ko needs to be added to initramfs?\n",
5112 tp->phydev->phy_id);
5116 tp->phydev->mac_managed_pm = 1;
5118 phy_support_asym_pause(tp->phydev);
5120 /* PHY will be woken up in rtl_open() */
5121 phy_suspend(tp->phydev);
5126 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
5128 rtl_enable_rxdvgate(tp);
5130 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
5132 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5134 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
5135 r8168g_wait_ll_share_fifo_ready(tp);
5137 r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15));
5138 r8168g_wait_ll_share_fifo_ready(tp);
5141 static void rtl_hw_init_8125(struct rtl8169_private *tp)
5143 rtl_enable_rxdvgate(tp);
5145 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
5147 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5149 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
5150 r8168g_wait_ll_share_fifo_ready(tp);
5152 r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0);
5153 r8168_mac_ocp_write(tp, 0xc0a6, 0x0150);
5154 r8168_mac_ocp_write(tp, 0xc01e, 0x5555);
5155 r8168g_wait_ll_share_fifo_ready(tp);
5158 static void rtl_hw_initialize(struct rtl8169_private *tp)
5160 switch (tp->mac_version) {
5161 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_53:
5162 rtl8168ep_stop_cmac(tp);
5164 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
5165 rtl_hw_init_8168g(tp);
5167 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_63:
5168 rtl_hw_init_8125(tp);
5175 static int rtl_jumbo_max(struct rtl8169_private *tp)
5177 /* Non-GBit versions don't support jumbo frames */
5178 if (!tp->supports_gmii)
5181 switch (tp->mac_version) {
5183 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
5186 case RTL_GIGA_MAC_VER_11:
5187 case RTL_GIGA_MAC_VER_12:
5188 case RTL_GIGA_MAC_VER_17:
5191 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
5198 static void rtl_disable_clk(void *data)
5200 clk_disable_unprepare(data);
5203 static int rtl_get_ether_clk(struct rtl8169_private *tp)
5205 struct device *d = tp_to_dev(tp);
5209 clk = devm_clk_get(d, "ether_clk");
5213 /* clk-core allows NULL (for suspend / resume) */
5216 dev_err_probe(d, rc, "failed to get clk\n");
5219 rc = clk_prepare_enable(clk);
5221 dev_err(d, "failed to enable clk: %d\n", rc);
5223 rc = devm_add_action_or_reset(d, rtl_disable_clk, clk);
5229 static void rtl_init_mac_address(struct rtl8169_private *tp)
5231 struct net_device *dev = tp->dev;
5232 u8 *mac_addr = dev->dev_addr;
5235 rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr);
5239 rtl_read_mac_address(tp, mac_addr);
5240 if (is_valid_ether_addr(mac_addr))
5243 rtl_read_mac_from_reg(tp, mac_addr, MAC0);
5244 if (is_valid_ether_addr(mac_addr))
5247 eth_hw_addr_random(dev);
5248 dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n");
5250 rtl_rar_set(tp, mac_addr);
5253 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
5255 struct rtl8169_private *tp;
5256 int jumbo_max, region, rc;
5257 enum mac_version chipset;
5258 struct net_device *dev;
5261 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
5265 SET_NETDEV_DEV(dev, &pdev->dev);
5266 dev->netdev_ops = &rtl_netdev_ops;
5267 tp = netdev_priv(dev);
5270 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1;
5272 tp->ocp_base = OCP_STD_PHY_BASE;
5274 dev->tstats = devm_netdev_alloc_pcpu_stats(&pdev->dev,
5275 struct pcpu_sw_netstats);
5279 /* Get the *optional* external "ether_clk" used on some boards */
5280 rc = rtl_get_ether_clk(tp);
5284 /* Disable ASPM L1 as that cause random device stop working
5285 * problems as well as full system hangs for some PCIe devices users.
5287 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L1);
5288 tp->aspm_manageable = !rc;
5290 /* enable device (incl. PCI PM wakeup and hotplug setup) */
5291 rc = pcim_enable_device(pdev);
5293 dev_err(&pdev->dev, "enable failure\n");
5297 if (pcim_set_mwi(pdev) < 0)
5298 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
5300 /* use first MMIO region */
5301 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
5303 dev_err(&pdev->dev, "no MMIO resource found\n");
5307 /* check for weird/broken PCI region reporting */
5308 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
5309 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
5313 rc = pcim_iomap_regions(pdev, BIT(region), KBUILD_MODNAME);
5315 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
5319 tp->mmio_addr = pcim_iomap_table(pdev)[region];
5321 xid = (RTL_R32(tp, TxConfig) >> 20) & 0xfcf;
5323 /* Identify chip attached to board */
5324 chipset = rtl8169_get_mac_version(xid, tp->supports_gmii);
5325 if (chipset == RTL_GIGA_MAC_NONE) {
5326 dev_err(&pdev->dev, "unknown chip XID %03x, contact r8169 maintainers (see MAINTAINERS file)\n", xid);
5330 tp->mac_version = chipset;
5332 tp->dash_type = rtl_check_dash(tp);
5334 tp->cp_cmd = RTL_R16(tp, CPlusCmd) & CPCMD_MASK;
5336 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 &&
5337 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)))
5338 dev->features |= NETIF_F_HIGHDMA;
5342 rtl8169_irq_mask_and_ack(tp);
5344 rtl_hw_initialize(tp);
5348 rc = rtl_alloc_irq(tp);
5350 dev_err(&pdev->dev, "Can't allocate interrupt\n");
5354 INIT_WORK(&tp->wk.work, rtl_task);
5356 rtl_init_mac_address(tp);
5358 dev->ethtool_ops = &rtl8169_ethtool_ops;
5360 netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT);
5362 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
5363 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
5364 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO;
5365 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
5368 * Pretend we are using VLANs; This bypasses a nasty bug where
5369 * Interrupts stop flowing on high load on 8110SCd controllers.
5371 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
5372 /* Disallow toggling */
5373 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
5375 if (rtl_chip_supports_csum_v2(tp))
5376 dev->hw_features |= NETIF_F_IPV6_CSUM;
5378 dev->features |= dev->hw_features;
5380 /* There has been a number of reports that using SG/TSO results in
5381 * tx timeouts. However for a lot of people SG/TSO works fine.
5382 * Therefore disable both features by default, but allow users to
5383 * enable them. Use at own risk!
5385 if (rtl_chip_supports_csum_v2(tp)) {
5386 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6;
5387 dev->gso_max_size = RTL_GSO_MAX_SIZE_V2;
5388 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V2;
5390 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO;
5391 dev->gso_max_size = RTL_GSO_MAX_SIZE_V1;
5392 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V1;
5395 dev->hw_features |= NETIF_F_RXALL;
5396 dev->hw_features |= NETIF_F_RXFCS;
5398 /* configure chip for default features */
5399 rtl8169_set_features(dev, dev->features);
5401 rtl_set_d3_pll_down(tp, true);
5403 jumbo_max = rtl_jumbo_max(tp);
5405 dev->max_mtu = jumbo_max;
5407 rtl_set_irq_mask(tp);
5409 tp->fw_name = rtl_chip_infos[chipset].fw_name;
5411 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
5412 &tp->counters_phys_addr,
5417 pci_set_drvdata(pdev, tp);
5419 rc = r8169_mdio_register(tp);
5423 rc = register_netdev(dev);
5427 netdev_info(dev, "%s, %pM, XID %03x, IRQ %d\n",
5428 rtl_chip_infos[chipset].name, dev->dev_addr, xid,
5429 pci_irq_vector(pdev, 0));
5432 netdev_info(dev, "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
5433 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?
5436 if (tp->dash_type != RTL_DASH_NONE) {
5437 netdev_info(dev, "DASH enabled\n");
5438 rtl8168_driver_start(tp);
5441 if (pci_dev_run_wake(pdev))
5442 pm_runtime_put_sync(&pdev->dev);
5447 static struct pci_driver rtl8169_pci_driver = {
5448 .name = KBUILD_MODNAME,
5449 .id_table = rtl8169_pci_tbl,
5450 .probe = rtl_init_one,
5451 .remove = rtl_remove_one,
5452 .shutdown = rtl_shutdown,
5453 .driver.pm = pm_ptr(&rtl8169_pm_ops),
5456 module_pci_driver(rtl8169_pci_driver);