drivers/net/ethernet/realtek/r8169_main.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   4  *
   5  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   6  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   7  * Copyright (c) a lot of people too. Please respect their work.
   8  *
   9  * See MAINTAINERS file for support contact information.
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/clk.h>
  17 #include <linux/delay.h>
  18 #include <linux/ethtool.h>
  19 #include <linux/phy.h>
  20 #include <linux/if_vlan.h>
  21 #include <linux/in.h>
  22 #include <linux/io.h>
  23 #include <linux/ip.h>
  24 #include <linux/tcp.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/pm_runtime.h>
  28 #include <linux/bitfield.h>
  29 #include <linux/prefetch.h>
  30 #include <linux/ipv6.h>
  31 #include <asm/unaligned.h>
  32 #include <net/ip6_checksum.h>
  33
  34 #include "r8169.h"
  35 #include "r8169_firmware.h"
  36
  37 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  38 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  39 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  40 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  41 #define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
  42 #define FIRMWARE_8168F_1        "rtl_nic/rtl8168f-1.fw"
  43 #define FIRMWARE_8168F_2        "rtl_nic/rtl8168f-2.fw"
  44 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  45 #define FIRMWARE_8402_1         "rtl_nic/rtl8402-1.fw"
  46 #define FIRMWARE_8411_1         "rtl_nic/rtl8411-1.fw"
  47 #define FIRMWARE_8411_2         "rtl_nic/rtl8411-2.fw"
  48 #define FIRMWARE_8106E_1        "rtl_nic/rtl8106e-1.fw"
  49 #define FIRMWARE_8106E_2        "rtl_nic/rtl8106e-2.fw"
  50 #define FIRMWARE_8168G_2        "rtl_nic/rtl8168g-2.fw"
  51 #define FIRMWARE_8168G_3        "rtl_nic/rtl8168g-3.fw"
  52 #define FIRMWARE_8168H_2        "rtl_nic/rtl8168h-2.fw"
  53 #define FIRMWARE_8168FP_3       "rtl_nic/rtl8168fp-3.fw"
  54 #define FIRMWARE_8107E_2        "rtl_nic/rtl8107e-2.fw"
  55 #define FIRMWARE_8125A_3        "rtl_nic/rtl8125a-3.fw"
  56 #define FIRMWARE_8125B_2        "rtl_nic/rtl8125b-2.fw"
  57
  58 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  59    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  60 #define MC_FILTER_LIMIT 32
  61
  62 #define TX_DMA_BURST    7       /* Maximum PCI burst, '7' is unlimited */
  63 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  64
  65 #define R8169_REGS_SIZE         256
  66 #define R8169_RX_BUF_SIZE       (SZ_16K - 1)
  67 #define NUM_TX_DESC     256     /* Number of Tx descriptor registers */
  68 #define NUM_RX_DESC     256     /* Number of Rx descriptor registers */
  69 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  70 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  71
  72 #define OCP_STD_PHY_BASE        0xa400
  73
  74 #define RTL_CFG_NO_GBIT 1
  75
  76 /* write/read MMIO register */
  77 #define RTL_W8(tp, reg, val8)   writeb((val8), tp->mmio_addr + (reg))
  78 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
  79 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
  80 #define RTL_R8(tp, reg)         readb(tp->mmio_addr + (reg))
  81 #define RTL_R16(tp, reg)                readw(tp->mmio_addr + (reg))
  82 #define RTL_R32(tp, reg)                readl(tp->mmio_addr + (reg))
  83
  84 #define JUMBO_4K        (4 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
  85 #define JUMBO_6K        (6 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
  86 #define JUMBO_7K        (7 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
  87 #define JUMBO_9K        (9 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
  88
  89 static const struct {
  90         const char *name;
  91         const char *fw_name;
  92 } rtl_chip_infos[] = {
  93         /* PCI devices. */
  94         [RTL_GIGA_MAC_VER_02] = {"RTL8169s"                             },
  95         [RTL_GIGA_MAC_VER_03] = {"RTL8110s"                             },
  96         [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb"                     },
  97         [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc"                     },
  98         [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc"                     },
  99         /* PCI-E devices. */
 100         [RTL_GIGA_MAC_VER_07] = {"RTL8102e"                             },
 101         [RTL_GIGA_MAC_VER_08] = {"RTL8102e"                             },
 102         [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e"                    },
 103         [RTL_GIGA_MAC_VER_10] = {"RTL8101e/RTL8100e"                    },
 104         [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b"                       },
 105         [RTL_GIGA_MAC_VER_14] = {"RTL8401"                              },
 106         [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b"                       },
 107         [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp"                     },
 108         [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c"                       },
 109         [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c"                       },
 110         [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c"                       },
 111         [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c"                       },
 112         [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp"                     },
 113         [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp"                     },
 114         [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d",      FIRMWARE_8168D_1},
 115         [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d",      FIRMWARE_8168D_2},
 116         [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp"                     },
 117         [RTL_GIGA_MAC_VER_29] = {"RTL8105e",            FIRMWARE_8105E_1},
 118         [RTL_GIGA_MAC_VER_30] = {"RTL8105e",            FIRMWARE_8105E_1},
 119         [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp"                     },
 120         [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e",      FIRMWARE_8168E_1},
 121         [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e",      FIRMWARE_8168E_2},
 122         [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl",  FIRMWARE_8168E_3},
 123         [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f",      FIRMWARE_8168F_1},
 124         [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f",      FIRMWARE_8168F_2},
 125         [RTL_GIGA_MAC_VER_37] = {"RTL8402",             FIRMWARE_8402_1 },
 126         [RTL_GIGA_MAC_VER_38] = {"RTL8411",             FIRMWARE_8411_1 },
 127         [RTL_GIGA_MAC_VER_39] = {"RTL8106e",            FIRMWARE_8106E_1},
 128         [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g",      FIRMWARE_8168G_2},
 129         [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu",    FIRMWARE_8168G_3},
 130         [RTL_GIGA_MAC_VER_43] = {"RTL8106eus",          FIRMWARE_8106E_2},
 131         [RTL_GIGA_MAC_VER_44] = {"RTL8411b",            FIRMWARE_8411_2 },
 132         [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h",      FIRMWARE_8168H_2},
 133         [RTL_GIGA_MAC_VER_48] = {"RTL8107e",            FIRMWARE_8107E_2},
 134         [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep"                     },
 135         [RTL_GIGA_MAC_VER_52] = {"RTL8168fp/RTL8117",  FIRMWARE_8168FP_3},
 136         [RTL_GIGA_MAC_VER_53] = {"RTL8168fp/RTL8117",                   },
 137         [RTL_GIGA_MAC_VER_61] = {"RTL8125A",            FIRMWARE_8125A_3},
 138         /* reserve 62 for CFG_METHOD_4 in the vendor driver */
 139         [RTL_GIGA_MAC_VER_63] = {"RTL8125B",            FIRMWARE_8125B_2},
 140 };
 141
 142 static const struct pci_device_id rtl8169_pci_tbl[] = {
 143         { PCI_VDEVICE(REALTEK,  0x2502) },
 144         { PCI_VDEVICE(REALTEK,  0x2600) },
 145         { PCI_VDEVICE(REALTEK,  0x8129) },
 146         { PCI_VDEVICE(REALTEK,  0x8136), RTL_CFG_NO_GBIT },
 147         { PCI_VDEVICE(REALTEK,  0x8161) },
 148         { PCI_VDEVICE(REALTEK,  0x8162) },
 149         { PCI_VDEVICE(REALTEK,  0x8167) },
 150         { PCI_VDEVICE(REALTEK,  0x8168) },
 151         { PCI_VDEVICE(NCUBE,    0x8168) },
 152         { PCI_VDEVICE(REALTEK,  0x8169) },
 153         { PCI_VENDOR_ID_DLINK,  0x4300,
 154                 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 },
 155         { PCI_VDEVICE(DLINK,    0x4300) },
 156         { PCI_VDEVICE(DLINK,    0x4302) },
 157         { PCI_VDEVICE(AT,       0xc107) },
 158         { PCI_VDEVICE(USR,      0x0116) },
 159         { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 },
 160         { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 },
 161         { PCI_VDEVICE(REALTEK,  0x8125) },
 162         { PCI_VDEVICE(REALTEK,  0x3000) },
 163         {}
 164 };
 165
 166 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 167
 168 enum rtl_registers {
 169         MAC0            = 0,    /* Ethernet hardware address. */
 170         MAC4            = 4,
 171         MAR0            = 8,    /* Multicast filter. */
 172         CounterAddrLow          = 0x10,
 173         CounterAddrHigh         = 0x14,
 174         TxDescStartAddrLow      = 0x20,
 175         TxDescStartAddrHigh     = 0x24,
 176         TxHDescStartAddrLow     = 0x28,
 177         TxHDescStartAddrHigh    = 0x2c,
 178         FLASH           = 0x30,
 179         ERSR            = 0x36,
 180         ChipCmd         = 0x37,
 181         TxPoll          = 0x38,
 182         IntrMask        = 0x3c,
 183         IntrStatus      = 0x3e,
 184
 185         TxConfig        = 0x40,
 186 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 187 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 188
 189         RxConfig        = 0x44,
 190 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 191 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 192 #define RXCFG_FIFO_SHIFT                13
 193                                         /* No threshold before first PCI xfer */
 194 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 195 #define RX_EARLY_OFF                    (1 << 11)
 196 #define RXCFG_DMA_SHIFT                 8
 197                                         /* Unlimited maximum PCI burst. */
 198 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 199
 200         Cfg9346         = 0x50,
 201         Config0         = 0x51,
 202         Config1         = 0x52,
 203         Config2         = 0x53,
 204 #define PME_SIGNAL                      (1 << 5)        /* 8168c and later */
 205
 206         Config3         = 0x54,
 207         Config4         = 0x55,
 208         Config5         = 0x56,
 209         PHYAR           = 0x60,
 210         PHYstatus       = 0x6c,
 211         RxMaxSize       = 0xda,
 212         CPlusCmd        = 0xe0,
 213         IntrMitigate    = 0xe2,
 214
 215 #define RTL_COALESCE_TX_USECS   GENMASK(15, 12)
 216 #define RTL_COALESCE_TX_FRAMES  GENMASK(11, 8)
 217 #define RTL_COALESCE_RX_USECS   GENMASK(7, 4)
 218 #define RTL_COALESCE_RX_FRAMES  GENMASK(3, 0)
 219
 220 #define RTL_COALESCE_T_MAX      0x0fU
 221 #define RTL_COALESCE_FRAME_MAX  (RTL_COALESCE_T_MAX * 4)
 222
 223         RxDescAddrLow   = 0xe4,
 224         RxDescAddrHigh  = 0xe8,
 225         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 226
 227 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 228
 229         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 230
 231 #define TxPacketMax     (8064 >> 7)
 232 #define EarlySize       0x27
 233
 234         FuncEvent       = 0xf0,
 235         FuncEventMask   = 0xf4,
 236         FuncPresetState = 0xf8,
 237         IBCR0           = 0xf8,
 238         IBCR2           = 0xf9,
 239         IBIMR0          = 0xfa,
 240         IBISR0          = 0xfb,
 241         FuncForceEvent  = 0xfc,
 242 };
 243
 244 enum rtl8168_8101_registers {
 245         CSIDR                   = 0x64,
 246         CSIAR                   = 0x68,
 247 #define CSIAR_FLAG                      0x80000000
 248 #define CSIAR_WRITE_CMD                 0x80000000
 249 #define CSIAR_BYTE_ENABLE               0x0000f000
 250 #define CSIAR_ADDR_MASK                 0x00000fff
 251         PMCH                    = 0x6f,
 252 #define D3COLD_NO_PLL_DOWN              BIT(7)
 253 #define D3HOT_NO_PLL_DOWN               BIT(6)
 254 #define D3_NO_PLL_DOWN                  (BIT(7) | BIT(6))
 255         EPHYAR                  = 0x80,
 256 #define EPHYAR_FLAG                     0x80000000
 257 #define EPHYAR_WRITE_CMD                0x80000000
 258 #define EPHYAR_REG_MASK                 0x1f
 259 #define EPHYAR_REG_SHIFT                16
 260 #define EPHYAR_DATA_MASK                0xffff
 261         DLLPR                   = 0xd0,
 262 #define PFM_EN                          (1 << 6)
 263 #define TX_10M_PS_EN                    (1 << 7)
 264         DBG_REG                 = 0xd1,
 265 #define FIX_NAK_1                       (1 << 4)
 266 #define FIX_NAK_2                       (1 << 3)
 267         TWSI                    = 0xd2,
 268         MCU                     = 0xd3,
 269 #define NOW_IS_OOB                      (1 << 7)
 270 #define TX_EMPTY                        (1 << 5)
 271 #define RX_EMPTY                        (1 << 4)
 272 #define RXTX_EMPTY                      (TX_EMPTY | RX_EMPTY)
 273 #define EN_NDP                          (1 << 3)
 274 #define EN_OOB_RESET                    (1 << 2)
 275 #define LINK_LIST_RDY                   (1 << 1)
 276         EFUSEAR                 = 0xdc,
 277 #define EFUSEAR_FLAG                    0x80000000
 278 #define EFUSEAR_WRITE_CMD               0x80000000
 279 #define EFUSEAR_READ_CMD                0x00000000
 280 #define EFUSEAR_REG_MASK                0x03ff
 281 #define EFUSEAR_REG_SHIFT               8
 282 #define EFUSEAR_DATA_MASK               0xff
 283         MISC_1                  = 0xf2,
 284 #define PFM_D3COLD_EN                   (1 << 6)
 285 };
 286
 287 enum rtl8168_registers {
 288         LED_FREQ                = 0x1a,
 289         EEE_LED                 = 0x1b,
 290         ERIDR                   = 0x70,
 291         ERIAR                   = 0x74,
 292 #define ERIAR_FLAG                      0x80000000
 293 #define ERIAR_WRITE_CMD                 0x80000000
 294 #define ERIAR_READ_CMD                  0x00000000
 295 #define ERIAR_ADDR_BYTE_ALIGN           4
 296 #define ERIAR_TYPE_SHIFT                16
 297 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 298 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 299 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 300 #define ERIAR_OOB                       (0x02 << ERIAR_TYPE_SHIFT)
 301 #define ERIAR_MASK_SHIFT                12
 302 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 303 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 304 #define ERIAR_MASK_0100                 (0x4 << ERIAR_MASK_SHIFT)
 305 #define ERIAR_MASK_0101                 (0x5 << ERIAR_MASK_SHIFT)
 306 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 307         EPHY_RXER_NUM           = 0x7c,
 308         OCPDR                   = 0xb0, /* OCP GPHY access */
 309 #define OCPDR_WRITE_CMD                 0x80000000
 310 #define OCPDR_READ_CMD                  0x00000000
 311 #define OCPDR_REG_MASK                  0x7f
 312 #define OCPDR_GPHY_REG_SHIFT            16
 313 #define OCPDR_DATA_MASK                 0xffff
 314         OCPAR                   = 0xb4,
 315 #define OCPAR_FLAG                      0x80000000
 316 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 317 #define OCPAR_GPHY_READ_CMD             0x0000f060
 318         GPHY_OCP                = 0xb8,
 319         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 320         MISC                    = 0xf0, /* 8168e only. */
 321 #define TXPLA_RST                       (1 << 29)
 322 #define DISABLE_LAN_EN                  (1 << 23) /* Enable GPIO pin */
 323 #define PWM_EN                          (1 << 22)
 324 #define RXDV_GATED_EN                   (1 << 19)
 325 #define EARLY_TALLY_EN                  (1 << 16)
 326 };
 327
 328 enum rtl8125_registers {
 329         IntrMask_8125           = 0x38,
 330         IntrStatus_8125         = 0x3c,
 331         TxPoll_8125             = 0x90,
 332         MAC0_BKP                = 0x19e0,
 333         EEE_TXIDLE_TIMER_8125   = 0x6048,
 334 };
 335
 336 #define RX_VLAN_INNER_8125      BIT(22)
 337 #define RX_VLAN_OUTER_8125      BIT(23)
 338 #define RX_VLAN_8125            (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125)
 339
 340 #define RX_FETCH_DFLT_8125      (8 << 27)
 341
 342 enum rtl_register_content {
 343         /* InterruptStatusBits */
 344         SYSErr          = 0x8000,
 345         PCSTimeout      = 0x4000,
 346         SWInt           = 0x0100,
 347         TxDescUnavail   = 0x0080,
 348         RxFIFOOver      = 0x0040,
 349         LinkChg         = 0x0020,
 350         RxOverflow      = 0x0010,
 351         TxErr           = 0x0008,
 352         TxOK            = 0x0004,
 353         RxErr           = 0x0002,
 354         RxOK            = 0x0001,
 355
 356         /* RxStatusDesc */
 357         RxRWT   = (1 << 22),
 358         RxRES   = (1 << 21),
 359         RxRUNT  = (1 << 20),
 360         RxCRC   = (1 << 19),
 361
 362         /* ChipCmdBits */
 363         StopReq         = 0x80,
 364         CmdReset        = 0x10,
 365         CmdRxEnb        = 0x08,
 366         CmdTxEnb        = 0x04,
 367         RxBufEmpty      = 0x01,
 368
 369         /* TXPoll register p.5 */
 370         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 371         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 372         FSWInt          = 0x01,         /* Forced software interrupt */
 373
 374         /* Cfg9346Bits */
 375         Cfg9346_Lock    = 0x00,
 376         Cfg9346_Unlock  = 0xc0,
 377
 378         /* rx_mode_bits */
 379         AcceptErr       = 0x20,
 380         AcceptRunt      = 0x10,
 381 #define RX_CONFIG_ACCEPT_ERR_MASK       0x30
 382         AcceptBroadcast = 0x08,
 383         AcceptMulticast = 0x04,
 384         AcceptMyPhys    = 0x02,
 385         AcceptAllPhys   = 0x01,
 386 #define RX_CONFIG_ACCEPT_OK_MASK        0x0f
 387 #define RX_CONFIG_ACCEPT_MASK           0x3f
 388
 389         /* TxConfigBits */
 390         TxInterFrameGapShift = 24,
 391         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 392
 393         /* Config1 register p.24 */
 394         LEDS1           = (1 << 7),
 395         LEDS0           = (1 << 6),
 396         Speed_down      = (1 << 4),
 397         MEMMAP          = (1 << 3),
 398         IOMAP           = (1 << 2),
 399         VPD             = (1 << 1),
 400         PMEnable        = (1 << 0),     /* Power Management Enable */
 401
 402         /* Config2 register p. 25 */
 403         ClkReqEn        = (1 << 7),     /* Clock Request Enable */
 404         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
 405         PCI_Clock_66MHz = 0x01,
 406         PCI_Clock_33MHz = 0x00,
 407
 408         /* Config3 register p.25 */
 409         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 410         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 411         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
 412         Rdy_to_L23      = (1 << 1),     /* L23 Enable */
 413         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 414
 415         /* Config4 register */
 416         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
 417
 418         /* Config5 register p.27 */
 419         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 420         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 421         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 422         Spi_en          = (1 << 3),
 423         LanWake         = (1 << 1),     /* LanWake enable/disable */
 424         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 425         ASPM_en         = (1 << 0),     /* ASPM enable */
 426
 427         /* CPlusCmd p.31 */
 428         EnableBist      = (1 << 15),    // 8168 8101
 429         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 430         EnAnaPLL        = (1 << 14),    // 8169
 431         Normal_mode     = (1 << 13),    // unused
 432         Force_half_dup  = (1 << 12),    // 8168 8101
 433         Force_rxflow_en = (1 << 11),    // 8168 8101
 434         Force_txflow_en = (1 << 10),    // 8168 8101
 435         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 436         ASF             = (1 << 8),     // 8168 8101
 437         PktCntrDisable  = (1 << 7),     // 8168 8101
 438         Mac_dbgo_sel    = 0x001c,       // 8168
 439         RxVlan          = (1 << 6),
 440         RxChkSum        = (1 << 5),
 441         PCIDAC          = (1 << 4),
 442         PCIMulRW        = (1 << 3),
 443 #define INTT_MASK       GENMASK(1, 0)
 444 #define CPCMD_MASK      (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
 445
 446         /* rtl8169_PHYstatus */
 447         TBI_Enable      = 0x80,
 448         TxFlowCtrl      = 0x40,
 449         RxFlowCtrl      = 0x20,
 450         _1000bpsF       = 0x10,
 451         _100bps         = 0x08,
 452         _10bps          = 0x04,
 453         LinkStatus      = 0x02,
 454         FullDup         = 0x01,
 455
 456         /* ResetCounterCommand */
 457         CounterReset    = 0x1,
 458
 459         /* DumpCounterCommand */
 460         CounterDump     = 0x8,
 461
 462         /* magic enable v2 */
 463         MagicPacket_v2  = (1 << 16),    /* Wake up when receives a Magic Packet */
 464 };
 465
 466 enum rtl_desc_bit {
 467         /* First doubleword. */
 468         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 469         RingEnd         = (1 << 30), /* End of descriptor ring */
 470         FirstFrag       = (1 << 29), /* First segment of a packet */
 471         LastFrag        = (1 << 28), /* Final segment of a packet */
 472 };
 473
 474 /* Generic case. */
 475 enum rtl_tx_desc_bit {
 476         /* First doubleword. */
 477         TD_LSO          = (1 << 27),            /* Large Send Offload */
 478 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 479
 480         /* Second doubleword. */
 481         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 482 };
 483
 484 /* 8169, 8168b and 810x except 8102e. */
 485 enum rtl_tx_desc_bit_0 {
 486         /* First doubleword. */
 487 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 488         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 489         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 490         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 491 };
 492
 493 /* 8102e, 8168c and beyond. */
 494 enum rtl_tx_desc_bit_1 {
 495         /* First doubleword. */
 496         TD1_GTSENV4     = (1 << 26),            /* Giant Send for IPv4 */
 497         TD1_GTSENV6     = (1 << 25),            /* Giant Send for IPv6 */
 498 #define GTTCPHO_SHIFT                   18
 499 #define GTTCPHO_MAX                     0x7f
 500
 501         /* Second doubleword. */
 502 #define TCPHO_SHIFT                     18
 503 #define TCPHO_MAX                       0x3ff
 504 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 505         TD1_IPv6_CS     = (1 << 28),            /* Calculate IPv6 checksum */
 506         TD1_IPv4_CS     = (1 << 29),            /* Calculate IPv4 checksum */
 507         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 508         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 509 };
 510
 511 enum rtl_rx_desc_bit {
 512         /* Rx private */
 513         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 514         PID0            = (1 << 17), /* Protocol ID bit 0/2 */
 515
 516 #define RxProtoUDP      (PID1)
 517 #define RxProtoTCP      (PID0)
 518 #define RxProtoIP       (PID1 | PID0)
 519 #define RxProtoMask     RxProtoIP
 520
 521         IPFail          = (1 << 16), /* IP checksum failed */
 522         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 523         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 524
 525 #define RxCSFailMask    (IPFail | UDPFail | TCPFail)
 526
 527         RxVlanTag       = (1 << 16), /* VLAN tag available */
 528 };
 529
 530 #define RTL_GSO_MAX_SIZE_V1     32000
 531 #define RTL_GSO_MAX_SEGS_V1     24
 532 #define RTL_GSO_MAX_SIZE_V2     64000
 533 #define RTL_GSO_MAX_SEGS_V2     64
 534
 535 struct TxDesc {
 536         __le32 opts1;
 537         __le32 opts2;
 538         __le64 addr;
 539 };
 540
 541 struct RxDesc {
 542         __le32 opts1;
 543         __le32 opts2;
 544         __le64 addr;
 545 };
 546
 547 struct ring_info {
 548         struct sk_buff  *skb;
 549         u32             len;
 550 };
 551
 552 struct rtl8169_counters {
 553         __le64  tx_packets;
 554         __le64  rx_packets;
 555         __le64  tx_errors;
 556         __le32  rx_errors;
 557         __le16  rx_missed;
 558         __le16  align_errors;
 559         __le32  tx_one_collision;
 560         __le32  tx_multi_collision;
 561         __le64  rx_unicast;
 562         __le64  rx_broadcast;
 563         __le32  rx_multicast;
 564         __le16  tx_aborted;
 565         __le16  tx_underun;
 566 };
 567
 568 struct rtl8169_tc_offsets {
 569         bool    inited;
 570         __le64  tx_errors;
 571         __le32  tx_multi_collision;
 572         __le16  tx_aborted;
 573         __le16  rx_missed;
 574 };
 575
 576 enum rtl_flag {
 577         RTL_FLAG_TASK_ENABLED = 0,
 578         RTL_FLAG_TASK_RESET_PENDING,
 579         RTL_FLAG_MAX
 580 };
 581
 582 enum rtl_dash_type {
 583         RTL_DASH_NONE,
 584         RTL_DASH_DP,
 585         RTL_DASH_EP,
 586 };
 587
 588 struct rtl8169_private {
 589         void __iomem *mmio_addr;        /* memory map physical address */
 590         struct pci_dev *pci_dev;
 591         struct net_device *dev;
 592         struct phy_device *phydev;
 593         struct napi_struct napi;
 594         enum mac_version mac_version;
 595         enum rtl_dash_type dash_type;
 596         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 597         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 598         u32 dirty_tx;
 599         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 600         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 601         dma_addr_t TxPhyAddr;
 602         dma_addr_t RxPhyAddr;
 603         struct page *Rx_databuff[NUM_RX_DESC];  /* Rx data buffers */
 604         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 605         u16 cp_cmd;
 606         u32 irq_mask;
 607         int irq;
 608         struct clk *clk;
 609
 610         struct {
 611                 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
 612                 struct work_struct work;
 613         } wk;
 614
 615         unsigned supports_gmii:1;
 616         unsigned aspm_manageable:1;
 617         dma_addr_t counters_phys_addr;
 618         struct rtl8169_counters *counters;
 619         struct rtl8169_tc_offsets tc_offset;
 620         u32 saved_wolopts;
 621         int eee_adv;
 622
 623         const char *fw_name;
 624         struct rtl_fw *rtl_fw;
 625
 626         u32 ocp_base;
 627 };
 628
 629 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp);
 630
 631 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 632 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 633 MODULE_SOFTDEP("pre: realtek");
 634 MODULE_LICENSE("GPL");
 635 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 636 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 637 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 638 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 639 MODULE_FIRMWARE(FIRMWARE_8168E_3);
 640 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 641 MODULE_FIRMWARE(FIRMWARE_8168F_1);
 642 MODULE_FIRMWARE(FIRMWARE_8168F_2);
 643 MODULE_FIRMWARE(FIRMWARE_8402_1);
 644 MODULE_FIRMWARE(FIRMWARE_8411_1);
 645 MODULE_FIRMWARE(FIRMWARE_8411_2);
 646 MODULE_FIRMWARE(FIRMWARE_8106E_1);
 647 MODULE_FIRMWARE(FIRMWARE_8106E_2);
 648 MODULE_FIRMWARE(FIRMWARE_8168G_2);
 649 MODULE_FIRMWARE(FIRMWARE_8168G_3);
 650 MODULE_FIRMWARE(FIRMWARE_8168H_2);
 651 MODULE_FIRMWARE(FIRMWARE_8168FP_3);
 652 MODULE_FIRMWARE(FIRMWARE_8107E_2);
 653 MODULE_FIRMWARE(FIRMWARE_8125A_3);
 654 MODULE_FIRMWARE(FIRMWARE_8125B_2);
 655
 656 static inline struct device *tp_to_dev(struct rtl8169_private *tp)
 657 {
 658         return &tp->pci_dev->dev;
 659 }
 660
 661 static void rtl_lock_config_regs(struct rtl8169_private *tp)
 662 {
 663         RTL_W8(tp, Cfg9346, Cfg9346_Lock);
 664 }
 665
 666 static void rtl_unlock_config_regs(struct rtl8169_private *tp)
 667 {
 668         RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
 669 }
 670
 671 static void rtl_pci_commit(struct rtl8169_private *tp)
 672 {
 673         /* Read an arbitrary register to commit a preceding PCI write */
 674         RTL_R8(tp, ChipCmd);
 675 }
 676
 677 static bool rtl_is_8125(struct rtl8169_private *tp)
 678 {
 679         return tp->mac_version >= RTL_GIGA_MAC_VER_61;
 680 }
 681
 682 static bool rtl_is_8168evl_up(struct rtl8169_private *tp)
 683 {
 684         return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
 685                tp->mac_version != RTL_GIGA_MAC_VER_39 &&
 686                tp->mac_version <= RTL_GIGA_MAC_VER_53;
 687 }
 688
 689 static bool rtl_supports_eee(struct rtl8169_private *tp)
 690 {
 691         return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
 692                tp->mac_version != RTL_GIGA_MAC_VER_37 &&
 693                tp->mac_version != RTL_GIGA_MAC_VER_39;
 694 }
 695
 696 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg)
 697 {
 698         int i;
 699
 700         for (i = 0; i < ETH_ALEN; i++)
 701                 mac[i] = RTL_R8(tp, reg + i);
 702 }
 703
 704 struct rtl_cond {
 705         bool (*check)(struct rtl8169_private *);
 706         const char *msg;
 707 };
 708
 709 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
 710                           unsigned long usecs, int n, bool high)
 711 {
 712         int i;
 713
 714         for (i = 0; i < n; i++) {
 715                 if (c->check(tp) == high)
 716                         return true;
 717                 fsleep(usecs);
 718         }
 719
 720         if (net_ratelimit())
 721                 netdev_err(tp->dev, "%s == %d (loop: %d, delay: %lu).\n",
 722                            c->msg, !high, n, usecs);
 723         return false;
 724 }
 725
 726 static bool rtl_loop_wait_high(struct rtl8169_private *tp,
 727                                const struct rtl_cond *c,
 728                                unsigned long d, int n)
 729 {
 730         return rtl_loop_wait(tp, c, d, n, true);
 731 }
 732
 733 static bool rtl_loop_wait_low(struct rtl8169_private *tp,
 734                               const struct rtl_cond *c,
 735                               unsigned long d, int n)
 736 {
 737         return rtl_loop_wait(tp, c, d, n, false);
 738 }
 739
 740 #define DECLARE_RTL_COND(name)                          \
 741 static bool name ## _check(struct rtl8169_private *);   \
 742                                                         \
 743 static const struct rtl_cond name = {                   \
 744         .check  = name ## _check,                       \
 745         .msg    = #name                                 \
 746 };                                                      \
 747                                                         \
 748 static bool name ## _check(struct rtl8169_private *tp)
 749
 750 static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type)
 751 {
 752         /* based on RTL8168FP_OOBMAC_BASE in vendor driver */
 753         if (type == ERIAR_OOB &&
 754             (tp->mac_version == RTL_GIGA_MAC_VER_52 ||
 755              tp->mac_version == RTL_GIGA_MAC_VER_53))
 756                 *cmd |= 0xf70 << 18;
 757 }
 758
 759 DECLARE_RTL_COND(rtl_eriar_cond)
 760 {
 761         return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
 762 }
 763
 764 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
 765                            u32 val, int type)
 766 {
 767         u32 cmd = ERIAR_WRITE_CMD | type | mask | addr;
 768
 769         if (WARN(addr & 3 || !mask, "addr: 0x%x, mask: 0x%08x\n", addr, mask))
 770                 return;
 771
 772         RTL_W32(tp, ERIDR, val);
 773         r8168fp_adjust_ocp_cmd(tp, &cmd, type);
 774         RTL_W32(tp, ERIAR, cmd);
 775
 776         rtl_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
 777 }
 778
 779 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
 780                           u32 val)
 781 {
 782         _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC);
 783 }
 784
 785 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
 786 {
 787         u32 cmd = ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr;
 788
 789         r8168fp_adjust_ocp_cmd(tp, &cmd, type);
 790         RTL_W32(tp, ERIAR, cmd);
 791
 792         return rtl_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
 793                 RTL_R32(tp, ERIDR) : ~0;
 794 }
 795
 796 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr)
 797 {
 798         return _rtl_eri_read(tp, addr, ERIAR_EXGMAC);
 799 }
 800
 801 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 p, u32 m)
 802 {
 803         u32 val = rtl_eri_read(tp, addr);
 804
 805         rtl_eri_write(tp, addr, ERIAR_MASK_1111, (val & ~m) | p);
 806 }
 807
 808 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 p)
 809 {
 810         rtl_w0w1_eri(tp, addr, p, 0);
 811 }
 812
 813 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 m)
 814 {
 815         rtl_w0w1_eri(tp, addr, 0, m);
 816 }
 817
 818 static bool rtl_ocp_reg_failure(u32 reg)
 819 {
 820         return WARN_ONCE(reg & 0xffff0001, "Invalid ocp reg %x!\n", reg);
 821 }
 822
 823 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
 824 {
 825         return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
 826 }
 827
 828 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 829 {
 830         if (rtl_ocp_reg_failure(reg))
 831                 return;
 832
 833         RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
 834
 835         rtl_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
 836 }
 837
 838 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
 839 {
 840         if (rtl_ocp_reg_failure(reg))
 841                 return 0;
 842
 843         RTL_W32(tp, GPHY_OCP, reg << 15);
 844
 845         return rtl_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
 846                 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT;
 847 }
 848
 849 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 850 {
 851         if (rtl_ocp_reg_failure(reg))
 852                 return;
 853
 854         RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
 855 }
 856
 857 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
 858 {
 859         if (rtl_ocp_reg_failure(reg))
 860                 return 0;
 861
 862         RTL_W32(tp, OCPDR, reg << 15);
 863
 864         return RTL_R32(tp, OCPDR);
 865 }
 866
 867 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask,
 868                                  u16 set)
 869 {
 870         u16 data = r8168_mac_ocp_read(tp, reg);
 871
 872         r8168_mac_ocp_write(tp, reg, (data & ~mask) | set);
 873 }
 874
 875 /* Work around a hw issue with RTL8168g PHY, the quirk disables
 876  * PHY MCU interrupts before PHY power-down.
 877  */
 878 static void rtl8168g_phy_suspend_quirk(struct rtl8169_private *tp, int value)
 879 {
 880         switch (tp->mac_version) {
 881         case RTL_GIGA_MAC_VER_40:
 882                 if (value & BMCR_RESET || !(value & BMCR_PDOWN))
 883                         rtl_eri_set_bits(tp, 0x1a8, 0xfc000000);
 884                 else
 885                         rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000);
 886                 break;
 887         default:
 888                 break;
 889         }
 890 };
 891
 892 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
 893 {
 894         if (reg == 0x1f) {
 895                 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
 896                 return;
 897         }
 898
 899         if (tp->ocp_base != OCP_STD_PHY_BASE)
 900                 reg -= 0x10;
 901
 902         if (tp->ocp_base == OCP_STD_PHY_BASE && reg == MII_BMCR)
 903                 rtl8168g_phy_suspend_quirk(tp, value);
 904
 905         r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
 906 }
 907
 908 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
 909 {
 910         if (reg == 0x1f)
 911                 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4;
 912
 913         if (tp->ocp_base != OCP_STD_PHY_BASE)
 914                 reg -= 0x10;
 915
 916         return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
 917 }
 918
 919 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
 920 {
 921         if (reg == 0x1f) {
 922                 tp->ocp_base = value << 4;
 923                 return;
 924         }
 925
 926         r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
 927 }
 928
 929 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
 930 {
 931         return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
 932 }
 933
 934 DECLARE_RTL_COND(rtl_phyar_cond)
 935 {
 936         return RTL_R32(tp, PHYAR) & 0x80000000;
 937 }
 938
 939 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
 940 {
 941         RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
 942
 943         rtl_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
 944         /*
 945          * According to hardware specs a 20us delay is required after write
 946          * complete indication, but before sending next command.
 947          */
 948         udelay(20);
 949 }
 950
 951 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
 952 {
 953         int value;
 954
 955         RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
 956
 957         value = rtl_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
 958                 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT;
 959
 960         /*
 961          * According to hardware specs a 20us delay is required after read
 962          * complete indication, but before sending next command.
 963          */
 964         udelay(20);
 965
 966         return value;
 967 }
 968
 969 DECLARE_RTL_COND(rtl_ocpar_cond)
 970 {
 971         return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
 972 }
 973
 974 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
 975
 976 static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
 977 {
 978         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
 979 }
 980
 981 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
 982 {
 983         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
 984 }
 985
 986 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
 987 {
 988         r8168dp_2_mdio_start(tp);
 989
 990         r8169_mdio_write(tp, reg, value);
 991
 992         r8168dp_2_mdio_stop(tp);
 993 }
 994
 995 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
 996 {
 997         int value;
 998
 999         /* Work around issue with chip reporting wrong PHY ID */
1000         if (reg == MII_PHYSID2)
1001                 return 0xc912;
1002
1003         r8168dp_2_mdio_start(tp);
1004
1005         value = r8169_mdio_read(tp, reg);
1006
1007         r8168dp_2_mdio_stop(tp);
1008
1009         return value;
1010 }
1011
1012 static void rtl_writephy(struct rtl8169_private *tp, int location, int val)
1013 {
1014         switch (tp->mac_version) {
1015         case RTL_GIGA_MAC_VER_28:
1016         case RTL_GIGA_MAC_VER_31:
1017                 r8168dp_2_mdio_write(tp, location, val);
1018                 break;
1019         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
1020                 r8168g_mdio_write(tp, location, val);
1021                 break;
1022         default:
1023                 r8169_mdio_write(tp, location, val);
1024                 break;
1025         }
1026 }
1027
1028 static int rtl_readphy(struct rtl8169_private *tp, int location)
1029 {
1030         switch (tp->mac_version) {
1031         case RTL_GIGA_MAC_VER_28:
1032         case RTL_GIGA_MAC_VER_31:
1033                 return r8168dp_2_mdio_read(tp, location);
1034         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
1035                 return r8168g_mdio_read(tp, location);
1036         default:
1037                 return r8169_mdio_read(tp, location);
1038         }
1039 }
1040
1041 DECLARE_RTL_COND(rtl_ephyar_cond)
1042 {
1043         return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1044 }
1045
1046 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1047 {
1048         RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1049                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1050
1051         rtl_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1052
1053         udelay(10);
1054 }
1055
1056 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1057 {
1058         RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1059
1060         return rtl_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1061                 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1062 }
1063
1064 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u16 reg)
1065 {
1066         RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff));
1067         return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1068                 RTL_R32(tp, OCPDR) : ~0;
1069 }
1070
1071 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u16 reg)
1072 {
1073         return _rtl_eri_read(tp, reg, ERIAR_OOB);
1074 }
1075
1076 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1077                               u32 data)
1078 {
1079         RTL_W32(tp, OCPDR, data);
1080         RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1081         rtl_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1082 }
1083
1084 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1085                               u32 data)
1086 {
1087         _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1088                        data, ERIAR_OOB);
1089 }
1090
1091 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd)
1092 {
1093         rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd);
1094
1095         r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001);
1096 }
1097
1098 #define OOB_CMD_RESET           0x00
1099 #define OOB_CMD_DRIVER_START    0x05
1100 #define OOB_CMD_DRIVER_STOP     0x06
1101
1102 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1103 {
1104         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1105 }
1106
1107 DECLARE_RTL_COND(rtl_dp_ocp_read_cond)
1108 {
1109         u16 reg;
1110
1111         reg = rtl8168_get_ocp_reg(tp);
1112
1113         return r8168dp_ocp_read(tp, reg) & 0x00000800;
1114 }
1115
1116 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1117 {
1118         return r8168ep_ocp_read(tp, 0x124) & 0x00000001;
1119 }
1120
1121 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1122 {
1123         return RTL_R8(tp, IBISR0) & 0x20;
1124 }
1125
1126 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1127 {
1128         RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1129         rtl_loop_wait_high(tp, &rtl_ocp_tx_cond, 50000, 2000);
1130         RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1131         RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1132 }
1133
1134 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1135 {
1136         r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START);
1137         rtl_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10000, 10);
1138 }
1139
1140 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1141 {
1142         r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1143         r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01);
1144         rtl_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10000, 10);
1145 }
1146
1147 static void rtl8168_driver_start(struct rtl8169_private *tp)
1148 {
1149         if (tp->dash_type == RTL_DASH_DP)
1150                 rtl8168dp_driver_start(tp);
1151         else
1152                 rtl8168ep_driver_start(tp);
1153 }
1154
1155 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1156 {
1157         r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1158         rtl_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10000, 10);
1159 }
1160
1161 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1162 {
1163         rtl8168ep_stop_cmac(tp);
1164         r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1165         r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01);
1166         rtl_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10000, 10);
1167 }
1168
1169 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1170 {
1171         if (tp->dash_type == RTL_DASH_DP)
1172                 rtl8168dp_driver_stop(tp);
1173         else
1174                 rtl8168ep_driver_stop(tp);
1175 }
1176
1177 static bool r8168dp_check_dash(struct rtl8169_private *tp)
1178 {
1179         u16 reg = rtl8168_get_ocp_reg(tp);
1180
1181         return r8168dp_ocp_read(tp, reg) & BIT(15);
1182 }
1183
1184 static bool r8168ep_check_dash(struct rtl8169_private *tp)
1185 {
1186         return r8168ep_ocp_read(tp, 0x128) & BIT(0);
1187 }
1188
1189 static enum rtl_dash_type rtl_check_dash(struct rtl8169_private *tp)
1190 {
1191         switch (tp->mac_version) {
1192         case RTL_GIGA_MAC_VER_28:
1193         case RTL_GIGA_MAC_VER_31:
1194                 return r8168dp_check_dash(tp) ? RTL_DASH_DP : RTL_DASH_NONE;
1195         case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_53:
1196                 return r8168ep_check_dash(tp) ? RTL_DASH_EP : RTL_DASH_NONE;
1197         default:
1198                 return RTL_DASH_NONE;
1199         }
1200 }
1201
1202 static void rtl_set_d3_pll_down(struct rtl8169_private *tp, bool enable)
1203 {
1204         switch (tp->mac_version) {
1205         case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_26:
1206         case RTL_GIGA_MAC_VER_29 ... RTL_GIGA_MAC_VER_30:
1207         case RTL_GIGA_MAC_VER_32 ... RTL_GIGA_MAC_VER_37:
1208         case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63:
1209                 if (enable)
1210                         RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~D3_NO_PLL_DOWN);
1211                 else
1212                         RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | D3_NO_PLL_DOWN);
1213                 break;
1214         default:
1215                 break;
1216         }
1217 }
1218
1219 static void rtl_reset_packet_filter(struct rtl8169_private *tp)
1220 {
1221         rtl_eri_clear_bits(tp, 0xdc, BIT(0));
1222         rtl_eri_set_bits(tp, 0xdc, BIT(0));
1223 }
1224
1225 DECLARE_RTL_COND(rtl_efusear_cond)
1226 {
1227         return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1228 }
1229
1230 u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1231 {
1232         RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1233
1234         return rtl_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1235                 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1236 }
1237
1238 static u32 rtl_get_events(struct rtl8169_private *tp)
1239 {
1240         if (rtl_is_8125(tp))
1241                 return RTL_R32(tp, IntrStatus_8125);
1242         else
1243                 return RTL_R16(tp, IntrStatus);
1244 }
1245
1246 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits)
1247 {
1248         if (rtl_is_8125(tp))
1249                 RTL_W32(tp, IntrStatus_8125, bits);
1250         else
1251                 RTL_W16(tp, IntrStatus, bits);
1252 }
1253
1254 static void rtl_irq_disable(struct rtl8169_private *tp)
1255 {
1256         if (rtl_is_8125(tp))
1257                 RTL_W32(tp, IntrMask_8125, 0);
1258         else
1259                 RTL_W16(tp, IntrMask, 0);
1260 }
1261
1262 static void rtl_irq_enable(struct rtl8169_private *tp)
1263 {
1264         if (rtl_is_8125(tp))
1265                 RTL_W32(tp, IntrMask_8125, tp->irq_mask);
1266         else
1267                 RTL_W16(tp, IntrMask, tp->irq_mask);
1268 }
1269
1270 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1271 {
1272         rtl_irq_disable(tp);
1273         rtl_ack_events(tp, 0xffffffff);
1274         rtl_pci_commit(tp);
1275 }
1276
1277 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1278 {
1279         struct phy_device *phydev = tp->phydev;
1280
1281         if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1282             tp->mac_version == RTL_GIGA_MAC_VER_38) {
1283                 if (phydev->speed == SPEED_1000) {
1284                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1285                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1286                 } else if (phydev->speed == SPEED_100) {
1287                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1288                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1289                 } else {
1290                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1291                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1292                 }
1293                 rtl_reset_packet_filter(tp);
1294         } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1295                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
1296                 if (phydev->speed == SPEED_1000) {
1297                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1298                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1299                 } else {
1300                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1301                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1302                 }
1303         } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1304                 if (phydev->speed == SPEED_10) {
1305                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02);
1306                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a);
1307                 } else {
1308                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
1309                 }
1310         }
1311 }
1312
1313 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1314
1315 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1316 {
1317         struct rtl8169_private *tp = netdev_priv(dev);
1318
1319         wol->supported = WAKE_ANY;
1320         wol->wolopts = tp->saved_wolopts;
1321 }
1322
1323 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1324 {
1325         static const struct {
1326                 u32 opt;
1327                 u16 reg;
1328                 u8  mask;
1329         } cfg[] = {
1330                 { WAKE_PHY,   Config3, LinkUp },
1331                 { WAKE_UCAST, Config5, UWF },
1332                 { WAKE_BCAST, Config5, BWF },
1333                 { WAKE_MCAST, Config5, MWF },
1334                 { WAKE_ANY,   Config5, LanWake },
1335                 { WAKE_MAGIC, Config3, MagicPacket }
1336         };
1337         unsigned int i, tmp = ARRAY_SIZE(cfg);
1338         u8 options;
1339
1340         rtl_unlock_config_regs(tp);
1341
1342         if (rtl_is_8168evl_up(tp)) {
1343                 tmp--;
1344                 if (wolopts & WAKE_MAGIC)
1345                         rtl_eri_set_bits(tp, 0x0dc, MagicPacket_v2);
1346                 else
1347                         rtl_eri_clear_bits(tp, 0x0dc, MagicPacket_v2);
1348         } else if (rtl_is_8125(tp)) {
1349                 tmp--;
1350                 if (wolopts & WAKE_MAGIC)
1351                         r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0));
1352                 else
1353                         r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0);
1354         }
1355
1356         for (i = 0; i < tmp; i++) {
1357                 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
1358                 if (wolopts & cfg[i].opt)
1359                         options |= cfg[i].mask;
1360                 RTL_W8(tp, cfg[i].reg, options);
1361         }
1362
1363         switch (tp->mac_version) {
1364         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
1365                 options = RTL_R8(tp, Config1) & ~PMEnable;
1366                 if (wolopts)
1367                         options |= PMEnable;
1368                 RTL_W8(tp, Config1, options);
1369                 break;
1370         case RTL_GIGA_MAC_VER_34:
1371         case RTL_GIGA_MAC_VER_37:
1372         case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63:
1373                 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
1374                 if (wolopts)
1375                         options |= PME_SIGNAL;
1376                 RTL_W8(tp, Config2, options);
1377                 break;
1378         default:
1379                 break;
1380         }
1381
1382         rtl_lock_config_regs(tp);
1383
1384         device_set_wakeup_enable(tp_to_dev(tp), wolopts);
1385
1386         if (tp->dash_type == RTL_DASH_NONE) {
1387                 rtl_set_d3_pll_down(tp, !wolopts);
1388                 tp->dev->wol_enabled = wolopts ? 1 : 0;
1389         }
1390 }
1391
1392 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1393 {
1394         struct rtl8169_private *tp = netdev_priv(dev);
1395
1396         if (wol->wolopts & ~WAKE_ANY)
1397                 return -EINVAL;
1398
1399         tp->saved_wolopts = wol->wolopts;
1400         __rtl8169_set_wol(tp, tp->saved_wolopts);
1401
1402         return 0;
1403 }
1404
1405 static void rtl8169_get_drvinfo(struct net_device *dev,
1406                                 struct ethtool_drvinfo *info)
1407 {
1408         struct rtl8169_private *tp = netdev_priv(dev);
1409         struct rtl_fw *rtl_fw = tp->rtl_fw;
1410
1411         strscpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
1412         strscpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1413         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1414         if (rtl_fw)
1415                 strscpy(info->fw_version, rtl_fw->version,
1416                         sizeof(info->fw_version));
1417 }
1418
1419 static int rtl8169_get_regs_len(struct net_device *dev)
1420 {
1421         return R8169_REGS_SIZE;
1422 }
1423
1424 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1425         netdev_features_t features)
1426 {
1427         struct rtl8169_private *tp = netdev_priv(dev);
1428
1429         if (dev->mtu > TD_MSS_MAX)
1430                 features &= ~NETIF_F_ALL_TSO;
1431
1432         if (dev->mtu > ETH_DATA_LEN &&
1433             tp->mac_version > RTL_GIGA_MAC_VER_06)
1434                 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_ALL_TSO);
1435
1436         return features;
1437 }
1438
1439 static void rtl_set_rx_config_features(struct rtl8169_private *tp,
1440                                        netdev_features_t features)
1441 {
1442         u32 rx_config = RTL_R32(tp, RxConfig);
1443
1444         if (features & NETIF_F_RXALL)
1445                 rx_config |= RX_CONFIG_ACCEPT_ERR_MASK;
1446         else
1447                 rx_config &= ~RX_CONFIG_ACCEPT_ERR_MASK;
1448
1449         if (rtl_is_8125(tp)) {
1450                 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1451                         rx_config |= RX_VLAN_8125;
1452                 else
1453                         rx_config &= ~RX_VLAN_8125;
1454         }
1455
1456         RTL_W32(tp, RxConfig, rx_config);
1457 }
1458
1459 static int rtl8169_set_features(struct net_device *dev,
1460                                 netdev_features_t features)
1461 {
1462         struct rtl8169_private *tp = netdev_priv(dev);
1463
1464         rtl_set_rx_config_features(tp, features);
1465
1466         if (features & NETIF_F_RXCSUM)
1467                 tp->cp_cmd |= RxChkSum;
1468         else
1469                 tp->cp_cmd &= ~RxChkSum;
1470
1471         if (!rtl_is_8125(tp)) {
1472                 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1473                         tp->cp_cmd |= RxVlan;
1474                 else
1475                         tp->cp_cmd &= ~RxVlan;
1476         }
1477
1478         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1479         rtl_pci_commit(tp);
1480
1481         return 0;
1482 }
1483
1484 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1485 {
1486         return (skb_vlan_tag_present(skb)) ?
1487                 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1488 }
1489
1490 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1491 {
1492         u32 opts2 = le32_to_cpu(desc->opts2);
1493
1494         if (opts2 & RxVlanTag)
1495                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1496 }
1497
1498 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1499                              void *p)
1500 {
1501         struct rtl8169_private *tp = netdev_priv(dev);
1502         u32 __iomem *data = tp->mmio_addr;
1503         u32 *dw = p;
1504         int i;
1505
1506         for (i = 0; i < R8169_REGS_SIZE; i += 4)
1507                 memcpy_fromio(dw++, data++, 4);
1508 }
1509
1510 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1511         "tx_packets",
1512         "rx_packets",
1513         "tx_errors",
1514         "rx_errors",
1515         "rx_missed",
1516         "align_errors",
1517         "tx_single_collisions",
1518         "tx_multi_collisions",
1519         "unicast",
1520         "broadcast",
1521         "multicast",
1522         "tx_aborted",
1523         "tx_underrun",
1524 };
1525
1526 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1527 {
1528         switch (sset) {
1529         case ETH_SS_STATS:
1530                 return ARRAY_SIZE(rtl8169_gstrings);
1531         default:
1532                 return -EOPNOTSUPP;
1533         }
1534 }
1535
1536 DECLARE_RTL_COND(rtl_counters_cond)
1537 {
1538         return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
1539 }
1540
1541 static void rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
1542 {
1543         u32 cmd = lower_32_bits(tp->counters_phys_addr);
1544
1545         RTL_W32(tp, CounterAddrHigh, upper_32_bits(tp->counters_phys_addr));
1546         rtl_pci_commit(tp);
1547         RTL_W32(tp, CounterAddrLow, cmd);
1548         RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
1549
1550         rtl_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
1551 }
1552
1553 static void rtl8169_update_counters(struct rtl8169_private *tp)
1554 {
1555         u8 val = RTL_R8(tp, ChipCmd);
1556
1557         /*
1558          * Some chips are unable to dump tally counters when the receiver
1559          * is disabled. If 0xff chip may be in a PCI power-save state.
1560          */
1561         if (val & CmdRxEnb && val != 0xff)
1562                 rtl8169_do_counters(tp, CounterDump);
1563 }
1564
1565 static void rtl8169_init_counter_offsets(struct rtl8169_private *tp)
1566 {
1567         struct rtl8169_counters *counters = tp->counters;
1568
1569         /*
1570          * rtl8169_init_counter_offsets is called from rtl_open.  On chip
1571          * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1572          * reset by a power cycle, while the counter values collected by the
1573          * driver are reset at every driver unload/load cycle.
1574          *
1575          * To make sure the HW values returned by @get_stats64 match the SW
1576          * values, we collect the initial values at first open(*) and use them
1577          * as offsets to normalize the values returned by @get_stats64.
1578          *
1579          * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1580          * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1581          * set at open time by rtl_hw_start.
1582          */
1583
1584         if (tp->tc_offset.inited)
1585                 return;
1586
1587         if (tp->mac_version >= RTL_GIGA_MAC_VER_19) {
1588                 rtl8169_do_counters(tp, CounterReset);
1589         } else {
1590                 rtl8169_update_counters(tp);
1591                 tp->tc_offset.tx_errors = counters->tx_errors;
1592                 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1593                 tp->tc_offset.tx_aborted = counters->tx_aborted;
1594                 tp->tc_offset.rx_missed = counters->rx_missed;
1595         }
1596
1597         tp->tc_offset.inited = true;
1598 }
1599
1600 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1601                                       struct ethtool_stats *stats, u64 *data)
1602 {
1603         struct rtl8169_private *tp = netdev_priv(dev);
1604         struct rtl8169_counters *counters;
1605
1606         counters = tp->counters;
1607         rtl8169_update_counters(tp);
1608
1609         data[0] = le64_to_cpu(counters->tx_packets);
1610         data[1] = le64_to_cpu(counters->rx_packets);
1611         data[2] = le64_to_cpu(counters->tx_errors);
1612         data[3] = le32_to_cpu(counters->rx_errors);
1613         data[4] = le16_to_cpu(counters->rx_missed);
1614         data[5] = le16_to_cpu(counters->align_errors);
1615         data[6] = le32_to_cpu(counters->tx_one_collision);
1616         data[7] = le32_to_cpu(counters->tx_multi_collision);
1617         data[8] = le64_to_cpu(counters->rx_unicast);
1618         data[9] = le64_to_cpu(counters->rx_broadcast);
1619         data[10] = le32_to_cpu(counters->rx_multicast);
1620         data[11] = le16_to_cpu(counters->tx_aborted);
1621         data[12] = le16_to_cpu(counters->tx_underun);
1622 }
1623
1624 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1625 {
1626         switch(stringset) {
1627         case ETH_SS_STATS:
1628                 memcpy(data, rtl8169_gstrings, sizeof(rtl8169_gstrings));
1629                 break;
1630         }
1631 }
1632
1633 /*
1634  * Interrupt coalescing
1635  *
1636  * > 1 - the availability of the IntrMitigate (0xe2) register through the
1637  * >     8169, 8168 and 810x line of chipsets
1638  *
1639  * 8169, 8168, and 8136(810x) serial chipsets support it.
1640  *
1641  * > 2 - the Tx timer unit at gigabit speed
1642  *
1643  * The unit of the timer depends on both the speed and the setting of CPlusCmd
1644  * (0xe0) bit 1 and bit 0.
1645  *
1646  * For 8169
1647  * bit[1:0] \ speed        1000M           100M            10M
1648  * 0 0                     320ns           2.56us          40.96us
1649  * 0 1                     2.56us          20.48us         327.7us
1650  * 1 0                     5.12us          40.96us         655.4us
1651  * 1 1                     10.24us         81.92us         1.31ms
1652  *
1653  * For the other
1654  * bit[1:0] \ speed        1000M           100M            10M
1655  * 0 0                     5us             2.56us          40.96us
1656  * 0 1                     40us            20.48us         327.7us
1657  * 1 0                     80us            40.96us         655.4us
1658  * 1 1                     160us           81.92us         1.31ms
1659  */
1660
1661 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
1662 struct rtl_coalesce_info {
1663         u32 speed;
1664         u32 scale_nsecs[4];
1665 };
1666
1667 /* produce array with base delay *1, *8, *8*2, *8*2*2 */
1668 #define COALESCE_DELAY(d) { (d), 8 * (d), 16 * (d), 32 * (d) }
1669
1670 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1671         { SPEED_1000,   COALESCE_DELAY(320) },
1672         { SPEED_100,    COALESCE_DELAY(2560) },
1673         { SPEED_10,     COALESCE_DELAY(40960) },
1674         { 0 },
1675 };
1676
1677 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1678         { SPEED_1000,   COALESCE_DELAY(5000) },
1679         { SPEED_100,    COALESCE_DELAY(2560) },
1680         { SPEED_10,     COALESCE_DELAY(40960) },
1681         { 0 },
1682 };
1683 #undef COALESCE_DELAY
1684
1685 /* get rx/tx scale vector corresponding to current speed */
1686 static const struct rtl_coalesce_info *
1687 rtl_coalesce_info(struct rtl8169_private *tp)
1688 {
1689         const struct rtl_coalesce_info *ci;
1690
1691         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1692                 ci = rtl_coalesce_info_8169;
1693         else
1694                 ci = rtl_coalesce_info_8168_8136;
1695
1696         /* if speed is unknown assume highest one */
1697         if (tp->phydev->speed == SPEED_UNKNOWN)
1698                 return ci;
1699
1700         for (; ci->speed; ci++) {
1701                 if (tp->phydev->speed == ci->speed)
1702                         return ci;
1703         }
1704
1705         return ERR_PTR(-ELNRNG);
1706 }
1707
1708 static int rtl_get_coalesce(struct net_device *dev,
1709                             struct ethtool_coalesce *ec,
1710                             struct kernel_ethtool_coalesce *kernel_coal,
1711                             struct netlink_ext_ack *extack)
1712 {
1713         struct rtl8169_private *tp = netdev_priv(dev);
1714         const struct rtl_coalesce_info *ci;
1715         u32 scale, c_us, c_fr;
1716         u16 intrmit;
1717
1718         if (rtl_is_8125(tp))
1719                 return -EOPNOTSUPP;
1720
1721         memset(ec, 0, sizeof(*ec));
1722
1723         /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1724         ci = rtl_coalesce_info(tp);
1725         if (IS_ERR(ci))
1726                 return PTR_ERR(ci);
1727
1728         scale = ci->scale_nsecs[tp->cp_cmd & INTT_MASK];
1729
1730         intrmit = RTL_R16(tp, IntrMitigate);
1731
1732         c_us = FIELD_GET(RTL_COALESCE_TX_USECS, intrmit);
1733         ec->tx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000);
1734
1735         c_fr = FIELD_GET(RTL_COALESCE_TX_FRAMES, intrmit);
1736         /* ethtool_coalesce states usecs and max_frames must not both be 0 */
1737         ec->tx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1;
1738
1739         c_us = FIELD_GET(RTL_COALESCE_RX_USECS, intrmit);
1740         ec->rx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000);
1741
1742         c_fr = FIELD_GET(RTL_COALESCE_RX_FRAMES, intrmit);
1743         ec->rx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1;
1744
1745         return 0;
1746 }
1747
1748 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, usec) */
1749 static int rtl_coalesce_choose_scale(struct rtl8169_private *tp, u32 usec,
1750                                      u16 *cp01)
1751 {
1752         const struct rtl_coalesce_info *ci;
1753         u16 i;
1754
1755         ci = rtl_coalesce_info(tp);
1756         if (IS_ERR(ci))
1757                 return PTR_ERR(ci);
1758
1759         for (i = 0; i < 4; i++) {
1760                 if (usec <= ci->scale_nsecs[i] * RTL_COALESCE_T_MAX / 1000U) {
1761                         *cp01 = i;
1762                         return ci->scale_nsecs[i];
1763                 }
1764         }
1765
1766         return -ERANGE;
1767 }
1768
1769 static int rtl_set_coalesce(struct net_device *dev,
1770                             struct ethtool_coalesce *ec,
1771                             struct kernel_ethtool_coalesce *kernel_coal,
1772                             struct netlink_ext_ack *extack)
1773 {
1774         struct rtl8169_private *tp = netdev_priv(dev);
1775         u32 tx_fr = ec->tx_max_coalesced_frames;
1776         u32 rx_fr = ec->rx_max_coalesced_frames;
1777         u32 coal_usec_max, units;
1778         u16 w = 0, cp01 = 0;
1779         int scale;
1780
1781         if (rtl_is_8125(tp))
1782                 return -EOPNOTSUPP;
1783
1784         if (rx_fr > RTL_COALESCE_FRAME_MAX || tx_fr > RTL_COALESCE_FRAME_MAX)
1785                 return -ERANGE;
1786
1787         coal_usec_max = max(ec->rx_coalesce_usecs, ec->tx_coalesce_usecs);
1788         scale = rtl_coalesce_choose_scale(tp, coal_usec_max, &cp01);
1789         if (scale < 0)
1790                 return scale;
1791
1792         /* Accept max_frames=1 we returned in rtl_get_coalesce. Accept it
1793          * not only when usecs=0 because of e.g. the following scenario:
1794          *
1795          * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
1796          * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
1797          * - then user does `ethtool -C eth0 rx-usecs 100`
1798          *
1799          * Since ethtool sends to kernel whole ethtool_coalesce settings,
1800          * if we want to ignore rx_frames then it has to be set to 0.
1801          */
1802         if (rx_fr == 1)
1803                 rx_fr = 0;
1804         if (tx_fr == 1)
1805                 tx_fr = 0;
1806
1807         /* HW requires time limit to be set if frame limit is set */
1808         if ((tx_fr && !ec->tx_coalesce_usecs) ||
1809             (rx_fr && !ec->rx_coalesce_usecs))
1810                 return -EINVAL;
1811
1812         w |= FIELD_PREP(RTL_COALESCE_TX_FRAMES, DIV_ROUND_UP(tx_fr, 4));
1813         w |= FIELD_PREP(RTL_COALESCE_RX_FRAMES, DIV_ROUND_UP(rx_fr, 4));
1814
1815         units = DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000U, scale);
1816         w |= FIELD_PREP(RTL_COALESCE_TX_USECS, units);
1817         units = DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000U, scale);
1818         w |= FIELD_PREP(RTL_COALESCE_RX_USECS, units);
1819
1820         RTL_W16(tp, IntrMitigate, w);
1821
1822         /* Meaning of PktCntrDisable bit changed from RTL8168e-vl */
1823         if (rtl_is_8168evl_up(tp)) {
1824                 if (!rx_fr && !tx_fr)
1825                         /* disable packet counter */
1826                         tp->cp_cmd |= PktCntrDisable;
1827                 else
1828                         tp->cp_cmd &= ~PktCntrDisable;
1829         }
1830
1831         tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
1832         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1833         rtl_pci_commit(tp);
1834
1835         return 0;
1836 }
1837
1838 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data)
1839 {
1840         struct rtl8169_private *tp = netdev_priv(dev);
1841
1842         if (!rtl_supports_eee(tp))
1843                 return -EOPNOTSUPP;
1844
1845         return phy_ethtool_get_eee(tp->phydev, data);
1846 }
1847
1848 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data)
1849 {
1850         struct rtl8169_private *tp = netdev_priv(dev);
1851         int ret;
1852
1853         if (!rtl_supports_eee(tp))
1854                 return -EOPNOTSUPP;
1855
1856         ret = phy_ethtool_set_eee(tp->phydev, data);
1857
1858         if (!ret)
1859                 tp->eee_adv = phy_read_mmd(dev->phydev, MDIO_MMD_AN,
1860                                            MDIO_AN_EEE_ADV);
1861         return ret;
1862 }
1863
1864 static void rtl8169_get_ringparam(struct net_device *dev,
1865                                   struct ethtool_ringparam *data,
1866                                   struct kernel_ethtool_ringparam *kernel_data,
1867                                   struct netlink_ext_ack *extack)
1868 {
1869         data->rx_max_pending = NUM_RX_DESC;
1870         data->rx_pending = NUM_RX_DESC;
1871         data->tx_max_pending = NUM_TX_DESC;
1872         data->tx_pending = NUM_TX_DESC;
1873 }
1874
1875 static void rtl8169_get_pauseparam(struct net_device *dev,
1876                                    struct ethtool_pauseparam *data)
1877 {
1878         struct rtl8169_private *tp = netdev_priv(dev);
1879         bool tx_pause, rx_pause;
1880
1881         phy_get_pause(tp->phydev, &tx_pause, &rx_pause);
1882
1883         data->autoneg = tp->phydev->autoneg;
1884         data->tx_pause = tx_pause ? 1 : 0;
1885         data->rx_pause = rx_pause ? 1 : 0;
1886 }
1887
1888 static int rtl8169_set_pauseparam(struct net_device *dev,
1889                                   struct ethtool_pauseparam *data)
1890 {
1891         struct rtl8169_private *tp = netdev_priv(dev);
1892
1893         if (dev->mtu > ETH_DATA_LEN)
1894                 return -EOPNOTSUPP;
1895
1896         phy_set_asym_pause(tp->phydev, data->rx_pause, data->tx_pause);
1897
1898         return 0;
1899 }
1900
1901 static const struct ethtool_ops rtl8169_ethtool_ops = {
1902         .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
1903                                      ETHTOOL_COALESCE_MAX_FRAMES,
1904         .get_drvinfo            = rtl8169_get_drvinfo,
1905         .get_regs_len           = rtl8169_get_regs_len,
1906         .get_link               = ethtool_op_get_link,
1907         .get_coalesce           = rtl_get_coalesce,
1908         .set_coalesce           = rtl_set_coalesce,
1909         .get_regs               = rtl8169_get_regs,
1910         .get_wol                = rtl8169_get_wol,
1911         .set_wol                = rtl8169_set_wol,
1912         .get_strings            = rtl8169_get_strings,
1913         .get_sset_count         = rtl8169_get_sset_count,
1914         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
1915         .get_ts_info            = ethtool_op_get_ts_info,
1916         .nway_reset             = phy_ethtool_nway_reset,
1917         .get_eee                = rtl8169_get_eee,
1918         .set_eee                = rtl8169_set_eee,
1919         .get_link_ksettings     = phy_ethtool_get_link_ksettings,
1920         .set_link_ksettings     = phy_ethtool_set_link_ksettings,
1921         .get_ringparam          = rtl8169_get_ringparam,
1922         .get_pauseparam         = rtl8169_get_pauseparam,
1923         .set_pauseparam         = rtl8169_set_pauseparam,
1924 };
1925
1926 static void rtl_enable_eee(struct rtl8169_private *tp)
1927 {
1928         struct phy_device *phydev = tp->phydev;
1929         int adv;
1930
1931         /* respect EEE advertisement the user may have set */
1932         if (tp->eee_adv >= 0)
1933                 adv = tp->eee_adv;
1934         else
1935                 adv = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
1936
1937         if (adv >= 0)
1938                 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, adv);
1939 }
1940
1941 static enum mac_version rtl8169_get_mac_version(u16 xid, bool gmii)
1942 {
1943         /*
1944          * The driver currently handles the 8168Bf and the 8168Be identically
1945          * but they can be identified more specifically through the test below
1946          * if needed:
1947          *
1948          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1949          *
1950          * Same thing for the 8101Eb and the 8101Ec:
1951          *
1952          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1953          */
1954         static const struct rtl_mac_info {
1955                 u16 mask;
1956                 u16 val;
1957                 enum mac_version ver;
1958         } mac_info[] = {
1959                 /* 8125B family. */
1960                 { 0x7cf, 0x641, RTL_GIGA_MAC_VER_63 },
1961
1962                 /* 8125A family. */
1963                 { 0x7cf, 0x609, RTL_GIGA_MAC_VER_61 },
1964                 /* It seems only XID 609 made it to the mass market.
1965                  * { 0x7cf, 0x608,      RTL_GIGA_MAC_VER_60 },
1966                  * { 0x7c8, 0x608,      RTL_GIGA_MAC_VER_61 },
1967                  */
1968
1969                 /* RTL8117 */
1970                 { 0x7cf, 0x54b, RTL_GIGA_MAC_VER_53 },
1971                 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52 },
1972
1973                 /* 8168EP family. */
1974                 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 },
1975                 /* It seems this chip version never made it to
1976                  * the wild. Let's disable detection.
1977                  * { 0x7cf, 0x501,      RTL_GIGA_MAC_VER_50 },
1978                  * { 0x7cf, 0x500,      RTL_GIGA_MAC_VER_49 },
1979                  */
1980
1981                 /* 8168H family. */
1982                 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 },
1983                 /* It seems this chip version never made it to
1984                  * the wild. Let's disable detection.
1985                  * { 0x7cf, 0x540,      RTL_GIGA_MAC_VER_45 },
1986                  */
1987
1988                 /* 8168G family. */
1989                 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 },
1990                 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 },
1991                 /* It seems this chip version never made it to
1992                  * the wild. Let's disable detection.
1993                  * { 0x7cf, 0x4c1,      RTL_GIGA_MAC_VER_41 },
1994                  */
1995                 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 },
1996
1997                 /* 8168F family. */
1998                 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 },
1999                 /* It seems this chip version never made it to
2000                  * the wild. Let's disable detection.
2001                  * { 0x7cf, 0x481,      RTL_GIGA_MAC_VER_36 },
2002                  */
2003                 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 },
2004
2005                 /* 8168E family. */
2006                 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 },
2007                 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 },
2008                 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 },
2009
2010                 /* 8168D family. */
2011                 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 },
2012                 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 },
2013
2014                 /* 8168DP family. */
2015                 /* It seems this early RTL8168dp version never made it to
2016                  * the wild. Support has been removed.
2017                  * { 0x7cf, 0x288,      RTL_GIGA_MAC_VER_27 },
2018                  */
2019                 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 },
2020                 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 },
2021
2022                 /* 8168C family. */
2023                 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 },
2024                 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 },
2025                 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 },
2026                 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 },
2027                 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 },
2028                 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 },
2029                 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 },
2030
2031                 /* 8168B family. */
2032                 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 },
2033                 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 },
2034
2035                 /* 8101 family. */
2036                 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 },
2037                 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 },
2038                 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 },
2039                 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 },
2040                 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 },
2041                 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 },
2042                 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 },
2043                 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 },
2044                 { 0x7cf, 0x240, RTL_GIGA_MAC_VER_14 },
2045                 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 },
2046                 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 },
2047                 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_10 },
2048
2049                 /* 8110 family. */
2050                 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 },
2051                 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 },
2052                 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 },
2053                 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 },
2054                 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 },
2055
2056                 /* Catch-all */
2057                 { 0x000, 0x000, RTL_GIGA_MAC_NONE   }
2058         };
2059         const struct rtl_mac_info *p = mac_info;
2060         enum mac_version ver;
2061
2062         while ((xid & p->mask) != p->val)
2063                 p++;
2064         ver = p->ver;
2065
2066         if (ver != RTL_GIGA_MAC_NONE && !gmii) {
2067                 if (ver == RTL_GIGA_MAC_VER_42)
2068                         ver = RTL_GIGA_MAC_VER_43;
2069                 else if (ver == RTL_GIGA_MAC_VER_46)
2070                         ver = RTL_GIGA_MAC_VER_48;
2071         }
2072
2073         return ver;
2074 }
2075
2076 static void rtl_release_firmware(struct rtl8169_private *tp)
2077 {
2078         if (tp->rtl_fw) {
2079                 rtl_fw_release_firmware(tp->rtl_fw);
2080                 kfree(tp->rtl_fw);
2081                 tp->rtl_fw = NULL;
2082         }
2083 }
2084
2085 void r8169_apply_firmware(struct rtl8169_private *tp)
2086 {
2087         int val;
2088
2089         /* TODO: release firmware if rtl_fw_write_firmware signals failure. */
2090         if (tp->rtl_fw) {
2091                 rtl_fw_write_firmware(tp, tp->rtl_fw);
2092                 /* At least one firmware doesn't reset tp->ocp_base. */
2093                 tp->ocp_base = OCP_STD_PHY_BASE;
2094
2095                 /* PHY soft reset may still be in progress */
2096                 phy_read_poll_timeout(tp->phydev, MII_BMCR, val,
2097                                       !(val & BMCR_RESET),
2098                                       50000, 600000, true);
2099         }
2100 }
2101
2102 static void rtl8168_config_eee_mac(struct rtl8169_private *tp)
2103 {
2104         /* Adjust EEE LED frequency */
2105         if (tp->mac_version != RTL_GIGA_MAC_VER_38)
2106                 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
2107
2108         rtl_eri_set_bits(tp, 0x1b0, 0x0003);
2109 }
2110
2111 static void rtl8125a_config_eee_mac(struct rtl8169_private *tp)
2112 {
2113         r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0));
2114         r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1));
2115 }
2116
2117 static void rtl8125_set_eee_txidle_timer(struct rtl8169_private *tp)
2118 {
2119         RTL_W16(tp, EEE_TXIDLE_TIMER_8125, tp->dev->mtu + ETH_HLEN + 0x20);
2120 }
2121
2122 static void rtl8125b_config_eee_mac(struct rtl8169_private *tp)
2123 {
2124         rtl8125_set_eee_txidle_timer(tp);
2125         r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0));
2126 }
2127
2128 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, const u8 *addr)
2129 {
2130         rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, get_unaligned_le32(addr));
2131         rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, get_unaligned_le16(addr + 4));
2132         rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, get_unaligned_le16(addr) << 16);
2133         rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, get_unaligned_le32(addr + 2));
2134 }
2135
2136 u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp)
2137 {
2138         u16 data1, data2, ioffset;
2139
2140         r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
2141         data1 = r8168_mac_ocp_read(tp, 0xdd02);
2142         data2 = r8168_mac_ocp_read(tp, 0xdd00);
2143
2144         ioffset = (data2 >> 1) & 0x7ff8;
2145         ioffset |= data2 & 0x0007;
2146         if (data1 & BIT(7))
2147                 ioffset |= BIT(15);
2148
2149         return ioffset;
2150 }
2151
2152 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
2153 {
2154         set_bit(flag, tp->wk.flags);
2155         schedule_work(&tp->wk.work);
2156 }
2157
2158 static void rtl8169_init_phy(struct rtl8169_private *tp)
2159 {
2160         r8169_hw_phy_config(tp, tp->phydev, tp->mac_version);
2161
2162         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2163                 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2164                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
2165                 /* set undocumented MAC Reg C+CR Offset 0x82h */
2166                 RTL_W8(tp, 0x82, 0x01);
2167         }
2168
2169         if (tp->mac_version == RTL_GIGA_MAC_VER_05 &&
2170             tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE &&
2171             tp->pci_dev->subsystem_device == 0xe000)
2172                 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b);
2173
2174         /* We may have called phy_speed_down before */
2175         phy_speed_up(tp->phydev);
2176
2177         if (rtl_supports_eee(tp))
2178                 rtl_enable_eee(tp);
2179
2180         genphy_soft_reset(tp->phydev);
2181 }
2182
2183 static void rtl_rar_set(struct rtl8169_private *tp, const u8 *addr)
2184 {
2185         rtl_unlock_config_regs(tp);
2186
2187         RTL_W32(tp, MAC4, get_unaligned_le16(addr + 4));
2188         rtl_pci_commit(tp);
2189
2190         RTL_W32(tp, MAC0, get_unaligned_le32(addr));
2191         rtl_pci_commit(tp);
2192
2193         if (tp->mac_version == RTL_GIGA_MAC_VER_34)
2194                 rtl_rar_exgmac_set(tp, addr);
2195
2196         rtl_lock_config_regs(tp);
2197 }
2198
2199 static int rtl_set_mac_address(struct net_device *dev, void *p)
2200 {
2201         struct rtl8169_private *tp = netdev_priv(dev);
2202         int ret;
2203
2204         ret = eth_mac_addr(dev, p);
2205         if (ret)
2206                 return ret;
2207
2208         rtl_rar_set(tp, dev->dev_addr);
2209
2210         return 0;
2211 }
2212
2213 static void rtl_init_rxcfg(struct rtl8169_private *tp)
2214 {
2215         switch (tp->mac_version) {
2216         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
2217         case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
2218                 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
2219                 break;
2220         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
2221         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
2222         case RTL_GIGA_MAC_VER_38:
2223                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
2224                 break;
2225         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53:
2226                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
2227                 break;
2228         case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63:
2229                 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST);
2230                 break;
2231         default:
2232                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
2233                 break;
2234         }
2235 }
2236
2237 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2238 {
2239         tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
2240 }
2241
2242 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
2243 {
2244         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2245         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
2246 }
2247
2248 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
2249 {
2250         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2251         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
2252 }
2253
2254 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
2255 {
2256         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2257 }
2258
2259 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
2260 {
2261         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2262 }
2263
2264 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
2265 {
2266         RTL_W8(tp, MaxTxPacketSize, 0x24);
2267         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2268         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
2269 }
2270
2271 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
2272 {
2273         RTL_W8(tp, MaxTxPacketSize, 0x3f);
2274         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2275         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
2276 }
2277
2278 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
2279 {
2280         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
2281 }
2282
2283 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
2284 {
2285         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
2286 }
2287
2288 static void rtl_jumbo_config(struct rtl8169_private *tp)
2289 {
2290         bool jumbo = tp->dev->mtu > ETH_DATA_LEN;
2291         int readrq = 4096;
2292
2293         rtl_unlock_config_regs(tp);
2294         switch (tp->mac_version) {
2295         case RTL_GIGA_MAC_VER_17:
2296                 if (jumbo) {
2297                         readrq = 512;
2298                         r8168b_1_hw_jumbo_enable(tp);
2299                 } else {
2300                         r8168b_1_hw_jumbo_disable(tp);
2301                 }
2302                 break;
2303         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26:
2304                 if (jumbo) {
2305                         readrq = 512;
2306                         r8168c_hw_jumbo_enable(tp);
2307                 } else {
2308                         r8168c_hw_jumbo_disable(tp);
2309                 }
2310                 break;
2311         case RTL_GIGA_MAC_VER_28:
2312                 if (jumbo)
2313                         r8168dp_hw_jumbo_enable(tp);
2314                 else
2315                         r8168dp_hw_jumbo_disable(tp);
2316                 break;
2317         case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33:
2318                 if (jumbo)
2319                         r8168e_hw_jumbo_enable(tp);
2320                 else
2321                         r8168e_hw_jumbo_disable(tp);
2322                 break;
2323         default:
2324                 break;
2325         }
2326         rtl_lock_config_regs(tp);
2327
2328         if (pci_is_pcie(tp->pci_dev) && tp->supports_gmii)
2329                 pcie_set_readrq(tp->pci_dev, readrq);
2330
2331         /* Chip doesn't support pause in jumbo mode */
2332         if (jumbo) {
2333                 linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT,
2334                                    tp->phydev->advertising);
2335                 linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
2336                                    tp->phydev->advertising);
2337                 phy_start_aneg(tp->phydev);
2338         }
2339 }
2340
2341 DECLARE_RTL_COND(rtl_chipcmd_cond)
2342 {
2343         return RTL_R8(tp, ChipCmd) & CmdReset;
2344 }
2345
2346 static void rtl_hw_reset(struct rtl8169_private *tp)
2347 {
2348         RTL_W8(tp, ChipCmd, CmdReset);
2349
2350         rtl_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
2351 }
2352
2353 static void rtl_request_firmware(struct rtl8169_private *tp)
2354 {
2355         struct rtl_fw *rtl_fw;
2356
2357         /* firmware loaded already or no firmware available */
2358         if (tp->rtl_fw || !tp->fw_name)
2359                 return;
2360
2361         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
2362         if (!rtl_fw)
2363                 return;
2364
2365         rtl_fw->phy_write = rtl_writephy;
2366         rtl_fw->phy_read = rtl_readphy;
2367         rtl_fw->mac_mcu_write = mac_mcu_write;
2368         rtl_fw->mac_mcu_read = mac_mcu_read;
2369         rtl_fw->fw_name = tp->fw_name;
2370         rtl_fw->dev = tp_to_dev(tp);
2371
2372         if (rtl_fw_request_firmware(rtl_fw))
2373                 kfree(rtl_fw);
2374         else
2375                 tp->rtl_fw = rtl_fw;
2376 }
2377
2378 static void rtl_rx_close(struct rtl8169_private *tp)
2379 {
2380         RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
2381 }
2382
2383 DECLARE_RTL_COND(rtl_npq_cond)
2384 {
2385         return RTL_R8(tp, TxPoll) & NPQ;
2386 }
2387
2388 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
2389 {
2390         return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
2391 }
2392
2393 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
2394 {
2395         return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
2396 }
2397
2398 DECLARE_RTL_COND(rtl_rxtx_empty_cond_2)
2399 {
2400         /* IntrMitigate has new functionality on RTL8125 */
2401         return (RTL_R16(tp, IntrMitigate) & 0x0103) == 0x0103;
2402 }
2403
2404 static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp)
2405 {
2406         switch (tp->mac_version) {
2407         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53:
2408                 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42);
2409                 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2410                 break;
2411         case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_61:
2412                 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2413                 break;
2414         case RTL_GIGA_MAC_VER_63:
2415                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
2416                 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2417                 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond_2, 100, 42);
2418                 break;
2419         default:
2420                 break;
2421         }
2422 }
2423
2424 static void rtl_disable_rxdvgate(struct rtl8169_private *tp)
2425 {
2426         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
2427 }
2428
2429 static void rtl_enable_rxdvgate(struct rtl8169_private *tp)
2430 {
2431         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
2432         fsleep(2000);
2433         rtl_wait_txrx_fifo_empty(tp);
2434 }
2435
2436 static void rtl_wol_enable_rx(struct rtl8169_private *tp)
2437 {
2438         if (tp->mac_version >= RTL_GIGA_MAC_VER_25)
2439                 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
2440                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
2441
2442         if (tp->mac_version >= RTL_GIGA_MAC_VER_40)
2443                 rtl_disable_rxdvgate(tp);
2444 }
2445
2446 static void rtl_prepare_power_down(struct rtl8169_private *tp)
2447 {
2448         if (tp->dash_type != RTL_DASH_NONE)
2449                 return;
2450
2451         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
2452             tp->mac_version == RTL_GIGA_MAC_VER_33)
2453                 rtl_ephy_write(tp, 0x19, 0xff64);
2454
2455         if (device_may_wakeup(tp_to_dev(tp))) {
2456                 phy_speed_down(tp->phydev, false);
2457                 rtl_wol_enable_rx(tp);
2458         }
2459 }
2460
2461 static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
2462 {
2463         u32 val = TX_DMA_BURST << TxDMAShift |
2464                   InterFrameGap << TxInterFrameGapShift;
2465
2466         if (rtl_is_8168evl_up(tp))
2467                 val |= TXCFG_AUTO_FIFO;
2468
2469         RTL_W32(tp, TxConfig, val);
2470 }
2471
2472 static void rtl_set_rx_max_size(struct rtl8169_private *tp)
2473 {
2474         /* Low hurts. Let's disable the filtering. */
2475         RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
2476 }
2477
2478 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
2479 {
2480         /*
2481          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
2482          * register to be written before TxDescAddrLow to work.
2483          * Switching from MMIO to I/O access fixes the issue as well.
2484          */
2485         RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
2486         RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
2487         RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
2488         RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
2489 }
2490
2491 static void rtl8169_set_magic_reg(struct rtl8169_private *tp)
2492 {
2493         u32 val;
2494
2495         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
2496                 val = 0x000fff00;
2497         else if (tp->mac_version == RTL_GIGA_MAC_VER_06)
2498                 val = 0x00ffff00;
2499         else
2500                 return;
2501
2502         if (RTL_R8(tp, Config2) & PCI_Clock_66MHz)
2503                 val |= 0xff;
2504
2505         RTL_W32(tp, 0x7c, val);
2506 }
2507
2508 static void rtl_set_rx_mode(struct net_device *dev)
2509 {
2510         u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast;
2511         /* Multicast hash filter */
2512         u32 mc_filter[2] = { 0xffffffff, 0xffffffff };
2513         struct rtl8169_private *tp = netdev_priv(dev);
2514         u32 tmp;
2515
2516         if (dev->flags & IFF_PROMISC) {
2517                 rx_mode |= AcceptAllPhys;
2518         } else if (netdev_mc_count(dev) > MC_FILTER_LIMIT ||
2519                    dev->flags & IFF_ALLMULTI ||
2520                    tp->mac_version == RTL_GIGA_MAC_VER_35) {
2521                 /* accept all multicasts */
2522         } else if (netdev_mc_empty(dev)) {
2523                 rx_mode &= ~AcceptMulticast;
2524         } else {
2525                 struct netdev_hw_addr *ha;
2526
2527                 mc_filter[1] = mc_filter[0] = 0;
2528                 netdev_for_each_mc_addr(ha, dev) {
2529                         u32 bit_nr = eth_hw_addr_crc(ha) >> 26;
2530                         mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31);
2531                 }
2532
2533                 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
2534                         tmp = mc_filter[0];
2535                         mc_filter[0] = swab32(mc_filter[1]);
2536                         mc_filter[1] = swab32(tmp);
2537                 }
2538         }
2539
2540         RTL_W32(tp, MAR0 + 4, mc_filter[1]);
2541         RTL_W32(tp, MAR0 + 0, mc_filter[0]);
2542
2543         tmp = RTL_R32(tp, RxConfig);
2544         RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode);
2545 }
2546
2547 DECLARE_RTL_COND(rtl_csiar_cond)
2548 {
2549         return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
2550 }
2551
2552 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
2553 {
2554         u32 func = PCI_FUNC(tp->pci_dev->devfn);
2555
2556         RTL_W32(tp, CSIDR, value);
2557         RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
2558                 CSIAR_BYTE_ENABLE | func << 16);
2559
2560         rtl_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
2561 }
2562
2563 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
2564 {
2565         u32 func = PCI_FUNC(tp->pci_dev->devfn);
2566
2567         RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
2568                 CSIAR_BYTE_ENABLE);
2569
2570         return rtl_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
2571                 RTL_R32(tp, CSIDR) : ~0;
2572 }
2573
2574 static void rtl_set_aspm_entry_latency(struct rtl8169_private *tp, u8 val)
2575 {
2576         struct pci_dev *pdev = tp->pci_dev;
2577         u32 csi;
2578
2579         /* According to Realtek the value at config space address 0x070f
2580          * controls the L0s/L1 entrance latency. We try standard ECAM access
2581          * first and if it fails fall back to CSI.
2582          * bit 0..2: L0: 0 = 1us, 1 = 2us .. 6 = 7us, 7 = 7us (no typo)
2583          * bit 3..5: L1: 0 = 1us, 1 = 2us .. 6 = 64us, 7 = 64us
2584          */
2585         if (pdev->cfg_size > 0x070f &&
2586             pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
2587                 return;
2588
2589         netdev_notice_once(tp->dev,
2590                 "No native access to PCI extended config space, falling back to CSI\n");
2591         csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
2592         rtl_csi_write(tp, 0x070c, csi | val << 24);
2593 }
2594
2595 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
2596 {
2597         /* L0 7us, L1 16us */
2598         rtl_set_aspm_entry_latency(tp, 0x27);
2599 }
2600
2601 struct ephy_info {
2602         unsigned int offset;
2603         u16 mask;
2604         u16 bits;
2605 };
2606
2607 static void __rtl_ephy_init(struct rtl8169_private *tp,
2608                             const struct ephy_info *e, int len)
2609 {
2610         u16 w;
2611
2612         while (len-- > 0) {
2613                 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
2614                 rtl_ephy_write(tp, e->offset, w);
2615                 e++;
2616         }
2617 }
2618
2619 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a))
2620
2621 static void rtl_disable_clock_request(struct rtl8169_private *tp)
2622 {
2623         pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
2624                                    PCI_EXP_LNKCTL_CLKREQ_EN);
2625 }
2626
2627 static void rtl_enable_clock_request(struct rtl8169_private *tp)
2628 {
2629         pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
2630                                  PCI_EXP_LNKCTL_CLKREQ_EN);
2631 }
2632
2633 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp)
2634 {
2635         /* work around an issue when PCI reset occurs during L2/L3 state */
2636         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23);
2637 }
2638
2639 static void rtl_enable_exit_l1(struct rtl8169_private *tp)
2640 {
2641         /* Bits control which events trigger ASPM L1 exit:
2642          * Bit 12: rxdv
2643          * Bit 11: ltr_msg
2644          * Bit 10: txdma_poll
2645          * Bit  9: xadm
2646          * Bit  8: pktavi
2647          * Bit  7: txpla
2648          */
2649         switch (tp->mac_version) {
2650         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
2651                 rtl_eri_set_bits(tp, 0xd4, 0x1f00);
2652                 break;
2653         case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_38:
2654                 rtl_eri_set_bits(tp, 0xd4, 0x0c00);
2655                 break;
2656         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
2657                 r8168_mac_ocp_modify(tp, 0xc0ac, 0, 0x1f80);
2658                 break;
2659         default:
2660                 break;
2661         }
2662 }
2663
2664 static void rtl_disable_exit_l1(struct rtl8169_private *tp)
2665 {
2666         switch (tp->mac_version) {
2667         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
2668                 rtl_eri_clear_bits(tp, 0xd4, 0x1f00);
2669                 break;
2670         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
2671                 r8168_mac_ocp_modify(tp, 0xc0ac, 0x1f80, 0);
2672                 break;
2673         default:
2674                 break;
2675         }
2676 }
2677
2678 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
2679 {
2680         /* Don't enable ASPM in the chip if OS can't control ASPM */
2681         if (enable && tp->aspm_manageable) {
2682                 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);
2683                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);
2684
2685                 switch (tp->mac_version) {
2686                 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48:
2687                 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63:
2688                         /* reset ephy tx/rx disable timer */
2689                         r8168_mac_ocp_modify(tp, 0xe094, 0xff00, 0);
2690                         /* chip can trigger L1.2 */
2691                         r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, BIT(2));
2692                         break;
2693                 default:
2694                         break;
2695                 }
2696         } else {
2697                 switch (tp->mac_version) {
2698                 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48:
2699                 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63:
2700                         r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, 0);
2701                         break;
2702                 default:
2703                         break;
2704                 }
2705
2706                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
2707                 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
2708         }
2709
2710         udelay(10);
2711 }
2712
2713 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat,
2714                               u16 tx_stat, u16 rx_dyn, u16 tx_dyn)
2715 {
2716         /* Usage of dynamic vs. static FIFO is controlled by bit
2717          * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known.
2718          */
2719         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn);
2720         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn);
2721 }
2722
2723 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp,
2724                                           u8 low, u8 high)
2725 {
2726         /* FIFO thresholds for pause flow control */
2727         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low);
2728         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high);
2729 }
2730
2731 static void rtl_hw_start_8168b(struct rtl8169_private *tp)
2732 {
2733         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2734 }
2735
2736 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
2737 {
2738         RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
2739
2740         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2741
2742         rtl_disable_clock_request(tp);
2743 }
2744
2745 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
2746 {
2747         static const struct ephy_info e_info_8168cp[] = {
2748                 { 0x01, 0,      0x0001 },
2749                 { 0x02, 0x0800, 0x1000 },
2750                 { 0x03, 0,      0x0042 },
2751                 { 0x06, 0x0080, 0x0000 },
2752                 { 0x07, 0,      0x2000 }
2753         };
2754
2755         rtl_set_def_aspm_entry_latency(tp);
2756
2757         rtl_ephy_init(tp, e_info_8168cp);
2758
2759         __rtl_hw_start_8168cp(tp);
2760 }
2761
2762 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
2763 {
2764         rtl_set_def_aspm_entry_latency(tp);
2765
2766         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2767 }
2768
2769 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
2770 {
2771         rtl_set_def_aspm_entry_latency(tp);
2772
2773         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2774
2775         /* Magic. */
2776         RTL_W8(tp, DBG_REG, 0x20);
2777 }
2778
2779 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
2780 {
2781         static const struct ephy_info e_info_8168c_1[] = {
2782                 { 0x02, 0x0800, 0x1000 },
2783                 { 0x03, 0,      0x0002 },
2784                 { 0x06, 0x0080, 0x0000 }
2785         };
2786
2787         rtl_set_def_aspm_entry_latency(tp);
2788
2789         RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
2790
2791         rtl_ephy_init(tp, e_info_8168c_1);
2792
2793         __rtl_hw_start_8168cp(tp);
2794 }
2795
2796 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
2797 {
2798         static const struct ephy_info e_info_8168c_2[] = {
2799                 { 0x01, 0,      0x0001 },
2800                 { 0x03, 0x0400, 0x0020 }
2801         };
2802
2803         rtl_set_def_aspm_entry_latency(tp);
2804
2805         rtl_ephy_init(tp, e_info_8168c_2);
2806
2807         __rtl_hw_start_8168cp(tp);
2808 }
2809
2810 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
2811 {
2812         rtl_set_def_aspm_entry_latency(tp);
2813
2814         __rtl_hw_start_8168cp(tp);
2815 }
2816
2817 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
2818 {
2819         rtl_set_def_aspm_entry_latency(tp);
2820
2821         rtl_disable_clock_request(tp);
2822 }
2823
2824 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
2825 {
2826         static const struct ephy_info e_info_8168d_4[] = {
2827                 { 0x0b, 0x0000, 0x0048 },
2828                 { 0x19, 0x0020, 0x0050 },
2829                 { 0x0c, 0x0100, 0x0020 },
2830                 { 0x10, 0x0004, 0x0000 },
2831         };
2832
2833         rtl_set_def_aspm_entry_latency(tp);
2834
2835         rtl_ephy_init(tp, e_info_8168d_4);
2836
2837         rtl_enable_clock_request(tp);
2838 }
2839
2840 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
2841 {
2842         static const struct ephy_info e_info_8168e_1[] = {
2843                 { 0x00, 0x0200, 0x0100 },
2844                 { 0x00, 0x0000, 0x0004 },
2845                 { 0x06, 0x0002, 0x0001 },
2846                 { 0x06, 0x0000, 0x0030 },
2847                 { 0x07, 0x0000, 0x2000 },
2848                 { 0x00, 0x0000, 0x0020 },
2849                 { 0x03, 0x5800, 0x2000 },
2850                 { 0x03, 0x0000, 0x0001 },
2851                 { 0x01, 0x0800, 0x1000 },
2852                 { 0x07, 0x0000, 0x4000 },
2853                 { 0x1e, 0x0000, 0x2000 },
2854                 { 0x19, 0xffff, 0xfe6c },
2855                 { 0x0a, 0x0000, 0x0040 }
2856         };
2857
2858         rtl_set_def_aspm_entry_latency(tp);
2859
2860         rtl_ephy_init(tp, e_info_8168e_1);
2861
2862         rtl_disable_clock_request(tp);
2863
2864         /* Reset tx FIFO pointer */
2865         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
2866         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
2867
2868         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
2869 }
2870
2871 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
2872 {
2873         static const struct ephy_info e_info_8168e_2[] = {
2874                 { 0x09, 0x0000, 0x0080 },
2875                 { 0x19, 0x0000, 0x0224 },
2876                 { 0x00, 0x0000, 0x0004 },
2877                 { 0x0c, 0x3df0, 0x0200 },
2878         };
2879
2880         rtl_set_def_aspm_entry_latency(tp);
2881
2882         rtl_ephy_init(tp, e_info_8168e_2);
2883
2884         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
2885         rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000);
2886         rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
2887         rtl_eri_set_bits(tp, 0x1d0, BIT(1));
2888         rtl_reset_packet_filter(tp);
2889         rtl_eri_set_bits(tp, 0x1b0, BIT(4));
2890         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
2891         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060);
2892
2893         rtl_disable_clock_request(tp);
2894
2895         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
2896
2897         rtl8168_config_eee_mac(tp);
2898
2899         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
2900         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
2901         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
2902
2903         rtl_hw_aspm_clkreq_enable(tp, true);
2904 }
2905
2906 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
2907 {
2908         rtl_set_def_aspm_entry_latency(tp);
2909
2910         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
2911         rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000);
2912         rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
2913         rtl_reset_packet_filter(tp);
2914         rtl_eri_set_bits(tp, 0x1b0, BIT(4));
2915         rtl_eri_set_bits(tp, 0x1d0, BIT(4) | BIT(1));
2916         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
2917         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060);
2918
2919         rtl_disable_clock_request(tp);
2920
2921         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
2922         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
2923         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
2924         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
2925
2926         rtl8168_config_eee_mac(tp);
2927 }
2928
2929 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
2930 {
2931         static const struct ephy_info e_info_8168f_1[] = {
2932                 { 0x06, 0x00c0, 0x0020 },
2933                 { 0x08, 0x0001, 0x0002 },
2934                 { 0x09, 0x0000, 0x0080 },
2935                 { 0x19, 0x0000, 0x0224 },
2936                 { 0x00, 0x0000, 0x0008 },
2937                 { 0x0c, 0x3df0, 0x0200 },
2938         };
2939
2940         rtl_hw_start_8168f(tp);
2941
2942         rtl_ephy_init(tp, e_info_8168f_1);
2943 }
2944
2945 static void rtl_hw_start_8411(struct rtl8169_private *tp)
2946 {
2947         static const struct ephy_info e_info_8168f_1[] = {
2948                 { 0x06, 0x00c0, 0x0020 },
2949                 { 0x0f, 0xffff, 0x5200 },
2950                 { 0x19, 0x0000, 0x0224 },
2951                 { 0x00, 0x0000, 0x0008 },
2952                 { 0x0c, 0x3df0, 0x0200 },
2953         };
2954
2955         rtl_hw_start_8168f(tp);
2956         rtl_pcie_state_l2l3_disable(tp);
2957
2958         rtl_ephy_init(tp, e_info_8168f_1);
2959 }
2960
2961 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
2962 {
2963         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
2964         rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
2965
2966         rtl_set_def_aspm_entry_latency(tp);
2967
2968         rtl_reset_packet_filter(tp);
2969         rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f);
2970
2971         rtl_disable_rxdvgate(tp);
2972
2973         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
2974         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
2975
2976         rtl8168_config_eee_mac(tp);
2977
2978         rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06);
2979         rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
2980
2981         rtl_pcie_state_l2l3_disable(tp);
2982 }
2983
2984 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
2985 {
2986         static const struct ephy_info e_info_8168g_1[] = {
2987                 { 0x00, 0x0008, 0x0000 },
2988                 { 0x0c, 0x3ff0, 0x0820 },
2989                 { 0x1e, 0x0000, 0x0001 },
2990                 { 0x19, 0x8000, 0x0000 }
2991         };
2992
2993         rtl_hw_start_8168g(tp);
2994
2995         /* disable aspm and clock request before access ephy */
2996         rtl_hw_aspm_clkreq_enable(tp, false);
2997         rtl_ephy_init(tp, e_info_8168g_1);
2998         rtl_hw_aspm_clkreq_enable(tp, true);
2999 }
3000
3001 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
3002 {
3003         static const struct ephy_info e_info_8168g_2[] = {
3004                 { 0x00, 0x0008, 0x0000 },
3005                 { 0x0c, 0x3ff0, 0x0820 },
3006                 { 0x19, 0xffff, 0x7c00 },
3007                 { 0x1e, 0xffff, 0x20eb },
3008                 { 0x0d, 0xffff, 0x1666 },
3009                 { 0x00, 0xffff, 0x10a3 },
3010                 { 0x06, 0xffff, 0xf050 },
3011                 { 0x04, 0x0000, 0x0010 },
3012                 { 0x1d, 0x4000, 0x0000 },
3013         };
3014
3015         rtl_hw_start_8168g(tp);
3016
3017         /* disable aspm and clock request before access ephy */
3018         rtl_hw_aspm_clkreq_enable(tp, false);
3019         rtl_ephy_init(tp, e_info_8168g_2);
3020 }
3021
3022 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
3023 {
3024         static const struct ephy_info e_info_8411_2[] = {
3025                 { 0x00, 0x0008, 0x0000 },
3026                 { 0x0c, 0x37d0, 0x0820 },
3027                 { 0x1e, 0x0000, 0x0001 },
3028                 { 0x19, 0x8021, 0x0000 },
3029                 { 0x1e, 0x0000, 0x2000 },
3030                 { 0x0d, 0x0100, 0x0200 },
3031                 { 0x00, 0x0000, 0x0080 },
3032                 { 0x06, 0x0000, 0x0010 },
3033                 { 0x04, 0x0000, 0x0010 },
3034                 { 0x1d, 0x0000, 0x4000 },
3035         };
3036
3037         rtl_hw_start_8168g(tp);
3038
3039         /* disable aspm and clock request before access ephy */
3040         rtl_hw_aspm_clkreq_enable(tp, false);
3041         rtl_ephy_init(tp, e_info_8411_2);
3042
3043         /* The following Realtek-provided magic fixes an issue with the RX unit
3044          * getting confused after the PHY having been powered-down.
3045          */
3046         r8168_mac_ocp_write(tp, 0xFC28, 0x0000);
3047         r8168_mac_ocp_write(tp, 0xFC2A, 0x0000);
3048         r8168_mac_ocp_write(tp, 0xFC2C, 0x0000);
3049         r8168_mac_ocp_write(tp, 0xFC2E, 0x0000);
3050         r8168_mac_ocp_write(tp, 0xFC30, 0x0000);
3051         r8168_mac_ocp_write(tp, 0xFC32, 0x0000);
3052         r8168_mac_ocp_write(tp, 0xFC34, 0x0000);
3053         r8168_mac_ocp_write(tp, 0xFC36, 0x0000);
3054         mdelay(3);
3055         r8168_mac_ocp_write(tp, 0xFC26, 0x0000);
3056
3057         r8168_mac_ocp_write(tp, 0xF800, 0xE008);
3058         r8168_mac_ocp_write(tp, 0xF802, 0xE00A);
3059         r8168_mac_ocp_write(tp, 0xF804, 0xE00C);
3060         r8168_mac_ocp_write(tp, 0xF806, 0xE00E);
3061         r8168_mac_ocp_write(tp, 0xF808, 0xE027);
3062         r8168_mac_ocp_write(tp, 0xF80A, 0xE04F);
3063         r8168_mac_ocp_write(tp, 0xF80C, 0xE05E);
3064         r8168_mac_ocp_write(tp, 0xF80E, 0xE065);
3065         r8168_mac_ocp_write(tp, 0xF810, 0xC602);
3066         r8168_mac_ocp_write(tp, 0xF812, 0xBE00);
3067         r8168_mac_ocp_write(tp, 0xF814, 0x0000);
3068         r8168_mac_ocp_write(tp, 0xF816, 0xC502);
3069         r8168_mac_ocp_write(tp, 0xF818, 0xBD00);
3070         r8168_mac_ocp_write(tp, 0xF81A, 0x074C);
3071         r8168_mac_ocp_write(tp, 0xF81C, 0xC302);
3072         r8168_mac_ocp_write(tp, 0xF81E, 0xBB00);
3073         r8168_mac_ocp_write(tp, 0xF820, 0x080A);
3074         r8168_mac_ocp_write(tp, 0xF822, 0x6420);
3075         r8168_mac_ocp_write(tp, 0xF824, 0x48C2);
3076         r8168_mac_ocp_write(tp, 0xF826, 0x8C20);
3077         r8168_mac_ocp_write(tp, 0xF828, 0xC516);
3078         r8168_mac_ocp_write(tp, 0xF82A, 0x64A4);
3079         r8168_mac_ocp_write(tp, 0xF82C, 0x49C0);
3080         r8168_mac_ocp_write(tp, 0xF82E, 0xF009);
3081         r8168_mac_ocp_write(tp, 0xF830, 0x74A2);
3082         r8168_mac_ocp_write(tp, 0xF832, 0x8CA5);
3083         r8168_mac_ocp_write(tp, 0xF834, 0x74A0);
3084         r8168_mac_ocp_write(tp, 0xF836, 0xC50E);
3085         r8168_mac_ocp_write(tp, 0xF838, 0x9CA2);
3086         r8168_mac_ocp_write(tp, 0xF83A, 0x1C11);
3087         r8168_mac_ocp_write(tp, 0xF83C, 0x9CA0);
3088         r8168_mac_ocp_write(tp, 0xF83E, 0xE006);
3089         r8168_mac_ocp_write(tp, 0xF840, 0x74F8);
3090         r8168_mac_ocp_write(tp, 0xF842, 0x48C4);
3091         r8168_mac_ocp_write(tp, 0xF844, 0x8CF8);
3092         r8168_mac_ocp_write(tp, 0xF846, 0xC404);
3093         r8168_mac_ocp_write(tp, 0xF848, 0xBC00);
3094         r8168_mac_ocp_write(tp, 0xF84A, 0xC403);
3095         r8168_mac_ocp_write(tp, 0xF84C, 0xBC00);
3096         r8168_mac_ocp_write(tp, 0xF84E, 0x0BF2);
3097         r8168_mac_ocp_write(tp, 0xF850, 0x0C0A);
3098         r8168_mac_ocp_write(tp, 0xF852, 0xE434);
3099         r8168_mac_ocp_write(tp, 0xF854, 0xD3C0);
3100         r8168_mac_ocp_write(tp, 0xF856, 0x49D9);
3101         r8168_mac_ocp_write(tp, 0xF858, 0xF01F);
3102         r8168_mac_ocp_write(tp, 0xF85A, 0xC526);
3103         r8168_mac_ocp_write(tp, 0xF85C, 0x64A5);
3104         r8168_mac_ocp_write(tp, 0xF85E, 0x1400);
3105         r8168_mac_ocp_write(tp, 0xF860, 0xF007);
3106         r8168_mac_ocp_write(tp, 0xF862, 0x0C01);
3107         r8168_mac_ocp_write(tp, 0xF864, 0x8CA5);
3108         r8168_mac_ocp_write(tp, 0xF866, 0x1C15);
3109         r8168_mac_ocp_write(tp, 0xF868, 0xC51B);
3110         r8168_mac_ocp_write(tp, 0xF86A, 0x9CA0);
3111         r8168_mac_ocp_write(tp, 0xF86C, 0xE013);
3112         r8168_mac_ocp_write(tp, 0xF86E, 0xC519);
3113         r8168_mac_ocp_write(tp, 0xF870, 0x74A0);
3114         r8168_mac_ocp_write(tp, 0xF872, 0x48C4);
3115         r8168_mac_ocp_write(tp, 0xF874, 0x8CA0);
3116         r8168_mac_ocp_write(tp, 0xF876, 0xC516);
3117         r8168_mac_ocp_write(tp, 0xF878, 0x74A4);
3118         r8168_mac_ocp_write(tp, 0xF87A, 0x48C8);
3119         r8168_mac_ocp_write(tp, 0xF87C, 0x48CA);
3120         r8168_mac_ocp_write(tp, 0xF87E, 0x9CA4);
3121         r8168_mac_ocp_write(tp, 0xF880, 0xC512);
3122         r8168_mac_ocp_write(tp, 0xF882, 0x1B00);
3123         r8168_mac_ocp_write(tp, 0xF884, 0x9BA0);
3124         r8168_mac_ocp_write(tp, 0xF886, 0x1B1C);
3125         r8168_mac_ocp_write(tp, 0xF888, 0x483F);
3126         r8168_mac_ocp_write(tp, 0xF88A, 0x9BA2);
3127         r8168_mac_ocp_write(tp, 0xF88C, 0x1B04);
3128         r8168_mac_ocp_write(tp, 0xF88E, 0xC508);
3129         r8168_mac_ocp_write(tp, 0xF890, 0x9BA0);
3130         r8168_mac_ocp_write(tp, 0xF892, 0xC505);
3131         r8168_mac_ocp_write(tp, 0xF894, 0xBD00);
3132         r8168_mac_ocp_write(tp, 0xF896, 0xC502);
3133         r8168_mac_ocp_write(tp, 0xF898, 0xBD00);
3134         r8168_mac_ocp_write(tp, 0xF89A, 0x0300);
3135         r8168_mac_ocp_write(tp, 0xF89C, 0x051E);
3136         r8168_mac_ocp_write(tp, 0xF89E, 0xE434);
3137         r8168_mac_ocp_write(tp, 0xF8A0, 0xE018);
3138         r8168_mac_ocp_write(tp, 0xF8A2, 0xE092);
3139         r8168_mac_ocp_write(tp, 0xF8A4, 0xDE20);
3140         r8168_mac_ocp_write(tp, 0xF8A6, 0xD3C0);
3141         r8168_mac_ocp_write(tp, 0xF8A8, 0xC50F);
3142         r8168_mac_ocp_write(tp, 0xF8AA, 0x76A4);
3143         r8168_mac_ocp_write(tp, 0xF8AC, 0x49E3);
3144         r8168_mac_ocp_write(tp, 0xF8AE, 0xF007);
3145         r8168_mac_ocp_write(tp, 0xF8B0, 0x49C0);
3146         r8168_mac_ocp_write(tp, 0xF8B2, 0xF103);
3147         r8168_mac_ocp_write(tp, 0xF8B4, 0xC607);
3148         r8168_mac_ocp_write(tp, 0xF8B6, 0xBE00);
3149         r8168_mac_ocp_write(tp, 0xF8B8, 0xC606);
3150         r8168_mac_ocp_write(tp, 0xF8BA, 0xBE00);
3151         r8168_mac_ocp_write(tp, 0xF8BC, 0xC602);
3152         r8168_mac_ocp_write(tp, 0xF8BE, 0xBE00);
3153         r8168_mac_ocp_write(tp, 0xF8C0, 0x0C4C);
3154         r8168_mac_ocp_write(tp, 0xF8C2, 0x0C28);
3155         r8168_mac_ocp_write(tp, 0xF8C4, 0x0C2C);
3156         r8168_mac_ocp_write(tp, 0xF8C6, 0xDC00);
3157         r8168_mac_ocp_write(tp, 0xF8C8, 0xC707);
3158         r8168_mac_ocp_write(tp, 0xF8CA, 0x1D00);
3159         r8168_mac_ocp_write(tp, 0xF8CC, 0x8DE2);
3160         r8168_mac_ocp_write(tp, 0xF8CE, 0x48C1);
3161         r8168_mac_ocp_write(tp, 0xF8D0, 0xC502);
3162         r8168_mac_ocp_write(tp, 0xF8D2, 0xBD00);
3163         r8168_mac_ocp_write(tp, 0xF8D4, 0x00AA);
3164         r8168_mac_ocp_write(tp, 0xF8D6, 0xE0C0);
3165         r8168_mac_ocp_write(tp, 0xF8D8, 0xC502);
3166         r8168_mac_ocp_write(tp, 0xF8DA, 0xBD00);
3167         r8168_mac_ocp_write(tp, 0xF8DC, 0x0132);
3168
3169         r8168_mac_ocp_write(tp, 0xFC26, 0x8000);
3170
3171         r8168_mac_ocp_write(tp, 0xFC2A, 0x0743);
3172         r8168_mac_ocp_write(tp, 0xFC2C, 0x0801);
3173         r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9);
3174         r8168_mac_ocp_write(tp, 0xFC30, 0x02FD);
3175         r8168_mac_ocp_write(tp, 0xFC32, 0x0C25);
3176         r8168_mac_ocp_write(tp, 0xFC34, 0x00A9);
3177         r8168_mac_ocp_write(tp, 0xFC36, 0x012D);
3178
3179         rtl_hw_aspm_clkreq_enable(tp, true);
3180 }
3181
3182 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
3183 {
3184         static const struct ephy_info e_info_8168h_1[] = {
3185                 { 0x1e, 0x0800, 0x0001 },
3186                 { 0x1d, 0x0000, 0x0800 },
3187                 { 0x05, 0xffff, 0x2089 },
3188                 { 0x06, 0xffff, 0x5881 },
3189                 { 0x04, 0xffff, 0x854a },
3190                 { 0x01, 0xffff, 0x068b }
3191         };
3192         int rg_saw_cnt;
3193
3194         /* disable aspm and clock request before access ephy */
3195         rtl_hw_aspm_clkreq_enable(tp, false);
3196         rtl_ephy_init(tp, e_info_8168h_1);
3197
3198         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3199         rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
3200
3201         rtl_set_def_aspm_entry_latency(tp);
3202
3203         rtl_reset_packet_filter(tp);
3204
3205         rtl_eri_set_bits(tp, 0xdc, 0x001c);
3206
3207         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3208
3209         rtl_disable_rxdvgate(tp);
3210
3211         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3212         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3213
3214         rtl8168_config_eee_mac(tp);
3215
3216         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3217         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3218
3219         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3220
3221         rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
3222
3223         rtl_pcie_state_l2l3_disable(tp);
3224
3225         rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff;
3226         if (rg_saw_cnt > 0) {
3227                 u16 sw_cnt_1ms_ini;
3228
3229                 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
3230                 sw_cnt_1ms_ini &= 0x0fff;
3231                 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);
3232         }
3233
3234         r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);
3235         r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008);
3236         r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f);
3237         r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);
3238
3239         r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
3240         r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
3241         r8168_mac_ocp_write(tp, 0xc094, 0x0000);
3242         r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
3243
3244         rtl_hw_aspm_clkreq_enable(tp, true);
3245 }
3246
3247 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
3248 {
3249         rtl8168ep_stop_cmac(tp);
3250
3251         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3252         rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
3253
3254         rtl_set_def_aspm_entry_latency(tp);
3255
3256         rtl_reset_packet_filter(tp);
3257
3258         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3259
3260         rtl_disable_rxdvgate(tp);
3261
3262         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3263         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3264
3265         rtl8168_config_eee_mac(tp);
3266
3267         rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06);
3268
3269         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3270
3271         rtl_pcie_state_l2l3_disable(tp);
3272 }
3273
3274 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
3275 {
3276         static const struct ephy_info e_info_8168ep_3[] = {
3277                 { 0x00, 0x0000, 0x0080 },
3278                 { 0x0d, 0x0100, 0x0200 },
3279                 { 0x19, 0x8021, 0x0000 },
3280                 { 0x1e, 0x0000, 0x2000 },
3281         };
3282
3283         /* disable aspm and clock request before access ephy */
3284         rtl_hw_aspm_clkreq_enable(tp, false);
3285         rtl_ephy_init(tp, e_info_8168ep_3);
3286
3287         rtl_hw_start_8168ep(tp);
3288
3289         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3290         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3291
3292         r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271);
3293         r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
3294         r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);
3295
3296         rtl_hw_aspm_clkreq_enable(tp, true);
3297 }
3298
3299 static void rtl_hw_start_8117(struct rtl8169_private *tp)
3300 {
3301         static const struct ephy_info e_info_8117[] = {
3302                 { 0x19, 0x0040, 0x1100 },
3303                 { 0x59, 0x0040, 0x1100 },
3304         };
3305         int rg_saw_cnt;
3306
3307         rtl8168ep_stop_cmac(tp);
3308
3309         /* disable aspm and clock request before access ephy */
3310         rtl_hw_aspm_clkreq_enable(tp, false);
3311         rtl_ephy_init(tp, e_info_8117);
3312
3313         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3314         rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
3315
3316         rtl_set_def_aspm_entry_latency(tp);
3317
3318         rtl_reset_packet_filter(tp);
3319
3320         rtl_eri_set_bits(tp, 0xd4, 0x0010);
3321
3322         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3323
3324         rtl_disable_rxdvgate(tp);
3325
3326         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3327         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3328
3329         rtl8168_config_eee_mac(tp);
3330
3331         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3332         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3333
3334         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3335
3336         rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
3337
3338         rtl_pcie_state_l2l3_disable(tp);
3339
3340         rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff;
3341         if (rg_saw_cnt > 0) {
3342                 u16 sw_cnt_1ms_ini;
3343
3344                 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff;
3345                 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);
3346         }
3347
3348         r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);
3349         r8168_mac_ocp_write(tp, 0xea80, 0x0003);
3350         r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009);
3351         r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);
3352
3353         r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
3354         r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
3355         r8168_mac_ocp_write(tp, 0xc094, 0x0000);
3356         r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
3357
3358         /* firmware is for MAC only */
3359         r8169_apply_firmware(tp);
3360
3361         rtl_hw_aspm_clkreq_enable(tp, true);
3362 }
3363
3364 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
3365 {
3366         static const struct ephy_info e_info_8102e_1[] = {
3367                 { 0x01, 0, 0x6e65 },
3368                 { 0x02, 0, 0x091f },
3369                 { 0x03, 0, 0xc2f9 },
3370                 { 0x06, 0, 0xafb5 },
3371                 { 0x07, 0, 0x0e00 },
3372                 { 0x19, 0, 0xec80 },
3373                 { 0x01, 0, 0x2e65 },
3374                 { 0x01, 0, 0x6e65 }
3375         };
3376         u8 cfg1;
3377
3378         rtl_set_def_aspm_entry_latency(tp);
3379
3380         RTL_W8(tp, DBG_REG, FIX_NAK_1);
3381
3382         RTL_W8(tp, Config1,
3383                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
3384         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3385
3386         cfg1 = RTL_R8(tp, Config1);
3387         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
3388                 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
3389
3390         rtl_ephy_init(tp, e_info_8102e_1);
3391 }
3392
3393 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
3394 {
3395         rtl_set_def_aspm_entry_latency(tp);
3396
3397         RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
3398         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3399 }
3400
3401 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
3402 {
3403         rtl_hw_start_8102e_2(tp);
3404
3405         rtl_ephy_write(tp, 0x03, 0xc2f9);
3406 }
3407
3408 static void rtl_hw_start_8401(struct rtl8169_private *tp)
3409 {
3410         static const struct ephy_info e_info_8401[] = {
3411                 { 0x01, 0xffff, 0x6fe5 },
3412                 { 0x03, 0xffff, 0x0599 },
3413                 { 0x06, 0xffff, 0xaf25 },
3414                 { 0x07, 0xffff, 0x8e68 },
3415         };
3416
3417         rtl_ephy_init(tp, e_info_8401);
3418         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3419 }
3420
3421 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
3422 {
3423         static const struct ephy_info e_info_8105e_1[] = {
3424                 { 0x07, 0, 0x4000 },
3425                 { 0x19, 0, 0x0200 },
3426                 { 0x19, 0, 0x0020 },
3427                 { 0x1e, 0, 0x2000 },
3428                 { 0x03, 0, 0x0001 },
3429                 { 0x19, 0, 0x0100 },
3430                 { 0x19, 0, 0x0004 },
3431                 { 0x0a, 0, 0x0020 }
3432         };
3433
3434         /* Force LAN exit from ASPM if Rx/Tx are not idle */
3435         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3436
3437         /* Disable Early Tally Counter */
3438         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
3439
3440         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
3441         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
3442
3443         rtl_ephy_init(tp, e_info_8105e_1);
3444
3445         rtl_pcie_state_l2l3_disable(tp);
3446 }
3447
3448 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
3449 {
3450         rtl_hw_start_8105e_1(tp);
3451         rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
3452 }
3453
3454 static void rtl_hw_start_8402(struct rtl8169_private *tp)
3455 {
3456         static const struct ephy_info e_info_8402[] = {
3457                 { 0x19, 0xffff, 0xff64 },
3458                 { 0x1e, 0, 0x4000 }
3459         };
3460
3461         rtl_set_def_aspm_entry_latency(tp);
3462
3463         /* Force LAN exit from ASPM if Rx/Tx are not idle */
3464         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3465
3466         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
3467
3468         rtl_ephy_init(tp, e_info_8402);
3469
3470         rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06);
3471         rtl_reset_packet_filter(tp);
3472         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3473         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3474         rtl_w0w1_eri(tp, 0x0d4, 0x0e00, 0xff00);
3475
3476         /* disable EEE */
3477         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3478
3479         rtl_pcie_state_l2l3_disable(tp);
3480 }
3481
3482 static void rtl_hw_start_8106(struct rtl8169_private *tp)
3483 {
3484         rtl_hw_aspm_clkreq_enable(tp, false);
3485
3486         /* Force LAN exit from ASPM if Rx/Tx are not idle */
3487         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3488
3489         RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
3490         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
3491         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3492
3493         /* L0 7us, L1 32us - needed to avoid issues with link-up detection */
3494         rtl_set_aspm_entry_latency(tp, 0x2f);
3495
3496         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
3497
3498         /* disable EEE */
3499         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3500
3501         rtl_pcie_state_l2l3_disable(tp);
3502         rtl_hw_aspm_clkreq_enable(tp, true);
3503 }
3504
3505 DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond)
3506 {
3507         return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13);
3508 }
3509
3510 static void rtl_hw_start_8125_common(struct rtl8169_private *tp)
3511 {
3512         rtl_pcie_state_l2l3_disable(tp);
3513
3514         RTL_W16(tp, 0x382, 0x221b);
3515         RTL_W8(tp, 0x4500, 0);
3516         RTL_W16(tp, 0x4800, 0);
3517
3518         /* disable UPS */
3519         r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000);
3520
3521         RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10);
3522
3523         r8168_mac_ocp_write(tp, 0xc140, 0xffff);
3524         r8168_mac_ocp_write(tp, 0xc142, 0xffff);
3525
3526         r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9);
3527         r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
3528         r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);
3529
3530         /* disable new tx descriptor format */
3531         r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000);
3532
3533         if (tp->mac_version == RTL_GIGA_MAC_VER_63)
3534                 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200);
3535         else
3536                 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400);
3537
3538         if (tp->mac_version == RTL_GIGA_MAC_VER_63)
3539                 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0000);
3540         else
3541                 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020);
3542
3543         r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c);
3544         r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033);
3545         r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040);
3546         r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030);
3547         r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000);
3548         r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001);
3549         r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403);
3550         r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0068);
3551         r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f);
3552
3553         r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000);
3554         r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001);
3555         udelay(1);
3556         r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000);
3557         RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030);
3558
3559         r8168_mac_ocp_write(tp, 0xe098, 0xc302);
3560
3561         rtl_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10);
3562
3563         if (tp->mac_version == RTL_GIGA_MAC_VER_63)
3564                 rtl8125b_config_eee_mac(tp);
3565         else
3566                 rtl8125a_config_eee_mac(tp);
3567
3568         rtl_disable_rxdvgate(tp);
3569 }
3570
3571 static void rtl_hw_start_8125a_2(struct rtl8169_private *tp)
3572 {
3573         static const struct ephy_info e_info_8125a_2[] = {
3574                 { 0x04, 0xffff, 0xd000 },
3575                 { 0x0a, 0xffff, 0x8653 },
3576                 { 0x23, 0xffff, 0xab66 },
3577                 { 0x20, 0xffff, 0x9455 },
3578                 { 0x21, 0xffff, 0x99ff },
3579                 { 0x29, 0xffff, 0xfe04 },
3580
3581                 { 0x44, 0xffff, 0xd000 },
3582                 { 0x4a, 0xffff, 0x8653 },
3583                 { 0x63, 0xffff, 0xab66 },
3584                 { 0x60, 0xffff, 0x9455 },
3585                 { 0x61, 0xffff, 0x99ff },
3586                 { 0x69, 0xffff, 0xfe04 },
3587         };
3588
3589         rtl_set_def_aspm_entry_latency(tp);
3590
3591         /* disable aspm and clock request before access ephy */
3592         rtl_hw_aspm_clkreq_enable(tp, false);
3593         rtl_ephy_init(tp, e_info_8125a_2);
3594
3595         rtl_hw_start_8125_common(tp);
3596         rtl_hw_aspm_clkreq_enable(tp, true);
3597 }
3598
3599 static void rtl_hw_start_8125b(struct rtl8169_private *tp)
3600 {
3601         static const struct ephy_info e_info_8125b[] = {
3602                 { 0x0b, 0xffff, 0xa908 },
3603                 { 0x1e, 0xffff, 0x20eb },
3604                 { 0x4b, 0xffff, 0xa908 },
3605                 { 0x5e, 0xffff, 0x20eb },
3606                 { 0x22, 0x0030, 0x0020 },
3607                 { 0x62, 0x0030, 0x0020 },
3608         };
3609
3610         rtl_set_def_aspm_entry_latency(tp);
3611         rtl_hw_aspm_clkreq_enable(tp, false);
3612
3613         rtl_ephy_init(tp, e_info_8125b);
3614         rtl_hw_start_8125_common(tp);
3615
3616         rtl_hw_aspm_clkreq_enable(tp, true);
3617 }
3618
3619 static void rtl_hw_config(struct rtl8169_private *tp)
3620 {
3621         static const rtl_generic_fct hw_configs[] = {
3622                 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1,
3623                 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3,
3624                 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2,
3625                 [RTL_GIGA_MAC_VER_10] = NULL,
3626                 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168b,
3627                 [RTL_GIGA_MAC_VER_14] = rtl_hw_start_8401,
3628                 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b,
3629                 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1,
3630                 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1,
3631                 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2,
3632                 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_2,
3633                 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4,
3634                 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2,
3635                 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3,
3636                 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d,
3637                 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d,
3638                 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4,
3639                 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1,
3640                 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2,
3641                 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168d,
3642                 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1,
3643                 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1,
3644                 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2,
3645                 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1,
3646                 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1,
3647                 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402,
3648                 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411,
3649                 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106,
3650                 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1,
3651                 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2,
3652                 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2,
3653                 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2,
3654                 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1,
3655                 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1,
3656                 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3,
3657                 [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117,
3658                 [RTL_GIGA_MAC_VER_53] = rtl_hw_start_8117,
3659                 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2,
3660                 [RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b,
3661         };
3662
3663         if (hw_configs[tp->mac_version])
3664                 hw_configs[tp->mac_version](tp);
3665 }
3666
3667 static void rtl_hw_start_8125(struct rtl8169_private *tp)
3668 {
3669         int i;
3670
3671         /* disable interrupt coalescing */
3672         for (i = 0xa00; i < 0xb00; i += 4)
3673                 RTL_W32(tp, i, 0);
3674
3675         rtl_hw_config(tp);
3676 }
3677
3678 static void rtl_hw_start_8168(struct rtl8169_private *tp)
3679 {
3680         if (rtl_is_8168evl_up(tp))
3681                 RTL_W8(tp, MaxTxPacketSize, EarlySize);
3682         else
3683                 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
3684
3685         rtl_hw_config(tp);
3686
3687         /* disable interrupt coalescing */
3688         RTL_W16(tp, IntrMitigate, 0x0000);
3689 }
3690
3691 static void rtl_hw_start_8169(struct rtl8169_private *tp)
3692 {
3693         RTL_W8(tp, EarlyTxThres, NoEarlyTx);
3694
3695         tp->cp_cmd |= PCIMulRW;
3696
3697         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3698             tp->mac_version == RTL_GIGA_MAC_VER_03)
3699                 tp->cp_cmd |= EnAnaPLL;
3700
3701         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
3702
3703         rtl8169_set_magic_reg(tp);
3704
3705         /* disable interrupt coalescing */
3706         RTL_W16(tp, IntrMitigate, 0x0000);
3707 }
3708
3709 static void rtl_hw_start(struct  rtl8169_private *tp)
3710 {
3711         rtl_unlock_config_regs(tp);
3712
3713         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
3714
3715         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3716                 rtl_hw_start_8169(tp);
3717         else if (rtl_is_8125(tp))
3718                 rtl_hw_start_8125(tp);
3719         else
3720                 rtl_hw_start_8168(tp);
3721
3722         rtl_enable_exit_l1(tp);
3723         rtl_set_rx_max_size(tp);
3724         rtl_set_rx_tx_desc_registers(tp);
3725         rtl_lock_config_regs(tp);
3726
3727         rtl_jumbo_config(tp);
3728
3729         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3730         rtl_pci_commit(tp);
3731
3732         RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
3733         rtl_init_rxcfg(tp);
3734         rtl_set_tx_config_registers(tp);
3735         rtl_set_rx_config_features(tp, tp->dev->features);
3736         rtl_set_rx_mode(tp->dev);
3737         rtl_irq_enable(tp);
3738 }
3739
3740 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
3741 {
3742         struct rtl8169_private *tp = netdev_priv(dev);
3743
3744         dev->mtu = new_mtu;
3745         netdev_update_features(dev);
3746         rtl_jumbo_config(tp);
3747
3748         switch (tp->mac_version) {
3749         case RTL_GIGA_MAC_VER_61:
3750         case RTL_GIGA_MAC_VER_63:
3751                 rtl8125_set_eee_txidle_timer(tp);
3752                 break;
3753         default:
3754                 break;
3755         }
3756
3757         return 0;
3758 }
3759
3760 static void rtl8169_mark_to_asic(struct RxDesc *desc)
3761 {
3762         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
3763
3764         desc->opts2 = 0;
3765         /* Force memory writes to complete before releasing descriptor */
3766         dma_wmb();
3767         WRITE_ONCE(desc->opts1, cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE));
3768 }
3769
3770 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
3771                                           struct RxDesc *desc)
3772 {
3773         struct device *d = tp_to_dev(tp);
3774         int node = dev_to_node(d);
3775         dma_addr_t mapping;
3776         struct page *data;
3777
3778         data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE));
3779         if (!data)
3780                 return NULL;
3781
3782         mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
3783         if (unlikely(dma_mapping_error(d, mapping))) {
3784                 netdev_err(tp->dev, "Failed to map RX DMA!\n");
3785                 __free_pages(data, get_order(R8169_RX_BUF_SIZE));
3786                 return NULL;
3787         }
3788
3789         desc->addr = cpu_to_le64(mapping);
3790         rtl8169_mark_to_asic(desc);
3791
3792         return data;
3793 }
3794
3795 static void rtl8169_rx_clear(struct rtl8169_private *tp)
3796 {
3797         int i;
3798
3799         for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) {
3800                 dma_unmap_page(tp_to_dev(tp),
3801                                le64_to_cpu(tp->RxDescArray[i].addr),
3802                                R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
3803                 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE));
3804                 tp->Rx_databuff[i] = NULL;
3805                 tp->RxDescArray[i].addr = 0;
3806                 tp->RxDescArray[i].opts1 = 0;
3807         }
3808 }
3809
3810 static int rtl8169_rx_fill(struct rtl8169_private *tp)
3811 {
3812         int i;
3813
3814         for (i = 0; i < NUM_RX_DESC; i++) {
3815                 struct page *data;
3816
3817                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
3818                 if (!data) {
3819                         rtl8169_rx_clear(tp);
3820                         return -ENOMEM;
3821                 }
3822                 tp->Rx_databuff[i] = data;
3823         }
3824
3825         /* mark as last descriptor in the ring */
3826         tp->RxDescArray[NUM_RX_DESC - 1].opts1 |= cpu_to_le32(RingEnd);
3827
3828         return 0;
3829 }
3830
3831 static int rtl8169_init_ring(struct rtl8169_private *tp)
3832 {
3833         rtl8169_init_ring_indexes(tp);
3834
3835         memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
3836         memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
3837
3838         return rtl8169_rx_fill(tp);
3839 }
3840
3841 static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int entry)
3842 {
3843         struct ring_info *tx_skb = tp->tx_skb + entry;
3844         struct TxDesc *desc = tp->TxDescArray + entry;
3845
3846         dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), tx_skb->len,
3847                          DMA_TO_DEVICE);
3848         memset(desc, 0, sizeof(*desc));
3849         memset(tx_skb, 0, sizeof(*tx_skb));
3850 }
3851
3852 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
3853                                    unsigned int n)
3854 {
3855         unsigned int i;
3856
3857         for (i = 0; i < n; i++) {
3858                 unsigned int entry = (start + i) % NUM_TX_DESC;
3859                 struct ring_info *tx_skb = tp->tx_skb + entry;
3860                 unsigned int len = tx_skb->len;
3861
3862                 if (len) {
3863                         struct sk_buff *skb = tx_skb->skb;
3864
3865                         rtl8169_unmap_tx_skb(tp, entry);
3866                         if (skb)
3867                                 dev_consume_skb_any(skb);
3868                 }
3869         }
3870 }
3871
3872 static void rtl8169_tx_clear(struct rtl8169_private *tp)
3873 {
3874         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
3875         netdev_reset_queue(tp->dev);
3876 }
3877
3878 static void rtl8169_cleanup(struct rtl8169_private *tp)
3879 {
3880         napi_disable(&tp->napi);
3881
3882         /* Give a racing hard_start_xmit a few cycles to complete. */
3883         synchronize_net();
3884
3885         /* Disable interrupts */
3886         rtl8169_irq_mask_and_ack(tp);
3887
3888         rtl_rx_close(tp);
3889
3890         switch (tp->mac_version) {
3891         case RTL_GIGA_MAC_VER_28:
3892         case RTL_GIGA_MAC_VER_31:
3893                 rtl_loop_wait_low(tp, &rtl_npq_cond, 20, 2000);
3894                 break;
3895         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
3896                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
3897                 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
3898                 break;
3899         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
3900                 rtl_enable_rxdvgate(tp);
3901                 fsleep(2000);
3902                 break;
3903         default:
3904                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
3905                 fsleep(100);
3906                 break;
3907         }
3908
3909         rtl_hw_reset(tp);
3910
3911         rtl8169_tx_clear(tp);
3912         rtl8169_init_ring_indexes(tp);
3913 }
3914
3915 static void rtl_reset_work(struct rtl8169_private *tp)
3916 {
3917         int i;
3918
3919         netif_stop_queue(tp->dev);
3920
3921         rtl8169_cleanup(tp);
3922
3923         for (i = 0; i < NUM_RX_DESC; i++)
3924                 rtl8169_mark_to_asic(tp->RxDescArray + i);
3925
3926         napi_enable(&tp->napi);
3927         rtl_hw_start(tp);
3928 }
3929
3930 static void rtl8169_tx_timeout(struct net_device *dev, unsigned int txqueue)
3931 {
3932         struct rtl8169_private *tp = netdev_priv(dev);
3933
3934         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
3935 }
3936
3937 static int rtl8169_tx_map(struct rtl8169_private *tp, const u32 *opts, u32 len,
3938                           void *addr, unsigned int entry, bool desc_own)
3939 {
3940         struct TxDesc *txd = tp->TxDescArray + entry;
3941         struct device *d = tp_to_dev(tp);
3942         dma_addr_t mapping;
3943         u32 opts1;
3944         int ret;
3945
3946         mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
3947         ret = dma_mapping_error(d, mapping);
3948         if (unlikely(ret)) {
3949                 if (net_ratelimit())
3950                         netdev_err(tp->dev, "Failed to map TX data!\n");
3951                 return ret;
3952         }
3953
3954         txd->addr = cpu_to_le64(mapping);
3955         txd->opts2 = cpu_to_le32(opts[1]);
3956
3957         opts1 = opts[0] | len;
3958         if (entry == NUM_TX_DESC - 1)
3959                 opts1 |= RingEnd;
3960         if (desc_own)
3961                 opts1 |= DescOwn;
3962         txd->opts1 = cpu_to_le32(opts1);
3963
3964         tp->tx_skb[entry].len = len;
3965
3966         return 0;
3967 }
3968
3969 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
3970                               const u32 *opts, unsigned int entry)
3971 {
3972         struct skb_shared_info *info = skb_shinfo(skb);
3973         unsigned int cur_frag;
3974
3975         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
3976                 const skb_frag_t *frag = info->frags + cur_frag;
3977                 void *addr = skb_frag_address(frag);
3978                 u32 len = skb_frag_size(frag);
3979
3980                 entry = (entry + 1) % NUM_TX_DESC;
3981
3982                 if (unlikely(rtl8169_tx_map(tp, opts, len, addr, entry, true)))
3983                         goto err_out;
3984         }
3985
3986         return 0;
3987
3988 err_out:
3989         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
3990         return -EIO;
3991 }
3992
3993 static bool rtl_skb_is_udp(struct sk_buff *skb)
3994 {
3995         int no = skb_network_offset(skb);
3996         struct ipv6hdr *i6h, _i6h;
3997         struct iphdr *ih, _ih;
3998
3999         switch (vlan_get_protocol(skb)) {
4000         case htons(ETH_P_IP):
4001                 ih = skb_header_pointer(skb, no, sizeof(_ih), &_ih);
4002                 return ih && ih->protocol == IPPROTO_UDP;
4003         case htons(ETH_P_IPV6):
4004                 i6h = skb_header_pointer(skb, no, sizeof(_i6h), &_i6h);
4005                 return i6h && i6h->nexthdr == IPPROTO_UDP;
4006         default:
4007                 return false;
4008         }
4009 }
4010
4011 #define RTL_MIN_PATCH_LEN       47
4012
4013 /* see rtl8125_get_patch_pad_len() in r8125 vendor driver */
4014 static unsigned int rtl8125_quirk_udp_padto(struct rtl8169_private *tp,
4015                                             struct sk_buff *skb)
4016 {
4017         unsigned int padto = 0, len = skb->len;
4018
4019         if (rtl_is_8125(tp) && len < 128 + RTL_MIN_PATCH_LEN &&
4020             rtl_skb_is_udp(skb) && skb_transport_header_was_set(skb)) {
4021                 unsigned int trans_data_len = skb_tail_pointer(skb) -
4022                                               skb_transport_header(skb);
4023
4024                 if (trans_data_len >= offsetof(struct udphdr, len) &&
4025                     trans_data_len < RTL_MIN_PATCH_LEN) {
4026                         u16 dest = ntohs(udp_hdr(skb)->dest);
4027
4028                         /* dest is a standard PTP port */
4029                         if (dest == 319 || dest == 320)
4030                                 padto = len + RTL_MIN_PATCH_LEN - trans_data_len;
4031                 }
4032
4033                 if (trans_data_len < sizeof(struct udphdr))
4034                         padto = max_t(unsigned int, padto,
4035                                       len + sizeof(struct udphdr) - trans_data_len);
4036         }
4037
4038         return padto;
4039 }
4040
4041 static unsigned int rtl_quirk_packet_padto(struct rtl8169_private *tp,
4042                                            struct sk_buff *skb)
4043 {
4044         unsigned int padto;
4045
4046         padto = rtl8125_quirk_udp_padto(tp, skb);
4047
4048         switch (tp->mac_version) {
4049         case RTL_GIGA_MAC_VER_34:
4050         case RTL_GIGA_MAC_VER_61:
4051         case RTL_GIGA_MAC_VER_63:
4052                 padto = max_t(unsigned int, padto, ETH_ZLEN);
4053                 break;
4054         default:
4055                 break;
4056         }
4057
4058         return padto;
4059 }
4060
4061 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts)
4062 {
4063         u32 mss = skb_shinfo(skb)->gso_size;
4064
4065         if (mss) {
4066                 opts[0] |= TD_LSO;
4067                 opts[0] |= mss << TD0_MSS_SHIFT;
4068         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4069                 const struct iphdr *ip = ip_hdr(skb);
4070
4071                 if (ip->protocol == IPPROTO_TCP)
4072                         opts[0] |= TD0_IP_CS | TD0_TCP_CS;
4073                 else if (ip->protocol == IPPROTO_UDP)
4074                         opts[0] |= TD0_IP_CS | TD0_UDP_CS;
4075                 else
4076                         WARN_ON_ONCE(1);
4077         }
4078 }
4079
4080 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
4081                                 struct sk_buff *skb, u32 *opts)
4082 {
4083         struct skb_shared_info *shinfo = skb_shinfo(skb);
4084         u32 mss = shinfo->gso_size;
4085
4086         if (mss) {
4087                 if (shinfo->gso_type & SKB_GSO_TCPV4) {
4088                         opts[0] |= TD1_GTSENV4;
4089                 } else if (shinfo->gso_type & SKB_GSO_TCPV6) {
4090                         if (skb_cow_head(skb, 0))
4091                                 return false;
4092
4093                         tcp_v6_gso_csum_prep(skb);
4094                         opts[0] |= TD1_GTSENV6;
4095                 } else {
4096                         WARN_ON_ONCE(1);
4097                 }
4098
4099                 opts[0] |= skb_transport_offset(skb) << GTTCPHO_SHIFT;
4100                 opts[1] |= mss << TD1_MSS_SHIFT;
4101         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4102                 u8 ip_protocol;
4103
4104                 switch (vlan_get_protocol(skb)) {
4105                 case htons(ETH_P_IP):
4106                         opts[1] |= TD1_IPv4_CS;
4107                         ip_protocol = ip_hdr(skb)->protocol;
4108                         break;
4109
4110                 case htons(ETH_P_IPV6):
4111                         opts[1] |= TD1_IPv6_CS;
4112                         ip_protocol = ipv6_hdr(skb)->nexthdr;
4113                         break;
4114
4115                 default:
4116                         ip_protocol = IPPROTO_RAW;
4117                         break;
4118                 }
4119
4120                 if (ip_protocol == IPPROTO_TCP)
4121                         opts[1] |= TD1_TCP_CS;
4122                 else if (ip_protocol == IPPROTO_UDP)
4123                         opts[1] |= TD1_UDP_CS;
4124                 else
4125                         WARN_ON_ONCE(1);
4126
4127                 opts[1] |= skb_transport_offset(skb) << TCPHO_SHIFT;
4128         } else {
4129                 unsigned int padto = rtl_quirk_packet_padto(tp, skb);
4130
4131                 /* skb_padto would free the skb on error */
4132                 return !__skb_put_padto(skb, padto, false);
4133         }
4134
4135         return true;
4136 }
4137
4138 static bool rtl_tx_slots_avail(struct rtl8169_private *tp)
4139 {
4140         unsigned int slots_avail = READ_ONCE(tp->dirty_tx) + NUM_TX_DESC
4141                                         - READ_ONCE(tp->cur_tx);
4142
4143         /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
4144         return slots_avail > MAX_SKB_FRAGS;
4145 }
4146
4147 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */
4148 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
4149 {
4150         switch (tp->mac_version) {
4151         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
4152         case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
4153                 return false;
4154         default:
4155                 return true;
4156         }
4157 }
4158
4159 static void rtl8169_doorbell(struct rtl8169_private *tp)
4160 {
4161         if (rtl_is_8125(tp))
4162                 RTL_W16(tp, TxPoll_8125, BIT(0));
4163         else
4164                 RTL_W8(tp, TxPoll, NPQ);
4165 }
4166
4167 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4168                                       struct net_device *dev)
4169 {
4170         unsigned int frags = skb_shinfo(skb)->nr_frags;
4171         struct rtl8169_private *tp = netdev_priv(dev);
4172         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
4173         struct TxDesc *txd_first, *txd_last;
4174         bool stop_queue, door_bell;
4175         u32 opts[2];
4176
4177         if (unlikely(!rtl_tx_slots_avail(tp))) {
4178                 if (net_ratelimit())
4179                         netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
4180                 goto err_stop_0;
4181         }
4182
4183         opts[1] = rtl8169_tx_vlan_tag(skb);
4184         opts[0] = 0;
4185
4186         if (!rtl_chip_supports_csum_v2(tp))
4187                 rtl8169_tso_csum_v1(skb, opts);
4188         else if (!rtl8169_tso_csum_v2(tp, skb, opts))
4189                 goto err_dma_0;
4190
4191         if (unlikely(rtl8169_tx_map(tp, opts, skb_headlen(skb), skb->data,
4192                                     entry, false)))
4193                 goto err_dma_0;
4194
4195         txd_first = tp->TxDescArray + entry;
4196
4197         if (frags) {
4198                 if (rtl8169_xmit_frags(tp, skb, opts, entry))
4199                         goto err_dma_1;
4200                 entry = (entry + frags) % NUM_TX_DESC;
4201         }
4202
4203         txd_last = tp->TxDescArray + entry;
4204         txd_last->opts1 |= cpu_to_le32(LastFrag);
4205         tp->tx_skb[entry].skb = skb;
4206
4207         skb_tx_timestamp(skb);
4208
4209         /* Force memory writes to complete before releasing descriptor */
4210         dma_wmb();
4211
4212         door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more());
4213
4214         txd_first->opts1 |= cpu_to_le32(DescOwn | FirstFrag);
4215
4216         /* rtl_tx needs to see descriptor changes before updated tp->cur_tx */
4217         smp_wmb();
4218
4219         WRITE_ONCE(tp->cur_tx, tp->cur_tx + frags + 1);
4220
4221         stop_queue = !rtl_tx_slots_avail(tp);
4222         if (unlikely(stop_queue)) {
4223                 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
4224                  * not miss a ring update when it notices a stopped queue.
4225                  */
4226                 smp_wmb();
4227                 netif_stop_queue(dev);
4228                 /* Sync with rtl_tx:
4229                  * - publish queue status and cur_tx ring index (write barrier)
4230                  * - refresh dirty_tx ring index (read barrier).
4231                  * May the current thread have a pessimistic view of the ring
4232                  * status and forget to wake up queue, a racing rtl_tx thread
4233                  * can't.
4234                  */
4235                 smp_mb__after_atomic();
4236                 if (rtl_tx_slots_avail(tp))
4237                         netif_start_queue(dev);
4238                 door_bell = true;
4239         }
4240
4241         if (door_bell)
4242                 rtl8169_doorbell(tp);
4243
4244         return NETDEV_TX_OK;
4245
4246 err_dma_1:
4247         rtl8169_unmap_tx_skb(tp, entry);
4248 err_dma_0:
4249         dev_kfree_skb_any(skb);
4250         dev->stats.tx_dropped++;
4251         return NETDEV_TX_OK;
4252
4253 err_stop_0:
4254         netif_stop_queue(dev);
4255         dev->stats.tx_dropped++;
4256         return NETDEV_TX_BUSY;
4257 }
4258
4259 static unsigned int rtl_last_frag_len(struct sk_buff *skb)
4260 {
4261         struct skb_shared_info *info = skb_shinfo(skb);
4262         unsigned int nr_frags = info->nr_frags;
4263
4264         if (!nr_frags)
4265                 return UINT_MAX;
4266
4267         return skb_frag_size(info->frags + nr_frags - 1);
4268 }
4269
4270 /* Workaround for hw issues with TSO on RTL8168evl */
4271 static netdev_features_t rtl8168evl_fix_tso(struct sk_buff *skb,
4272                                             netdev_features_t features)
4273 {
4274         /* IPv4 header has options field */
4275         if (vlan_get_protocol(skb) == htons(ETH_P_IP) &&
4276             ip_hdrlen(skb) > sizeof(struct iphdr))
4277                 features &= ~NETIF_F_ALL_TSO;
4278
4279         /* IPv4 TCP header has options field */
4280         else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4 &&
4281                  tcp_hdrlen(skb) > sizeof(struct tcphdr))
4282                 features &= ~NETIF_F_ALL_TSO;
4283
4284         else if (rtl_last_frag_len(skb) <= 6)
4285                 features &= ~NETIF_F_ALL_TSO;
4286
4287         return features;
4288 }
4289
4290 static netdev_features_t rtl8169_features_check(struct sk_buff *skb,
4291                                                 struct net_device *dev,
4292                                                 netdev_features_t features)
4293 {
4294         struct rtl8169_private *tp = netdev_priv(dev);
4295
4296         if (skb_is_gso(skb)) {
4297                 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4298                         features = rtl8168evl_fix_tso(skb, features);
4299
4300                 if (skb_transport_offset(skb) > GTTCPHO_MAX &&
4301                     rtl_chip_supports_csum_v2(tp))
4302                         features &= ~NETIF_F_ALL_TSO;
4303         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4304                 /* work around hw bug on some chip versions */
4305                 if (skb->len < ETH_ZLEN)
4306                         features &= ~NETIF_F_CSUM_MASK;
4307
4308                 if (rtl_quirk_packet_padto(tp, skb))
4309                         features &= ~NETIF_F_CSUM_MASK;
4310
4311                 if (skb_transport_offset(skb) > TCPHO_MAX &&
4312                     rtl_chip_supports_csum_v2(tp))
4313                         features &= ~NETIF_F_CSUM_MASK;
4314         }
4315
4316         return vlan_features_check(skb, features);
4317 }
4318
4319 static void rtl8169_pcierr_interrupt(struct net_device *dev)
4320 {
4321         struct rtl8169_private *tp = netdev_priv(dev);
4322         struct pci_dev *pdev = tp->pci_dev;
4323         int pci_status_errs;
4324         u16 pci_cmd;
4325
4326         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4327
4328         pci_status_errs = pci_status_get_and_clear_errors(pdev);
4329
4330         if (net_ratelimit())
4331                 netdev_err(dev, "PCI error (cmd = 0x%04x, status_errs = 0x%04x)\n",
4332                            pci_cmd, pci_status_errs);
4333
4334         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
4335 }
4336
4337 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp,
4338                    int budget)
4339 {
4340         unsigned int dirty_tx, bytes_compl = 0, pkts_compl = 0;
4341         struct sk_buff *skb;
4342
4343         dirty_tx = tp->dirty_tx;
4344
4345         while (READ_ONCE(tp->cur_tx) != dirty_tx) {
4346                 unsigned int entry = dirty_tx % NUM_TX_DESC;
4347                 u32 status;
4348
4349                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
4350                 if (status & DescOwn)
4351                         break;
4352
4353                 skb = tp->tx_skb[entry].skb;
4354                 rtl8169_unmap_tx_skb(tp, entry);
4355
4356                 if (skb) {
4357                         pkts_compl++;
4358                         bytes_compl += skb->len;
4359                         napi_consume_skb(skb, budget);
4360                 }
4361                 dirty_tx++;
4362         }
4363
4364         if (tp->dirty_tx != dirty_tx) {
4365                 netdev_completed_queue(dev, pkts_compl, bytes_compl);
4366                 dev_sw_netstats_tx_add(dev, pkts_compl, bytes_compl);
4367
4368                 /* Sync with rtl8169_start_xmit:
4369                  * - publish dirty_tx ring index (write barrier)
4370                  * - refresh cur_tx ring index and queue status (read barrier)
4371                  * May the current thread miss the stopped queue condition,
4372                  * a racing xmit thread can only have a right view of the
4373                  * ring status.
4374                  */
4375                 smp_store_mb(tp->dirty_tx, dirty_tx);
4376                 if (netif_queue_stopped(dev) && rtl_tx_slots_avail(tp))
4377                         netif_wake_queue(dev);
4378                 /*
4379                  * 8168 hack: TxPoll requests are lost when the Tx packets are
4380                  * too close. Let's kick an extra TxPoll request when a burst
4381                  * of start_xmit activity is detected (if it is not detected,
4382                  * it is slow enough). -- FR
4383                  * If skb is NULL then we come here again once a tx irq is
4384                  * triggered after the last fragment is marked transmitted.
4385                  */
4386                 if (tp->cur_tx != dirty_tx && skb)
4387                         rtl8169_doorbell(tp);
4388         }
4389 }
4390
4391 static inline int rtl8169_fragmented_frame(u32 status)
4392 {
4393         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4394 }
4395
4396 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
4397 {
4398         u32 status = opts1 & (RxProtoMask | RxCSFailMask);
4399
4400         if (status == RxProtoTCP || status == RxProtoUDP)
4401                 skb->ip_summed = CHECKSUM_UNNECESSARY;
4402         else
4403                 skb_checksum_none_assert(skb);
4404 }
4405
4406 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, int budget)
4407 {
4408         struct device *d = tp_to_dev(tp);
4409         int count;
4410
4411         for (count = 0; count < budget; count++, tp->cur_rx++) {
4412                 unsigned int pkt_size, entry = tp->cur_rx % NUM_RX_DESC;
4413                 struct RxDesc *desc = tp->RxDescArray + entry;
4414                 struct sk_buff *skb;
4415                 const void *rx_buf;
4416                 dma_addr_t addr;
4417                 u32 status;
4418
4419                 status = le32_to_cpu(desc->opts1);
4420                 if (status & DescOwn)
4421                         break;
4422
4423                 /* This barrier is needed to keep us from reading
4424                  * any other fields out of the Rx descriptor until
4425                  * we know the status of DescOwn
4426                  */
4427                 dma_rmb();
4428
4429                 if (unlikely(status & RxRES)) {
4430                         if (net_ratelimit())
4431                                 netdev_warn(dev, "Rx ERROR. status = %08x\n",
4432                                             status);
4433                         dev->stats.rx_errors++;
4434                         if (status & (RxRWT | RxRUNT))
4435                                 dev->stats.rx_length_errors++;
4436                         if (status & RxCRC)
4437                                 dev->stats.rx_crc_errors++;
4438
4439                         if (!(dev->features & NETIF_F_RXALL))
4440                                 goto release_descriptor;
4441                         else if (status & RxRWT || !(status & (RxRUNT | RxCRC)))
4442                                 goto release_descriptor;
4443                 }
4444
4445                 pkt_size = status & GENMASK(13, 0);
4446                 if (likely(!(dev->features & NETIF_F_RXFCS)))
4447                         pkt_size -= ETH_FCS_LEN;
4448
4449                 /* The driver does not support incoming fragmented frames.
4450                  * They are seen as a symptom of over-mtu sized frames.
4451                  */
4452                 if (unlikely(rtl8169_fragmented_frame(status))) {
4453                         dev->stats.rx_dropped++;
4454                         dev->stats.rx_length_errors++;
4455                         goto release_descriptor;
4456                 }
4457
4458                 skb = napi_alloc_skb(&tp->napi, pkt_size);
4459                 if (unlikely(!skb)) {
4460                         dev->stats.rx_dropped++;
4461                         goto release_descriptor;
4462                 }
4463
4464                 addr = le64_to_cpu(desc->addr);
4465                 rx_buf = page_address(tp->Rx_databuff[entry]);
4466
4467                 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
4468                 prefetch(rx_buf);
4469                 skb_copy_to_linear_data(skb, rx_buf, pkt_size);
4470                 skb->tail += pkt_size;
4471                 skb->len = pkt_size;
4472                 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
4473
4474                 rtl8169_rx_csum(skb, status);
4475                 skb->protocol = eth_type_trans(skb, dev);
4476
4477                 rtl8169_rx_vlan_tag(desc, skb);
4478
4479                 if (skb->pkt_type == PACKET_MULTICAST)
4480                         dev->stats.multicast++;
4481
4482                 napi_gro_receive(&tp->napi, skb);
4483
4484                 dev_sw_netstats_rx_add(dev, pkt_size);
4485 release_descriptor:
4486                 rtl8169_mark_to_asic(desc);
4487         }
4488
4489         return count;
4490 }
4491
4492 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
4493 {
4494         struct rtl8169_private *tp = dev_instance;
4495         u32 status = rtl_get_events(tp);
4496
4497         if ((status & 0xffff) == 0xffff || !(status & tp->irq_mask))
4498                 return IRQ_NONE;
4499
4500         if (unlikely(status & SYSErr)) {
4501                 rtl8169_pcierr_interrupt(tp->dev);
4502                 goto out;
4503         }
4504
4505         if (status & LinkChg)
4506                 phy_mac_interrupt(tp->phydev);
4507
4508         if (unlikely(status & RxFIFOOver &&
4509             tp->mac_version == RTL_GIGA_MAC_VER_11)) {
4510                 netif_stop_queue(tp->dev);
4511                 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
4512         }
4513
4514         if (napi_schedule_prep(&tp->napi)) {
4515                 rtl_irq_disable(tp);
4516                 __napi_schedule(&tp->napi);
4517         }
4518 out:
4519         rtl_ack_events(tp, status);
4520
4521         return IRQ_HANDLED;
4522 }
4523
4524 static void rtl_task(struct work_struct *work)
4525 {
4526         struct rtl8169_private *tp =
4527                 container_of(work, struct rtl8169_private, wk.work);
4528
4529         rtnl_lock();
4530
4531         if (!netif_running(tp->dev) ||
4532             !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
4533                 goto out_unlock;
4534
4535         if (test_and_clear_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags)) {
4536                 rtl_reset_work(tp);
4537                 netif_wake_queue(tp->dev);
4538         }
4539 out_unlock:
4540         rtnl_unlock();
4541 }
4542
4543 static int rtl8169_poll(struct napi_struct *napi, int budget)
4544 {
4545         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
4546         struct net_device *dev = tp->dev;
4547         int work_done;
4548
4549         rtl_tx(dev, tp, budget);
4550
4551         work_done = rtl_rx(dev, tp, budget);
4552
4553         if (work_done < budget && napi_complete_done(napi, work_done))
4554                 rtl_irq_enable(tp);
4555
4556         return work_done;
4557 }
4558
4559 static void r8169_phylink_handler(struct net_device *ndev)
4560 {
4561         struct rtl8169_private *tp = netdev_priv(ndev);
4562         struct device *d = tp_to_dev(tp);
4563
4564         if (netif_carrier_ok(ndev)) {
4565                 rtl_link_chg_patch(tp);
4566                 pm_request_resume(d);
4567         } else {
4568                 pm_runtime_idle(d);
4569         }
4570
4571         phy_print_status(tp->phydev);
4572 }
4573
4574 static int r8169_phy_connect(struct rtl8169_private *tp)
4575 {
4576         struct phy_device *phydev = tp->phydev;
4577         phy_interface_t phy_mode;
4578         int ret;
4579
4580         phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
4581                    PHY_INTERFACE_MODE_MII;
4582
4583         ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
4584                                  phy_mode);
4585         if (ret)
4586                 return ret;
4587
4588         if (!tp->supports_gmii)
4589                 phy_set_max_speed(phydev, SPEED_100);
4590
4591         phy_attached_info(phydev);
4592
4593         return 0;
4594 }
4595
4596 static void rtl8169_down(struct rtl8169_private *tp)
4597 {
4598         /* Clear all task flags */
4599         bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
4600
4601         phy_stop(tp->phydev);
4602
4603         rtl8169_update_counters(tp);
4604
4605         pci_clear_master(tp->pci_dev);
4606         rtl_pci_commit(tp);
4607
4608         rtl8169_cleanup(tp);
4609         rtl_disable_exit_l1(tp);
4610         rtl_prepare_power_down(tp);
4611 }
4612
4613 static void rtl8169_up(struct rtl8169_private *tp)
4614 {
4615         pci_set_master(tp->pci_dev);
4616         phy_init_hw(tp->phydev);
4617         phy_resume(tp->phydev);
4618         rtl8169_init_phy(tp);
4619         napi_enable(&tp->napi);
4620         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
4621         rtl_reset_work(tp);
4622
4623         phy_start(tp->phydev);
4624 }
4625
4626 static int rtl8169_close(struct net_device *dev)
4627 {
4628         struct rtl8169_private *tp = netdev_priv(dev);
4629         struct pci_dev *pdev = tp->pci_dev;
4630
4631         pm_runtime_get_sync(&pdev->dev);
4632
4633         netif_stop_queue(dev);
4634         rtl8169_down(tp);
4635         rtl8169_rx_clear(tp);
4636
4637         cancel_work_sync(&tp->wk.work);
4638
4639         free_irq(tp->irq, tp);
4640
4641         phy_disconnect(tp->phydev);
4642
4643         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4644                           tp->RxPhyAddr);
4645         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4646                           tp->TxPhyAddr);
4647         tp->TxDescArray = NULL;
4648         tp->RxDescArray = NULL;
4649
4650         pm_runtime_put_sync(&pdev->dev);
4651
4652         return 0;
4653 }
4654
4655 #ifdef CONFIG_NET_POLL_CONTROLLER
4656 static void rtl8169_netpoll(struct net_device *dev)
4657 {
4658         struct rtl8169_private *tp = netdev_priv(dev);
4659
4660         rtl8169_interrupt(tp->irq, tp);
4661 }
4662 #endif
4663
4664 static int rtl_open(struct net_device *dev)
4665 {
4666         struct rtl8169_private *tp = netdev_priv(dev);
4667         struct pci_dev *pdev = tp->pci_dev;
4668         unsigned long irqflags;
4669         int retval = -ENOMEM;
4670
4671         pm_runtime_get_sync(&pdev->dev);
4672
4673         /*
4674          * Rx and Tx descriptors needs 256 bytes alignment.
4675          * dma_alloc_coherent provides more.
4676          */
4677         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
4678                                              &tp->TxPhyAddr, GFP_KERNEL);
4679         if (!tp->TxDescArray)
4680                 goto out;
4681
4682         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
4683                                              &tp->RxPhyAddr, GFP_KERNEL);
4684         if (!tp->RxDescArray)
4685                 goto err_free_tx_0;
4686
4687         retval = rtl8169_init_ring(tp);
4688         if (retval < 0)
4689                 goto err_free_rx_1;
4690
4691         rtl_request_firmware(tp);
4692
4693         irqflags = pci_dev_msi_enabled(pdev) ? IRQF_NO_THREAD : IRQF_SHARED;
4694         retval = request_irq(tp->irq, rtl8169_interrupt, irqflags, dev->name, tp);
4695         if (retval < 0)
4696                 goto err_release_fw_2;
4697
4698         retval = r8169_phy_connect(tp);
4699         if (retval)
4700                 goto err_free_irq;
4701
4702         rtl8169_up(tp);
4703         rtl8169_init_counter_offsets(tp);
4704         netif_start_queue(dev);
4705 out:
4706         pm_runtime_put_sync(&pdev->dev);
4707
4708         return retval;
4709
4710 err_free_irq:
4711         free_irq(tp->irq, tp);
4712 err_release_fw_2:
4713         rtl_release_firmware(tp);
4714         rtl8169_rx_clear(tp);
4715 err_free_rx_1:
4716         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4717                           tp->RxPhyAddr);
4718         tp->RxDescArray = NULL;
4719 err_free_tx_0:
4720         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4721                           tp->TxPhyAddr);
4722         tp->TxDescArray = NULL;
4723         goto out;
4724 }
4725
4726 static void
4727 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
4728 {
4729         struct rtl8169_private *tp = netdev_priv(dev);
4730         struct pci_dev *pdev = tp->pci_dev;
4731         struct rtl8169_counters *counters = tp->counters;
4732
4733         pm_runtime_get_noresume(&pdev->dev);
4734
4735         netdev_stats_to_stats64(stats, &dev->stats);
4736         dev_fetch_sw_netstats(stats, dev->tstats);
4737
4738         /*
4739          * Fetch additional counter values missing in stats collected by driver
4740          * from tally counters.
4741          */
4742         if (pm_runtime_active(&pdev->dev))
4743                 rtl8169_update_counters(tp);
4744
4745         /*
4746          * Subtract values fetched during initalization.
4747          * See rtl8169_init_counter_offsets for a description why we do that.
4748          */
4749         stats->tx_errors = le64_to_cpu(counters->tx_errors) -
4750                 le64_to_cpu(tp->tc_offset.tx_errors);
4751         stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
4752                 le32_to_cpu(tp->tc_offset.tx_multi_collision);
4753         stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
4754                 le16_to_cpu(tp->tc_offset.tx_aborted);
4755         stats->rx_missed_errors = le16_to_cpu(counters->rx_missed) -
4756                 le16_to_cpu(tp->tc_offset.rx_missed);
4757
4758         pm_runtime_put_noidle(&pdev->dev);
4759 }
4760
4761 static void rtl8169_net_suspend(struct rtl8169_private *tp)
4762 {
4763         netif_device_detach(tp->dev);
4764
4765         if (netif_running(tp->dev))
4766                 rtl8169_down(tp);
4767 }
4768
4769 static int rtl8169_runtime_resume(struct device *dev)
4770 {
4771         struct rtl8169_private *tp = dev_get_drvdata(dev);
4772
4773         rtl_rar_set(tp, tp->dev->dev_addr);
4774         __rtl8169_set_wol(tp, tp->saved_wolopts);
4775
4776         if (tp->TxDescArray)
4777                 rtl8169_up(tp);
4778
4779         netif_device_attach(tp->dev);
4780
4781         return 0;
4782 }
4783
4784 static int rtl8169_suspend(struct device *device)
4785 {
4786         struct rtl8169_private *tp = dev_get_drvdata(device);
4787
4788         rtnl_lock();
4789         rtl8169_net_suspend(tp);
4790         if (!device_may_wakeup(tp_to_dev(tp)))
4791                 clk_disable_unprepare(tp->clk);
4792         rtnl_unlock();
4793
4794         return 0;
4795 }
4796
4797 static int rtl8169_resume(struct device *device)
4798 {
4799         struct rtl8169_private *tp = dev_get_drvdata(device);
4800
4801         if (!device_may_wakeup(tp_to_dev(tp)))
4802                 clk_prepare_enable(tp->clk);
4803
4804         /* Reportedly at least Asus X453MA truncates packets otherwise */
4805         if (tp->mac_version == RTL_GIGA_MAC_VER_37)
4806                 rtl_init_rxcfg(tp);
4807
4808         return rtl8169_runtime_resume(device);
4809 }
4810
4811 static int rtl8169_runtime_suspend(struct device *device)
4812 {
4813         struct rtl8169_private *tp = dev_get_drvdata(device);
4814
4815         if (!tp->TxDescArray) {
4816                 netif_device_detach(tp->dev);
4817                 return 0;
4818         }
4819
4820         rtnl_lock();
4821         __rtl8169_set_wol(tp, WAKE_PHY);
4822         rtl8169_net_suspend(tp);
4823         rtnl_unlock();
4824
4825         return 0;
4826 }
4827
4828 static int rtl8169_runtime_idle(struct device *device)
4829 {
4830         struct rtl8169_private *tp = dev_get_drvdata(device);
4831
4832         if (tp->dash_type != RTL_DASH_NONE)
4833                 return -EBUSY;
4834
4835         if (!netif_running(tp->dev) || !netif_carrier_ok(tp->dev))
4836                 pm_schedule_suspend(device, 10000);
4837
4838         return -EBUSY;
4839 }
4840
4841 static const struct dev_pm_ops rtl8169_pm_ops = {
4842         SYSTEM_SLEEP_PM_OPS(rtl8169_suspend, rtl8169_resume)
4843         RUNTIME_PM_OPS(rtl8169_runtime_suspend, rtl8169_runtime_resume,
4844                        rtl8169_runtime_idle)
4845 };
4846
4847 static void rtl_shutdown(struct pci_dev *pdev)
4848 {
4849         struct rtl8169_private *tp = pci_get_drvdata(pdev);
4850
4851         rtnl_lock();
4852         rtl8169_net_suspend(tp);
4853         rtnl_unlock();
4854
4855         /* Restore original MAC address */
4856         rtl_rar_set(tp, tp->dev->perm_addr);
4857
4858         if (system_state == SYSTEM_POWER_OFF &&
4859             tp->dash_type == RTL_DASH_NONE) {
4860                 pci_wake_from_d3(pdev, tp->saved_wolopts);
4861                 pci_set_power_state(pdev, PCI_D3hot);
4862         }
4863 }
4864
4865 static void rtl_remove_one(struct pci_dev *pdev)
4866 {
4867         struct rtl8169_private *tp = pci_get_drvdata(pdev);
4868
4869         if (pci_dev_run_wake(pdev))
4870                 pm_runtime_get_noresume(&pdev->dev);
4871
4872         unregister_netdev(tp->dev);
4873
4874         if (tp->dash_type != RTL_DASH_NONE)
4875                 rtl8168_driver_stop(tp);
4876
4877         rtl_release_firmware(tp);
4878
4879         /* restore original MAC address */
4880         rtl_rar_set(tp, tp->dev->perm_addr);
4881 }
4882
4883 static const struct net_device_ops rtl_netdev_ops = {
4884         .ndo_open               = rtl_open,
4885         .ndo_stop               = rtl8169_close,
4886         .ndo_get_stats64        = rtl8169_get_stats64,
4887         .ndo_start_xmit         = rtl8169_start_xmit,
4888         .ndo_features_check     = rtl8169_features_check,
4889         .ndo_tx_timeout         = rtl8169_tx_timeout,
4890         .ndo_validate_addr      = eth_validate_addr,
4891         .ndo_change_mtu         = rtl8169_change_mtu,
4892         .ndo_fix_features       = rtl8169_fix_features,
4893         .ndo_set_features       = rtl8169_set_features,
4894         .ndo_set_mac_address    = rtl_set_mac_address,
4895         .ndo_eth_ioctl          = phy_do_ioctl_running,
4896         .ndo_set_rx_mode        = rtl_set_rx_mode,
4897 #ifdef CONFIG_NET_POLL_CONTROLLER
4898         .ndo_poll_controller    = rtl8169_netpoll,
4899 #endif
4900
4901 };
4902
4903 static void rtl_set_irq_mask(struct rtl8169_private *tp)
4904 {
4905         tp->irq_mask = RxOK | RxErr | TxOK | TxErr | LinkChg;
4906
4907         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
4908                 tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver;
4909         else if (tp->mac_version == RTL_GIGA_MAC_VER_11)
4910                 /* special workaround needed */
4911                 tp->irq_mask |= RxFIFOOver;
4912         else
4913                 tp->irq_mask |= RxOverflow;
4914 }
4915
4916 static int rtl_alloc_irq(struct rtl8169_private *tp)
4917 {
4918         unsigned int flags;
4919
4920         switch (tp->mac_version) {
4921         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
4922                 rtl_unlock_config_regs(tp);
4923                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
4924                 rtl_lock_config_regs(tp);
4925                 fallthrough;
4926         case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_17:
4927                 flags = PCI_IRQ_LEGACY;
4928                 break;
4929         default:
4930                 flags = PCI_IRQ_ALL_TYPES;
4931                 break;
4932         }
4933
4934         return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
4935 }
4936
4937 static void rtl_read_mac_address(struct rtl8169_private *tp,
4938                                  u8 mac_addr[ETH_ALEN])
4939 {
4940         /* Get MAC address */
4941         if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) {
4942                 u32 value;
4943
4944                 value = rtl_eri_read(tp, 0xe0);
4945                 put_unaligned_le32(value, mac_addr);
4946                 value = rtl_eri_read(tp, 0xe4);
4947                 put_unaligned_le16(value, mac_addr + 4);
4948         } else if (rtl_is_8125(tp)) {
4949                 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP);
4950         }
4951 }
4952
4953 DECLARE_RTL_COND(rtl_link_list_ready_cond)
4954 {
4955         return RTL_R8(tp, MCU) & LINK_LIST_RDY;
4956 }
4957
4958 static void r8168g_wait_ll_share_fifo_ready(struct rtl8169_private *tp)
4959 {
4960         rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42);
4961 }
4962
4963 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
4964 {
4965         struct rtl8169_private *tp = mii_bus->priv;
4966
4967         if (phyaddr > 0)
4968                 return -ENODEV;
4969
4970         return rtl_readphy(tp, phyreg);
4971 }
4972
4973 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
4974                                 int phyreg, u16 val)
4975 {
4976         struct rtl8169_private *tp = mii_bus->priv;
4977
4978         if (phyaddr > 0)
4979                 return -ENODEV;
4980
4981         rtl_writephy(tp, phyreg, val);
4982
4983         return 0;
4984 }
4985
4986 static int r8169_mdio_register(struct rtl8169_private *tp)
4987 {
4988         struct pci_dev *pdev = tp->pci_dev;
4989         struct mii_bus *new_bus;
4990         int ret;
4991
4992         new_bus = devm_mdiobus_alloc(&pdev->dev);
4993         if (!new_bus)
4994                 return -ENOMEM;
4995
4996         new_bus->name = "r8169";
4997         new_bus->priv = tp;
4998         new_bus->parent = &pdev->dev;
4999         new_bus->irq[0] = PHY_MAC_INTERRUPT;
5000         snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x-%x",
5001                  pci_domain_nr(pdev->bus), pci_dev_id(pdev));
5002
5003         new_bus->read = r8169_mdio_read_reg;
5004         new_bus->write = r8169_mdio_write_reg;
5005
5006         ret = devm_mdiobus_register(&pdev->dev, new_bus);
5007         if (ret)
5008                 return ret;
5009
5010         tp->phydev = mdiobus_get_phy(new_bus, 0);
5011         if (!tp->phydev) {
5012                 return -ENODEV;
5013         } else if (!tp->phydev->drv) {
5014                 /* Most chip versions fail with the genphy driver.
5015                  * Therefore ensure that the dedicated PHY driver is loaded.
5016                  */
5017                 dev_err(&pdev->dev, "no dedicated PHY driver found for PHY ID 0x%08x, maybe realtek.ko needs to be added to initramfs?\n",
5018                         tp->phydev->phy_id);
5019                 return -EUNATCH;
5020         }
5021
5022         tp->phydev->mac_managed_pm = true;
5023
5024         phy_support_asym_pause(tp->phydev);
5025
5026         /* PHY will be woken up in rtl_open() */
5027         phy_suspend(tp->phydev);
5028
5029         return 0;
5030 }
5031
5032 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
5033 {
5034         rtl_enable_rxdvgate(tp);
5035
5036         RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
5037         msleep(1);
5038         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5039
5040         r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
5041         r8168g_wait_ll_share_fifo_ready(tp);
5042
5043         r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15));
5044         r8168g_wait_ll_share_fifo_ready(tp);
5045 }
5046
5047 static void rtl_hw_init_8125(struct rtl8169_private *tp)
5048 {
5049         rtl_enable_rxdvgate(tp);
5050
5051         RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
5052         msleep(1);
5053         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5054
5055         r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
5056         r8168g_wait_ll_share_fifo_ready(tp);
5057
5058         r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0);
5059         r8168_mac_ocp_write(tp, 0xc0a6, 0x0150);
5060         r8168_mac_ocp_write(tp, 0xc01e, 0x5555);
5061         r8168g_wait_ll_share_fifo_ready(tp);
5062 }
5063
5064 static void rtl_hw_initialize(struct rtl8169_private *tp)
5065 {
5066         switch (tp->mac_version) {
5067         case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_53:
5068                 rtl8168ep_stop_cmac(tp);
5069                 fallthrough;
5070         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
5071                 rtl_hw_init_8168g(tp);
5072                 break;
5073         case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63:
5074                 rtl_hw_init_8125(tp);
5075                 break;
5076         default:
5077                 break;
5078         }
5079 }
5080
5081 static int rtl_jumbo_max(struct rtl8169_private *tp)
5082 {
5083         /* Non-GBit versions don't support jumbo frames */
5084         if (!tp->supports_gmii)
5085                 return 0;
5086
5087         switch (tp->mac_version) {
5088         /* RTL8169 */
5089         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
5090                 return JUMBO_7K;
5091         /* RTL8168b */
5092         case RTL_GIGA_MAC_VER_11:
5093         case RTL_GIGA_MAC_VER_17:
5094                 return JUMBO_4K;
5095         /* RTL8168c */
5096         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
5097                 return JUMBO_6K;
5098         default:
5099                 return JUMBO_9K;
5100         }
5101 }
5102
5103 static void rtl_init_mac_address(struct rtl8169_private *tp)
5104 {
5105         u8 mac_addr[ETH_ALEN] __aligned(2) = {};
5106         struct net_device *dev = tp->dev;
5107         int rc;
5108
5109         rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr);
5110         if (!rc)
5111                 goto done;
5112
5113         rtl_read_mac_address(tp, mac_addr);
5114         if (is_valid_ether_addr(mac_addr))
5115                 goto done;
5116
5117         rtl_read_mac_from_reg(tp, mac_addr, MAC0);
5118         if (is_valid_ether_addr(mac_addr))
5119                 goto done;
5120
5121         eth_random_addr(mac_addr);
5122         dev->addr_assign_type = NET_ADDR_RANDOM;
5123         dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n");
5124 done:
5125         eth_hw_addr_set(dev, mac_addr);
5126         rtl_rar_set(tp, mac_addr);
5127 }
5128
5129 /* register is set if system vendor successfully tested ASPM 1.2 */
5130 static bool rtl_aspm_is_safe(struct rtl8169_private *tp)
5131 {
5132         if (tp->mac_version >= RTL_GIGA_MAC_VER_61 &&
5133             r8168_mac_ocp_read(tp, 0xc0b2) & 0xf)
5134                 return true;
5135
5136         return false;
5137 }
5138
5139 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
5140 {
5141         struct rtl8169_private *tp;
5142         int jumbo_max, region, rc;
5143         enum mac_version chipset;
5144         struct net_device *dev;
5145         u16 xid;
5146
5147         dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
5148         if (!dev)
5149                 return -ENOMEM;
5150
5151         SET_NETDEV_DEV(dev, &pdev->dev);
5152         dev->netdev_ops = &rtl_netdev_ops;
5153         tp = netdev_priv(dev);
5154         tp->dev = dev;
5155         tp->pci_dev = pdev;
5156         tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1;
5157         tp->eee_adv = -1;
5158         tp->ocp_base = OCP_STD_PHY_BASE;
5159
5160         dev->tstats = devm_netdev_alloc_pcpu_stats(&pdev->dev,
5161                                                    struct pcpu_sw_netstats);
5162         if (!dev->tstats)
5163                 return -ENOMEM;
5164
5165         /* Get the *optional* external "ether_clk" used on some boards */
5166         tp->clk = devm_clk_get_optional_enabled(&pdev->dev, "ether_clk");
5167         if (IS_ERR(tp->clk))
5168                 return dev_err_probe(&pdev->dev, PTR_ERR(tp->clk), "failed to get ether_clk\n");
5169
5170         /* enable device (incl. PCI PM wakeup and hotplug setup) */
5171         rc = pcim_enable_device(pdev);
5172         if (rc < 0) {
5173                 dev_err(&pdev->dev, "enable failure\n");
5174                 return rc;
5175         }
5176
5177         if (pcim_set_mwi(pdev) < 0)
5178                 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
5179
5180         /* use first MMIO region */
5181         region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
5182         if (region < 0) {
5183                 dev_err(&pdev->dev, "no MMIO resource found\n");
5184                 return -ENODEV;
5185         }
5186
5187         rc = pcim_iomap_regions(pdev, BIT(region), KBUILD_MODNAME);
5188         if (rc < 0) {
5189                 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
5190                 return rc;
5191         }
5192
5193         tp->mmio_addr = pcim_iomap_table(pdev)[region];
5194
5195         xid = (RTL_R32(tp, TxConfig) >> 20) & 0xfcf;
5196
5197         /* Identify chip attached to board */
5198         chipset = rtl8169_get_mac_version(xid, tp->supports_gmii);
5199         if (chipset == RTL_GIGA_MAC_NONE) {
5200                 dev_err(&pdev->dev, "unknown chip XID %03x, contact r8169 maintainers (see MAINTAINERS file)\n", xid);
5201                 return -ENODEV;
5202         }
5203
5204         tp->mac_version = chipset;
5205
5206         /* Disable ASPM L1 as that cause random device stop working
5207          * problems as well as full system hangs for some PCIe devices users.
5208          * Chips from RTL8168h partially have issues with L1.2, but seem
5209          * to work fine with L1 and L1.1.
5210          */
5211         if (rtl_aspm_is_safe(tp))
5212                 rc = 0;
5213         else if (tp->mac_version >= RTL_GIGA_MAC_VER_46)
5214                 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L1_2);
5215         else
5216                 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L1);
5217         tp->aspm_manageable = !rc;
5218
5219         tp->dash_type = rtl_check_dash(tp);
5220
5221         tp->cp_cmd = RTL_R16(tp, CPlusCmd) & CPCMD_MASK;
5222
5223         if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 &&
5224             !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)))
5225                 dev->features |= NETIF_F_HIGHDMA;
5226
5227         rtl_init_rxcfg(tp);
5228
5229         rtl8169_irq_mask_and_ack(tp);
5230
5231         rtl_hw_initialize(tp);
5232
5233         rtl_hw_reset(tp);
5234
5235         rc = rtl_alloc_irq(tp);
5236         if (rc < 0) {
5237                 dev_err(&pdev->dev, "Can't allocate interrupt\n");
5238                 return rc;
5239         }
5240         tp->irq = pci_irq_vector(pdev, 0);
5241
5242         INIT_WORK(&tp->wk.work, rtl_task);
5243
5244         rtl_init_mac_address(tp);
5245
5246         dev->ethtool_ops = &rtl8169_ethtool_ops;
5247
5248         netif_napi_add(dev, &tp->napi, rtl8169_poll);
5249
5250         dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
5251                            NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
5252         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO;
5253         dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
5254
5255         /*
5256          * Pretend we are using VLANs; This bypasses a nasty bug where
5257          * Interrupts stop flowing on high load on 8110SCd controllers.
5258          */
5259         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
5260                 /* Disallow toggling */
5261                 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
5262
5263         if (rtl_chip_supports_csum_v2(tp))
5264                 dev->hw_features |= NETIF_F_IPV6_CSUM;
5265
5266         dev->features |= dev->hw_features;
5267
5268         /* There has been a number of reports that using SG/TSO results in
5269          * tx timeouts. However for a lot of people SG/TSO works fine.
5270          * Therefore disable both features by default, but allow users to
5271          * enable them. Use at own risk!
5272          */
5273         if (rtl_chip_supports_csum_v2(tp)) {
5274                 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6;
5275                 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V2);
5276                 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V2);
5277         } else {
5278                 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO;
5279                 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V1);
5280                 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V1);
5281         }
5282
5283         dev->hw_features |= NETIF_F_RXALL;
5284         dev->hw_features |= NETIF_F_RXFCS;
5285
5286         netdev_sw_irq_coalesce_default_on(dev);
5287
5288         /* configure chip for default features */
5289         rtl8169_set_features(dev, dev->features);
5290
5291         if (tp->dash_type == RTL_DASH_NONE) {
5292                 rtl_set_d3_pll_down(tp, true);
5293         } else {
5294                 rtl_set_d3_pll_down(tp, false);
5295                 dev->wol_enabled = 1;
5296         }
5297
5298         jumbo_max = rtl_jumbo_max(tp);
5299         if (jumbo_max)
5300                 dev->max_mtu = jumbo_max;
5301
5302         rtl_set_irq_mask(tp);
5303
5304         tp->fw_name = rtl_chip_infos[chipset].fw_name;
5305
5306         tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
5307                                             &tp->counters_phys_addr,
5308                                             GFP_KERNEL);
5309         if (!tp->counters)
5310                 return -ENOMEM;
5311
5312         pci_set_drvdata(pdev, tp);
5313
5314         rc = r8169_mdio_register(tp);
5315         if (rc)
5316                 return rc;
5317
5318         rc = register_netdev(dev);
5319         if (rc)
5320                 return rc;
5321
5322         netdev_info(dev, "%s, %pM, XID %03x, IRQ %d\n",
5323                     rtl_chip_infos[chipset].name, dev->dev_addr, xid, tp->irq);
5324
5325         if (jumbo_max)
5326                 netdev_info(dev, "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
5327                             jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?
5328                             "ok" : "ko");
5329
5330         if (tp->dash_type != RTL_DASH_NONE) {
5331                 netdev_info(dev, "DASH enabled\n");
5332                 rtl8168_driver_start(tp);
5333         }
5334
5335         if (pci_dev_run_wake(pdev))
5336                 pm_runtime_put_sync(&pdev->dev);
5337
5338         return 0;
5339 }
5340
5341 static struct pci_driver rtl8169_pci_driver = {
5342         .name           = KBUILD_MODNAME,
5343         .id_table       = rtl8169_pci_tbl,
5344         .probe          = rtl_init_one,
5345         .remove         = rtl_remove_one,
5346         .shutdown       = rtl_shutdown,
5347         .driver.pm      = pm_ptr(&rtl8169_pm_ops),
5348 };
5349
5350 module_pci_driver(rtl8169_pci_driver);