drivers/net/ethernet/realtek/r8169_main.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   4  *
   5  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   6  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   7  * Copyright (c) a lot of people too. Please respect their work.
   8  *
   9  * See MAINTAINERS file for support contact information.
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/clk.h>
  17 #include <linux/delay.h>
  18 #include <linux/ethtool.h>
  19 #include <linux/phy.h>
  20 #include <linux/if_vlan.h>
  21 #include <linux/in.h>
  22 #include <linux/io.h>
  23 #include <linux/ip.h>
  24 #include <linux/tcp.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/pm_runtime.h>
  28 #include <linux/bitfield.h>
  29 #include <linux/prefetch.h>
  30 #include <linux/ipv6.h>
  31 #include <net/ip6_checksum.h>
  32
  33 #include "r8169.h"
  34 #include "r8169_firmware.h"
  35
  36 #define MODULENAME "r8169"
  37
  38 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  39 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  40 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  41 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  42 #define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
  43 #define FIRMWARE_8168F_1        "rtl_nic/rtl8168f-1.fw"
  44 #define FIRMWARE_8168F_2        "rtl_nic/rtl8168f-2.fw"
  45 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  46 #define FIRMWARE_8402_1         "rtl_nic/rtl8402-1.fw"
  47 #define FIRMWARE_8411_1         "rtl_nic/rtl8411-1.fw"
  48 #define FIRMWARE_8411_2         "rtl_nic/rtl8411-2.fw"
  49 #define FIRMWARE_8106E_1        "rtl_nic/rtl8106e-1.fw"
  50 #define FIRMWARE_8106E_2        "rtl_nic/rtl8106e-2.fw"
  51 #define FIRMWARE_8168G_2        "rtl_nic/rtl8168g-2.fw"
  52 #define FIRMWARE_8168G_3        "rtl_nic/rtl8168g-3.fw"
  53 #define FIRMWARE_8168H_1        "rtl_nic/rtl8168h-1.fw"
  54 #define FIRMWARE_8168H_2        "rtl_nic/rtl8168h-2.fw"
  55 #define FIRMWARE_8168FP_3       "rtl_nic/rtl8168fp-3.fw"
  56 #define FIRMWARE_8107E_1        "rtl_nic/rtl8107e-1.fw"
  57 #define FIRMWARE_8107E_2        "rtl_nic/rtl8107e-2.fw"
  58 #define FIRMWARE_8125A_3        "rtl_nic/rtl8125a-3.fw"
  59 #define FIRMWARE_8125B_2        "rtl_nic/rtl8125b-2.fw"
  60
  61 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  62    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  63 #define MC_FILTER_LIMIT 32
  64
  65 #define TX_DMA_BURST    7       /* Maximum PCI burst, '7' is unlimited */
  66 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  67
  68 #define R8169_REGS_SIZE         256
  69 #define R8169_RX_BUF_SIZE       (SZ_16K - 1)
  70 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  71 #define NUM_RX_DESC     256U    /* Number of Rx descriptor registers */
  72 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  73 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  74
  75 #define OCP_STD_PHY_BASE        0xa400
  76
  77 #define RTL_CFG_NO_GBIT 1
  78
  79 /* write/read MMIO register */
  80 #define RTL_W8(tp, reg, val8)   writeb((val8), tp->mmio_addr + (reg))
  81 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
  82 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
  83 #define RTL_R8(tp, reg)         readb(tp->mmio_addr + (reg))
  84 #define RTL_R16(tp, reg)                readw(tp->mmio_addr + (reg))
  85 #define RTL_R32(tp, reg)                readl(tp->mmio_addr + (reg))
  86
  87 #define JUMBO_4K        (4 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
  88 #define JUMBO_6K        (6 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
  89 #define JUMBO_7K        (7 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
  90 #define JUMBO_9K        (9 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
  91
  92 static const struct {
  93         const char *name;
  94         const char *fw_name;
  95 } rtl_chip_infos[] = {
  96         /* PCI devices. */
  97         [RTL_GIGA_MAC_VER_02] = {"RTL8169s"                             },
  98         [RTL_GIGA_MAC_VER_03] = {"RTL8110s"                             },
  99         [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb"                     },
 100         [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc"                     },
 101         [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc"                     },
 102         /* PCI-E devices. */
 103         [RTL_GIGA_MAC_VER_07] = {"RTL8102e"                             },
 104         [RTL_GIGA_MAC_VER_08] = {"RTL8102e"                             },
 105         [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e"                    },
 106         [RTL_GIGA_MAC_VER_10] = {"RTL8101e"                             },
 107         [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b"                       },
 108         [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b"                       },
 109         [RTL_GIGA_MAC_VER_13] = {"RTL8101e/RTL8100e"                    },
 110         [RTL_GIGA_MAC_VER_14] = {"RTL8401"                              },
 111         [RTL_GIGA_MAC_VER_16] = {"RTL8101e"                             },
 112         [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b"                       },
 113         [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp"                     },
 114         [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c"                       },
 115         [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c"                       },
 116         [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c"                       },
 117         [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c"                       },
 118         [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp"                     },
 119         [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp"                     },
 120         [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d",      FIRMWARE_8168D_1},
 121         [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d",      FIRMWARE_8168D_2},
 122         [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp"                     },
 123         [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp"                     },
 124         [RTL_GIGA_MAC_VER_29] = {"RTL8105e",            FIRMWARE_8105E_1},
 125         [RTL_GIGA_MAC_VER_30] = {"RTL8105e",            FIRMWARE_8105E_1},
 126         [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp"                     },
 127         [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e",      FIRMWARE_8168E_1},
 128         [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e",      FIRMWARE_8168E_2},
 129         [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl",  FIRMWARE_8168E_3},
 130         [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f",      FIRMWARE_8168F_1},
 131         [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f",      FIRMWARE_8168F_2},
 132         [RTL_GIGA_MAC_VER_37] = {"RTL8402",             FIRMWARE_8402_1 },
 133         [RTL_GIGA_MAC_VER_38] = {"RTL8411",             FIRMWARE_8411_1 },
 134         [RTL_GIGA_MAC_VER_39] = {"RTL8106e",            FIRMWARE_8106E_1},
 135         [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g",      FIRMWARE_8168G_2},
 136         [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g"                       },
 137         [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu",    FIRMWARE_8168G_3},
 138         [RTL_GIGA_MAC_VER_43] = {"RTL8106eus",          FIRMWARE_8106E_2},
 139         [RTL_GIGA_MAC_VER_44] = {"RTL8411b",            FIRMWARE_8411_2 },
 140         [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h",      FIRMWARE_8168H_1},
 141         [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h",      FIRMWARE_8168H_2},
 142         [RTL_GIGA_MAC_VER_47] = {"RTL8107e",            FIRMWARE_8107E_1},
 143         [RTL_GIGA_MAC_VER_48] = {"RTL8107e",            FIRMWARE_8107E_2},
 144         [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep"                     },
 145         [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep"                     },
 146         [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep"                     },
 147         [RTL_GIGA_MAC_VER_52] = {"RTL8168fp/RTL8117",  FIRMWARE_8168FP_3},
 148         [RTL_GIGA_MAC_VER_60] = {"RTL8125A"                             },
 149         [RTL_GIGA_MAC_VER_61] = {"RTL8125A",            FIRMWARE_8125A_3},
 150         /* reserve 62 for CFG_METHOD_4 in the vendor driver */
 151         [RTL_GIGA_MAC_VER_63] = {"RTL8125B",            FIRMWARE_8125B_2},
 152 };
 153
 154 static const struct pci_device_id rtl8169_pci_tbl[] = {
 155         { PCI_VDEVICE(REALTEK,  0x2502) },
 156         { PCI_VDEVICE(REALTEK,  0x2600) },
 157         { PCI_VDEVICE(REALTEK,  0x8129) },
 158         { PCI_VDEVICE(REALTEK,  0x8136), RTL_CFG_NO_GBIT },
 159         { PCI_VDEVICE(REALTEK,  0x8161) },
 160         { PCI_VDEVICE(REALTEK,  0x8167) },
 161         { PCI_VDEVICE(REALTEK,  0x8168) },
 162         { PCI_VDEVICE(NCUBE,    0x8168) },
 163         { PCI_VDEVICE(REALTEK,  0x8169) },
 164         { PCI_VENDOR_ID_DLINK,  0x4300,
 165                 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 },
 166         { PCI_VDEVICE(DLINK,    0x4300) },
 167         { PCI_VDEVICE(DLINK,    0x4302) },
 168         { PCI_VDEVICE(AT,       0xc107) },
 169         { PCI_VDEVICE(USR,      0x0116) },
 170         { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 },
 171         { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 },
 172         { PCI_VDEVICE(REALTEK,  0x8125) },
 173         { PCI_VDEVICE(REALTEK,  0x3000) },
 174         {}
 175 };
 176
 177 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 178
 179 enum rtl_registers {
 180         MAC0            = 0,    /* Ethernet hardware address. */
 181         MAC4            = 4,
 182         MAR0            = 8,    /* Multicast filter. */
 183         CounterAddrLow          = 0x10,
 184         CounterAddrHigh         = 0x14,
 185         TxDescStartAddrLow      = 0x20,
 186         TxDescStartAddrHigh     = 0x24,
 187         TxHDescStartAddrLow     = 0x28,
 188         TxHDescStartAddrHigh    = 0x2c,
 189         FLASH           = 0x30,
 190         ERSR            = 0x36,
 191         ChipCmd         = 0x37,
 192         TxPoll          = 0x38,
 193         IntrMask        = 0x3c,
 194         IntrStatus      = 0x3e,
 195
 196         TxConfig        = 0x40,
 197 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 198 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 199
 200         RxConfig        = 0x44,
 201 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 202 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 203 #define RXCFG_FIFO_SHIFT                13
 204                                         /* No threshold before first PCI xfer */
 205 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 206 #define RX_EARLY_OFF                    (1 << 11)
 207 #define RXCFG_DMA_SHIFT                 8
 208                                         /* Unlimited maximum PCI burst. */
 209 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 210
 211         Cfg9346         = 0x50,
 212         Config0         = 0x51,
 213         Config1         = 0x52,
 214         Config2         = 0x53,
 215 #define PME_SIGNAL                      (1 << 5)        /* 8168c and later */
 216
 217         Config3         = 0x54,
 218         Config4         = 0x55,
 219         Config5         = 0x56,
 220         PHYAR           = 0x60,
 221         PHYstatus       = 0x6c,
 222         RxMaxSize       = 0xda,
 223         CPlusCmd        = 0xe0,
 224         IntrMitigate    = 0xe2,
 225
 226 #define RTL_COALESCE_TX_USECS   GENMASK(15, 12)
 227 #define RTL_COALESCE_TX_FRAMES  GENMASK(11, 8)
 228 #define RTL_COALESCE_RX_USECS   GENMASK(7, 4)
 229 #define RTL_COALESCE_RX_FRAMES  GENMASK(3, 0)
 230
 231 #define RTL_COALESCE_T_MAX      0x0fU
 232 #define RTL_COALESCE_FRAME_MAX  (RTL_COALESCE_T_MAX * 4)
 233
 234         RxDescAddrLow   = 0xe4,
 235         RxDescAddrHigh  = 0xe8,
 236         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 237
 238 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 239
 240         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 241
 242 #define TxPacketMax     (8064 >> 7)
 243 #define EarlySize       0x27
 244
 245         FuncEvent       = 0xf0,
 246         FuncEventMask   = 0xf4,
 247         FuncPresetState = 0xf8,
 248         IBCR0           = 0xf8,
 249         IBCR2           = 0xf9,
 250         IBIMR0          = 0xfa,
 251         IBISR0          = 0xfb,
 252         FuncForceEvent  = 0xfc,
 253 };
 254
 255 enum rtl8168_8101_registers {
 256         CSIDR                   = 0x64,
 257         CSIAR                   = 0x68,
 258 #define CSIAR_FLAG                      0x80000000
 259 #define CSIAR_WRITE_CMD                 0x80000000
 260 #define CSIAR_BYTE_ENABLE               0x0000f000
 261 #define CSIAR_ADDR_MASK                 0x00000fff
 262         PMCH                    = 0x6f,
 263         EPHYAR                  = 0x80,
 264 #define EPHYAR_FLAG                     0x80000000
 265 #define EPHYAR_WRITE_CMD                0x80000000
 266 #define EPHYAR_REG_MASK                 0x1f
 267 #define EPHYAR_REG_SHIFT                16
 268 #define EPHYAR_DATA_MASK                0xffff
 269         DLLPR                   = 0xd0,
 270 #define PFM_EN                          (1 << 6)
 271 #define TX_10M_PS_EN                    (1 << 7)
 272         DBG_REG                 = 0xd1,
 273 #define FIX_NAK_1                       (1 << 4)
 274 #define FIX_NAK_2                       (1 << 3)
 275         TWSI                    = 0xd2,
 276         MCU                     = 0xd3,
 277 #define NOW_IS_OOB                      (1 << 7)
 278 #define TX_EMPTY                        (1 << 5)
 279 #define RX_EMPTY                        (1 << 4)
 280 #define RXTX_EMPTY                      (TX_EMPTY | RX_EMPTY)
 281 #define EN_NDP                          (1 << 3)
 282 #define EN_OOB_RESET                    (1 << 2)
 283 #define LINK_LIST_RDY                   (1 << 1)
 284         EFUSEAR                 = 0xdc,
 285 #define EFUSEAR_FLAG                    0x80000000
 286 #define EFUSEAR_WRITE_CMD               0x80000000
 287 #define EFUSEAR_READ_CMD                0x00000000
 288 #define EFUSEAR_REG_MASK                0x03ff
 289 #define EFUSEAR_REG_SHIFT               8
 290 #define EFUSEAR_DATA_MASK               0xff
 291         MISC_1                  = 0xf2,
 292 #define PFM_D3COLD_EN                   (1 << 6)
 293 };
 294
 295 enum rtl8168_registers {
 296         LED_FREQ                = 0x1a,
 297         EEE_LED                 = 0x1b,
 298         ERIDR                   = 0x70,
 299         ERIAR                   = 0x74,
 300 #define ERIAR_FLAG                      0x80000000
 301 #define ERIAR_WRITE_CMD                 0x80000000
 302 #define ERIAR_READ_CMD                  0x00000000
 303 #define ERIAR_ADDR_BYTE_ALIGN           4
 304 #define ERIAR_TYPE_SHIFT                16
 305 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 306 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 307 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 308 #define ERIAR_OOB                       (0x02 << ERIAR_TYPE_SHIFT)
 309 #define ERIAR_MASK_SHIFT                12
 310 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 311 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 312 #define ERIAR_MASK_0100                 (0x4 << ERIAR_MASK_SHIFT)
 313 #define ERIAR_MASK_0101                 (0x5 << ERIAR_MASK_SHIFT)
 314 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 315         EPHY_RXER_NUM           = 0x7c,
 316         OCPDR                   = 0xb0, /* OCP GPHY access */
 317 #define OCPDR_WRITE_CMD                 0x80000000
 318 #define OCPDR_READ_CMD                  0x00000000
 319 #define OCPDR_REG_MASK                  0x7f
 320 #define OCPDR_GPHY_REG_SHIFT            16
 321 #define OCPDR_DATA_MASK                 0xffff
 322         OCPAR                   = 0xb4,
 323 #define OCPAR_FLAG                      0x80000000
 324 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 325 #define OCPAR_GPHY_READ_CMD             0x0000f060
 326         GPHY_OCP                = 0xb8,
 327         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 328         MISC                    = 0xf0, /* 8168e only. */
 329 #define TXPLA_RST                       (1 << 29)
 330 #define DISABLE_LAN_EN                  (1 << 23) /* Enable GPIO pin */
 331 #define PWM_EN                          (1 << 22)
 332 #define RXDV_GATED_EN                   (1 << 19)
 333 #define EARLY_TALLY_EN                  (1 << 16)
 334 };
 335
 336 enum rtl8125_registers {
 337         IntrMask_8125           = 0x38,
 338         IntrStatus_8125         = 0x3c,
 339         TxPoll_8125             = 0x90,
 340         MAC0_BKP                = 0x19e0,
 341         EEE_TXIDLE_TIMER_8125   = 0x6048,
 342 };
 343
 344 #define RX_VLAN_INNER_8125      BIT(22)
 345 #define RX_VLAN_OUTER_8125      BIT(23)
 346 #define RX_VLAN_8125            (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125)
 347
 348 #define RX_FETCH_DFLT_8125      (8 << 27)
 349
 350 enum rtl_register_content {
 351         /* InterruptStatusBits */
 352         SYSErr          = 0x8000,
 353         PCSTimeout      = 0x4000,
 354         SWInt           = 0x0100,
 355         TxDescUnavail   = 0x0080,
 356         RxFIFOOver      = 0x0040,
 357         LinkChg         = 0x0020,
 358         RxOverflow      = 0x0010,
 359         TxErr           = 0x0008,
 360         TxOK            = 0x0004,
 361         RxErr           = 0x0002,
 362         RxOK            = 0x0001,
 363
 364         /* RxStatusDesc */
 365         RxRWT   = (1 << 22),
 366         RxRES   = (1 << 21),
 367         RxRUNT  = (1 << 20),
 368         RxCRC   = (1 << 19),
 369
 370         /* ChipCmdBits */
 371         StopReq         = 0x80,
 372         CmdReset        = 0x10,
 373         CmdRxEnb        = 0x08,
 374         CmdTxEnb        = 0x04,
 375         RxBufEmpty      = 0x01,
 376
 377         /* TXPoll register p.5 */
 378         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 379         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 380         FSWInt          = 0x01,         /* Forced software interrupt */
 381
 382         /* Cfg9346Bits */
 383         Cfg9346_Lock    = 0x00,
 384         Cfg9346_Unlock  = 0xc0,
 385
 386         /* rx_mode_bits */
 387         AcceptErr       = 0x20,
 388         AcceptRunt      = 0x10,
 389 #define RX_CONFIG_ACCEPT_ERR_MASK       0x30
 390         AcceptBroadcast = 0x08,
 391         AcceptMulticast = 0x04,
 392         AcceptMyPhys    = 0x02,
 393         AcceptAllPhys   = 0x01,
 394 #define RX_CONFIG_ACCEPT_OK_MASK        0x0f
 395 #define RX_CONFIG_ACCEPT_MASK           0x3f
 396
 397         /* TxConfigBits */
 398         TxInterFrameGapShift = 24,
 399         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 400
 401         /* Config1 register p.24 */
 402         LEDS1           = (1 << 7),
 403         LEDS0           = (1 << 6),
 404         Speed_down      = (1 << 4),
 405         MEMMAP          = (1 << 3),
 406         IOMAP           = (1 << 2),
 407         VPD             = (1 << 1),
 408         PMEnable        = (1 << 0),     /* Power Management Enable */
 409
 410         /* Config2 register p. 25 */
 411         ClkReqEn        = (1 << 7),     /* Clock Request Enable */
 412         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
 413         PCI_Clock_66MHz = 0x01,
 414         PCI_Clock_33MHz = 0x00,
 415
 416         /* Config3 register p.25 */
 417         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 418         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 419         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
 420         Rdy_to_L23      = (1 << 1),     /* L23 Enable */
 421         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 422
 423         /* Config4 register */
 424         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
 425
 426         /* Config5 register p.27 */
 427         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 428         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 429         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 430         Spi_en          = (1 << 3),
 431         LanWake         = (1 << 1),     /* LanWake enable/disable */
 432         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 433         ASPM_en         = (1 << 0),     /* ASPM enable */
 434
 435         /* CPlusCmd p.31 */
 436         EnableBist      = (1 << 15),    // 8168 8101
 437         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 438         EnAnaPLL        = (1 << 14),    // 8169
 439         Normal_mode     = (1 << 13),    // unused
 440         Force_half_dup  = (1 << 12),    // 8168 8101
 441         Force_rxflow_en = (1 << 11),    // 8168 8101
 442         Force_txflow_en = (1 << 10),    // 8168 8101
 443         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 444         ASF             = (1 << 8),     // 8168 8101
 445         PktCntrDisable  = (1 << 7),     // 8168 8101
 446         Mac_dbgo_sel    = 0x001c,       // 8168
 447         RxVlan          = (1 << 6),
 448         RxChkSum        = (1 << 5),
 449         PCIDAC          = (1 << 4),
 450         PCIMulRW        = (1 << 3),
 451 #define INTT_MASK       GENMASK(1, 0)
 452 #define CPCMD_MASK      (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
 453
 454         /* rtl8169_PHYstatus */
 455         TBI_Enable      = 0x80,
 456         TxFlowCtrl      = 0x40,
 457         RxFlowCtrl      = 0x20,
 458         _1000bpsF       = 0x10,
 459         _100bps         = 0x08,
 460         _10bps          = 0x04,
 461         LinkStatus      = 0x02,
 462         FullDup         = 0x01,
 463
 464         /* ResetCounterCommand */
 465         CounterReset    = 0x1,
 466
 467         /* DumpCounterCommand */
 468         CounterDump     = 0x8,
 469
 470         /* magic enable v2 */
 471         MagicPacket_v2  = (1 << 16),    /* Wake up when receives a Magic Packet */
 472 };
 473
 474 enum rtl_desc_bit {
 475         /* First doubleword. */
 476         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 477         RingEnd         = (1 << 30), /* End of descriptor ring */
 478         FirstFrag       = (1 << 29), /* First segment of a packet */
 479         LastFrag        = (1 << 28), /* Final segment of a packet */
 480 };
 481
 482 /* Generic case. */
 483 enum rtl_tx_desc_bit {
 484         /* First doubleword. */
 485         TD_LSO          = (1 << 27),            /* Large Send Offload */
 486 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 487
 488         /* Second doubleword. */
 489         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 490 };
 491
 492 /* 8169, 8168b and 810x except 8102e. */
 493 enum rtl_tx_desc_bit_0 {
 494         /* First doubleword. */
 495 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 496         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 497         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 498         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 499 };
 500
 501 /* 8102e, 8168c and beyond. */
 502 enum rtl_tx_desc_bit_1 {
 503         /* First doubleword. */
 504         TD1_GTSENV4     = (1 << 26),            /* Giant Send for IPv4 */
 505         TD1_GTSENV6     = (1 << 25),            /* Giant Send for IPv6 */
 506 #define GTTCPHO_SHIFT                   18
 507 #define GTTCPHO_MAX                     0x7f
 508
 509         /* Second doubleword. */
 510 #define TCPHO_SHIFT                     18
 511 #define TCPHO_MAX                       0x3ff
 512 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 513         TD1_IPv6_CS     = (1 << 28),            /* Calculate IPv6 checksum */
 514         TD1_IPv4_CS     = (1 << 29),            /* Calculate IPv4 checksum */
 515         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 516         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 517 };
 518
 519 enum rtl_rx_desc_bit {
 520         /* Rx private */
 521         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 522         PID0            = (1 << 17), /* Protocol ID bit 0/2 */
 523
 524 #define RxProtoUDP      (PID1)
 525 #define RxProtoTCP      (PID0)
 526 #define RxProtoIP       (PID1 | PID0)
 527 #define RxProtoMask     RxProtoIP
 528
 529         IPFail          = (1 << 16), /* IP checksum failed */
 530         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 531         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 532         RxVlanTag       = (1 << 16), /* VLAN tag available */
 533 };
 534
 535 #define RTL_GSO_MAX_SIZE_V1     32000
 536 #define RTL_GSO_MAX_SEGS_V1     24
 537 #define RTL_GSO_MAX_SIZE_V2     64000
 538 #define RTL_GSO_MAX_SEGS_V2     64
 539
 540 struct TxDesc {
 541         __le32 opts1;
 542         __le32 opts2;
 543         __le64 addr;
 544 };
 545
 546 struct RxDesc {
 547         __le32 opts1;
 548         __le32 opts2;
 549         __le64 addr;
 550 };
 551
 552 struct ring_info {
 553         struct sk_buff  *skb;
 554         u32             len;
 555 };
 556
 557 struct rtl8169_counters {
 558         __le64  tx_packets;
 559         __le64  rx_packets;
 560         __le64  tx_errors;
 561         __le32  rx_errors;
 562         __le16  rx_missed;
 563         __le16  align_errors;
 564         __le32  tx_one_collision;
 565         __le32  tx_multi_collision;
 566         __le64  rx_unicast;
 567         __le64  rx_broadcast;
 568         __le32  rx_multicast;
 569         __le16  tx_aborted;
 570         __le16  tx_underun;
 571 };
 572
 573 struct rtl8169_tc_offsets {
 574         bool    inited;
 575         __le64  tx_errors;
 576         __le32  tx_multi_collision;
 577         __le16  tx_aborted;
 578         __le16  rx_missed;
 579 };
 580
 581 enum rtl_flag {
 582         RTL_FLAG_TASK_ENABLED = 0,
 583         RTL_FLAG_TASK_RESET_PENDING,
 584         RTL_FLAG_MAX
 585 };
 586
 587 struct rtl8169_stats {
 588         u64                     packets;
 589         u64                     bytes;
 590         struct u64_stats_sync   syncp;
 591 };
 592
 593 struct rtl8169_private {
 594         void __iomem *mmio_addr;        /* memory map physical address */
 595         struct pci_dev *pci_dev;
 596         struct net_device *dev;
 597         struct phy_device *phydev;
 598         struct napi_struct napi;
 599         enum mac_version mac_version;
 600         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 601         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 602         u32 dirty_tx;
 603         struct rtl8169_stats rx_stats;
 604         struct rtl8169_stats tx_stats;
 605         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 606         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 607         dma_addr_t TxPhyAddr;
 608         dma_addr_t RxPhyAddr;
 609         struct page *Rx_databuff[NUM_RX_DESC];  /* Rx data buffers */
 610         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 611         u16 cp_cmd;
 612         u32 irq_mask;
 613         struct clk *clk;
 614
 615         struct {
 616                 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
 617                 struct work_struct work;
 618         } wk;
 619
 620         unsigned supports_gmii:1;
 621         unsigned aspm_manageable:1;
 622         dma_addr_t counters_phys_addr;
 623         struct rtl8169_counters *counters;
 624         struct rtl8169_tc_offsets tc_offset;
 625         u32 saved_wolopts;
 626         int eee_adv;
 627
 628         const char *fw_name;
 629         struct rtl_fw *rtl_fw;
 630
 631         u32 ocp_base;
 632 };
 633
 634 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp);
 635
 636 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 637 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 638 MODULE_SOFTDEP("pre: realtek");
 639 MODULE_LICENSE("GPL");
 640 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 641 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 642 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 643 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 644 MODULE_FIRMWARE(FIRMWARE_8168E_3);
 645 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 646 MODULE_FIRMWARE(FIRMWARE_8168F_1);
 647 MODULE_FIRMWARE(FIRMWARE_8168F_2);
 648 MODULE_FIRMWARE(FIRMWARE_8402_1);
 649 MODULE_FIRMWARE(FIRMWARE_8411_1);
 650 MODULE_FIRMWARE(FIRMWARE_8411_2);
 651 MODULE_FIRMWARE(FIRMWARE_8106E_1);
 652 MODULE_FIRMWARE(FIRMWARE_8106E_2);
 653 MODULE_FIRMWARE(FIRMWARE_8168G_2);
 654 MODULE_FIRMWARE(FIRMWARE_8168G_3);
 655 MODULE_FIRMWARE(FIRMWARE_8168H_1);
 656 MODULE_FIRMWARE(FIRMWARE_8168H_2);
 657 MODULE_FIRMWARE(FIRMWARE_8168FP_3);
 658 MODULE_FIRMWARE(FIRMWARE_8107E_1);
 659 MODULE_FIRMWARE(FIRMWARE_8107E_2);
 660 MODULE_FIRMWARE(FIRMWARE_8125A_3);
 661 MODULE_FIRMWARE(FIRMWARE_8125B_2);
 662
 663 static inline struct device *tp_to_dev(struct rtl8169_private *tp)
 664 {
 665         return &tp->pci_dev->dev;
 666 }
 667
 668 static void rtl_lock_config_regs(struct rtl8169_private *tp)
 669 {
 670         RTL_W8(tp, Cfg9346, Cfg9346_Lock);
 671 }
 672
 673 static void rtl_unlock_config_regs(struct rtl8169_private *tp)
 674 {
 675         RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
 676 }
 677
 678 static void rtl_pci_commit(struct rtl8169_private *tp)
 679 {
 680         /* Read an arbitrary register to commit a preceding PCI write */
 681         RTL_R8(tp, ChipCmd);
 682 }
 683
 684 static bool rtl_is_8125(struct rtl8169_private *tp)
 685 {
 686         return tp->mac_version >= RTL_GIGA_MAC_VER_60;
 687 }
 688
 689 static bool rtl_is_8168evl_up(struct rtl8169_private *tp)
 690 {
 691         return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
 692                tp->mac_version != RTL_GIGA_MAC_VER_39 &&
 693                tp->mac_version <= RTL_GIGA_MAC_VER_52;
 694 }
 695
 696 static bool rtl_supports_eee(struct rtl8169_private *tp)
 697 {
 698         return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
 699                tp->mac_version != RTL_GIGA_MAC_VER_37 &&
 700                tp->mac_version != RTL_GIGA_MAC_VER_39;
 701 }
 702
 703 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg)
 704 {
 705         int i;
 706
 707         for (i = 0; i < ETH_ALEN; i++)
 708                 mac[i] = RTL_R8(tp, reg + i);
 709 }
 710
 711 struct rtl_cond {
 712         bool (*check)(struct rtl8169_private *);
 713         const char *msg;
 714 };
 715
 716 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
 717                           unsigned long usecs, int n, bool high)
 718 {
 719         int i;
 720
 721         for (i = 0; i < n; i++) {
 722                 if (c->check(tp) == high)
 723                         return true;
 724                 fsleep(usecs);
 725         }
 726
 727         if (net_ratelimit())
 728                 netdev_err(tp->dev, "%s == %d (loop: %d, delay: %lu).\n",
 729                            c->msg, !high, n, usecs);
 730         return false;
 731 }
 732
 733 static bool rtl_loop_wait_high(struct rtl8169_private *tp,
 734                                const struct rtl_cond *c,
 735                                unsigned long d, int n)
 736 {
 737         return rtl_loop_wait(tp, c, d, n, true);
 738 }
 739
 740 static bool rtl_loop_wait_low(struct rtl8169_private *tp,
 741                               const struct rtl_cond *c,
 742                               unsigned long d, int n)
 743 {
 744         return rtl_loop_wait(tp, c, d, n, false);
 745 }
 746
 747 #define DECLARE_RTL_COND(name)                          \
 748 static bool name ## _check(struct rtl8169_private *);   \
 749                                                         \
 750 static const struct rtl_cond name = {                   \
 751         .check  = name ## _check,                       \
 752         .msg    = #name                                 \
 753 };                                                      \
 754                                                         \
 755 static bool name ## _check(struct rtl8169_private *tp)
 756
 757 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
 758 {
 759         if (reg & 0xffff0001) {
 760                 if (net_ratelimit())
 761                         netdev_err(tp->dev, "Invalid ocp reg %x!\n", reg);
 762                 return true;
 763         }
 764         return false;
 765 }
 766
 767 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
 768 {
 769         return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
 770 }
 771
 772 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 773 {
 774         if (rtl_ocp_reg_failure(tp, reg))
 775                 return;
 776
 777         RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
 778
 779         rtl_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
 780 }
 781
 782 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
 783 {
 784         if (rtl_ocp_reg_failure(tp, reg))
 785                 return 0;
 786
 787         RTL_W32(tp, GPHY_OCP, reg << 15);
 788
 789         return rtl_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
 790                 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT;
 791 }
 792
 793 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 794 {
 795         if (rtl_ocp_reg_failure(tp, reg))
 796                 return;
 797
 798         RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
 799 }
 800
 801 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
 802 {
 803         if (rtl_ocp_reg_failure(tp, reg))
 804                 return 0;
 805
 806         RTL_W32(tp, OCPDR, reg << 15);
 807
 808         return RTL_R32(tp, OCPDR);
 809 }
 810
 811 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask,
 812                                  u16 set)
 813 {
 814         u16 data = r8168_mac_ocp_read(tp, reg);
 815
 816         r8168_mac_ocp_write(tp, reg, (data & ~mask) | set);
 817 }
 818
 819 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
 820 {
 821         if (reg == 0x1f) {
 822                 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
 823                 return;
 824         }
 825
 826         if (tp->ocp_base != OCP_STD_PHY_BASE)
 827                 reg -= 0x10;
 828
 829         r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
 830 }
 831
 832 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
 833 {
 834         if (reg == 0x1f)
 835                 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4;
 836
 837         if (tp->ocp_base != OCP_STD_PHY_BASE)
 838                 reg -= 0x10;
 839
 840         return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
 841 }
 842
 843 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
 844 {
 845         if (reg == 0x1f) {
 846                 tp->ocp_base = value << 4;
 847                 return;
 848         }
 849
 850         r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
 851 }
 852
 853 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
 854 {
 855         return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
 856 }
 857
 858 DECLARE_RTL_COND(rtl_phyar_cond)
 859 {
 860         return RTL_R32(tp, PHYAR) & 0x80000000;
 861 }
 862
 863 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
 864 {
 865         RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
 866
 867         rtl_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
 868         /*
 869          * According to hardware specs a 20us delay is required after write
 870          * complete indication, but before sending next command.
 871          */
 872         udelay(20);
 873 }
 874
 875 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
 876 {
 877         int value;
 878
 879         RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
 880
 881         value = rtl_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
 882                 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT;
 883
 884         /*
 885          * According to hardware specs a 20us delay is required after read
 886          * complete indication, but before sending next command.
 887          */
 888         udelay(20);
 889
 890         return value;
 891 }
 892
 893 DECLARE_RTL_COND(rtl_ocpar_cond)
 894 {
 895         return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
 896 }
 897
 898 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
 899 {
 900         RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
 901         RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
 902         RTL_W32(tp, EPHY_RXER_NUM, 0);
 903
 904         rtl_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
 905 }
 906
 907 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
 908 {
 909         r8168dp_1_mdio_access(tp, reg,
 910                               OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
 911 }
 912
 913 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
 914 {
 915         r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
 916
 917         mdelay(1);
 918         RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
 919         RTL_W32(tp, EPHY_RXER_NUM, 0);
 920
 921         return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
 922                 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : -ETIMEDOUT;
 923 }
 924
 925 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
 926
 927 static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
 928 {
 929         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
 930 }
 931
 932 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
 933 {
 934         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
 935 }
 936
 937 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
 938 {
 939         r8168dp_2_mdio_start(tp);
 940
 941         r8169_mdio_write(tp, reg, value);
 942
 943         r8168dp_2_mdio_stop(tp);
 944 }
 945
 946 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
 947 {
 948         int value;
 949
 950         /* Work around issue with chip reporting wrong PHY ID */
 951         if (reg == MII_PHYSID2)
 952                 return 0xc912;
 953
 954         r8168dp_2_mdio_start(tp);
 955
 956         value = r8169_mdio_read(tp, reg);
 957
 958         r8168dp_2_mdio_stop(tp);
 959
 960         return value;
 961 }
 962
 963 static void rtl_writephy(struct rtl8169_private *tp, int location, int val)
 964 {
 965         switch (tp->mac_version) {
 966         case RTL_GIGA_MAC_VER_27:
 967                 r8168dp_1_mdio_write(tp, location, val);
 968                 break;
 969         case RTL_GIGA_MAC_VER_28:
 970         case RTL_GIGA_MAC_VER_31:
 971                 r8168dp_2_mdio_write(tp, location, val);
 972                 break;
 973         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
 974                 r8168g_mdio_write(tp, location, val);
 975                 break;
 976         default:
 977                 r8169_mdio_write(tp, location, val);
 978                 break;
 979         }
 980 }
 981
 982 static int rtl_readphy(struct rtl8169_private *tp, int location)
 983 {
 984         switch (tp->mac_version) {
 985         case RTL_GIGA_MAC_VER_27:
 986                 return r8168dp_1_mdio_read(tp, location);
 987         case RTL_GIGA_MAC_VER_28:
 988         case RTL_GIGA_MAC_VER_31:
 989                 return r8168dp_2_mdio_read(tp, location);
 990         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
 991                 return r8168g_mdio_read(tp, location);
 992         default:
 993                 return r8169_mdio_read(tp, location);
 994         }
 995 }
 996
 997 DECLARE_RTL_COND(rtl_ephyar_cond)
 998 {
 999         return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1000 }
1001
1002 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1003 {
1004         RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1005                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1006
1007         rtl_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1008
1009         udelay(10);
1010 }
1011
1012 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1013 {
1014         RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1015
1016         return rtl_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1017                 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1018 }
1019
1020 static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type)
1021 {
1022         /* based on RTL8168FP_OOBMAC_BASE in vendor driver */
1023         if (tp->mac_version == RTL_GIGA_MAC_VER_52 && type == ERIAR_OOB)
1024                 *cmd |= 0x7f0 << 18;
1025 }
1026
1027 DECLARE_RTL_COND(rtl_eriar_cond)
1028 {
1029         return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
1030 }
1031
1032 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1033                            u32 val, int type)
1034 {
1035         u32 cmd = ERIAR_WRITE_CMD | type | mask | addr;
1036
1037         BUG_ON((addr & 3) || (mask == 0));
1038         RTL_W32(tp, ERIDR, val);
1039         r8168fp_adjust_ocp_cmd(tp, &cmd, type);
1040         RTL_W32(tp, ERIAR, cmd);
1041
1042         rtl_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1043 }
1044
1045 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1046                           u32 val)
1047 {
1048         _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC);
1049 }
1050
1051 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1052 {
1053         u32 cmd = ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr;
1054
1055         r8168fp_adjust_ocp_cmd(tp, &cmd, type);
1056         RTL_W32(tp, ERIAR, cmd);
1057
1058         return rtl_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1059                 RTL_R32(tp, ERIDR) : ~0;
1060 }
1061
1062 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr)
1063 {
1064         return _rtl_eri_read(tp, addr, ERIAR_EXGMAC);
1065 }
1066
1067 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 p, u32 m)
1068 {
1069         u32 val = rtl_eri_read(tp, addr);
1070
1071         rtl_eri_write(tp, addr, ERIAR_MASK_1111, (val & ~m) | p);
1072 }
1073
1074 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 p)
1075 {
1076         rtl_w0w1_eri(tp, addr, p, 0);
1077 }
1078
1079 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 m)
1080 {
1081         rtl_w0w1_eri(tp, addr, 0, m);
1082 }
1083
1084 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u16 reg)
1085 {
1086         RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff));
1087         return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1088                 RTL_R32(tp, OCPDR) : ~0;
1089 }
1090
1091 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u16 reg)
1092 {
1093         return _rtl_eri_read(tp, reg, ERIAR_OOB);
1094 }
1095
1096 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1097                               u32 data)
1098 {
1099         RTL_W32(tp, OCPDR, data);
1100         RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1101         rtl_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1102 }
1103
1104 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1105                               u32 data)
1106 {
1107         _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1108                        data, ERIAR_OOB);
1109 }
1110
1111 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd)
1112 {
1113         rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd);
1114
1115         r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001);
1116 }
1117
1118 #define OOB_CMD_RESET           0x00
1119 #define OOB_CMD_DRIVER_START    0x05
1120 #define OOB_CMD_DRIVER_STOP     0x06
1121
1122 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1123 {
1124         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1125 }
1126
1127 DECLARE_RTL_COND(rtl_dp_ocp_read_cond)
1128 {
1129         u16 reg;
1130
1131         reg = rtl8168_get_ocp_reg(tp);
1132
1133         return r8168dp_ocp_read(tp, reg) & 0x00000800;
1134 }
1135
1136 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1137 {
1138         return r8168ep_ocp_read(tp, 0x124) & 0x00000001;
1139 }
1140
1141 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1142 {
1143         return RTL_R8(tp, IBISR0) & 0x20;
1144 }
1145
1146 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1147 {
1148         RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1149         rtl_loop_wait_high(tp, &rtl_ocp_tx_cond, 50000, 2000);
1150         RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1151         RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1152 }
1153
1154 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1155 {
1156         r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START);
1157         rtl_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10000, 10);
1158 }
1159
1160 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1161 {
1162         r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1163         r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01);
1164         rtl_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10000, 10);
1165 }
1166
1167 static void rtl8168_driver_start(struct rtl8169_private *tp)
1168 {
1169         switch (tp->mac_version) {
1170         case RTL_GIGA_MAC_VER_27:
1171         case RTL_GIGA_MAC_VER_28:
1172         case RTL_GIGA_MAC_VER_31:
1173                 rtl8168dp_driver_start(tp);
1174                 break;
1175         case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52:
1176                 rtl8168ep_driver_start(tp);
1177                 break;
1178         default:
1179                 BUG();
1180                 break;
1181         }
1182 }
1183
1184 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1185 {
1186         r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1187         rtl_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10000, 10);
1188 }
1189
1190 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1191 {
1192         rtl8168ep_stop_cmac(tp);
1193         r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1194         r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01);
1195         rtl_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10000, 10);
1196 }
1197
1198 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1199 {
1200         switch (tp->mac_version) {
1201         case RTL_GIGA_MAC_VER_27:
1202         case RTL_GIGA_MAC_VER_28:
1203         case RTL_GIGA_MAC_VER_31:
1204                 rtl8168dp_driver_stop(tp);
1205                 break;
1206         case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52:
1207                 rtl8168ep_driver_stop(tp);
1208                 break;
1209         default:
1210                 BUG();
1211                 break;
1212         }
1213 }
1214
1215 static bool r8168dp_check_dash(struct rtl8169_private *tp)
1216 {
1217         u16 reg = rtl8168_get_ocp_reg(tp);
1218
1219         return !!(r8168dp_ocp_read(tp, reg) & 0x00008000);
1220 }
1221
1222 static bool r8168ep_check_dash(struct rtl8169_private *tp)
1223 {
1224         return r8168ep_ocp_read(tp, 0x128) & 0x00000001;
1225 }
1226
1227 static bool r8168_check_dash(struct rtl8169_private *tp)
1228 {
1229         switch (tp->mac_version) {
1230         case RTL_GIGA_MAC_VER_27:
1231         case RTL_GIGA_MAC_VER_28:
1232         case RTL_GIGA_MAC_VER_31:
1233                 return r8168dp_check_dash(tp);
1234         case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52:
1235                 return r8168ep_check_dash(tp);
1236         default:
1237                 return false;
1238         }
1239 }
1240
1241 static void rtl_reset_packet_filter(struct rtl8169_private *tp)
1242 {
1243         rtl_eri_clear_bits(tp, 0xdc, BIT(0));
1244         rtl_eri_set_bits(tp, 0xdc, BIT(0));
1245 }
1246
1247 DECLARE_RTL_COND(rtl_efusear_cond)
1248 {
1249         return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1250 }
1251
1252 u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1253 {
1254         RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1255
1256         return rtl_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1257                 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1258 }
1259
1260 static u32 rtl_get_events(struct rtl8169_private *tp)
1261 {
1262         if (rtl_is_8125(tp))
1263                 return RTL_R32(tp, IntrStatus_8125);
1264         else
1265                 return RTL_R16(tp, IntrStatus);
1266 }
1267
1268 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits)
1269 {
1270         if (rtl_is_8125(tp))
1271                 RTL_W32(tp, IntrStatus_8125, bits);
1272         else
1273                 RTL_W16(tp, IntrStatus, bits);
1274 }
1275
1276 static void rtl_irq_disable(struct rtl8169_private *tp)
1277 {
1278         if (rtl_is_8125(tp))
1279                 RTL_W32(tp, IntrMask_8125, 0);
1280         else
1281                 RTL_W16(tp, IntrMask, 0);
1282 }
1283
1284 static void rtl_irq_enable(struct rtl8169_private *tp)
1285 {
1286         if (rtl_is_8125(tp))
1287                 RTL_W32(tp, IntrMask_8125, tp->irq_mask);
1288         else
1289                 RTL_W16(tp, IntrMask, tp->irq_mask);
1290 }
1291
1292 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1293 {
1294         rtl_irq_disable(tp);
1295         rtl_ack_events(tp, 0xffffffff);
1296         rtl_pci_commit(tp);
1297 }
1298
1299 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1300 {
1301         struct phy_device *phydev = tp->phydev;
1302
1303         if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1304             tp->mac_version == RTL_GIGA_MAC_VER_38) {
1305                 if (phydev->speed == SPEED_1000) {
1306                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1307                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1308                 } else if (phydev->speed == SPEED_100) {
1309                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1310                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1311                 } else {
1312                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1313                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1314                 }
1315                 rtl_reset_packet_filter(tp);
1316         } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1317                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
1318                 if (phydev->speed == SPEED_1000) {
1319                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1320                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1321                 } else {
1322                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1323                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1324                 }
1325         } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1326                 if (phydev->speed == SPEED_10) {
1327                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02);
1328                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a);
1329                 } else {
1330                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
1331                 }
1332         }
1333 }
1334
1335 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1336
1337 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1338 {
1339         struct rtl8169_private *tp = netdev_priv(dev);
1340
1341         wol->supported = WAKE_ANY;
1342         wol->wolopts = tp->saved_wolopts;
1343 }
1344
1345 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1346 {
1347         static const struct {
1348                 u32 opt;
1349                 u16 reg;
1350                 u8  mask;
1351         } cfg[] = {
1352                 { WAKE_PHY,   Config3, LinkUp },
1353                 { WAKE_UCAST, Config5, UWF },
1354                 { WAKE_BCAST, Config5, BWF },
1355                 { WAKE_MCAST, Config5, MWF },
1356                 { WAKE_ANY,   Config5, LanWake },
1357                 { WAKE_MAGIC, Config3, MagicPacket }
1358         };
1359         unsigned int i, tmp = ARRAY_SIZE(cfg);
1360         u8 options;
1361
1362         rtl_unlock_config_regs(tp);
1363
1364         if (rtl_is_8168evl_up(tp)) {
1365                 tmp--;
1366                 if (wolopts & WAKE_MAGIC)
1367                         rtl_eri_set_bits(tp, 0x0dc, MagicPacket_v2);
1368                 else
1369                         rtl_eri_clear_bits(tp, 0x0dc, MagicPacket_v2);
1370         } else if (rtl_is_8125(tp)) {
1371                 tmp--;
1372                 if (wolopts & WAKE_MAGIC)
1373                         r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0));
1374                 else
1375                         r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0);
1376         }
1377
1378         for (i = 0; i < tmp; i++) {
1379                 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
1380                 if (wolopts & cfg[i].opt)
1381                         options |= cfg[i].mask;
1382                 RTL_W8(tp, cfg[i].reg, options);
1383         }
1384
1385         switch (tp->mac_version) {
1386         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
1387                 options = RTL_R8(tp, Config1) & ~PMEnable;
1388                 if (wolopts)
1389                         options |= PMEnable;
1390                 RTL_W8(tp, Config1, options);
1391                 break;
1392         case RTL_GIGA_MAC_VER_34:
1393         case RTL_GIGA_MAC_VER_37:
1394         case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63:
1395                 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
1396                 if (wolopts)
1397                         options |= PME_SIGNAL;
1398                 RTL_W8(tp, Config2, options);
1399                 break;
1400         default:
1401                 break;
1402         }
1403
1404         rtl_lock_config_regs(tp);
1405
1406         device_set_wakeup_enable(tp_to_dev(tp), wolopts);
1407         tp->dev->wol_enabled = wolopts ? 1 : 0;
1408 }
1409
1410 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1411 {
1412         struct rtl8169_private *tp = netdev_priv(dev);
1413
1414         if (wol->wolopts & ~WAKE_ANY)
1415                 return -EINVAL;
1416
1417         tp->saved_wolopts = wol->wolopts;
1418         __rtl8169_set_wol(tp, tp->saved_wolopts);
1419
1420         return 0;
1421 }
1422
1423 static void rtl8169_get_drvinfo(struct net_device *dev,
1424                                 struct ethtool_drvinfo *info)
1425 {
1426         struct rtl8169_private *tp = netdev_priv(dev);
1427         struct rtl_fw *rtl_fw = tp->rtl_fw;
1428
1429         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1430         strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1431         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1432         if (rtl_fw)
1433                 strlcpy(info->fw_version, rtl_fw->version,
1434                         sizeof(info->fw_version));
1435 }
1436
1437 static int rtl8169_get_regs_len(struct net_device *dev)
1438 {
1439         return R8169_REGS_SIZE;
1440 }
1441
1442 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1443         netdev_features_t features)
1444 {
1445         struct rtl8169_private *tp = netdev_priv(dev);
1446
1447         if (dev->mtu > TD_MSS_MAX)
1448                 features &= ~NETIF_F_ALL_TSO;
1449
1450         if (dev->mtu > ETH_DATA_LEN &&
1451             tp->mac_version > RTL_GIGA_MAC_VER_06)
1452                 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_ALL_TSO);
1453
1454         return features;
1455 }
1456
1457 static void rtl_set_rx_config_features(struct rtl8169_private *tp,
1458                                        netdev_features_t features)
1459 {
1460         u32 rx_config = RTL_R32(tp, RxConfig);
1461
1462         if (features & NETIF_F_RXALL)
1463                 rx_config |= RX_CONFIG_ACCEPT_ERR_MASK;
1464         else
1465                 rx_config &= ~RX_CONFIG_ACCEPT_ERR_MASK;
1466
1467         if (rtl_is_8125(tp)) {
1468                 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1469                         rx_config |= RX_VLAN_8125;
1470                 else
1471                         rx_config &= ~RX_VLAN_8125;
1472         }
1473
1474         RTL_W32(tp, RxConfig, rx_config);
1475 }
1476
1477 static int rtl8169_set_features(struct net_device *dev,
1478                                 netdev_features_t features)
1479 {
1480         struct rtl8169_private *tp = netdev_priv(dev);
1481
1482         rtl_set_rx_config_features(tp, features);
1483
1484         if (features & NETIF_F_RXCSUM)
1485                 tp->cp_cmd |= RxChkSum;
1486         else
1487                 tp->cp_cmd &= ~RxChkSum;
1488
1489         if (!rtl_is_8125(tp)) {
1490                 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1491                         tp->cp_cmd |= RxVlan;
1492                 else
1493                         tp->cp_cmd &= ~RxVlan;
1494         }
1495
1496         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1497         rtl_pci_commit(tp);
1498
1499         return 0;
1500 }
1501
1502 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1503 {
1504         return (skb_vlan_tag_present(skb)) ?
1505                 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1506 }
1507
1508 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1509 {
1510         u32 opts2 = le32_to_cpu(desc->opts2);
1511
1512         if (opts2 & RxVlanTag)
1513                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1514 }
1515
1516 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1517                              void *p)
1518 {
1519         struct rtl8169_private *tp = netdev_priv(dev);
1520         u32 __iomem *data = tp->mmio_addr;
1521         u32 *dw = p;
1522         int i;
1523
1524         for (i = 0; i < R8169_REGS_SIZE; i += 4)
1525                 memcpy_fromio(dw++, data++, 4);
1526 }
1527
1528 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1529         "tx_packets",
1530         "rx_packets",
1531         "tx_errors",
1532         "rx_errors",
1533         "rx_missed",
1534         "align_errors",
1535         "tx_single_collisions",
1536         "tx_multi_collisions",
1537         "unicast",
1538         "broadcast",
1539         "multicast",
1540         "tx_aborted",
1541         "tx_underrun",
1542 };
1543
1544 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1545 {
1546         switch (sset) {
1547         case ETH_SS_STATS:
1548                 return ARRAY_SIZE(rtl8169_gstrings);
1549         default:
1550                 return -EOPNOTSUPP;
1551         }
1552 }
1553
1554 DECLARE_RTL_COND(rtl_counters_cond)
1555 {
1556         return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
1557 }
1558
1559 static void rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
1560 {
1561         dma_addr_t paddr = tp->counters_phys_addr;
1562         u32 cmd;
1563
1564         RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
1565         rtl_pci_commit(tp);
1566         cmd = (u64)paddr & DMA_BIT_MASK(32);
1567         RTL_W32(tp, CounterAddrLow, cmd);
1568         RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
1569
1570         rtl_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
1571 }
1572
1573 static void rtl8169_reset_counters(struct rtl8169_private *tp)
1574 {
1575         /*
1576          * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
1577          * tally counters.
1578          */
1579         if (tp->mac_version >= RTL_GIGA_MAC_VER_19)
1580                 rtl8169_do_counters(tp, CounterReset);
1581 }
1582
1583 static void rtl8169_update_counters(struct rtl8169_private *tp)
1584 {
1585         u8 val = RTL_R8(tp, ChipCmd);
1586
1587         /*
1588          * Some chips are unable to dump tally counters when the receiver
1589          * is disabled. If 0xff chip may be in a PCI power-save state.
1590          */
1591         if (val & CmdRxEnb && val != 0xff)
1592                 rtl8169_do_counters(tp, CounterDump);
1593 }
1594
1595 static void rtl8169_init_counter_offsets(struct rtl8169_private *tp)
1596 {
1597         struct rtl8169_counters *counters = tp->counters;
1598
1599         /*
1600          * rtl8169_init_counter_offsets is called from rtl_open.  On chip
1601          * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1602          * reset by a power cycle, while the counter values collected by the
1603          * driver are reset at every driver unload/load cycle.
1604          *
1605          * To make sure the HW values returned by @get_stats64 match the SW
1606          * values, we collect the initial values at first open(*) and use them
1607          * as offsets to normalize the values returned by @get_stats64.
1608          *
1609          * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1610          * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1611          * set at open time by rtl_hw_start.
1612          */
1613
1614         if (tp->tc_offset.inited)
1615                 return;
1616
1617         rtl8169_reset_counters(tp);
1618         rtl8169_update_counters(tp);
1619
1620         tp->tc_offset.tx_errors = counters->tx_errors;
1621         tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1622         tp->tc_offset.tx_aborted = counters->tx_aborted;
1623         tp->tc_offset.rx_missed = counters->rx_missed;
1624         tp->tc_offset.inited = true;
1625 }
1626
1627 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1628                                       struct ethtool_stats *stats, u64 *data)
1629 {
1630         struct rtl8169_private *tp = netdev_priv(dev);
1631         struct rtl8169_counters *counters;
1632
1633         counters = tp->counters;
1634         rtl8169_update_counters(tp);
1635
1636         data[0] = le64_to_cpu(counters->tx_packets);
1637         data[1] = le64_to_cpu(counters->rx_packets);
1638         data[2] = le64_to_cpu(counters->tx_errors);
1639         data[3] = le32_to_cpu(counters->rx_errors);
1640         data[4] = le16_to_cpu(counters->rx_missed);
1641         data[5] = le16_to_cpu(counters->align_errors);
1642         data[6] = le32_to_cpu(counters->tx_one_collision);
1643         data[7] = le32_to_cpu(counters->tx_multi_collision);
1644         data[8] = le64_to_cpu(counters->rx_unicast);
1645         data[9] = le64_to_cpu(counters->rx_broadcast);
1646         data[10] = le32_to_cpu(counters->rx_multicast);
1647         data[11] = le16_to_cpu(counters->tx_aborted);
1648         data[12] = le16_to_cpu(counters->tx_underun);
1649 }
1650
1651 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1652 {
1653         switch(stringset) {
1654         case ETH_SS_STATS:
1655                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1656                 break;
1657         }
1658 }
1659
1660 /*
1661  * Interrupt coalescing
1662  *
1663  * > 1 - the availability of the IntrMitigate (0xe2) register through the
1664  * >     8169, 8168 and 810x line of chipsets
1665  *
1666  * 8169, 8168, and 8136(810x) serial chipsets support it.
1667  *
1668  * > 2 - the Tx timer unit at gigabit speed
1669  *
1670  * The unit of the timer depends on both the speed and the setting of CPlusCmd
1671  * (0xe0) bit 1 and bit 0.
1672  *
1673  * For 8169
1674  * bit[1:0] \ speed        1000M           100M            10M
1675  * 0 0                     320ns           2.56us          40.96us
1676  * 0 1                     2.56us          20.48us         327.7us
1677  * 1 0                     5.12us          40.96us         655.4us
1678  * 1 1                     10.24us         81.92us         1.31ms
1679  *
1680  * For the other
1681  * bit[1:0] \ speed        1000M           100M            10M
1682  * 0 0                     5us             2.56us          40.96us
1683  * 0 1                     40us            20.48us         327.7us
1684  * 1 0                     80us            40.96us         655.4us
1685  * 1 1                     160us           81.92us         1.31ms
1686  */
1687
1688 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
1689 struct rtl_coalesce_info {
1690         u32 speed;
1691         u32 scale_nsecs[4];
1692 };
1693
1694 /* produce array with base delay *1, *8, *8*2, *8*2*2 */
1695 #define COALESCE_DELAY(d) { (d), 8 * (d), 16 * (d), 32 * (d) }
1696
1697 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1698         { SPEED_1000,   COALESCE_DELAY(320) },
1699         { SPEED_100,    COALESCE_DELAY(2560) },
1700         { SPEED_10,     COALESCE_DELAY(40960) },
1701         { 0 },
1702 };
1703
1704 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1705         { SPEED_1000,   COALESCE_DELAY(5000) },
1706         { SPEED_100,    COALESCE_DELAY(2560) },
1707         { SPEED_10,     COALESCE_DELAY(40960) },
1708         { 0 },
1709 };
1710 #undef COALESCE_DELAY
1711
1712 /* get rx/tx scale vector corresponding to current speed */
1713 static const struct rtl_coalesce_info *
1714 rtl_coalesce_info(struct rtl8169_private *tp)
1715 {
1716         const struct rtl_coalesce_info *ci;
1717
1718         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1719                 ci = rtl_coalesce_info_8169;
1720         else
1721                 ci = rtl_coalesce_info_8168_8136;
1722
1723         /* if speed is unknown assume highest one */
1724         if (tp->phydev->speed == SPEED_UNKNOWN)
1725                 return ci;
1726
1727         for (; ci->speed; ci++) {
1728                 if (tp->phydev->speed == ci->speed)
1729                         return ci;
1730         }
1731
1732         return ERR_PTR(-ELNRNG);
1733 }
1734
1735 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1736 {
1737         struct rtl8169_private *tp = netdev_priv(dev);
1738         const struct rtl_coalesce_info *ci;
1739         u32 scale, c_us, c_fr;
1740         u16 intrmit;
1741
1742         if (rtl_is_8125(tp))
1743                 return -EOPNOTSUPP;
1744
1745         memset(ec, 0, sizeof(*ec));
1746
1747         /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1748         ci = rtl_coalesce_info(tp);
1749         if (IS_ERR(ci))
1750                 return PTR_ERR(ci);
1751
1752         scale = ci->scale_nsecs[tp->cp_cmd & INTT_MASK];
1753
1754         intrmit = RTL_R16(tp, IntrMitigate);
1755
1756         c_us = FIELD_GET(RTL_COALESCE_TX_USECS, intrmit);
1757         ec->tx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000);
1758
1759         c_fr = FIELD_GET(RTL_COALESCE_TX_FRAMES, intrmit);
1760         /* ethtool_coalesce states usecs and max_frames must not both be 0 */
1761         ec->tx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1;
1762
1763         c_us = FIELD_GET(RTL_COALESCE_RX_USECS, intrmit);
1764         ec->rx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000);
1765
1766         c_fr = FIELD_GET(RTL_COALESCE_RX_FRAMES, intrmit);
1767         ec->rx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1;
1768
1769         return 0;
1770 }
1771
1772 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, usec) */
1773 static int rtl_coalesce_choose_scale(struct rtl8169_private *tp, u32 usec,
1774                                      u16 *cp01)
1775 {
1776         const struct rtl_coalesce_info *ci;
1777         u16 i;
1778
1779         ci = rtl_coalesce_info(tp);
1780         if (IS_ERR(ci))
1781                 return PTR_ERR(ci);
1782
1783         for (i = 0; i < 4; i++) {
1784                 if (usec <= ci->scale_nsecs[i] * RTL_COALESCE_T_MAX / 1000U) {
1785                         *cp01 = i;
1786                         return ci->scale_nsecs[i];
1787                 }
1788         }
1789
1790         return -ERANGE;
1791 }
1792
1793 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1794 {
1795         struct rtl8169_private *tp = netdev_priv(dev);
1796         u32 tx_fr = ec->tx_max_coalesced_frames;
1797         u32 rx_fr = ec->rx_max_coalesced_frames;
1798         u32 coal_usec_max, units;
1799         u16 w = 0, cp01 = 0;
1800         int scale;
1801
1802         if (rtl_is_8125(tp))
1803                 return -EOPNOTSUPP;
1804
1805         if (rx_fr > RTL_COALESCE_FRAME_MAX || tx_fr > RTL_COALESCE_FRAME_MAX)
1806                 return -ERANGE;
1807
1808         coal_usec_max = max(ec->rx_coalesce_usecs, ec->tx_coalesce_usecs);
1809         scale = rtl_coalesce_choose_scale(tp, coal_usec_max, &cp01);
1810         if (scale < 0)
1811                 return scale;
1812
1813         /* Accept max_frames=1 we returned in rtl_get_coalesce. Accept it
1814          * not only when usecs=0 because of e.g. the following scenario:
1815          *
1816          * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
1817          * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
1818          * - then user does `ethtool -C eth0 rx-usecs 100`
1819          *
1820          * Since ethtool sends to kernel whole ethtool_coalesce settings,
1821          * if we want to ignore rx_frames then it has to be set to 0.
1822          */
1823         if (rx_fr == 1)
1824                 rx_fr = 0;
1825         if (tx_fr == 1)
1826                 tx_fr = 0;
1827
1828         /* HW requires time limit to be set if frame limit is set */
1829         if ((tx_fr && !ec->tx_coalesce_usecs) ||
1830             (rx_fr && !ec->rx_coalesce_usecs))
1831                 return -EINVAL;
1832
1833         w |= FIELD_PREP(RTL_COALESCE_TX_FRAMES, DIV_ROUND_UP(tx_fr, 4));
1834         w |= FIELD_PREP(RTL_COALESCE_RX_FRAMES, DIV_ROUND_UP(rx_fr, 4));
1835
1836         units = DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000U, scale);
1837         w |= FIELD_PREP(RTL_COALESCE_TX_USECS, units);
1838         units = DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000U, scale);
1839         w |= FIELD_PREP(RTL_COALESCE_RX_USECS, units);
1840
1841         RTL_W16(tp, IntrMitigate, w);
1842
1843         /* Meaning of PktCntrDisable bit changed from RTL8168e-vl */
1844         if (rtl_is_8168evl_up(tp)) {
1845                 if (!rx_fr && !tx_fr)
1846                         /* disable packet counter */
1847                         tp->cp_cmd |= PktCntrDisable;
1848                 else
1849                         tp->cp_cmd &= ~PktCntrDisable;
1850         }
1851
1852         tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
1853         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1854         rtl_pci_commit(tp);
1855
1856         return 0;
1857 }
1858
1859 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data)
1860 {
1861         struct rtl8169_private *tp = netdev_priv(dev);
1862
1863         if (!rtl_supports_eee(tp))
1864                 return -EOPNOTSUPP;
1865
1866         return phy_ethtool_get_eee(tp->phydev, data);
1867 }
1868
1869 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data)
1870 {
1871         struct rtl8169_private *tp = netdev_priv(dev);
1872         int ret;
1873
1874         if (!rtl_supports_eee(tp))
1875                 return -EOPNOTSUPP;
1876
1877         ret = phy_ethtool_set_eee(tp->phydev, data);
1878
1879         if (!ret)
1880                 tp->eee_adv = phy_read_mmd(dev->phydev, MDIO_MMD_AN,
1881                                            MDIO_AN_EEE_ADV);
1882         return ret;
1883 }
1884
1885 static const struct ethtool_ops rtl8169_ethtool_ops = {
1886         .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
1887                                      ETHTOOL_COALESCE_MAX_FRAMES,
1888         .get_drvinfo            = rtl8169_get_drvinfo,
1889         .get_regs_len           = rtl8169_get_regs_len,
1890         .get_link               = ethtool_op_get_link,
1891         .get_coalesce           = rtl_get_coalesce,
1892         .set_coalesce           = rtl_set_coalesce,
1893         .get_regs               = rtl8169_get_regs,
1894         .get_wol                = rtl8169_get_wol,
1895         .set_wol                = rtl8169_set_wol,
1896         .get_strings            = rtl8169_get_strings,
1897         .get_sset_count         = rtl8169_get_sset_count,
1898         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
1899         .get_ts_info            = ethtool_op_get_ts_info,
1900         .nway_reset             = phy_ethtool_nway_reset,
1901         .get_eee                = rtl8169_get_eee,
1902         .set_eee                = rtl8169_set_eee,
1903         .get_link_ksettings     = phy_ethtool_get_link_ksettings,
1904         .set_link_ksettings     = phy_ethtool_set_link_ksettings,
1905 };
1906
1907 static void rtl_enable_eee(struct rtl8169_private *tp)
1908 {
1909         struct phy_device *phydev = tp->phydev;
1910         int adv;
1911
1912         /* respect EEE advertisement the user may have set */
1913         if (tp->eee_adv >= 0)
1914                 adv = tp->eee_adv;
1915         else
1916                 adv = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
1917
1918         if (adv >= 0)
1919                 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, adv);
1920 }
1921
1922 static enum mac_version rtl8169_get_mac_version(u16 xid, bool gmii)
1923 {
1924         /*
1925          * The driver currently handles the 8168Bf and the 8168Be identically
1926          * but they can be identified more specifically through the test below
1927          * if needed:
1928          *
1929          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1930          *
1931          * Same thing for the 8101Eb and the 8101Ec:
1932          *
1933          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1934          */
1935         static const struct rtl_mac_info {
1936                 u16 mask;
1937                 u16 val;
1938                 enum mac_version ver;
1939         } mac_info[] = {
1940                 /* 8125B family. */
1941                 { 0x7cf, 0x641, RTL_GIGA_MAC_VER_63 },
1942
1943                 /* 8125A family. */
1944                 { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 },
1945                 { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 },
1946
1947                 /* RTL8117 */
1948                 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52 },
1949
1950                 /* 8168EP family. */
1951                 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 },
1952                 { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 },
1953                 { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 },
1954
1955                 /* 8168H family. */
1956                 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 },
1957                 { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 },
1958
1959                 /* 8168G family. */
1960                 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 },
1961                 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 },
1962                 { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 },
1963                 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 },
1964
1965                 /* 8168F family. */
1966                 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 },
1967                 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 },
1968                 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 },
1969
1970                 /* 8168E family. */
1971                 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 },
1972                 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 },
1973                 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 },
1974
1975                 /* 8168D family. */
1976                 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 },
1977                 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 },
1978
1979                 /* 8168DP family. */
1980                 { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 },
1981                 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 },
1982                 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 },
1983
1984                 /* 8168C family. */
1985                 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 },
1986                 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 },
1987                 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 },
1988                 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 },
1989                 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 },
1990                 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 },
1991                 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 },
1992
1993                 /* 8168B family. */
1994                 { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12 },
1995                 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 },
1996                 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 },
1997
1998                 /* 8101 family. */
1999                 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 },
2000                 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 },
2001                 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 },
2002                 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 },
2003                 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 },
2004                 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 },
2005                 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 },
2006                 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 },
2007                 { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13 },
2008                 { 0x7cf, 0x240, RTL_GIGA_MAC_VER_14 },
2009                 { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10 },
2010                 { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16 },
2011                 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 },
2012                 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 },
2013                 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16 },
2014                 /* FIXME: where did these entries come from ? -- FR */
2015                 { 0xfc8, 0x388, RTL_GIGA_MAC_VER_13 },
2016                 { 0xfc8, 0x308, RTL_GIGA_MAC_VER_13 },
2017
2018                 /* 8110 family. */
2019                 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 },
2020                 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 },
2021                 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 },
2022                 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 },
2023                 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 },
2024
2025                 /* Catch-all */
2026                 { 0x000, 0x000, RTL_GIGA_MAC_NONE   }
2027         };
2028         const struct rtl_mac_info *p = mac_info;
2029         enum mac_version ver;
2030
2031         while ((xid & p->mask) != p->val)
2032                 p++;
2033         ver = p->ver;
2034
2035         if (ver != RTL_GIGA_MAC_NONE && !gmii) {
2036                 if (ver == RTL_GIGA_MAC_VER_42)
2037                         ver = RTL_GIGA_MAC_VER_43;
2038                 else if (ver == RTL_GIGA_MAC_VER_45)
2039                         ver = RTL_GIGA_MAC_VER_47;
2040                 else if (ver == RTL_GIGA_MAC_VER_46)
2041                         ver = RTL_GIGA_MAC_VER_48;
2042         }
2043
2044         return ver;
2045 }
2046
2047 static void rtl_release_firmware(struct rtl8169_private *tp)
2048 {
2049         if (tp->rtl_fw) {
2050                 rtl_fw_release_firmware(tp->rtl_fw);
2051                 kfree(tp->rtl_fw);
2052                 tp->rtl_fw = NULL;
2053         }
2054 }
2055
2056 void r8169_apply_firmware(struct rtl8169_private *tp)
2057 {
2058         /* TODO: release firmware if rtl_fw_write_firmware signals failure. */
2059         if (tp->rtl_fw) {
2060                 rtl_fw_write_firmware(tp, tp->rtl_fw);
2061                 /* At least one firmware doesn't reset tp->ocp_base. */
2062                 tp->ocp_base = OCP_STD_PHY_BASE;
2063         }
2064 }
2065
2066 static void rtl8168_config_eee_mac(struct rtl8169_private *tp)
2067 {
2068         /* Adjust EEE LED frequency */
2069         if (tp->mac_version != RTL_GIGA_MAC_VER_38)
2070                 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
2071
2072         rtl_eri_set_bits(tp, 0x1b0, 0x0003);
2073 }
2074
2075 static void rtl8125a_config_eee_mac(struct rtl8169_private *tp)
2076 {
2077         r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0));
2078         r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1));
2079 }
2080
2081 static void rtl8125_set_eee_txidle_timer(struct rtl8169_private *tp)
2082 {
2083         RTL_W16(tp, EEE_TXIDLE_TIMER_8125, tp->dev->mtu + ETH_HLEN + 0x20);
2084 }
2085
2086 static void rtl8125b_config_eee_mac(struct rtl8169_private *tp)
2087 {
2088         rtl8125_set_eee_txidle_timer(tp);
2089         r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0));
2090 }
2091
2092 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
2093 {
2094         const u16 w[] = {
2095                 addr[0] | (addr[1] << 8),
2096                 addr[2] | (addr[3] << 8),
2097                 addr[4] | (addr[5] << 8)
2098         };
2099
2100         rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, w[0] | (w[1] << 16));
2101         rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, w[2]);
2102         rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, w[0] << 16);
2103         rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, w[1] | (w[2] << 16));
2104 }
2105
2106 u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp)
2107 {
2108         u16 data1, data2, ioffset;
2109
2110         r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
2111         data1 = r8168_mac_ocp_read(tp, 0xdd02);
2112         data2 = r8168_mac_ocp_read(tp, 0xdd00);
2113
2114         ioffset = (data2 >> 1) & 0x7ff8;
2115         ioffset |= data2 & 0x0007;
2116         if (data1 & BIT(7))
2117                 ioffset |= BIT(15);
2118
2119         return ioffset;
2120 }
2121
2122 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
2123 {
2124         set_bit(flag, tp->wk.flags);
2125         schedule_work(&tp->wk.work);
2126 }
2127
2128 static void rtl8169_init_phy(struct rtl8169_private *tp)
2129 {
2130         r8169_hw_phy_config(tp, tp->phydev, tp->mac_version);
2131
2132         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2133                 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2134                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
2135                 /* set undocumented MAC Reg C+CR Offset 0x82h */
2136                 RTL_W8(tp, 0x82, 0x01);
2137         }
2138
2139         if (tp->mac_version == RTL_GIGA_MAC_VER_05 &&
2140             tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE &&
2141             tp->pci_dev->subsystem_device == 0xe000)
2142                 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b);
2143
2144         /* We may have called phy_speed_down before */
2145         phy_speed_up(tp->phydev);
2146
2147         if (rtl_supports_eee(tp))
2148                 rtl_enable_eee(tp);
2149
2150         genphy_soft_reset(tp->phydev);
2151 }
2152
2153 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
2154 {
2155         rtl_unlock_config_regs(tp);
2156
2157         RTL_W32(tp, MAC4, addr[4] | addr[5] << 8);
2158         rtl_pci_commit(tp);
2159
2160         RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
2161         rtl_pci_commit(tp);
2162
2163         if (tp->mac_version == RTL_GIGA_MAC_VER_34)
2164                 rtl_rar_exgmac_set(tp, addr);
2165
2166         rtl_lock_config_regs(tp);
2167 }
2168
2169 static int rtl_set_mac_address(struct net_device *dev, void *p)
2170 {
2171         struct rtl8169_private *tp = netdev_priv(dev);
2172         int ret;
2173
2174         ret = eth_mac_addr(dev, p);
2175         if (ret)
2176                 return ret;
2177
2178         rtl_rar_set(tp, dev->dev_addr);
2179
2180         return 0;
2181 }
2182
2183 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
2184 {
2185         switch (tp->mac_version) {
2186         case RTL_GIGA_MAC_VER_25:
2187         case RTL_GIGA_MAC_VER_26:
2188         case RTL_GIGA_MAC_VER_29:
2189         case RTL_GIGA_MAC_VER_30:
2190         case RTL_GIGA_MAC_VER_32:
2191         case RTL_GIGA_MAC_VER_33:
2192         case RTL_GIGA_MAC_VER_34:
2193         case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_63:
2194                 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
2195                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
2196                 break;
2197         default:
2198                 break;
2199         }
2200 }
2201
2202 static void rtl_pll_power_down(struct rtl8169_private *tp)
2203 {
2204         if (r8168_check_dash(tp))
2205                 return;
2206
2207         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
2208             tp->mac_version == RTL_GIGA_MAC_VER_33)
2209                 rtl_ephy_write(tp, 0x19, 0xff64);
2210
2211         if (device_may_wakeup(tp_to_dev(tp))) {
2212                 phy_speed_down(tp->phydev, false);
2213                 rtl_wol_suspend_quirk(tp);
2214                 return;
2215         }
2216
2217         switch (tp->mac_version) {
2218         case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
2219         case RTL_GIGA_MAC_VER_37:
2220         case RTL_GIGA_MAC_VER_39:
2221         case RTL_GIGA_MAC_VER_43:
2222         case RTL_GIGA_MAC_VER_44:
2223         case RTL_GIGA_MAC_VER_45:
2224         case RTL_GIGA_MAC_VER_46:
2225         case RTL_GIGA_MAC_VER_47:
2226         case RTL_GIGA_MAC_VER_48:
2227         case RTL_GIGA_MAC_VER_50 ... RTL_GIGA_MAC_VER_63:
2228                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
2229                 break;
2230         case RTL_GIGA_MAC_VER_40:
2231         case RTL_GIGA_MAC_VER_41:
2232         case RTL_GIGA_MAC_VER_49:
2233                 rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000);
2234                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
2235                 break;
2236         default:
2237                 break;
2238         }
2239 }
2240
2241 static void rtl_pll_power_up(struct rtl8169_private *tp)
2242 {
2243         switch (tp->mac_version) {
2244         case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
2245         case RTL_GIGA_MAC_VER_37:
2246         case RTL_GIGA_MAC_VER_39:
2247         case RTL_GIGA_MAC_VER_43:
2248                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);
2249                 break;
2250         case RTL_GIGA_MAC_VER_44:
2251         case RTL_GIGA_MAC_VER_45:
2252         case RTL_GIGA_MAC_VER_46:
2253         case RTL_GIGA_MAC_VER_47:
2254         case RTL_GIGA_MAC_VER_48:
2255         case RTL_GIGA_MAC_VER_50 ... RTL_GIGA_MAC_VER_63:
2256                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
2257                 break;
2258         case RTL_GIGA_MAC_VER_40:
2259         case RTL_GIGA_MAC_VER_41:
2260         case RTL_GIGA_MAC_VER_49:
2261                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
2262                 rtl_eri_set_bits(tp, 0x1a8, 0xfc000000);
2263                 break;
2264         default:
2265                 break;
2266         }
2267
2268         phy_resume(tp->phydev);
2269 }
2270
2271 static void rtl_init_rxcfg(struct rtl8169_private *tp)
2272 {
2273         switch (tp->mac_version) {
2274         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
2275         case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
2276                 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
2277                 break;
2278         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
2279         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
2280         case RTL_GIGA_MAC_VER_38:
2281                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
2282                 break;
2283         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_52:
2284                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
2285                 break;
2286         case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_63:
2287                 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST);
2288                 break;
2289         default:
2290                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
2291                 break;
2292         }
2293 }
2294
2295 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2296 {
2297         tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
2298 }
2299
2300 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
2301 {
2302         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2303         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
2304 }
2305
2306 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
2307 {
2308         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2309         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
2310 }
2311
2312 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
2313 {
2314         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2315 }
2316
2317 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
2318 {
2319         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2320 }
2321
2322 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
2323 {
2324         RTL_W8(tp, MaxTxPacketSize, 0x3f);
2325         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2326         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
2327 }
2328
2329 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
2330 {
2331         RTL_W8(tp, MaxTxPacketSize, 0x0c);
2332         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2333         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
2334 }
2335
2336 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
2337 {
2338         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
2339 }
2340
2341 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
2342 {
2343         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
2344 }
2345
2346 static void rtl_jumbo_config(struct rtl8169_private *tp)
2347 {
2348         bool jumbo = tp->dev->mtu > ETH_DATA_LEN;
2349
2350         rtl_unlock_config_regs(tp);
2351         switch (tp->mac_version) {
2352         case RTL_GIGA_MAC_VER_12:
2353         case RTL_GIGA_MAC_VER_17:
2354                 if (jumbo) {
2355                         pcie_set_readrq(tp->pci_dev, 512);
2356                         r8168b_1_hw_jumbo_enable(tp);
2357                 } else {
2358                         r8168b_1_hw_jumbo_disable(tp);
2359                 }
2360                 break;
2361         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26:
2362                 if (jumbo) {
2363                         pcie_set_readrq(tp->pci_dev, 512);
2364                         r8168c_hw_jumbo_enable(tp);
2365                 } else {
2366                         r8168c_hw_jumbo_disable(tp);
2367                 }
2368                 break;
2369         case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28:
2370                 if (jumbo)
2371                         r8168dp_hw_jumbo_enable(tp);
2372                 else
2373                         r8168dp_hw_jumbo_disable(tp);
2374                 break;
2375         case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33:
2376                 if (jumbo) {
2377                         pcie_set_readrq(tp->pci_dev, 512);
2378                         r8168e_hw_jumbo_enable(tp);
2379                 } else {
2380                         r8168e_hw_jumbo_disable(tp);
2381                 }
2382                 break;
2383         default:
2384                 break;
2385         }
2386         rtl_lock_config_regs(tp);
2387
2388         if (!jumbo && pci_is_pcie(tp->pci_dev) && tp->supports_gmii)
2389                 pcie_set_readrq(tp->pci_dev, 4096);
2390 }
2391
2392 DECLARE_RTL_COND(rtl_chipcmd_cond)
2393 {
2394         return RTL_R8(tp, ChipCmd) & CmdReset;
2395 }
2396
2397 static void rtl_hw_reset(struct rtl8169_private *tp)
2398 {
2399         RTL_W8(tp, ChipCmd, CmdReset);
2400
2401         rtl_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
2402 }
2403
2404 static void rtl_request_firmware(struct rtl8169_private *tp)
2405 {
2406         struct rtl_fw *rtl_fw;
2407
2408         /* firmware loaded already or no firmware available */
2409         if (tp->rtl_fw || !tp->fw_name)
2410                 return;
2411
2412         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
2413         if (!rtl_fw)
2414                 return;
2415
2416         rtl_fw->phy_write = rtl_writephy;
2417         rtl_fw->phy_read = rtl_readphy;
2418         rtl_fw->mac_mcu_write = mac_mcu_write;
2419         rtl_fw->mac_mcu_read = mac_mcu_read;
2420         rtl_fw->fw_name = tp->fw_name;
2421         rtl_fw->dev = tp_to_dev(tp);
2422
2423         if (rtl_fw_request_firmware(rtl_fw))
2424                 kfree(rtl_fw);
2425         else
2426                 tp->rtl_fw = rtl_fw;
2427 }
2428
2429 static void rtl_rx_close(struct rtl8169_private *tp)
2430 {
2431         RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
2432 }
2433
2434 DECLARE_RTL_COND(rtl_npq_cond)
2435 {
2436         return RTL_R8(tp, TxPoll) & NPQ;
2437 }
2438
2439 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
2440 {
2441         return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
2442 }
2443
2444 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
2445 {
2446         return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
2447 }
2448
2449 DECLARE_RTL_COND(rtl_rxtx_empty_cond_2)
2450 {
2451         /* IntrMitigate has new functionality on RTL8125 */
2452         return (RTL_R16(tp, IntrMitigate) & 0x0103) == 0x0103;
2453 }
2454
2455 static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp)
2456 {
2457         switch (tp->mac_version) {
2458         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_52:
2459                 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42);
2460                 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2461                 break;
2462         case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_61:
2463                 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2464                 break;
2465         case RTL_GIGA_MAC_VER_63:
2466                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
2467                 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2468                 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond_2, 100, 42);
2469                 break;
2470         default:
2471                 break;
2472         }
2473 }
2474
2475 static void rtl_enable_rxdvgate(struct rtl8169_private *tp)
2476 {
2477         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
2478         fsleep(2000);
2479         rtl_wait_txrx_fifo_empty(tp);
2480 }
2481
2482 static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
2483 {
2484         u32 val = TX_DMA_BURST << TxDMAShift |
2485                   InterFrameGap << TxInterFrameGapShift;
2486
2487         if (rtl_is_8168evl_up(tp))
2488                 val |= TXCFG_AUTO_FIFO;
2489
2490         RTL_W32(tp, TxConfig, val);
2491 }
2492
2493 static void rtl_set_rx_max_size(struct rtl8169_private *tp)
2494 {
2495         /* Low hurts. Let's disable the filtering. */
2496         RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
2497 }
2498
2499 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
2500 {
2501         /*
2502          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
2503          * register to be written before TxDescAddrLow to work.
2504          * Switching from MMIO to I/O access fixes the issue as well.
2505          */
2506         RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
2507         RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
2508         RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
2509         RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
2510 }
2511
2512 static void rtl8169_set_magic_reg(struct rtl8169_private *tp)
2513 {
2514         u32 val;
2515
2516         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
2517                 val = 0x000fff00;
2518         else if (tp->mac_version == RTL_GIGA_MAC_VER_06)
2519                 val = 0x00ffff00;
2520         else
2521                 return;
2522
2523         if (RTL_R8(tp, Config2) & PCI_Clock_66MHz)
2524                 val |= 0xff;
2525
2526         RTL_W32(tp, 0x7c, val);
2527 }
2528
2529 static void rtl_set_rx_mode(struct net_device *dev)
2530 {
2531         u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast;
2532         /* Multicast hash filter */
2533         u32 mc_filter[2] = { 0xffffffff, 0xffffffff };
2534         struct rtl8169_private *tp = netdev_priv(dev);
2535         u32 tmp;
2536
2537         if (dev->flags & IFF_PROMISC) {
2538                 rx_mode |= AcceptAllPhys;
2539         } else if (netdev_mc_count(dev) > MC_FILTER_LIMIT ||
2540                    dev->flags & IFF_ALLMULTI ||
2541                    tp->mac_version == RTL_GIGA_MAC_VER_35) {
2542                 /* accept all multicasts */
2543         } else if (netdev_mc_empty(dev)) {
2544                 rx_mode &= ~AcceptMulticast;
2545         } else {
2546                 struct netdev_hw_addr *ha;
2547
2548                 mc_filter[1] = mc_filter[0] = 0;
2549                 netdev_for_each_mc_addr(ha, dev) {
2550                         u32 bit_nr = eth_hw_addr_crc(ha) >> 26;
2551                         mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31);
2552                 }
2553
2554                 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
2555                         tmp = mc_filter[0];
2556                         mc_filter[0] = swab32(mc_filter[1]);
2557                         mc_filter[1] = swab32(tmp);
2558                 }
2559         }
2560
2561         RTL_W32(tp, MAR0 + 4, mc_filter[1]);
2562         RTL_W32(tp, MAR0 + 0, mc_filter[0]);
2563
2564         tmp = RTL_R32(tp, RxConfig);
2565         RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode);
2566 }
2567
2568 DECLARE_RTL_COND(rtl_csiar_cond)
2569 {
2570         return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
2571 }
2572
2573 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
2574 {
2575         u32 func = PCI_FUNC(tp->pci_dev->devfn);
2576
2577         RTL_W32(tp, CSIDR, value);
2578         RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
2579                 CSIAR_BYTE_ENABLE | func << 16);
2580
2581         rtl_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
2582 }
2583
2584 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
2585 {
2586         u32 func = PCI_FUNC(tp->pci_dev->devfn);
2587
2588         RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
2589                 CSIAR_BYTE_ENABLE);
2590
2591         return rtl_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
2592                 RTL_R32(tp, CSIDR) : ~0;
2593 }
2594
2595 static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val)
2596 {
2597         struct pci_dev *pdev = tp->pci_dev;
2598         u32 csi;
2599
2600         /* According to Realtek the value at config space address 0x070f
2601          * controls the L0s/L1 entrance latency. We try standard ECAM access
2602          * first and if it fails fall back to CSI.
2603          */
2604         if (pdev->cfg_size > 0x070f &&
2605             pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
2606                 return;
2607
2608         netdev_notice_once(tp->dev,
2609                 "No native access to PCI extended config space, falling back to CSI\n");
2610         csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
2611         rtl_csi_write(tp, 0x070c, csi | val << 24);
2612 }
2613
2614 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
2615 {
2616         rtl_csi_access_enable(tp, 0x27);
2617 }
2618
2619 struct ephy_info {
2620         unsigned int offset;
2621         u16 mask;
2622         u16 bits;
2623 };
2624
2625 static void __rtl_ephy_init(struct rtl8169_private *tp,
2626                             const struct ephy_info *e, int len)
2627 {
2628         u16 w;
2629
2630         while (len-- > 0) {
2631                 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
2632                 rtl_ephy_write(tp, e->offset, w);
2633                 e++;
2634         }
2635 }
2636
2637 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a))
2638
2639 static void rtl_disable_clock_request(struct rtl8169_private *tp)
2640 {
2641         pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
2642                                    PCI_EXP_LNKCTL_CLKREQ_EN);
2643 }
2644
2645 static void rtl_enable_clock_request(struct rtl8169_private *tp)
2646 {
2647         pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
2648                                  PCI_EXP_LNKCTL_CLKREQ_EN);
2649 }
2650
2651 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp)
2652 {
2653         /* work around an issue when PCI reset occurs during L2/L3 state */
2654         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23);
2655 }
2656
2657 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
2658 {
2659         /* Don't enable ASPM in the chip if OS can't control ASPM */
2660         if (enable && tp->aspm_manageable) {
2661                 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);
2662                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);
2663         } else {
2664                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
2665                 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
2666         }
2667
2668         udelay(10);
2669 }
2670
2671 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat,
2672                               u16 tx_stat, u16 rx_dyn, u16 tx_dyn)
2673 {
2674         /* Usage of dynamic vs. static FIFO is controlled by bit
2675          * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known.
2676          */
2677         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn);
2678         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn);
2679 }
2680
2681 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp,
2682                                           u8 low, u8 high)
2683 {
2684         /* FIFO thresholds for pause flow control */
2685         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low);
2686         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high);
2687 }
2688
2689 static void rtl_hw_start_8168b(struct rtl8169_private *tp)
2690 {
2691         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2692 }
2693
2694 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
2695 {
2696         RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
2697
2698         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2699
2700         rtl_disable_clock_request(tp);
2701 }
2702
2703 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
2704 {
2705         static const struct ephy_info e_info_8168cp[] = {
2706                 { 0x01, 0,      0x0001 },
2707                 { 0x02, 0x0800, 0x1000 },
2708                 { 0x03, 0,      0x0042 },
2709                 { 0x06, 0x0080, 0x0000 },
2710                 { 0x07, 0,      0x2000 }
2711         };
2712
2713         rtl_set_def_aspm_entry_latency(tp);
2714
2715         rtl_ephy_init(tp, e_info_8168cp);
2716
2717         __rtl_hw_start_8168cp(tp);
2718 }
2719
2720 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
2721 {
2722         rtl_set_def_aspm_entry_latency(tp);
2723
2724         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2725 }
2726
2727 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
2728 {
2729         rtl_set_def_aspm_entry_latency(tp);
2730
2731         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2732
2733         /* Magic. */
2734         RTL_W8(tp, DBG_REG, 0x20);
2735 }
2736
2737 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
2738 {
2739         static const struct ephy_info e_info_8168c_1[] = {
2740                 { 0x02, 0x0800, 0x1000 },
2741                 { 0x03, 0,      0x0002 },
2742                 { 0x06, 0x0080, 0x0000 }
2743         };
2744
2745         rtl_set_def_aspm_entry_latency(tp);
2746
2747         RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
2748
2749         rtl_ephy_init(tp, e_info_8168c_1);
2750
2751         __rtl_hw_start_8168cp(tp);
2752 }
2753
2754 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
2755 {
2756         static const struct ephy_info e_info_8168c_2[] = {
2757                 { 0x01, 0,      0x0001 },
2758                 { 0x03, 0x0400, 0x0020 }
2759         };
2760
2761         rtl_set_def_aspm_entry_latency(tp);
2762
2763         rtl_ephy_init(tp, e_info_8168c_2);
2764
2765         __rtl_hw_start_8168cp(tp);
2766 }
2767
2768 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
2769 {
2770         rtl_hw_start_8168c_2(tp);
2771 }
2772
2773 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
2774 {
2775         rtl_set_def_aspm_entry_latency(tp);
2776
2777         __rtl_hw_start_8168cp(tp);
2778 }
2779
2780 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
2781 {
2782         rtl_set_def_aspm_entry_latency(tp);
2783
2784         rtl_disable_clock_request(tp);
2785 }
2786
2787 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
2788 {
2789         static const struct ephy_info e_info_8168d_4[] = {
2790                 { 0x0b, 0x0000, 0x0048 },
2791                 { 0x19, 0x0020, 0x0050 },
2792                 { 0x0c, 0x0100, 0x0020 },
2793                 { 0x10, 0x0004, 0x0000 },
2794         };
2795
2796         rtl_set_def_aspm_entry_latency(tp);
2797
2798         rtl_ephy_init(tp, e_info_8168d_4);
2799
2800         rtl_enable_clock_request(tp);
2801 }
2802
2803 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
2804 {
2805         static const struct ephy_info e_info_8168e_1[] = {
2806                 { 0x00, 0x0200, 0x0100 },
2807                 { 0x00, 0x0000, 0x0004 },
2808                 { 0x06, 0x0002, 0x0001 },
2809                 { 0x06, 0x0000, 0x0030 },
2810                 { 0x07, 0x0000, 0x2000 },
2811                 { 0x00, 0x0000, 0x0020 },
2812                 { 0x03, 0x5800, 0x2000 },
2813                 { 0x03, 0x0000, 0x0001 },
2814                 { 0x01, 0x0800, 0x1000 },
2815                 { 0x07, 0x0000, 0x4000 },
2816                 { 0x1e, 0x0000, 0x2000 },
2817                 { 0x19, 0xffff, 0xfe6c },
2818                 { 0x0a, 0x0000, 0x0040 }
2819         };
2820
2821         rtl_set_def_aspm_entry_latency(tp);
2822
2823         rtl_ephy_init(tp, e_info_8168e_1);
2824
2825         rtl_disable_clock_request(tp);
2826
2827         /* Reset tx FIFO pointer */
2828         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
2829         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
2830
2831         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
2832 }
2833
2834 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
2835 {
2836         static const struct ephy_info e_info_8168e_2[] = {
2837                 { 0x09, 0x0000, 0x0080 },
2838                 { 0x19, 0x0000, 0x0224 },
2839                 { 0x00, 0x0000, 0x0004 },
2840                 { 0x0c, 0x3df0, 0x0200 },
2841         };
2842
2843         rtl_set_def_aspm_entry_latency(tp);
2844
2845         rtl_ephy_init(tp, e_info_8168e_2);
2846
2847         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
2848         rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000);
2849         rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
2850         rtl_eri_set_bits(tp, 0x0d4, 0x1f00);
2851         rtl_eri_set_bits(tp, 0x1d0, BIT(1));
2852         rtl_reset_packet_filter(tp);
2853         rtl_eri_set_bits(tp, 0x1b0, BIT(4));
2854         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
2855         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060);
2856
2857         rtl_disable_clock_request(tp);
2858
2859         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
2860
2861         rtl8168_config_eee_mac(tp);
2862
2863         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
2864         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
2865         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
2866
2867         rtl_hw_aspm_clkreq_enable(tp, true);
2868 }
2869
2870 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
2871 {
2872         rtl_set_def_aspm_entry_latency(tp);
2873
2874         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
2875         rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000);
2876         rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
2877         rtl_reset_packet_filter(tp);
2878         rtl_eri_set_bits(tp, 0x1b0, BIT(4));
2879         rtl_eri_set_bits(tp, 0x1d0, BIT(4) | BIT(1));
2880         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
2881         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060);
2882
2883         rtl_disable_clock_request(tp);
2884
2885         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
2886         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
2887         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
2888         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
2889
2890         rtl8168_config_eee_mac(tp);
2891 }
2892
2893 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
2894 {
2895         static const struct ephy_info e_info_8168f_1[] = {
2896                 { 0x06, 0x00c0, 0x0020 },
2897                 { 0x08, 0x0001, 0x0002 },
2898                 { 0x09, 0x0000, 0x0080 },
2899                 { 0x19, 0x0000, 0x0224 },
2900                 { 0x00, 0x0000, 0x0008 },
2901                 { 0x0c, 0x3df0, 0x0200 },
2902         };
2903
2904         rtl_hw_start_8168f(tp);
2905
2906         rtl_ephy_init(tp, e_info_8168f_1);
2907
2908         rtl_eri_set_bits(tp, 0x0d4, 0x1f00);
2909 }
2910
2911 static void rtl_hw_start_8411(struct rtl8169_private *tp)
2912 {
2913         static const struct ephy_info e_info_8168f_1[] = {
2914                 { 0x06, 0x00c0, 0x0020 },
2915                 { 0x0f, 0xffff, 0x5200 },
2916                 { 0x19, 0x0000, 0x0224 },
2917                 { 0x00, 0x0000, 0x0008 },
2918                 { 0x0c, 0x3df0, 0x0200 },
2919         };
2920
2921         rtl_hw_start_8168f(tp);
2922         rtl_pcie_state_l2l3_disable(tp);
2923
2924         rtl_ephy_init(tp, e_info_8168f_1);
2925
2926         rtl_eri_set_bits(tp, 0x0d4, 0x0c00);
2927 }
2928
2929 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
2930 {
2931         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
2932         rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
2933
2934         rtl_set_def_aspm_entry_latency(tp);
2935
2936         rtl_reset_packet_filter(tp);
2937         rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f);
2938
2939         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
2940
2941         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
2942         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
2943         rtl_eri_set_bits(tp, 0x0d4, 0x1f80);
2944
2945         rtl8168_config_eee_mac(tp);
2946
2947         rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06);
2948         rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
2949
2950         rtl_pcie_state_l2l3_disable(tp);
2951 }
2952
2953 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
2954 {
2955         static const struct ephy_info e_info_8168g_1[] = {
2956                 { 0x00, 0x0008, 0x0000 },
2957                 { 0x0c, 0x3ff0, 0x0820 },
2958                 { 0x1e, 0x0000, 0x0001 },
2959                 { 0x19, 0x8000, 0x0000 }
2960         };
2961
2962         rtl_hw_start_8168g(tp);
2963
2964         /* disable aspm and clock request before access ephy */
2965         rtl_hw_aspm_clkreq_enable(tp, false);
2966         rtl_ephy_init(tp, e_info_8168g_1);
2967         rtl_hw_aspm_clkreq_enable(tp, true);
2968 }
2969
2970 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
2971 {
2972         static const struct ephy_info e_info_8168g_2[] = {
2973                 { 0x00, 0x0008, 0x0000 },
2974                 { 0x0c, 0x3ff0, 0x0820 },
2975                 { 0x19, 0xffff, 0x7c00 },
2976                 { 0x1e, 0xffff, 0x20eb },
2977                 { 0x0d, 0xffff, 0x1666 },
2978                 { 0x00, 0xffff, 0x10a3 },
2979                 { 0x06, 0xffff, 0xf050 },
2980                 { 0x04, 0x0000, 0x0010 },
2981                 { 0x1d, 0x4000, 0x0000 },
2982         };
2983
2984         rtl_hw_start_8168g(tp);
2985
2986         /* disable aspm and clock request before access ephy */
2987         rtl_hw_aspm_clkreq_enable(tp, false);
2988         rtl_ephy_init(tp, e_info_8168g_2);
2989 }
2990
2991 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
2992 {
2993         static const struct ephy_info e_info_8411_2[] = {
2994                 { 0x00, 0x0008, 0x0000 },
2995                 { 0x0c, 0x37d0, 0x0820 },
2996                 { 0x1e, 0x0000, 0x0001 },
2997                 { 0x19, 0x8021, 0x0000 },
2998                 { 0x1e, 0x0000, 0x2000 },
2999                 { 0x0d, 0x0100, 0x0200 },
3000                 { 0x00, 0x0000, 0x0080 },
3001                 { 0x06, 0x0000, 0x0010 },
3002                 { 0x04, 0x0000, 0x0010 },
3003                 { 0x1d, 0x0000, 0x4000 },
3004         };
3005
3006         rtl_hw_start_8168g(tp);
3007
3008         /* disable aspm and clock request before access ephy */
3009         rtl_hw_aspm_clkreq_enable(tp, false);
3010         rtl_ephy_init(tp, e_info_8411_2);
3011
3012         /* The following Realtek-provided magic fixes an issue with the RX unit
3013          * getting confused after the PHY having been powered-down.
3014          */
3015         r8168_mac_ocp_write(tp, 0xFC28, 0x0000);
3016         r8168_mac_ocp_write(tp, 0xFC2A, 0x0000);
3017         r8168_mac_ocp_write(tp, 0xFC2C, 0x0000);
3018         r8168_mac_ocp_write(tp, 0xFC2E, 0x0000);
3019         r8168_mac_ocp_write(tp, 0xFC30, 0x0000);
3020         r8168_mac_ocp_write(tp, 0xFC32, 0x0000);
3021         r8168_mac_ocp_write(tp, 0xFC34, 0x0000);
3022         r8168_mac_ocp_write(tp, 0xFC36, 0x0000);
3023         mdelay(3);
3024         r8168_mac_ocp_write(tp, 0xFC26, 0x0000);
3025
3026         r8168_mac_ocp_write(tp, 0xF800, 0xE008);
3027         r8168_mac_ocp_write(tp, 0xF802, 0xE00A);
3028         r8168_mac_ocp_write(tp, 0xF804, 0xE00C);
3029         r8168_mac_ocp_write(tp, 0xF806, 0xE00E);
3030         r8168_mac_ocp_write(tp, 0xF808, 0xE027);
3031         r8168_mac_ocp_write(tp, 0xF80A, 0xE04F);
3032         r8168_mac_ocp_write(tp, 0xF80C, 0xE05E);
3033         r8168_mac_ocp_write(tp, 0xF80E, 0xE065);
3034         r8168_mac_ocp_write(tp, 0xF810, 0xC602);
3035         r8168_mac_ocp_write(tp, 0xF812, 0xBE00);
3036         r8168_mac_ocp_write(tp, 0xF814, 0x0000);
3037         r8168_mac_ocp_write(tp, 0xF816, 0xC502);
3038         r8168_mac_ocp_write(tp, 0xF818, 0xBD00);
3039         r8168_mac_ocp_write(tp, 0xF81A, 0x074C);
3040         r8168_mac_ocp_write(tp, 0xF81C, 0xC302);
3041         r8168_mac_ocp_write(tp, 0xF81E, 0xBB00);
3042         r8168_mac_ocp_write(tp, 0xF820, 0x080A);
3043         r8168_mac_ocp_write(tp, 0xF822, 0x6420);
3044         r8168_mac_ocp_write(tp, 0xF824, 0x48C2);
3045         r8168_mac_ocp_write(tp, 0xF826, 0x8C20);
3046         r8168_mac_ocp_write(tp, 0xF828, 0xC516);
3047         r8168_mac_ocp_write(tp, 0xF82A, 0x64A4);
3048         r8168_mac_ocp_write(tp, 0xF82C, 0x49C0);
3049         r8168_mac_ocp_write(tp, 0xF82E, 0xF009);
3050         r8168_mac_ocp_write(tp, 0xF830, 0x74A2);
3051         r8168_mac_ocp_write(tp, 0xF832, 0x8CA5);
3052         r8168_mac_ocp_write(tp, 0xF834, 0x74A0);
3053         r8168_mac_ocp_write(tp, 0xF836, 0xC50E);
3054         r8168_mac_ocp_write(tp, 0xF838, 0x9CA2);
3055         r8168_mac_ocp_write(tp, 0xF83A, 0x1C11);
3056         r8168_mac_ocp_write(tp, 0xF83C, 0x9CA0);
3057         r8168_mac_ocp_write(tp, 0xF83E, 0xE006);
3058         r8168_mac_ocp_write(tp, 0xF840, 0x74F8);
3059         r8168_mac_ocp_write(tp, 0xF842, 0x48C4);
3060         r8168_mac_ocp_write(tp, 0xF844, 0x8CF8);
3061         r8168_mac_ocp_write(tp, 0xF846, 0xC404);
3062         r8168_mac_ocp_write(tp, 0xF848, 0xBC00);
3063         r8168_mac_ocp_write(tp, 0xF84A, 0xC403);
3064         r8168_mac_ocp_write(tp, 0xF84C, 0xBC00);
3065         r8168_mac_ocp_write(tp, 0xF84E, 0x0BF2);
3066         r8168_mac_ocp_write(tp, 0xF850, 0x0C0A);
3067         r8168_mac_ocp_write(tp, 0xF852, 0xE434);
3068         r8168_mac_ocp_write(tp, 0xF854, 0xD3C0);
3069         r8168_mac_ocp_write(tp, 0xF856, 0x49D9);
3070         r8168_mac_ocp_write(tp, 0xF858, 0xF01F);
3071         r8168_mac_ocp_write(tp, 0xF85A, 0xC526);
3072         r8168_mac_ocp_write(tp, 0xF85C, 0x64A5);
3073         r8168_mac_ocp_write(tp, 0xF85E, 0x1400);
3074         r8168_mac_ocp_write(tp, 0xF860, 0xF007);
3075         r8168_mac_ocp_write(tp, 0xF862, 0x0C01);
3076         r8168_mac_ocp_write(tp, 0xF864, 0x8CA5);
3077         r8168_mac_ocp_write(tp, 0xF866, 0x1C15);
3078         r8168_mac_ocp_write(tp, 0xF868, 0xC51B);
3079         r8168_mac_ocp_write(tp, 0xF86A, 0x9CA0);
3080         r8168_mac_ocp_write(tp, 0xF86C, 0xE013);
3081         r8168_mac_ocp_write(tp, 0xF86E, 0xC519);
3082         r8168_mac_ocp_write(tp, 0xF870, 0x74A0);
3083         r8168_mac_ocp_write(tp, 0xF872, 0x48C4);
3084         r8168_mac_ocp_write(tp, 0xF874, 0x8CA0);
3085         r8168_mac_ocp_write(tp, 0xF876, 0xC516);
3086         r8168_mac_ocp_write(tp, 0xF878, 0x74A4);
3087         r8168_mac_ocp_write(tp, 0xF87A, 0x48C8);
3088         r8168_mac_ocp_write(tp, 0xF87C, 0x48CA);
3089         r8168_mac_ocp_write(tp, 0xF87E, 0x9CA4);
3090         r8168_mac_ocp_write(tp, 0xF880, 0xC512);
3091         r8168_mac_ocp_write(tp, 0xF882, 0x1B00);
3092         r8168_mac_ocp_write(tp, 0xF884, 0x9BA0);
3093         r8168_mac_ocp_write(tp, 0xF886, 0x1B1C);
3094         r8168_mac_ocp_write(tp, 0xF888, 0x483F);
3095         r8168_mac_ocp_write(tp, 0xF88A, 0x9BA2);
3096         r8168_mac_ocp_write(tp, 0xF88C, 0x1B04);
3097         r8168_mac_ocp_write(tp, 0xF88E, 0xC508);
3098         r8168_mac_ocp_write(tp, 0xF890, 0x9BA0);
3099         r8168_mac_ocp_write(tp, 0xF892, 0xC505);
3100         r8168_mac_ocp_write(tp, 0xF894, 0xBD00);
3101         r8168_mac_ocp_write(tp, 0xF896, 0xC502);
3102         r8168_mac_ocp_write(tp, 0xF898, 0xBD00);
3103         r8168_mac_ocp_write(tp, 0xF89A, 0x0300);
3104         r8168_mac_ocp_write(tp, 0xF89C, 0x051E);
3105         r8168_mac_ocp_write(tp, 0xF89E, 0xE434);
3106         r8168_mac_ocp_write(tp, 0xF8A0, 0xE018);
3107         r8168_mac_ocp_write(tp, 0xF8A2, 0xE092);
3108         r8168_mac_ocp_write(tp, 0xF8A4, 0xDE20);
3109         r8168_mac_ocp_write(tp, 0xF8A6, 0xD3C0);
3110         r8168_mac_ocp_write(tp, 0xF8A8, 0xC50F);
3111         r8168_mac_ocp_write(tp, 0xF8AA, 0x76A4);
3112         r8168_mac_ocp_write(tp, 0xF8AC, 0x49E3);
3113         r8168_mac_ocp_write(tp, 0xF8AE, 0xF007);
3114         r8168_mac_ocp_write(tp, 0xF8B0, 0x49C0);
3115         r8168_mac_ocp_write(tp, 0xF8B2, 0xF103);
3116         r8168_mac_ocp_write(tp, 0xF8B4, 0xC607);
3117         r8168_mac_ocp_write(tp, 0xF8B6, 0xBE00);
3118         r8168_mac_ocp_write(tp, 0xF8B8, 0xC606);
3119         r8168_mac_ocp_write(tp, 0xF8BA, 0xBE00);
3120         r8168_mac_ocp_write(tp, 0xF8BC, 0xC602);
3121         r8168_mac_ocp_write(tp, 0xF8BE, 0xBE00);
3122         r8168_mac_ocp_write(tp, 0xF8C0, 0x0C4C);
3123         r8168_mac_ocp_write(tp, 0xF8C2, 0x0C28);
3124         r8168_mac_ocp_write(tp, 0xF8C4, 0x0C2C);
3125         r8168_mac_ocp_write(tp, 0xF8C6, 0xDC00);
3126         r8168_mac_ocp_write(tp, 0xF8C8, 0xC707);
3127         r8168_mac_ocp_write(tp, 0xF8CA, 0x1D00);
3128         r8168_mac_ocp_write(tp, 0xF8CC, 0x8DE2);
3129         r8168_mac_ocp_write(tp, 0xF8CE, 0x48C1);
3130         r8168_mac_ocp_write(tp, 0xF8D0, 0xC502);
3131         r8168_mac_ocp_write(tp, 0xF8D2, 0xBD00);
3132         r8168_mac_ocp_write(tp, 0xF8D4, 0x00AA);
3133         r8168_mac_ocp_write(tp, 0xF8D6, 0xE0C0);
3134         r8168_mac_ocp_write(tp, 0xF8D8, 0xC502);
3135         r8168_mac_ocp_write(tp, 0xF8DA, 0xBD00);
3136         r8168_mac_ocp_write(tp, 0xF8DC, 0x0132);
3137
3138         r8168_mac_ocp_write(tp, 0xFC26, 0x8000);
3139
3140         r8168_mac_ocp_write(tp, 0xFC2A, 0x0743);
3141         r8168_mac_ocp_write(tp, 0xFC2C, 0x0801);
3142         r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9);
3143         r8168_mac_ocp_write(tp, 0xFC30, 0x02FD);
3144         r8168_mac_ocp_write(tp, 0xFC32, 0x0C25);
3145         r8168_mac_ocp_write(tp, 0xFC34, 0x00A9);
3146         r8168_mac_ocp_write(tp, 0xFC36, 0x012D);
3147
3148         rtl_hw_aspm_clkreq_enable(tp, true);
3149 }
3150
3151 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
3152 {
3153         static const struct ephy_info e_info_8168h_1[] = {
3154                 { 0x1e, 0x0800, 0x0001 },
3155                 { 0x1d, 0x0000, 0x0800 },
3156                 { 0x05, 0xffff, 0x2089 },
3157                 { 0x06, 0xffff, 0x5881 },
3158                 { 0x04, 0xffff, 0x854a },
3159                 { 0x01, 0xffff, 0x068b }
3160         };
3161         int rg_saw_cnt;
3162
3163         /* disable aspm and clock request before access ephy */
3164         rtl_hw_aspm_clkreq_enable(tp, false);
3165         rtl_ephy_init(tp, e_info_8168h_1);
3166
3167         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3168         rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
3169
3170         rtl_set_def_aspm_entry_latency(tp);
3171
3172         rtl_reset_packet_filter(tp);
3173
3174         rtl_eri_set_bits(tp, 0xd4, 0x1f00);
3175         rtl_eri_set_bits(tp, 0xdc, 0x001c);
3176
3177         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3178
3179         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
3180
3181         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3182         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3183
3184         rtl8168_config_eee_mac(tp);
3185
3186         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3187         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3188
3189         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3190
3191         rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
3192
3193         rtl_pcie_state_l2l3_disable(tp);
3194
3195         rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff;
3196         if (rg_saw_cnt > 0) {
3197                 u16 sw_cnt_1ms_ini;
3198
3199                 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
3200                 sw_cnt_1ms_ini &= 0x0fff;
3201                 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);
3202         }
3203
3204         r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);
3205         r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008);
3206         r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f);
3207         r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);
3208
3209         r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
3210         r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
3211         r8168_mac_ocp_write(tp, 0xc094, 0x0000);
3212         r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
3213
3214         rtl_hw_aspm_clkreq_enable(tp, true);
3215 }
3216
3217 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
3218 {
3219         rtl8168ep_stop_cmac(tp);
3220
3221         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3222         rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
3223
3224         rtl_set_def_aspm_entry_latency(tp);
3225
3226         rtl_reset_packet_filter(tp);
3227
3228         rtl_eri_set_bits(tp, 0xd4, 0x1f80);
3229
3230         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3231
3232         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
3233
3234         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3235         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3236
3237         rtl8168_config_eee_mac(tp);
3238
3239         rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06);
3240
3241         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3242
3243         rtl_pcie_state_l2l3_disable(tp);
3244 }
3245
3246 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
3247 {
3248         static const struct ephy_info e_info_8168ep_1[] = {
3249                 { 0x00, 0xffff, 0x10ab },
3250                 { 0x06, 0xffff, 0xf030 },
3251                 { 0x08, 0xffff, 0x2006 },
3252                 { 0x0d, 0xffff, 0x1666 },
3253                 { 0x0c, 0x3ff0, 0x0000 }
3254         };
3255
3256         /* disable aspm and clock request before access ephy */
3257         rtl_hw_aspm_clkreq_enable(tp, false);
3258         rtl_ephy_init(tp, e_info_8168ep_1);
3259
3260         rtl_hw_start_8168ep(tp);
3261
3262         rtl_hw_aspm_clkreq_enable(tp, true);
3263 }
3264
3265 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
3266 {
3267         static const struct ephy_info e_info_8168ep_2[] = {
3268                 { 0x00, 0xffff, 0x10a3 },
3269                 { 0x19, 0xffff, 0xfc00 },
3270                 { 0x1e, 0xffff, 0x20ea }
3271         };
3272
3273         /* disable aspm and clock request before access ephy */
3274         rtl_hw_aspm_clkreq_enable(tp, false);
3275         rtl_ephy_init(tp, e_info_8168ep_2);
3276
3277         rtl_hw_start_8168ep(tp);
3278
3279         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3280         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3281
3282         rtl_hw_aspm_clkreq_enable(tp, true);
3283 }
3284
3285 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
3286 {
3287         static const struct ephy_info e_info_8168ep_3[] = {
3288                 { 0x00, 0x0000, 0x0080 },
3289                 { 0x0d, 0x0100, 0x0200 },
3290                 { 0x19, 0x8021, 0x0000 },
3291                 { 0x1e, 0x0000, 0x2000 },
3292         };
3293
3294         /* disable aspm and clock request before access ephy */
3295         rtl_hw_aspm_clkreq_enable(tp, false);
3296         rtl_ephy_init(tp, e_info_8168ep_3);
3297
3298         rtl_hw_start_8168ep(tp);
3299
3300         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3301         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3302
3303         r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271);
3304         r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
3305         r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);
3306
3307         rtl_hw_aspm_clkreq_enable(tp, true);
3308 }
3309
3310 static void rtl_hw_start_8117(struct rtl8169_private *tp)
3311 {
3312         static const struct ephy_info e_info_8117[] = {
3313                 { 0x19, 0x0040, 0x1100 },
3314                 { 0x59, 0x0040, 0x1100 },
3315         };
3316         int rg_saw_cnt;
3317
3318         rtl8168ep_stop_cmac(tp);
3319
3320         /* disable aspm and clock request before access ephy */
3321         rtl_hw_aspm_clkreq_enable(tp, false);
3322         rtl_ephy_init(tp, e_info_8117);
3323
3324         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3325         rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
3326
3327         rtl_set_def_aspm_entry_latency(tp);
3328
3329         rtl_reset_packet_filter(tp);
3330
3331         rtl_eri_set_bits(tp, 0xd4, 0x1f90);
3332
3333         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3334
3335         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
3336
3337         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3338         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3339
3340         rtl8168_config_eee_mac(tp);
3341
3342         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3343         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3344
3345         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3346
3347         rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
3348
3349         rtl_pcie_state_l2l3_disable(tp);
3350
3351         rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff;
3352         if (rg_saw_cnt > 0) {
3353                 u16 sw_cnt_1ms_ini;
3354
3355                 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff;
3356                 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);
3357         }
3358
3359         r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);
3360         r8168_mac_ocp_write(tp, 0xea80, 0x0003);
3361         r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009);
3362         r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);
3363
3364         r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
3365         r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
3366         r8168_mac_ocp_write(tp, 0xc094, 0x0000);
3367         r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
3368
3369         /* firmware is for MAC only */
3370         r8169_apply_firmware(tp);
3371
3372         rtl_hw_aspm_clkreq_enable(tp, true);
3373 }
3374
3375 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
3376 {
3377         static const struct ephy_info e_info_8102e_1[] = {
3378                 { 0x01, 0, 0x6e65 },
3379                 { 0x02, 0, 0x091f },
3380                 { 0x03, 0, 0xc2f9 },
3381                 { 0x06, 0, 0xafb5 },
3382                 { 0x07, 0, 0x0e00 },
3383                 { 0x19, 0, 0xec80 },
3384                 { 0x01, 0, 0x2e65 },
3385                 { 0x01, 0, 0x6e65 }
3386         };
3387         u8 cfg1;
3388
3389         rtl_set_def_aspm_entry_latency(tp);
3390
3391         RTL_W8(tp, DBG_REG, FIX_NAK_1);
3392
3393         RTL_W8(tp, Config1,
3394                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
3395         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3396
3397         cfg1 = RTL_R8(tp, Config1);
3398         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
3399                 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
3400
3401         rtl_ephy_init(tp, e_info_8102e_1);
3402 }
3403
3404 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
3405 {
3406         rtl_set_def_aspm_entry_latency(tp);
3407
3408         RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
3409         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3410 }
3411
3412 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
3413 {
3414         rtl_hw_start_8102e_2(tp);
3415
3416         rtl_ephy_write(tp, 0x03, 0xc2f9);
3417 }
3418
3419 static void rtl_hw_start_8401(struct rtl8169_private *tp)
3420 {
3421         static const struct ephy_info e_info_8401[] = {
3422                 { 0x01, 0xffff, 0x6fe5 },
3423                 { 0x03, 0xffff, 0x0599 },
3424                 { 0x06, 0xffff, 0xaf25 },
3425                 { 0x07, 0xffff, 0x8e68 },
3426         };
3427
3428         rtl_ephy_init(tp, e_info_8401);
3429         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3430 }
3431
3432 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
3433 {
3434         static const struct ephy_info e_info_8105e_1[] = {
3435                 { 0x07, 0, 0x4000 },
3436                 { 0x19, 0, 0x0200 },
3437                 { 0x19, 0, 0x0020 },
3438                 { 0x1e, 0, 0x2000 },
3439                 { 0x03, 0, 0x0001 },
3440                 { 0x19, 0, 0x0100 },
3441                 { 0x19, 0, 0x0004 },
3442                 { 0x0a, 0, 0x0020 }
3443         };
3444
3445         /* Force LAN exit from ASPM if Rx/Tx are not idle */
3446         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3447
3448         /* Disable Early Tally Counter */
3449         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
3450
3451         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
3452         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
3453
3454         rtl_ephy_init(tp, e_info_8105e_1);
3455
3456         rtl_pcie_state_l2l3_disable(tp);
3457 }
3458
3459 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
3460 {
3461         rtl_hw_start_8105e_1(tp);
3462         rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
3463 }
3464
3465 static void rtl_hw_start_8402(struct rtl8169_private *tp)
3466 {
3467         static const struct ephy_info e_info_8402[] = {
3468                 { 0x19, 0xffff, 0xff64 },
3469                 { 0x1e, 0, 0x4000 }
3470         };
3471
3472         rtl_set_def_aspm_entry_latency(tp);
3473
3474         /* Force LAN exit from ASPM if Rx/Tx are not idle */
3475         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3476
3477         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
3478
3479         rtl_ephy_init(tp, e_info_8402);
3480
3481         rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06);
3482         rtl_reset_packet_filter(tp);
3483         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3484         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3485         rtl_w0w1_eri(tp, 0x0d4, 0x0e00, 0xff00);
3486
3487         /* disable EEE */
3488         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3489
3490         rtl_pcie_state_l2l3_disable(tp);
3491 }
3492
3493 static void rtl_hw_start_8106(struct rtl8169_private *tp)
3494 {
3495         rtl_hw_aspm_clkreq_enable(tp, false);
3496
3497         /* Force LAN exit from ASPM if Rx/Tx are not idle */
3498         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3499
3500         RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
3501         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
3502         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3503
3504         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
3505
3506         /* disable EEE */
3507         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3508
3509         rtl_pcie_state_l2l3_disable(tp);
3510         rtl_hw_aspm_clkreq_enable(tp, true);
3511 }
3512
3513 DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond)
3514 {
3515         return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13);
3516 }
3517
3518 static void rtl_hw_start_8125_common(struct rtl8169_private *tp)
3519 {
3520         rtl_pcie_state_l2l3_disable(tp);
3521
3522         RTL_W16(tp, 0x382, 0x221b);
3523         RTL_W8(tp, 0x4500, 0);
3524         RTL_W16(tp, 0x4800, 0);
3525
3526         /* disable UPS */
3527         r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000);
3528
3529         RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10);
3530
3531         r8168_mac_ocp_write(tp, 0xc140, 0xffff);
3532         r8168_mac_ocp_write(tp, 0xc142, 0xffff);
3533
3534         r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9);
3535         r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
3536         r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);
3537
3538         /* disable new tx descriptor format */
3539         r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000);
3540
3541         if (tp->mac_version == RTL_GIGA_MAC_VER_63)
3542                 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200);
3543         else
3544                 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400);
3545
3546         if (tp->mac_version == RTL_GIGA_MAC_VER_63)
3547                 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0000);
3548         else
3549                 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020);
3550
3551         r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c);
3552         r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033);
3553         r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040);
3554         r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030);
3555         r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000);
3556         r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001);
3557         r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403);
3558         r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0068);
3559         r8168_mac_ocp_modify(tp, 0xc0ac, 0x0080, 0x1f00);
3560         r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f);
3561
3562         r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000);
3563         r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001);
3564         udelay(1);
3565         r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000);
3566         RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030);
3567
3568         r8168_mac_ocp_write(tp, 0xe098, 0xc302);
3569
3570         rtl_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10);
3571
3572         if (tp->mac_version == RTL_GIGA_MAC_VER_63)
3573                 rtl8125b_config_eee_mac(tp);
3574         else
3575                 rtl8125a_config_eee_mac(tp);
3576
3577         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
3578         udelay(10);
3579 }
3580
3581 static void rtl_hw_start_8125a_1(struct rtl8169_private *tp)
3582 {
3583         static const struct ephy_info e_info_8125a_1[] = {
3584                 { 0x01, 0xffff, 0xa812 },
3585                 { 0x09, 0xffff, 0x520c },
3586                 { 0x04, 0xffff, 0xd000 },
3587                 { 0x0d, 0xffff, 0xf702 },
3588                 { 0x0a, 0xffff, 0x8653 },
3589                 { 0x06, 0xffff, 0x001e },
3590                 { 0x08, 0xffff, 0x3595 },
3591                 { 0x20, 0xffff, 0x9455 },
3592                 { 0x21, 0xffff, 0x99ff },
3593                 { 0x02, 0xffff, 0x6046 },
3594                 { 0x29, 0xffff, 0xfe00 },
3595                 { 0x23, 0xffff, 0xab62 },
3596
3597                 { 0x41, 0xffff, 0xa80c },
3598                 { 0x49, 0xffff, 0x520c },
3599                 { 0x44, 0xffff, 0xd000 },
3600                 { 0x4d, 0xffff, 0xf702 },
3601                 { 0x4a, 0xffff, 0x8653 },
3602                 { 0x46, 0xffff, 0x001e },
3603                 { 0x48, 0xffff, 0x3595 },
3604                 { 0x60, 0xffff, 0x9455 },
3605                 { 0x61, 0xffff, 0x99ff },
3606                 { 0x42, 0xffff, 0x6046 },
3607                 { 0x69, 0xffff, 0xfe00 },
3608                 { 0x63, 0xffff, 0xab62 },
3609         };
3610
3611         rtl_set_def_aspm_entry_latency(tp);
3612
3613         /* disable aspm and clock request before access ephy */
3614         rtl_hw_aspm_clkreq_enable(tp, false);
3615         rtl_ephy_init(tp, e_info_8125a_1);
3616
3617         rtl_hw_start_8125_common(tp);
3618         rtl_hw_aspm_clkreq_enable(tp, true);
3619 }
3620
3621 static void rtl_hw_start_8125a_2(struct rtl8169_private *tp)
3622 {
3623         static const struct ephy_info e_info_8125a_2[] = {
3624                 { 0x04, 0xffff, 0xd000 },
3625                 { 0x0a, 0xffff, 0x8653 },
3626                 { 0x23, 0xffff, 0xab66 },
3627                 { 0x20, 0xffff, 0x9455 },
3628                 { 0x21, 0xffff, 0x99ff },
3629                 { 0x29, 0xffff, 0xfe04 },
3630
3631                 { 0x44, 0xffff, 0xd000 },
3632                 { 0x4a, 0xffff, 0x8653 },
3633                 { 0x63, 0xffff, 0xab66 },
3634                 { 0x60, 0xffff, 0x9455 },
3635                 { 0x61, 0xffff, 0x99ff },
3636                 { 0x69, 0xffff, 0xfe04 },
3637         };
3638
3639         rtl_set_def_aspm_entry_latency(tp);
3640
3641         /* disable aspm and clock request before access ephy */
3642         rtl_hw_aspm_clkreq_enable(tp, false);
3643         rtl_ephy_init(tp, e_info_8125a_2);
3644
3645         rtl_hw_start_8125_common(tp);
3646         rtl_hw_aspm_clkreq_enable(tp, true);
3647 }
3648
3649 static void rtl_hw_start_8125b(struct rtl8169_private *tp)
3650 {
3651         static const struct ephy_info e_info_8125b[] = {
3652                 { 0x0b, 0xffff, 0xa908 },
3653                 { 0x1e, 0xffff, 0x20eb },
3654                 { 0x4b, 0xffff, 0xa908 },
3655                 { 0x5e, 0xffff, 0x20eb },
3656                 { 0x22, 0x0030, 0x0020 },
3657                 { 0x62, 0x0030, 0x0020 },
3658         };
3659
3660         rtl_set_def_aspm_entry_latency(tp);
3661         rtl_hw_aspm_clkreq_enable(tp, false);
3662
3663         rtl_ephy_init(tp, e_info_8125b);
3664         rtl_hw_start_8125_common(tp);
3665
3666         rtl_hw_aspm_clkreq_enable(tp, true);
3667 }
3668
3669 static void rtl_hw_config(struct rtl8169_private *tp)
3670 {
3671         static const rtl_generic_fct hw_configs[] = {
3672                 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1,
3673                 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3,
3674                 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2,
3675                 [RTL_GIGA_MAC_VER_10] = NULL,
3676                 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168b,
3677                 [RTL_GIGA_MAC_VER_12] = rtl_hw_start_8168b,
3678                 [RTL_GIGA_MAC_VER_13] = NULL,
3679                 [RTL_GIGA_MAC_VER_14] = rtl_hw_start_8401,
3680                 [RTL_GIGA_MAC_VER_16] = NULL,
3681                 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b,
3682                 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1,
3683                 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1,
3684                 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2,
3685                 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_3,
3686                 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4,
3687                 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2,
3688                 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3,
3689                 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d,
3690                 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d,
3691                 [RTL_GIGA_MAC_VER_27] = rtl_hw_start_8168d,
3692                 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4,
3693                 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1,
3694                 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2,
3695                 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168d,
3696                 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1,
3697                 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1,
3698                 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2,
3699                 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1,
3700                 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1,
3701                 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402,
3702                 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411,
3703                 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106,
3704                 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1,
3705                 [RTL_GIGA_MAC_VER_41] = rtl_hw_start_8168g_1,
3706                 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2,
3707                 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2,
3708                 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2,
3709                 [RTL_GIGA_MAC_VER_45] = rtl_hw_start_8168h_1,
3710                 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1,
3711                 [RTL_GIGA_MAC_VER_47] = rtl_hw_start_8168h_1,
3712                 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1,
3713                 [RTL_GIGA_MAC_VER_49] = rtl_hw_start_8168ep_1,
3714                 [RTL_GIGA_MAC_VER_50] = rtl_hw_start_8168ep_2,
3715                 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3,
3716                 [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117,
3717                 [RTL_GIGA_MAC_VER_60] = rtl_hw_start_8125a_1,
3718                 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2,
3719                 [RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b,
3720         };
3721
3722         if (hw_configs[tp->mac_version])
3723                 hw_configs[tp->mac_version](tp);
3724 }
3725
3726 static void rtl_hw_start_8125(struct rtl8169_private *tp)
3727 {
3728         int i;
3729
3730         /* disable interrupt coalescing */
3731         for (i = 0xa00; i < 0xb00; i += 4)
3732                 RTL_W32(tp, i, 0);
3733
3734         rtl_hw_config(tp);
3735 }
3736
3737 static void rtl_hw_start_8168(struct rtl8169_private *tp)
3738 {
3739         if (rtl_is_8168evl_up(tp))
3740                 RTL_W8(tp, MaxTxPacketSize, EarlySize);
3741         else
3742                 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
3743
3744         rtl_hw_config(tp);
3745
3746         /* disable interrupt coalescing */
3747         RTL_W16(tp, IntrMitigate, 0x0000);
3748 }
3749
3750 static void rtl_hw_start_8169(struct rtl8169_private *tp)
3751 {
3752         RTL_W8(tp, EarlyTxThres, NoEarlyTx);
3753
3754         tp->cp_cmd |= PCIMulRW;
3755
3756         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3757             tp->mac_version == RTL_GIGA_MAC_VER_03)
3758                 tp->cp_cmd |= EnAnaPLL;
3759
3760         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
3761
3762         rtl8169_set_magic_reg(tp);
3763
3764         /* disable interrupt coalescing */
3765         RTL_W16(tp, IntrMitigate, 0x0000);
3766 }
3767
3768 static void rtl_hw_start(struct  rtl8169_private *tp)
3769 {
3770         rtl_unlock_config_regs(tp);
3771
3772         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
3773
3774         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3775                 rtl_hw_start_8169(tp);
3776         else if (rtl_is_8125(tp))
3777                 rtl_hw_start_8125(tp);
3778         else
3779                 rtl_hw_start_8168(tp);
3780
3781         rtl_set_rx_max_size(tp);
3782         rtl_set_rx_tx_desc_registers(tp);
3783         rtl_lock_config_regs(tp);
3784
3785         rtl_jumbo_config(tp);
3786
3787         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3788         rtl_pci_commit(tp);
3789
3790         RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
3791         rtl_init_rxcfg(tp);
3792         rtl_set_tx_config_registers(tp);
3793         rtl_set_rx_config_features(tp, tp->dev->features);
3794         rtl_set_rx_mode(tp->dev);
3795         rtl_irq_enable(tp);
3796 }
3797
3798 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
3799 {
3800         struct rtl8169_private *tp = netdev_priv(dev);
3801
3802         dev->mtu = new_mtu;
3803         netdev_update_features(dev);
3804         rtl_jumbo_config(tp);
3805
3806         switch (tp->mac_version) {
3807         case RTL_GIGA_MAC_VER_61:
3808         case RTL_GIGA_MAC_VER_63:
3809                 rtl8125_set_eee_txidle_timer(tp);
3810                 break;
3811         default:
3812                 break;
3813         }
3814
3815         return 0;
3816 }
3817
3818 static void rtl8169_mark_to_asic(struct RxDesc *desc)
3819 {
3820         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
3821
3822         desc->opts2 = 0;
3823         /* Force memory writes to complete before releasing descriptor */
3824         dma_wmb();
3825         WRITE_ONCE(desc->opts1, cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE));
3826 }
3827
3828 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
3829                                           struct RxDesc *desc)
3830 {
3831         struct device *d = tp_to_dev(tp);
3832         int node = dev_to_node(d);
3833         dma_addr_t mapping;
3834         struct page *data;
3835
3836         data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE));
3837         if (!data)
3838                 return NULL;
3839
3840         mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
3841         if (unlikely(dma_mapping_error(d, mapping))) {
3842                 netdev_err(tp->dev, "Failed to map RX DMA!\n");
3843                 __free_pages(data, get_order(R8169_RX_BUF_SIZE));
3844                 return NULL;
3845         }
3846
3847         desc->addr = cpu_to_le64(mapping);
3848         rtl8169_mark_to_asic(desc);
3849
3850         return data;
3851 }
3852
3853 static void rtl8169_rx_clear(struct rtl8169_private *tp)
3854 {
3855         unsigned int i;
3856
3857         for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) {
3858                 dma_unmap_page(tp_to_dev(tp),
3859                                le64_to_cpu(tp->RxDescArray[i].addr),
3860                                R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
3861                 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE));
3862                 tp->Rx_databuff[i] = NULL;
3863                 tp->RxDescArray[i].addr = 0;
3864                 tp->RxDescArray[i].opts1 = 0;
3865         }
3866 }
3867
3868 static int rtl8169_rx_fill(struct rtl8169_private *tp)
3869 {
3870         unsigned int i;
3871
3872         for (i = 0; i < NUM_RX_DESC; i++) {
3873                 struct page *data;
3874
3875                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
3876                 if (!data) {
3877                         rtl8169_rx_clear(tp);
3878                         return -ENOMEM;
3879                 }
3880                 tp->Rx_databuff[i] = data;
3881         }
3882
3883         /* mark as last descriptor in the ring */
3884         tp->RxDescArray[NUM_RX_DESC - 1].opts1 |= cpu_to_le32(RingEnd);
3885
3886         return 0;
3887 }
3888
3889 static int rtl8169_init_ring(struct rtl8169_private *tp)
3890 {
3891         rtl8169_init_ring_indexes(tp);
3892
3893         memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
3894         memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
3895
3896         return rtl8169_rx_fill(tp);
3897 }
3898
3899 static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int entry)
3900 {
3901         struct ring_info *tx_skb = tp->tx_skb + entry;
3902         struct TxDesc *desc = tp->TxDescArray + entry;
3903
3904         dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), tx_skb->len,
3905                          DMA_TO_DEVICE);
3906         memset(desc, 0, sizeof(*desc));
3907         memset(tx_skb, 0, sizeof(*tx_skb));
3908 }
3909
3910 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
3911                                    unsigned int n)
3912 {
3913         unsigned int i;
3914
3915         for (i = 0; i < n; i++) {
3916                 unsigned int entry = (start + i) % NUM_TX_DESC;
3917                 struct ring_info *tx_skb = tp->tx_skb + entry;
3918                 unsigned int len = tx_skb->len;
3919
3920                 if (len) {
3921                         struct sk_buff *skb = tx_skb->skb;
3922
3923                         rtl8169_unmap_tx_skb(tp, entry);
3924                         if (skb)
3925                                 dev_consume_skb_any(skb);
3926                 }
3927         }
3928 }
3929
3930 static void rtl8169_tx_clear(struct rtl8169_private *tp)
3931 {
3932         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
3933         netdev_reset_queue(tp->dev);
3934 }
3935
3936 static void rtl8169_cleanup(struct rtl8169_private *tp, bool going_down)
3937 {
3938         napi_disable(&tp->napi);
3939
3940         /* Give a racing hard_start_xmit a few cycles to complete. */
3941         synchronize_net();
3942
3943         /* Disable interrupts */
3944         rtl8169_irq_mask_and_ack(tp);
3945
3946         rtl_rx_close(tp);
3947
3948         if (going_down && tp->dev->wol_enabled)
3949                 goto no_reset;
3950
3951         switch (tp->mac_version) {
3952         case RTL_GIGA_MAC_VER_27:
3953         case RTL_GIGA_MAC_VER_28:
3954         case RTL_GIGA_MAC_VER_31:
3955                 rtl_loop_wait_low(tp, &rtl_npq_cond, 20, 2000);
3956                 break;
3957         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
3958                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
3959                 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
3960                 break;
3961         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
3962                 rtl_enable_rxdvgate(tp);
3963                 fsleep(2000);
3964                 break;
3965         default:
3966                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
3967                 fsleep(100);
3968                 break;
3969         }
3970
3971         rtl_hw_reset(tp);
3972 no_reset:
3973         rtl8169_tx_clear(tp);
3974         rtl8169_init_ring_indexes(tp);
3975 }
3976
3977 static void rtl_reset_work(struct rtl8169_private *tp)
3978 {
3979         int i;
3980
3981         netif_stop_queue(tp->dev);
3982
3983         rtl8169_cleanup(tp, false);
3984
3985         for (i = 0; i < NUM_RX_DESC; i++)
3986                 rtl8169_mark_to_asic(tp->RxDescArray + i);
3987
3988         napi_enable(&tp->napi);
3989         rtl_hw_start(tp);
3990 }
3991
3992 static void rtl8169_tx_timeout(struct net_device *dev, unsigned int txqueue)
3993 {
3994         struct rtl8169_private *tp = netdev_priv(dev);
3995
3996         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
3997 }
3998
3999 static int rtl8169_tx_map(struct rtl8169_private *tp, const u32 *opts, u32 len,
4000                           void *addr, unsigned int entry, bool desc_own)
4001 {
4002         struct TxDesc *txd = tp->TxDescArray + entry;
4003         struct device *d = tp_to_dev(tp);
4004         dma_addr_t mapping;
4005         u32 opts1;
4006         int ret;
4007
4008         mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
4009         ret = dma_mapping_error(d, mapping);
4010         if (unlikely(ret)) {
4011                 if (net_ratelimit())
4012                         netdev_err(tp->dev, "Failed to map TX data!\n");
4013                 return ret;
4014         }
4015
4016         txd->addr = cpu_to_le64(mapping);
4017         txd->opts2 = cpu_to_le32(opts[1]);
4018
4019         opts1 = opts[0] | len;
4020         if (entry == NUM_TX_DESC - 1)
4021                 opts1 |= RingEnd;
4022         if (desc_own)
4023                 opts1 |= DescOwn;
4024         txd->opts1 = cpu_to_le32(opts1);
4025
4026         tp->tx_skb[entry].len = len;
4027
4028         return 0;
4029 }
4030
4031 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4032                               const u32 *opts, unsigned int entry)
4033 {
4034         struct skb_shared_info *info = skb_shinfo(skb);
4035         unsigned int cur_frag;
4036
4037         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4038                 const skb_frag_t *frag = info->frags + cur_frag;
4039                 void *addr = skb_frag_address(frag);
4040                 u32 len = skb_frag_size(frag);
4041
4042                 entry = (entry + 1) % NUM_TX_DESC;
4043
4044                 if (unlikely(rtl8169_tx_map(tp, opts, len, addr, entry, true)))
4045                         goto err_out;
4046         }
4047
4048         return 0;
4049
4050 err_out:
4051         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
4052         return -EIO;
4053 }
4054
4055 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
4056 {
4057         return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
4058 }
4059
4060 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts)
4061 {
4062         u32 mss = skb_shinfo(skb)->gso_size;
4063
4064         if (mss) {
4065                 opts[0] |= TD_LSO;
4066                 opts[0] |= mss << TD0_MSS_SHIFT;
4067         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4068                 const struct iphdr *ip = ip_hdr(skb);
4069
4070                 if (ip->protocol == IPPROTO_TCP)
4071                         opts[0] |= TD0_IP_CS | TD0_TCP_CS;
4072                 else if (ip->protocol == IPPROTO_UDP)
4073                         opts[0] |= TD0_IP_CS | TD0_UDP_CS;
4074                 else
4075                         WARN_ON_ONCE(1);
4076         }
4077 }
4078
4079 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
4080                                 struct sk_buff *skb, u32 *opts)
4081 {
4082         u32 transport_offset = (u32)skb_transport_offset(skb);
4083         struct skb_shared_info *shinfo = skb_shinfo(skb);
4084         u32 mss = shinfo->gso_size;
4085
4086         if (mss) {
4087                 if (shinfo->gso_type & SKB_GSO_TCPV4) {
4088                         opts[0] |= TD1_GTSENV4;
4089                 } else if (shinfo->gso_type & SKB_GSO_TCPV6) {
4090                         if (skb_cow_head(skb, 0))
4091                                 return false;
4092
4093                         tcp_v6_gso_csum_prep(skb);
4094                         opts[0] |= TD1_GTSENV6;
4095                 } else {
4096                         WARN_ON_ONCE(1);
4097                 }
4098
4099                 opts[0] |= transport_offset << GTTCPHO_SHIFT;
4100                 opts[1] |= mss << TD1_MSS_SHIFT;
4101         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4102                 u8 ip_protocol;
4103
4104                 switch (vlan_get_protocol(skb)) {
4105                 case htons(ETH_P_IP):
4106                         opts[1] |= TD1_IPv4_CS;
4107                         ip_protocol = ip_hdr(skb)->protocol;
4108                         break;
4109
4110                 case htons(ETH_P_IPV6):
4111                         opts[1] |= TD1_IPv6_CS;
4112                         ip_protocol = ipv6_hdr(skb)->nexthdr;
4113                         break;
4114
4115                 default:
4116                         ip_protocol = IPPROTO_RAW;
4117                         break;
4118                 }
4119
4120                 if (ip_protocol == IPPROTO_TCP)
4121                         opts[1] |= TD1_TCP_CS;
4122                 else if (ip_protocol == IPPROTO_UDP)
4123                         opts[1] |= TD1_UDP_CS;
4124                 else
4125                         WARN_ON_ONCE(1);
4126
4127                 opts[1] |= transport_offset << TCPHO_SHIFT;
4128         } else {
4129                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
4130                         return !eth_skb_pad(skb);
4131         }
4132
4133         return true;
4134 }
4135
4136 static bool rtl_tx_slots_avail(struct rtl8169_private *tp,
4137                                unsigned int nr_frags)
4138 {
4139         unsigned int slots_avail = tp->dirty_tx + NUM_TX_DESC - tp->cur_tx;
4140
4141         /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
4142         return slots_avail > nr_frags;
4143 }
4144
4145 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */
4146 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
4147 {
4148         switch (tp->mac_version) {
4149         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
4150         case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
4151                 return false;
4152         default:
4153                 return true;
4154         }
4155 }
4156
4157 static void rtl8169_doorbell(struct rtl8169_private *tp)
4158 {
4159         if (rtl_is_8125(tp))
4160                 RTL_W16(tp, TxPoll_8125, BIT(0));
4161         else
4162                 RTL_W8(tp, TxPoll, NPQ);
4163 }
4164
4165 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4166                                       struct net_device *dev)
4167 {
4168         unsigned int frags = skb_shinfo(skb)->nr_frags;
4169         struct rtl8169_private *tp = netdev_priv(dev);
4170         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
4171         struct TxDesc *txd_first, *txd_last;
4172         bool stop_queue, door_bell;
4173         u32 opts[2];
4174
4175         txd_first = tp->TxDescArray + entry;
4176
4177         if (unlikely(!rtl_tx_slots_avail(tp, frags))) {
4178                 if (net_ratelimit())
4179                         netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
4180                 goto err_stop_0;
4181         }
4182
4183         if (unlikely(le32_to_cpu(txd_first->opts1) & DescOwn))
4184                 goto err_stop_0;
4185
4186         opts[1] = rtl8169_tx_vlan_tag(skb);
4187         opts[0] = 0;
4188
4189         if (!rtl_chip_supports_csum_v2(tp))
4190                 rtl8169_tso_csum_v1(skb, opts);
4191         else if (!rtl8169_tso_csum_v2(tp, skb, opts))
4192                 goto err_dma_0;
4193
4194         if (unlikely(rtl8169_tx_map(tp, opts, skb_headlen(skb), skb->data,
4195                                     entry, false)))
4196                 goto err_dma_0;
4197
4198         if (frags) {
4199                 if (rtl8169_xmit_frags(tp, skb, opts, entry))
4200                         goto err_dma_1;
4201                 entry = (entry + frags) % NUM_TX_DESC;
4202         }
4203
4204         txd_last = tp->TxDescArray + entry;
4205         txd_last->opts1 |= cpu_to_le32(LastFrag);
4206         tp->tx_skb[entry].skb = skb;
4207
4208         skb_tx_timestamp(skb);
4209
4210         /* Force memory writes to complete before releasing descriptor */
4211         dma_wmb();
4212
4213         door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more());
4214
4215         txd_first->opts1 |= cpu_to_le32(DescOwn | FirstFrag);
4216
4217         /* rtl_tx needs to see descriptor changes before updated tp->cur_tx */
4218         smp_wmb();
4219
4220         tp->cur_tx += frags + 1;
4221
4222         stop_queue = !rtl_tx_slots_avail(tp, MAX_SKB_FRAGS);
4223         if (unlikely(stop_queue)) {
4224                 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
4225                  * not miss a ring update when it notices a stopped queue.
4226                  */
4227                 smp_wmb();
4228                 netif_stop_queue(dev);
4229                 door_bell = true;
4230         }
4231
4232         if (door_bell)
4233                 rtl8169_doorbell(tp);
4234
4235         if (unlikely(stop_queue)) {
4236                 /* Sync with rtl_tx:
4237                  * - publish queue status and cur_tx ring index (write barrier)
4238                  * - refresh dirty_tx ring index (read barrier).
4239                  * May the current thread have a pessimistic view of the ring
4240                  * status and forget to wake up queue, a racing rtl_tx thread
4241                  * can't.
4242                  */
4243                 smp_mb();
4244                 if (rtl_tx_slots_avail(tp, MAX_SKB_FRAGS))
4245                         netif_start_queue(dev);
4246         }
4247
4248         return NETDEV_TX_OK;
4249
4250 err_dma_1:
4251         rtl8169_unmap_tx_skb(tp, entry);
4252 err_dma_0:
4253         dev_kfree_skb_any(skb);
4254         dev->stats.tx_dropped++;
4255         return NETDEV_TX_OK;
4256
4257 err_stop_0:
4258         netif_stop_queue(dev);
4259         dev->stats.tx_dropped++;
4260         return NETDEV_TX_BUSY;
4261 }
4262
4263 static unsigned int rtl_last_frag_len(struct sk_buff *skb)
4264 {
4265         struct skb_shared_info *info = skb_shinfo(skb);
4266         unsigned int nr_frags = info->nr_frags;
4267
4268         if (!nr_frags)
4269                 return UINT_MAX;
4270
4271         return skb_frag_size(info->frags + nr_frags - 1);
4272 }
4273
4274 /* Workaround for hw issues with TSO on RTL8168evl */
4275 static netdev_features_t rtl8168evl_fix_tso(struct sk_buff *skb,
4276                                             netdev_features_t features)
4277 {
4278         /* IPv4 header has options field */
4279         if (vlan_get_protocol(skb) == htons(ETH_P_IP) &&
4280             ip_hdrlen(skb) > sizeof(struct iphdr))
4281                 features &= ~NETIF_F_ALL_TSO;
4282
4283         /* IPv4 TCP header has options field */
4284         else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4 &&
4285                  tcp_hdrlen(skb) > sizeof(struct tcphdr))
4286                 features &= ~NETIF_F_ALL_TSO;
4287
4288         else if (rtl_last_frag_len(skb) <= 6)
4289                 features &= ~NETIF_F_ALL_TSO;
4290
4291         return features;
4292 }
4293
4294 static netdev_features_t rtl8169_features_check(struct sk_buff *skb,
4295                                                 struct net_device *dev,
4296                                                 netdev_features_t features)
4297 {
4298         int transport_offset = skb_transport_offset(skb);
4299         struct rtl8169_private *tp = netdev_priv(dev);
4300
4301         if (skb_is_gso(skb)) {
4302                 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4303                         features = rtl8168evl_fix_tso(skb, features);
4304
4305                 if (transport_offset > GTTCPHO_MAX &&
4306                     rtl_chip_supports_csum_v2(tp))
4307                         features &= ~NETIF_F_ALL_TSO;
4308         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4309                 if (skb->len < ETH_ZLEN) {
4310                         switch (tp->mac_version) {
4311                         case RTL_GIGA_MAC_VER_11:
4312                         case RTL_GIGA_MAC_VER_12:
4313                         case RTL_GIGA_MAC_VER_17:
4314                         case RTL_GIGA_MAC_VER_34:
4315                                 features &= ~NETIF_F_CSUM_MASK;
4316                                 break;
4317                         default:
4318                                 break;
4319                         }
4320                 }
4321
4322                 if (transport_offset > TCPHO_MAX &&
4323                     rtl_chip_supports_csum_v2(tp))
4324                         features &= ~NETIF_F_CSUM_MASK;
4325         }
4326
4327         return vlan_features_check(skb, features);
4328 }
4329
4330 static void rtl8169_pcierr_interrupt(struct net_device *dev)
4331 {
4332         struct rtl8169_private *tp = netdev_priv(dev);
4333         struct pci_dev *pdev = tp->pci_dev;
4334         int pci_status_errs;
4335         u16 pci_cmd;
4336
4337         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4338
4339         pci_status_errs = pci_status_get_and_clear_errors(pdev);
4340
4341         if (net_ratelimit())
4342                 netdev_err(dev, "PCI error (cmd = 0x%04x, status_errs = 0x%04x)\n",
4343                            pci_cmd, pci_status_errs);
4344         /*
4345          * The recovery sequence below admits a very elaborated explanation:
4346          * - it seems to work;
4347          * - I did not see what else could be done;
4348          * - it makes iop3xx happy.
4349          *
4350          * Feel free to adjust to your needs.
4351          */
4352         if (pdev->broken_parity_status)
4353                 pci_cmd &= ~PCI_COMMAND_PARITY;
4354         else
4355                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
4356
4357         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
4358
4359         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
4360 }
4361
4362 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp,
4363                    int budget)
4364 {
4365         unsigned int dirty_tx, tx_left, bytes_compl = 0, pkts_compl = 0;
4366
4367         dirty_tx = tp->dirty_tx;
4368         smp_rmb();
4369
4370         for (tx_left = tp->cur_tx - dirty_tx; tx_left > 0; tx_left--) {
4371                 unsigned int entry = dirty_tx % NUM_TX_DESC;
4372                 struct sk_buff *skb = tp->tx_skb[entry].skb;
4373                 u32 status;
4374
4375                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
4376                 if (status & DescOwn)
4377                         break;
4378
4379                 rtl8169_unmap_tx_skb(tp, entry);
4380
4381                 if (skb) {
4382                         pkts_compl++;
4383                         bytes_compl += skb->len;
4384                         napi_consume_skb(skb, budget);
4385                 }
4386                 dirty_tx++;
4387         }
4388
4389         if (tp->dirty_tx != dirty_tx) {
4390                 netdev_completed_queue(dev, pkts_compl, bytes_compl);
4391
4392                 u64_stats_update_begin(&tp->tx_stats.syncp);
4393                 tp->tx_stats.packets += pkts_compl;
4394                 tp->tx_stats.bytes += bytes_compl;
4395                 u64_stats_update_end(&tp->tx_stats.syncp);
4396
4397                 tp->dirty_tx = dirty_tx;
4398                 /* Sync with rtl8169_start_xmit:
4399                  * - publish dirty_tx ring index (write barrier)
4400                  * - refresh cur_tx ring index and queue status (read barrier)
4401                  * May the current thread miss the stopped queue condition,
4402                  * a racing xmit thread can only have a right view of the
4403                  * ring status.
4404                  */
4405                 smp_mb();
4406                 if (netif_queue_stopped(dev) &&
4407                     rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) {
4408                         netif_wake_queue(dev);
4409                 }
4410                 /*
4411                  * 8168 hack: TxPoll requests are lost when the Tx packets are
4412                  * too close. Let's kick an extra TxPoll request when a burst
4413                  * of start_xmit activity is detected (if it is not detected,
4414                  * it is slow enough). -- FR
4415                  */
4416                 if (tp->cur_tx != dirty_tx)
4417                         rtl8169_doorbell(tp);
4418         }
4419 }
4420
4421 static inline int rtl8169_fragmented_frame(u32 status)
4422 {
4423         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4424 }
4425
4426 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
4427 {
4428         u32 status = opts1 & RxProtoMask;
4429
4430         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
4431             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
4432                 skb->ip_summed = CHECKSUM_UNNECESSARY;
4433         else
4434                 skb_checksum_none_assert(skb);
4435 }
4436
4437 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
4438 {
4439         unsigned int cur_rx, rx_left, count;
4440         struct device *d = tp_to_dev(tp);
4441
4442         cur_rx = tp->cur_rx;
4443
4444         for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
4445                 unsigned int pkt_size, entry = cur_rx % NUM_RX_DESC;
4446                 struct RxDesc *desc = tp->RxDescArray + entry;
4447                 struct sk_buff *skb;
4448                 const void *rx_buf;
4449                 dma_addr_t addr;
4450                 u32 status;
4451
4452                 status = le32_to_cpu(desc->opts1);
4453                 if (status & DescOwn)
4454                         break;
4455
4456                 /* This barrier is needed to keep us from reading
4457                  * any other fields out of the Rx descriptor until
4458                  * we know the status of DescOwn
4459                  */
4460                 dma_rmb();
4461
4462                 if (unlikely(status & RxRES)) {
4463                         if (net_ratelimit())
4464                                 netdev_warn(dev, "Rx ERROR. status = %08x\n",
4465                                             status);
4466                         dev->stats.rx_errors++;
4467                         if (status & (RxRWT | RxRUNT))
4468                                 dev->stats.rx_length_errors++;
4469                         if (status & RxCRC)
4470                                 dev->stats.rx_crc_errors++;
4471
4472                         if (!(dev->features & NETIF_F_RXALL))
4473                                 goto release_descriptor;
4474                         else if (status & RxRWT || !(status & (RxRUNT | RxCRC)))
4475                                 goto release_descriptor;
4476                 }
4477
4478                 pkt_size = status & GENMASK(13, 0);
4479                 if (likely(!(dev->features & NETIF_F_RXFCS)))
4480                         pkt_size -= ETH_FCS_LEN;
4481
4482                 /* The driver does not support incoming fragmented frames.
4483                  * They are seen as a symptom of over-mtu sized frames.
4484                  */
4485                 if (unlikely(rtl8169_fragmented_frame(status))) {
4486                         dev->stats.rx_dropped++;
4487                         dev->stats.rx_length_errors++;
4488                         goto release_descriptor;
4489                 }
4490
4491                 skb = napi_alloc_skb(&tp->napi, pkt_size);
4492                 if (unlikely(!skb)) {
4493                         dev->stats.rx_dropped++;
4494                         goto release_descriptor;
4495                 }
4496
4497                 addr = le64_to_cpu(desc->addr);
4498                 rx_buf = page_address(tp->Rx_databuff[entry]);
4499
4500                 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
4501                 prefetch(rx_buf);
4502                 skb_copy_to_linear_data(skb, rx_buf, pkt_size);
4503                 skb->tail += pkt_size;
4504                 skb->len = pkt_size;
4505                 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
4506
4507                 rtl8169_rx_csum(skb, status);
4508                 skb->protocol = eth_type_trans(skb, dev);
4509
4510                 rtl8169_rx_vlan_tag(desc, skb);
4511
4512                 if (skb->pkt_type == PACKET_MULTICAST)
4513                         dev->stats.multicast++;
4514
4515                 napi_gro_receive(&tp->napi, skb);
4516
4517                 u64_stats_update_begin(&tp->rx_stats.syncp);
4518                 tp->rx_stats.packets++;
4519                 tp->rx_stats.bytes += pkt_size;
4520                 u64_stats_update_end(&tp->rx_stats.syncp);
4521
4522 release_descriptor:
4523                 rtl8169_mark_to_asic(desc);
4524         }
4525
4526         count = cur_rx - tp->cur_rx;
4527         tp->cur_rx = cur_rx;
4528
4529         return count;
4530 }
4531
4532 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
4533 {
4534         struct rtl8169_private *tp = dev_instance;
4535         u32 status = rtl_get_events(tp);
4536
4537         if ((status & 0xffff) == 0xffff || !(status & tp->irq_mask))
4538                 return IRQ_NONE;
4539
4540         if (unlikely(status & SYSErr)) {
4541                 rtl8169_pcierr_interrupt(tp->dev);
4542                 goto out;
4543         }
4544
4545         if (status & LinkChg)
4546                 phy_mac_interrupt(tp->phydev);
4547
4548         if (unlikely(status & RxFIFOOver &&
4549             tp->mac_version == RTL_GIGA_MAC_VER_11)) {
4550                 netif_stop_queue(tp->dev);
4551                 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
4552         }
4553
4554         rtl_irq_disable(tp);
4555         napi_schedule_irqoff(&tp->napi);
4556 out:
4557         rtl_ack_events(tp, status);
4558
4559         return IRQ_HANDLED;
4560 }
4561
4562 static void rtl_task(struct work_struct *work)
4563 {
4564         struct rtl8169_private *tp =
4565                 container_of(work, struct rtl8169_private, wk.work);
4566
4567         rtnl_lock();
4568
4569         if (!netif_running(tp->dev) ||
4570             !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
4571                 goto out_unlock;
4572
4573         if (test_and_clear_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags)) {
4574                 rtl_reset_work(tp);
4575                 netif_wake_queue(tp->dev);
4576         }
4577 out_unlock:
4578         rtnl_unlock();
4579 }
4580
4581 static int rtl8169_poll(struct napi_struct *napi, int budget)
4582 {
4583         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
4584         struct net_device *dev = tp->dev;
4585         int work_done;
4586
4587         work_done = rtl_rx(dev, tp, (u32) budget);
4588
4589         rtl_tx(dev, tp, budget);
4590
4591         if (work_done < budget && napi_complete_done(napi, work_done))
4592                 rtl_irq_enable(tp);
4593
4594         return work_done;
4595 }
4596
4597 static void r8169_phylink_handler(struct net_device *ndev)
4598 {
4599         struct rtl8169_private *tp = netdev_priv(ndev);
4600
4601         if (netif_carrier_ok(ndev)) {
4602                 rtl_link_chg_patch(tp);
4603                 pm_request_resume(&tp->pci_dev->dev);
4604         } else {
4605                 pm_runtime_idle(&tp->pci_dev->dev);
4606         }
4607
4608         if (net_ratelimit())
4609                 phy_print_status(tp->phydev);
4610 }
4611
4612 static int r8169_phy_connect(struct rtl8169_private *tp)
4613 {
4614         struct phy_device *phydev = tp->phydev;
4615         phy_interface_t phy_mode;
4616         int ret;
4617
4618         phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
4619                    PHY_INTERFACE_MODE_MII;
4620
4621         ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
4622                                  phy_mode);
4623         if (ret)
4624                 return ret;
4625
4626         if (!tp->supports_gmii)
4627                 phy_set_max_speed(phydev, SPEED_100);
4628
4629         phy_support_asym_pause(phydev);
4630
4631         phy_attached_info(phydev);
4632
4633         return 0;
4634 }
4635
4636 static void rtl8169_down(struct rtl8169_private *tp)
4637 {
4638         /* Clear all task flags */
4639         bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
4640
4641         phy_stop(tp->phydev);
4642
4643         rtl8169_update_counters(tp);
4644
4645         rtl8169_cleanup(tp, true);
4646
4647         rtl_pll_power_down(tp);
4648 }
4649
4650 static void rtl8169_up(struct rtl8169_private *tp)
4651 {
4652         rtl_pll_power_up(tp);
4653         rtl8169_init_phy(tp);
4654         napi_enable(&tp->napi);
4655         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
4656         rtl_reset_work(tp);
4657
4658         phy_start(tp->phydev);
4659 }
4660
4661 static int rtl8169_close(struct net_device *dev)
4662 {
4663         struct rtl8169_private *tp = netdev_priv(dev);
4664         struct pci_dev *pdev = tp->pci_dev;
4665
4666         pm_runtime_get_sync(&pdev->dev);
4667
4668         netif_stop_queue(dev);
4669         rtl8169_down(tp);
4670         rtl8169_rx_clear(tp);
4671
4672         cancel_work_sync(&tp->wk.work);
4673
4674         phy_disconnect(tp->phydev);
4675
4676         pci_free_irq(pdev, 0, tp);
4677
4678         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4679                           tp->RxPhyAddr);
4680         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4681                           tp->TxPhyAddr);
4682         tp->TxDescArray = NULL;
4683         tp->RxDescArray = NULL;
4684
4685         pm_runtime_put_sync(&pdev->dev);
4686
4687         return 0;
4688 }
4689
4690 #ifdef CONFIG_NET_POLL_CONTROLLER
4691 static void rtl8169_netpoll(struct net_device *dev)
4692 {
4693         struct rtl8169_private *tp = netdev_priv(dev);
4694
4695         rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp);
4696 }
4697 #endif
4698
4699 static int rtl_open(struct net_device *dev)
4700 {
4701         struct rtl8169_private *tp = netdev_priv(dev);
4702         struct pci_dev *pdev = tp->pci_dev;
4703         int retval = -ENOMEM;
4704
4705         pm_runtime_get_sync(&pdev->dev);
4706
4707         /*
4708          * Rx and Tx descriptors needs 256 bytes alignment.
4709          * dma_alloc_coherent provides more.
4710          */
4711         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
4712                                              &tp->TxPhyAddr, GFP_KERNEL);
4713         if (!tp->TxDescArray)
4714                 goto err_pm_runtime_put;
4715
4716         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
4717                                              &tp->RxPhyAddr, GFP_KERNEL);
4718         if (!tp->RxDescArray)
4719                 goto err_free_tx_0;
4720
4721         retval = rtl8169_init_ring(tp);
4722         if (retval < 0)
4723                 goto err_free_rx_1;
4724
4725         rtl_request_firmware(tp);
4726
4727         retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, tp,
4728                                  dev->name);
4729         if (retval < 0)
4730                 goto err_release_fw_2;
4731
4732         retval = r8169_phy_connect(tp);
4733         if (retval)
4734                 goto err_free_irq;
4735
4736         rtl8169_up(tp);
4737         rtl8169_init_counter_offsets(tp);
4738         netif_start_queue(dev);
4739
4740         pm_runtime_put_sync(&pdev->dev);
4741 out:
4742         return retval;
4743
4744 err_free_irq:
4745         pci_free_irq(pdev, 0, tp);
4746 err_release_fw_2:
4747         rtl_release_firmware(tp);
4748         rtl8169_rx_clear(tp);
4749 err_free_rx_1:
4750         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4751                           tp->RxPhyAddr);
4752         tp->RxDescArray = NULL;
4753 err_free_tx_0:
4754         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4755                           tp->TxPhyAddr);
4756         tp->TxDescArray = NULL;
4757 err_pm_runtime_put:
4758         pm_runtime_put_noidle(&pdev->dev);
4759         goto out;
4760 }
4761
4762 static void
4763 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
4764 {
4765         struct rtl8169_private *tp = netdev_priv(dev);
4766         struct pci_dev *pdev = tp->pci_dev;
4767         struct rtl8169_counters *counters = tp->counters;
4768         unsigned int start;
4769
4770         pm_runtime_get_noresume(&pdev->dev);
4771
4772         netdev_stats_to_stats64(stats, &dev->stats);
4773
4774         do {
4775                 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
4776                 stats->rx_packets = tp->rx_stats.packets;
4777                 stats->rx_bytes = tp->rx_stats.bytes;
4778         } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
4779
4780         do {
4781                 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
4782                 stats->tx_packets = tp->tx_stats.packets;
4783                 stats->tx_bytes = tp->tx_stats.bytes;
4784         } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
4785
4786         /*
4787          * Fetch additional counter values missing in stats collected by driver
4788          * from tally counters.
4789          */
4790         if (pm_runtime_active(&pdev->dev))
4791                 rtl8169_update_counters(tp);
4792
4793         /*
4794          * Subtract values fetched during initalization.
4795          * See rtl8169_init_counter_offsets for a description why we do that.
4796          */
4797         stats->tx_errors = le64_to_cpu(counters->tx_errors) -
4798                 le64_to_cpu(tp->tc_offset.tx_errors);
4799         stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
4800                 le32_to_cpu(tp->tc_offset.tx_multi_collision);
4801         stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
4802                 le16_to_cpu(tp->tc_offset.tx_aborted);
4803         stats->rx_missed_errors = le16_to_cpu(counters->rx_missed) -
4804                 le16_to_cpu(tp->tc_offset.rx_missed);
4805
4806         pm_runtime_put_noidle(&pdev->dev);
4807 }
4808
4809 static void rtl8169_net_suspend(struct rtl8169_private *tp)
4810 {
4811         netif_device_detach(tp->dev);
4812
4813         if (netif_running(tp->dev))
4814                 rtl8169_down(tp);
4815 }
4816
4817 #ifdef CONFIG_PM
4818
4819 static int rtl8169_net_resume(struct rtl8169_private *tp)
4820 {
4821         rtl_rar_set(tp, tp->dev->dev_addr);
4822
4823         if (tp->TxDescArray)
4824                 rtl8169_up(tp);
4825
4826         netif_device_attach(tp->dev);
4827
4828         return 0;
4829 }
4830
4831 static int __maybe_unused rtl8169_suspend(struct device *device)
4832 {
4833         struct rtl8169_private *tp = dev_get_drvdata(device);
4834
4835         rtnl_lock();
4836         rtl8169_net_suspend(tp);
4837         if (!device_may_wakeup(tp_to_dev(tp)))
4838                 clk_disable_unprepare(tp->clk);
4839         rtnl_unlock();
4840
4841         return 0;
4842 }
4843
4844 static int __maybe_unused rtl8169_resume(struct device *device)
4845 {
4846         struct rtl8169_private *tp = dev_get_drvdata(device);
4847
4848         if (!device_may_wakeup(tp_to_dev(tp)))
4849                 clk_prepare_enable(tp->clk);
4850
4851         /* Reportedly at least Asus X453MA truncates packets otherwise */
4852         if (tp->mac_version == RTL_GIGA_MAC_VER_37)
4853                 rtl_init_rxcfg(tp);
4854
4855         return rtl8169_net_resume(tp);
4856 }
4857
4858 static int rtl8169_runtime_suspend(struct device *device)
4859 {
4860         struct rtl8169_private *tp = dev_get_drvdata(device);
4861
4862         if (!tp->TxDescArray) {
4863                 netif_device_detach(tp->dev);
4864                 return 0;
4865         }
4866
4867         rtnl_lock();
4868         __rtl8169_set_wol(tp, WAKE_PHY);
4869         rtl8169_net_suspend(tp);
4870         rtnl_unlock();
4871
4872         return 0;
4873 }
4874
4875 static int rtl8169_runtime_resume(struct device *device)
4876 {
4877         struct rtl8169_private *tp = dev_get_drvdata(device);
4878
4879         __rtl8169_set_wol(tp, tp->saved_wolopts);
4880
4881         return rtl8169_net_resume(tp);
4882 }
4883
4884 static int rtl8169_runtime_idle(struct device *device)
4885 {
4886         struct rtl8169_private *tp = dev_get_drvdata(device);
4887
4888         if (!netif_running(tp->dev) || !netif_carrier_ok(tp->dev))
4889                 pm_schedule_suspend(device, 10000);
4890
4891         return -EBUSY;
4892 }
4893
4894 static const struct dev_pm_ops rtl8169_pm_ops = {
4895         SET_SYSTEM_SLEEP_PM_OPS(rtl8169_suspend, rtl8169_resume)
4896         SET_RUNTIME_PM_OPS(rtl8169_runtime_suspend, rtl8169_runtime_resume,
4897                            rtl8169_runtime_idle)
4898 };
4899
4900 #endif /* CONFIG_PM */
4901
4902 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
4903 {
4904         /* WoL fails with 8168b when the receiver is disabled. */
4905         switch (tp->mac_version) {
4906         case RTL_GIGA_MAC_VER_11:
4907         case RTL_GIGA_MAC_VER_12:
4908         case RTL_GIGA_MAC_VER_17:
4909                 pci_clear_master(tp->pci_dev);
4910
4911                 RTL_W8(tp, ChipCmd, CmdRxEnb);
4912                 rtl_pci_commit(tp);
4913                 break;
4914         default:
4915                 break;
4916         }
4917 }
4918
4919 static void rtl_shutdown(struct pci_dev *pdev)
4920 {
4921         struct rtl8169_private *tp = pci_get_drvdata(pdev);
4922
4923         rtnl_lock();
4924         rtl8169_net_suspend(tp);
4925         rtnl_unlock();
4926
4927         /* Restore original MAC address */
4928         rtl_rar_set(tp, tp->dev->perm_addr);
4929
4930         if (system_state == SYSTEM_POWER_OFF) {
4931                 if (tp->saved_wolopts) {
4932                         rtl_wol_suspend_quirk(tp);
4933                         rtl_wol_shutdown_quirk(tp);
4934                 }
4935
4936                 pci_wake_from_d3(pdev, true);
4937                 pci_set_power_state(pdev, PCI_D3hot);
4938         }
4939 }
4940
4941 static void rtl_remove_one(struct pci_dev *pdev)
4942 {
4943         struct rtl8169_private *tp = pci_get_drvdata(pdev);
4944
4945         if (pci_dev_run_wake(pdev))
4946                 pm_runtime_get_noresume(&pdev->dev);
4947
4948         unregister_netdev(tp->dev);
4949
4950         if (r8168_check_dash(tp))
4951                 rtl8168_driver_stop(tp);
4952
4953         rtl_release_firmware(tp);
4954
4955         /* restore original MAC address */
4956         rtl_rar_set(tp, tp->dev->perm_addr);
4957 }
4958
4959 static const struct net_device_ops rtl_netdev_ops = {
4960         .ndo_open               = rtl_open,
4961         .ndo_stop               = rtl8169_close,
4962         .ndo_get_stats64        = rtl8169_get_stats64,
4963         .ndo_start_xmit         = rtl8169_start_xmit,
4964         .ndo_features_check     = rtl8169_features_check,
4965         .ndo_tx_timeout         = rtl8169_tx_timeout,
4966         .ndo_validate_addr      = eth_validate_addr,
4967         .ndo_change_mtu         = rtl8169_change_mtu,
4968         .ndo_fix_features       = rtl8169_fix_features,
4969         .ndo_set_features       = rtl8169_set_features,
4970         .ndo_set_mac_address    = rtl_set_mac_address,
4971         .ndo_do_ioctl           = phy_do_ioctl_running,
4972         .ndo_set_rx_mode        = rtl_set_rx_mode,
4973 #ifdef CONFIG_NET_POLL_CONTROLLER
4974         .ndo_poll_controller    = rtl8169_netpoll,
4975 #endif
4976
4977 };
4978
4979 static void rtl_set_irq_mask(struct rtl8169_private *tp)
4980 {
4981         tp->irq_mask = RxOK | RxErr | TxOK | TxErr | LinkChg;
4982
4983         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
4984                 tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver;
4985         else if (tp->mac_version == RTL_GIGA_MAC_VER_11)
4986                 /* special workaround needed */
4987                 tp->irq_mask |= RxFIFOOver;
4988         else
4989                 tp->irq_mask |= RxOverflow;
4990 }
4991
4992 static int rtl_alloc_irq(struct rtl8169_private *tp)
4993 {
4994         unsigned int flags;
4995
4996         switch (tp->mac_version) {
4997         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
4998                 rtl_unlock_config_regs(tp);
4999                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
5000                 rtl_lock_config_regs(tp);
5001                 fallthrough;
5002         case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_17:
5003                 flags = PCI_IRQ_LEGACY;
5004                 break;
5005         default:
5006                 flags = PCI_IRQ_ALL_TYPES;
5007                 break;
5008         }
5009
5010         return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
5011 }
5012
5013 static void rtl_read_mac_address(struct rtl8169_private *tp,
5014                                  u8 mac_addr[ETH_ALEN])
5015 {
5016         /* Get MAC address */
5017         if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) {
5018                 u32 value = rtl_eri_read(tp, 0xe0);
5019
5020                 mac_addr[0] = (value >>  0) & 0xff;
5021                 mac_addr[1] = (value >>  8) & 0xff;
5022                 mac_addr[2] = (value >> 16) & 0xff;
5023                 mac_addr[3] = (value >> 24) & 0xff;
5024
5025                 value = rtl_eri_read(tp, 0xe4);
5026                 mac_addr[4] = (value >>  0) & 0xff;
5027                 mac_addr[5] = (value >>  8) & 0xff;
5028         } else if (rtl_is_8125(tp)) {
5029                 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP);
5030         }
5031 }
5032
5033 DECLARE_RTL_COND(rtl_link_list_ready_cond)
5034 {
5035         return RTL_R8(tp, MCU) & LINK_LIST_RDY;
5036 }
5037
5038 static void r8168g_wait_ll_share_fifo_ready(struct rtl8169_private *tp)
5039 {
5040         rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42);
5041 }
5042
5043 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
5044 {
5045         struct rtl8169_private *tp = mii_bus->priv;
5046
5047         if (phyaddr > 0)
5048                 return -ENODEV;
5049
5050         return rtl_readphy(tp, phyreg);
5051 }
5052
5053 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
5054                                 int phyreg, u16 val)
5055 {
5056         struct rtl8169_private *tp = mii_bus->priv;
5057
5058         if (phyaddr > 0)
5059                 return -ENODEV;
5060
5061         rtl_writephy(tp, phyreg, val);
5062
5063         return 0;
5064 }
5065
5066 static int r8169_mdio_register(struct rtl8169_private *tp)
5067 {
5068         struct pci_dev *pdev = tp->pci_dev;
5069         struct mii_bus *new_bus;
5070         int ret;
5071
5072         new_bus = devm_mdiobus_alloc(&pdev->dev);
5073         if (!new_bus)
5074                 return -ENOMEM;
5075
5076         new_bus->name = "r8169";
5077         new_bus->priv = tp;
5078         new_bus->parent = &pdev->dev;
5079         new_bus->irq[0] = PHY_IGNORE_INTERRUPT;
5080         snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x", pci_dev_id(pdev));
5081
5082         new_bus->read = r8169_mdio_read_reg;
5083         new_bus->write = r8169_mdio_write_reg;
5084
5085         ret = devm_mdiobus_register(&pdev->dev, new_bus);
5086         if (ret)
5087                 return ret;
5088
5089         tp->phydev = mdiobus_get_phy(new_bus, 0);
5090         if (!tp->phydev) {
5091                 return -ENODEV;
5092         } else if (!tp->phydev->drv) {
5093                 /* Most chip versions fail with the genphy driver.
5094                  * Therefore ensure that the dedicated PHY driver is loaded.
5095                  */
5096                 dev_err(&pdev->dev, "no dedicated PHY driver found for PHY ID 0x%08x, maybe realtek.ko needs to be added to initramfs?\n",
5097                         tp->phydev->phy_id);
5098                 return -EUNATCH;
5099         }
5100
5101         /* PHY will be woken up in rtl_open() */
5102         phy_suspend(tp->phydev);
5103
5104         return 0;
5105 }
5106
5107 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
5108 {
5109         rtl_enable_rxdvgate(tp);
5110
5111         RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
5112         msleep(1);
5113         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5114
5115         r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
5116         r8168g_wait_ll_share_fifo_ready(tp);
5117
5118         r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15));
5119         r8168g_wait_ll_share_fifo_ready(tp);
5120 }
5121
5122 static void rtl_hw_init_8125(struct rtl8169_private *tp)
5123 {
5124         rtl_enable_rxdvgate(tp);
5125
5126         RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
5127         msleep(1);
5128         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5129
5130         r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
5131         r8168g_wait_ll_share_fifo_ready(tp);
5132
5133         r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0);
5134         r8168_mac_ocp_write(tp, 0xc0a6, 0x0150);
5135         r8168_mac_ocp_write(tp, 0xc01e, 0x5555);
5136         r8168g_wait_ll_share_fifo_ready(tp);
5137 }
5138
5139 static void rtl_hw_initialize(struct rtl8169_private *tp)
5140 {
5141         switch (tp->mac_version) {
5142         case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52:
5143                 rtl8168ep_stop_cmac(tp);
5144                 fallthrough;
5145         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
5146                 rtl_hw_init_8168g(tp);
5147                 break;
5148         case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_63:
5149                 rtl_hw_init_8125(tp);
5150                 break;
5151         default:
5152                 break;
5153         }
5154 }
5155
5156 static int rtl_jumbo_max(struct rtl8169_private *tp)
5157 {
5158         /* Non-GBit versions don't support jumbo frames */
5159         if (!tp->supports_gmii)
5160                 return 0;
5161
5162         switch (tp->mac_version) {
5163         /* RTL8169 */
5164         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
5165                 return JUMBO_7K;
5166         /* RTL8168b */
5167         case RTL_GIGA_MAC_VER_11:
5168         case RTL_GIGA_MAC_VER_12:
5169         case RTL_GIGA_MAC_VER_17:
5170                 return JUMBO_4K;
5171         /* RTL8168c */
5172         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
5173                 return JUMBO_6K;
5174         default:
5175                 return JUMBO_9K;
5176         }
5177 }
5178
5179 static void rtl_disable_clk(void *data)
5180 {
5181         clk_disable_unprepare(data);
5182 }
5183
5184 static int rtl_get_ether_clk(struct rtl8169_private *tp)
5185 {
5186         struct device *d = tp_to_dev(tp);
5187         struct clk *clk;
5188         int rc;
5189
5190         clk = devm_clk_get(d, "ether_clk");
5191         if (IS_ERR(clk)) {
5192                 rc = PTR_ERR(clk);
5193                 if (rc == -ENOENT)
5194                         /* clk-core allows NULL (for suspend / resume) */
5195                         rc = 0;
5196                 else if (rc != -EPROBE_DEFER)
5197                         dev_err(d, "failed to get clk: %d\n", rc);
5198         } else {
5199                 tp->clk = clk;
5200                 rc = clk_prepare_enable(clk);
5201                 if (rc)
5202                         dev_err(d, "failed to enable clk: %d\n", rc);
5203                 else
5204                         rc = devm_add_action_or_reset(d, rtl_disable_clk, clk);
5205         }
5206
5207         return rc;
5208 }
5209
5210 static void rtl_init_mac_address(struct rtl8169_private *tp)
5211 {
5212         struct net_device *dev = tp->dev;
5213         u8 *mac_addr = dev->dev_addr;
5214         int rc;
5215
5216         rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr);
5217         if (!rc)
5218                 goto done;
5219
5220         rtl_read_mac_address(tp, mac_addr);
5221         if (is_valid_ether_addr(mac_addr))
5222                 goto done;
5223
5224         rtl_read_mac_from_reg(tp, mac_addr, MAC0);
5225         if (is_valid_ether_addr(mac_addr))
5226                 goto done;
5227
5228         eth_hw_addr_random(dev);
5229         dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n");
5230 done:
5231         rtl_rar_set(tp, mac_addr);
5232 }
5233
5234 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
5235 {
5236         struct rtl8169_private *tp;
5237         int jumbo_max, region, rc;
5238         enum mac_version chipset;
5239         struct net_device *dev;
5240         u16 xid;
5241
5242         dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
5243         if (!dev)
5244                 return -ENOMEM;
5245
5246         SET_NETDEV_DEV(dev, &pdev->dev);
5247         dev->netdev_ops = &rtl_netdev_ops;
5248         tp = netdev_priv(dev);
5249         tp->dev = dev;
5250         tp->pci_dev = pdev;
5251         tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1;
5252         tp->eee_adv = -1;
5253         tp->ocp_base = OCP_STD_PHY_BASE;
5254
5255         /* Get the *optional* external "ether_clk" used on some boards */
5256         rc = rtl_get_ether_clk(tp);
5257         if (rc)
5258                 return rc;
5259
5260         /* Disable ASPM completely as that cause random device stop working
5261          * problems as well as full system hangs for some PCIe devices users.
5262          */
5263         rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
5264                                           PCIE_LINK_STATE_L1);
5265         tp->aspm_manageable = !rc;
5266
5267         /* enable device (incl. PCI PM wakeup and hotplug setup) */
5268         rc = pcim_enable_device(pdev);
5269         if (rc < 0) {
5270                 dev_err(&pdev->dev, "enable failure\n");
5271                 return rc;
5272         }
5273
5274         if (pcim_set_mwi(pdev) < 0)
5275                 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
5276
5277         /* use first MMIO region */
5278         region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
5279         if (region < 0) {
5280                 dev_err(&pdev->dev, "no MMIO resource found\n");
5281                 return -ENODEV;
5282         }
5283
5284         /* check for weird/broken PCI region reporting */
5285         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
5286                 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
5287                 return -ENODEV;
5288         }
5289
5290         rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME);
5291         if (rc < 0) {
5292                 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
5293                 return rc;
5294         }
5295
5296         tp->mmio_addr = pcim_iomap_table(pdev)[region];
5297
5298         xid = (RTL_R32(tp, TxConfig) >> 20) & 0xfcf;
5299
5300         /* Identify chip attached to board */
5301         chipset = rtl8169_get_mac_version(xid, tp->supports_gmii);
5302         if (chipset == RTL_GIGA_MAC_NONE) {
5303                 dev_err(&pdev->dev, "unknown chip XID %03x\n", xid);
5304                 return -ENODEV;
5305         }
5306
5307         tp->mac_version = chipset;
5308
5309         tp->cp_cmd = RTL_R16(tp, CPlusCmd) & CPCMD_MASK;
5310
5311         if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 &&
5312             !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)))
5313                 dev->features |= NETIF_F_HIGHDMA;
5314
5315         rtl_init_rxcfg(tp);
5316
5317         rtl8169_irq_mask_and_ack(tp);
5318
5319         rtl_hw_initialize(tp);
5320
5321         rtl_hw_reset(tp);
5322
5323         pci_set_master(pdev);
5324
5325         rc = rtl_alloc_irq(tp);
5326         if (rc < 0) {
5327                 dev_err(&pdev->dev, "Can't allocate interrupt\n");
5328                 return rc;
5329         }
5330
5331         INIT_WORK(&tp->wk.work, rtl_task);
5332         u64_stats_init(&tp->rx_stats.syncp);
5333         u64_stats_init(&tp->tx_stats.syncp);
5334
5335         rtl_init_mac_address(tp);
5336
5337         dev->ethtool_ops = &rtl8169_ethtool_ops;
5338
5339         netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT);
5340
5341         dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
5342                            NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
5343         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO;
5344         dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
5345
5346         /*
5347          * Pretend we are using VLANs; This bypasses a nasty bug where
5348          * Interrupts stop flowing on high load on 8110SCd controllers.
5349          */
5350         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
5351                 /* Disallow toggling */
5352                 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
5353
5354         if (rtl_chip_supports_csum_v2(tp))
5355                 dev->hw_features |= NETIF_F_IPV6_CSUM;
5356
5357         dev->features |= dev->hw_features;
5358
5359         /* There has been a number of reports that using SG/TSO results in
5360          * tx timeouts. However for a lot of people SG/TSO works fine.
5361          * Therefore disable both features by default, but allow users to
5362          * enable them. Use at own risk!
5363          */
5364         if (rtl_chip_supports_csum_v2(tp)) {
5365                 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6;
5366                 dev->gso_max_size = RTL_GSO_MAX_SIZE_V2;
5367                 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V2;
5368         } else {
5369                 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO;
5370                 dev->gso_max_size = RTL_GSO_MAX_SIZE_V1;
5371                 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V1;
5372         }
5373
5374         dev->hw_features |= NETIF_F_RXALL;
5375         dev->hw_features |= NETIF_F_RXFCS;
5376
5377         /* configure chip for default features */
5378         rtl8169_set_features(dev, dev->features);
5379
5380         jumbo_max = rtl_jumbo_max(tp);
5381         if (jumbo_max)
5382                 dev->max_mtu = jumbo_max;
5383
5384         rtl_set_irq_mask(tp);
5385
5386         tp->fw_name = rtl_chip_infos[chipset].fw_name;
5387
5388         tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
5389                                             &tp->counters_phys_addr,
5390                                             GFP_KERNEL);
5391         if (!tp->counters)
5392                 return -ENOMEM;
5393
5394         pci_set_drvdata(pdev, tp);
5395
5396         rc = r8169_mdio_register(tp);
5397         if (rc)
5398                 return rc;
5399
5400         /* chip gets powered up in rtl_open() */
5401         rtl_pll_power_down(tp);
5402
5403         rc = register_netdev(dev);
5404         if (rc)
5405                 return rc;
5406
5407         netdev_info(dev, "%s, %pM, XID %03x, IRQ %d\n",
5408                     rtl_chip_infos[chipset].name, dev->dev_addr, xid,
5409                     pci_irq_vector(pdev, 0));
5410
5411         if (jumbo_max)
5412                 netdev_info(dev, "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
5413                             jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?
5414                             "ok" : "ko");
5415
5416         if (r8168_check_dash(tp)) {
5417                 netdev_info(dev, "DASH enabled\n");
5418                 rtl8168_driver_start(tp);
5419         }
5420
5421         if (pci_dev_run_wake(pdev))
5422                 pm_runtime_put_sync(&pdev->dev);
5423
5424         return 0;
5425 }
5426
5427 static struct pci_driver rtl8169_pci_driver = {
5428         .name           = MODULENAME,
5429         .id_table       = rtl8169_pci_tbl,
5430         .probe          = rtl_init_one,
5431         .remove         = rtl_remove_one,
5432         .shutdown       = rtl_shutdown,
5433 #ifdef CONFIG_PM
5434         .driver.pm      = &rtl8169_pm_ops,
5435 #endif
5436 };
5437
5438 module_pci_driver(rtl8169_pci_driver);