1 // SPDX-License-Identifier: GPL-2.0-only
3 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
7 * Copyright (c) a lot of people too. Please respect their work.
9 * See MAINTAINERS file for support contact information.
12 #include <linux/module.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/clk.h>
17 #include <linux/delay.h>
18 #include <linux/ethtool.h>
19 #include <linux/phy.h>
20 #include <linux/if_vlan.h>
24 #include <linux/tcp.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/bitfield.h>
29 #include <linux/prefetch.h>
30 #include <linux/ipv6.h>
31 #include <asm/unaligned.h>
32 #include <net/ip6_checksum.h>
33 #include <net/netdev_queues.h>
36 #include "r8169_firmware.h"
38 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
39 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
40 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
41 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
42 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
43 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
44 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
45 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
46 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
47 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
48 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
49 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
50 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
51 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
52 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
53 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw"
54 #define FIRMWARE_8168FP_3 "rtl_nic/rtl8168fp-3.fw"
55 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw"
56 #define FIRMWARE_8125A_3 "rtl_nic/rtl8125a-3.fw"
57 #define FIRMWARE_8125B_2 "rtl_nic/rtl8125b-2.fw"
59 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
60 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
61 #define MC_FILTER_LIMIT 32
63 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
64 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
66 #define R8169_REGS_SIZE 256
67 #define R8169_RX_BUF_SIZE (SZ_16K - 1)
68 #define NUM_TX_DESC 256 /* Number of Tx descriptor registers */
69 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
70 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
71 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
72 #define R8169_TX_STOP_THRS (MAX_SKB_FRAGS + 1)
73 #define R8169_TX_START_THRS (2 * R8169_TX_STOP_THRS)
75 #define OCP_STD_PHY_BASE 0xa400
77 #define RTL_CFG_NO_GBIT 1
79 /* write/read MMIO register */
80 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg))
81 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
82 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
83 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg))
84 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg))
85 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg))
87 #define JUMBO_4K (4 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
88 #define JUMBO_6K (6 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
89 #define JUMBO_7K (7 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
90 #define JUMBO_9K (9 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
95 } rtl_chip_infos[] = {
97 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" },
98 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" },
99 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" },
100 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" },
101 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" },
103 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" },
104 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" },
105 [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e" },
106 [RTL_GIGA_MAC_VER_10] = {"RTL8101e/RTL8100e" },
107 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" },
108 [RTL_GIGA_MAC_VER_14] = {"RTL8401" },
109 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" },
110 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" },
111 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" },
112 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" },
113 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" },
114 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" },
115 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" },
116 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" },
117 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1},
118 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2},
119 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" },
120 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1},
121 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1},
122 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" },
123 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1},
124 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2},
125 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3},
126 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1},
127 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2},
128 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 },
129 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 },
130 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1},
131 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2},
132 [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu", FIRMWARE_8168G_3},
133 [RTL_GIGA_MAC_VER_43] = {"RTL8106eus", FIRMWARE_8106E_2},
134 [RTL_GIGA_MAC_VER_44] = {"RTL8411b", FIRMWARE_8411_2 },
135 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2},
136 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2},
137 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" },
138 [RTL_GIGA_MAC_VER_52] = {"RTL8168fp/RTL8117", FIRMWARE_8168FP_3},
139 [RTL_GIGA_MAC_VER_53] = {"RTL8168fp/RTL8117", },
140 [RTL_GIGA_MAC_VER_61] = {"RTL8125A", FIRMWARE_8125A_3},
141 /* reserve 62 for CFG_METHOD_4 in the vendor driver */
142 [RTL_GIGA_MAC_VER_63] = {"RTL8125B", FIRMWARE_8125B_2},
145 static const struct pci_device_id rtl8169_pci_tbl[] = {
146 { PCI_VDEVICE(REALTEK, 0x2502) },
147 { PCI_VDEVICE(REALTEK, 0x2600) },
148 { PCI_VDEVICE(REALTEK, 0x8129) },
149 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT },
150 { PCI_VDEVICE(REALTEK, 0x8161) },
151 { PCI_VDEVICE(REALTEK, 0x8162) },
152 { PCI_VDEVICE(REALTEK, 0x8167) },
153 { PCI_VDEVICE(REALTEK, 0x8168) },
154 { PCI_VDEVICE(NCUBE, 0x8168) },
155 { PCI_VDEVICE(REALTEK, 0x8169) },
156 { PCI_VENDOR_ID_DLINK, 0x4300,
157 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 },
158 { PCI_VDEVICE(DLINK, 0x4300) },
159 { PCI_VDEVICE(DLINK, 0x4302) },
160 { PCI_VDEVICE(AT, 0xc107) },
161 { PCI_VDEVICE(USR, 0x0116) },
162 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 },
163 { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 },
164 { PCI_VDEVICE(REALTEK, 0x8125) },
165 { PCI_VDEVICE(REALTEK, 0x3000) },
169 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
172 MAC0 = 0, /* Ethernet hardware address. */
174 MAR0 = 8, /* Multicast filter. */
175 CounterAddrLow = 0x10,
176 CounterAddrHigh = 0x14,
177 TxDescStartAddrLow = 0x20,
178 TxDescStartAddrHigh = 0x24,
179 TxHDescStartAddrLow = 0x28,
180 TxHDescStartAddrHigh = 0x2c,
189 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
190 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
193 #define RX128_INT_EN (1 << 15) /* 8111c and later */
194 #define RX_MULTI_EN (1 << 14) /* 8111c only */
195 #define RXCFG_FIFO_SHIFT 13
196 /* No threshold before first PCI xfer */
197 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
198 #define RX_EARLY_OFF (1 << 11)
199 #define RXCFG_DMA_SHIFT 8
200 /* Unlimited maximum PCI burst. */
201 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
207 #define PME_SIGNAL (1 << 5) /* 8168c and later */
218 #define RTL_COALESCE_TX_USECS GENMASK(15, 12)
219 #define RTL_COALESCE_TX_FRAMES GENMASK(11, 8)
220 #define RTL_COALESCE_RX_USECS GENMASK(7, 4)
221 #define RTL_COALESCE_RX_FRAMES GENMASK(3, 0)
223 #define RTL_COALESCE_T_MAX 0x0fU
224 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_T_MAX * 4)
226 RxDescAddrLow = 0xe4,
227 RxDescAddrHigh = 0xe8,
228 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
230 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
232 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
234 #define TxPacketMax (8064 >> 7)
235 #define EarlySize 0x27
238 FuncEventMask = 0xf4,
239 FuncPresetState = 0xf8,
244 FuncForceEvent = 0xfc,
247 enum rtl8168_8101_registers {
250 #define CSIAR_FLAG 0x80000000
251 #define CSIAR_WRITE_CMD 0x80000000
252 #define CSIAR_BYTE_ENABLE 0x0000f000
253 #define CSIAR_ADDR_MASK 0x00000fff
255 #define D3COLD_NO_PLL_DOWN BIT(7)
256 #define D3HOT_NO_PLL_DOWN BIT(6)
257 #define D3_NO_PLL_DOWN (BIT(7) | BIT(6))
259 #define EPHYAR_FLAG 0x80000000
260 #define EPHYAR_WRITE_CMD 0x80000000
261 #define EPHYAR_REG_MASK 0x1f
262 #define EPHYAR_REG_SHIFT 16
263 #define EPHYAR_DATA_MASK 0xffff
265 #define PFM_EN (1 << 6)
266 #define TX_10M_PS_EN (1 << 7)
268 #define FIX_NAK_1 (1 << 4)
269 #define FIX_NAK_2 (1 << 3)
272 #define NOW_IS_OOB (1 << 7)
273 #define TX_EMPTY (1 << 5)
274 #define RX_EMPTY (1 << 4)
275 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
276 #define EN_NDP (1 << 3)
277 #define EN_OOB_RESET (1 << 2)
278 #define LINK_LIST_RDY (1 << 1)
280 #define EFUSEAR_FLAG 0x80000000
281 #define EFUSEAR_WRITE_CMD 0x80000000
282 #define EFUSEAR_READ_CMD 0x00000000
283 #define EFUSEAR_REG_MASK 0x03ff
284 #define EFUSEAR_REG_SHIFT 8
285 #define EFUSEAR_DATA_MASK 0xff
287 #define PFM_D3COLD_EN (1 << 6)
290 enum rtl8168_registers {
295 #define ERIAR_FLAG 0x80000000
296 #define ERIAR_WRITE_CMD 0x80000000
297 #define ERIAR_READ_CMD 0x00000000
298 #define ERIAR_ADDR_BYTE_ALIGN 4
299 #define ERIAR_TYPE_SHIFT 16
300 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
301 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
302 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
303 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT)
304 #define ERIAR_MASK_SHIFT 12
305 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
306 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
307 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
308 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
309 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
310 EPHY_RXER_NUM = 0x7c,
311 OCPDR = 0xb0, /* OCP GPHY access */
312 #define OCPDR_WRITE_CMD 0x80000000
313 #define OCPDR_READ_CMD 0x00000000
314 #define OCPDR_REG_MASK 0x7f
315 #define OCPDR_GPHY_REG_SHIFT 16
316 #define OCPDR_DATA_MASK 0xffff
318 #define OCPAR_FLAG 0x80000000
319 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
320 #define OCPAR_GPHY_READ_CMD 0x0000f060
322 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
323 MISC = 0xf0, /* 8168e only. */
324 #define TXPLA_RST (1 << 29)
325 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
326 #define PWM_EN (1 << 22)
327 #define RXDV_GATED_EN (1 << 19)
328 #define EARLY_TALLY_EN (1 << 16)
331 enum rtl8125_registers {
332 IntrMask_8125 = 0x38,
333 IntrStatus_8125 = 0x3c,
336 EEE_TXIDLE_TIMER_8125 = 0x6048,
339 #define RX_VLAN_INNER_8125 BIT(22)
340 #define RX_VLAN_OUTER_8125 BIT(23)
341 #define RX_VLAN_8125 (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125)
343 #define RX_FETCH_DFLT_8125 (8 << 27)
345 enum rtl_register_content {
346 /* InterruptStatusBits */
350 TxDescUnavail = 0x0080,
372 /* TXPoll register p.5 */
373 HPQ = 0x80, /* Poll cmd on the high prio queue */
374 NPQ = 0x40, /* Poll cmd on the low prio queue */
375 FSWInt = 0x01, /* Forced software interrupt */
379 Cfg9346_Unlock = 0xc0,
384 #define RX_CONFIG_ACCEPT_ERR_MASK 0x30
385 AcceptBroadcast = 0x08,
386 AcceptMulticast = 0x04,
388 AcceptAllPhys = 0x01,
389 #define RX_CONFIG_ACCEPT_OK_MASK 0x0f
390 #define RX_CONFIG_ACCEPT_MASK 0x3f
393 TxInterFrameGapShift = 24,
394 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
396 /* Config1 register p.24 */
399 Speed_down = (1 << 4),
403 PMEnable = (1 << 0), /* Power Management Enable */
405 /* Config2 register p. 25 */
406 ClkReqEn = (1 << 7), /* Clock Request Enable */
407 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
408 PCI_Clock_66MHz = 0x01,
409 PCI_Clock_33MHz = 0x00,
411 /* Config3 register p.25 */
412 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
413 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
414 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
415 Rdy_to_L23 = (1 << 1), /* L23 Enable */
416 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
418 /* Config4 register */
419 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
421 /* Config5 register p.27 */
422 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
423 MWF = (1 << 5), /* Accept Multicast wakeup frame */
424 UWF = (1 << 4), /* Accept Unicast wakeup frame */
426 LanWake = (1 << 1), /* LanWake enable/disable */
427 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
428 ASPM_en = (1 << 0), /* ASPM enable */
431 EnableBist = (1 << 15), // 8168 8101
432 Mac_dbgo_oe = (1 << 14), // 8168 8101
433 EnAnaPLL = (1 << 14), // 8169
434 Normal_mode = (1 << 13), // unused
435 Force_half_dup = (1 << 12), // 8168 8101
436 Force_rxflow_en = (1 << 11), // 8168 8101
437 Force_txflow_en = (1 << 10), // 8168 8101
438 Cxpl_dbg_sel = (1 << 9), // 8168 8101
439 ASF = (1 << 8), // 8168 8101
440 PktCntrDisable = (1 << 7), // 8168 8101
441 Mac_dbgo_sel = 0x001c, // 8168
446 #define INTT_MASK GENMASK(1, 0)
447 #define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
449 /* rtl8169_PHYstatus */
459 /* ResetCounterCommand */
462 /* DumpCounterCommand */
465 /* magic enable v2 */
466 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */
470 /* First doubleword. */
471 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
472 RingEnd = (1 << 30), /* End of descriptor ring */
473 FirstFrag = (1 << 29), /* First segment of a packet */
474 LastFrag = (1 << 28), /* Final segment of a packet */
478 enum rtl_tx_desc_bit {
479 /* First doubleword. */
480 TD_LSO = (1 << 27), /* Large Send Offload */
481 #define TD_MSS_MAX 0x07ffu /* MSS value */
483 /* Second doubleword. */
484 TxVlanTag = (1 << 17), /* Add VLAN tag */
487 /* 8169, 8168b and 810x except 8102e. */
488 enum rtl_tx_desc_bit_0 {
489 /* First doubleword. */
490 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
491 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
492 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
493 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
496 /* 8102e, 8168c and beyond. */
497 enum rtl_tx_desc_bit_1 {
498 /* First doubleword. */
499 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */
500 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */
501 #define GTTCPHO_SHIFT 18
502 #define GTTCPHO_MAX 0x7f
504 /* Second doubleword. */
505 #define TCPHO_SHIFT 18
506 #define TCPHO_MAX 0x3ff
507 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
508 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */
509 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */
510 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
511 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
514 enum rtl_rx_desc_bit {
516 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
517 PID0 = (1 << 17), /* Protocol ID bit 0/2 */
519 #define RxProtoUDP (PID1)
520 #define RxProtoTCP (PID0)
521 #define RxProtoIP (PID1 | PID0)
522 #define RxProtoMask RxProtoIP
524 IPFail = (1 << 16), /* IP checksum failed */
525 UDPFail = (1 << 15), /* UDP/IP checksum failed */
526 TCPFail = (1 << 14), /* TCP/IP checksum failed */
528 #define RxCSFailMask (IPFail | UDPFail | TCPFail)
530 RxVlanTag = (1 << 16), /* VLAN tag available */
533 #define RTL_GSO_MAX_SIZE_V1 32000
534 #define RTL_GSO_MAX_SEGS_V1 24
535 #define RTL_GSO_MAX_SIZE_V2 64000
536 #define RTL_GSO_MAX_SEGS_V2 64
555 struct rtl8169_counters {
562 __le32 tx_one_collision;
563 __le32 tx_multi_collision;
571 struct rtl8169_tc_offsets {
574 __le32 tx_multi_collision;
580 RTL_FLAG_TASK_ENABLED = 0,
581 RTL_FLAG_TASK_RESET_PENDING,
582 RTL_FLAG_TASK_TX_TIMEOUT,
592 struct rtl8169_private {
593 void __iomem *mmio_addr; /* memory map physical address */
594 struct pci_dev *pci_dev;
595 struct net_device *dev;
596 struct phy_device *phydev;
597 struct napi_struct napi;
598 enum mac_version mac_version;
599 enum rtl_dash_type dash_type;
600 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
601 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
603 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
604 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
605 dma_addr_t TxPhyAddr;
606 dma_addr_t RxPhyAddr;
607 struct page *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
608 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
615 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
616 struct work_struct work;
619 raw_spinlock_t config25_lock;
620 raw_spinlock_t mac_ocp_lock;
622 raw_spinlock_t cfg9346_usage_lock;
623 int cfg9346_usage_count;
625 unsigned supports_gmii:1;
626 unsigned aspm_manageable:1;
627 dma_addr_t counters_phys_addr;
628 struct rtl8169_counters *counters;
629 struct rtl8169_tc_offsets tc_offset;
634 struct rtl_fw *rtl_fw;
639 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp);
641 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
642 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
643 MODULE_SOFTDEP("pre: realtek");
644 MODULE_LICENSE("GPL");
645 MODULE_FIRMWARE(FIRMWARE_8168D_1);
646 MODULE_FIRMWARE(FIRMWARE_8168D_2);
647 MODULE_FIRMWARE(FIRMWARE_8168E_1);
648 MODULE_FIRMWARE(FIRMWARE_8168E_2);
649 MODULE_FIRMWARE(FIRMWARE_8168E_3);
650 MODULE_FIRMWARE(FIRMWARE_8105E_1);
651 MODULE_FIRMWARE(FIRMWARE_8168F_1);
652 MODULE_FIRMWARE(FIRMWARE_8168F_2);
653 MODULE_FIRMWARE(FIRMWARE_8402_1);
654 MODULE_FIRMWARE(FIRMWARE_8411_1);
655 MODULE_FIRMWARE(FIRMWARE_8411_2);
656 MODULE_FIRMWARE(FIRMWARE_8106E_1);
657 MODULE_FIRMWARE(FIRMWARE_8106E_2);
658 MODULE_FIRMWARE(FIRMWARE_8168G_2);
659 MODULE_FIRMWARE(FIRMWARE_8168G_3);
660 MODULE_FIRMWARE(FIRMWARE_8168H_2);
661 MODULE_FIRMWARE(FIRMWARE_8168FP_3);
662 MODULE_FIRMWARE(FIRMWARE_8107E_2);
663 MODULE_FIRMWARE(FIRMWARE_8125A_3);
664 MODULE_FIRMWARE(FIRMWARE_8125B_2);
666 static inline struct device *tp_to_dev(struct rtl8169_private *tp)
668 return &tp->pci_dev->dev;
671 static void rtl_lock_config_regs(struct rtl8169_private *tp)
675 raw_spin_lock_irqsave(&tp->cfg9346_usage_lock, flags);
676 if (!--tp->cfg9346_usage_count)
677 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
678 raw_spin_unlock_irqrestore(&tp->cfg9346_usage_lock, flags);
681 static void rtl_unlock_config_regs(struct rtl8169_private *tp)
685 raw_spin_lock_irqsave(&tp->cfg9346_usage_lock, flags);
686 if (!tp->cfg9346_usage_count++)
687 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
688 raw_spin_unlock_irqrestore(&tp->cfg9346_usage_lock, flags);
691 static void rtl_pci_commit(struct rtl8169_private *tp)
693 /* Read an arbitrary register to commit a preceding PCI write */
697 static void rtl_mod_config2(struct rtl8169_private *tp, u8 clear, u8 set)
702 raw_spin_lock_irqsave(&tp->config25_lock, flags);
703 val = RTL_R8(tp, Config2);
704 RTL_W8(tp, Config2, (val & ~clear) | set);
705 raw_spin_unlock_irqrestore(&tp->config25_lock, flags);
708 static void rtl_mod_config5(struct rtl8169_private *tp, u8 clear, u8 set)
713 raw_spin_lock_irqsave(&tp->config25_lock, flags);
714 val = RTL_R8(tp, Config5);
715 RTL_W8(tp, Config5, (val & ~clear) | set);
716 raw_spin_unlock_irqrestore(&tp->config25_lock, flags);
719 static bool rtl_is_8125(struct rtl8169_private *tp)
721 return tp->mac_version >= RTL_GIGA_MAC_VER_61;
724 static bool rtl_is_8168evl_up(struct rtl8169_private *tp)
726 return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
727 tp->mac_version != RTL_GIGA_MAC_VER_39 &&
728 tp->mac_version <= RTL_GIGA_MAC_VER_53;
731 static bool rtl_supports_eee(struct rtl8169_private *tp)
733 return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
734 tp->mac_version != RTL_GIGA_MAC_VER_37 &&
735 tp->mac_version != RTL_GIGA_MAC_VER_39;
738 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg)
742 for (i = 0; i < ETH_ALEN; i++)
743 mac[i] = RTL_R8(tp, reg + i);
747 bool (*check)(struct rtl8169_private *);
751 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
752 unsigned long usecs, int n, bool high)
756 for (i = 0; i < n; i++) {
757 if (c->check(tp) == high)
763 netdev_err(tp->dev, "%s == %d (loop: %d, delay: %lu).\n",
764 c->msg, !high, n, usecs);
768 static bool rtl_loop_wait_high(struct rtl8169_private *tp,
769 const struct rtl_cond *c,
770 unsigned long d, int n)
772 return rtl_loop_wait(tp, c, d, n, true);
775 static bool rtl_loop_wait_low(struct rtl8169_private *tp,
776 const struct rtl_cond *c,
777 unsigned long d, int n)
779 return rtl_loop_wait(tp, c, d, n, false);
782 #define DECLARE_RTL_COND(name) \
783 static bool name ## _check(struct rtl8169_private *); \
785 static const struct rtl_cond name = { \
786 .check = name ## _check, \
790 static bool name ## _check(struct rtl8169_private *tp)
792 static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type)
794 /* based on RTL8168FP_OOBMAC_BASE in vendor driver */
795 if (type == ERIAR_OOB &&
796 (tp->mac_version == RTL_GIGA_MAC_VER_52 ||
797 tp->mac_version == RTL_GIGA_MAC_VER_53))
801 DECLARE_RTL_COND(rtl_eriar_cond)
803 return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
806 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
809 u32 cmd = ERIAR_WRITE_CMD | type | mask | addr;
811 if (WARN(addr & 3 || !mask, "addr: 0x%x, mask: 0x%08x\n", addr, mask))
814 RTL_W32(tp, ERIDR, val);
815 r8168fp_adjust_ocp_cmd(tp, &cmd, type);
816 RTL_W32(tp, ERIAR, cmd);
818 rtl_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
821 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
824 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC);
827 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
829 u32 cmd = ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr;
831 r8168fp_adjust_ocp_cmd(tp, &cmd, type);
832 RTL_W32(tp, ERIAR, cmd);
834 return rtl_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
835 RTL_R32(tp, ERIDR) : ~0;
838 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr)
840 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC);
843 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 p, u32 m)
845 u32 val = rtl_eri_read(tp, addr);
847 rtl_eri_write(tp, addr, ERIAR_MASK_1111, (val & ~m) | p);
850 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 p)
852 rtl_w0w1_eri(tp, addr, p, 0);
855 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 m)
857 rtl_w0w1_eri(tp, addr, 0, m);
860 static bool rtl_ocp_reg_failure(u32 reg)
862 return WARN_ONCE(reg & 0xffff0001, "Invalid ocp reg %x!\n", reg);
865 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
867 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
870 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
872 if (rtl_ocp_reg_failure(reg))
875 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
877 rtl_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
880 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
882 if (rtl_ocp_reg_failure(reg))
885 RTL_W32(tp, GPHY_OCP, reg << 15);
887 return rtl_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
888 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT;
891 static void __r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
893 if (rtl_ocp_reg_failure(reg))
896 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
899 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
903 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags);
904 __r8168_mac_ocp_write(tp, reg, data);
905 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags);
908 static u16 __r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
910 if (rtl_ocp_reg_failure(reg))
913 RTL_W32(tp, OCPDR, reg << 15);
915 return RTL_R32(tp, OCPDR);
918 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
923 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags);
924 val = __r8168_mac_ocp_read(tp, reg);
925 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags);
930 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask,
936 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags);
937 data = __r8168_mac_ocp_read(tp, reg);
938 __r8168_mac_ocp_write(tp, reg, (data & ~mask) | set);
939 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags);
942 /* Work around a hw issue with RTL8168g PHY, the quirk disables
943 * PHY MCU interrupts before PHY power-down.
945 static void rtl8168g_phy_suspend_quirk(struct rtl8169_private *tp, int value)
947 switch (tp->mac_version) {
948 case RTL_GIGA_MAC_VER_40:
949 if (value & BMCR_RESET || !(value & BMCR_PDOWN))
950 rtl_eri_set_bits(tp, 0x1a8, 0xfc000000);
952 rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000);
959 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
962 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
966 if (tp->ocp_base != OCP_STD_PHY_BASE)
969 if (tp->ocp_base == OCP_STD_PHY_BASE && reg == MII_BMCR)
970 rtl8168g_phy_suspend_quirk(tp, value);
972 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
975 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
978 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4;
980 if (tp->ocp_base != OCP_STD_PHY_BASE)
983 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
986 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
989 tp->ocp_base = value << 4;
993 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
996 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
998 return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
1001 DECLARE_RTL_COND(rtl_phyar_cond)
1003 return RTL_R32(tp, PHYAR) & 0x80000000;
1006 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1008 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1010 rtl_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
1012 * According to hardware specs a 20us delay is required after write
1013 * complete indication, but before sending next command.
1018 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1022 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
1024 value = rtl_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1025 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT;
1028 * According to hardware specs a 20us delay is required after read
1029 * complete indication, but before sending next command.
1036 DECLARE_RTL_COND(rtl_ocpar_cond)
1038 return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
1041 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
1043 static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
1045 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1048 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
1050 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1053 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
1055 r8168dp_2_mdio_start(tp);
1057 r8169_mdio_write(tp, reg, value);
1059 r8168dp_2_mdio_stop(tp);
1062 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1066 /* Work around issue with chip reporting wrong PHY ID */
1067 if (reg == MII_PHYSID2)
1070 r8168dp_2_mdio_start(tp);
1072 value = r8169_mdio_read(tp, reg);
1074 r8168dp_2_mdio_stop(tp);
1079 static void rtl_writephy(struct rtl8169_private *tp, int location, int val)
1081 switch (tp->mac_version) {
1082 case RTL_GIGA_MAC_VER_28:
1083 case RTL_GIGA_MAC_VER_31:
1084 r8168dp_2_mdio_write(tp, location, val);
1086 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
1087 r8168g_mdio_write(tp, location, val);
1090 r8169_mdio_write(tp, location, val);
1095 static int rtl_readphy(struct rtl8169_private *tp, int location)
1097 switch (tp->mac_version) {
1098 case RTL_GIGA_MAC_VER_28:
1099 case RTL_GIGA_MAC_VER_31:
1100 return r8168dp_2_mdio_read(tp, location);
1101 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
1102 return r8168g_mdio_read(tp, location);
1104 return r8169_mdio_read(tp, location);
1108 DECLARE_RTL_COND(rtl_ephyar_cond)
1110 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1113 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1115 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1116 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1118 rtl_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1123 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1125 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1127 return rtl_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1128 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1131 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u16 reg)
1133 RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff));
1134 return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1135 RTL_R32(tp, OCPDR) : ~0;
1138 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u16 reg)
1140 return _rtl_eri_read(tp, reg, ERIAR_OOB);
1143 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1146 RTL_W32(tp, OCPDR, data);
1147 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1148 rtl_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1151 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1154 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1158 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd)
1160 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd);
1162 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001);
1165 #define OOB_CMD_RESET 0x00
1166 #define OOB_CMD_DRIVER_START 0x05
1167 #define OOB_CMD_DRIVER_STOP 0x06
1169 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1171 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1174 DECLARE_RTL_COND(rtl_dp_ocp_read_cond)
1178 reg = rtl8168_get_ocp_reg(tp);
1180 return r8168dp_ocp_read(tp, reg) & 0x00000800;
1183 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1185 return r8168ep_ocp_read(tp, 0x124) & 0x00000001;
1188 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1190 return RTL_R8(tp, IBISR0) & 0x20;
1193 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1195 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1196 rtl_loop_wait_high(tp, &rtl_ocp_tx_cond, 50000, 2000);
1197 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1198 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1201 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1203 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START);
1204 rtl_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10000, 10);
1207 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1209 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1210 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01);
1211 rtl_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10000, 10);
1214 static void rtl8168_driver_start(struct rtl8169_private *tp)
1216 if (tp->dash_type == RTL_DASH_DP)
1217 rtl8168dp_driver_start(tp);
1219 rtl8168ep_driver_start(tp);
1222 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1224 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1225 rtl_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10000, 10);
1228 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1230 rtl8168ep_stop_cmac(tp);
1231 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1232 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01);
1233 rtl_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10000, 10);
1236 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1238 if (tp->dash_type == RTL_DASH_DP)
1239 rtl8168dp_driver_stop(tp);
1241 rtl8168ep_driver_stop(tp);
1244 static bool r8168dp_check_dash(struct rtl8169_private *tp)
1246 u16 reg = rtl8168_get_ocp_reg(tp);
1248 return r8168dp_ocp_read(tp, reg) & BIT(15);
1251 static bool r8168ep_check_dash(struct rtl8169_private *tp)
1253 return r8168ep_ocp_read(tp, 0x128) & BIT(0);
1256 static enum rtl_dash_type rtl_check_dash(struct rtl8169_private *tp)
1258 switch (tp->mac_version) {
1259 case RTL_GIGA_MAC_VER_28:
1260 case RTL_GIGA_MAC_VER_31:
1261 return r8168dp_check_dash(tp) ? RTL_DASH_DP : RTL_DASH_NONE;
1262 case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_53:
1263 return r8168ep_check_dash(tp) ? RTL_DASH_EP : RTL_DASH_NONE;
1265 return RTL_DASH_NONE;
1269 static void rtl_set_d3_pll_down(struct rtl8169_private *tp, bool enable)
1271 switch (tp->mac_version) {
1272 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_26:
1273 case RTL_GIGA_MAC_VER_29 ... RTL_GIGA_MAC_VER_30:
1274 case RTL_GIGA_MAC_VER_32 ... RTL_GIGA_MAC_VER_37:
1275 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63:
1277 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~D3_NO_PLL_DOWN);
1279 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | D3_NO_PLL_DOWN);
1286 static void rtl_reset_packet_filter(struct rtl8169_private *tp)
1288 rtl_eri_clear_bits(tp, 0xdc, BIT(0));
1289 rtl_eri_set_bits(tp, 0xdc, BIT(0));
1292 DECLARE_RTL_COND(rtl_efusear_cond)
1294 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1297 u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1299 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1301 return rtl_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1302 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1305 static u32 rtl_get_events(struct rtl8169_private *tp)
1307 if (rtl_is_8125(tp))
1308 return RTL_R32(tp, IntrStatus_8125);
1310 return RTL_R16(tp, IntrStatus);
1313 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits)
1315 if (rtl_is_8125(tp))
1316 RTL_W32(tp, IntrStatus_8125, bits);
1318 RTL_W16(tp, IntrStatus, bits);
1321 static void rtl_irq_disable(struct rtl8169_private *tp)
1323 if (rtl_is_8125(tp))
1324 RTL_W32(tp, IntrMask_8125, 0);
1326 RTL_W16(tp, IntrMask, 0);
1329 static void rtl_irq_enable(struct rtl8169_private *tp)
1331 if (rtl_is_8125(tp))
1332 RTL_W32(tp, IntrMask_8125, tp->irq_mask);
1334 RTL_W16(tp, IntrMask, tp->irq_mask);
1337 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1339 rtl_irq_disable(tp);
1340 rtl_ack_events(tp, 0xffffffff);
1344 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1346 struct phy_device *phydev = tp->phydev;
1348 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1349 tp->mac_version == RTL_GIGA_MAC_VER_38) {
1350 if (phydev->speed == SPEED_1000) {
1351 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1352 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1353 } else if (phydev->speed == SPEED_100) {
1354 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1355 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1357 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1358 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1360 rtl_reset_packet_filter(tp);
1361 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1362 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1363 if (phydev->speed == SPEED_1000) {
1364 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1365 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1367 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1368 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1370 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1371 if (phydev->speed == SPEED_10) {
1372 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02);
1373 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a);
1375 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
1380 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1382 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1384 struct rtl8169_private *tp = netdev_priv(dev);
1386 wol->supported = WAKE_ANY;
1387 wol->wolopts = tp->saved_wolopts;
1390 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1392 static const struct {
1397 { WAKE_PHY, Config3, LinkUp },
1398 { WAKE_UCAST, Config5, UWF },
1399 { WAKE_BCAST, Config5, BWF },
1400 { WAKE_MCAST, Config5, MWF },
1401 { WAKE_ANY, Config5, LanWake },
1402 { WAKE_MAGIC, Config3, MagicPacket }
1404 unsigned int i, tmp = ARRAY_SIZE(cfg);
1405 unsigned long flags;
1408 rtl_unlock_config_regs(tp);
1410 if (rtl_is_8168evl_up(tp)) {
1412 if (wolopts & WAKE_MAGIC)
1413 rtl_eri_set_bits(tp, 0x0dc, MagicPacket_v2);
1415 rtl_eri_clear_bits(tp, 0x0dc, MagicPacket_v2);
1416 } else if (rtl_is_8125(tp)) {
1418 if (wolopts & WAKE_MAGIC)
1419 r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0));
1421 r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0);
1424 raw_spin_lock_irqsave(&tp->config25_lock, flags);
1425 for (i = 0; i < tmp; i++) {
1426 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
1427 if (wolopts & cfg[i].opt)
1428 options |= cfg[i].mask;
1429 RTL_W8(tp, cfg[i].reg, options);
1431 raw_spin_unlock_irqrestore(&tp->config25_lock, flags);
1433 switch (tp->mac_version) {
1434 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
1435 options = RTL_R8(tp, Config1) & ~PMEnable;
1437 options |= PMEnable;
1438 RTL_W8(tp, Config1, options);
1440 case RTL_GIGA_MAC_VER_34:
1441 case RTL_GIGA_MAC_VER_37:
1442 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63:
1444 rtl_mod_config2(tp, 0, PME_SIGNAL);
1446 rtl_mod_config2(tp, PME_SIGNAL, 0);
1452 rtl_lock_config_regs(tp);
1454 device_set_wakeup_enable(tp_to_dev(tp), wolopts);
1456 if (tp->dash_type == RTL_DASH_NONE) {
1457 rtl_set_d3_pll_down(tp, !wolopts);
1458 tp->dev->wol_enabled = wolopts ? 1 : 0;
1462 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1464 struct rtl8169_private *tp = netdev_priv(dev);
1466 if (wol->wolopts & ~WAKE_ANY)
1469 tp->saved_wolopts = wol->wolopts;
1470 __rtl8169_set_wol(tp, tp->saved_wolopts);
1475 static void rtl8169_get_drvinfo(struct net_device *dev,
1476 struct ethtool_drvinfo *info)
1478 struct rtl8169_private *tp = netdev_priv(dev);
1479 struct rtl_fw *rtl_fw = tp->rtl_fw;
1481 strscpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
1482 strscpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1483 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1485 strscpy(info->fw_version, rtl_fw->version,
1486 sizeof(info->fw_version));
1489 static int rtl8169_get_regs_len(struct net_device *dev)
1491 return R8169_REGS_SIZE;
1494 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1495 netdev_features_t features)
1497 struct rtl8169_private *tp = netdev_priv(dev);
1499 if (dev->mtu > TD_MSS_MAX)
1500 features &= ~NETIF_F_ALL_TSO;
1502 if (dev->mtu > ETH_DATA_LEN &&
1503 tp->mac_version > RTL_GIGA_MAC_VER_06)
1504 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_ALL_TSO);
1509 static void rtl_set_rx_config_features(struct rtl8169_private *tp,
1510 netdev_features_t features)
1512 u32 rx_config = RTL_R32(tp, RxConfig);
1514 if (features & NETIF_F_RXALL)
1515 rx_config |= RX_CONFIG_ACCEPT_ERR_MASK;
1517 rx_config &= ~RX_CONFIG_ACCEPT_ERR_MASK;
1519 if (rtl_is_8125(tp)) {
1520 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1521 rx_config |= RX_VLAN_8125;
1523 rx_config &= ~RX_VLAN_8125;
1526 RTL_W32(tp, RxConfig, rx_config);
1529 static int rtl8169_set_features(struct net_device *dev,
1530 netdev_features_t features)
1532 struct rtl8169_private *tp = netdev_priv(dev);
1534 rtl_set_rx_config_features(tp, features);
1536 if (features & NETIF_F_RXCSUM)
1537 tp->cp_cmd |= RxChkSum;
1539 tp->cp_cmd &= ~RxChkSum;
1541 if (!rtl_is_8125(tp)) {
1542 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1543 tp->cp_cmd |= RxVlan;
1545 tp->cp_cmd &= ~RxVlan;
1548 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1554 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1556 return (skb_vlan_tag_present(skb)) ?
1557 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1560 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1562 u32 opts2 = le32_to_cpu(desc->opts2);
1564 if (opts2 & RxVlanTag)
1565 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1568 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1571 struct rtl8169_private *tp = netdev_priv(dev);
1572 u32 __iomem *data = tp->mmio_addr;
1576 for (i = 0; i < R8169_REGS_SIZE; i += 4)
1577 memcpy_fromio(dw++, data++, 4);
1580 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1587 "tx_single_collisions",
1588 "tx_multi_collisions",
1596 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1600 return ARRAY_SIZE(rtl8169_gstrings);
1606 DECLARE_RTL_COND(rtl_counters_cond)
1608 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
1611 static void rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
1613 u32 cmd = lower_32_bits(tp->counters_phys_addr);
1615 RTL_W32(tp, CounterAddrHigh, upper_32_bits(tp->counters_phys_addr));
1617 RTL_W32(tp, CounterAddrLow, cmd);
1618 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
1620 rtl_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
1623 static void rtl8169_update_counters(struct rtl8169_private *tp)
1625 u8 val = RTL_R8(tp, ChipCmd);
1628 * Some chips are unable to dump tally counters when the receiver
1629 * is disabled. If 0xff chip may be in a PCI power-save state.
1631 if (val & CmdRxEnb && val != 0xff)
1632 rtl8169_do_counters(tp, CounterDump);
1635 static void rtl8169_init_counter_offsets(struct rtl8169_private *tp)
1637 struct rtl8169_counters *counters = tp->counters;
1640 * rtl8169_init_counter_offsets is called from rtl_open. On chip
1641 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1642 * reset by a power cycle, while the counter values collected by the
1643 * driver are reset at every driver unload/load cycle.
1645 * To make sure the HW values returned by @get_stats64 match the SW
1646 * values, we collect the initial values at first open(*) and use them
1647 * as offsets to normalize the values returned by @get_stats64.
1649 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1650 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1651 * set at open time by rtl_hw_start.
1654 if (tp->tc_offset.inited)
1657 if (tp->mac_version >= RTL_GIGA_MAC_VER_19) {
1658 rtl8169_do_counters(tp, CounterReset);
1660 rtl8169_update_counters(tp);
1661 tp->tc_offset.tx_errors = counters->tx_errors;
1662 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1663 tp->tc_offset.tx_aborted = counters->tx_aborted;
1664 tp->tc_offset.rx_missed = counters->rx_missed;
1667 tp->tc_offset.inited = true;
1670 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1671 struct ethtool_stats *stats, u64 *data)
1673 struct rtl8169_private *tp = netdev_priv(dev);
1674 struct rtl8169_counters *counters;
1676 counters = tp->counters;
1677 rtl8169_update_counters(tp);
1679 data[0] = le64_to_cpu(counters->tx_packets);
1680 data[1] = le64_to_cpu(counters->rx_packets);
1681 data[2] = le64_to_cpu(counters->tx_errors);
1682 data[3] = le32_to_cpu(counters->rx_errors);
1683 data[4] = le16_to_cpu(counters->rx_missed);
1684 data[5] = le16_to_cpu(counters->align_errors);
1685 data[6] = le32_to_cpu(counters->tx_one_collision);
1686 data[7] = le32_to_cpu(counters->tx_multi_collision);
1687 data[8] = le64_to_cpu(counters->rx_unicast);
1688 data[9] = le64_to_cpu(counters->rx_broadcast);
1689 data[10] = le32_to_cpu(counters->rx_multicast);
1690 data[11] = le16_to_cpu(counters->tx_aborted);
1691 data[12] = le16_to_cpu(counters->tx_underun);
1694 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1698 memcpy(data, rtl8169_gstrings, sizeof(rtl8169_gstrings));
1704 * Interrupt coalescing
1706 * > 1 - the availability of the IntrMitigate (0xe2) register through the
1707 * > 8169, 8168 and 810x line of chipsets
1709 * 8169, 8168, and 8136(810x) serial chipsets support it.
1711 * > 2 - the Tx timer unit at gigabit speed
1713 * The unit of the timer depends on both the speed and the setting of CPlusCmd
1714 * (0xe0) bit 1 and bit 0.
1717 * bit[1:0] \ speed 1000M 100M 10M
1718 * 0 0 320ns 2.56us 40.96us
1719 * 0 1 2.56us 20.48us 327.7us
1720 * 1 0 5.12us 40.96us 655.4us
1721 * 1 1 10.24us 81.92us 1.31ms
1724 * bit[1:0] \ speed 1000M 100M 10M
1725 * 0 0 5us 2.56us 40.96us
1726 * 0 1 40us 20.48us 327.7us
1727 * 1 0 80us 40.96us 655.4us
1728 * 1 1 160us 81.92us 1.31ms
1731 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
1732 struct rtl_coalesce_info {
1737 /* produce array with base delay *1, *8, *8*2, *8*2*2 */
1738 #define COALESCE_DELAY(d) { (d), 8 * (d), 16 * (d), 32 * (d) }
1740 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1741 { SPEED_1000, COALESCE_DELAY(320) },
1742 { SPEED_100, COALESCE_DELAY(2560) },
1743 { SPEED_10, COALESCE_DELAY(40960) },
1747 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1748 { SPEED_1000, COALESCE_DELAY(5000) },
1749 { SPEED_100, COALESCE_DELAY(2560) },
1750 { SPEED_10, COALESCE_DELAY(40960) },
1753 #undef COALESCE_DELAY
1755 /* get rx/tx scale vector corresponding to current speed */
1756 static const struct rtl_coalesce_info *
1757 rtl_coalesce_info(struct rtl8169_private *tp)
1759 const struct rtl_coalesce_info *ci;
1761 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1762 ci = rtl_coalesce_info_8169;
1764 ci = rtl_coalesce_info_8168_8136;
1766 /* if speed is unknown assume highest one */
1767 if (tp->phydev->speed == SPEED_UNKNOWN)
1770 for (; ci->speed; ci++) {
1771 if (tp->phydev->speed == ci->speed)
1775 return ERR_PTR(-ELNRNG);
1778 static int rtl_get_coalesce(struct net_device *dev,
1779 struct ethtool_coalesce *ec,
1780 struct kernel_ethtool_coalesce *kernel_coal,
1781 struct netlink_ext_ack *extack)
1783 struct rtl8169_private *tp = netdev_priv(dev);
1784 const struct rtl_coalesce_info *ci;
1785 u32 scale, c_us, c_fr;
1788 if (rtl_is_8125(tp))
1791 memset(ec, 0, sizeof(*ec));
1793 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1794 ci = rtl_coalesce_info(tp);
1798 scale = ci->scale_nsecs[tp->cp_cmd & INTT_MASK];
1800 intrmit = RTL_R16(tp, IntrMitigate);
1802 c_us = FIELD_GET(RTL_COALESCE_TX_USECS, intrmit);
1803 ec->tx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000);
1805 c_fr = FIELD_GET(RTL_COALESCE_TX_FRAMES, intrmit);
1806 /* ethtool_coalesce states usecs and max_frames must not both be 0 */
1807 ec->tx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1;
1809 c_us = FIELD_GET(RTL_COALESCE_RX_USECS, intrmit);
1810 ec->rx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000);
1812 c_fr = FIELD_GET(RTL_COALESCE_RX_FRAMES, intrmit);
1813 ec->rx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1;
1818 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, usec) */
1819 static int rtl_coalesce_choose_scale(struct rtl8169_private *tp, u32 usec,
1822 const struct rtl_coalesce_info *ci;
1825 ci = rtl_coalesce_info(tp);
1829 for (i = 0; i < 4; i++) {
1830 if (usec <= ci->scale_nsecs[i] * RTL_COALESCE_T_MAX / 1000U) {
1832 return ci->scale_nsecs[i];
1839 static int rtl_set_coalesce(struct net_device *dev,
1840 struct ethtool_coalesce *ec,
1841 struct kernel_ethtool_coalesce *kernel_coal,
1842 struct netlink_ext_ack *extack)
1844 struct rtl8169_private *tp = netdev_priv(dev);
1845 u32 tx_fr = ec->tx_max_coalesced_frames;
1846 u32 rx_fr = ec->rx_max_coalesced_frames;
1847 u32 coal_usec_max, units;
1848 u16 w = 0, cp01 = 0;
1851 if (rtl_is_8125(tp))
1854 if (rx_fr > RTL_COALESCE_FRAME_MAX || tx_fr > RTL_COALESCE_FRAME_MAX)
1857 coal_usec_max = max(ec->rx_coalesce_usecs, ec->tx_coalesce_usecs);
1858 scale = rtl_coalesce_choose_scale(tp, coal_usec_max, &cp01);
1862 /* Accept max_frames=1 we returned in rtl_get_coalesce. Accept it
1863 * not only when usecs=0 because of e.g. the following scenario:
1865 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
1866 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
1867 * - then user does `ethtool -C eth0 rx-usecs 100`
1869 * Since ethtool sends to kernel whole ethtool_coalesce settings,
1870 * if we want to ignore rx_frames then it has to be set to 0.
1877 /* HW requires time limit to be set if frame limit is set */
1878 if ((tx_fr && !ec->tx_coalesce_usecs) ||
1879 (rx_fr && !ec->rx_coalesce_usecs))
1882 w |= FIELD_PREP(RTL_COALESCE_TX_FRAMES, DIV_ROUND_UP(tx_fr, 4));
1883 w |= FIELD_PREP(RTL_COALESCE_RX_FRAMES, DIV_ROUND_UP(rx_fr, 4));
1885 units = DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000U, scale);
1886 w |= FIELD_PREP(RTL_COALESCE_TX_USECS, units);
1887 units = DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000U, scale);
1888 w |= FIELD_PREP(RTL_COALESCE_RX_USECS, units);
1890 RTL_W16(tp, IntrMitigate, w);
1892 /* Meaning of PktCntrDisable bit changed from RTL8168e-vl */
1893 if (rtl_is_8168evl_up(tp)) {
1894 if (!rx_fr && !tx_fr)
1895 /* disable packet counter */
1896 tp->cp_cmd |= PktCntrDisable;
1898 tp->cp_cmd &= ~PktCntrDisable;
1901 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
1902 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1908 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data)
1910 struct rtl8169_private *tp = netdev_priv(dev);
1912 if (!rtl_supports_eee(tp))
1915 return phy_ethtool_get_eee(tp->phydev, data);
1918 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data)
1920 struct rtl8169_private *tp = netdev_priv(dev);
1923 if (!rtl_supports_eee(tp))
1926 ret = phy_ethtool_set_eee(tp->phydev, data);
1929 tp->eee_adv = phy_read_mmd(dev->phydev, MDIO_MMD_AN,
1934 static void rtl8169_get_ringparam(struct net_device *dev,
1935 struct ethtool_ringparam *data,
1936 struct kernel_ethtool_ringparam *kernel_data,
1937 struct netlink_ext_ack *extack)
1939 data->rx_max_pending = NUM_RX_DESC;
1940 data->rx_pending = NUM_RX_DESC;
1941 data->tx_max_pending = NUM_TX_DESC;
1942 data->tx_pending = NUM_TX_DESC;
1945 static void rtl8169_get_pauseparam(struct net_device *dev,
1946 struct ethtool_pauseparam *data)
1948 struct rtl8169_private *tp = netdev_priv(dev);
1949 bool tx_pause, rx_pause;
1951 phy_get_pause(tp->phydev, &tx_pause, &rx_pause);
1953 data->autoneg = tp->phydev->autoneg;
1954 data->tx_pause = tx_pause ? 1 : 0;
1955 data->rx_pause = rx_pause ? 1 : 0;
1958 static int rtl8169_set_pauseparam(struct net_device *dev,
1959 struct ethtool_pauseparam *data)
1961 struct rtl8169_private *tp = netdev_priv(dev);
1963 if (dev->mtu > ETH_DATA_LEN)
1966 phy_set_asym_pause(tp->phydev, data->rx_pause, data->tx_pause);
1971 static const struct ethtool_ops rtl8169_ethtool_ops = {
1972 .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
1973 ETHTOOL_COALESCE_MAX_FRAMES,
1974 .get_drvinfo = rtl8169_get_drvinfo,
1975 .get_regs_len = rtl8169_get_regs_len,
1976 .get_link = ethtool_op_get_link,
1977 .get_coalesce = rtl_get_coalesce,
1978 .set_coalesce = rtl_set_coalesce,
1979 .get_regs = rtl8169_get_regs,
1980 .get_wol = rtl8169_get_wol,
1981 .set_wol = rtl8169_set_wol,
1982 .get_strings = rtl8169_get_strings,
1983 .get_sset_count = rtl8169_get_sset_count,
1984 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1985 .get_ts_info = ethtool_op_get_ts_info,
1986 .nway_reset = phy_ethtool_nway_reset,
1987 .get_eee = rtl8169_get_eee,
1988 .set_eee = rtl8169_set_eee,
1989 .get_link_ksettings = phy_ethtool_get_link_ksettings,
1990 .set_link_ksettings = phy_ethtool_set_link_ksettings,
1991 .get_ringparam = rtl8169_get_ringparam,
1992 .get_pauseparam = rtl8169_get_pauseparam,
1993 .set_pauseparam = rtl8169_set_pauseparam,
1996 static void rtl_enable_eee(struct rtl8169_private *tp)
1998 struct phy_device *phydev = tp->phydev;
2001 /* respect EEE advertisement the user may have set */
2002 if (tp->eee_adv >= 0)
2005 adv = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
2008 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, adv);
2011 static enum mac_version rtl8169_get_mac_version(u16 xid, bool gmii)
2014 * The driver currently handles the 8168Bf and the 8168Be identically
2015 * but they can be identified more specifically through the test below
2018 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2020 * Same thing for the 8101Eb and the 8101Ec:
2022 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2024 static const struct rtl_mac_info {
2027 enum mac_version ver;
2030 { 0x7cf, 0x641, RTL_GIGA_MAC_VER_63 },
2033 { 0x7cf, 0x609, RTL_GIGA_MAC_VER_61 },
2034 /* It seems only XID 609 made it to the mass market.
2035 * { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 },
2036 * { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 },
2040 { 0x7cf, 0x54b, RTL_GIGA_MAC_VER_53 },
2041 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52 },
2043 /* 8168EP family. */
2044 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 },
2045 /* It seems this chip version never made it to
2046 * the wild. Let's disable detection.
2047 * { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 },
2048 * { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 },
2052 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 },
2053 /* It seems this chip version never made it to
2054 * the wild. Let's disable detection.
2055 * { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 },
2059 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 },
2060 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 },
2061 /* It seems this chip version never made it to
2062 * the wild. Let's disable detection.
2063 * { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 },
2065 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 },
2068 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 },
2069 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 },
2070 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 },
2073 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 },
2074 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 },
2075 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 },
2078 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 },
2079 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 },
2081 /* 8168DP family. */
2082 /* It seems this early RTL8168dp version never made it to
2083 * the wild. Support has been removed.
2084 * { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 },
2086 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 },
2087 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 },
2090 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 },
2091 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 },
2092 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 },
2093 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 },
2094 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 },
2095 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 },
2096 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 },
2099 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 },
2100 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 },
2103 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 },
2104 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 },
2105 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 },
2106 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 },
2107 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 },
2108 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 },
2109 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 },
2110 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 },
2111 { 0x7cf, 0x240, RTL_GIGA_MAC_VER_14 },
2112 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 },
2113 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 },
2114 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_10 },
2117 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 },
2118 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 },
2119 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 },
2120 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 },
2121 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 },
2124 { 0x000, 0x000, RTL_GIGA_MAC_NONE }
2126 const struct rtl_mac_info *p = mac_info;
2127 enum mac_version ver;
2129 while ((xid & p->mask) != p->val)
2133 if (ver != RTL_GIGA_MAC_NONE && !gmii) {
2134 if (ver == RTL_GIGA_MAC_VER_42)
2135 ver = RTL_GIGA_MAC_VER_43;
2136 else if (ver == RTL_GIGA_MAC_VER_46)
2137 ver = RTL_GIGA_MAC_VER_48;
2143 static void rtl_release_firmware(struct rtl8169_private *tp)
2146 rtl_fw_release_firmware(tp->rtl_fw);
2152 void r8169_apply_firmware(struct rtl8169_private *tp)
2156 /* TODO: release firmware if rtl_fw_write_firmware signals failure. */
2158 rtl_fw_write_firmware(tp, tp->rtl_fw);
2159 /* At least one firmware doesn't reset tp->ocp_base. */
2160 tp->ocp_base = OCP_STD_PHY_BASE;
2162 /* PHY soft reset may still be in progress */
2163 phy_read_poll_timeout(tp->phydev, MII_BMCR, val,
2164 !(val & BMCR_RESET),
2165 50000, 600000, true);
2169 static void rtl8168_config_eee_mac(struct rtl8169_private *tp)
2171 /* Adjust EEE LED frequency */
2172 if (tp->mac_version != RTL_GIGA_MAC_VER_38)
2173 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
2175 rtl_eri_set_bits(tp, 0x1b0, 0x0003);
2178 static void rtl8125a_config_eee_mac(struct rtl8169_private *tp)
2180 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0));
2181 r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1));
2184 static void rtl8125_set_eee_txidle_timer(struct rtl8169_private *tp)
2186 RTL_W16(tp, EEE_TXIDLE_TIMER_8125, tp->dev->mtu + ETH_HLEN + 0x20);
2189 static void rtl8125b_config_eee_mac(struct rtl8169_private *tp)
2191 rtl8125_set_eee_txidle_timer(tp);
2192 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0));
2195 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, const u8 *addr)
2197 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, get_unaligned_le32(addr));
2198 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, get_unaligned_le16(addr + 4));
2199 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, get_unaligned_le16(addr) << 16);
2200 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, get_unaligned_le32(addr + 2));
2203 u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp)
2205 u16 data1, data2, ioffset;
2207 r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
2208 data1 = r8168_mac_ocp_read(tp, 0xdd02);
2209 data2 = r8168_mac_ocp_read(tp, 0xdd00);
2211 ioffset = (data2 >> 1) & 0x7ff8;
2212 ioffset |= data2 & 0x0007;
2219 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
2221 set_bit(flag, tp->wk.flags);
2222 schedule_work(&tp->wk.work);
2225 static void rtl8169_init_phy(struct rtl8169_private *tp)
2227 r8169_hw_phy_config(tp, tp->phydev, tp->mac_version);
2229 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2230 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2231 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
2232 /* set undocumented MAC Reg C+CR Offset 0x82h */
2233 RTL_W8(tp, 0x82, 0x01);
2236 if (tp->mac_version == RTL_GIGA_MAC_VER_05 &&
2237 tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE &&
2238 tp->pci_dev->subsystem_device == 0xe000)
2239 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b);
2241 /* We may have called phy_speed_down before */
2242 phy_speed_up(tp->phydev);
2244 if (rtl_supports_eee(tp))
2247 genphy_soft_reset(tp->phydev);
2250 static void rtl_rar_set(struct rtl8169_private *tp, const u8 *addr)
2252 rtl_unlock_config_regs(tp);
2254 RTL_W32(tp, MAC4, get_unaligned_le16(addr + 4));
2257 RTL_W32(tp, MAC0, get_unaligned_le32(addr));
2260 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
2261 rtl_rar_exgmac_set(tp, addr);
2263 rtl_lock_config_regs(tp);
2266 static int rtl_set_mac_address(struct net_device *dev, void *p)
2268 struct rtl8169_private *tp = netdev_priv(dev);
2271 ret = eth_mac_addr(dev, p);
2275 rtl_rar_set(tp, dev->dev_addr);
2280 static void rtl_init_rxcfg(struct rtl8169_private *tp)
2282 switch (tp->mac_version) {
2283 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
2284 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
2285 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
2287 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
2288 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
2289 case RTL_GIGA_MAC_VER_38:
2290 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
2292 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53:
2293 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
2295 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63:
2296 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST);
2299 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
2304 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2306 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
2309 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
2311 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2312 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
2315 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
2317 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2318 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
2321 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
2323 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2326 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
2328 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2331 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
2333 RTL_W8(tp, MaxTxPacketSize, 0x24);
2334 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2335 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
2338 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
2340 RTL_W8(tp, MaxTxPacketSize, 0x3f);
2341 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2342 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
2345 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
2347 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
2350 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
2352 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
2355 static void rtl_jumbo_config(struct rtl8169_private *tp)
2357 bool jumbo = tp->dev->mtu > ETH_DATA_LEN;
2360 rtl_unlock_config_regs(tp);
2361 switch (tp->mac_version) {
2362 case RTL_GIGA_MAC_VER_17:
2365 r8168b_1_hw_jumbo_enable(tp);
2367 r8168b_1_hw_jumbo_disable(tp);
2370 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26:
2373 r8168c_hw_jumbo_enable(tp);
2375 r8168c_hw_jumbo_disable(tp);
2378 case RTL_GIGA_MAC_VER_28:
2380 r8168dp_hw_jumbo_enable(tp);
2382 r8168dp_hw_jumbo_disable(tp);
2384 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33:
2386 r8168e_hw_jumbo_enable(tp);
2388 r8168e_hw_jumbo_disable(tp);
2393 rtl_lock_config_regs(tp);
2395 if (pci_is_pcie(tp->pci_dev) && tp->supports_gmii)
2396 pcie_set_readrq(tp->pci_dev, readrq);
2398 /* Chip doesn't support pause in jumbo mode */
2400 linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT,
2401 tp->phydev->advertising);
2402 linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
2403 tp->phydev->advertising);
2404 phy_start_aneg(tp->phydev);
2408 DECLARE_RTL_COND(rtl_chipcmd_cond)
2410 return RTL_R8(tp, ChipCmd) & CmdReset;
2413 static void rtl_hw_reset(struct rtl8169_private *tp)
2415 RTL_W8(tp, ChipCmd, CmdReset);
2417 rtl_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
2420 static void rtl_request_firmware(struct rtl8169_private *tp)
2422 struct rtl_fw *rtl_fw;
2424 /* firmware loaded already or no firmware available */
2425 if (tp->rtl_fw || !tp->fw_name)
2428 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
2432 rtl_fw->phy_write = rtl_writephy;
2433 rtl_fw->phy_read = rtl_readphy;
2434 rtl_fw->mac_mcu_write = mac_mcu_write;
2435 rtl_fw->mac_mcu_read = mac_mcu_read;
2436 rtl_fw->fw_name = tp->fw_name;
2437 rtl_fw->dev = tp_to_dev(tp);
2439 if (rtl_fw_request_firmware(rtl_fw))
2442 tp->rtl_fw = rtl_fw;
2445 static void rtl_rx_close(struct rtl8169_private *tp)
2447 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
2450 DECLARE_RTL_COND(rtl_npq_cond)
2452 return RTL_R8(tp, TxPoll) & NPQ;
2455 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
2457 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
2460 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
2462 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
2465 DECLARE_RTL_COND(rtl_rxtx_empty_cond_2)
2467 /* IntrMitigate has new functionality on RTL8125 */
2468 return (RTL_R16(tp, IntrMitigate) & 0x0103) == 0x0103;
2471 static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp)
2473 switch (tp->mac_version) {
2474 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53:
2475 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42);
2476 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2478 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_61:
2479 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2481 case RTL_GIGA_MAC_VER_63:
2482 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
2483 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2484 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond_2, 100, 42);
2491 static void rtl_disable_rxdvgate(struct rtl8169_private *tp)
2493 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
2496 static void rtl_enable_rxdvgate(struct rtl8169_private *tp)
2498 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
2500 rtl_wait_txrx_fifo_empty(tp);
2503 static void rtl_wol_enable_rx(struct rtl8169_private *tp)
2505 if (tp->mac_version >= RTL_GIGA_MAC_VER_25)
2506 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
2507 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
2509 if (tp->mac_version >= RTL_GIGA_MAC_VER_40)
2510 rtl_disable_rxdvgate(tp);
2513 static void rtl_prepare_power_down(struct rtl8169_private *tp)
2515 if (tp->dash_type != RTL_DASH_NONE)
2518 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
2519 tp->mac_version == RTL_GIGA_MAC_VER_33)
2520 rtl_ephy_write(tp, 0x19, 0xff64);
2522 if (device_may_wakeup(tp_to_dev(tp))) {
2523 phy_speed_down(tp->phydev, false);
2524 rtl_wol_enable_rx(tp);
2528 static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
2530 u32 val = TX_DMA_BURST << TxDMAShift |
2531 InterFrameGap << TxInterFrameGapShift;
2533 if (rtl_is_8168evl_up(tp))
2534 val |= TXCFG_AUTO_FIFO;
2536 RTL_W32(tp, TxConfig, val);
2539 static void rtl_set_rx_max_size(struct rtl8169_private *tp)
2541 /* Low hurts. Let's disable the filtering. */
2542 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
2545 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
2548 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
2549 * register to be written before TxDescAddrLow to work.
2550 * Switching from MMIO to I/O access fixes the issue as well.
2552 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
2553 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
2554 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
2555 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
2558 static void rtl8169_set_magic_reg(struct rtl8169_private *tp)
2562 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
2564 else if (tp->mac_version == RTL_GIGA_MAC_VER_06)
2569 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz)
2572 RTL_W32(tp, 0x7c, val);
2575 static void rtl_set_rx_mode(struct net_device *dev)
2577 u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast;
2578 /* Multicast hash filter */
2579 u32 mc_filter[2] = { 0xffffffff, 0xffffffff };
2580 struct rtl8169_private *tp = netdev_priv(dev);
2583 if (dev->flags & IFF_PROMISC) {
2584 rx_mode |= AcceptAllPhys;
2585 } else if (!(dev->flags & IFF_MULTICAST)) {
2586 rx_mode &= ~AcceptMulticast;
2587 } else if (netdev_mc_count(dev) > MC_FILTER_LIMIT ||
2588 dev->flags & IFF_ALLMULTI ||
2589 tp->mac_version == RTL_GIGA_MAC_VER_35 ||
2590 tp->mac_version == RTL_GIGA_MAC_VER_46 ||
2591 tp->mac_version == RTL_GIGA_MAC_VER_48) {
2592 /* accept all multicasts */
2593 } else if (netdev_mc_empty(dev)) {
2594 rx_mode &= ~AcceptMulticast;
2596 struct netdev_hw_addr *ha;
2598 mc_filter[1] = mc_filter[0] = 0;
2599 netdev_for_each_mc_addr(ha, dev) {
2600 u32 bit_nr = eth_hw_addr_crc(ha) >> 26;
2601 mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31);
2604 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
2606 mc_filter[0] = swab32(mc_filter[1]);
2607 mc_filter[1] = swab32(tmp);
2611 RTL_W32(tp, MAR0 + 4, mc_filter[1]);
2612 RTL_W32(tp, MAR0 + 0, mc_filter[0]);
2614 tmp = RTL_R32(tp, RxConfig);
2615 RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode);
2618 DECLARE_RTL_COND(rtl_csiar_cond)
2620 return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
2623 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
2625 u32 func = PCI_FUNC(tp->pci_dev->devfn);
2627 RTL_W32(tp, CSIDR, value);
2628 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
2629 CSIAR_BYTE_ENABLE | func << 16);
2631 rtl_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
2634 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
2636 u32 func = PCI_FUNC(tp->pci_dev->devfn);
2638 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
2641 return rtl_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
2642 RTL_R32(tp, CSIDR) : ~0;
2645 static void rtl_set_aspm_entry_latency(struct rtl8169_private *tp, u8 val)
2647 struct pci_dev *pdev = tp->pci_dev;
2650 /* According to Realtek the value at config space address 0x070f
2651 * controls the L0s/L1 entrance latency. We try standard ECAM access
2652 * first and if it fails fall back to CSI.
2653 * bit 0..2: L0: 0 = 1us, 1 = 2us .. 6 = 7us, 7 = 7us (no typo)
2654 * bit 3..5: L1: 0 = 1us, 1 = 2us .. 6 = 64us, 7 = 64us
2656 if (pdev->cfg_size > 0x070f &&
2657 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
2660 netdev_notice_once(tp->dev,
2661 "No native access to PCI extended config space, falling back to CSI\n");
2662 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
2663 rtl_csi_write(tp, 0x070c, csi | val << 24);
2666 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
2668 /* L0 7us, L1 16us */
2669 rtl_set_aspm_entry_latency(tp, 0x27);
2673 unsigned int offset;
2678 static void __rtl_ephy_init(struct rtl8169_private *tp,
2679 const struct ephy_info *e, int len)
2684 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
2685 rtl_ephy_write(tp, e->offset, w);
2690 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a))
2692 static void rtl_disable_clock_request(struct rtl8169_private *tp)
2694 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
2695 PCI_EXP_LNKCTL_CLKREQ_EN);
2698 static void rtl_enable_clock_request(struct rtl8169_private *tp)
2700 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
2701 PCI_EXP_LNKCTL_CLKREQ_EN);
2704 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp)
2706 /* work around an issue when PCI reset occurs during L2/L3 state */
2707 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23);
2710 static void rtl_enable_exit_l1(struct rtl8169_private *tp)
2712 /* Bits control which events trigger ASPM L1 exit:
2715 * Bit 10: txdma_poll
2720 switch (tp->mac_version) {
2721 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
2722 rtl_eri_set_bits(tp, 0xd4, 0x1f00);
2724 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_38:
2725 rtl_eri_set_bits(tp, 0xd4, 0x0c00);
2727 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
2728 r8168_mac_ocp_modify(tp, 0xc0ac, 0, 0x1f80);
2735 static void rtl_disable_exit_l1(struct rtl8169_private *tp)
2737 switch (tp->mac_version) {
2738 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
2739 rtl_eri_clear_bits(tp, 0xd4, 0x1f00);
2741 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
2742 r8168_mac_ocp_modify(tp, 0xc0ac, 0x1f80, 0);
2749 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
2751 if (tp->mac_version < RTL_GIGA_MAC_VER_32)
2754 /* Don't enable ASPM in the chip if OS can't control ASPM */
2755 if (enable && tp->aspm_manageable) {
2756 /* On these chip versions ASPM can even harm
2757 * bus communication of other PCI devices.
2759 if (tp->mac_version == RTL_GIGA_MAC_VER_42 ||
2760 tp->mac_version == RTL_GIGA_MAC_VER_43)
2763 rtl_mod_config5(tp, 0, ASPM_en);
2764 rtl_mod_config2(tp, 0, ClkReqEn);
2766 switch (tp->mac_version) {
2767 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48:
2768 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63:
2769 /* reset ephy tx/rx disable timer */
2770 r8168_mac_ocp_modify(tp, 0xe094, 0xff00, 0);
2771 /* chip can trigger L1.2 */
2772 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, BIT(2));
2778 switch (tp->mac_version) {
2779 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48:
2780 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63:
2781 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, 0);
2787 rtl_mod_config2(tp, ClkReqEn, 0);
2788 rtl_mod_config5(tp, ASPM_en, 0);
2792 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat,
2793 u16 tx_stat, u16 rx_dyn, u16 tx_dyn)
2795 /* Usage of dynamic vs. static FIFO is controlled by bit
2796 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known.
2798 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn);
2799 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn);
2802 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp,
2805 /* FIFO thresholds for pause flow control */
2806 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low);
2807 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high);
2810 static void rtl_hw_start_8168b(struct rtl8169_private *tp)
2812 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2815 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
2817 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
2819 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2821 rtl_disable_clock_request(tp);
2824 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
2826 static const struct ephy_info e_info_8168cp[] = {
2827 { 0x01, 0, 0x0001 },
2828 { 0x02, 0x0800, 0x1000 },
2829 { 0x03, 0, 0x0042 },
2830 { 0x06, 0x0080, 0x0000 },
2834 rtl_set_def_aspm_entry_latency(tp);
2836 rtl_ephy_init(tp, e_info_8168cp);
2838 __rtl_hw_start_8168cp(tp);
2841 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
2843 rtl_set_def_aspm_entry_latency(tp);
2845 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2848 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
2850 rtl_set_def_aspm_entry_latency(tp);
2852 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2855 RTL_W8(tp, DBG_REG, 0x20);
2858 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
2860 static const struct ephy_info e_info_8168c_1[] = {
2861 { 0x02, 0x0800, 0x1000 },
2862 { 0x03, 0, 0x0002 },
2863 { 0x06, 0x0080, 0x0000 }
2866 rtl_set_def_aspm_entry_latency(tp);
2868 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
2870 rtl_ephy_init(tp, e_info_8168c_1);
2872 __rtl_hw_start_8168cp(tp);
2875 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
2877 static const struct ephy_info e_info_8168c_2[] = {
2878 { 0x01, 0, 0x0001 },
2879 { 0x03, 0x0400, 0x0020 }
2882 rtl_set_def_aspm_entry_latency(tp);
2884 rtl_ephy_init(tp, e_info_8168c_2);
2886 __rtl_hw_start_8168cp(tp);
2889 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
2891 rtl_set_def_aspm_entry_latency(tp);
2893 __rtl_hw_start_8168cp(tp);
2896 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
2898 rtl_set_def_aspm_entry_latency(tp);
2900 rtl_disable_clock_request(tp);
2903 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
2905 static const struct ephy_info e_info_8168d_4[] = {
2906 { 0x0b, 0x0000, 0x0048 },
2907 { 0x19, 0x0020, 0x0050 },
2908 { 0x0c, 0x0100, 0x0020 },
2909 { 0x10, 0x0004, 0x0000 },
2912 rtl_set_def_aspm_entry_latency(tp);
2914 rtl_ephy_init(tp, e_info_8168d_4);
2916 rtl_enable_clock_request(tp);
2919 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
2921 static const struct ephy_info e_info_8168e_1[] = {
2922 { 0x00, 0x0200, 0x0100 },
2923 { 0x00, 0x0000, 0x0004 },
2924 { 0x06, 0x0002, 0x0001 },
2925 { 0x06, 0x0000, 0x0030 },
2926 { 0x07, 0x0000, 0x2000 },
2927 { 0x00, 0x0000, 0x0020 },
2928 { 0x03, 0x5800, 0x2000 },
2929 { 0x03, 0x0000, 0x0001 },
2930 { 0x01, 0x0800, 0x1000 },
2931 { 0x07, 0x0000, 0x4000 },
2932 { 0x1e, 0x0000, 0x2000 },
2933 { 0x19, 0xffff, 0xfe6c },
2934 { 0x0a, 0x0000, 0x0040 }
2937 rtl_set_def_aspm_entry_latency(tp);
2939 rtl_ephy_init(tp, e_info_8168e_1);
2941 rtl_disable_clock_request(tp);
2943 /* Reset tx FIFO pointer */
2944 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
2945 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
2947 rtl_mod_config5(tp, Spi_en, 0);
2950 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
2952 static const struct ephy_info e_info_8168e_2[] = {
2953 { 0x09, 0x0000, 0x0080 },
2954 { 0x19, 0x0000, 0x0224 },
2955 { 0x00, 0x0000, 0x0004 },
2956 { 0x0c, 0x3df0, 0x0200 },
2959 rtl_set_def_aspm_entry_latency(tp);
2961 rtl_ephy_init(tp, e_info_8168e_2);
2963 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
2964 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000);
2965 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
2966 rtl_eri_set_bits(tp, 0x1d0, BIT(1));
2967 rtl_reset_packet_filter(tp);
2968 rtl_eri_set_bits(tp, 0x1b0, BIT(4));
2969 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
2970 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060);
2972 rtl_disable_clock_request(tp);
2974 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
2976 rtl8168_config_eee_mac(tp);
2978 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
2979 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
2980 rtl_mod_config5(tp, Spi_en, 0);
2983 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
2985 rtl_set_def_aspm_entry_latency(tp);
2987 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
2988 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000);
2989 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
2990 rtl_reset_packet_filter(tp);
2991 rtl_eri_set_bits(tp, 0x1b0, BIT(4));
2992 rtl_eri_set_bits(tp, 0x1d0, BIT(4) | BIT(1));
2993 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
2994 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060);
2996 rtl_disable_clock_request(tp);
2998 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
2999 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
3000 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
3001 rtl_mod_config5(tp, Spi_en, 0);
3003 rtl8168_config_eee_mac(tp);
3006 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
3008 static const struct ephy_info e_info_8168f_1[] = {
3009 { 0x06, 0x00c0, 0x0020 },
3010 { 0x08, 0x0001, 0x0002 },
3011 { 0x09, 0x0000, 0x0080 },
3012 { 0x19, 0x0000, 0x0224 },
3013 { 0x00, 0x0000, 0x0008 },
3014 { 0x0c, 0x3df0, 0x0200 },
3017 rtl_hw_start_8168f(tp);
3019 rtl_ephy_init(tp, e_info_8168f_1);
3022 static void rtl_hw_start_8411(struct rtl8169_private *tp)
3024 static const struct ephy_info e_info_8168f_1[] = {
3025 { 0x06, 0x00c0, 0x0020 },
3026 { 0x0f, 0xffff, 0x5200 },
3027 { 0x19, 0x0000, 0x0224 },
3028 { 0x00, 0x0000, 0x0008 },
3029 { 0x0c, 0x3df0, 0x0200 },
3032 rtl_hw_start_8168f(tp);
3033 rtl_pcie_state_l2l3_disable(tp);
3035 rtl_ephy_init(tp, e_info_8168f_1);
3038 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
3040 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3041 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
3043 rtl_set_def_aspm_entry_latency(tp);
3045 rtl_reset_packet_filter(tp);
3046 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f);
3048 rtl_disable_rxdvgate(tp);
3050 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3051 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3053 rtl8168_config_eee_mac(tp);
3055 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06);
3056 rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
3058 rtl_pcie_state_l2l3_disable(tp);
3061 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
3063 static const struct ephy_info e_info_8168g_1[] = {
3064 { 0x00, 0x0008, 0x0000 },
3065 { 0x0c, 0x3ff0, 0x0820 },
3066 { 0x1e, 0x0000, 0x0001 },
3067 { 0x19, 0x8000, 0x0000 }
3070 rtl_hw_start_8168g(tp);
3071 rtl_ephy_init(tp, e_info_8168g_1);
3074 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
3076 static const struct ephy_info e_info_8168g_2[] = {
3077 { 0x00, 0x0008, 0x0000 },
3078 { 0x0c, 0x3ff0, 0x0820 },
3079 { 0x19, 0xffff, 0x7c00 },
3080 { 0x1e, 0xffff, 0x20eb },
3081 { 0x0d, 0xffff, 0x1666 },
3082 { 0x00, 0xffff, 0x10a3 },
3083 { 0x06, 0xffff, 0xf050 },
3084 { 0x04, 0x0000, 0x0010 },
3085 { 0x1d, 0x4000, 0x0000 },
3088 rtl_hw_start_8168g(tp);
3089 rtl_ephy_init(tp, e_info_8168g_2);
3092 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
3094 static const struct ephy_info e_info_8411_2[] = {
3095 { 0x00, 0x0008, 0x0000 },
3096 { 0x0c, 0x37d0, 0x0820 },
3097 { 0x1e, 0x0000, 0x0001 },
3098 { 0x19, 0x8021, 0x0000 },
3099 { 0x1e, 0x0000, 0x2000 },
3100 { 0x0d, 0x0100, 0x0200 },
3101 { 0x00, 0x0000, 0x0080 },
3102 { 0x06, 0x0000, 0x0010 },
3103 { 0x04, 0x0000, 0x0010 },
3104 { 0x1d, 0x0000, 0x4000 },
3107 rtl_hw_start_8168g(tp);
3109 rtl_ephy_init(tp, e_info_8411_2);
3111 /* The following Realtek-provided magic fixes an issue with the RX unit
3112 * getting confused after the PHY having been powered-down.
3114 r8168_mac_ocp_write(tp, 0xFC28, 0x0000);
3115 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000);
3116 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000);
3117 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000);
3118 r8168_mac_ocp_write(tp, 0xFC30, 0x0000);
3119 r8168_mac_ocp_write(tp, 0xFC32, 0x0000);
3120 r8168_mac_ocp_write(tp, 0xFC34, 0x0000);
3121 r8168_mac_ocp_write(tp, 0xFC36, 0x0000);
3123 r8168_mac_ocp_write(tp, 0xFC26, 0x0000);
3125 r8168_mac_ocp_write(tp, 0xF800, 0xE008);
3126 r8168_mac_ocp_write(tp, 0xF802, 0xE00A);
3127 r8168_mac_ocp_write(tp, 0xF804, 0xE00C);
3128 r8168_mac_ocp_write(tp, 0xF806, 0xE00E);
3129 r8168_mac_ocp_write(tp, 0xF808, 0xE027);
3130 r8168_mac_ocp_write(tp, 0xF80A, 0xE04F);
3131 r8168_mac_ocp_write(tp, 0xF80C, 0xE05E);
3132 r8168_mac_ocp_write(tp, 0xF80E, 0xE065);
3133 r8168_mac_ocp_write(tp, 0xF810, 0xC602);
3134 r8168_mac_ocp_write(tp, 0xF812, 0xBE00);
3135 r8168_mac_ocp_write(tp, 0xF814, 0x0000);
3136 r8168_mac_ocp_write(tp, 0xF816, 0xC502);
3137 r8168_mac_ocp_write(tp, 0xF818, 0xBD00);
3138 r8168_mac_ocp_write(tp, 0xF81A, 0x074C);
3139 r8168_mac_ocp_write(tp, 0xF81C, 0xC302);
3140 r8168_mac_ocp_write(tp, 0xF81E, 0xBB00);
3141 r8168_mac_ocp_write(tp, 0xF820, 0x080A);
3142 r8168_mac_ocp_write(tp, 0xF822, 0x6420);
3143 r8168_mac_ocp_write(tp, 0xF824, 0x48C2);
3144 r8168_mac_ocp_write(tp, 0xF826, 0x8C20);
3145 r8168_mac_ocp_write(tp, 0xF828, 0xC516);
3146 r8168_mac_ocp_write(tp, 0xF82A, 0x64A4);
3147 r8168_mac_ocp_write(tp, 0xF82C, 0x49C0);
3148 r8168_mac_ocp_write(tp, 0xF82E, 0xF009);
3149 r8168_mac_ocp_write(tp, 0xF830, 0x74A2);
3150 r8168_mac_ocp_write(tp, 0xF832, 0x8CA5);
3151 r8168_mac_ocp_write(tp, 0xF834, 0x74A0);
3152 r8168_mac_ocp_write(tp, 0xF836, 0xC50E);
3153 r8168_mac_ocp_write(tp, 0xF838, 0x9CA2);
3154 r8168_mac_ocp_write(tp, 0xF83A, 0x1C11);
3155 r8168_mac_ocp_write(tp, 0xF83C, 0x9CA0);
3156 r8168_mac_ocp_write(tp, 0xF83E, 0xE006);
3157 r8168_mac_ocp_write(tp, 0xF840, 0x74F8);
3158 r8168_mac_ocp_write(tp, 0xF842, 0x48C4);
3159 r8168_mac_ocp_write(tp, 0xF844, 0x8CF8);
3160 r8168_mac_ocp_write(tp, 0xF846, 0xC404);
3161 r8168_mac_ocp_write(tp, 0xF848, 0xBC00);
3162 r8168_mac_ocp_write(tp, 0xF84A, 0xC403);
3163 r8168_mac_ocp_write(tp, 0xF84C, 0xBC00);
3164 r8168_mac_ocp_write(tp, 0xF84E, 0x0BF2);
3165 r8168_mac_ocp_write(tp, 0xF850, 0x0C0A);
3166 r8168_mac_ocp_write(tp, 0xF852, 0xE434);
3167 r8168_mac_ocp_write(tp, 0xF854, 0xD3C0);
3168 r8168_mac_ocp_write(tp, 0xF856, 0x49D9);
3169 r8168_mac_ocp_write(tp, 0xF858, 0xF01F);
3170 r8168_mac_ocp_write(tp, 0xF85A, 0xC526);
3171 r8168_mac_ocp_write(tp, 0xF85C, 0x64A5);
3172 r8168_mac_ocp_write(tp, 0xF85E, 0x1400);
3173 r8168_mac_ocp_write(tp, 0xF860, 0xF007);
3174 r8168_mac_ocp_write(tp, 0xF862, 0x0C01);
3175 r8168_mac_ocp_write(tp, 0xF864, 0x8CA5);
3176 r8168_mac_ocp_write(tp, 0xF866, 0x1C15);
3177 r8168_mac_ocp_write(tp, 0xF868, 0xC51B);
3178 r8168_mac_ocp_write(tp, 0xF86A, 0x9CA0);
3179 r8168_mac_ocp_write(tp, 0xF86C, 0xE013);
3180 r8168_mac_ocp_write(tp, 0xF86E, 0xC519);
3181 r8168_mac_ocp_write(tp, 0xF870, 0x74A0);
3182 r8168_mac_ocp_write(tp, 0xF872, 0x48C4);
3183 r8168_mac_ocp_write(tp, 0xF874, 0x8CA0);
3184 r8168_mac_ocp_write(tp, 0xF876, 0xC516);
3185 r8168_mac_ocp_write(tp, 0xF878, 0x74A4);
3186 r8168_mac_ocp_write(tp, 0xF87A, 0x48C8);
3187 r8168_mac_ocp_write(tp, 0xF87C, 0x48CA);
3188 r8168_mac_ocp_write(tp, 0xF87E, 0x9CA4);
3189 r8168_mac_ocp_write(tp, 0xF880, 0xC512);
3190 r8168_mac_ocp_write(tp, 0xF882, 0x1B00);
3191 r8168_mac_ocp_write(tp, 0xF884, 0x9BA0);
3192 r8168_mac_ocp_write(tp, 0xF886, 0x1B1C);
3193 r8168_mac_ocp_write(tp, 0xF888, 0x483F);
3194 r8168_mac_ocp_write(tp, 0xF88A, 0x9BA2);
3195 r8168_mac_ocp_write(tp, 0xF88C, 0x1B04);
3196 r8168_mac_ocp_write(tp, 0xF88E, 0xC508);
3197 r8168_mac_ocp_write(tp, 0xF890, 0x9BA0);
3198 r8168_mac_ocp_write(tp, 0xF892, 0xC505);
3199 r8168_mac_ocp_write(tp, 0xF894, 0xBD00);
3200 r8168_mac_ocp_write(tp, 0xF896, 0xC502);
3201 r8168_mac_ocp_write(tp, 0xF898, 0xBD00);
3202 r8168_mac_ocp_write(tp, 0xF89A, 0x0300);
3203 r8168_mac_ocp_write(tp, 0xF89C, 0x051E);
3204 r8168_mac_ocp_write(tp, 0xF89E, 0xE434);
3205 r8168_mac_ocp_write(tp, 0xF8A0, 0xE018);
3206 r8168_mac_ocp_write(tp, 0xF8A2, 0xE092);
3207 r8168_mac_ocp_write(tp, 0xF8A4, 0xDE20);
3208 r8168_mac_ocp_write(tp, 0xF8A6, 0xD3C0);
3209 r8168_mac_ocp_write(tp, 0xF8A8, 0xC50F);
3210 r8168_mac_ocp_write(tp, 0xF8AA, 0x76A4);
3211 r8168_mac_ocp_write(tp, 0xF8AC, 0x49E3);
3212 r8168_mac_ocp_write(tp, 0xF8AE, 0xF007);
3213 r8168_mac_ocp_write(tp, 0xF8B0, 0x49C0);
3214 r8168_mac_ocp_write(tp, 0xF8B2, 0xF103);
3215 r8168_mac_ocp_write(tp, 0xF8B4, 0xC607);
3216 r8168_mac_ocp_write(tp, 0xF8B6, 0xBE00);
3217 r8168_mac_ocp_write(tp, 0xF8B8, 0xC606);
3218 r8168_mac_ocp_write(tp, 0xF8BA, 0xBE00);
3219 r8168_mac_ocp_write(tp, 0xF8BC, 0xC602);
3220 r8168_mac_ocp_write(tp, 0xF8BE, 0xBE00);
3221 r8168_mac_ocp_write(tp, 0xF8C0, 0x0C4C);
3222 r8168_mac_ocp_write(tp, 0xF8C2, 0x0C28);
3223 r8168_mac_ocp_write(tp, 0xF8C4, 0x0C2C);
3224 r8168_mac_ocp_write(tp, 0xF8C6, 0xDC00);
3225 r8168_mac_ocp_write(tp, 0xF8C8, 0xC707);
3226 r8168_mac_ocp_write(tp, 0xF8CA, 0x1D00);
3227 r8168_mac_ocp_write(tp, 0xF8CC, 0x8DE2);
3228 r8168_mac_ocp_write(tp, 0xF8CE, 0x48C1);
3229 r8168_mac_ocp_write(tp, 0xF8D0, 0xC502);
3230 r8168_mac_ocp_write(tp, 0xF8D2, 0xBD00);
3231 r8168_mac_ocp_write(tp, 0xF8D4, 0x00AA);
3232 r8168_mac_ocp_write(tp, 0xF8D6, 0xE0C0);
3233 r8168_mac_ocp_write(tp, 0xF8D8, 0xC502);
3234 r8168_mac_ocp_write(tp, 0xF8DA, 0xBD00);
3235 r8168_mac_ocp_write(tp, 0xF8DC, 0x0132);
3237 r8168_mac_ocp_write(tp, 0xFC26, 0x8000);
3239 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743);
3240 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801);
3241 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9);
3242 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD);
3243 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25);
3244 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9);
3245 r8168_mac_ocp_write(tp, 0xFC36, 0x012D);
3248 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
3250 static const struct ephy_info e_info_8168h_1[] = {
3251 { 0x1e, 0x0800, 0x0001 },
3252 { 0x1d, 0x0000, 0x0800 },
3253 { 0x05, 0xffff, 0x2089 },
3254 { 0x06, 0xffff, 0x5881 },
3255 { 0x04, 0xffff, 0x854a },
3256 { 0x01, 0xffff, 0x068b }
3260 rtl_ephy_init(tp, e_info_8168h_1);
3262 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3263 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
3265 rtl_set_def_aspm_entry_latency(tp);
3267 rtl_reset_packet_filter(tp);
3269 rtl_eri_set_bits(tp, 0xdc, 0x001c);
3271 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3273 rtl_disable_rxdvgate(tp);
3275 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3276 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3278 rtl8168_config_eee_mac(tp);
3280 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3281 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3283 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3285 rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
3287 rtl_pcie_state_l2l3_disable(tp);
3289 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff;
3290 if (rg_saw_cnt > 0) {
3293 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
3294 sw_cnt_1ms_ini &= 0x0fff;
3295 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);
3298 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);
3299 r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008);
3300 r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f);
3301 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);
3303 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
3304 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
3305 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
3306 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
3309 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
3311 rtl8168ep_stop_cmac(tp);
3313 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3314 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
3316 rtl_set_def_aspm_entry_latency(tp);
3318 rtl_reset_packet_filter(tp);
3320 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3322 rtl_disable_rxdvgate(tp);
3324 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3325 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3327 rtl8168_config_eee_mac(tp);
3329 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06);
3331 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3333 rtl_pcie_state_l2l3_disable(tp);
3336 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
3338 static const struct ephy_info e_info_8168ep_3[] = {
3339 { 0x00, 0x0000, 0x0080 },
3340 { 0x0d, 0x0100, 0x0200 },
3341 { 0x19, 0x8021, 0x0000 },
3342 { 0x1e, 0x0000, 0x2000 },
3345 rtl_ephy_init(tp, e_info_8168ep_3);
3347 rtl_hw_start_8168ep(tp);
3349 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3350 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3352 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271);
3353 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
3354 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);
3357 static void rtl_hw_start_8117(struct rtl8169_private *tp)
3359 static const struct ephy_info e_info_8117[] = {
3360 { 0x19, 0x0040, 0x1100 },
3361 { 0x59, 0x0040, 0x1100 },
3365 rtl8168ep_stop_cmac(tp);
3366 rtl_ephy_init(tp, e_info_8117);
3368 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3369 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
3371 rtl_set_def_aspm_entry_latency(tp);
3373 rtl_reset_packet_filter(tp);
3375 rtl_eri_set_bits(tp, 0xd4, 0x0010);
3377 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3379 rtl_disable_rxdvgate(tp);
3381 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3382 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3384 rtl8168_config_eee_mac(tp);
3386 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3387 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3389 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3391 rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
3393 rtl_pcie_state_l2l3_disable(tp);
3395 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff;
3396 if (rg_saw_cnt > 0) {
3399 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff;
3400 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);
3403 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);
3404 r8168_mac_ocp_write(tp, 0xea80, 0x0003);
3405 r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009);
3406 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);
3408 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
3409 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
3410 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
3411 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
3413 /* firmware is for MAC only */
3414 r8169_apply_firmware(tp);
3417 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
3419 static const struct ephy_info e_info_8102e_1[] = {
3420 { 0x01, 0, 0x6e65 },
3421 { 0x02, 0, 0x091f },
3422 { 0x03, 0, 0xc2f9 },
3423 { 0x06, 0, 0xafb5 },
3424 { 0x07, 0, 0x0e00 },
3425 { 0x19, 0, 0xec80 },
3426 { 0x01, 0, 0x2e65 },
3431 rtl_set_def_aspm_entry_latency(tp);
3433 RTL_W8(tp, DBG_REG, FIX_NAK_1);
3436 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
3437 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3439 cfg1 = RTL_R8(tp, Config1);
3440 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
3441 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
3443 rtl_ephy_init(tp, e_info_8102e_1);
3446 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
3448 rtl_set_def_aspm_entry_latency(tp);
3450 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
3451 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3454 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
3456 rtl_hw_start_8102e_2(tp);
3458 rtl_ephy_write(tp, 0x03, 0xc2f9);
3461 static void rtl_hw_start_8401(struct rtl8169_private *tp)
3463 static const struct ephy_info e_info_8401[] = {
3464 { 0x01, 0xffff, 0x6fe5 },
3465 { 0x03, 0xffff, 0x0599 },
3466 { 0x06, 0xffff, 0xaf25 },
3467 { 0x07, 0xffff, 0x8e68 },
3470 rtl_ephy_init(tp, e_info_8401);
3471 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3474 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
3476 static const struct ephy_info e_info_8105e_1[] = {
3477 { 0x07, 0, 0x4000 },
3478 { 0x19, 0, 0x0200 },
3479 { 0x19, 0, 0x0020 },
3480 { 0x1e, 0, 0x2000 },
3481 { 0x03, 0, 0x0001 },
3482 { 0x19, 0, 0x0100 },
3483 { 0x19, 0, 0x0004 },
3487 /* Force LAN exit from ASPM if Rx/Tx are not idle */
3488 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3490 /* Disable Early Tally Counter */
3491 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
3493 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
3494 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
3496 rtl_ephy_init(tp, e_info_8105e_1);
3498 rtl_pcie_state_l2l3_disable(tp);
3501 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
3503 rtl_hw_start_8105e_1(tp);
3504 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
3507 static void rtl_hw_start_8402(struct rtl8169_private *tp)
3509 static const struct ephy_info e_info_8402[] = {
3510 { 0x19, 0xffff, 0xff64 },
3514 rtl_set_def_aspm_entry_latency(tp);
3516 /* Force LAN exit from ASPM if Rx/Tx are not idle */
3517 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3519 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
3521 rtl_ephy_init(tp, e_info_8402);
3523 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06);
3524 rtl_reset_packet_filter(tp);
3525 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3526 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3527 rtl_w0w1_eri(tp, 0x0d4, 0x0e00, 0xff00);
3530 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3532 rtl_pcie_state_l2l3_disable(tp);
3535 static void rtl_hw_start_8106(struct rtl8169_private *tp)
3537 /* Force LAN exit from ASPM if Rx/Tx are not idle */
3538 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3540 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
3541 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
3542 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3544 /* L0 7us, L1 32us - needed to avoid issues with link-up detection */
3545 rtl_set_aspm_entry_latency(tp, 0x2f);
3547 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
3550 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3552 rtl_pcie_state_l2l3_disable(tp);
3555 DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond)
3557 return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13);
3560 static void rtl_hw_start_8125_common(struct rtl8169_private *tp)
3562 rtl_pcie_state_l2l3_disable(tp);
3564 RTL_W16(tp, 0x382, 0x221b);
3565 RTL_W8(tp, 0x4500, 0);
3566 RTL_W16(tp, 0x4800, 0);
3569 r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000);
3571 RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10);
3573 r8168_mac_ocp_write(tp, 0xc140, 0xffff);
3574 r8168_mac_ocp_write(tp, 0xc142, 0xffff);
3576 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9);
3577 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
3578 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);
3580 /* disable new tx descriptor format */
3581 r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000);
3583 if (tp->mac_version == RTL_GIGA_MAC_VER_63)
3584 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200);
3586 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400);
3588 if (tp->mac_version == RTL_GIGA_MAC_VER_63)
3589 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0000);
3591 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020);
3593 r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c);
3594 r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033);
3595 r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040);
3596 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030);
3597 r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000);
3598 r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001);
3599 r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403);
3600 r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0068);
3601 r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f);
3603 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000);
3604 r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001);
3606 r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000);
3607 RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030);
3609 r8168_mac_ocp_write(tp, 0xe098, 0xc302);
3611 rtl_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10);
3613 if (tp->mac_version == RTL_GIGA_MAC_VER_63)
3614 rtl8125b_config_eee_mac(tp);
3616 rtl8125a_config_eee_mac(tp);
3618 rtl_disable_rxdvgate(tp);
3621 static void rtl_hw_start_8125a_2(struct rtl8169_private *tp)
3623 static const struct ephy_info e_info_8125a_2[] = {
3624 { 0x04, 0xffff, 0xd000 },
3625 { 0x0a, 0xffff, 0x8653 },
3626 { 0x23, 0xffff, 0xab66 },
3627 { 0x20, 0xffff, 0x9455 },
3628 { 0x21, 0xffff, 0x99ff },
3629 { 0x29, 0xffff, 0xfe04 },
3631 { 0x44, 0xffff, 0xd000 },
3632 { 0x4a, 0xffff, 0x8653 },
3633 { 0x63, 0xffff, 0xab66 },
3634 { 0x60, 0xffff, 0x9455 },
3635 { 0x61, 0xffff, 0x99ff },
3636 { 0x69, 0xffff, 0xfe04 },
3639 rtl_set_def_aspm_entry_latency(tp);
3640 rtl_ephy_init(tp, e_info_8125a_2);
3641 rtl_hw_start_8125_common(tp);
3644 static void rtl_hw_start_8125b(struct rtl8169_private *tp)
3646 static const struct ephy_info e_info_8125b[] = {
3647 { 0x0b, 0xffff, 0xa908 },
3648 { 0x1e, 0xffff, 0x20eb },
3649 { 0x4b, 0xffff, 0xa908 },
3650 { 0x5e, 0xffff, 0x20eb },
3651 { 0x22, 0x0030, 0x0020 },
3652 { 0x62, 0x0030, 0x0020 },
3655 rtl_set_def_aspm_entry_latency(tp);
3656 rtl_ephy_init(tp, e_info_8125b);
3657 rtl_hw_start_8125_common(tp);
3660 static void rtl_hw_config(struct rtl8169_private *tp)
3662 static const rtl_generic_fct hw_configs[] = {
3663 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1,
3664 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3,
3665 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2,
3666 [RTL_GIGA_MAC_VER_10] = NULL,
3667 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168b,
3668 [RTL_GIGA_MAC_VER_14] = rtl_hw_start_8401,
3669 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b,
3670 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1,
3671 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1,
3672 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2,
3673 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_2,
3674 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4,
3675 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2,
3676 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3,
3677 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d,
3678 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d,
3679 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4,
3680 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1,
3681 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2,
3682 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168d,
3683 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1,
3684 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1,
3685 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2,
3686 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1,
3687 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1,
3688 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402,
3689 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411,
3690 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106,
3691 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1,
3692 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2,
3693 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2,
3694 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2,
3695 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1,
3696 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1,
3697 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3,
3698 [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117,
3699 [RTL_GIGA_MAC_VER_53] = rtl_hw_start_8117,
3700 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2,
3701 [RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b,
3704 if (hw_configs[tp->mac_version])
3705 hw_configs[tp->mac_version](tp);
3708 static void rtl_hw_start_8125(struct rtl8169_private *tp)
3712 /* disable interrupt coalescing */
3713 for (i = 0xa00; i < 0xb00; i += 4)
3719 static void rtl_hw_start_8168(struct rtl8169_private *tp)
3721 if (rtl_is_8168evl_up(tp))
3722 RTL_W8(tp, MaxTxPacketSize, EarlySize);
3724 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
3728 /* disable interrupt coalescing */
3729 RTL_W16(tp, IntrMitigate, 0x0000);
3732 static void rtl_hw_start_8169(struct rtl8169_private *tp)
3734 RTL_W8(tp, EarlyTxThres, NoEarlyTx);
3736 tp->cp_cmd |= PCIMulRW;
3738 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3739 tp->mac_version == RTL_GIGA_MAC_VER_03)
3740 tp->cp_cmd |= EnAnaPLL;
3742 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
3744 rtl8169_set_magic_reg(tp);
3746 /* disable interrupt coalescing */
3747 RTL_W16(tp, IntrMitigate, 0x0000);
3750 static void rtl_hw_start(struct rtl8169_private *tp)
3752 rtl_unlock_config_regs(tp);
3753 /* disable aspm and clock request before ephy access */
3754 rtl_hw_aspm_clkreq_enable(tp, false);
3755 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
3757 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3758 rtl_hw_start_8169(tp);
3759 else if (rtl_is_8125(tp))
3760 rtl_hw_start_8125(tp);
3762 rtl_hw_start_8168(tp);
3764 rtl_enable_exit_l1(tp);
3765 rtl_hw_aspm_clkreq_enable(tp, true);
3766 rtl_set_rx_max_size(tp);
3767 rtl_set_rx_tx_desc_registers(tp);
3768 rtl_lock_config_regs(tp);
3770 rtl_jumbo_config(tp);
3772 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3775 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
3777 rtl_set_tx_config_registers(tp);
3778 rtl_set_rx_config_features(tp, tp->dev->features);
3779 rtl_set_rx_mode(tp->dev);
3783 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
3785 struct rtl8169_private *tp = netdev_priv(dev);
3788 netdev_update_features(dev);
3789 rtl_jumbo_config(tp);
3791 switch (tp->mac_version) {
3792 case RTL_GIGA_MAC_VER_61:
3793 case RTL_GIGA_MAC_VER_63:
3794 rtl8125_set_eee_txidle_timer(tp);
3803 static void rtl8169_mark_to_asic(struct RxDesc *desc)
3805 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
3808 /* Force memory writes to complete before releasing descriptor */
3810 WRITE_ONCE(desc->opts1, cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE));
3813 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
3814 struct RxDesc *desc)
3816 struct device *d = tp_to_dev(tp);
3817 int node = dev_to_node(d);
3821 data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE));
3825 mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
3826 if (unlikely(dma_mapping_error(d, mapping))) {
3827 netdev_err(tp->dev, "Failed to map RX DMA!\n");
3828 __free_pages(data, get_order(R8169_RX_BUF_SIZE));
3832 desc->addr = cpu_to_le64(mapping);
3833 rtl8169_mark_to_asic(desc);
3838 static void rtl8169_rx_clear(struct rtl8169_private *tp)
3842 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) {
3843 dma_unmap_page(tp_to_dev(tp),
3844 le64_to_cpu(tp->RxDescArray[i].addr),
3845 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
3846 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE));
3847 tp->Rx_databuff[i] = NULL;
3848 tp->RxDescArray[i].addr = 0;
3849 tp->RxDescArray[i].opts1 = 0;
3853 static int rtl8169_rx_fill(struct rtl8169_private *tp)
3857 for (i = 0; i < NUM_RX_DESC; i++) {
3860 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
3862 rtl8169_rx_clear(tp);
3865 tp->Rx_databuff[i] = data;
3868 /* mark as last descriptor in the ring */
3869 tp->RxDescArray[NUM_RX_DESC - 1].opts1 |= cpu_to_le32(RingEnd);
3874 static int rtl8169_init_ring(struct rtl8169_private *tp)
3876 rtl8169_init_ring_indexes(tp);
3878 memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
3879 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
3881 return rtl8169_rx_fill(tp);
3884 static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int entry)
3886 struct ring_info *tx_skb = tp->tx_skb + entry;
3887 struct TxDesc *desc = tp->TxDescArray + entry;
3889 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), tx_skb->len,
3891 memset(desc, 0, sizeof(*desc));
3892 memset(tx_skb, 0, sizeof(*tx_skb));
3895 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
3900 for (i = 0; i < n; i++) {
3901 unsigned int entry = (start + i) % NUM_TX_DESC;
3902 struct ring_info *tx_skb = tp->tx_skb + entry;
3903 unsigned int len = tx_skb->len;
3906 struct sk_buff *skb = tx_skb->skb;
3908 rtl8169_unmap_tx_skb(tp, entry);
3910 dev_consume_skb_any(skb);
3915 static void rtl8169_tx_clear(struct rtl8169_private *tp)
3917 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
3918 netdev_reset_queue(tp->dev);
3921 static void rtl8169_cleanup(struct rtl8169_private *tp)
3923 napi_disable(&tp->napi);
3925 /* Give a racing hard_start_xmit a few cycles to complete. */
3928 /* Disable interrupts */
3929 rtl8169_irq_mask_and_ack(tp);
3933 switch (tp->mac_version) {
3934 case RTL_GIGA_MAC_VER_28:
3935 case RTL_GIGA_MAC_VER_31:
3936 rtl_loop_wait_low(tp, &rtl_npq_cond, 20, 2000);
3938 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
3939 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
3940 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
3942 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
3943 rtl_enable_rxdvgate(tp);
3947 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
3954 rtl8169_tx_clear(tp);
3955 rtl8169_init_ring_indexes(tp);
3958 static void rtl_reset_work(struct rtl8169_private *tp)
3962 netif_stop_queue(tp->dev);
3964 rtl8169_cleanup(tp);
3966 for (i = 0; i < NUM_RX_DESC; i++)
3967 rtl8169_mark_to_asic(tp->RxDescArray + i);
3969 napi_enable(&tp->napi);
3973 static void rtl8169_tx_timeout(struct net_device *dev, unsigned int txqueue)
3975 struct rtl8169_private *tp = netdev_priv(dev);
3977 rtl_schedule_task(tp, RTL_FLAG_TASK_TX_TIMEOUT);
3980 static int rtl8169_tx_map(struct rtl8169_private *tp, const u32 *opts, u32 len,
3981 void *addr, unsigned int entry, bool desc_own)
3983 struct TxDesc *txd = tp->TxDescArray + entry;
3984 struct device *d = tp_to_dev(tp);
3989 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
3990 ret = dma_mapping_error(d, mapping);
3991 if (unlikely(ret)) {
3992 if (net_ratelimit())
3993 netdev_err(tp->dev, "Failed to map TX data!\n");
3997 txd->addr = cpu_to_le64(mapping);
3998 txd->opts2 = cpu_to_le32(opts[1]);
4000 opts1 = opts[0] | len;
4001 if (entry == NUM_TX_DESC - 1)
4005 txd->opts1 = cpu_to_le32(opts1);
4007 tp->tx_skb[entry].len = len;
4012 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4013 const u32 *opts, unsigned int entry)
4015 struct skb_shared_info *info = skb_shinfo(skb);
4016 unsigned int cur_frag;
4018 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4019 const skb_frag_t *frag = info->frags + cur_frag;
4020 void *addr = skb_frag_address(frag);
4021 u32 len = skb_frag_size(frag);
4023 entry = (entry + 1) % NUM_TX_DESC;
4025 if (unlikely(rtl8169_tx_map(tp, opts, len, addr, entry, true)))
4032 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
4036 static bool rtl_skb_is_udp(struct sk_buff *skb)
4038 int no = skb_network_offset(skb);
4039 struct ipv6hdr *i6h, _i6h;
4040 struct iphdr *ih, _ih;
4042 switch (vlan_get_protocol(skb)) {
4043 case htons(ETH_P_IP):
4044 ih = skb_header_pointer(skb, no, sizeof(_ih), &_ih);
4045 return ih && ih->protocol == IPPROTO_UDP;
4046 case htons(ETH_P_IPV6):
4047 i6h = skb_header_pointer(skb, no, sizeof(_i6h), &_i6h);
4048 return i6h && i6h->nexthdr == IPPROTO_UDP;
4054 #define RTL_MIN_PATCH_LEN 47
4056 /* see rtl8125_get_patch_pad_len() in r8125 vendor driver */
4057 static unsigned int rtl8125_quirk_udp_padto(struct rtl8169_private *tp,
4058 struct sk_buff *skb)
4060 unsigned int padto = 0, len = skb->len;
4062 if (rtl_is_8125(tp) && len < 128 + RTL_MIN_PATCH_LEN &&
4063 rtl_skb_is_udp(skb) && skb_transport_header_was_set(skb)) {
4064 unsigned int trans_data_len = skb_tail_pointer(skb) -
4065 skb_transport_header(skb);
4067 if (trans_data_len >= offsetof(struct udphdr, len) &&
4068 trans_data_len < RTL_MIN_PATCH_LEN) {
4069 u16 dest = ntohs(udp_hdr(skb)->dest);
4071 /* dest is a standard PTP port */
4072 if (dest == 319 || dest == 320)
4073 padto = len + RTL_MIN_PATCH_LEN - trans_data_len;
4076 if (trans_data_len < sizeof(struct udphdr))
4077 padto = max_t(unsigned int, padto,
4078 len + sizeof(struct udphdr) - trans_data_len);
4084 static unsigned int rtl_quirk_packet_padto(struct rtl8169_private *tp,
4085 struct sk_buff *skb)
4089 padto = rtl8125_quirk_udp_padto(tp, skb);
4091 switch (tp->mac_version) {
4092 case RTL_GIGA_MAC_VER_34:
4093 case RTL_GIGA_MAC_VER_61:
4094 case RTL_GIGA_MAC_VER_63:
4095 padto = max_t(unsigned int, padto, ETH_ZLEN);
4104 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts)
4106 u32 mss = skb_shinfo(skb)->gso_size;
4110 opts[0] |= mss << TD0_MSS_SHIFT;
4111 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4112 const struct iphdr *ip = ip_hdr(skb);
4114 if (ip->protocol == IPPROTO_TCP)
4115 opts[0] |= TD0_IP_CS | TD0_TCP_CS;
4116 else if (ip->protocol == IPPROTO_UDP)
4117 opts[0] |= TD0_IP_CS | TD0_UDP_CS;
4123 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
4124 struct sk_buff *skb, u32 *opts)
4126 struct skb_shared_info *shinfo = skb_shinfo(skb);
4127 u32 mss = shinfo->gso_size;
4130 if (shinfo->gso_type & SKB_GSO_TCPV4) {
4131 opts[0] |= TD1_GTSENV4;
4132 } else if (shinfo->gso_type & SKB_GSO_TCPV6) {
4133 if (skb_cow_head(skb, 0))
4136 tcp_v6_gso_csum_prep(skb);
4137 opts[0] |= TD1_GTSENV6;
4142 opts[0] |= skb_transport_offset(skb) << GTTCPHO_SHIFT;
4143 opts[1] |= mss << TD1_MSS_SHIFT;
4144 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4147 switch (vlan_get_protocol(skb)) {
4148 case htons(ETH_P_IP):
4149 opts[1] |= TD1_IPv4_CS;
4150 ip_protocol = ip_hdr(skb)->protocol;
4153 case htons(ETH_P_IPV6):
4154 opts[1] |= TD1_IPv6_CS;
4155 ip_protocol = ipv6_hdr(skb)->nexthdr;
4159 ip_protocol = IPPROTO_RAW;
4163 if (ip_protocol == IPPROTO_TCP)
4164 opts[1] |= TD1_TCP_CS;
4165 else if (ip_protocol == IPPROTO_UDP)
4166 opts[1] |= TD1_UDP_CS;
4170 opts[1] |= skb_transport_offset(skb) << TCPHO_SHIFT;
4172 unsigned int padto = rtl_quirk_packet_padto(tp, skb);
4174 /* skb_padto would free the skb on error */
4175 return !__skb_put_padto(skb, padto, false);
4181 static unsigned int rtl_tx_slots_avail(struct rtl8169_private *tp)
4183 return READ_ONCE(tp->dirty_tx) + NUM_TX_DESC - READ_ONCE(tp->cur_tx);
4186 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */
4187 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
4189 switch (tp->mac_version) {
4190 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
4191 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
4198 static void rtl8169_doorbell(struct rtl8169_private *tp)
4200 if (rtl_is_8125(tp))
4201 RTL_W16(tp, TxPoll_8125, BIT(0));
4203 RTL_W8(tp, TxPoll, NPQ);
4206 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4207 struct net_device *dev)
4209 unsigned int frags = skb_shinfo(skb)->nr_frags;
4210 struct rtl8169_private *tp = netdev_priv(dev);
4211 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
4212 struct TxDesc *txd_first, *txd_last;
4213 bool stop_queue, door_bell;
4216 if (unlikely(!rtl_tx_slots_avail(tp))) {
4217 if (net_ratelimit())
4218 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
4222 opts[1] = rtl8169_tx_vlan_tag(skb);
4225 if (!rtl_chip_supports_csum_v2(tp))
4226 rtl8169_tso_csum_v1(skb, opts);
4227 else if (!rtl8169_tso_csum_v2(tp, skb, opts))
4230 if (unlikely(rtl8169_tx_map(tp, opts, skb_headlen(skb), skb->data,
4234 txd_first = tp->TxDescArray + entry;
4237 if (rtl8169_xmit_frags(tp, skb, opts, entry))
4239 entry = (entry + frags) % NUM_TX_DESC;
4242 txd_last = tp->TxDescArray + entry;
4243 txd_last->opts1 |= cpu_to_le32(LastFrag);
4244 tp->tx_skb[entry].skb = skb;
4246 skb_tx_timestamp(skb);
4248 /* Force memory writes to complete before releasing descriptor */
4251 door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more());
4253 txd_first->opts1 |= cpu_to_le32(DescOwn | FirstFrag);
4255 /* rtl_tx needs to see descriptor changes before updated tp->cur_tx */
4258 WRITE_ONCE(tp->cur_tx, tp->cur_tx + frags + 1);
4260 stop_queue = !netif_subqueue_maybe_stop(dev, 0, rtl_tx_slots_avail(tp),
4262 R8169_TX_START_THRS);
4263 if (door_bell || stop_queue)
4264 rtl8169_doorbell(tp);
4266 return NETDEV_TX_OK;
4269 rtl8169_unmap_tx_skb(tp, entry);
4271 dev_kfree_skb_any(skb);
4272 dev->stats.tx_dropped++;
4273 return NETDEV_TX_OK;
4276 netif_stop_queue(dev);
4277 dev->stats.tx_dropped++;
4278 return NETDEV_TX_BUSY;
4281 static unsigned int rtl_last_frag_len(struct sk_buff *skb)
4283 struct skb_shared_info *info = skb_shinfo(skb);
4284 unsigned int nr_frags = info->nr_frags;
4289 return skb_frag_size(info->frags + nr_frags - 1);
4292 /* Workaround for hw issues with TSO on RTL8168evl */
4293 static netdev_features_t rtl8168evl_fix_tso(struct sk_buff *skb,
4294 netdev_features_t features)
4296 /* IPv4 header has options field */
4297 if (vlan_get_protocol(skb) == htons(ETH_P_IP) &&
4298 ip_hdrlen(skb) > sizeof(struct iphdr))
4299 features &= ~NETIF_F_ALL_TSO;
4301 /* IPv4 TCP header has options field */
4302 else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4 &&
4303 tcp_hdrlen(skb) > sizeof(struct tcphdr))
4304 features &= ~NETIF_F_ALL_TSO;
4306 else if (rtl_last_frag_len(skb) <= 6)
4307 features &= ~NETIF_F_ALL_TSO;
4312 static netdev_features_t rtl8169_features_check(struct sk_buff *skb,
4313 struct net_device *dev,
4314 netdev_features_t features)
4316 struct rtl8169_private *tp = netdev_priv(dev);
4318 if (skb_is_gso(skb)) {
4319 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4320 features = rtl8168evl_fix_tso(skb, features);
4322 if (skb_transport_offset(skb) > GTTCPHO_MAX &&
4323 rtl_chip_supports_csum_v2(tp))
4324 features &= ~NETIF_F_ALL_TSO;
4325 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4326 /* work around hw bug on some chip versions */
4327 if (skb->len < ETH_ZLEN)
4328 features &= ~NETIF_F_CSUM_MASK;
4330 if (rtl_quirk_packet_padto(tp, skb))
4331 features &= ~NETIF_F_CSUM_MASK;
4333 if (skb_transport_offset(skb) > TCPHO_MAX &&
4334 rtl_chip_supports_csum_v2(tp))
4335 features &= ~NETIF_F_CSUM_MASK;
4338 return vlan_features_check(skb, features);
4341 static void rtl8169_pcierr_interrupt(struct net_device *dev)
4343 struct rtl8169_private *tp = netdev_priv(dev);
4344 struct pci_dev *pdev = tp->pci_dev;
4345 int pci_status_errs;
4348 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4350 pci_status_errs = pci_status_get_and_clear_errors(pdev);
4352 if (net_ratelimit())
4353 netdev_err(dev, "PCI error (cmd = 0x%04x, status_errs = 0x%04x)\n",
4354 pci_cmd, pci_status_errs);
4356 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
4359 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp,
4362 unsigned int dirty_tx, bytes_compl = 0, pkts_compl = 0;
4363 struct sk_buff *skb;
4365 dirty_tx = tp->dirty_tx;
4367 while (READ_ONCE(tp->cur_tx) != dirty_tx) {
4368 unsigned int entry = dirty_tx % NUM_TX_DESC;
4371 status = le32_to_cpu(READ_ONCE(tp->TxDescArray[entry].opts1));
4372 if (status & DescOwn)
4375 skb = tp->tx_skb[entry].skb;
4376 rtl8169_unmap_tx_skb(tp, entry);
4380 bytes_compl += skb->len;
4381 napi_consume_skb(skb, budget);
4386 if (tp->dirty_tx != dirty_tx) {
4387 dev_sw_netstats_tx_add(dev, pkts_compl, bytes_compl);
4388 WRITE_ONCE(tp->dirty_tx, dirty_tx);
4390 netif_subqueue_completed_wake(dev, 0, pkts_compl, bytes_compl,
4391 rtl_tx_slots_avail(tp),
4392 R8169_TX_START_THRS);
4394 * 8168 hack: TxPoll requests are lost when the Tx packets are
4395 * too close. Let's kick an extra TxPoll request when a burst
4396 * of start_xmit activity is detected (if it is not detected,
4397 * it is slow enough). -- FR
4398 * If skb is NULL then we come here again once a tx irq is
4399 * triggered after the last fragment is marked transmitted.
4401 if (READ_ONCE(tp->cur_tx) != dirty_tx && skb)
4402 rtl8169_doorbell(tp);
4406 static inline int rtl8169_fragmented_frame(u32 status)
4408 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4411 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
4413 u32 status = opts1 & (RxProtoMask | RxCSFailMask);
4415 if (status == RxProtoTCP || status == RxProtoUDP)
4416 skb->ip_summed = CHECKSUM_UNNECESSARY;
4418 skb_checksum_none_assert(skb);
4421 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, int budget)
4423 struct device *d = tp_to_dev(tp);
4426 for (count = 0; count < budget; count++, tp->cur_rx++) {
4427 unsigned int pkt_size, entry = tp->cur_rx % NUM_RX_DESC;
4428 struct RxDesc *desc = tp->RxDescArray + entry;
4429 struct sk_buff *skb;
4434 status = le32_to_cpu(READ_ONCE(desc->opts1));
4435 if (status & DescOwn)
4438 /* This barrier is needed to keep us from reading
4439 * any other fields out of the Rx descriptor until
4440 * we know the status of DescOwn
4444 if (unlikely(status & RxRES)) {
4445 if (net_ratelimit())
4446 netdev_warn(dev, "Rx ERROR. status = %08x\n",
4448 dev->stats.rx_errors++;
4449 if (status & (RxRWT | RxRUNT))
4450 dev->stats.rx_length_errors++;
4452 dev->stats.rx_crc_errors++;
4454 if (!(dev->features & NETIF_F_RXALL))
4455 goto release_descriptor;
4456 else if (status & RxRWT || !(status & (RxRUNT | RxCRC)))
4457 goto release_descriptor;
4460 pkt_size = status & GENMASK(13, 0);
4461 if (likely(!(dev->features & NETIF_F_RXFCS)))
4462 pkt_size -= ETH_FCS_LEN;
4464 /* The driver does not support incoming fragmented frames.
4465 * They are seen as a symptom of over-mtu sized frames.
4467 if (unlikely(rtl8169_fragmented_frame(status))) {
4468 dev->stats.rx_dropped++;
4469 dev->stats.rx_length_errors++;
4470 goto release_descriptor;
4473 skb = napi_alloc_skb(&tp->napi, pkt_size);
4474 if (unlikely(!skb)) {
4475 dev->stats.rx_dropped++;
4476 goto release_descriptor;
4479 addr = le64_to_cpu(desc->addr);
4480 rx_buf = page_address(tp->Rx_databuff[entry]);
4482 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
4484 skb_copy_to_linear_data(skb, rx_buf, pkt_size);
4485 skb->tail += pkt_size;
4486 skb->len = pkt_size;
4487 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
4489 rtl8169_rx_csum(skb, status);
4490 skb->protocol = eth_type_trans(skb, dev);
4492 rtl8169_rx_vlan_tag(desc, skb);
4494 if (skb->pkt_type == PACKET_MULTICAST)
4495 dev->stats.multicast++;
4497 napi_gro_receive(&tp->napi, skb);
4499 dev_sw_netstats_rx_add(dev, pkt_size);
4501 rtl8169_mark_to_asic(desc);
4507 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
4509 struct rtl8169_private *tp = dev_instance;
4510 u32 status = rtl_get_events(tp);
4512 if ((status & 0xffff) == 0xffff || !(status & tp->irq_mask))
4515 if (unlikely(status & SYSErr)) {
4516 rtl8169_pcierr_interrupt(tp->dev);
4520 if (status & LinkChg)
4521 phy_mac_interrupt(tp->phydev);
4523 if (unlikely(status & RxFIFOOver &&
4524 tp->mac_version == RTL_GIGA_MAC_VER_11)) {
4525 netif_stop_queue(tp->dev);
4526 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
4529 if (napi_schedule_prep(&tp->napi)) {
4530 rtl_irq_disable(tp);
4531 __napi_schedule(&tp->napi);
4534 rtl_ack_events(tp, status);
4539 static void rtl_task(struct work_struct *work)
4541 struct rtl8169_private *tp =
4542 container_of(work, struct rtl8169_private, wk.work);
4547 if (!netif_running(tp->dev) ||
4548 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
4551 if (test_and_clear_bit(RTL_FLAG_TASK_TX_TIMEOUT, tp->wk.flags)) {
4552 /* if chip isn't accessible, reset bus to revive it */
4553 if (RTL_R32(tp, TxConfig) == ~0) {
4554 ret = pci_reset_bus(tp->pci_dev);
4556 netdev_err(tp->dev, "Can't reset secondary PCI bus, detach NIC\n");
4557 netif_device_detach(tp->dev);
4562 /* ASPM compatibility issues are a typical reason for tx timeouts */
4563 ret = pci_disable_link_state(tp->pci_dev, PCIE_LINK_STATE_L1 |
4564 PCIE_LINK_STATE_L0S);
4566 netdev_warn_once(tp->dev, "ASPM disabled on Tx timeout\n");
4570 if (test_and_clear_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags)) {
4573 netif_wake_queue(tp->dev);
4579 static int rtl8169_poll(struct napi_struct *napi, int budget)
4581 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
4582 struct net_device *dev = tp->dev;
4585 rtl_tx(dev, tp, budget);
4587 work_done = rtl_rx(dev, tp, budget);
4589 if (work_done < budget && napi_complete_done(napi, work_done))
4595 static void r8169_phylink_handler(struct net_device *ndev)
4597 struct rtl8169_private *tp = netdev_priv(ndev);
4598 struct device *d = tp_to_dev(tp);
4600 if (netif_carrier_ok(ndev)) {
4601 rtl_link_chg_patch(tp);
4602 pm_request_resume(d);
4603 netif_wake_queue(tp->dev);
4605 /* In few cases rx is broken after link-down otherwise */
4606 if (rtl_is_8125(tp))
4611 phy_print_status(tp->phydev);
4614 static int r8169_phy_connect(struct rtl8169_private *tp)
4616 struct phy_device *phydev = tp->phydev;
4617 phy_interface_t phy_mode;
4620 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
4621 PHY_INTERFACE_MODE_MII;
4623 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
4628 if (!tp->supports_gmii)
4629 phy_set_max_speed(phydev, SPEED_100);
4631 phy_attached_info(phydev);
4636 static void rtl8169_down(struct rtl8169_private *tp)
4638 /* Clear all task flags */
4639 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
4641 phy_stop(tp->phydev);
4643 rtl8169_update_counters(tp);
4645 pci_clear_master(tp->pci_dev);
4648 rtl8169_cleanup(tp);
4649 rtl_disable_exit_l1(tp);
4650 rtl_prepare_power_down(tp);
4653 static void rtl8169_up(struct rtl8169_private *tp)
4655 pci_set_master(tp->pci_dev);
4656 phy_init_hw(tp->phydev);
4657 phy_resume(tp->phydev);
4658 rtl8169_init_phy(tp);
4659 napi_enable(&tp->napi);
4660 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
4663 phy_start(tp->phydev);
4666 static int rtl8169_close(struct net_device *dev)
4668 struct rtl8169_private *tp = netdev_priv(dev);
4669 struct pci_dev *pdev = tp->pci_dev;
4671 pm_runtime_get_sync(&pdev->dev);
4673 netif_stop_queue(dev);
4675 rtl8169_rx_clear(tp);
4677 cancel_work_sync(&tp->wk.work);
4679 free_irq(tp->irq, tp);
4681 phy_disconnect(tp->phydev);
4683 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4685 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4687 tp->TxDescArray = NULL;
4688 tp->RxDescArray = NULL;
4690 pm_runtime_put_sync(&pdev->dev);
4695 #ifdef CONFIG_NET_POLL_CONTROLLER
4696 static void rtl8169_netpoll(struct net_device *dev)
4698 struct rtl8169_private *tp = netdev_priv(dev);
4700 rtl8169_interrupt(tp->irq, tp);
4704 static int rtl_open(struct net_device *dev)
4706 struct rtl8169_private *tp = netdev_priv(dev);
4707 struct pci_dev *pdev = tp->pci_dev;
4708 unsigned long irqflags;
4709 int retval = -ENOMEM;
4711 pm_runtime_get_sync(&pdev->dev);
4714 * Rx and Tx descriptors needs 256 bytes alignment.
4715 * dma_alloc_coherent provides more.
4717 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
4718 &tp->TxPhyAddr, GFP_KERNEL);
4719 if (!tp->TxDescArray)
4722 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
4723 &tp->RxPhyAddr, GFP_KERNEL);
4724 if (!tp->RxDescArray)
4727 retval = rtl8169_init_ring(tp);
4731 rtl_request_firmware(tp);
4733 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_NO_THREAD : IRQF_SHARED;
4734 retval = request_irq(tp->irq, rtl8169_interrupt, irqflags, dev->name, tp);
4736 goto err_release_fw_2;
4738 retval = r8169_phy_connect(tp);
4743 rtl8169_init_counter_offsets(tp);
4744 netif_start_queue(dev);
4746 pm_runtime_put_sync(&pdev->dev);
4751 free_irq(tp->irq, tp);
4753 rtl_release_firmware(tp);
4754 rtl8169_rx_clear(tp);
4756 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4758 tp->RxDescArray = NULL;
4760 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4762 tp->TxDescArray = NULL;
4767 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
4769 struct rtl8169_private *tp = netdev_priv(dev);
4770 struct pci_dev *pdev = tp->pci_dev;
4771 struct rtl8169_counters *counters = tp->counters;
4773 pm_runtime_get_noresume(&pdev->dev);
4775 netdev_stats_to_stats64(stats, &dev->stats);
4776 dev_fetch_sw_netstats(stats, dev->tstats);
4779 * Fetch additional counter values missing in stats collected by driver
4780 * from tally counters.
4782 if (pm_runtime_active(&pdev->dev))
4783 rtl8169_update_counters(tp);
4786 * Subtract values fetched during initalization.
4787 * See rtl8169_init_counter_offsets for a description why we do that.
4789 stats->tx_errors = le64_to_cpu(counters->tx_errors) -
4790 le64_to_cpu(tp->tc_offset.tx_errors);
4791 stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
4792 le32_to_cpu(tp->tc_offset.tx_multi_collision);
4793 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
4794 le16_to_cpu(tp->tc_offset.tx_aborted);
4795 stats->rx_missed_errors = le16_to_cpu(counters->rx_missed) -
4796 le16_to_cpu(tp->tc_offset.rx_missed);
4798 pm_runtime_put_noidle(&pdev->dev);
4801 static void rtl8169_net_suspend(struct rtl8169_private *tp)
4803 netif_device_detach(tp->dev);
4805 if (netif_running(tp->dev))
4809 static int rtl8169_runtime_resume(struct device *dev)
4811 struct rtl8169_private *tp = dev_get_drvdata(dev);
4813 rtl_rar_set(tp, tp->dev->dev_addr);
4814 __rtl8169_set_wol(tp, tp->saved_wolopts);
4816 if (tp->TxDescArray)
4819 netif_device_attach(tp->dev);
4824 static int rtl8169_suspend(struct device *device)
4826 struct rtl8169_private *tp = dev_get_drvdata(device);
4829 rtl8169_net_suspend(tp);
4830 if (!device_may_wakeup(tp_to_dev(tp)))
4831 clk_disable_unprepare(tp->clk);
4837 static int rtl8169_resume(struct device *device)
4839 struct rtl8169_private *tp = dev_get_drvdata(device);
4841 if (!device_may_wakeup(tp_to_dev(tp)))
4842 clk_prepare_enable(tp->clk);
4844 /* Reportedly at least Asus X453MA truncates packets otherwise */
4845 if (tp->mac_version == RTL_GIGA_MAC_VER_37)
4848 return rtl8169_runtime_resume(device);
4851 static int rtl8169_runtime_suspend(struct device *device)
4853 struct rtl8169_private *tp = dev_get_drvdata(device);
4855 if (!tp->TxDescArray) {
4856 netif_device_detach(tp->dev);
4861 __rtl8169_set_wol(tp, WAKE_PHY);
4862 rtl8169_net_suspend(tp);
4868 static int rtl8169_runtime_idle(struct device *device)
4870 struct rtl8169_private *tp = dev_get_drvdata(device);
4872 if (tp->dash_type != RTL_DASH_NONE)
4875 if (!netif_running(tp->dev) || !netif_carrier_ok(tp->dev))
4876 pm_schedule_suspend(device, 10000);
4881 static const struct dev_pm_ops rtl8169_pm_ops = {
4882 SYSTEM_SLEEP_PM_OPS(rtl8169_suspend, rtl8169_resume)
4883 RUNTIME_PM_OPS(rtl8169_runtime_suspend, rtl8169_runtime_resume,
4884 rtl8169_runtime_idle)
4887 static void rtl_shutdown(struct pci_dev *pdev)
4889 struct rtl8169_private *tp = pci_get_drvdata(pdev);
4892 rtl8169_net_suspend(tp);
4895 /* Restore original MAC address */
4896 rtl_rar_set(tp, tp->dev->perm_addr);
4898 if (system_state == SYSTEM_POWER_OFF &&
4899 tp->dash_type == RTL_DASH_NONE) {
4900 pci_wake_from_d3(pdev, tp->saved_wolopts);
4901 pci_set_power_state(pdev, PCI_D3hot);
4905 static void rtl_remove_one(struct pci_dev *pdev)
4907 struct rtl8169_private *tp = pci_get_drvdata(pdev);
4909 if (pci_dev_run_wake(pdev))
4910 pm_runtime_get_noresume(&pdev->dev);
4912 unregister_netdev(tp->dev);
4914 if (tp->dash_type != RTL_DASH_NONE)
4915 rtl8168_driver_stop(tp);
4917 rtl_release_firmware(tp);
4919 /* restore original MAC address */
4920 rtl_rar_set(tp, tp->dev->perm_addr);
4923 static const struct net_device_ops rtl_netdev_ops = {
4924 .ndo_open = rtl_open,
4925 .ndo_stop = rtl8169_close,
4926 .ndo_get_stats64 = rtl8169_get_stats64,
4927 .ndo_start_xmit = rtl8169_start_xmit,
4928 .ndo_features_check = rtl8169_features_check,
4929 .ndo_tx_timeout = rtl8169_tx_timeout,
4930 .ndo_validate_addr = eth_validate_addr,
4931 .ndo_change_mtu = rtl8169_change_mtu,
4932 .ndo_fix_features = rtl8169_fix_features,
4933 .ndo_set_features = rtl8169_set_features,
4934 .ndo_set_mac_address = rtl_set_mac_address,
4935 .ndo_eth_ioctl = phy_do_ioctl_running,
4936 .ndo_set_rx_mode = rtl_set_rx_mode,
4937 #ifdef CONFIG_NET_POLL_CONTROLLER
4938 .ndo_poll_controller = rtl8169_netpoll,
4943 static void rtl_set_irq_mask(struct rtl8169_private *tp)
4945 tp->irq_mask = RxOK | RxErr | TxOK | TxErr | LinkChg;
4947 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
4948 tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver;
4949 else if (tp->mac_version == RTL_GIGA_MAC_VER_11)
4950 /* special workaround needed */
4951 tp->irq_mask |= RxFIFOOver;
4953 tp->irq_mask |= RxOverflow;
4956 static int rtl_alloc_irq(struct rtl8169_private *tp)
4960 switch (tp->mac_version) {
4961 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
4962 rtl_unlock_config_regs(tp);
4963 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
4964 rtl_lock_config_regs(tp);
4966 case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_17:
4967 flags = PCI_IRQ_LEGACY;
4970 flags = PCI_IRQ_ALL_TYPES;
4974 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
4977 static void rtl_read_mac_address(struct rtl8169_private *tp,
4978 u8 mac_addr[ETH_ALEN])
4980 /* Get MAC address */
4981 if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) {
4984 value = rtl_eri_read(tp, 0xe0);
4985 put_unaligned_le32(value, mac_addr);
4986 value = rtl_eri_read(tp, 0xe4);
4987 put_unaligned_le16(value, mac_addr + 4);
4988 } else if (rtl_is_8125(tp)) {
4989 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP);
4993 DECLARE_RTL_COND(rtl_link_list_ready_cond)
4995 return RTL_R8(tp, MCU) & LINK_LIST_RDY;
4998 static void r8168g_wait_ll_share_fifo_ready(struct rtl8169_private *tp)
5000 rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42);
5003 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
5005 struct rtl8169_private *tp = mii_bus->priv;
5010 return rtl_readphy(tp, phyreg);
5013 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
5014 int phyreg, u16 val)
5016 struct rtl8169_private *tp = mii_bus->priv;
5021 rtl_writephy(tp, phyreg, val);
5026 static int r8169_mdio_register(struct rtl8169_private *tp)
5028 struct pci_dev *pdev = tp->pci_dev;
5029 struct mii_bus *new_bus;
5032 new_bus = devm_mdiobus_alloc(&pdev->dev);
5036 new_bus->name = "r8169";
5038 new_bus->parent = &pdev->dev;
5039 new_bus->irq[0] = PHY_MAC_INTERRUPT;
5040 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x-%x",
5041 pci_domain_nr(pdev->bus), pci_dev_id(pdev));
5043 new_bus->read = r8169_mdio_read_reg;
5044 new_bus->write = r8169_mdio_write_reg;
5046 ret = devm_mdiobus_register(&pdev->dev, new_bus);
5050 tp->phydev = mdiobus_get_phy(new_bus, 0);
5053 } else if (!tp->phydev->drv) {
5054 /* Most chip versions fail with the genphy driver.
5055 * Therefore ensure that the dedicated PHY driver is loaded.
5057 dev_err(&pdev->dev, "no dedicated PHY driver found for PHY ID 0x%08x, maybe realtek.ko needs to be added to initramfs?\n",
5058 tp->phydev->phy_id);
5062 tp->phydev->mac_managed_pm = true;
5064 phy_support_asym_pause(tp->phydev);
5066 /* PHY will be woken up in rtl_open() */
5067 phy_suspend(tp->phydev);
5072 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
5074 rtl_enable_rxdvgate(tp);
5076 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
5078 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5080 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
5081 r8168g_wait_ll_share_fifo_ready(tp);
5083 r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15));
5084 r8168g_wait_ll_share_fifo_ready(tp);
5087 static void rtl_hw_init_8125(struct rtl8169_private *tp)
5089 rtl_enable_rxdvgate(tp);
5091 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
5093 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5095 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
5096 r8168g_wait_ll_share_fifo_ready(tp);
5098 r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0);
5099 r8168_mac_ocp_write(tp, 0xc0a6, 0x0150);
5100 r8168_mac_ocp_write(tp, 0xc01e, 0x5555);
5101 r8168g_wait_ll_share_fifo_ready(tp);
5104 static void rtl_hw_initialize(struct rtl8169_private *tp)
5106 switch (tp->mac_version) {
5107 case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_53:
5108 rtl8168ep_stop_cmac(tp);
5110 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
5111 rtl_hw_init_8168g(tp);
5113 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63:
5114 rtl_hw_init_8125(tp);
5121 static int rtl_jumbo_max(struct rtl8169_private *tp)
5123 /* Non-GBit versions don't support jumbo frames */
5124 if (!tp->supports_gmii)
5127 switch (tp->mac_version) {
5129 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
5132 case RTL_GIGA_MAC_VER_11:
5133 case RTL_GIGA_MAC_VER_17:
5136 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
5143 static void rtl_init_mac_address(struct rtl8169_private *tp)
5145 u8 mac_addr[ETH_ALEN] __aligned(2) = {};
5146 struct net_device *dev = tp->dev;
5149 rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr);
5153 rtl_read_mac_address(tp, mac_addr);
5154 if (is_valid_ether_addr(mac_addr))
5157 rtl_read_mac_from_reg(tp, mac_addr, MAC0);
5158 if (is_valid_ether_addr(mac_addr))
5161 eth_random_addr(mac_addr);
5162 dev->addr_assign_type = NET_ADDR_RANDOM;
5163 dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n");
5165 eth_hw_addr_set(dev, mac_addr);
5166 rtl_rar_set(tp, mac_addr);
5169 /* register is set if system vendor successfully tested ASPM 1.2 */
5170 static bool rtl_aspm_is_safe(struct rtl8169_private *tp)
5172 if (tp->mac_version >= RTL_GIGA_MAC_VER_61 &&
5173 r8168_mac_ocp_read(tp, 0xc0b2) & 0xf)
5179 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
5181 struct rtl8169_private *tp;
5182 int jumbo_max, region, rc;
5183 enum mac_version chipset;
5184 struct net_device *dev;
5188 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
5192 SET_NETDEV_DEV(dev, &pdev->dev);
5193 dev->netdev_ops = &rtl_netdev_ops;
5194 tp = netdev_priv(dev);
5197 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1;
5199 tp->ocp_base = OCP_STD_PHY_BASE;
5201 raw_spin_lock_init(&tp->cfg9346_usage_lock);
5202 raw_spin_lock_init(&tp->config25_lock);
5203 raw_spin_lock_init(&tp->mac_ocp_lock);
5205 dev->tstats = devm_netdev_alloc_pcpu_stats(&pdev->dev,
5206 struct pcpu_sw_netstats);
5210 /* Get the *optional* external "ether_clk" used on some boards */
5211 tp->clk = devm_clk_get_optional_enabled(&pdev->dev, "ether_clk");
5212 if (IS_ERR(tp->clk))
5213 return dev_err_probe(&pdev->dev, PTR_ERR(tp->clk), "failed to get ether_clk\n");
5215 /* enable device (incl. PCI PM wakeup and hotplug setup) */
5216 rc = pcim_enable_device(pdev);
5218 return dev_err_probe(&pdev->dev, rc, "enable failure\n");
5220 if (pcim_set_mwi(pdev) < 0)
5221 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
5223 /* use first MMIO region */
5224 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
5226 return dev_err_probe(&pdev->dev, -ENODEV, "no MMIO resource found\n");
5228 rc = pcim_iomap_regions(pdev, BIT(region), KBUILD_MODNAME);
5230 return dev_err_probe(&pdev->dev, rc, "cannot remap MMIO, aborting\n");
5232 tp->mmio_addr = pcim_iomap_table(pdev)[region];
5234 txconfig = RTL_R32(tp, TxConfig);
5235 if (txconfig == ~0U)
5236 return dev_err_probe(&pdev->dev, -EIO, "PCI read failed\n");
5238 xid = (txconfig >> 20) & 0xfcf;
5240 /* Identify chip attached to board */
5241 chipset = rtl8169_get_mac_version(xid, tp->supports_gmii);
5242 if (chipset == RTL_GIGA_MAC_NONE)
5243 return dev_err_probe(&pdev->dev, -ENODEV,
5244 "unknown chip XID %03x, contact r8169 maintainers (see MAINTAINERS file)\n",
5246 tp->mac_version = chipset;
5248 /* Disable ASPM L1 as that cause random device stop working
5249 * problems as well as full system hangs for some PCIe devices users.
5251 if (rtl_aspm_is_safe(tp))
5254 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L1);
5255 tp->aspm_manageable = !rc;
5257 tp->dash_type = rtl_check_dash(tp);
5259 tp->cp_cmd = RTL_R16(tp, CPlusCmd) & CPCMD_MASK;
5261 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 &&
5262 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)))
5263 dev->features |= NETIF_F_HIGHDMA;
5267 rtl8169_irq_mask_and_ack(tp);
5269 rtl_hw_initialize(tp);
5273 rc = rtl_alloc_irq(tp);
5275 return dev_err_probe(&pdev->dev, rc, "Can't allocate interrupt\n");
5277 tp->irq = pci_irq_vector(pdev, 0);
5279 INIT_WORK(&tp->wk.work, rtl_task);
5281 rtl_init_mac_address(tp);
5283 dev->ethtool_ops = &rtl8169_ethtool_ops;
5285 netif_napi_add(dev, &tp->napi, rtl8169_poll);
5287 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
5288 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
5289 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO;
5290 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
5293 * Pretend we are using VLANs; This bypasses a nasty bug where
5294 * Interrupts stop flowing on high load on 8110SCd controllers.
5296 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
5297 /* Disallow toggling */
5298 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
5300 if (rtl_chip_supports_csum_v2(tp))
5301 dev->hw_features |= NETIF_F_IPV6_CSUM;
5303 dev->features |= dev->hw_features;
5305 /* There has been a number of reports that using SG/TSO results in
5306 * tx timeouts. However for a lot of people SG/TSO works fine.
5307 * Therefore disable both features by default, but allow users to
5308 * enable them. Use at own risk!
5310 if (rtl_chip_supports_csum_v2(tp)) {
5311 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6;
5312 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V2);
5313 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V2);
5315 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO;
5316 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V1);
5317 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V1);
5320 dev->hw_features |= NETIF_F_RXALL;
5321 dev->hw_features |= NETIF_F_RXFCS;
5323 netdev_sw_irq_coalesce_default_on(dev);
5325 /* configure chip for default features */
5326 rtl8169_set_features(dev, dev->features);
5328 if (tp->dash_type == RTL_DASH_NONE) {
5329 rtl_set_d3_pll_down(tp, true);
5331 rtl_set_d3_pll_down(tp, false);
5332 dev->wol_enabled = 1;
5335 jumbo_max = rtl_jumbo_max(tp);
5337 dev->max_mtu = jumbo_max;
5339 rtl_set_irq_mask(tp);
5341 tp->fw_name = rtl_chip_infos[chipset].fw_name;
5343 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
5344 &tp->counters_phys_addr,
5349 pci_set_drvdata(pdev, tp);
5351 rc = r8169_mdio_register(tp);
5355 rc = register_netdev(dev);
5359 netdev_info(dev, "%s, %pM, XID %03x, IRQ %d\n",
5360 rtl_chip_infos[chipset].name, dev->dev_addr, xid, tp->irq);
5363 netdev_info(dev, "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
5364 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?
5367 if (tp->dash_type != RTL_DASH_NONE) {
5368 netdev_info(dev, "DASH enabled\n");
5369 rtl8168_driver_start(tp);
5372 if (pci_dev_run_wake(pdev))
5373 pm_runtime_put_sync(&pdev->dev);
5378 static struct pci_driver rtl8169_pci_driver = {
5379 .name = KBUILD_MODNAME,
5380 .id_table = rtl8169_pci_tbl,
5381 .probe = rtl_init_one,
5382 .remove = rtl_remove_one,
5383 .shutdown = rtl_shutdown,
5384 .driver.pm = pm_ptr(&rtl8169_pm_ops),
5387 module_pci_driver(rtl8169_pci_driver);