2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
8 * See MAINTAINERS file for support contact information.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/clk.h>
17 #include <linux/delay.h>
18 #include <linux/ethtool.h>
19 #include <linux/phy.h>
20 #include <linux/if_vlan.h>
21 #include <linux/crc32.h>
25 #include <linux/tcp.h>
26 #include <linux/interrupt.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/firmware.h>
30 #include <linux/prefetch.h>
31 #include <linux/ipv6.h>
32 #include <net/ip6_checksum.h>
34 #define MODULENAME "r8169"
36 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
37 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
38 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
39 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
40 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
41 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
42 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
43 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
44 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
45 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
46 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
47 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
48 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
49 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
50 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
51 #define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw"
52 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw"
53 #define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw"
54 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw"
56 #define R8169_MSG_DEFAULT \
57 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
59 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
60 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
61 static const int multicast_filter_limit = 32;
63 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
64 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
66 #define R8169_REGS_SIZE 256
67 #define R8169_RX_BUF_SIZE (SZ_16K - 1)
68 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
69 #define NUM_RX_DESC 256U /* Number of Rx descriptor registers */
70 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
71 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
73 /* write/read MMIO register */
74 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg))
75 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
76 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
77 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg))
78 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg))
79 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg))
82 RTL_GIGA_MAC_VER_01 = 0,
133 RTL_GIGA_MAC_NONE = 0xff,
136 #define JUMBO_1K ETH_DATA_LEN
137 #define JUMBO_4K (4*1024 - ETH_HLEN - 2)
138 #define JUMBO_6K (6*1024 - ETH_HLEN - 2)
139 #define JUMBO_7K (7*1024 - ETH_HLEN - 2)
140 #define JUMBO_9K (9*1024 - ETH_HLEN - 2)
142 static const struct {
145 } rtl_chip_infos[] = {
147 [RTL_GIGA_MAC_VER_01] = {"RTL8169" },
148 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" },
149 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" },
150 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" },
151 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" },
152 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" },
154 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" },
155 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" },
156 [RTL_GIGA_MAC_VER_09] = {"RTL8102e" },
157 [RTL_GIGA_MAC_VER_10] = {"RTL8101e" },
158 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" },
159 [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b" },
160 [RTL_GIGA_MAC_VER_13] = {"RTL8101e" },
161 [RTL_GIGA_MAC_VER_14] = {"RTL8100e" },
162 [RTL_GIGA_MAC_VER_15] = {"RTL8100e" },
163 [RTL_GIGA_MAC_VER_16] = {"RTL8101e" },
164 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" },
165 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" },
166 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" },
167 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" },
168 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" },
169 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" },
170 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" },
171 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" },
172 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1},
173 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2},
174 [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp" },
175 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" },
176 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1},
177 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1},
178 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" },
179 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1},
180 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2},
181 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3},
182 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1},
183 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2},
184 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 },
185 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 },
186 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1},
187 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2},
188 [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g" },
189 [RTL_GIGA_MAC_VER_42] = {"RTL8168g/8111g", FIRMWARE_8168G_3},
190 [RTL_GIGA_MAC_VER_43] = {"RTL8106e", FIRMWARE_8106E_2},
191 [RTL_GIGA_MAC_VER_44] = {"RTL8411", FIRMWARE_8411_2 },
192 [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h", FIRMWARE_8168H_1},
193 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2},
194 [RTL_GIGA_MAC_VER_47] = {"RTL8107e", FIRMWARE_8107E_1},
195 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2},
196 [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep" },
197 [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep" },
198 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" },
207 static const struct pci_device_id rtl8169_pci_tbl[] = {
208 { PCI_VDEVICE(REALTEK, 0x2502), RTL_CFG_1 },
209 { PCI_VDEVICE(REALTEK, 0x2600), RTL_CFG_1 },
210 { PCI_VDEVICE(REALTEK, 0x8129), RTL_CFG_0 },
211 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_2 },
212 { PCI_VDEVICE(REALTEK, 0x8161), RTL_CFG_1 },
213 { PCI_VDEVICE(REALTEK, 0x8167), RTL_CFG_0 },
214 { PCI_VDEVICE(REALTEK, 0x8168), RTL_CFG_1 },
215 { PCI_VDEVICE(NCUBE, 0x8168), RTL_CFG_1 },
216 { PCI_VDEVICE(REALTEK, 0x8169), RTL_CFG_0 },
217 { PCI_VENDOR_ID_DLINK, 0x4300,
218 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 },
219 { PCI_VDEVICE(DLINK, 0x4300), RTL_CFG_0 },
220 { PCI_VDEVICE(DLINK, 0x4302), RTL_CFG_0 },
221 { PCI_VDEVICE(AT, 0xc107), RTL_CFG_0 },
222 { PCI_VDEVICE(USR, 0x0116), RTL_CFG_0 },
223 { PCI_VENDOR_ID_LINKSYS, 0x1032,
224 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
226 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
230 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
232 static int use_dac = -1;
238 MAC0 = 0, /* Ethernet hardware address. */
240 MAR0 = 8, /* Multicast filter. */
241 CounterAddrLow = 0x10,
242 CounterAddrHigh = 0x14,
243 TxDescStartAddrLow = 0x20,
244 TxDescStartAddrHigh = 0x24,
245 TxHDescStartAddrLow = 0x28,
246 TxHDescStartAddrHigh = 0x2c,
255 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
256 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
259 #define RX128_INT_EN (1 << 15) /* 8111c and later */
260 #define RX_MULTI_EN (1 << 14) /* 8111c only */
261 #define RXCFG_FIFO_SHIFT 13
262 /* No threshold before first PCI xfer */
263 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
264 #define RX_EARLY_OFF (1 << 11)
265 #define RXCFG_DMA_SHIFT 8
266 /* Unlimited maximum PCI burst. */
267 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
274 #define PME_SIGNAL (1 << 5) /* 8168c and later */
286 #define RTL_COALESCE_MASK 0x0f
287 #define RTL_COALESCE_SHIFT 4
288 #define RTL_COALESCE_T_MAX (RTL_COALESCE_MASK)
289 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_MASK << 2)
291 RxDescAddrLow = 0xe4,
292 RxDescAddrHigh = 0xe8,
293 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
295 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
297 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
299 #define TxPacketMax (8064 >> 7)
300 #define EarlySize 0x27
303 FuncEventMask = 0xf4,
304 FuncPresetState = 0xf8,
309 FuncForceEvent = 0xfc,
312 enum rtl8168_8101_registers {
315 #define CSIAR_FLAG 0x80000000
316 #define CSIAR_WRITE_CMD 0x80000000
317 #define CSIAR_BYTE_ENABLE 0x0000f000
318 #define CSIAR_ADDR_MASK 0x00000fff
321 #define EPHYAR_FLAG 0x80000000
322 #define EPHYAR_WRITE_CMD 0x80000000
323 #define EPHYAR_REG_MASK 0x1f
324 #define EPHYAR_REG_SHIFT 16
325 #define EPHYAR_DATA_MASK 0xffff
327 #define PFM_EN (1 << 6)
328 #define TX_10M_PS_EN (1 << 7)
330 #define FIX_NAK_1 (1 << 4)
331 #define FIX_NAK_2 (1 << 3)
334 #define NOW_IS_OOB (1 << 7)
335 #define TX_EMPTY (1 << 5)
336 #define RX_EMPTY (1 << 4)
337 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
338 #define EN_NDP (1 << 3)
339 #define EN_OOB_RESET (1 << 2)
340 #define LINK_LIST_RDY (1 << 1)
342 #define EFUSEAR_FLAG 0x80000000
343 #define EFUSEAR_WRITE_CMD 0x80000000
344 #define EFUSEAR_READ_CMD 0x00000000
345 #define EFUSEAR_REG_MASK 0x03ff
346 #define EFUSEAR_REG_SHIFT 8
347 #define EFUSEAR_DATA_MASK 0xff
349 #define PFM_D3COLD_EN (1 << 6)
352 enum rtl8168_registers {
357 #define ERIAR_FLAG 0x80000000
358 #define ERIAR_WRITE_CMD 0x80000000
359 #define ERIAR_READ_CMD 0x00000000
360 #define ERIAR_ADDR_BYTE_ALIGN 4
361 #define ERIAR_TYPE_SHIFT 16
362 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
363 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
364 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
365 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT)
366 #define ERIAR_MASK_SHIFT 12
367 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
368 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
369 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
370 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
371 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
372 EPHY_RXER_NUM = 0x7c,
373 OCPDR = 0xb0, /* OCP GPHY access */
374 #define OCPDR_WRITE_CMD 0x80000000
375 #define OCPDR_READ_CMD 0x00000000
376 #define OCPDR_REG_MASK 0x7f
377 #define OCPDR_GPHY_REG_SHIFT 16
378 #define OCPDR_DATA_MASK 0xffff
380 #define OCPAR_FLAG 0x80000000
381 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
382 #define OCPAR_GPHY_READ_CMD 0x0000f060
384 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
385 MISC = 0xf0, /* 8168e only. */
386 #define TXPLA_RST (1 << 29)
387 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
388 #define PWM_EN (1 << 22)
389 #define RXDV_GATED_EN (1 << 19)
390 #define EARLY_TALLY_EN (1 << 16)
393 enum rtl_register_content {
394 /* InterruptStatusBits */
398 TxDescUnavail = 0x0080,
422 /* TXPoll register p.5 */
423 HPQ = 0x80, /* Poll cmd on the high prio queue */
424 NPQ = 0x40, /* Poll cmd on the low prio queue */
425 FSWInt = 0x01, /* Forced software interrupt */
429 Cfg9346_Unlock = 0xc0,
434 AcceptBroadcast = 0x08,
435 AcceptMulticast = 0x04,
437 AcceptAllPhys = 0x01,
438 #define RX_CONFIG_ACCEPT_MASK 0x3f
441 TxInterFrameGapShift = 24,
442 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
444 /* Config1 register p.24 */
447 Speed_down = (1 << 4),
451 PMEnable = (1 << 0), /* Power Management Enable */
453 /* Config2 register p. 25 */
454 ClkReqEn = (1 << 7), /* Clock Request Enable */
455 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
456 PCI_Clock_66MHz = 0x01,
457 PCI_Clock_33MHz = 0x00,
459 /* Config3 register p.25 */
460 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
461 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
462 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
463 Rdy_to_L23 = (1 << 1), /* L23 Enable */
464 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
466 /* Config4 register */
467 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
469 /* Config5 register p.27 */
470 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
471 MWF = (1 << 5), /* Accept Multicast wakeup frame */
472 UWF = (1 << 4), /* Accept Unicast wakeup frame */
474 LanWake = (1 << 1), /* LanWake enable/disable */
475 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
476 ASPM_en = (1 << 0), /* ASPM enable */
479 EnableBist = (1 << 15), // 8168 8101
480 Mac_dbgo_oe = (1 << 14), // 8168 8101
481 Normal_mode = (1 << 13), // unused
482 Force_half_dup = (1 << 12), // 8168 8101
483 Force_rxflow_en = (1 << 11), // 8168 8101
484 Force_txflow_en = (1 << 10), // 8168 8101
485 Cxpl_dbg_sel = (1 << 9), // 8168 8101
486 ASF = (1 << 8), // 8168 8101
487 PktCntrDisable = (1 << 7), // 8168 8101
488 Mac_dbgo_sel = 0x001c, // 8168
493 #define INTT_MASK GENMASK(1, 0)
494 INTT_0 = 0x0000, // 8168
495 INTT_1 = 0x0001, // 8168
496 INTT_2 = 0x0002, // 8168
497 INTT_3 = 0x0003, // 8168
499 /* rtl8169_PHYstatus */
510 TBILinkOK = 0x02000000,
512 /* ResetCounterCommand */
515 /* DumpCounterCommand */
518 /* magic enable v2 */
519 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */
523 /* First doubleword. */
524 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
525 RingEnd = (1 << 30), /* End of descriptor ring */
526 FirstFrag = (1 << 29), /* First segment of a packet */
527 LastFrag = (1 << 28), /* Final segment of a packet */
531 enum rtl_tx_desc_bit {
532 /* First doubleword. */
533 TD_LSO = (1 << 27), /* Large Send Offload */
534 #define TD_MSS_MAX 0x07ffu /* MSS value */
536 /* Second doubleword. */
537 TxVlanTag = (1 << 17), /* Add VLAN tag */
540 /* 8169, 8168b and 810x except 8102e. */
541 enum rtl_tx_desc_bit_0 {
542 /* First doubleword. */
543 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
544 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
545 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
546 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
549 /* 8102e, 8168c and beyond. */
550 enum rtl_tx_desc_bit_1 {
551 /* First doubleword. */
552 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */
553 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */
554 #define GTTCPHO_SHIFT 18
555 #define GTTCPHO_MAX 0x7fU
557 /* Second doubleword. */
558 #define TCPHO_SHIFT 18
559 #define TCPHO_MAX 0x3ffU
560 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
561 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */
562 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */
563 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
564 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
567 enum rtl_rx_desc_bit {
569 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
570 PID0 = (1 << 17), /* Protocol ID bit 0/2 */
572 #define RxProtoUDP (PID1)
573 #define RxProtoTCP (PID0)
574 #define RxProtoIP (PID1 | PID0)
575 #define RxProtoMask RxProtoIP
577 IPFail = (1 << 16), /* IP checksum failed */
578 UDPFail = (1 << 15), /* UDP/IP checksum failed */
579 TCPFail = (1 << 14), /* TCP/IP checksum failed */
580 RxVlanTag = (1 << 16), /* VLAN tag available */
583 #define RsvdMask 0x3fffc000
584 #define CPCMD_QUIRK_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
603 struct rtl8169_counters {
610 __le32 tx_one_collision;
611 __le32 tx_multi_collision;
619 struct rtl8169_tc_offsets {
622 __le32 tx_multi_collision;
627 RTL_FLAG_TASK_ENABLED = 0,
628 RTL_FLAG_TASK_RESET_PENDING,
632 struct rtl8169_stats {
635 struct u64_stats_sync syncp;
638 struct rtl8169_private {
639 void __iomem *mmio_addr; /* memory map physical address */
640 struct pci_dev *pci_dev;
641 struct net_device *dev;
642 struct napi_struct napi;
645 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
646 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
648 struct rtl8169_stats rx_stats;
649 struct rtl8169_stats tx_stats;
650 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
651 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
652 dma_addr_t TxPhyAddr;
653 dma_addr_t RxPhyAddr;
654 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
655 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
659 const struct rtl_coalesce_info *coalesce_info;
663 void (*write)(struct rtl8169_private *, int, int);
664 int (*read)(struct rtl8169_private *, int);
668 void (*enable)(struct rtl8169_private *);
669 void (*disable)(struct rtl8169_private *);
672 void (*hw_start)(struct rtl8169_private *tp);
673 bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
676 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
678 struct work_struct work;
681 unsigned supports_gmii:1;
682 struct mii_bus *mii_bus;
683 dma_addr_t counters_phys_addr;
684 struct rtl8169_counters *counters;
685 struct rtl8169_tc_offsets tc_offset;
689 const struct firmware *fw;
691 #define RTL_VER_SIZE 32
693 char version[RTL_VER_SIZE];
695 struct rtl_fw_phy_action {
700 #define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
705 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
706 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
707 module_param(use_dac, int, 0);
708 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
709 module_param_named(debug, debug.msg_enable, int, 0);
710 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
711 MODULE_SOFTDEP("pre: realtek");
712 MODULE_LICENSE("GPL");
713 MODULE_FIRMWARE(FIRMWARE_8168D_1);
714 MODULE_FIRMWARE(FIRMWARE_8168D_2);
715 MODULE_FIRMWARE(FIRMWARE_8168E_1);
716 MODULE_FIRMWARE(FIRMWARE_8168E_2);
717 MODULE_FIRMWARE(FIRMWARE_8168E_3);
718 MODULE_FIRMWARE(FIRMWARE_8105E_1);
719 MODULE_FIRMWARE(FIRMWARE_8168F_1);
720 MODULE_FIRMWARE(FIRMWARE_8168F_2);
721 MODULE_FIRMWARE(FIRMWARE_8402_1);
722 MODULE_FIRMWARE(FIRMWARE_8411_1);
723 MODULE_FIRMWARE(FIRMWARE_8411_2);
724 MODULE_FIRMWARE(FIRMWARE_8106E_1);
725 MODULE_FIRMWARE(FIRMWARE_8106E_2);
726 MODULE_FIRMWARE(FIRMWARE_8168G_2);
727 MODULE_FIRMWARE(FIRMWARE_8168G_3);
728 MODULE_FIRMWARE(FIRMWARE_8168H_1);
729 MODULE_FIRMWARE(FIRMWARE_8168H_2);
730 MODULE_FIRMWARE(FIRMWARE_8107E_1);
731 MODULE_FIRMWARE(FIRMWARE_8107E_2);
733 static inline struct device *tp_to_dev(struct rtl8169_private *tp)
735 return &tp->pci_dev->dev;
738 static void rtl_lock_work(struct rtl8169_private *tp)
740 mutex_lock(&tp->wk.mutex);
743 static void rtl_unlock_work(struct rtl8169_private *tp)
745 mutex_unlock(&tp->wk.mutex);
748 static void rtl_tx_performance_tweak(struct rtl8169_private *tp, u16 force)
750 pcie_capability_clear_and_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
751 PCI_EXP_DEVCTL_READRQ, force);
755 bool (*check)(struct rtl8169_private *);
759 static void rtl_udelay(unsigned int d)
764 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
765 void (*delay)(unsigned int), unsigned int d, int n,
770 for (i = 0; i < n; i++) {
772 if (c->check(tp) == high)
775 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
776 c->msg, !high, n, d);
780 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
781 const struct rtl_cond *c,
782 unsigned int d, int n)
784 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
787 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
788 const struct rtl_cond *c,
789 unsigned int d, int n)
791 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
794 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
795 const struct rtl_cond *c,
796 unsigned int d, int n)
798 return rtl_loop_wait(tp, c, msleep, d, n, true);
801 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
802 const struct rtl_cond *c,
803 unsigned int d, int n)
805 return rtl_loop_wait(tp, c, msleep, d, n, false);
808 #define DECLARE_RTL_COND(name) \
809 static bool name ## _check(struct rtl8169_private *); \
811 static const struct rtl_cond name = { \
812 .check = name ## _check, \
816 static bool name ## _check(struct rtl8169_private *tp)
818 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
820 if (reg & 0xffff0001) {
821 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
827 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
829 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
832 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
834 if (rtl_ocp_reg_failure(tp, reg))
837 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
839 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
842 static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
844 if (rtl_ocp_reg_failure(tp, reg))
847 RTL_W32(tp, GPHY_OCP, reg << 15);
849 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
850 (RTL_R32(tp, GPHY_OCP) & 0xffff) : ~0;
853 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
855 if (rtl_ocp_reg_failure(tp, reg))
858 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
861 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
863 if (rtl_ocp_reg_failure(tp, reg))
866 RTL_W32(tp, OCPDR, reg << 15);
868 return RTL_R32(tp, OCPDR);
871 #define OCP_STD_PHY_BASE 0xa400
873 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
876 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
880 if (tp->ocp_base != OCP_STD_PHY_BASE)
883 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
886 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
888 if (tp->ocp_base != OCP_STD_PHY_BASE)
891 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
894 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
897 tp->ocp_base = value << 4;
901 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
904 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
906 return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
909 DECLARE_RTL_COND(rtl_phyar_cond)
911 return RTL_R32(tp, PHYAR) & 0x80000000;
914 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
916 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
918 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
920 * According to hardware specs a 20us delay is required after write
921 * complete indication, but before sending next command.
926 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
930 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
932 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
933 RTL_R32(tp, PHYAR) & 0xffff : ~0;
936 * According to hardware specs a 20us delay is required after read
937 * complete indication, but before sending next command.
944 DECLARE_RTL_COND(rtl_ocpar_cond)
946 return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
949 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
951 RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
952 RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
953 RTL_W32(tp, EPHY_RXER_NUM, 0);
955 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
958 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
960 r8168dp_1_mdio_access(tp, reg,
961 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
964 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
966 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
969 RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
970 RTL_W32(tp, EPHY_RXER_NUM, 0);
972 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
973 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : ~0;
976 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
978 static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
980 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
983 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
985 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
988 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
990 r8168dp_2_mdio_start(tp);
992 r8169_mdio_write(tp, reg, value);
994 r8168dp_2_mdio_stop(tp);
997 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1001 r8168dp_2_mdio_start(tp);
1003 value = r8169_mdio_read(tp, reg);
1005 r8168dp_2_mdio_stop(tp);
1010 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1012 tp->mdio_ops.write(tp, location, val);
1015 static int rtl_readphy(struct rtl8169_private *tp, int location)
1017 return tp->mdio_ops.read(tp, location);
1020 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1022 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1025 static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1029 val = rtl_readphy(tp, reg_addr);
1030 rtl_writephy(tp, reg_addr, (val & ~m) | p);
1033 DECLARE_RTL_COND(rtl_ephyar_cond)
1035 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1038 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1040 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1041 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1043 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1048 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1050 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1052 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1053 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1056 DECLARE_RTL_COND(rtl_eriar_cond)
1058 return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
1061 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1064 BUG_ON((addr & 3) || (mask == 0));
1065 RTL_W32(tp, ERIDR, val);
1066 RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1068 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1071 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1073 RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1075 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1076 RTL_R32(tp, ERIDR) : ~0;
1079 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1084 val = rtl_eri_read(tp, addr, type);
1085 rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
1088 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1090 RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1091 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1092 RTL_R32(tp, OCPDR) : ~0;
1095 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1097 return rtl_eri_read(tp, reg, ERIAR_OOB);
1100 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1103 RTL_W32(tp, OCPDR, data);
1104 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1105 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1108 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1111 rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1115 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd)
1117 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd, ERIAR_EXGMAC);
1119 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001);
1122 #define OOB_CMD_RESET 0x00
1123 #define OOB_CMD_DRIVER_START 0x05
1124 #define OOB_CMD_DRIVER_STOP 0x06
1126 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1128 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1131 DECLARE_RTL_COND(rtl_dp_ocp_read_cond)
1135 reg = rtl8168_get_ocp_reg(tp);
1137 return r8168dp_ocp_read(tp, 0x0f, reg) & 0x00000800;
1140 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1142 return r8168ep_ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1145 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1147 return RTL_R8(tp, IBISR0) & 0x20;
1150 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1152 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1153 rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000);
1154 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1155 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1158 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1160 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START);
1161 rtl_msleep_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10, 10);
1164 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1166 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1167 r8168ep_ocp_write(tp, 0x01, 0x30,
1168 r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
1169 rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1172 static void rtl8168_driver_start(struct rtl8169_private *tp)
1174 switch (tp->mac_version) {
1175 case RTL_GIGA_MAC_VER_27:
1176 case RTL_GIGA_MAC_VER_28:
1177 case RTL_GIGA_MAC_VER_31:
1178 rtl8168dp_driver_start(tp);
1180 case RTL_GIGA_MAC_VER_49:
1181 case RTL_GIGA_MAC_VER_50:
1182 case RTL_GIGA_MAC_VER_51:
1183 rtl8168ep_driver_start(tp);
1191 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1193 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1194 rtl_msleep_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10, 10);
1197 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1199 rtl8168ep_stop_cmac(tp);
1200 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1201 r8168ep_ocp_write(tp, 0x01, 0x30,
1202 r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
1203 rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1206 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1208 switch (tp->mac_version) {
1209 case RTL_GIGA_MAC_VER_27:
1210 case RTL_GIGA_MAC_VER_28:
1211 case RTL_GIGA_MAC_VER_31:
1212 rtl8168dp_driver_stop(tp);
1214 case RTL_GIGA_MAC_VER_49:
1215 case RTL_GIGA_MAC_VER_50:
1216 case RTL_GIGA_MAC_VER_51:
1217 rtl8168ep_driver_stop(tp);
1225 static bool r8168dp_check_dash(struct rtl8169_private *tp)
1227 u16 reg = rtl8168_get_ocp_reg(tp);
1229 return !!(r8168dp_ocp_read(tp, 0x0f, reg) & 0x00008000);
1232 static bool r8168ep_check_dash(struct rtl8169_private *tp)
1234 return !!(r8168ep_ocp_read(tp, 0x0f, 0x128) & 0x00000001);
1237 static bool r8168_check_dash(struct rtl8169_private *tp)
1239 switch (tp->mac_version) {
1240 case RTL_GIGA_MAC_VER_27:
1241 case RTL_GIGA_MAC_VER_28:
1242 case RTL_GIGA_MAC_VER_31:
1243 return r8168dp_check_dash(tp);
1244 case RTL_GIGA_MAC_VER_49:
1245 case RTL_GIGA_MAC_VER_50:
1246 case RTL_GIGA_MAC_VER_51:
1247 return r8168ep_check_dash(tp);
1259 static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
1260 const struct exgmac_reg *r, int len)
1263 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1268 DECLARE_RTL_COND(rtl_efusear_cond)
1270 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1273 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1275 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1277 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1278 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1281 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1283 RTL_W16(tp, IntrStatus, bits);
1286 static void rtl_irq_disable(struct rtl8169_private *tp)
1288 RTL_W16(tp, IntrMask, 0);
1291 #define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1292 #define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1293 #define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1295 static void rtl_irq_enable(struct rtl8169_private *tp)
1297 RTL_W16(tp, IntrMask, tp->irq_mask);
1300 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1302 rtl_irq_disable(tp);
1303 rtl_ack_events(tp, 0xffff);
1305 RTL_R8(tp, ChipCmd);
1308 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1310 struct net_device *dev = tp->dev;
1311 struct phy_device *phydev = dev->phydev;
1313 if (!netif_running(dev))
1316 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1317 tp->mac_version == RTL_GIGA_MAC_VER_38) {
1318 if (phydev->speed == SPEED_1000) {
1319 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1321 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1323 } else if (phydev->speed == SPEED_100) {
1324 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1326 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1329 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1331 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1334 /* Reset packet filter */
1335 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1337 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1339 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1340 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1341 if (phydev->speed == SPEED_1000) {
1342 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1344 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1347 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1349 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1352 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1353 if (phydev->speed == SPEED_10) {
1354 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1356 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1359 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1365 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1367 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1372 options = RTL_R8(tp, Config1);
1373 if (!(options & PMEnable))
1376 options = RTL_R8(tp, Config3);
1377 if (options & LinkUp)
1378 wolopts |= WAKE_PHY;
1379 switch (tp->mac_version) {
1380 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
1381 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1382 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
1383 wolopts |= WAKE_MAGIC;
1386 if (options & MagicPacket)
1387 wolopts |= WAKE_MAGIC;
1391 options = RTL_R8(tp, Config5);
1393 wolopts |= WAKE_UCAST;
1395 wolopts |= WAKE_BCAST;
1397 wolopts |= WAKE_MCAST;
1402 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1404 struct rtl8169_private *tp = netdev_priv(dev);
1407 wol->supported = WAKE_ANY;
1408 wol->wolopts = tp->saved_wolopts;
1409 rtl_unlock_work(tp);
1412 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1414 unsigned int i, tmp;
1415 static const struct {
1420 { WAKE_PHY, Config3, LinkUp },
1421 { WAKE_UCAST, Config5, UWF },
1422 { WAKE_BCAST, Config5, BWF },
1423 { WAKE_MCAST, Config5, MWF },
1424 { WAKE_ANY, Config5, LanWake },
1425 { WAKE_MAGIC, Config3, MagicPacket }
1429 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
1431 switch (tp->mac_version) {
1432 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
1433 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1434 tmp = ARRAY_SIZE(cfg) - 1;
1435 if (wolopts & WAKE_MAGIC)
1451 tmp = ARRAY_SIZE(cfg);
1455 for (i = 0; i < tmp; i++) {
1456 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
1457 if (wolopts & cfg[i].opt)
1458 options |= cfg[i].mask;
1459 RTL_W8(tp, cfg[i].reg, options);
1462 switch (tp->mac_version) {
1463 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1464 options = RTL_R8(tp, Config1) & ~PMEnable;
1466 options |= PMEnable;
1467 RTL_W8(tp, Config1, options);
1470 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
1472 options |= PME_SIGNAL;
1473 RTL_W8(tp, Config2, options);
1477 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
1479 device_set_wakeup_enable(tp_to_dev(tp), wolopts);
1482 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1484 struct rtl8169_private *tp = netdev_priv(dev);
1485 struct device *d = tp_to_dev(tp);
1487 if (wol->wolopts & ~WAKE_ANY)
1490 pm_runtime_get_noresume(d);
1494 tp->saved_wolopts = wol->wolopts;
1496 if (pm_runtime_active(d))
1497 __rtl8169_set_wol(tp, tp->saved_wolopts);
1499 rtl_unlock_work(tp);
1501 pm_runtime_put_noidle(d);
1506 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1508 return rtl_chip_infos[tp->mac_version].fw_name;
1511 static void rtl8169_get_drvinfo(struct net_device *dev,
1512 struct ethtool_drvinfo *info)
1514 struct rtl8169_private *tp = netdev_priv(dev);
1515 struct rtl_fw *rtl_fw = tp->rtl_fw;
1517 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1518 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1519 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1520 if (!IS_ERR_OR_NULL(rtl_fw))
1521 strlcpy(info->fw_version, rtl_fw->version,
1522 sizeof(info->fw_version));
1525 static int rtl8169_get_regs_len(struct net_device *dev)
1527 return R8169_REGS_SIZE;
1530 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1531 netdev_features_t features)
1533 struct rtl8169_private *tp = netdev_priv(dev);
1535 if (dev->mtu > TD_MSS_MAX)
1536 features &= ~NETIF_F_ALL_TSO;
1538 if (dev->mtu > JUMBO_1K &&
1539 tp->mac_version > RTL_GIGA_MAC_VER_06)
1540 features &= ~NETIF_F_IP_CSUM;
1545 static int rtl8169_set_features(struct net_device *dev,
1546 netdev_features_t features)
1548 struct rtl8169_private *tp = netdev_priv(dev);
1553 rx_config = RTL_R32(tp, RxConfig);
1554 if (features & NETIF_F_RXALL)
1555 rx_config |= (AcceptErr | AcceptRunt);
1557 rx_config &= ~(AcceptErr | AcceptRunt);
1559 RTL_W32(tp, RxConfig, rx_config);
1561 if (features & NETIF_F_RXCSUM)
1562 tp->cp_cmd |= RxChkSum;
1564 tp->cp_cmd &= ~RxChkSum;
1566 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1567 tp->cp_cmd |= RxVlan;
1569 tp->cp_cmd &= ~RxVlan;
1571 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1572 RTL_R16(tp, CPlusCmd);
1574 rtl_unlock_work(tp);
1579 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1581 return (skb_vlan_tag_present(skb)) ?
1582 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1585 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1587 u32 opts2 = le32_to_cpu(desc->opts2);
1589 if (opts2 & RxVlanTag)
1590 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1593 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1596 struct rtl8169_private *tp = netdev_priv(dev);
1597 u32 __iomem *data = tp->mmio_addr;
1602 for (i = 0; i < R8169_REGS_SIZE; i += 4)
1603 memcpy_fromio(dw++, data++, 4);
1604 rtl_unlock_work(tp);
1607 static u32 rtl8169_get_msglevel(struct net_device *dev)
1609 struct rtl8169_private *tp = netdev_priv(dev);
1611 return tp->msg_enable;
1614 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1616 struct rtl8169_private *tp = netdev_priv(dev);
1618 tp->msg_enable = value;
1621 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1628 "tx_single_collisions",
1629 "tx_multi_collisions",
1637 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1641 return ARRAY_SIZE(rtl8169_gstrings);
1647 DECLARE_RTL_COND(rtl_counters_cond)
1649 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
1652 static bool rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
1654 dma_addr_t paddr = tp->counters_phys_addr;
1657 RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
1658 RTL_R32(tp, CounterAddrHigh);
1659 cmd = (u64)paddr & DMA_BIT_MASK(32);
1660 RTL_W32(tp, CounterAddrLow, cmd);
1661 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
1663 return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
1666 static bool rtl8169_reset_counters(struct rtl8169_private *tp)
1669 * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
1672 if (tp->mac_version < RTL_GIGA_MAC_VER_19)
1675 return rtl8169_do_counters(tp, CounterReset);
1678 static bool rtl8169_update_counters(struct rtl8169_private *tp)
1680 u8 val = RTL_R8(tp, ChipCmd);
1683 * Some chips are unable to dump tally counters when the receiver
1684 * is disabled. If 0xff chip may be in a PCI power-save state.
1686 if (!(val & CmdRxEnb) || val == 0xff)
1689 return rtl8169_do_counters(tp, CounterDump);
1692 static bool rtl8169_init_counter_offsets(struct rtl8169_private *tp)
1694 struct rtl8169_counters *counters = tp->counters;
1698 * rtl8169_init_counter_offsets is called from rtl_open. On chip
1699 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1700 * reset by a power cycle, while the counter values collected by the
1701 * driver are reset at every driver unload/load cycle.
1703 * To make sure the HW values returned by @get_stats64 match the SW
1704 * values, we collect the initial values at first open(*) and use them
1705 * as offsets to normalize the values returned by @get_stats64.
1707 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1708 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1709 * set at open time by rtl_hw_start.
1712 if (tp->tc_offset.inited)
1715 /* If both, reset and update fail, propagate to caller. */
1716 if (rtl8169_reset_counters(tp))
1719 if (rtl8169_update_counters(tp))
1722 tp->tc_offset.tx_errors = counters->tx_errors;
1723 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1724 tp->tc_offset.tx_aborted = counters->tx_aborted;
1725 tp->tc_offset.inited = true;
1730 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1731 struct ethtool_stats *stats, u64 *data)
1733 struct rtl8169_private *tp = netdev_priv(dev);
1734 struct device *d = tp_to_dev(tp);
1735 struct rtl8169_counters *counters = tp->counters;
1739 pm_runtime_get_noresume(d);
1741 if (pm_runtime_active(d))
1742 rtl8169_update_counters(tp);
1744 pm_runtime_put_noidle(d);
1746 data[0] = le64_to_cpu(counters->tx_packets);
1747 data[1] = le64_to_cpu(counters->rx_packets);
1748 data[2] = le64_to_cpu(counters->tx_errors);
1749 data[3] = le32_to_cpu(counters->rx_errors);
1750 data[4] = le16_to_cpu(counters->rx_missed);
1751 data[5] = le16_to_cpu(counters->align_errors);
1752 data[6] = le32_to_cpu(counters->tx_one_collision);
1753 data[7] = le32_to_cpu(counters->tx_multi_collision);
1754 data[8] = le64_to_cpu(counters->rx_unicast);
1755 data[9] = le64_to_cpu(counters->rx_broadcast);
1756 data[10] = le32_to_cpu(counters->rx_multicast);
1757 data[11] = le16_to_cpu(counters->tx_aborted);
1758 data[12] = le16_to_cpu(counters->tx_underun);
1761 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1765 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1771 * Interrupt coalescing
1773 * > 1 - the availability of the IntrMitigate (0xe2) register through the
1774 * > 8169, 8168 and 810x line of chipsets
1776 * 8169, 8168, and 8136(810x) serial chipsets support it.
1778 * > 2 - the Tx timer unit at gigabit speed
1780 * The unit of the timer depends on both the speed and the setting of CPlusCmd
1781 * (0xe0) bit 1 and bit 0.
1784 * bit[1:0] \ speed 1000M 100M 10M
1785 * 0 0 320ns 2.56us 40.96us
1786 * 0 1 2.56us 20.48us 327.7us
1787 * 1 0 5.12us 40.96us 655.4us
1788 * 1 1 10.24us 81.92us 1.31ms
1791 * bit[1:0] \ speed 1000M 100M 10M
1792 * 0 0 5us 2.56us 40.96us
1793 * 0 1 40us 20.48us 327.7us
1794 * 1 0 80us 40.96us 655.4us
1795 * 1 1 160us 81.92us 1.31ms
1798 /* rx/tx scale factors for one particular CPlusCmd[0:1] value */
1799 struct rtl_coalesce_scale {
1804 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
1805 struct rtl_coalesce_info {
1807 struct rtl_coalesce_scale scalev[4]; /* each CPlusCmd[0:1] case */
1810 /* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */
1811 #define rxtx_x1822(r, t) { \
1814 {{(r)*8*2, (t)*8*2}}, \
1815 {{(r)*8*2*2, (t)*8*2*2}}, \
1817 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1818 /* speed delays: rx00 tx00 */
1819 { SPEED_10, rxtx_x1822(40960, 40960) },
1820 { SPEED_100, rxtx_x1822( 2560, 2560) },
1821 { SPEED_1000, rxtx_x1822( 320, 320) },
1825 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1826 /* speed delays: rx00 tx00 */
1827 { SPEED_10, rxtx_x1822(40960, 40960) },
1828 { SPEED_100, rxtx_x1822( 2560, 2560) },
1829 { SPEED_1000, rxtx_x1822( 5000, 5000) },
1834 /* get rx/tx scale vector corresponding to current speed */
1835 static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev)
1837 struct rtl8169_private *tp = netdev_priv(dev);
1838 struct ethtool_link_ksettings ecmd;
1839 const struct rtl_coalesce_info *ci;
1842 rc = phy_ethtool_get_link_ksettings(dev, &ecmd);
1846 for (ci = tp->coalesce_info; ci->speed != 0; ci++) {
1847 if (ecmd.base.speed == ci->speed) {
1852 return ERR_PTR(-ELNRNG);
1855 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1857 struct rtl8169_private *tp = netdev_priv(dev);
1858 const struct rtl_coalesce_info *ci;
1859 const struct rtl_coalesce_scale *scale;
1863 } coal_settings [] = {
1864 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs },
1865 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs }
1866 }, *p = coal_settings;
1870 memset(ec, 0, sizeof(*ec));
1872 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1873 ci = rtl_coalesce_info(dev);
1877 scale = &ci->scalev[tp->cp_cmd & INTT_MASK];
1879 /* read IntrMitigate and adjust according to scale */
1880 for (w = RTL_R16(tp, IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) {
1881 *p->max_frames = (w & RTL_COALESCE_MASK) << 2;
1882 w >>= RTL_COALESCE_SHIFT;
1883 *p->usecs = w & RTL_COALESCE_MASK;
1886 for (i = 0; i < 2; i++) {
1887 p = coal_settings + i;
1888 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000;
1891 * ethtool_coalesce says it is illegal to set both usecs and
1894 if (!*p->usecs && !*p->max_frames)
1901 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */
1902 static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale(
1903 struct net_device *dev, u32 nsec, u16 *cp01)
1905 const struct rtl_coalesce_info *ci;
1908 ci = rtl_coalesce_info(dev);
1910 return ERR_CAST(ci);
1912 for (i = 0; i < 4; i++) {
1913 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0],
1914 ci->scalev[i].nsecs[1]);
1915 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) {
1917 return &ci->scalev[i];
1921 return ERR_PTR(-EINVAL);
1924 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1926 struct rtl8169_private *tp = netdev_priv(dev);
1927 const struct rtl_coalesce_scale *scale;
1931 } coal_settings [] = {
1932 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs },
1933 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs }
1934 }, *p = coal_settings;
1938 scale = rtl_coalesce_choose_scale(dev,
1939 max(p[0].usecs, p[1].usecs) * 1000, &cp01);
1941 return PTR_ERR(scale);
1943 for (i = 0; i < 2; i++, p++) {
1947 * accept max_frames=1 we returned in rtl_get_coalesce.
1948 * accept it not only when usecs=0 because of e.g. the following scenario:
1950 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
1951 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
1952 * - then user does `ethtool -C eth0 rx-usecs 100`
1954 * since ethtool sends to kernel whole ethtool_coalesce
1955 * settings, if we do not handle rx_usecs=!0, rx_frames=1
1956 * we'll reject it below in `frames % 4 != 0`.
1958 if (p->frames == 1) {
1962 units = p->usecs * 1000 / scale->nsecs[i];
1963 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4)
1966 w <<= RTL_COALESCE_SHIFT;
1968 w <<= RTL_COALESCE_SHIFT;
1969 w |= p->frames >> 2;
1974 RTL_W16(tp, IntrMitigate, swab16(w));
1976 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
1977 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1978 RTL_R16(tp, CPlusCmd);
1980 rtl_unlock_work(tp);
1985 static const struct ethtool_ops rtl8169_ethtool_ops = {
1986 .get_drvinfo = rtl8169_get_drvinfo,
1987 .get_regs_len = rtl8169_get_regs_len,
1988 .get_link = ethtool_op_get_link,
1989 .get_coalesce = rtl_get_coalesce,
1990 .set_coalesce = rtl_set_coalesce,
1991 .get_msglevel = rtl8169_get_msglevel,
1992 .set_msglevel = rtl8169_set_msglevel,
1993 .get_regs = rtl8169_get_regs,
1994 .get_wol = rtl8169_get_wol,
1995 .set_wol = rtl8169_set_wol,
1996 .get_strings = rtl8169_get_strings,
1997 .get_sset_count = rtl8169_get_sset_count,
1998 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1999 .get_ts_info = ethtool_op_get_ts_info,
2000 .nway_reset = phy_ethtool_nway_reset,
2001 .get_link_ksettings = phy_ethtool_get_link_ksettings,
2002 .set_link_ksettings = phy_ethtool_set_link_ksettings,
2005 static void rtl8169_get_mac_version(struct rtl8169_private *tp)
2008 * The driver currently handles the 8168Bf and the 8168Be identically
2009 * but they can be identified more specifically through the test below
2012 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2014 * Same thing for the 8101Eb and the 8101Ec:
2016 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2018 static const struct rtl_mac_info {
2023 /* 8168EP family. */
2024 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 },
2025 { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 },
2026 { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 },
2029 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 },
2030 { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 },
2033 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 },
2034 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 },
2035 { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 },
2036 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 },
2039 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 },
2040 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 },
2041 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 },
2044 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 },
2045 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 },
2046 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 },
2049 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 },
2050 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 },
2052 /* 8168DP family. */
2053 { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 },
2054 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 },
2055 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 },
2058 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 },
2059 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 },
2060 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 },
2061 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 },
2062 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 },
2063 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 },
2064 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 },
2067 { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12 },
2068 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 },
2069 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 },
2072 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 },
2073 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 },
2074 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 },
2075 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 },
2076 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 },
2077 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 },
2078 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 },
2079 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 },
2080 { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13 },
2081 { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10 },
2082 { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16 },
2083 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 },
2084 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 },
2085 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16 },
2086 /* FIXME: where did these entries come from ? -- FR */
2087 { 0xfc8, 0x388, RTL_GIGA_MAC_VER_15 },
2088 { 0xfc8, 0x308, RTL_GIGA_MAC_VER_14 },
2091 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 },
2092 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 },
2093 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 },
2094 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 },
2095 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 },
2096 { 0xfc8, 0x000, RTL_GIGA_MAC_VER_01 },
2099 { 0x000, 0x000, RTL_GIGA_MAC_NONE }
2101 const struct rtl_mac_info *p = mac_info;
2102 u16 reg = RTL_R32(tp, TxConfig) >> 20;
2104 while ((reg & p->mask) != p->val)
2106 tp->mac_version = p->mac_version;
2108 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2109 dev_err(tp_to_dev(tp), "unknown chip XID %03x\n", reg & 0xfcf);
2110 } else if (!tp->supports_gmii) {
2111 if (tp->mac_version == RTL_GIGA_MAC_VER_42)
2112 tp->mac_version = RTL_GIGA_MAC_VER_43;
2113 else if (tp->mac_version == RTL_GIGA_MAC_VER_45)
2114 tp->mac_version = RTL_GIGA_MAC_VER_47;
2115 else if (tp->mac_version == RTL_GIGA_MAC_VER_46)
2116 tp->mac_version = RTL_GIGA_MAC_VER_48;
2125 static void rtl_writephy_batch(struct rtl8169_private *tp,
2126 const struct phy_reg *regs, int len)
2129 rtl_writephy(tp, regs->reg, regs->val);
2134 #define PHY_READ 0x00000000
2135 #define PHY_DATA_OR 0x10000000
2136 #define PHY_DATA_AND 0x20000000
2137 #define PHY_BJMPN 0x30000000
2138 #define PHY_MDIO_CHG 0x40000000
2139 #define PHY_CLEAR_READCOUNT 0x70000000
2140 #define PHY_WRITE 0x80000000
2141 #define PHY_READCOUNT_EQ_SKIP 0x90000000
2142 #define PHY_COMP_EQ_SKIPN 0xa0000000
2143 #define PHY_COMP_NEQ_SKIPN 0xb0000000
2144 #define PHY_WRITE_PREVIOUS 0xc0000000
2145 #define PHY_SKIPN 0xd0000000
2146 #define PHY_DELAY_MS 0xe0000000
2150 char version[RTL_VER_SIZE];
2156 #define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2158 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2160 const struct firmware *fw = rtl_fw->fw;
2161 struct fw_info *fw_info = (struct fw_info *)fw->data;
2162 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2163 char *version = rtl_fw->version;
2166 if (fw->size < FW_OPCODE_SIZE)
2169 if (!fw_info->magic) {
2170 size_t i, size, start;
2173 if (fw->size < sizeof(*fw_info))
2176 for (i = 0; i < fw->size; i++)
2177 checksum += fw->data[i];
2181 start = le32_to_cpu(fw_info->fw_start);
2182 if (start > fw->size)
2185 size = le32_to_cpu(fw_info->fw_len);
2186 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2189 memcpy(version, fw_info->version, RTL_VER_SIZE);
2191 pa->code = (__le32 *)(fw->data + start);
2194 if (fw->size % FW_OPCODE_SIZE)
2197 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2199 pa->code = (__le32 *)fw->data;
2200 pa->size = fw->size / FW_OPCODE_SIZE;
2202 version[RTL_VER_SIZE - 1] = 0;
2209 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2210 struct rtl_fw_phy_action *pa)
2215 for (index = 0; index < pa->size; index++) {
2216 u32 action = le32_to_cpu(pa->code[index]);
2217 u32 regno = (action & 0x0fff0000) >> 16;
2219 switch(action & 0xf0000000) {
2224 case PHY_CLEAR_READCOUNT:
2226 case PHY_WRITE_PREVIOUS:
2231 if (regno > index) {
2232 netif_err(tp, ifup, tp->dev,
2233 "Out of range of firmware\n");
2237 case PHY_READCOUNT_EQ_SKIP:
2238 if (index + 2 >= pa->size) {
2239 netif_err(tp, ifup, tp->dev,
2240 "Out of range of firmware\n");
2244 case PHY_COMP_EQ_SKIPN:
2245 case PHY_COMP_NEQ_SKIPN:
2247 if (index + 1 + regno >= pa->size) {
2248 netif_err(tp, ifup, tp->dev,
2249 "Out of range of firmware\n");
2255 netif_err(tp, ifup, tp->dev,
2256 "Invalid action 0x%08x\n", action);
2265 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2267 struct net_device *dev = tp->dev;
2270 if (!rtl_fw_format_ok(tp, rtl_fw)) {
2271 netif_err(tp, ifup, dev, "invalid firmware\n");
2275 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2281 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2283 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2284 struct mdio_ops org, *ops = &tp->mdio_ops;
2288 predata = count = 0;
2289 org.write = ops->write;
2290 org.read = ops->read;
2292 for (index = 0; index < pa->size; ) {
2293 u32 action = le32_to_cpu(pa->code[index]);
2294 u32 data = action & 0x0000ffff;
2295 u32 regno = (action & 0x0fff0000) >> 16;
2300 switch(action & 0xf0000000) {
2302 predata = rtl_readphy(tp, regno);
2319 ops->write = org.write;
2320 ops->read = org.read;
2321 } else if (data == 1) {
2322 ops->write = mac_mcu_write;
2323 ops->read = mac_mcu_read;
2328 case PHY_CLEAR_READCOUNT:
2333 rtl_writephy(tp, regno, data);
2336 case PHY_READCOUNT_EQ_SKIP:
2337 index += (count == data) ? 2 : 1;
2339 case PHY_COMP_EQ_SKIPN:
2340 if (predata == data)
2344 case PHY_COMP_NEQ_SKIPN:
2345 if (predata != data)
2349 case PHY_WRITE_PREVIOUS:
2350 rtl_writephy(tp, regno, predata);
2366 ops->write = org.write;
2367 ops->read = org.read;
2370 static void rtl_release_firmware(struct rtl8169_private *tp)
2372 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2373 release_firmware(tp->rtl_fw->fw);
2376 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2379 static void rtl_apply_firmware(struct rtl8169_private *tp)
2381 struct rtl_fw *rtl_fw = tp->rtl_fw;
2383 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2384 if (!IS_ERR_OR_NULL(rtl_fw))
2385 rtl_phy_write_fw(tp, rtl_fw);
2388 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2390 if (rtl_readphy(tp, reg) != val)
2391 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2393 rtl_apply_firmware(tp);
2396 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2398 static const struct phy_reg phy_reg_init[] = {
2460 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2463 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2465 static const struct phy_reg phy_reg_init[] = {
2471 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2474 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2476 struct pci_dev *pdev = tp->pci_dev;
2478 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2479 (pdev->subsystem_device != 0xe000))
2482 rtl_writephy(tp, 0x1f, 0x0001);
2483 rtl_writephy(tp, 0x10, 0xf01b);
2484 rtl_writephy(tp, 0x1f, 0x0000);
2487 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2489 static const struct phy_reg phy_reg_init[] = {
2529 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2531 rtl8169scd_hw_phy_config_quirk(tp);
2534 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2536 static const struct phy_reg phy_reg_init[] = {
2584 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2587 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2589 static const struct phy_reg phy_reg_init[] = {
2594 rtl_writephy(tp, 0x1f, 0x0001);
2595 rtl_patchphy(tp, 0x16, 1 << 0);
2597 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2600 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2602 static const struct phy_reg phy_reg_init[] = {
2608 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2611 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2613 static const struct phy_reg phy_reg_init[] = {
2621 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2624 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2626 static const struct phy_reg phy_reg_init[] = {
2632 rtl_writephy(tp, 0x1f, 0x0000);
2633 rtl_patchphy(tp, 0x14, 1 << 5);
2634 rtl_patchphy(tp, 0x0d, 1 << 5);
2636 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2639 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2641 static const struct phy_reg phy_reg_init[] = {
2661 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2663 rtl_patchphy(tp, 0x14, 1 << 5);
2664 rtl_patchphy(tp, 0x0d, 1 << 5);
2665 rtl_writephy(tp, 0x1f, 0x0000);
2668 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2670 static const struct phy_reg phy_reg_init[] = {
2688 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2690 rtl_patchphy(tp, 0x16, 1 << 0);
2691 rtl_patchphy(tp, 0x14, 1 << 5);
2692 rtl_patchphy(tp, 0x0d, 1 << 5);
2693 rtl_writephy(tp, 0x1f, 0x0000);
2696 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2698 static const struct phy_reg phy_reg_init[] = {
2710 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2712 rtl_patchphy(tp, 0x16, 1 << 0);
2713 rtl_patchphy(tp, 0x14, 1 << 5);
2714 rtl_patchphy(tp, 0x0d, 1 << 5);
2715 rtl_writephy(tp, 0x1f, 0x0000);
2718 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2720 rtl8168c_3_hw_phy_config(tp);
2723 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2725 static const struct phy_reg phy_reg_init_0[] = {
2726 /* Channel Estimation */
2747 * Enhance line driver power
2756 * Can not link to 1Gbps with bad cable
2757 * Decrease SNR threshold form 21.07dB to 19.04dB
2766 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2770 * Fine Tune Switching regulator parameter
2772 rtl_writephy(tp, 0x1f, 0x0002);
2773 rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
2774 rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
2776 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2777 static const struct phy_reg phy_reg_init[] = {
2787 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2789 val = rtl_readphy(tp, 0x0d);
2791 if ((val & 0x00ff) != 0x006c) {
2792 static const u32 set[] = {
2793 0x0065, 0x0066, 0x0067, 0x0068,
2794 0x0069, 0x006a, 0x006b, 0x006c
2798 rtl_writephy(tp, 0x1f, 0x0002);
2801 for (i = 0; i < ARRAY_SIZE(set); i++)
2802 rtl_writephy(tp, 0x0d, val | set[i]);
2805 static const struct phy_reg phy_reg_init[] = {
2813 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2816 /* RSET couple improve */
2817 rtl_writephy(tp, 0x1f, 0x0002);
2818 rtl_patchphy(tp, 0x0d, 0x0300);
2819 rtl_patchphy(tp, 0x0f, 0x0010);
2821 /* Fine tune PLL performance */
2822 rtl_writephy(tp, 0x1f, 0x0002);
2823 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2824 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
2826 rtl_writephy(tp, 0x1f, 0x0005);
2827 rtl_writephy(tp, 0x05, 0x001b);
2829 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2831 rtl_writephy(tp, 0x1f, 0x0000);
2834 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2836 static const struct phy_reg phy_reg_init_0[] = {
2837 /* Channel Estimation */
2858 * Enhance line driver power
2867 * Can not link to 1Gbps with bad cable
2868 * Decrease SNR threshold form 21.07dB to 19.04dB
2877 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2879 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2880 static const struct phy_reg phy_reg_init[] = {
2891 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2893 val = rtl_readphy(tp, 0x0d);
2894 if ((val & 0x00ff) != 0x006c) {
2895 static const u32 set[] = {
2896 0x0065, 0x0066, 0x0067, 0x0068,
2897 0x0069, 0x006a, 0x006b, 0x006c
2901 rtl_writephy(tp, 0x1f, 0x0002);
2904 for (i = 0; i < ARRAY_SIZE(set); i++)
2905 rtl_writephy(tp, 0x0d, val | set[i]);
2908 static const struct phy_reg phy_reg_init[] = {
2916 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2919 /* Fine tune PLL performance */
2920 rtl_writephy(tp, 0x1f, 0x0002);
2921 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2922 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
2924 /* Switching regulator Slew rate */
2925 rtl_writephy(tp, 0x1f, 0x0002);
2926 rtl_patchphy(tp, 0x0f, 0x0017);
2928 rtl_writephy(tp, 0x1f, 0x0005);
2929 rtl_writephy(tp, 0x05, 0x001b);
2931 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2933 rtl_writephy(tp, 0x1f, 0x0000);
2936 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2938 static const struct phy_reg phy_reg_init[] = {
2994 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2997 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2999 static const struct phy_reg phy_reg_init[] = {
3009 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3010 rtl_patchphy(tp, 0x0d, 1 << 5);
3013 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
3015 static const struct phy_reg phy_reg_init[] = {
3016 /* Enable Delay cap */
3022 /* Channel estimation fine tune */
3031 /* Update PFM & 10M TX idle timer */
3043 rtl_apply_firmware(tp);
3045 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3047 /* DCO enable for 10M IDLE Power */
3048 rtl_writephy(tp, 0x1f, 0x0007);
3049 rtl_writephy(tp, 0x1e, 0x0023);
3050 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3051 rtl_writephy(tp, 0x1f, 0x0000);
3053 /* For impedance matching */
3054 rtl_writephy(tp, 0x1f, 0x0002);
3055 rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
3056 rtl_writephy(tp, 0x1f, 0x0000);
3058 /* PHY auto speed down */
3059 rtl_writephy(tp, 0x1f, 0x0007);
3060 rtl_writephy(tp, 0x1e, 0x002d);
3061 rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
3062 rtl_writephy(tp, 0x1f, 0x0000);
3063 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3065 rtl_writephy(tp, 0x1f, 0x0005);
3066 rtl_writephy(tp, 0x05, 0x8b86);
3067 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3068 rtl_writephy(tp, 0x1f, 0x0000);
3070 rtl_writephy(tp, 0x1f, 0x0005);
3071 rtl_writephy(tp, 0x05, 0x8b85);
3072 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3073 rtl_writephy(tp, 0x1f, 0x0007);
3074 rtl_writephy(tp, 0x1e, 0x0020);
3075 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
3076 rtl_writephy(tp, 0x1f, 0x0006);
3077 rtl_writephy(tp, 0x00, 0x5a00);
3078 rtl_writephy(tp, 0x1f, 0x0000);
3079 rtl_writephy(tp, 0x0d, 0x0007);
3080 rtl_writephy(tp, 0x0e, 0x003c);
3081 rtl_writephy(tp, 0x0d, 0x4007);
3082 rtl_writephy(tp, 0x0e, 0x0000);
3083 rtl_writephy(tp, 0x0d, 0x0000);
3086 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3089 addr[0] | (addr[1] << 8),
3090 addr[2] | (addr[3] << 8),
3091 addr[4] | (addr[5] << 8)
3093 const struct exgmac_reg e[] = {
3094 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3095 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3096 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3097 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3100 rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3103 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3105 static const struct phy_reg phy_reg_init[] = {
3106 /* Enable Delay cap */
3115 /* Channel estimation fine tune */
3132 rtl_apply_firmware(tp);
3134 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3136 /* For 4-corner performance improve */
3137 rtl_writephy(tp, 0x1f, 0x0005);
3138 rtl_writephy(tp, 0x05, 0x8b80);
3139 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3140 rtl_writephy(tp, 0x1f, 0x0000);
3142 /* PHY auto speed down */
3143 rtl_writephy(tp, 0x1f, 0x0004);
3144 rtl_writephy(tp, 0x1f, 0x0007);
3145 rtl_writephy(tp, 0x1e, 0x002d);
3146 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3147 rtl_writephy(tp, 0x1f, 0x0002);
3148 rtl_writephy(tp, 0x1f, 0x0000);
3149 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3151 /* improve 10M EEE waveform */
3152 rtl_writephy(tp, 0x1f, 0x0005);
3153 rtl_writephy(tp, 0x05, 0x8b86);
3154 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3155 rtl_writephy(tp, 0x1f, 0x0000);
3157 /* Improve 2-pair detection performance */
3158 rtl_writephy(tp, 0x1f, 0x0005);
3159 rtl_writephy(tp, 0x05, 0x8b85);
3160 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3161 rtl_writephy(tp, 0x1f, 0x0000);
3164 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0003, 0x0000, ERIAR_EXGMAC);
3165 rtl_writephy(tp, 0x1f, 0x0005);
3166 rtl_writephy(tp, 0x05, 0x8b85);
3167 rtl_w0w1_phy(tp, 0x06, 0x2000, 0x0000);
3168 rtl_writephy(tp, 0x1f, 0x0004);
3169 rtl_writephy(tp, 0x1f, 0x0007);
3170 rtl_writephy(tp, 0x1e, 0x0020);
3171 rtl_w0w1_phy(tp, 0x15, 0x0100, 0x0000);
3172 rtl_writephy(tp, 0x1f, 0x0002);
3173 rtl_writephy(tp, 0x1f, 0x0000);
3174 rtl_writephy(tp, 0x0d, 0x0007);
3175 rtl_writephy(tp, 0x0e, 0x003c);
3176 rtl_writephy(tp, 0x0d, 0x4007);
3177 rtl_writephy(tp, 0x0e, 0x0006);
3178 rtl_writephy(tp, 0x0d, 0x0000);
3181 rtl_writephy(tp, 0x1f, 0x0003);
3182 rtl_w0w1_phy(tp, 0x19, 0x0001, 0x0000);
3183 rtl_w0w1_phy(tp, 0x10, 0x0400, 0x0000);
3184 rtl_writephy(tp, 0x1f, 0x0000);
3185 rtl_writephy(tp, 0x1f, 0x0005);
3186 rtl_w0w1_phy(tp, 0x01, 0x0100, 0x0000);
3187 rtl_writephy(tp, 0x1f, 0x0000);
3189 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3190 rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3193 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3195 /* For 4-corner performance improve */
3196 rtl_writephy(tp, 0x1f, 0x0005);
3197 rtl_writephy(tp, 0x05, 0x8b80);
3198 rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
3199 rtl_writephy(tp, 0x1f, 0x0000);
3201 /* PHY auto speed down */
3202 rtl_writephy(tp, 0x1f, 0x0007);
3203 rtl_writephy(tp, 0x1e, 0x002d);
3204 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3205 rtl_writephy(tp, 0x1f, 0x0000);
3206 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3208 /* Improve 10M EEE waveform */
3209 rtl_writephy(tp, 0x1f, 0x0005);
3210 rtl_writephy(tp, 0x05, 0x8b86);
3211 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3212 rtl_writephy(tp, 0x1f, 0x0000);
3215 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3217 static const struct phy_reg phy_reg_init[] = {
3218 /* Channel estimation fine tune */
3223 /* Modify green table for giga & fnet */
3240 /* Modify green table for 10M */
3246 /* Disable hiimpedance detection (RTCT) */
3252 rtl_apply_firmware(tp);
3254 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3256 rtl8168f_hw_phy_config(tp);
3258 /* Improve 2-pair detection performance */
3259 rtl_writephy(tp, 0x1f, 0x0005);
3260 rtl_writephy(tp, 0x05, 0x8b85);
3261 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3262 rtl_writephy(tp, 0x1f, 0x0000);
3265 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3267 rtl_apply_firmware(tp);
3269 rtl8168f_hw_phy_config(tp);
3272 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3274 static const struct phy_reg phy_reg_init[] = {
3275 /* Channel estimation fine tune */
3280 /* Modify green table for giga & fnet */
3297 /* Modify green table for 10M */
3303 /* Disable hiimpedance detection (RTCT) */
3310 rtl_apply_firmware(tp);
3312 rtl8168f_hw_phy_config(tp);
3314 /* Improve 2-pair detection performance */
3315 rtl_writephy(tp, 0x1f, 0x0005);
3316 rtl_writephy(tp, 0x05, 0x8b85);
3317 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3318 rtl_writephy(tp, 0x1f, 0x0000);
3320 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3322 /* Modify green table for giga */
3323 rtl_writephy(tp, 0x1f, 0x0005);
3324 rtl_writephy(tp, 0x05, 0x8b54);
3325 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3326 rtl_writephy(tp, 0x05, 0x8b5d);
3327 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3328 rtl_writephy(tp, 0x05, 0x8a7c);
3329 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3330 rtl_writephy(tp, 0x05, 0x8a7f);
3331 rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
3332 rtl_writephy(tp, 0x05, 0x8a82);
3333 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3334 rtl_writephy(tp, 0x05, 0x8a85);
3335 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3336 rtl_writephy(tp, 0x05, 0x8a88);
3337 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3338 rtl_writephy(tp, 0x1f, 0x0000);
3340 /* uc same-seed solution */
3341 rtl_writephy(tp, 0x1f, 0x0005);
3342 rtl_writephy(tp, 0x05, 0x8b85);
3343 rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
3344 rtl_writephy(tp, 0x1f, 0x0000);
3347 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
3348 rtl_writephy(tp, 0x1f, 0x0005);
3349 rtl_writephy(tp, 0x05, 0x8b85);
3350 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3351 rtl_writephy(tp, 0x1f, 0x0004);
3352 rtl_writephy(tp, 0x1f, 0x0007);
3353 rtl_writephy(tp, 0x1e, 0x0020);
3354 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
3355 rtl_writephy(tp, 0x1f, 0x0000);
3356 rtl_writephy(tp, 0x0d, 0x0007);
3357 rtl_writephy(tp, 0x0e, 0x003c);
3358 rtl_writephy(tp, 0x0d, 0x4007);
3359 rtl_writephy(tp, 0x0e, 0x0000);
3360 rtl_writephy(tp, 0x0d, 0x0000);
3363 rtl_writephy(tp, 0x1f, 0x0003);
3364 rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3365 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3366 rtl_writephy(tp, 0x1f, 0x0000);
3369 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3371 rtl_apply_firmware(tp);
3373 rtl_writephy(tp, 0x1f, 0x0a46);
3374 if (rtl_readphy(tp, 0x10) & 0x0100) {
3375 rtl_writephy(tp, 0x1f, 0x0bcc);
3376 rtl_w0w1_phy(tp, 0x12, 0x0000, 0x8000);
3378 rtl_writephy(tp, 0x1f, 0x0bcc);
3379 rtl_w0w1_phy(tp, 0x12, 0x8000, 0x0000);
3382 rtl_writephy(tp, 0x1f, 0x0a46);
3383 if (rtl_readphy(tp, 0x13) & 0x0100) {
3384 rtl_writephy(tp, 0x1f, 0x0c41);
3385 rtl_w0w1_phy(tp, 0x15, 0x0002, 0x0000);
3387 rtl_writephy(tp, 0x1f, 0x0c41);
3388 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0002);
3391 /* Enable PHY auto speed down */
3392 rtl_writephy(tp, 0x1f, 0x0a44);
3393 rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3395 rtl_writephy(tp, 0x1f, 0x0bcc);
3396 rtl_w0w1_phy(tp, 0x14, 0x0100, 0x0000);
3397 rtl_writephy(tp, 0x1f, 0x0a44);
3398 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3399 rtl_writephy(tp, 0x1f, 0x0a43);
3400 rtl_writephy(tp, 0x13, 0x8084);
3401 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3402 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3404 /* EEE auto-fallback function */
3405 rtl_writephy(tp, 0x1f, 0x0a4b);
3406 rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3408 /* Enable UC LPF tune function */
3409 rtl_writephy(tp, 0x1f, 0x0a43);
3410 rtl_writephy(tp, 0x13, 0x8012);
3411 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3413 rtl_writephy(tp, 0x1f, 0x0c42);
3414 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3416 /* Improve SWR Efficiency */
3417 rtl_writephy(tp, 0x1f, 0x0bcd);
3418 rtl_writephy(tp, 0x14, 0x5065);
3419 rtl_writephy(tp, 0x14, 0xd065);
3420 rtl_writephy(tp, 0x1f, 0x0bc8);
3421 rtl_writephy(tp, 0x11, 0x5655);
3422 rtl_writephy(tp, 0x1f, 0x0bcd);
3423 rtl_writephy(tp, 0x14, 0x1065);
3424 rtl_writephy(tp, 0x14, 0x9065);
3425 rtl_writephy(tp, 0x14, 0x1065);
3427 /* Check ALDPS bit, disable it if enabled */
3428 rtl_writephy(tp, 0x1f, 0x0a43);
3429 if (rtl_readphy(tp, 0x10) & 0x0004)
3430 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3432 rtl_writephy(tp, 0x1f, 0x0000);
3435 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3437 rtl_apply_firmware(tp);
3440 static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3445 rtl_apply_firmware(tp);
3447 /* CHN EST parameters adjust - giga master */
3448 rtl_writephy(tp, 0x1f, 0x0a43);
3449 rtl_writephy(tp, 0x13, 0x809b);
3450 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
3451 rtl_writephy(tp, 0x13, 0x80a2);
3452 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
3453 rtl_writephy(tp, 0x13, 0x80a4);
3454 rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
3455 rtl_writephy(tp, 0x13, 0x809c);
3456 rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
3457 rtl_writephy(tp, 0x1f, 0x0000);
3459 /* CHN EST parameters adjust - giga slave */
3460 rtl_writephy(tp, 0x1f, 0x0a43);
3461 rtl_writephy(tp, 0x13, 0x80ad);
3462 rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
3463 rtl_writephy(tp, 0x13, 0x80b4);
3464 rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
3465 rtl_writephy(tp, 0x13, 0x80ac);
3466 rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
3467 rtl_writephy(tp, 0x1f, 0x0000);
3469 /* CHN EST parameters adjust - fnet */
3470 rtl_writephy(tp, 0x1f, 0x0a43);
3471 rtl_writephy(tp, 0x13, 0x808e);
3472 rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
3473 rtl_writephy(tp, 0x13, 0x8090);
3474 rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
3475 rtl_writephy(tp, 0x13, 0x8092);
3476 rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
3477 rtl_writephy(tp, 0x1f, 0x0000);
3479 /* enable R-tune & PGA-retune function */
3481 rtl_writephy(tp, 0x1f, 0x0a46);
3482 data = rtl_readphy(tp, 0x13);
3485 dout_tapbin |= data;
3486 data = rtl_readphy(tp, 0x12);
3489 dout_tapbin |= data;
3490 dout_tapbin = ~(dout_tapbin^0x08);
3492 dout_tapbin &= 0xf000;
3493 rtl_writephy(tp, 0x1f, 0x0a43);
3494 rtl_writephy(tp, 0x13, 0x827a);
3495 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3496 rtl_writephy(tp, 0x13, 0x827b);
3497 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3498 rtl_writephy(tp, 0x13, 0x827c);
3499 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3500 rtl_writephy(tp, 0x13, 0x827d);
3501 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3503 rtl_writephy(tp, 0x1f, 0x0a43);
3504 rtl_writephy(tp, 0x13, 0x0811);
3505 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3506 rtl_writephy(tp, 0x1f, 0x0a42);
3507 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3508 rtl_writephy(tp, 0x1f, 0x0000);
3510 /* enable GPHY 10M */
3511 rtl_writephy(tp, 0x1f, 0x0a44);
3512 rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3513 rtl_writephy(tp, 0x1f, 0x0000);
3515 /* SAR ADC performance */
3516 rtl_writephy(tp, 0x1f, 0x0bca);
3517 rtl_w0w1_phy(tp, 0x17, 0x4000, 0x3000);
3518 rtl_writephy(tp, 0x1f, 0x0000);
3520 rtl_writephy(tp, 0x1f, 0x0a43);
3521 rtl_writephy(tp, 0x13, 0x803f);
3522 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3523 rtl_writephy(tp, 0x13, 0x8047);
3524 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3525 rtl_writephy(tp, 0x13, 0x804f);
3526 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3527 rtl_writephy(tp, 0x13, 0x8057);
3528 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3529 rtl_writephy(tp, 0x13, 0x805f);
3530 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3531 rtl_writephy(tp, 0x13, 0x8067);
3532 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3533 rtl_writephy(tp, 0x13, 0x806f);
3534 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3535 rtl_writephy(tp, 0x1f, 0x0000);
3537 /* disable phy pfm mode */
3538 rtl_writephy(tp, 0x1f, 0x0a44);
3539 rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
3540 rtl_writephy(tp, 0x1f, 0x0000);
3542 /* Check ALDPS bit, disable it if enabled */
3543 rtl_writephy(tp, 0x1f, 0x0a43);
3544 if (rtl_readphy(tp, 0x10) & 0x0004)
3545 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3547 rtl_writephy(tp, 0x1f, 0x0000);
3550 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3552 u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3556 rtl_apply_firmware(tp);
3558 /* CHIN EST parameter update */
3559 rtl_writephy(tp, 0x1f, 0x0a43);
3560 rtl_writephy(tp, 0x13, 0x808a);
3561 rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
3562 rtl_writephy(tp, 0x1f, 0x0000);
3564 /* enable R-tune & PGA-retune function */
3565 rtl_writephy(tp, 0x1f, 0x0a43);
3566 rtl_writephy(tp, 0x13, 0x0811);
3567 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3568 rtl_writephy(tp, 0x1f, 0x0a42);
3569 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3570 rtl_writephy(tp, 0x1f, 0x0000);
3572 /* enable GPHY 10M */
3573 rtl_writephy(tp, 0x1f, 0x0a44);
3574 rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3575 rtl_writephy(tp, 0x1f, 0x0000);
3577 r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3578 data = r8168_mac_ocp_read(tp, 0xdd02);
3579 ioffset_p3 = ((data & 0x80)>>7);
3582 data = r8168_mac_ocp_read(tp, 0xdd00);
3583 ioffset_p3 |= ((data & (0xe000))>>13);
3584 ioffset_p2 = ((data & (0x1e00))>>9);
3585 ioffset_p1 = ((data & (0x01e0))>>5);
3586 ioffset_p0 = ((data & 0x0010)>>4);
3588 ioffset_p0 |= (data & (0x07));
3589 data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3591 if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
3592 (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) {
3593 rtl_writephy(tp, 0x1f, 0x0bcf);
3594 rtl_writephy(tp, 0x16, data);
3595 rtl_writephy(tp, 0x1f, 0x0000);
3598 /* Modify rlen (TX LPF corner frequency) level */
3599 rtl_writephy(tp, 0x1f, 0x0bcd);
3600 data = rtl_readphy(tp, 0x16);
3605 data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
3606 rtl_writephy(tp, 0x17, data);
3607 rtl_writephy(tp, 0x1f, 0x0bcd);
3608 rtl_writephy(tp, 0x1f, 0x0000);
3610 /* disable phy pfm mode */
3611 rtl_writephy(tp, 0x1f, 0x0a44);
3612 rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
3613 rtl_writephy(tp, 0x1f, 0x0000);
3615 /* Check ALDPS bit, disable it if enabled */
3616 rtl_writephy(tp, 0x1f, 0x0a43);
3617 if (rtl_readphy(tp, 0x10) & 0x0004)
3618 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3620 rtl_writephy(tp, 0x1f, 0x0000);
3623 static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
3625 /* Enable PHY auto speed down */
3626 rtl_writephy(tp, 0x1f, 0x0a44);
3627 rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3628 rtl_writephy(tp, 0x1f, 0x0000);
3630 /* patch 10M & ALDPS */
3631 rtl_writephy(tp, 0x1f, 0x0bcc);
3632 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
3633 rtl_writephy(tp, 0x1f, 0x0a44);
3634 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3635 rtl_writephy(tp, 0x1f, 0x0a43);
3636 rtl_writephy(tp, 0x13, 0x8084);
3637 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3638 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3639 rtl_writephy(tp, 0x1f, 0x0000);
3641 /* Enable EEE auto-fallback function */
3642 rtl_writephy(tp, 0x1f, 0x0a4b);
3643 rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3644 rtl_writephy(tp, 0x1f, 0x0000);
3646 /* Enable UC LPF tune function */
3647 rtl_writephy(tp, 0x1f, 0x0a43);
3648 rtl_writephy(tp, 0x13, 0x8012);
3649 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3650 rtl_writephy(tp, 0x1f, 0x0000);
3652 /* set rg_sel_sdm_rate */
3653 rtl_writephy(tp, 0x1f, 0x0c42);
3654 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3655 rtl_writephy(tp, 0x1f, 0x0000);
3657 /* Check ALDPS bit, disable it if enabled */
3658 rtl_writephy(tp, 0x1f, 0x0a43);
3659 if (rtl_readphy(tp, 0x10) & 0x0004)
3660 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3662 rtl_writephy(tp, 0x1f, 0x0000);
3665 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
3667 /* patch 10M & ALDPS */
3668 rtl_writephy(tp, 0x1f, 0x0bcc);
3669 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
3670 rtl_writephy(tp, 0x1f, 0x0a44);
3671 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3672 rtl_writephy(tp, 0x1f, 0x0a43);
3673 rtl_writephy(tp, 0x13, 0x8084);
3674 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3675 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3676 rtl_writephy(tp, 0x1f, 0x0000);
3678 /* Enable UC LPF tune function */
3679 rtl_writephy(tp, 0x1f, 0x0a43);
3680 rtl_writephy(tp, 0x13, 0x8012);
3681 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3682 rtl_writephy(tp, 0x1f, 0x0000);
3684 /* Set rg_sel_sdm_rate */
3685 rtl_writephy(tp, 0x1f, 0x0c42);
3686 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3687 rtl_writephy(tp, 0x1f, 0x0000);
3689 /* Channel estimation parameters */
3690 rtl_writephy(tp, 0x1f, 0x0a43);
3691 rtl_writephy(tp, 0x13, 0x80f3);
3692 rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
3693 rtl_writephy(tp, 0x13, 0x80f0);
3694 rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
3695 rtl_writephy(tp, 0x13, 0x80ef);
3696 rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
3697 rtl_writephy(tp, 0x13, 0x80f6);
3698 rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
3699 rtl_writephy(tp, 0x13, 0x80ec);
3700 rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
3701 rtl_writephy(tp, 0x13, 0x80ed);
3702 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3703 rtl_writephy(tp, 0x13, 0x80f2);
3704 rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
3705 rtl_writephy(tp, 0x13, 0x80f4);
3706 rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
3707 rtl_writephy(tp, 0x1f, 0x0a43);
3708 rtl_writephy(tp, 0x13, 0x8110);
3709 rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
3710 rtl_writephy(tp, 0x13, 0x810f);
3711 rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
3712 rtl_writephy(tp, 0x13, 0x8111);
3713 rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
3714 rtl_writephy(tp, 0x13, 0x8113);
3715 rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
3716 rtl_writephy(tp, 0x13, 0x8115);
3717 rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
3718 rtl_writephy(tp, 0x13, 0x810e);
3719 rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
3720 rtl_writephy(tp, 0x13, 0x810c);
3721 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3722 rtl_writephy(tp, 0x13, 0x810b);
3723 rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
3724 rtl_writephy(tp, 0x1f, 0x0a43);
3725 rtl_writephy(tp, 0x13, 0x80d1);
3726 rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
3727 rtl_writephy(tp, 0x13, 0x80cd);
3728 rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
3729 rtl_writephy(tp, 0x13, 0x80d3);
3730 rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
3731 rtl_writephy(tp, 0x13, 0x80d5);
3732 rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
3733 rtl_writephy(tp, 0x13, 0x80d7);
3734 rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
3736 /* Force PWM-mode */
3737 rtl_writephy(tp, 0x1f, 0x0bcd);
3738 rtl_writephy(tp, 0x14, 0x5065);
3739 rtl_writephy(tp, 0x14, 0xd065);
3740 rtl_writephy(tp, 0x1f, 0x0bc8);
3741 rtl_writephy(tp, 0x12, 0x00ed);
3742 rtl_writephy(tp, 0x1f, 0x0bcd);
3743 rtl_writephy(tp, 0x14, 0x1065);
3744 rtl_writephy(tp, 0x14, 0x9065);
3745 rtl_writephy(tp, 0x14, 0x1065);
3746 rtl_writephy(tp, 0x1f, 0x0000);
3748 /* Check ALDPS bit, disable it if enabled */
3749 rtl_writephy(tp, 0x1f, 0x0a43);
3750 if (rtl_readphy(tp, 0x10) & 0x0004)
3751 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3753 rtl_writephy(tp, 0x1f, 0x0000);
3756 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3758 static const struct phy_reg phy_reg_init[] = {
3765 rtl_writephy(tp, 0x1f, 0x0000);
3766 rtl_patchphy(tp, 0x11, 1 << 12);
3767 rtl_patchphy(tp, 0x19, 1 << 13);
3768 rtl_patchphy(tp, 0x10, 1 << 15);
3770 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3773 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3775 static const struct phy_reg phy_reg_init[] = {
3789 /* Disable ALDPS before ram code */
3790 rtl_writephy(tp, 0x1f, 0x0000);
3791 rtl_writephy(tp, 0x18, 0x0310);
3794 rtl_apply_firmware(tp);
3796 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3799 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3801 /* Disable ALDPS before setting firmware */
3802 rtl_writephy(tp, 0x1f, 0x0000);
3803 rtl_writephy(tp, 0x18, 0x0310);
3806 rtl_apply_firmware(tp);
3809 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3810 rtl_writephy(tp, 0x1f, 0x0004);
3811 rtl_writephy(tp, 0x10, 0x401f);
3812 rtl_writephy(tp, 0x19, 0x7030);
3813 rtl_writephy(tp, 0x1f, 0x0000);
3816 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3818 static const struct phy_reg phy_reg_init[] = {
3825 /* Disable ALDPS before ram code */
3826 rtl_writephy(tp, 0x1f, 0x0000);
3827 rtl_writephy(tp, 0x18, 0x0310);
3830 rtl_apply_firmware(tp);
3832 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3833 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3835 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3838 static void rtl_hw_phy_config(struct net_device *dev)
3840 struct rtl8169_private *tp = netdev_priv(dev);
3842 switch (tp->mac_version) {
3843 case RTL_GIGA_MAC_VER_01:
3845 case RTL_GIGA_MAC_VER_02:
3846 case RTL_GIGA_MAC_VER_03:
3847 rtl8169s_hw_phy_config(tp);
3849 case RTL_GIGA_MAC_VER_04:
3850 rtl8169sb_hw_phy_config(tp);
3852 case RTL_GIGA_MAC_VER_05:
3853 rtl8169scd_hw_phy_config(tp);
3855 case RTL_GIGA_MAC_VER_06:
3856 rtl8169sce_hw_phy_config(tp);
3858 case RTL_GIGA_MAC_VER_07:
3859 case RTL_GIGA_MAC_VER_08:
3860 case RTL_GIGA_MAC_VER_09:
3861 rtl8102e_hw_phy_config(tp);
3863 case RTL_GIGA_MAC_VER_11:
3864 rtl8168bb_hw_phy_config(tp);
3866 case RTL_GIGA_MAC_VER_12:
3867 rtl8168bef_hw_phy_config(tp);
3869 case RTL_GIGA_MAC_VER_17:
3870 rtl8168bef_hw_phy_config(tp);
3872 case RTL_GIGA_MAC_VER_18:
3873 rtl8168cp_1_hw_phy_config(tp);
3875 case RTL_GIGA_MAC_VER_19:
3876 rtl8168c_1_hw_phy_config(tp);
3878 case RTL_GIGA_MAC_VER_20:
3879 rtl8168c_2_hw_phy_config(tp);
3881 case RTL_GIGA_MAC_VER_21:
3882 rtl8168c_3_hw_phy_config(tp);
3884 case RTL_GIGA_MAC_VER_22:
3885 rtl8168c_4_hw_phy_config(tp);
3887 case RTL_GIGA_MAC_VER_23:
3888 case RTL_GIGA_MAC_VER_24:
3889 rtl8168cp_2_hw_phy_config(tp);
3891 case RTL_GIGA_MAC_VER_25:
3892 rtl8168d_1_hw_phy_config(tp);
3894 case RTL_GIGA_MAC_VER_26:
3895 rtl8168d_2_hw_phy_config(tp);
3897 case RTL_GIGA_MAC_VER_27:
3898 rtl8168d_3_hw_phy_config(tp);
3900 case RTL_GIGA_MAC_VER_28:
3901 rtl8168d_4_hw_phy_config(tp);
3903 case RTL_GIGA_MAC_VER_29:
3904 case RTL_GIGA_MAC_VER_30:
3905 rtl8105e_hw_phy_config(tp);
3907 case RTL_GIGA_MAC_VER_31:
3910 case RTL_GIGA_MAC_VER_32:
3911 case RTL_GIGA_MAC_VER_33:
3912 rtl8168e_1_hw_phy_config(tp);
3914 case RTL_GIGA_MAC_VER_34:
3915 rtl8168e_2_hw_phy_config(tp);
3917 case RTL_GIGA_MAC_VER_35:
3918 rtl8168f_1_hw_phy_config(tp);
3920 case RTL_GIGA_MAC_VER_36:
3921 rtl8168f_2_hw_phy_config(tp);
3924 case RTL_GIGA_MAC_VER_37:
3925 rtl8402_hw_phy_config(tp);
3928 case RTL_GIGA_MAC_VER_38:
3929 rtl8411_hw_phy_config(tp);
3932 case RTL_GIGA_MAC_VER_39:
3933 rtl8106e_hw_phy_config(tp);
3936 case RTL_GIGA_MAC_VER_40:
3937 rtl8168g_1_hw_phy_config(tp);
3939 case RTL_GIGA_MAC_VER_42:
3940 case RTL_GIGA_MAC_VER_43:
3941 case RTL_GIGA_MAC_VER_44:
3942 rtl8168g_2_hw_phy_config(tp);
3944 case RTL_GIGA_MAC_VER_45:
3945 case RTL_GIGA_MAC_VER_47:
3946 rtl8168h_1_hw_phy_config(tp);
3948 case RTL_GIGA_MAC_VER_46:
3949 case RTL_GIGA_MAC_VER_48:
3950 rtl8168h_2_hw_phy_config(tp);
3953 case RTL_GIGA_MAC_VER_49:
3954 rtl8168ep_1_hw_phy_config(tp);
3956 case RTL_GIGA_MAC_VER_50:
3957 case RTL_GIGA_MAC_VER_51:
3958 rtl8168ep_2_hw_phy_config(tp);
3961 case RTL_GIGA_MAC_VER_41:
3967 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3969 if (!test_and_set_bit(flag, tp->wk.flags))
3970 schedule_work(&tp->wk.work);
3973 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
3975 return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
3976 (RTL_R8(tp, PHYstatus) & TBI_Enable);
3979 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3981 rtl_hw_phy_config(dev);
3983 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3984 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3985 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
3986 netif_dbg(tp, drv, dev,
3987 "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3988 RTL_W8(tp, 0x82, 0x01);
3991 /* We may have called phy_speed_down before */
3992 phy_speed_up(dev->phydev);
3994 genphy_soft_reset(dev->phydev);
3996 /* It was reported that several chips end up with 10MBit/Half on a
3997 * 1GBit link after resuming from S3. For whatever reason the PHY on
3998 * these chips doesn't properly start a renegotiation when soft-reset.
3999 * Explicitly requesting a renegotiation fixes this.
4001 if (dev->phydev->autoneg == AUTONEG_ENABLE)
4002 phy_restart_aneg(dev->phydev);
4005 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
4009 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4011 RTL_W32(tp, MAC4, addr[4] | addr[5] << 8);
4014 RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
4017 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4018 rtl_rar_exgmac_set(tp, addr);
4020 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4022 rtl_unlock_work(tp);
4025 static int rtl_set_mac_address(struct net_device *dev, void *p)
4027 struct rtl8169_private *tp = netdev_priv(dev);
4028 struct device *d = tp_to_dev(tp);
4031 ret = eth_mac_addr(dev, p);
4035 pm_runtime_get_noresume(d);
4037 if (pm_runtime_active(d))
4038 rtl_rar_set(tp, dev->dev_addr);
4040 pm_runtime_put_noidle(d);
4045 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4047 if (!netif_running(dev))
4050 return phy_mii_ioctl(dev->phydev, ifr, cmd);
4053 static void rtl_init_mdio_ops(struct rtl8169_private *tp)
4055 struct mdio_ops *ops = &tp->mdio_ops;
4057 switch (tp->mac_version) {
4058 case RTL_GIGA_MAC_VER_27:
4059 ops->write = r8168dp_1_mdio_write;
4060 ops->read = r8168dp_1_mdio_read;
4062 case RTL_GIGA_MAC_VER_28:
4063 case RTL_GIGA_MAC_VER_31:
4064 ops->write = r8168dp_2_mdio_write;
4065 ops->read = r8168dp_2_mdio_read;
4067 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4068 ops->write = r8168g_mdio_write;
4069 ops->read = r8168g_mdio_read;
4072 ops->write = r8169_mdio_write;
4073 ops->read = r8169_mdio_read;
4078 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
4080 switch (tp->mac_version) {
4081 case RTL_GIGA_MAC_VER_25:
4082 case RTL_GIGA_MAC_VER_26:
4083 case RTL_GIGA_MAC_VER_29:
4084 case RTL_GIGA_MAC_VER_30:
4085 case RTL_GIGA_MAC_VER_32:
4086 case RTL_GIGA_MAC_VER_33:
4087 case RTL_GIGA_MAC_VER_34:
4088 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_51:
4089 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
4090 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
4097 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
4099 struct phy_device *phydev;
4101 if (!__rtl8169_get_wol(tp))
4104 /* phydev may not be attached to netdevice */
4105 phydev = mdiobus_get_phy(tp->mii_bus, 0);
4107 phy_speed_down(phydev, false);
4108 rtl_wol_suspend_quirk(tp);
4113 static void r8168_pll_power_down(struct rtl8169_private *tp)
4115 if (r8168_check_dash(tp))
4118 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4119 tp->mac_version == RTL_GIGA_MAC_VER_33)
4120 rtl_ephy_write(tp, 0x19, 0xff64);
4122 if (rtl_wol_pll_power_down(tp))
4125 switch (tp->mac_version) {
4126 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
4127 case RTL_GIGA_MAC_VER_37:
4128 case RTL_GIGA_MAC_VER_39:
4129 case RTL_GIGA_MAC_VER_43:
4130 case RTL_GIGA_MAC_VER_44:
4131 case RTL_GIGA_MAC_VER_45:
4132 case RTL_GIGA_MAC_VER_46:
4133 case RTL_GIGA_MAC_VER_47:
4134 case RTL_GIGA_MAC_VER_48:
4135 case RTL_GIGA_MAC_VER_50:
4136 case RTL_GIGA_MAC_VER_51:
4137 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
4139 case RTL_GIGA_MAC_VER_40:
4140 case RTL_GIGA_MAC_VER_41:
4141 case RTL_GIGA_MAC_VER_49:
4142 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
4143 0xfc000000, ERIAR_EXGMAC);
4144 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
4149 static void r8168_pll_power_up(struct rtl8169_private *tp)
4151 switch (tp->mac_version) {
4152 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
4153 case RTL_GIGA_MAC_VER_37:
4154 case RTL_GIGA_MAC_VER_39:
4155 case RTL_GIGA_MAC_VER_43:
4156 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);
4158 case RTL_GIGA_MAC_VER_44:
4159 case RTL_GIGA_MAC_VER_45:
4160 case RTL_GIGA_MAC_VER_46:
4161 case RTL_GIGA_MAC_VER_47:
4162 case RTL_GIGA_MAC_VER_48:
4163 case RTL_GIGA_MAC_VER_50:
4164 case RTL_GIGA_MAC_VER_51:
4165 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
4167 case RTL_GIGA_MAC_VER_40:
4168 case RTL_GIGA_MAC_VER_41:
4169 case RTL_GIGA_MAC_VER_49:
4170 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
4171 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
4172 0x00000000, ERIAR_EXGMAC);
4176 phy_resume(tp->dev->phydev);
4177 /* give MAC/PHY some time to resume */
4181 static void rtl_pll_power_down(struct rtl8169_private *tp)
4183 switch (tp->mac_version) {
4184 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4185 case RTL_GIGA_MAC_VER_13 ... RTL_GIGA_MAC_VER_15:
4188 r8168_pll_power_down(tp);
4192 static void rtl_pll_power_up(struct rtl8169_private *tp)
4194 switch (tp->mac_version) {
4195 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4196 case RTL_GIGA_MAC_VER_13 ... RTL_GIGA_MAC_VER_15:
4199 r8168_pll_power_up(tp);
4203 static void rtl_init_rxcfg(struct rtl8169_private *tp)
4205 switch (tp->mac_version) {
4206 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4207 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
4208 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4210 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
4211 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
4212 case RTL_GIGA_MAC_VER_38:
4213 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4215 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4216 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
4219 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
4224 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4226 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
4229 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4231 if (tp->jumbo_ops.enable) {
4232 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4233 tp->jumbo_ops.enable(tp);
4234 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4238 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4240 if (tp->jumbo_ops.disable) {
4241 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4242 tp->jumbo_ops.disable(tp);
4243 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4247 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4249 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4250 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
4251 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
4254 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4256 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4257 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
4258 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4261 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4263 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4266 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4268 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4271 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4273 RTL_W8(tp, MaxTxPacketSize, 0x3f);
4274 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4275 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
4276 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
4279 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4281 RTL_W8(tp, MaxTxPacketSize, 0x0c);
4282 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4283 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
4284 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4287 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4289 rtl_tx_performance_tweak(tp,
4290 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
4293 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4295 rtl_tx_performance_tweak(tp,
4296 PCI_EXP_DEVCTL_READRQ_4096B | PCI_EXP_DEVCTL_NOSNOOP_EN);
4299 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4301 r8168b_0_hw_jumbo_enable(tp);
4303 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
4306 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4308 r8168b_0_hw_jumbo_disable(tp);
4310 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4313 static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
4315 struct jumbo_ops *ops = &tp->jumbo_ops;
4317 switch (tp->mac_version) {
4318 case RTL_GIGA_MAC_VER_11:
4319 ops->disable = r8168b_0_hw_jumbo_disable;
4320 ops->enable = r8168b_0_hw_jumbo_enable;
4322 case RTL_GIGA_MAC_VER_12:
4323 case RTL_GIGA_MAC_VER_17:
4324 ops->disable = r8168b_1_hw_jumbo_disable;
4325 ops->enable = r8168b_1_hw_jumbo_enable;
4327 case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
4328 case RTL_GIGA_MAC_VER_19:
4329 case RTL_GIGA_MAC_VER_20:
4330 case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
4331 case RTL_GIGA_MAC_VER_22:
4332 case RTL_GIGA_MAC_VER_23:
4333 case RTL_GIGA_MAC_VER_24:
4334 case RTL_GIGA_MAC_VER_25:
4335 case RTL_GIGA_MAC_VER_26:
4336 ops->disable = r8168c_hw_jumbo_disable;
4337 ops->enable = r8168c_hw_jumbo_enable;
4339 case RTL_GIGA_MAC_VER_27:
4340 case RTL_GIGA_MAC_VER_28:
4341 ops->disable = r8168dp_hw_jumbo_disable;
4342 ops->enable = r8168dp_hw_jumbo_enable;
4344 case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
4345 case RTL_GIGA_MAC_VER_32:
4346 case RTL_GIGA_MAC_VER_33:
4347 case RTL_GIGA_MAC_VER_34:
4348 ops->disable = r8168e_hw_jumbo_disable;
4349 ops->enable = r8168e_hw_jumbo_enable;
4353 * No action needed for jumbo frames with 8169.
4354 * No jumbo for 810x at all.
4356 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4358 ops->disable = NULL;
4364 DECLARE_RTL_COND(rtl_chipcmd_cond)
4366 return RTL_R8(tp, ChipCmd) & CmdReset;
4369 static void rtl_hw_reset(struct rtl8169_private *tp)
4371 RTL_W8(tp, ChipCmd, CmdReset);
4373 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
4376 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
4378 struct rtl_fw *rtl_fw;
4382 name = rtl_lookup_firmware_name(tp);
4384 goto out_no_firmware;
4386 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4390 rc = request_firmware(&rtl_fw->fw, name, tp_to_dev(tp));
4394 rc = rtl_check_firmware(tp, rtl_fw);
4396 goto err_release_firmware;
4398 tp->rtl_fw = rtl_fw;
4402 err_release_firmware:
4403 release_firmware(rtl_fw->fw);
4407 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4414 static void rtl_request_firmware(struct rtl8169_private *tp)
4416 if (IS_ERR(tp->rtl_fw))
4417 rtl_request_uncached_firmware(tp);
4420 static void rtl_rx_close(struct rtl8169_private *tp)
4422 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
4425 DECLARE_RTL_COND(rtl_npq_cond)
4427 return RTL_R8(tp, TxPoll) & NPQ;
4430 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4432 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
4435 static void rtl8169_hw_reset(struct rtl8169_private *tp)
4437 /* Disable interrupts */
4438 rtl8169_irq_mask_and_ack(tp);
4442 switch (tp->mac_version) {
4443 case RTL_GIGA_MAC_VER_27:
4444 case RTL_GIGA_MAC_VER_28:
4445 case RTL_GIGA_MAC_VER_31:
4446 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
4448 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
4449 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4450 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4451 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
4454 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4462 static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
4464 u32 val = TX_DMA_BURST << TxDMAShift |
4465 InterFrameGap << TxInterFrameGapShift;
4467 if (tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
4468 tp->mac_version != RTL_GIGA_MAC_VER_39)
4469 val |= TXCFG_AUTO_FIFO;
4471 RTL_W32(tp, TxConfig, val);
4474 static void rtl_set_rx_max_size(struct rtl8169_private *tp)
4476 /* Low hurts. Let's disable the filtering. */
4477 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
4480 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
4483 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4484 * register to be written before TxDescAddrLow to work.
4485 * Switching from MMIO to I/O access fixes the issue as well.
4487 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4488 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4489 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4490 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4493 static void rtl8169_set_magic_reg(struct rtl8169_private *tp, unsigned mac_version)
4497 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4499 else if (tp->mac_version == RTL_GIGA_MAC_VER_06)
4504 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz)
4507 RTL_W32(tp, 0x7c, val);
4510 static void rtl_set_rx_mode(struct net_device *dev)
4512 struct rtl8169_private *tp = netdev_priv(dev);
4513 u32 mc_filter[2]; /* Multicast hash filter */
4517 if (dev->flags & IFF_PROMISC) {
4518 /* Unconditionally log net taps. */
4519 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4521 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4523 mc_filter[1] = mc_filter[0] = 0xffffffff;
4524 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4525 (dev->flags & IFF_ALLMULTI)) {
4526 /* Too many to filter perfectly -- accept all multicasts. */
4527 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4528 mc_filter[1] = mc_filter[0] = 0xffffffff;
4530 struct netdev_hw_addr *ha;
4532 rx_mode = AcceptBroadcast | AcceptMyPhys;
4533 mc_filter[1] = mc_filter[0] = 0;
4534 netdev_for_each_mc_addr(ha, dev) {
4535 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4536 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4537 rx_mode |= AcceptMulticast;
4541 if (dev->features & NETIF_F_RXALL)
4542 rx_mode |= (AcceptErr | AcceptRunt);
4544 tmp = (RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4546 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4547 u32 data = mc_filter[0];
4549 mc_filter[0] = swab32(mc_filter[1]);
4550 mc_filter[1] = swab32(data);
4553 if (tp->mac_version == RTL_GIGA_MAC_VER_35)
4554 mc_filter[1] = mc_filter[0] = 0xffffffff;
4556 RTL_W32(tp, MAR0 + 4, mc_filter[1]);
4557 RTL_W32(tp, MAR0 + 0, mc_filter[0]);
4559 RTL_W32(tp, RxConfig, tmp);
4562 static void rtl_hw_start(struct rtl8169_private *tp)
4564 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4568 rtl_set_rx_max_size(tp);
4569 rtl_set_rx_tx_desc_registers(tp);
4570 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4572 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4573 RTL_R8(tp, IntrMask);
4574 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
4576 rtl_set_tx_config_registers(tp);
4578 rtl_set_rx_mode(tp->dev);
4579 /* no early-rx interrupts */
4580 RTL_W16(tp, MultiIntr, RTL_R16(tp, MultiIntr) & 0xf000);
4584 static void rtl_hw_start_8169(struct rtl8169_private *tp)
4586 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4587 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4589 RTL_W8(tp, EarlyTxThres, NoEarlyTx);
4591 tp->cp_cmd |= PCIMulRW;
4593 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4594 tp->mac_version == RTL_GIGA_MAC_VER_03) {
4595 netif_dbg(tp, drv, tp->dev,
4596 "Set MAC Reg C+CR Offset 0xe0. Bit 3 and Bit 14 MUST be 1\n");
4597 tp->cp_cmd |= (1 << 14);
4600 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4602 rtl8169_set_magic_reg(tp, tp->mac_version);
4605 * Undocumented corner. Supposedly:
4606 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4608 RTL_W16(tp, IntrMitigate, 0x0000);
4610 RTL_W32(tp, RxMissed, 0);
4613 DECLARE_RTL_COND(rtl_csiar_cond)
4615 return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
4618 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
4620 u32 func = PCI_FUNC(tp->pci_dev->devfn);
4622 RTL_W32(tp, CSIDR, value);
4623 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4624 CSIAR_BYTE_ENABLE | func << 16);
4626 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4629 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
4631 u32 func = PCI_FUNC(tp->pci_dev->devfn);
4633 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
4636 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4637 RTL_R32(tp, CSIDR) : ~0;
4640 static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val)
4642 struct pci_dev *pdev = tp->pci_dev;
4645 /* According to Realtek the value at config space address 0x070f
4646 * controls the L0s/L1 entrance latency. We try standard ECAM access
4647 * first and if it fails fall back to CSI.
4649 if (pdev->cfg_size > 0x070f &&
4650 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
4653 netdev_notice_once(tp->dev,
4654 "No native access to PCI extended config space, falling back to CSI\n");
4655 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4656 rtl_csi_write(tp, 0x070c, csi | val << 24);
4659 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
4661 rtl_csi_access_enable(tp, 0x27);
4665 unsigned int offset;
4670 static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
4676 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4677 rtl_ephy_write(tp, e->offset, w);
4682 static void rtl_disable_clock_request(struct rtl8169_private *tp)
4684 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
4685 PCI_EXP_LNKCTL_CLKREQ_EN);
4688 static void rtl_enable_clock_request(struct rtl8169_private *tp)
4690 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
4691 PCI_EXP_LNKCTL_CLKREQ_EN);
4694 static void rtl_pcie_state_l2l3_enable(struct rtl8169_private *tp, bool enable)
4698 data = RTL_R8(tp, Config3);
4703 data &= ~Rdy_to_L23;
4705 RTL_W8(tp, Config3, data);
4708 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
4711 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);
4712 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);
4714 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
4715 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
4721 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
4723 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4725 tp->cp_cmd &= CPCMD_QUIRK_MASK;
4726 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4728 if (tp->dev->mtu <= ETH_DATA_LEN) {
4729 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B |
4730 PCI_EXP_DEVCTL_NOSNOOP_EN);
4734 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
4736 rtl_hw_start_8168bb(tp);
4738 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4740 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4743 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
4745 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
4747 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4749 if (tp->dev->mtu <= ETH_DATA_LEN)
4750 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4752 rtl_disable_clock_request(tp);
4754 tp->cp_cmd &= CPCMD_QUIRK_MASK;
4755 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4758 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
4760 static const struct ephy_info e_info_8168cp[] = {
4761 { 0x01, 0, 0x0001 },
4762 { 0x02, 0x0800, 0x1000 },
4763 { 0x03, 0, 0x0042 },
4764 { 0x06, 0x0080, 0x0000 },
4768 rtl_set_def_aspm_entry_latency(tp);
4770 rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4772 __rtl_hw_start_8168cp(tp);
4775 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
4777 rtl_set_def_aspm_entry_latency(tp);
4779 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4781 if (tp->dev->mtu <= ETH_DATA_LEN)
4782 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4784 tp->cp_cmd &= CPCMD_QUIRK_MASK;
4785 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4788 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
4790 rtl_set_def_aspm_entry_latency(tp);
4792 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4795 RTL_W8(tp, DBG_REG, 0x20);
4797 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4799 if (tp->dev->mtu <= ETH_DATA_LEN)
4800 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4802 tp->cp_cmd &= CPCMD_QUIRK_MASK;
4803 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4806 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
4808 static const struct ephy_info e_info_8168c_1[] = {
4809 { 0x02, 0x0800, 0x1000 },
4810 { 0x03, 0, 0x0002 },
4811 { 0x06, 0x0080, 0x0000 }
4814 rtl_set_def_aspm_entry_latency(tp);
4816 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4818 rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4820 __rtl_hw_start_8168cp(tp);
4823 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
4825 static const struct ephy_info e_info_8168c_2[] = {
4826 { 0x01, 0, 0x0001 },
4827 { 0x03, 0x0400, 0x0220 }
4830 rtl_set_def_aspm_entry_latency(tp);
4832 rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4834 __rtl_hw_start_8168cp(tp);
4837 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
4839 rtl_hw_start_8168c_2(tp);
4842 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
4844 rtl_set_def_aspm_entry_latency(tp);
4846 __rtl_hw_start_8168cp(tp);
4849 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
4851 rtl_set_def_aspm_entry_latency(tp);
4853 rtl_disable_clock_request(tp);
4855 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4857 if (tp->dev->mtu <= ETH_DATA_LEN)
4858 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4860 tp->cp_cmd &= CPCMD_QUIRK_MASK;
4861 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4864 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4866 rtl_set_def_aspm_entry_latency(tp);
4868 if (tp->dev->mtu <= ETH_DATA_LEN)
4869 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4871 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4873 rtl_disable_clock_request(tp);
4876 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
4878 static const struct ephy_info e_info_8168d_4[] = {
4879 { 0x0b, 0x0000, 0x0048 },
4880 { 0x19, 0x0020, 0x0050 },
4881 { 0x0c, 0x0100, 0x0020 }
4884 rtl_set_def_aspm_entry_latency(tp);
4886 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4888 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4890 rtl_ephy_init(tp, e_info_8168d_4, ARRAY_SIZE(e_info_8168d_4));
4892 rtl_enable_clock_request(tp);
4895 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
4897 static const struct ephy_info e_info_8168e_1[] = {
4898 { 0x00, 0x0200, 0x0100 },
4899 { 0x00, 0x0000, 0x0004 },
4900 { 0x06, 0x0002, 0x0001 },
4901 { 0x06, 0x0000, 0x0030 },
4902 { 0x07, 0x0000, 0x2000 },
4903 { 0x00, 0x0000, 0x0020 },
4904 { 0x03, 0x5800, 0x2000 },
4905 { 0x03, 0x0000, 0x0001 },
4906 { 0x01, 0x0800, 0x1000 },
4907 { 0x07, 0x0000, 0x4000 },
4908 { 0x1e, 0x0000, 0x2000 },
4909 { 0x19, 0xffff, 0xfe6c },
4910 { 0x0a, 0x0000, 0x0040 }
4913 rtl_set_def_aspm_entry_latency(tp);
4915 rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
4917 if (tp->dev->mtu <= ETH_DATA_LEN)
4918 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4920 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4922 rtl_disable_clock_request(tp);
4924 /* Reset tx FIFO pointer */
4925 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
4926 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
4928 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4931 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
4933 static const struct ephy_info e_info_8168e_2[] = {
4934 { 0x09, 0x0000, 0x0080 },
4935 { 0x19, 0x0000, 0x0224 }
4938 rtl_set_def_aspm_entry_latency(tp);
4940 rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
4942 if (tp->dev->mtu <= ETH_DATA_LEN)
4943 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4945 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4946 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4947 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4948 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4949 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4950 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
4951 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4952 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
4954 RTL_W8(tp, MaxTxPacketSize, EarlySize);
4956 rtl_disable_clock_request(tp);
4958 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
4960 /* Adjust EEE LED frequency */
4961 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
4963 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
4964 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
4965 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4967 rtl_hw_aspm_clkreq_enable(tp, true);
4970 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
4972 rtl_set_def_aspm_entry_latency(tp);
4974 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4976 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4977 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4978 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4979 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4980 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
4981 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
4982 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4983 rtl_w0w1_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4984 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4985 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
4987 RTL_W8(tp, MaxTxPacketSize, EarlySize);
4989 rtl_disable_clock_request(tp);
4991 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
4992 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
4993 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
4994 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4997 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
4999 static const struct ephy_info e_info_8168f_1[] = {
5000 { 0x06, 0x00c0, 0x0020 },
5001 { 0x08, 0x0001, 0x0002 },
5002 { 0x09, 0x0000, 0x0080 },
5003 { 0x19, 0x0000, 0x0224 }
5006 rtl_hw_start_8168f(tp);
5008 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5010 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5012 /* Adjust EEE LED frequency */
5013 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5016 static void rtl_hw_start_8411(struct rtl8169_private *tp)
5018 static const struct ephy_info e_info_8168f_1[] = {
5019 { 0x06, 0x00c0, 0x0020 },
5020 { 0x0f, 0xffff, 0x5200 },
5021 { 0x1e, 0x0000, 0x4000 },
5022 { 0x19, 0x0000, 0x0224 }
5025 rtl_hw_start_8168f(tp);
5026 rtl_pcie_state_l2l3_enable(tp, false);
5028 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5030 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
5033 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
5035 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
5036 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5037 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5038 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5040 rtl_set_def_aspm_entry_latency(tp);
5042 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5044 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5045 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5046 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
5048 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5049 RTL_W8(tp, MaxTxPacketSize, EarlySize);
5051 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5052 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5054 /* Adjust EEE LED frequency */
5055 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5057 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5058 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
5060 rtl_pcie_state_l2l3_enable(tp, false);
5063 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
5065 static const struct ephy_info e_info_8168g_1[] = {
5066 { 0x00, 0x0000, 0x0008 },
5067 { 0x0c, 0x37d0, 0x0820 },
5068 { 0x1e, 0x0000, 0x0001 },
5069 { 0x19, 0x8000, 0x0000 }
5072 rtl_hw_start_8168g(tp);
5074 /* disable aspm and clock request before access ephy */
5075 rtl_hw_aspm_clkreq_enable(tp, false);
5076 rtl_ephy_init(tp, e_info_8168g_1, ARRAY_SIZE(e_info_8168g_1));
5077 rtl_hw_aspm_clkreq_enable(tp, true);
5080 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
5082 static const struct ephy_info e_info_8168g_2[] = {
5083 { 0x00, 0x0000, 0x0008 },
5084 { 0x0c, 0x3df0, 0x0200 },
5085 { 0x19, 0xffff, 0xfc00 },
5086 { 0x1e, 0xffff, 0x20eb }
5089 rtl_hw_start_8168g(tp);
5091 /* disable aspm and clock request before access ephy */
5092 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
5093 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
5094 rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
5097 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
5099 static const struct ephy_info e_info_8411_2[] = {
5100 { 0x00, 0x0000, 0x0008 },
5101 { 0x0c, 0x3df0, 0x0200 },
5102 { 0x0f, 0xffff, 0x5200 },
5103 { 0x19, 0x0020, 0x0000 },
5104 { 0x1e, 0x0000, 0x2000 }
5107 rtl_hw_start_8168g(tp);
5109 /* disable aspm and clock request before access ephy */
5110 rtl_hw_aspm_clkreq_enable(tp, false);
5111 rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
5112 rtl_hw_aspm_clkreq_enable(tp, true);
5115 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
5119 static const struct ephy_info e_info_8168h_1[] = {
5120 { 0x1e, 0x0800, 0x0001 },
5121 { 0x1d, 0x0000, 0x0800 },
5122 { 0x05, 0xffff, 0x2089 },
5123 { 0x06, 0xffff, 0x5881 },
5124 { 0x04, 0xffff, 0x154a },
5125 { 0x01, 0xffff, 0x068b }
5128 /* disable aspm and clock request before access ephy */
5129 rtl_hw_aspm_clkreq_enable(tp, false);
5130 rtl_ephy_init(tp, e_info_8168h_1, ARRAY_SIZE(e_info_8168h_1));
5132 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
5133 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5134 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5135 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5137 rtl_set_def_aspm_entry_latency(tp);
5139 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5141 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5142 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5144 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_1111, 0x0010, 0x00, ERIAR_EXGMAC);
5146 rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f00, 0x00, ERIAR_EXGMAC);
5148 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
5150 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5151 RTL_W8(tp, MaxTxPacketSize, EarlySize);
5153 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5154 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5156 /* Adjust EEE LED frequency */
5157 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5159 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5160 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5162 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
5164 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
5166 rtl_pcie_state_l2l3_enable(tp, false);
5168 rtl_writephy(tp, 0x1f, 0x0c42);
5169 rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
5170 rtl_writephy(tp, 0x1f, 0x0000);
5171 if (rg_saw_cnt > 0) {
5174 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
5175 sw_cnt_1ms_ini &= 0x0fff;
5176 data = r8168_mac_ocp_read(tp, 0xd412);
5178 data |= sw_cnt_1ms_ini;
5179 r8168_mac_ocp_write(tp, 0xd412, data);
5182 data = r8168_mac_ocp_read(tp, 0xe056);
5185 r8168_mac_ocp_write(tp, 0xe056, data);
5187 data = r8168_mac_ocp_read(tp, 0xe052);
5190 r8168_mac_ocp_write(tp, 0xe052, data);
5192 data = r8168_mac_ocp_read(tp, 0xe0d6);
5195 r8168_mac_ocp_write(tp, 0xe0d6, data);
5197 data = r8168_mac_ocp_read(tp, 0xd420);
5200 r8168_mac_ocp_write(tp, 0xd420, data);
5202 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
5203 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
5204 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
5205 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
5207 rtl_hw_aspm_clkreq_enable(tp, true);
5210 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
5212 rtl8168ep_stop_cmac(tp);
5214 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
5215 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x2f, ERIAR_EXGMAC);
5216 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x5f, ERIAR_EXGMAC);
5217 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5219 rtl_set_def_aspm_entry_latency(tp);
5221 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5223 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5224 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5226 rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f80, 0x00, ERIAR_EXGMAC);
5228 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
5230 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5231 RTL_W8(tp, MaxTxPacketSize, EarlySize);
5233 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5234 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5236 /* Adjust EEE LED frequency */
5237 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5239 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5241 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
5243 rtl_pcie_state_l2l3_enable(tp, false);
5246 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
5248 static const struct ephy_info e_info_8168ep_1[] = {
5249 { 0x00, 0xffff, 0x10ab },
5250 { 0x06, 0xffff, 0xf030 },
5251 { 0x08, 0xffff, 0x2006 },
5252 { 0x0d, 0xffff, 0x1666 },
5253 { 0x0c, 0x3ff0, 0x0000 }
5256 /* disable aspm and clock request before access ephy */
5257 rtl_hw_aspm_clkreq_enable(tp, false);
5258 rtl_ephy_init(tp, e_info_8168ep_1, ARRAY_SIZE(e_info_8168ep_1));
5260 rtl_hw_start_8168ep(tp);
5262 rtl_hw_aspm_clkreq_enable(tp, true);
5265 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
5267 static const struct ephy_info e_info_8168ep_2[] = {
5268 { 0x00, 0xffff, 0x10a3 },
5269 { 0x19, 0xffff, 0xfc00 },
5270 { 0x1e, 0xffff, 0x20ea }
5273 /* disable aspm and clock request before access ephy */
5274 rtl_hw_aspm_clkreq_enable(tp, false);
5275 rtl_ephy_init(tp, e_info_8168ep_2, ARRAY_SIZE(e_info_8168ep_2));
5277 rtl_hw_start_8168ep(tp);
5279 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5280 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5282 rtl_hw_aspm_clkreq_enable(tp, true);
5285 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
5288 static const struct ephy_info e_info_8168ep_3[] = {
5289 { 0x00, 0xffff, 0x10a3 },
5290 { 0x19, 0xffff, 0x7c00 },
5291 { 0x1e, 0xffff, 0x20eb },
5292 { 0x0d, 0xffff, 0x1666 }
5295 /* disable aspm and clock request before access ephy */
5296 rtl_hw_aspm_clkreq_enable(tp, false);
5297 rtl_ephy_init(tp, e_info_8168ep_3, ARRAY_SIZE(e_info_8168ep_3));
5299 rtl_hw_start_8168ep(tp);
5301 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5302 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5304 data = r8168_mac_ocp_read(tp, 0xd3e2);
5307 r8168_mac_ocp_write(tp, 0xd3e2, data);
5309 data = r8168_mac_ocp_read(tp, 0xd3e4);
5311 r8168_mac_ocp_write(tp, 0xd3e4, data);
5313 data = r8168_mac_ocp_read(tp, 0xe860);
5315 r8168_mac_ocp_write(tp, 0xe860, data);
5317 rtl_hw_aspm_clkreq_enable(tp, true);
5320 static void rtl_hw_start_8168(struct rtl8169_private *tp)
5322 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5324 tp->cp_cmd &= ~INTT_MASK;
5325 tp->cp_cmd |= PktCntrDisable | INTT_1;
5326 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5328 RTL_W16(tp, IntrMitigate, 0x5151);
5330 /* Work around for RxFIFO overflow. */
5331 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
5332 tp->irq_mask |= RxFIFOOver;
5333 tp->irq_mask &= ~RxOverflow;
5336 switch (tp->mac_version) {
5337 case RTL_GIGA_MAC_VER_11:
5338 rtl_hw_start_8168bb(tp);
5341 case RTL_GIGA_MAC_VER_12:
5342 case RTL_GIGA_MAC_VER_17:
5343 rtl_hw_start_8168bef(tp);
5346 case RTL_GIGA_MAC_VER_18:
5347 rtl_hw_start_8168cp_1(tp);
5350 case RTL_GIGA_MAC_VER_19:
5351 rtl_hw_start_8168c_1(tp);
5354 case RTL_GIGA_MAC_VER_20:
5355 rtl_hw_start_8168c_2(tp);
5358 case RTL_GIGA_MAC_VER_21:
5359 rtl_hw_start_8168c_3(tp);
5362 case RTL_GIGA_MAC_VER_22:
5363 rtl_hw_start_8168c_4(tp);
5366 case RTL_GIGA_MAC_VER_23:
5367 rtl_hw_start_8168cp_2(tp);
5370 case RTL_GIGA_MAC_VER_24:
5371 rtl_hw_start_8168cp_3(tp);
5374 case RTL_GIGA_MAC_VER_25:
5375 case RTL_GIGA_MAC_VER_26:
5376 case RTL_GIGA_MAC_VER_27:
5377 rtl_hw_start_8168d(tp);
5380 case RTL_GIGA_MAC_VER_28:
5381 rtl_hw_start_8168d_4(tp);
5384 case RTL_GIGA_MAC_VER_31:
5385 rtl_hw_start_8168dp(tp);
5388 case RTL_GIGA_MAC_VER_32:
5389 case RTL_GIGA_MAC_VER_33:
5390 rtl_hw_start_8168e_1(tp);
5392 case RTL_GIGA_MAC_VER_34:
5393 rtl_hw_start_8168e_2(tp);
5396 case RTL_GIGA_MAC_VER_35:
5397 case RTL_GIGA_MAC_VER_36:
5398 rtl_hw_start_8168f_1(tp);
5401 case RTL_GIGA_MAC_VER_38:
5402 rtl_hw_start_8411(tp);
5405 case RTL_GIGA_MAC_VER_40:
5406 case RTL_GIGA_MAC_VER_41:
5407 rtl_hw_start_8168g_1(tp);
5409 case RTL_GIGA_MAC_VER_42:
5410 rtl_hw_start_8168g_2(tp);
5413 case RTL_GIGA_MAC_VER_44:
5414 rtl_hw_start_8411_2(tp);
5417 case RTL_GIGA_MAC_VER_45:
5418 case RTL_GIGA_MAC_VER_46:
5419 rtl_hw_start_8168h_1(tp);
5422 case RTL_GIGA_MAC_VER_49:
5423 rtl_hw_start_8168ep_1(tp);
5426 case RTL_GIGA_MAC_VER_50:
5427 rtl_hw_start_8168ep_2(tp);
5430 case RTL_GIGA_MAC_VER_51:
5431 rtl_hw_start_8168ep_3(tp);
5435 netif_err(tp, drv, tp->dev,
5436 "unknown chipset (mac_version = %d)\n",
5442 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
5444 static const struct ephy_info e_info_8102e_1[] = {
5445 { 0x01, 0, 0x6e65 },
5446 { 0x02, 0, 0x091f },
5447 { 0x03, 0, 0xc2f9 },
5448 { 0x06, 0, 0xafb5 },
5449 { 0x07, 0, 0x0e00 },
5450 { 0x19, 0, 0xec80 },
5451 { 0x01, 0, 0x2e65 },
5456 rtl_set_def_aspm_entry_latency(tp);
5458 RTL_W8(tp, DBG_REG, FIX_NAK_1);
5460 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5463 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5464 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5466 cfg1 = RTL_R8(tp, Config1);
5467 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5468 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
5470 rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
5473 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
5475 rtl_set_def_aspm_entry_latency(tp);
5477 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5479 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
5480 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5483 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
5485 rtl_hw_start_8102e_2(tp);
5487 rtl_ephy_write(tp, 0x03, 0xc2f9);
5490 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5492 static const struct ephy_info e_info_8105e_1[] = {
5493 { 0x07, 0, 0x4000 },
5494 { 0x19, 0, 0x0200 },
5495 { 0x19, 0, 0x0020 },
5496 { 0x1e, 0, 0x2000 },
5497 { 0x03, 0, 0x0001 },
5498 { 0x19, 0, 0x0100 },
5499 { 0x19, 0, 0x0004 },
5503 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5504 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5506 /* Disable Early Tally Counter */
5507 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
5509 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5510 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5512 rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
5514 rtl_pcie_state_l2l3_enable(tp, false);
5517 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5519 rtl_hw_start_8105e_1(tp);
5520 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5523 static void rtl_hw_start_8402(struct rtl8169_private *tp)
5525 static const struct ephy_info e_info_8402[] = {
5526 { 0x19, 0xffff, 0xff64 },
5530 rtl_set_def_aspm_entry_latency(tp);
5532 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5533 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5535 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5537 rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
5539 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5541 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
5542 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
5543 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5544 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5545 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5546 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5547 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
5549 rtl_pcie_state_l2l3_enable(tp, false);
5552 static void rtl_hw_start_8106(struct rtl8169_private *tp)
5554 rtl_hw_aspm_clkreq_enable(tp, false);
5556 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5557 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5559 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5560 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5561 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5563 rtl_pcie_state_l2l3_enable(tp, false);
5564 rtl_hw_aspm_clkreq_enable(tp, true);
5567 static void rtl_hw_start_8101(struct rtl8169_private *tp)
5569 if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
5570 tp->irq_mask &= ~RxFIFOOver;
5572 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
5573 tp->mac_version == RTL_GIGA_MAC_VER_16)
5574 pcie_capability_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
5575 PCI_EXP_DEVCTL_NOSNOOP_EN);
5577 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5579 tp->cp_cmd &= CPCMD_QUIRK_MASK;
5580 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5582 switch (tp->mac_version) {
5583 case RTL_GIGA_MAC_VER_07:
5584 rtl_hw_start_8102e_1(tp);
5587 case RTL_GIGA_MAC_VER_08:
5588 rtl_hw_start_8102e_3(tp);
5591 case RTL_GIGA_MAC_VER_09:
5592 rtl_hw_start_8102e_2(tp);
5595 case RTL_GIGA_MAC_VER_29:
5596 rtl_hw_start_8105e_1(tp);
5598 case RTL_GIGA_MAC_VER_30:
5599 rtl_hw_start_8105e_2(tp);
5602 case RTL_GIGA_MAC_VER_37:
5603 rtl_hw_start_8402(tp);
5606 case RTL_GIGA_MAC_VER_39:
5607 rtl_hw_start_8106(tp);
5609 case RTL_GIGA_MAC_VER_43:
5610 rtl_hw_start_8168g_2(tp);
5612 case RTL_GIGA_MAC_VER_47:
5613 case RTL_GIGA_MAC_VER_48:
5614 rtl_hw_start_8168h_1(tp);
5618 RTL_W16(tp, IntrMitigate, 0x0000);
5621 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5623 struct rtl8169_private *tp = netdev_priv(dev);
5625 if (new_mtu > ETH_DATA_LEN)
5626 rtl_hw_jumbo_enable(tp);
5628 rtl_hw_jumbo_disable(tp);
5631 netdev_update_features(dev);
5636 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5638 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
5639 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5642 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5643 void **data_buff, struct RxDesc *desc)
5645 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr),
5646 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
5650 rtl8169_make_unusable_by_asic(desc);
5653 static inline void rtl8169_mark_to_asic(struct RxDesc *desc)
5655 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5657 /* Force memory writes to complete before releasing descriptor */
5660 desc->opts1 = cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE);
5663 static inline void *rtl8169_align(void *data)
5665 return (void *)ALIGN((long)data, 16);
5668 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5669 struct RxDesc *desc)
5673 struct device *d = tp_to_dev(tp);
5674 int node = dev_to_node(d);
5676 data = kmalloc_node(R8169_RX_BUF_SIZE, GFP_KERNEL, node);
5680 if (rtl8169_align(data) != data) {
5682 data = kmalloc_node(R8169_RX_BUF_SIZE + 15, GFP_KERNEL, node);
5687 mapping = dma_map_single(d, rtl8169_align(data), R8169_RX_BUF_SIZE,
5689 if (unlikely(dma_mapping_error(d, mapping))) {
5690 if (net_ratelimit())
5691 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
5695 desc->addr = cpu_to_le64(mapping);
5696 rtl8169_mark_to_asic(desc);
5704 static void rtl8169_rx_clear(struct rtl8169_private *tp)
5708 for (i = 0; i < NUM_RX_DESC; i++) {
5709 if (tp->Rx_databuff[i]) {
5710 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
5711 tp->RxDescArray + i);
5716 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
5718 desc->opts1 |= cpu_to_le32(RingEnd);
5721 static int rtl8169_rx_fill(struct rtl8169_private *tp)
5725 for (i = 0; i < NUM_RX_DESC; i++) {
5728 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
5730 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
5733 tp->Rx_databuff[i] = data;
5736 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5740 rtl8169_rx_clear(tp);
5744 static int rtl8169_init_ring(struct rtl8169_private *tp)
5746 rtl8169_init_ring_indexes(tp);
5748 memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
5749 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
5751 return rtl8169_rx_fill(tp);
5754 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
5755 struct TxDesc *desc)
5757 unsigned int len = tx_skb->len;
5759 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5767 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5772 for (i = 0; i < n; i++) {
5773 unsigned int entry = (start + i) % NUM_TX_DESC;
5774 struct ring_info *tx_skb = tp->tx_skb + entry;
5775 unsigned int len = tx_skb->len;
5778 struct sk_buff *skb = tx_skb->skb;
5780 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
5781 tp->TxDescArray + entry);
5783 dev_consume_skb_any(skb);
5790 static void rtl8169_tx_clear(struct rtl8169_private *tp)
5792 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
5793 tp->cur_tx = tp->dirty_tx = 0;
5794 netdev_reset_queue(tp->dev);
5797 static void rtl_reset_work(struct rtl8169_private *tp)
5799 struct net_device *dev = tp->dev;
5802 napi_disable(&tp->napi);
5803 netif_stop_queue(dev);
5806 rtl8169_hw_reset(tp);
5808 for (i = 0; i < NUM_RX_DESC; i++)
5809 rtl8169_mark_to_asic(tp->RxDescArray + i);
5811 rtl8169_tx_clear(tp);
5812 rtl8169_init_ring_indexes(tp);
5814 napi_enable(&tp->napi);
5816 netif_wake_queue(dev);
5819 static void rtl8169_tx_timeout(struct net_device *dev)
5821 struct rtl8169_private *tp = netdev_priv(dev);
5823 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5826 static __le32 rtl8169_get_txd_opts1(u32 opts0, u32 len, unsigned int entry)
5828 u32 status = opts0 | len;
5830 if (entry == NUM_TX_DESC - 1)
5833 return cpu_to_le32(status);
5836 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5839 struct skb_shared_info *info = skb_shinfo(skb);
5840 unsigned int cur_frag, entry;
5841 struct TxDesc *uninitialized_var(txd);
5842 struct device *d = tp_to_dev(tp);
5845 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5846 const skb_frag_t *frag = info->frags + cur_frag;
5851 entry = (entry + 1) % NUM_TX_DESC;
5853 txd = tp->TxDescArray + entry;
5854 len = skb_frag_size(frag);
5855 addr = skb_frag_address(frag);
5856 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5857 if (unlikely(dma_mapping_error(d, mapping))) {
5858 if (net_ratelimit())
5859 netif_err(tp, drv, tp->dev,
5860 "Failed to map TX fragments DMA!\n");
5864 txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry);
5865 txd->opts2 = cpu_to_le32(opts[1]);
5866 txd->addr = cpu_to_le64(mapping);
5868 tp->tx_skb[entry].len = len;
5872 tp->tx_skb[entry].skb = skb;
5873 txd->opts1 |= cpu_to_le32(LastFrag);
5879 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5883 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
5885 return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
5888 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5889 struct net_device *dev);
5890 /* r8169_csum_workaround()
5891 * The hw limites the value the transport offset. When the offset is out of the
5892 * range, calculate the checksum by sw.
5894 static void r8169_csum_workaround(struct rtl8169_private *tp,
5895 struct sk_buff *skb)
5897 if (skb_shinfo(skb)->gso_size) {
5898 netdev_features_t features = tp->dev->features;
5899 struct sk_buff *segs, *nskb;
5901 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
5902 segs = skb_gso_segment(skb, features);
5903 if (IS_ERR(segs) || !segs)
5910 rtl8169_start_xmit(nskb, tp->dev);
5913 dev_consume_skb_any(skb);
5914 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5915 if (skb_checksum_help(skb) < 0)
5918 rtl8169_start_xmit(skb, tp->dev);
5920 struct net_device_stats *stats;
5923 stats = &tp->dev->stats;
5924 stats->tx_dropped++;
5925 dev_kfree_skb_any(skb);
5929 /* msdn_giant_send_check()
5930 * According to the document of microsoft, the TCP Pseudo Header excludes the
5931 * packet length for IPv6 TCP large packets.
5933 static int msdn_giant_send_check(struct sk_buff *skb)
5935 const struct ipv6hdr *ipv6h;
5939 ret = skb_cow_head(skb, 0);
5943 ipv6h = ipv6_hdr(skb);
5947 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
5952 static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp,
5953 struct sk_buff *skb, u32 *opts)
5955 u32 mss = skb_shinfo(skb)->gso_size;
5959 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
5960 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5961 const struct iphdr *ip = ip_hdr(skb);
5963 if (ip->protocol == IPPROTO_TCP)
5964 opts[0] |= TD0_IP_CS | TD0_TCP_CS;
5965 else if (ip->protocol == IPPROTO_UDP)
5966 opts[0] |= TD0_IP_CS | TD0_UDP_CS;
5974 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
5975 struct sk_buff *skb, u32 *opts)
5977 u32 transport_offset = (u32)skb_transport_offset(skb);
5978 u32 mss = skb_shinfo(skb)->gso_size;
5981 if (transport_offset > GTTCPHO_MAX) {
5982 netif_warn(tp, tx_err, tp->dev,
5983 "Invalid transport offset 0x%x for TSO\n",
5988 switch (vlan_get_protocol(skb)) {
5989 case htons(ETH_P_IP):
5990 opts[0] |= TD1_GTSENV4;
5993 case htons(ETH_P_IPV6):
5994 if (msdn_giant_send_check(skb))
5997 opts[0] |= TD1_GTSENV6;
6005 opts[0] |= transport_offset << GTTCPHO_SHIFT;
6006 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
6007 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6010 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
6011 return !(skb_checksum_help(skb) || eth_skb_pad(skb));
6013 if (transport_offset > TCPHO_MAX) {
6014 netif_warn(tp, tx_err, tp->dev,
6015 "Invalid transport offset 0x%x\n",
6020 switch (vlan_get_protocol(skb)) {
6021 case htons(ETH_P_IP):
6022 opts[1] |= TD1_IPv4_CS;
6023 ip_protocol = ip_hdr(skb)->protocol;
6026 case htons(ETH_P_IPV6):
6027 opts[1] |= TD1_IPv6_CS;
6028 ip_protocol = ipv6_hdr(skb)->nexthdr;
6032 ip_protocol = IPPROTO_RAW;
6036 if (ip_protocol == IPPROTO_TCP)
6037 opts[1] |= TD1_TCP_CS;
6038 else if (ip_protocol == IPPROTO_UDP)
6039 opts[1] |= TD1_UDP_CS;
6043 opts[1] |= transport_offset << TCPHO_SHIFT;
6045 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
6046 return !eth_skb_pad(skb);
6052 static bool rtl_tx_slots_avail(struct rtl8169_private *tp,
6053 unsigned int nr_frags)
6055 unsigned int slots_avail = tp->dirty_tx + NUM_TX_DESC - tp->cur_tx;
6057 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
6058 return slots_avail > nr_frags;
6061 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6062 struct net_device *dev)
6064 struct rtl8169_private *tp = netdev_priv(dev);
6065 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
6066 struct TxDesc *txd = tp->TxDescArray + entry;
6067 struct device *d = tp_to_dev(tp);
6073 if (unlikely(!rtl_tx_slots_avail(tp, skb_shinfo(skb)->nr_frags))) {
6074 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
6078 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
6081 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
6084 if (!tp->tso_csum(tp, skb, opts)) {
6085 r8169_csum_workaround(tp, skb);
6086 return NETDEV_TX_OK;
6089 len = skb_headlen(skb);
6090 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
6091 if (unlikely(dma_mapping_error(d, mapping))) {
6092 if (net_ratelimit())
6093 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
6097 tp->tx_skb[entry].len = len;
6098 txd->addr = cpu_to_le64(mapping);
6100 frags = rtl8169_xmit_frags(tp, skb, opts);
6104 opts[0] |= FirstFrag;
6106 opts[0] |= FirstFrag | LastFrag;
6107 tp->tx_skb[entry].skb = skb;
6110 txd->opts2 = cpu_to_le32(opts[1]);
6112 skb_tx_timestamp(skb);
6114 /* Force memory writes to complete before releasing descriptor */
6117 txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry);
6119 /* Force all memory writes to complete before notifying device */
6122 tp->cur_tx += frags + 1;
6124 stop_queue = !rtl_tx_slots_avail(tp, MAX_SKB_FRAGS);
6125 if (unlikely(stop_queue))
6126 netif_stop_queue(dev);
6128 if (__netdev_sent_queue(dev, skb->len, skb->xmit_more))
6129 RTL_W8(tp, TxPoll, NPQ);
6131 if (unlikely(stop_queue)) {
6132 /* Sync with rtl_tx:
6133 * - publish queue status and cur_tx ring index (write barrier)
6134 * - refresh dirty_tx ring index (read barrier).
6135 * May the current thread have a pessimistic view of the ring
6136 * status and forget to wake up queue, a racing rtl_tx thread
6140 if (rtl_tx_slots_avail(tp, MAX_SKB_FRAGS))
6141 netif_wake_queue(dev);
6144 return NETDEV_TX_OK;
6147 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
6149 dev_kfree_skb_any(skb);
6150 dev->stats.tx_dropped++;
6151 return NETDEV_TX_OK;
6154 netif_stop_queue(dev);
6155 dev->stats.tx_dropped++;
6156 return NETDEV_TX_BUSY;
6159 static void rtl8169_pcierr_interrupt(struct net_device *dev)
6161 struct rtl8169_private *tp = netdev_priv(dev);
6162 struct pci_dev *pdev = tp->pci_dev;
6163 u16 pci_status, pci_cmd;
6165 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
6166 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
6168 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
6169 pci_cmd, pci_status);
6172 * The recovery sequence below admits a very elaborated explanation:
6173 * - it seems to work;
6174 * - I did not see what else could be done;
6175 * - it makes iop3xx happy.
6177 * Feel free to adjust to your needs.
6179 if (pdev->broken_parity_status)
6180 pci_cmd &= ~PCI_COMMAND_PARITY;
6182 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
6184 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
6186 pci_write_config_word(pdev, PCI_STATUS,
6187 pci_status & (PCI_STATUS_DETECTED_PARITY |
6188 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
6189 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
6191 /* The infamous DAC f*ckup only happens at boot time */
6192 if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
6193 netif_info(tp, intr, dev, "disabling PCI DAC\n");
6194 tp->cp_cmd &= ~PCIDAC;
6195 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
6196 dev->features &= ~NETIF_F_HIGHDMA;
6199 rtl8169_hw_reset(tp);
6201 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6204 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp,
6207 unsigned int dirty_tx, tx_left, bytes_compl = 0, pkts_compl = 0;
6209 dirty_tx = tp->dirty_tx;
6211 tx_left = tp->cur_tx - dirty_tx;
6213 while (tx_left > 0) {
6214 unsigned int entry = dirty_tx % NUM_TX_DESC;
6215 struct ring_info *tx_skb = tp->tx_skb + entry;
6218 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
6219 if (status & DescOwn)
6222 /* This barrier is needed to keep us from reading
6223 * any other fields out of the Tx descriptor until
6224 * we know the status of DescOwn
6228 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
6229 tp->TxDescArray + entry);
6230 if (status & LastFrag) {
6232 bytes_compl += tx_skb->skb->len;
6233 napi_consume_skb(tx_skb->skb, budget);
6240 if (tp->dirty_tx != dirty_tx) {
6241 netdev_completed_queue(dev, pkts_compl, bytes_compl);
6243 u64_stats_update_begin(&tp->tx_stats.syncp);
6244 tp->tx_stats.packets += pkts_compl;
6245 tp->tx_stats.bytes += bytes_compl;
6246 u64_stats_update_end(&tp->tx_stats.syncp);
6248 tp->dirty_tx = dirty_tx;
6249 /* Sync with rtl8169_start_xmit:
6250 * - publish dirty_tx ring index (write barrier)
6251 * - refresh cur_tx ring index and queue status (read barrier)
6252 * May the current thread miss the stopped queue condition,
6253 * a racing xmit thread can only have a right view of the
6257 if (netif_queue_stopped(dev) &&
6258 rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) {
6259 netif_wake_queue(dev);
6262 * 8168 hack: TxPoll requests are lost when the Tx packets are
6263 * too close. Let's kick an extra TxPoll request when a burst
6264 * of start_xmit activity is detected (if it is not detected,
6265 * it is slow enough). -- FR
6267 if (tp->cur_tx != dirty_tx)
6268 RTL_W8(tp, TxPoll, NPQ);
6272 static inline int rtl8169_fragmented_frame(u32 status)
6274 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
6277 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
6279 u32 status = opts1 & RxProtoMask;
6281 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
6282 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
6283 skb->ip_summed = CHECKSUM_UNNECESSARY;
6285 skb_checksum_none_assert(skb);
6288 static struct sk_buff *rtl8169_try_rx_copy(void *data,
6289 struct rtl8169_private *tp,
6293 struct sk_buff *skb;
6294 struct device *d = tp_to_dev(tp);
6296 data = rtl8169_align(data);
6297 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6299 skb = napi_alloc_skb(&tp->napi, pkt_size);
6301 skb_copy_to_linear_data(skb, data, pkt_size);
6302 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
6307 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
6309 unsigned int cur_rx, rx_left;
6312 cur_rx = tp->cur_rx;
6314 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
6315 unsigned int entry = cur_rx % NUM_RX_DESC;
6316 struct RxDesc *desc = tp->RxDescArray + entry;
6319 status = le32_to_cpu(desc->opts1);
6320 if (status & DescOwn)
6323 /* This barrier is needed to keep us from reading
6324 * any other fields out of the Rx descriptor until
6325 * we know the status of DescOwn
6329 if (unlikely(status & RxRES)) {
6330 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
6332 dev->stats.rx_errors++;
6333 if (status & (RxRWT | RxRUNT))
6334 dev->stats.rx_length_errors++;
6336 dev->stats.rx_crc_errors++;
6337 /* RxFOVF is a reserved bit on later chip versions */
6338 if (tp->mac_version == RTL_GIGA_MAC_VER_01 &&
6340 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6341 dev->stats.rx_fifo_errors++;
6342 } else if (status & (RxRUNT | RxCRC) &&
6343 !(status & RxRWT) &&
6344 dev->features & NETIF_F_RXALL) {
6348 struct sk_buff *skb;
6353 addr = le64_to_cpu(desc->addr);
6354 if (likely(!(dev->features & NETIF_F_RXFCS)))
6355 pkt_size = (status & 0x00003fff) - 4;
6357 pkt_size = status & 0x00003fff;
6360 * The driver does not support incoming fragmented
6361 * frames. They are seen as a symptom of over-mtu
6364 if (unlikely(rtl8169_fragmented_frame(status))) {
6365 dev->stats.rx_dropped++;
6366 dev->stats.rx_length_errors++;
6367 goto release_descriptor;
6370 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
6371 tp, pkt_size, addr);
6373 dev->stats.rx_dropped++;
6374 goto release_descriptor;
6377 rtl8169_rx_csum(skb, status);
6378 skb_put(skb, pkt_size);
6379 skb->protocol = eth_type_trans(skb, dev);
6381 rtl8169_rx_vlan_tag(desc, skb);
6383 if (skb->pkt_type == PACKET_MULTICAST)
6384 dev->stats.multicast++;
6386 napi_gro_receive(&tp->napi, skb);
6388 u64_stats_update_begin(&tp->rx_stats.syncp);
6389 tp->rx_stats.packets++;
6390 tp->rx_stats.bytes += pkt_size;
6391 u64_stats_update_end(&tp->rx_stats.syncp);
6395 rtl8169_mark_to_asic(desc);
6398 count = cur_rx - tp->cur_rx;
6399 tp->cur_rx = cur_rx;
6404 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
6406 struct rtl8169_private *tp = dev_instance;
6407 u16 status = RTL_R16(tp, IntrStatus);
6408 u16 irq_mask = RTL_R16(tp, IntrMask);
6410 if (status == 0xffff || !(status & irq_mask))
6413 if (unlikely(status & SYSErr)) {
6414 rtl8169_pcierr_interrupt(tp->dev);
6418 if (status & LinkChg && tp->dev->phydev)
6419 phy_mac_interrupt(tp->dev->phydev);
6421 if (unlikely(status & RxFIFOOver &&
6422 tp->mac_version == RTL_GIGA_MAC_VER_11)) {
6423 netif_stop_queue(tp->dev);
6424 /* XXX - Hack alert. See rtl_task(). */
6425 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
6428 if (status & RTL_EVENT_NAPI) {
6429 rtl_irq_disable(tp);
6430 napi_schedule_irqoff(&tp->napi);
6433 rtl_ack_events(tp, status);
6438 static void rtl_task(struct work_struct *work)
6440 static const struct {
6442 void (*action)(struct rtl8169_private *);
6444 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
6446 struct rtl8169_private *tp =
6447 container_of(work, struct rtl8169_private, wk.work);
6448 struct net_device *dev = tp->dev;
6453 if (!netif_running(dev) ||
6454 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
6457 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
6460 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
6462 rtl_work[i].action(tp);
6466 rtl_unlock_work(tp);
6469 static int rtl8169_poll(struct napi_struct *napi, int budget)
6471 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
6472 struct net_device *dev = tp->dev;
6475 work_done = rtl_rx(dev, tp, (u32) budget);
6477 rtl_tx(dev, tp, budget);
6479 if (work_done < budget) {
6480 napi_complete_done(napi, work_done);
6487 static void rtl8169_rx_missed(struct net_device *dev)
6489 struct rtl8169_private *tp = netdev_priv(dev);
6491 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
6494 dev->stats.rx_missed_errors += RTL_R32(tp, RxMissed) & 0xffffff;
6495 RTL_W32(tp, RxMissed, 0);
6498 static void r8169_phylink_handler(struct net_device *ndev)
6500 struct rtl8169_private *tp = netdev_priv(ndev);
6502 if (netif_carrier_ok(ndev)) {
6503 rtl_link_chg_patch(tp);
6504 pm_request_resume(&tp->pci_dev->dev);
6506 pm_runtime_idle(&tp->pci_dev->dev);
6509 if (net_ratelimit())
6510 phy_print_status(ndev->phydev);
6513 static int r8169_phy_connect(struct rtl8169_private *tp)
6515 struct phy_device *phydev = mdiobus_get_phy(tp->mii_bus, 0);
6516 phy_interface_t phy_mode;
6519 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
6520 PHY_INTERFACE_MODE_MII;
6522 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
6527 if (!tp->supports_gmii)
6528 phy_set_max_speed(phydev, SPEED_100);
6530 /* Ensure to advertise everything, incl. pause */
6531 linkmode_copy(phydev->advertising, phydev->supported);
6533 phy_attached_info(phydev);
6538 static void rtl8169_down(struct net_device *dev)
6540 struct rtl8169_private *tp = netdev_priv(dev);
6542 phy_stop(dev->phydev);
6544 napi_disable(&tp->napi);
6545 netif_stop_queue(dev);
6547 rtl8169_hw_reset(tp);
6549 * At this point device interrupts can not be enabled in any function,
6550 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6551 * and napi is disabled (rtl8169_poll).
6553 rtl8169_rx_missed(dev);
6555 /* Give a racing hard_start_xmit a few cycles to complete. */
6558 rtl8169_tx_clear(tp);
6560 rtl8169_rx_clear(tp);
6562 rtl_pll_power_down(tp);
6565 static int rtl8169_close(struct net_device *dev)
6567 struct rtl8169_private *tp = netdev_priv(dev);
6568 struct pci_dev *pdev = tp->pci_dev;
6570 pm_runtime_get_sync(&pdev->dev);
6572 /* Update counters before going down */
6573 rtl8169_update_counters(tp);
6576 /* Clear all task flags */
6577 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6580 rtl_unlock_work(tp);
6582 cancel_work_sync(&tp->wk.work);
6584 phy_disconnect(dev->phydev);
6586 pci_free_irq(pdev, 0, tp);
6588 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6590 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6592 tp->TxDescArray = NULL;
6593 tp->RxDescArray = NULL;
6595 pm_runtime_put_sync(&pdev->dev);
6600 #ifdef CONFIG_NET_POLL_CONTROLLER
6601 static void rtl8169_netpoll(struct net_device *dev)
6603 struct rtl8169_private *tp = netdev_priv(dev);
6605 rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp);
6609 static int rtl_open(struct net_device *dev)
6611 struct rtl8169_private *tp = netdev_priv(dev);
6612 struct pci_dev *pdev = tp->pci_dev;
6613 int retval = -ENOMEM;
6615 pm_runtime_get_sync(&pdev->dev);
6618 * Rx and Tx descriptors needs 256 bytes alignment.
6619 * dma_alloc_coherent provides more.
6621 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6622 &tp->TxPhyAddr, GFP_KERNEL);
6623 if (!tp->TxDescArray)
6624 goto err_pm_runtime_put;
6626 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6627 &tp->RxPhyAddr, GFP_KERNEL);
6628 if (!tp->RxDescArray)
6631 retval = rtl8169_init_ring(tp);
6635 INIT_WORK(&tp->wk.work, rtl_task);
6639 rtl_request_firmware(tp);
6641 retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, tp,
6644 goto err_release_fw_2;
6646 retval = r8169_phy_connect(tp);
6652 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6654 napi_enable(&tp->napi);
6656 rtl8169_init_phy(dev, tp);
6658 rtl_pll_power_up(tp);
6662 if (!rtl8169_init_counter_offsets(tp))
6663 netif_warn(tp, hw, dev, "counter reset/update failed\n");
6665 phy_start(dev->phydev);
6666 netif_start_queue(dev);
6668 rtl_unlock_work(tp);
6670 pm_runtime_put_sync(&pdev->dev);
6675 pci_free_irq(pdev, 0, tp);
6677 rtl_release_firmware(tp);
6678 rtl8169_rx_clear(tp);
6680 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6682 tp->RxDescArray = NULL;
6684 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6686 tp->TxDescArray = NULL;
6688 pm_runtime_put_noidle(&pdev->dev);
6693 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
6695 struct rtl8169_private *tp = netdev_priv(dev);
6696 struct pci_dev *pdev = tp->pci_dev;
6697 struct rtl8169_counters *counters = tp->counters;
6700 pm_runtime_get_noresume(&pdev->dev);
6702 if (netif_running(dev) && pm_runtime_active(&pdev->dev))
6703 rtl8169_rx_missed(dev);
6706 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
6707 stats->rx_packets = tp->rx_stats.packets;
6708 stats->rx_bytes = tp->rx_stats.bytes;
6709 } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
6712 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
6713 stats->tx_packets = tp->tx_stats.packets;
6714 stats->tx_bytes = tp->tx_stats.bytes;
6715 } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
6717 stats->rx_dropped = dev->stats.rx_dropped;
6718 stats->tx_dropped = dev->stats.tx_dropped;
6719 stats->rx_length_errors = dev->stats.rx_length_errors;
6720 stats->rx_errors = dev->stats.rx_errors;
6721 stats->rx_crc_errors = dev->stats.rx_crc_errors;
6722 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
6723 stats->rx_missed_errors = dev->stats.rx_missed_errors;
6724 stats->multicast = dev->stats.multicast;
6727 * Fetch additonal counter values missing in stats collected by driver
6728 * from tally counters.
6730 if (pm_runtime_active(&pdev->dev))
6731 rtl8169_update_counters(tp);
6734 * Subtract values fetched during initalization.
6735 * See rtl8169_init_counter_offsets for a description why we do that.
6737 stats->tx_errors = le64_to_cpu(counters->tx_errors) -
6738 le64_to_cpu(tp->tc_offset.tx_errors);
6739 stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
6740 le32_to_cpu(tp->tc_offset.tx_multi_collision);
6741 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
6742 le16_to_cpu(tp->tc_offset.tx_aborted);
6744 pm_runtime_put_noidle(&pdev->dev);
6747 static void rtl8169_net_suspend(struct net_device *dev)
6749 struct rtl8169_private *tp = netdev_priv(dev);
6751 if (!netif_running(dev))
6754 phy_stop(dev->phydev);
6755 netif_device_detach(dev);
6758 napi_disable(&tp->napi);
6759 /* Clear all task flags */
6760 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6762 rtl_unlock_work(tp);
6764 rtl_pll_power_down(tp);
6769 static int rtl8169_suspend(struct device *device)
6771 struct net_device *dev = dev_get_drvdata(device);
6772 struct rtl8169_private *tp = netdev_priv(dev);
6774 rtl8169_net_suspend(dev);
6775 clk_disable_unprepare(tp->clk);
6780 static void __rtl8169_resume(struct net_device *dev)
6782 struct rtl8169_private *tp = netdev_priv(dev);
6784 netif_device_attach(dev);
6786 rtl_pll_power_up(tp);
6787 rtl8169_init_phy(dev, tp);
6789 phy_start(tp->dev->phydev);
6792 napi_enable(&tp->napi);
6793 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6794 rtl_unlock_work(tp);
6796 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6799 static int rtl8169_resume(struct device *device)
6801 struct net_device *dev = dev_get_drvdata(device);
6802 struct rtl8169_private *tp = netdev_priv(dev);
6804 clk_prepare_enable(tp->clk);
6806 if (netif_running(dev))
6807 __rtl8169_resume(dev);
6812 static int rtl8169_runtime_suspend(struct device *device)
6814 struct net_device *dev = dev_get_drvdata(device);
6815 struct rtl8169_private *tp = netdev_priv(dev);
6817 if (!tp->TxDescArray)
6821 __rtl8169_set_wol(tp, WAKE_ANY);
6822 rtl_unlock_work(tp);
6824 rtl8169_net_suspend(dev);
6826 /* Update counters before going runtime suspend */
6827 rtl8169_rx_missed(dev);
6828 rtl8169_update_counters(tp);
6833 static int rtl8169_runtime_resume(struct device *device)
6835 struct net_device *dev = dev_get_drvdata(device);
6836 struct rtl8169_private *tp = netdev_priv(dev);
6837 rtl_rar_set(tp, dev->dev_addr);
6839 if (!tp->TxDescArray)
6843 __rtl8169_set_wol(tp, tp->saved_wolopts);
6844 rtl_unlock_work(tp);
6846 __rtl8169_resume(dev);
6851 static int rtl8169_runtime_idle(struct device *device)
6853 struct net_device *dev = dev_get_drvdata(device);
6855 if (!netif_running(dev) || !netif_carrier_ok(dev))
6856 pm_schedule_suspend(device, 10000);
6861 static const struct dev_pm_ops rtl8169_pm_ops = {
6862 .suspend = rtl8169_suspend,
6863 .resume = rtl8169_resume,
6864 .freeze = rtl8169_suspend,
6865 .thaw = rtl8169_resume,
6866 .poweroff = rtl8169_suspend,
6867 .restore = rtl8169_resume,
6868 .runtime_suspend = rtl8169_runtime_suspend,
6869 .runtime_resume = rtl8169_runtime_resume,
6870 .runtime_idle = rtl8169_runtime_idle,
6873 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
6875 #else /* !CONFIG_PM */
6877 #define RTL8169_PM_OPS NULL
6879 #endif /* !CONFIG_PM */
6881 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6883 /* WoL fails with 8168b when the receiver is disabled. */
6884 switch (tp->mac_version) {
6885 case RTL_GIGA_MAC_VER_11:
6886 case RTL_GIGA_MAC_VER_12:
6887 case RTL_GIGA_MAC_VER_17:
6888 pci_clear_master(tp->pci_dev);
6890 RTL_W8(tp, ChipCmd, CmdRxEnb);
6892 RTL_R8(tp, ChipCmd);
6899 static void rtl_shutdown(struct pci_dev *pdev)
6901 struct net_device *dev = pci_get_drvdata(pdev);
6902 struct rtl8169_private *tp = netdev_priv(dev);
6904 rtl8169_net_suspend(dev);
6906 /* Restore original MAC address */
6907 rtl_rar_set(tp, dev->perm_addr);
6909 rtl8169_hw_reset(tp);
6911 if (system_state == SYSTEM_POWER_OFF) {
6912 if (tp->saved_wolopts) {
6913 rtl_wol_suspend_quirk(tp);
6914 rtl_wol_shutdown_quirk(tp);
6917 pci_wake_from_d3(pdev, true);
6918 pci_set_power_state(pdev, PCI_D3hot);
6922 static void rtl_remove_one(struct pci_dev *pdev)
6924 struct net_device *dev = pci_get_drvdata(pdev);
6925 struct rtl8169_private *tp = netdev_priv(dev);
6927 if (r8168_check_dash(tp))
6928 rtl8168_driver_stop(tp);
6930 netif_napi_del(&tp->napi);
6932 unregister_netdev(dev);
6933 mdiobus_unregister(tp->mii_bus);
6935 rtl_release_firmware(tp);
6937 if (pci_dev_run_wake(pdev))
6938 pm_runtime_get_noresume(&pdev->dev);
6940 /* restore original MAC address */
6941 rtl_rar_set(tp, dev->perm_addr);
6944 static const struct net_device_ops rtl_netdev_ops = {
6945 .ndo_open = rtl_open,
6946 .ndo_stop = rtl8169_close,
6947 .ndo_get_stats64 = rtl8169_get_stats64,
6948 .ndo_start_xmit = rtl8169_start_xmit,
6949 .ndo_tx_timeout = rtl8169_tx_timeout,
6950 .ndo_validate_addr = eth_validate_addr,
6951 .ndo_change_mtu = rtl8169_change_mtu,
6952 .ndo_fix_features = rtl8169_fix_features,
6953 .ndo_set_features = rtl8169_set_features,
6954 .ndo_set_mac_address = rtl_set_mac_address,
6955 .ndo_do_ioctl = rtl8169_ioctl,
6956 .ndo_set_rx_mode = rtl_set_rx_mode,
6957 #ifdef CONFIG_NET_POLL_CONTROLLER
6958 .ndo_poll_controller = rtl8169_netpoll,
6963 static const struct rtl_cfg_info {
6964 void (*hw_start)(struct rtl8169_private *tp);
6966 unsigned int has_gmii:1;
6967 const struct rtl_coalesce_info *coalesce_info;
6968 } rtl_cfg_infos [] = {
6970 .hw_start = rtl_hw_start_8169,
6971 .irq_mask = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
6973 .coalesce_info = rtl_coalesce_info_8169,
6976 .hw_start = rtl_hw_start_8168,
6977 .irq_mask = LinkChg | RxOverflow,
6979 .coalesce_info = rtl_coalesce_info_8168_8136,
6982 .hw_start = rtl_hw_start_8101,
6983 .irq_mask = LinkChg | RxOverflow | RxFIFOOver,
6984 .coalesce_info = rtl_coalesce_info_8168_8136,
6988 static int rtl_alloc_irq(struct rtl8169_private *tp)
6992 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
6993 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
6994 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
6995 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
6996 flags = PCI_IRQ_LEGACY;
6998 flags = PCI_IRQ_ALL_TYPES;
7001 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
7004 DECLARE_RTL_COND(rtl_link_list_ready_cond)
7006 return RTL_R8(tp, MCU) & LINK_LIST_RDY;
7009 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
7011 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
7014 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
7016 struct rtl8169_private *tp = mii_bus->priv;
7021 return rtl_readphy(tp, phyreg);
7024 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
7025 int phyreg, u16 val)
7027 struct rtl8169_private *tp = mii_bus->priv;
7032 rtl_writephy(tp, phyreg, val);
7037 static int r8169_mdio_register(struct rtl8169_private *tp)
7039 struct pci_dev *pdev = tp->pci_dev;
7040 struct phy_device *phydev;
7041 struct mii_bus *new_bus;
7044 new_bus = devm_mdiobus_alloc(&pdev->dev);
7048 new_bus->name = "r8169";
7050 new_bus->parent = &pdev->dev;
7051 new_bus->irq[0] = PHY_IGNORE_INTERRUPT;
7052 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x",
7053 PCI_DEVID(pdev->bus->number, pdev->devfn));
7055 new_bus->read = r8169_mdio_read_reg;
7056 new_bus->write = r8169_mdio_write_reg;
7058 ret = mdiobus_register(new_bus);
7062 phydev = mdiobus_get_phy(new_bus, 0);
7064 mdiobus_unregister(new_bus);
7068 /* PHY will be woken up in rtl_open() */
7069 phy_suspend(phydev);
7071 tp->mii_bus = new_bus;
7076 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
7080 tp->ocp_base = OCP_STD_PHY_BASE;
7082 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
7084 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
7087 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
7090 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
7092 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
7094 data = r8168_mac_ocp_read(tp, 0xe8de);
7096 r8168_mac_ocp_write(tp, 0xe8de, data);
7098 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7101 data = r8168_mac_ocp_read(tp, 0xe8de);
7103 r8168_mac_ocp_write(tp, 0xe8de, data);
7105 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7109 static void rtl_hw_init_8168ep(struct rtl8169_private *tp)
7111 rtl8168ep_stop_cmac(tp);
7112 rtl_hw_init_8168g(tp);
7115 static void rtl_hw_initialize(struct rtl8169_private *tp)
7117 switch (tp->mac_version) {
7118 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
7119 rtl_hw_init_8168g(tp);
7121 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_51:
7122 rtl_hw_init_8168ep(tp);
7129 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */
7130 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
7132 switch (tp->mac_version) {
7133 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
7134 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
7141 static int rtl_jumbo_max(struct rtl8169_private *tp)
7143 /* Non-GBit versions don't support jumbo frames */
7144 if (!tp->supports_gmii)
7147 switch (tp->mac_version) {
7149 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
7152 case RTL_GIGA_MAC_VER_11:
7153 case RTL_GIGA_MAC_VER_12:
7154 case RTL_GIGA_MAC_VER_17:
7157 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
7164 static void rtl_disable_clk(void *data)
7166 clk_disable_unprepare(data);
7169 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7171 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
7172 struct rtl8169_private *tp;
7173 struct net_device *dev;
7174 int chipset, region, i;
7177 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
7181 SET_NETDEV_DEV(dev, &pdev->dev);
7182 dev->netdev_ops = &rtl_netdev_ops;
7183 tp = netdev_priv(dev);
7186 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
7187 tp->supports_gmii = cfg->has_gmii;
7189 /* Get the *optional* external "ether_clk" used on some boards */
7190 tp->clk = devm_clk_get(&pdev->dev, "ether_clk");
7191 if (IS_ERR(tp->clk)) {
7192 rc = PTR_ERR(tp->clk);
7193 if (rc == -ENOENT) {
7194 /* clk-core allows NULL (for suspend / resume) */
7196 } else if (rc == -EPROBE_DEFER) {
7199 dev_err(&pdev->dev, "failed to get clk: %d\n", rc);
7203 rc = clk_prepare_enable(tp->clk);
7205 dev_err(&pdev->dev, "failed to enable clk: %d\n", rc);
7209 rc = devm_add_action_or_reset(&pdev->dev, rtl_disable_clk,
7215 /* enable device (incl. PCI PM wakeup and hotplug setup) */
7216 rc = pcim_enable_device(pdev);
7218 dev_err(&pdev->dev, "enable failure\n");
7222 if (pcim_set_mwi(pdev) < 0)
7223 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
7225 /* use first MMIO region */
7226 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
7228 dev_err(&pdev->dev, "no MMIO resource found\n");
7232 /* check for weird/broken PCI region reporting */
7233 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
7234 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
7238 rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME);
7240 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
7244 tp->mmio_addr = pcim_iomap_table(pdev)[region];
7246 /* Identify chip attached to board */
7247 rtl8169_get_mac_version(tp);
7248 if (tp->mac_version == RTL_GIGA_MAC_NONE)
7251 if (rtl_tbi_enabled(tp)) {
7252 dev_err(&pdev->dev, "TBI fiber mode not supported\n");
7256 tp->cp_cmd = RTL_R16(tp, CPlusCmd);
7258 if (sizeof(dma_addr_t) > 4 && (use_dac == 1 || (use_dac == -1 &&
7259 tp->mac_version >= RTL_GIGA_MAC_VER_18)) &&
7260 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
7262 /* CPlusCmd Dual Access Cycle is only needed for non-PCIe */
7263 if (!pci_is_pcie(pdev))
7264 tp->cp_cmd |= PCIDAC;
7265 dev->features |= NETIF_F_HIGHDMA;
7267 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
7269 dev_err(&pdev->dev, "DMA configuration failed\n");
7276 rtl8169_irq_mask_and_ack(tp);
7278 rtl_hw_initialize(tp);
7282 pci_set_master(pdev);
7284 rtl_init_mdio_ops(tp);
7285 rtl_init_jumbo_ops(tp);
7287 chipset = tp->mac_version;
7289 rc = rtl_alloc_irq(tp);
7291 dev_err(&pdev->dev, "Can't allocate interrupt\n");
7295 tp->saved_wolopts = __rtl8169_get_wol(tp);
7297 mutex_init(&tp->wk.mutex);
7298 u64_stats_init(&tp->rx_stats.syncp);
7299 u64_stats_init(&tp->tx_stats.syncp);
7301 /* Get MAC address */
7302 switch (tp->mac_version) {
7303 u8 mac_addr[ETH_ALEN] __aligned(4);
7304 case RTL_GIGA_MAC_VER_35 ... RTL_GIGA_MAC_VER_38:
7305 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
7306 *(u32 *)&mac_addr[0] = rtl_eri_read(tp, 0xe0, ERIAR_EXGMAC);
7307 *(u16 *)&mac_addr[4] = rtl_eri_read(tp, 0xe4, ERIAR_EXGMAC);
7309 if (is_valid_ether_addr(mac_addr))
7310 rtl_rar_set(tp, mac_addr);
7315 for (i = 0; i < ETH_ALEN; i++)
7316 dev->dev_addr[i] = RTL_R8(tp, MAC0 + i);
7318 dev->ethtool_ops = &rtl8169_ethtool_ops;
7320 netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT);
7322 /* don't enable SG, IP_CSUM and TSO by default - it might not work
7323 * properly for all devices */
7324 dev->features |= NETIF_F_RXCSUM |
7325 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
7327 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7328 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
7329 NETIF_F_HW_VLAN_CTAG_RX;
7330 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7332 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
7334 tp->cp_cmd |= RxChkSum | RxVlan;
7337 * Pretend we are using VLANs; This bypasses a nasty bug where
7338 * Interrupts stop flowing on high load on 8110SCd controllers.
7340 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
7341 /* Disallow toggling */
7342 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
7344 if (rtl_chip_supports_csum_v2(tp)) {
7345 tp->tso_csum = rtl8169_tso_csum_v2;
7346 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
7348 tp->tso_csum = rtl8169_tso_csum_v1;
7351 dev->hw_features |= NETIF_F_RXALL;
7352 dev->hw_features |= NETIF_F_RXFCS;
7354 /* MTU range: 60 - hw-specific max */
7355 dev->min_mtu = ETH_ZLEN;
7356 jumbo_max = rtl_jumbo_max(tp);
7357 dev->max_mtu = jumbo_max;
7359 tp->hw_start = cfg->hw_start;
7360 tp->irq_mask = RTL_EVENT_NAPI | cfg->irq_mask;
7361 tp->coalesce_info = cfg->coalesce_info;
7363 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
7365 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
7366 &tp->counters_phys_addr,
7371 pci_set_drvdata(pdev, dev);
7373 rc = r8169_mdio_register(tp);
7377 /* chip gets powered up in rtl_open() */
7378 rtl_pll_power_down(tp);
7380 rc = register_netdev(dev);
7382 goto err_mdio_unregister;
7384 netif_info(tp, probe, dev, "%s, %pM, XID %03x, IRQ %d\n",
7385 rtl_chip_infos[chipset].name, dev->dev_addr,
7386 (RTL_R32(tp, TxConfig) >> 20) & 0xfcf,
7387 pci_irq_vector(pdev, 0));
7389 if (jumbo_max > JUMBO_1K)
7390 netif_info(tp, probe, dev,
7391 "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
7392 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?
7395 if (r8168_check_dash(tp))
7396 rtl8168_driver_start(tp);
7398 if (pci_dev_run_wake(pdev))
7399 pm_runtime_put_sync(&pdev->dev);
7403 err_mdio_unregister:
7404 mdiobus_unregister(tp->mii_bus);
7408 static struct pci_driver rtl8169_pci_driver = {
7410 .id_table = rtl8169_pci_tbl,
7411 .probe = rtl_init_one,
7412 .remove = rtl_remove_one,
7413 .shutdown = rtl_shutdown,
7414 .driver.pm = RTL8169_PM_OPS,
7417 module_pci_driver(rtl8169_pci_driver);