drivers/net/ethernet/realtek/r8169.c

   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/clk.h>
  17 #include <linux/delay.h>
  18 #include <linux/ethtool.h>
  19 #include <linux/phy.h>
  20 #include <linux/if_vlan.h>
  21 #include <linux/crc32.h>
  22 #include <linux/in.h>
  23 #include <linux/io.h>
  24 #include <linux/ip.h>
  25 #include <linux/tcp.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/dma-mapping.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/firmware.h>
  30 #include <linux/prefetch.h>
  31 #include <linux/ipv6.h>
  32 #include <net/ip6_checksum.h>
  33
  34 #define MODULENAME "r8169"
  35
  36 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  37 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  38 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  39 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  40 #define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
  41 #define FIRMWARE_8168F_1        "rtl_nic/rtl8168f-1.fw"
  42 #define FIRMWARE_8168F_2        "rtl_nic/rtl8168f-2.fw"
  43 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  44 #define FIRMWARE_8402_1         "rtl_nic/rtl8402-1.fw"
  45 #define FIRMWARE_8411_1         "rtl_nic/rtl8411-1.fw"
  46 #define FIRMWARE_8411_2         "rtl_nic/rtl8411-2.fw"
  47 #define FIRMWARE_8106E_1        "rtl_nic/rtl8106e-1.fw"
  48 #define FIRMWARE_8106E_2        "rtl_nic/rtl8106e-2.fw"
  49 #define FIRMWARE_8168G_2        "rtl_nic/rtl8168g-2.fw"
  50 #define FIRMWARE_8168G_3        "rtl_nic/rtl8168g-3.fw"
  51 #define FIRMWARE_8168H_1        "rtl_nic/rtl8168h-1.fw"
  52 #define FIRMWARE_8168H_2        "rtl_nic/rtl8168h-2.fw"
  53 #define FIRMWARE_8107E_1        "rtl_nic/rtl8107e-1.fw"
  54 #define FIRMWARE_8107E_2        "rtl_nic/rtl8107e-2.fw"
  55
  56 #define R8169_MSG_DEFAULT \
  57         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  58
  59 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  60    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  61 static const int multicast_filter_limit = 32;
  62
  63 #define TX_DMA_BURST    7       /* Maximum PCI burst, '7' is unlimited */
  64 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  65
  66 #define R8169_REGS_SIZE         256
  67 #define R8169_RX_BUF_SIZE       (SZ_16K - 1)
  68 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  69 #define NUM_RX_DESC     256U    /* Number of Rx descriptor registers */
  70 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  71 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  72
  73 /* write/read MMIO register */
  74 #define RTL_W8(tp, reg, val8)   writeb((val8), tp->mmio_addr + (reg))
  75 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
  76 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
  77 #define RTL_R8(tp, reg)         readb(tp->mmio_addr + (reg))
  78 #define RTL_R16(tp, reg)                readw(tp->mmio_addr + (reg))
  79 #define RTL_R32(tp, reg)                readl(tp->mmio_addr + (reg))
  80
  81 enum mac_version {
  82         RTL_GIGA_MAC_VER_01 = 0,
  83         RTL_GIGA_MAC_VER_02,
  84         RTL_GIGA_MAC_VER_03,
  85         RTL_GIGA_MAC_VER_04,
  86         RTL_GIGA_MAC_VER_05,
  87         RTL_GIGA_MAC_VER_06,
  88         RTL_GIGA_MAC_VER_07,
  89         RTL_GIGA_MAC_VER_08,
  90         RTL_GIGA_MAC_VER_09,
  91         RTL_GIGA_MAC_VER_10,
  92         RTL_GIGA_MAC_VER_11,
  93         RTL_GIGA_MAC_VER_12,
  94         RTL_GIGA_MAC_VER_13,
  95         RTL_GIGA_MAC_VER_14,
  96         RTL_GIGA_MAC_VER_15,
  97         RTL_GIGA_MAC_VER_16,
  98         RTL_GIGA_MAC_VER_17,
  99         RTL_GIGA_MAC_VER_18,
 100         RTL_GIGA_MAC_VER_19,
 101         RTL_GIGA_MAC_VER_20,
 102         RTL_GIGA_MAC_VER_21,
 103         RTL_GIGA_MAC_VER_22,
 104         RTL_GIGA_MAC_VER_23,
 105         RTL_GIGA_MAC_VER_24,
 106         RTL_GIGA_MAC_VER_25,
 107         RTL_GIGA_MAC_VER_26,
 108         RTL_GIGA_MAC_VER_27,
 109         RTL_GIGA_MAC_VER_28,
 110         RTL_GIGA_MAC_VER_29,
 111         RTL_GIGA_MAC_VER_30,
 112         RTL_GIGA_MAC_VER_31,
 113         RTL_GIGA_MAC_VER_32,
 114         RTL_GIGA_MAC_VER_33,
 115         RTL_GIGA_MAC_VER_34,
 116         RTL_GIGA_MAC_VER_35,
 117         RTL_GIGA_MAC_VER_36,
 118         RTL_GIGA_MAC_VER_37,
 119         RTL_GIGA_MAC_VER_38,
 120         RTL_GIGA_MAC_VER_39,
 121         RTL_GIGA_MAC_VER_40,
 122         RTL_GIGA_MAC_VER_41,
 123         RTL_GIGA_MAC_VER_42,
 124         RTL_GIGA_MAC_VER_43,
 125         RTL_GIGA_MAC_VER_44,
 126         RTL_GIGA_MAC_VER_45,
 127         RTL_GIGA_MAC_VER_46,
 128         RTL_GIGA_MAC_VER_47,
 129         RTL_GIGA_MAC_VER_48,
 130         RTL_GIGA_MAC_VER_49,
 131         RTL_GIGA_MAC_VER_50,
 132         RTL_GIGA_MAC_VER_51,
 133         RTL_GIGA_MAC_NONE   = 0xff,
 134 };
 135
 136 #define JUMBO_1K        ETH_DATA_LEN
 137 #define JUMBO_4K        (4*1024 - ETH_HLEN - 2)
 138 #define JUMBO_6K        (6*1024 - ETH_HLEN - 2)
 139 #define JUMBO_7K        (7*1024 - ETH_HLEN - 2)
 140 #define JUMBO_9K        (9*1024 - ETH_HLEN - 2)
 141
 142 static const struct {
 143         const char *name;
 144         const char *fw_name;
 145 } rtl_chip_infos[] = {
 146         /* PCI devices. */
 147         [RTL_GIGA_MAC_VER_01] = {"RTL8169"                              },
 148         [RTL_GIGA_MAC_VER_02] = {"RTL8169s"                             },
 149         [RTL_GIGA_MAC_VER_03] = {"RTL8110s"                             },
 150         [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb"                     },
 151         [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc"                     },
 152         [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc"                     },
 153         /* PCI-E devices. */
 154         [RTL_GIGA_MAC_VER_07] = {"RTL8102e"                             },
 155         [RTL_GIGA_MAC_VER_08] = {"RTL8102e"                             },
 156         [RTL_GIGA_MAC_VER_09] = {"RTL8102e"                             },
 157         [RTL_GIGA_MAC_VER_10] = {"RTL8101e"                             },
 158         [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b"                       },
 159         [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b"                       },
 160         [RTL_GIGA_MAC_VER_13] = {"RTL8101e"                             },
 161         [RTL_GIGA_MAC_VER_14] = {"RTL8100e"                             },
 162         [RTL_GIGA_MAC_VER_15] = {"RTL8100e"                             },
 163         [RTL_GIGA_MAC_VER_16] = {"RTL8101e"                             },
 164         [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b"                       },
 165         [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp"                     },
 166         [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c"                       },
 167         [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c"                       },
 168         [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c"                       },
 169         [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c"                       },
 170         [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp"                     },
 171         [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp"                     },
 172         [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d",      FIRMWARE_8168D_1},
 173         [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d",      FIRMWARE_8168D_2},
 174         [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp"                     },
 175         [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp"                     },
 176         [RTL_GIGA_MAC_VER_29] = {"RTL8105e",            FIRMWARE_8105E_1},
 177         [RTL_GIGA_MAC_VER_30] = {"RTL8105e",            FIRMWARE_8105E_1},
 178         [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp"                     },
 179         [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e",      FIRMWARE_8168E_1},
 180         [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e",      FIRMWARE_8168E_2},
 181         [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl",  FIRMWARE_8168E_3},
 182         [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f",      FIRMWARE_8168F_1},
 183         [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f",      FIRMWARE_8168F_2},
 184         [RTL_GIGA_MAC_VER_37] = {"RTL8402",             FIRMWARE_8402_1 },
 185         [RTL_GIGA_MAC_VER_38] = {"RTL8411",             FIRMWARE_8411_1 },
 186         [RTL_GIGA_MAC_VER_39] = {"RTL8106e",            FIRMWARE_8106E_1},
 187         [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g",      FIRMWARE_8168G_2},
 188         [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g"                       },
 189         [RTL_GIGA_MAC_VER_42] = {"RTL8168g/8111g",      FIRMWARE_8168G_3},
 190         [RTL_GIGA_MAC_VER_43] = {"RTL8106e",            FIRMWARE_8106E_2},
 191         [RTL_GIGA_MAC_VER_44] = {"RTL8411",             FIRMWARE_8411_2 },
 192         [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h",      FIRMWARE_8168H_1},
 193         [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h",      FIRMWARE_8168H_2},
 194         [RTL_GIGA_MAC_VER_47] = {"RTL8107e",            FIRMWARE_8107E_1},
 195         [RTL_GIGA_MAC_VER_48] = {"RTL8107e",            FIRMWARE_8107E_2},
 196         [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep"                     },
 197         [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep"                     },
 198         [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep"                     },
 199 };
 200
 201 enum cfg_version {
 202         RTL_CFG_0 = 0x00,
 203         RTL_CFG_1,
 204         RTL_CFG_2
 205 };
 206
 207 static const struct pci_device_id rtl8169_pci_tbl[] = {
 208         { PCI_VDEVICE(REALTEK,  0x8129), RTL_CFG_0 },
 209         { PCI_VDEVICE(REALTEK,  0x8136), RTL_CFG_2 },
 210         { PCI_VDEVICE(REALTEK,  0x8161), RTL_CFG_1 },
 211         { PCI_VDEVICE(REALTEK,  0x8167), RTL_CFG_0 },
 212         { PCI_VDEVICE(REALTEK,  0x8168), RTL_CFG_1 },
 213         { PCI_VDEVICE(NCUBE,    0x8168), RTL_CFG_1 },
 214         { PCI_VDEVICE(REALTEK,  0x8169), RTL_CFG_0 },
 215         { PCI_VENDOR_ID_DLINK,  0x4300,
 216                 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 },
 217         { PCI_VDEVICE(DLINK,    0x4300), RTL_CFG_0 },
 218         { PCI_VDEVICE(DLINK,    0x4302), RTL_CFG_0 },
 219         { PCI_VDEVICE(AT,       0xc107), RTL_CFG_0 },
 220         { PCI_VDEVICE(USR,      0x0116), RTL_CFG_0 },
 221         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 222                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 223         { 0x0001,                               0x8168,
 224                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 225         {}
 226 };
 227
 228 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 229
 230 static int use_dac = -1;
 231 static struct {
 232         u32 msg_enable;
 233 } debug = { -1 };
 234
 235 enum rtl_registers {
 236         MAC0            = 0,    /* Ethernet hardware address. */
 237         MAC4            = 4,
 238         MAR0            = 8,    /* Multicast filter. */
 239         CounterAddrLow          = 0x10,
 240         CounterAddrHigh         = 0x14,
 241         TxDescStartAddrLow      = 0x20,
 242         TxDescStartAddrHigh     = 0x24,
 243         TxHDescStartAddrLow     = 0x28,
 244         TxHDescStartAddrHigh    = 0x2c,
 245         FLASH           = 0x30,
 246         ERSR            = 0x36,
 247         ChipCmd         = 0x37,
 248         TxPoll          = 0x38,
 249         IntrMask        = 0x3c,
 250         IntrStatus      = 0x3e,
 251
 252         TxConfig        = 0x40,
 253 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 254 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 255
 256         RxConfig        = 0x44,
 257 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 258 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 259 #define RXCFG_FIFO_SHIFT                13
 260                                         /* No threshold before first PCI xfer */
 261 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 262 #define RX_EARLY_OFF                    (1 << 11)
 263 #define RXCFG_DMA_SHIFT                 8
 264                                         /* Unlimited maximum PCI burst. */
 265 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 266
 267         RxMissed        = 0x4c,
 268         Cfg9346         = 0x50,
 269         Config0         = 0x51,
 270         Config1         = 0x52,
 271         Config2         = 0x53,
 272 #define PME_SIGNAL                      (1 << 5)        /* 8168c and later */
 273
 274         Config3         = 0x54,
 275         Config4         = 0x55,
 276         Config5         = 0x56,
 277         MultiIntr       = 0x5c,
 278         PHYAR           = 0x60,
 279         PHYstatus       = 0x6c,
 280         RxMaxSize       = 0xda,
 281         CPlusCmd        = 0xe0,
 282         IntrMitigate    = 0xe2,
 283
 284 #define RTL_COALESCE_MASK       0x0f
 285 #define RTL_COALESCE_SHIFT      4
 286 #define RTL_COALESCE_T_MAX      (RTL_COALESCE_MASK)
 287 #define RTL_COALESCE_FRAME_MAX  (RTL_COALESCE_MASK << 2)
 288
 289         RxDescAddrLow   = 0xe4,
 290         RxDescAddrHigh  = 0xe8,
 291         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 292
 293 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 294
 295         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 296
 297 #define TxPacketMax     (8064 >> 7)
 298 #define EarlySize       0x27
 299
 300         FuncEvent       = 0xf0,
 301         FuncEventMask   = 0xf4,
 302         FuncPresetState = 0xf8,
 303         IBCR0           = 0xf8,
 304         IBCR2           = 0xf9,
 305         IBIMR0          = 0xfa,
 306         IBISR0          = 0xfb,
 307         FuncForceEvent  = 0xfc,
 308 };
 309
 310 enum rtl8168_8101_registers {
 311         CSIDR                   = 0x64,
 312         CSIAR                   = 0x68,
 313 #define CSIAR_FLAG                      0x80000000
 314 #define CSIAR_WRITE_CMD                 0x80000000
 315 #define CSIAR_BYTE_ENABLE               0x0000f000
 316 #define CSIAR_ADDR_MASK                 0x00000fff
 317         PMCH                    = 0x6f,
 318         EPHYAR                  = 0x80,
 319 #define EPHYAR_FLAG                     0x80000000
 320 #define EPHYAR_WRITE_CMD                0x80000000
 321 #define EPHYAR_REG_MASK                 0x1f
 322 #define EPHYAR_REG_SHIFT                16
 323 #define EPHYAR_DATA_MASK                0xffff
 324         DLLPR                   = 0xd0,
 325 #define PFM_EN                          (1 << 6)
 326 #define TX_10M_PS_EN                    (1 << 7)
 327         DBG_REG                 = 0xd1,
 328 #define FIX_NAK_1                       (1 << 4)
 329 #define FIX_NAK_2                       (1 << 3)
 330         TWSI                    = 0xd2,
 331         MCU                     = 0xd3,
 332 #define NOW_IS_OOB                      (1 << 7)
 333 #define TX_EMPTY                        (1 << 5)
 334 #define RX_EMPTY                        (1 << 4)
 335 #define RXTX_EMPTY                      (TX_EMPTY | RX_EMPTY)
 336 #define EN_NDP                          (1 << 3)
 337 #define EN_OOB_RESET                    (1 << 2)
 338 #define LINK_LIST_RDY                   (1 << 1)
 339         EFUSEAR                 = 0xdc,
 340 #define EFUSEAR_FLAG                    0x80000000
 341 #define EFUSEAR_WRITE_CMD               0x80000000
 342 #define EFUSEAR_READ_CMD                0x00000000
 343 #define EFUSEAR_REG_MASK                0x03ff
 344 #define EFUSEAR_REG_SHIFT               8
 345 #define EFUSEAR_DATA_MASK               0xff
 346         MISC_1                  = 0xf2,
 347 #define PFM_D3COLD_EN                   (1 << 6)
 348 };
 349
 350 enum rtl8168_registers {
 351         LED_FREQ                = 0x1a,
 352         EEE_LED                 = 0x1b,
 353         ERIDR                   = 0x70,
 354         ERIAR                   = 0x74,
 355 #define ERIAR_FLAG                      0x80000000
 356 #define ERIAR_WRITE_CMD                 0x80000000
 357 #define ERIAR_READ_CMD                  0x00000000
 358 #define ERIAR_ADDR_BYTE_ALIGN           4
 359 #define ERIAR_TYPE_SHIFT                16
 360 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 361 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 362 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 363 #define ERIAR_OOB                       (0x02 << ERIAR_TYPE_SHIFT)
 364 #define ERIAR_MASK_SHIFT                12
 365 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 366 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 367 #define ERIAR_MASK_0100                 (0x4 << ERIAR_MASK_SHIFT)
 368 #define ERIAR_MASK_0101                 (0x5 << ERIAR_MASK_SHIFT)
 369 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 370         EPHY_RXER_NUM           = 0x7c,
 371         OCPDR                   = 0xb0, /* OCP GPHY access */
 372 #define OCPDR_WRITE_CMD                 0x80000000
 373 #define OCPDR_READ_CMD                  0x00000000
 374 #define OCPDR_REG_MASK                  0x7f
 375 #define OCPDR_GPHY_REG_SHIFT            16
 376 #define OCPDR_DATA_MASK                 0xffff
 377         OCPAR                   = 0xb4,
 378 #define OCPAR_FLAG                      0x80000000
 379 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 380 #define OCPAR_GPHY_READ_CMD             0x0000f060
 381         GPHY_OCP                = 0xb8,
 382         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 383         MISC                    = 0xf0, /* 8168e only. */
 384 #define TXPLA_RST                       (1 << 29)
 385 #define DISABLE_LAN_EN                  (1 << 23) /* Enable GPIO pin */
 386 #define PWM_EN                          (1 << 22)
 387 #define RXDV_GATED_EN                   (1 << 19)
 388 #define EARLY_TALLY_EN                  (1 << 16)
 389 };
 390
 391 enum rtl_register_content {
 392         /* InterruptStatusBits */
 393         SYSErr          = 0x8000,
 394         PCSTimeout      = 0x4000,
 395         SWInt           = 0x0100,
 396         TxDescUnavail   = 0x0080,
 397         RxFIFOOver      = 0x0040,
 398         LinkChg         = 0x0020,
 399         RxOverflow      = 0x0010,
 400         TxErr           = 0x0008,
 401         TxOK            = 0x0004,
 402         RxErr           = 0x0002,
 403         RxOK            = 0x0001,
 404
 405         /* RxStatusDesc */
 406         RxBOVF  = (1 << 24),
 407         RxFOVF  = (1 << 23),
 408         RxRWT   = (1 << 22),
 409         RxRES   = (1 << 21),
 410         RxRUNT  = (1 << 20),
 411         RxCRC   = (1 << 19),
 412
 413         /* ChipCmdBits */
 414         StopReq         = 0x80,
 415         CmdReset        = 0x10,
 416         CmdRxEnb        = 0x08,
 417         CmdTxEnb        = 0x04,
 418         RxBufEmpty      = 0x01,
 419
 420         /* TXPoll register p.5 */
 421         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 422         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 423         FSWInt          = 0x01,         /* Forced software interrupt */
 424
 425         /* Cfg9346Bits */
 426         Cfg9346_Lock    = 0x00,
 427         Cfg9346_Unlock  = 0xc0,
 428
 429         /* rx_mode_bits */
 430         AcceptErr       = 0x20,
 431         AcceptRunt      = 0x10,
 432         AcceptBroadcast = 0x08,
 433         AcceptMulticast = 0x04,
 434         AcceptMyPhys    = 0x02,
 435         AcceptAllPhys   = 0x01,
 436 #define RX_CONFIG_ACCEPT_MASK           0x3f
 437
 438         /* TxConfigBits */
 439         TxInterFrameGapShift = 24,
 440         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 441
 442         /* Config1 register p.24 */
 443         LEDS1           = (1 << 7),
 444         LEDS0           = (1 << 6),
 445         Speed_down      = (1 << 4),
 446         MEMMAP          = (1 << 3),
 447         IOMAP           = (1 << 2),
 448         VPD             = (1 << 1),
 449         PMEnable        = (1 << 0),     /* Power Management Enable */
 450
 451         /* Config2 register p. 25 */
 452         ClkReqEn        = (1 << 7),     /* Clock Request Enable */
 453         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
 454         PCI_Clock_66MHz = 0x01,
 455         PCI_Clock_33MHz = 0x00,
 456
 457         /* Config3 register p.25 */
 458         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 459         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 460         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
 461         Rdy_to_L23      = (1 << 1),     /* L23 Enable */
 462         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 463
 464         /* Config4 register */
 465         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
 466
 467         /* Config5 register p.27 */
 468         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 469         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 470         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 471         Spi_en          = (1 << 3),
 472         LanWake         = (1 << 1),     /* LanWake enable/disable */
 473         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 474         ASPM_en         = (1 << 0),     /* ASPM enable */
 475
 476         /* CPlusCmd p.31 */
 477         EnableBist      = (1 << 15),    // 8168 8101
 478         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 479         Normal_mode     = (1 << 13),    // unused
 480         Force_half_dup  = (1 << 12),    // 8168 8101
 481         Force_rxflow_en = (1 << 11),    // 8168 8101
 482         Force_txflow_en = (1 << 10),    // 8168 8101
 483         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 484         ASF             = (1 << 8),     // 8168 8101
 485         PktCntrDisable  = (1 << 7),     // 8168 8101
 486         Mac_dbgo_sel    = 0x001c,       // 8168
 487         RxVlan          = (1 << 6),
 488         RxChkSum        = (1 << 5),
 489         PCIDAC          = (1 << 4),
 490         PCIMulRW        = (1 << 3),
 491 #define INTT_MASK       GENMASK(1, 0)
 492         INTT_0          = 0x0000,       // 8168
 493         INTT_1          = 0x0001,       // 8168
 494         INTT_2          = 0x0002,       // 8168
 495         INTT_3          = 0x0003,       // 8168
 496
 497         /* rtl8169_PHYstatus */
 498         TBI_Enable      = 0x80,
 499         TxFlowCtrl      = 0x40,
 500         RxFlowCtrl      = 0x20,
 501         _1000bpsF       = 0x10,
 502         _100bps         = 0x08,
 503         _10bps          = 0x04,
 504         LinkStatus      = 0x02,
 505         FullDup         = 0x01,
 506
 507         /* _TBICSRBit */
 508         TBILinkOK       = 0x02000000,
 509
 510         /* ResetCounterCommand */
 511         CounterReset    = 0x1,
 512
 513         /* DumpCounterCommand */
 514         CounterDump     = 0x8,
 515
 516         /* magic enable v2 */
 517         MagicPacket_v2  = (1 << 16),    /* Wake up when receives a Magic Packet */
 518 };
 519
 520 enum rtl_desc_bit {
 521         /* First doubleword. */
 522         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 523         RingEnd         = (1 << 30), /* End of descriptor ring */
 524         FirstFrag       = (1 << 29), /* First segment of a packet */
 525         LastFrag        = (1 << 28), /* Final segment of a packet */
 526 };
 527
 528 /* Generic case. */
 529 enum rtl_tx_desc_bit {
 530         /* First doubleword. */
 531         TD_LSO          = (1 << 27),            /* Large Send Offload */
 532 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 533
 534         /* Second doubleword. */
 535         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 536 };
 537
 538 /* 8169, 8168b and 810x except 8102e. */
 539 enum rtl_tx_desc_bit_0 {
 540         /* First doubleword. */
 541 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 542         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 543         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 544         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 545 };
 546
 547 /* 8102e, 8168c and beyond. */
 548 enum rtl_tx_desc_bit_1 {
 549         /* First doubleword. */
 550         TD1_GTSENV4     = (1 << 26),            /* Giant Send for IPv4 */
 551         TD1_GTSENV6     = (1 << 25),            /* Giant Send for IPv6 */
 552 #define GTTCPHO_SHIFT                   18
 553 #define GTTCPHO_MAX                     0x7fU
 554
 555         /* Second doubleword. */
 556 #define TCPHO_SHIFT                     18
 557 #define TCPHO_MAX                       0x3ffU
 558 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 559         TD1_IPv6_CS     = (1 << 28),            /* Calculate IPv6 checksum */
 560         TD1_IPv4_CS     = (1 << 29),            /* Calculate IPv4 checksum */
 561         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 562         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 563 };
 564
 565 enum rtl_rx_desc_bit {
 566         /* Rx private */
 567         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 568         PID0            = (1 << 17), /* Protocol ID bit 0/2 */
 569
 570 #define RxProtoUDP      (PID1)
 571 #define RxProtoTCP      (PID0)
 572 #define RxProtoIP       (PID1 | PID0)
 573 #define RxProtoMask     RxProtoIP
 574
 575         IPFail          = (1 << 16), /* IP checksum failed */
 576         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 577         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 578         RxVlanTag       = (1 << 16), /* VLAN tag available */
 579 };
 580
 581 #define RsvdMask        0x3fffc000
 582 #define CPCMD_QUIRK_MASK        (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
 583
 584 struct TxDesc {
 585         __le32 opts1;
 586         __le32 opts2;
 587         __le64 addr;
 588 };
 589
 590 struct RxDesc {
 591         __le32 opts1;
 592         __le32 opts2;
 593         __le64 addr;
 594 };
 595
 596 struct ring_info {
 597         struct sk_buff  *skb;
 598         u32             len;
 599 };
 600
 601 struct rtl8169_counters {
 602         __le64  tx_packets;
 603         __le64  rx_packets;
 604         __le64  tx_errors;
 605         __le32  rx_errors;
 606         __le16  rx_missed;
 607         __le16  align_errors;
 608         __le32  tx_one_collision;
 609         __le32  tx_multi_collision;
 610         __le64  rx_unicast;
 611         __le64  rx_broadcast;
 612         __le32  rx_multicast;
 613         __le16  tx_aborted;
 614         __le16  tx_underun;
 615 };
 616
 617 struct rtl8169_tc_offsets {
 618         bool    inited;
 619         __le64  tx_errors;
 620         __le32  tx_multi_collision;
 621         __le16  tx_aborted;
 622 };
 623
 624 enum rtl_flag {
 625         RTL_FLAG_TASK_ENABLED = 0,
 626         RTL_FLAG_TASK_RESET_PENDING,
 627         RTL_FLAG_MAX
 628 };
 629
 630 struct rtl8169_stats {
 631         u64                     packets;
 632         u64                     bytes;
 633         struct u64_stats_sync   syncp;
 634 };
 635
 636 struct rtl8169_private {
 637         void __iomem *mmio_addr;        /* memory map physical address */
 638         struct pci_dev *pci_dev;
 639         struct net_device *dev;
 640         struct napi_struct napi;
 641         u32 msg_enable;
 642         u16 mac_version;
 643         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 644         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 645         u32 dirty_tx;
 646         struct rtl8169_stats rx_stats;
 647         struct rtl8169_stats tx_stats;
 648         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 649         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 650         dma_addr_t TxPhyAddr;
 651         dma_addr_t RxPhyAddr;
 652         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
 653         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 654         u16 cp_cmd;
 655
 656         u16 irq_mask;
 657         const struct rtl_coalesce_info *coalesce_info;
 658         struct clk *clk;
 659
 660         struct mdio_ops {
 661                 void (*write)(struct rtl8169_private *, int, int);
 662                 int (*read)(struct rtl8169_private *, int);
 663         } mdio_ops;
 664
 665         struct jumbo_ops {
 666                 void (*enable)(struct rtl8169_private *);
 667                 void (*disable)(struct rtl8169_private *);
 668         } jumbo_ops;
 669
 670         void (*hw_start)(struct rtl8169_private *tp);
 671         bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
 672
 673         struct {
 674                 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
 675                 struct mutex mutex;
 676                 struct work_struct work;
 677         } wk;
 678
 679         unsigned supports_gmii:1;
 680         struct mii_bus *mii_bus;
 681         dma_addr_t counters_phys_addr;
 682         struct rtl8169_counters *counters;
 683         struct rtl8169_tc_offsets tc_offset;
 684         u32 saved_wolopts;
 685
 686         struct rtl_fw {
 687                 const struct firmware *fw;
 688
 689 #define RTL_VER_SIZE            32
 690
 691                 char version[RTL_VER_SIZE];
 692
 693                 struct rtl_fw_phy_action {
 694                         __le32 *code;
 695                         size_t size;
 696                 } phy_action;
 697         } *rtl_fw;
 698 #define RTL_FIRMWARE_UNKNOWN    ERR_PTR(-EAGAIN)
 699
 700         u32 ocp_base;
 701 };
 702
 703 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 704 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 705 module_param(use_dac, int, 0);
 706 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 707 module_param_named(debug, debug.msg_enable, int, 0);
 708 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 709 MODULE_LICENSE("GPL");
 710 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 711 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 712 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 713 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 714 MODULE_FIRMWARE(FIRMWARE_8168E_3);
 715 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 716 MODULE_FIRMWARE(FIRMWARE_8168F_1);
 717 MODULE_FIRMWARE(FIRMWARE_8168F_2);
 718 MODULE_FIRMWARE(FIRMWARE_8402_1);
 719 MODULE_FIRMWARE(FIRMWARE_8411_1);
 720 MODULE_FIRMWARE(FIRMWARE_8411_2);
 721 MODULE_FIRMWARE(FIRMWARE_8106E_1);
 722 MODULE_FIRMWARE(FIRMWARE_8106E_2);
 723 MODULE_FIRMWARE(FIRMWARE_8168G_2);
 724 MODULE_FIRMWARE(FIRMWARE_8168G_3);
 725 MODULE_FIRMWARE(FIRMWARE_8168H_1);
 726 MODULE_FIRMWARE(FIRMWARE_8168H_2);
 727 MODULE_FIRMWARE(FIRMWARE_8107E_1);
 728 MODULE_FIRMWARE(FIRMWARE_8107E_2);
 729
 730 static inline struct device *tp_to_dev(struct rtl8169_private *tp)
 731 {
 732         return &tp->pci_dev->dev;
 733 }
 734
 735 static void rtl_lock_work(struct rtl8169_private *tp)
 736 {
 737         mutex_lock(&tp->wk.mutex);
 738 }
 739
 740 static void rtl_unlock_work(struct rtl8169_private *tp)
 741 {
 742         mutex_unlock(&tp->wk.mutex);
 743 }
 744
 745 static void rtl_tx_performance_tweak(struct rtl8169_private *tp, u16 force)
 746 {
 747         pcie_capability_clear_and_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
 748                                            PCI_EXP_DEVCTL_READRQ, force);
 749 }
 750
 751 struct rtl_cond {
 752         bool (*check)(struct rtl8169_private *);
 753         const char *msg;
 754 };
 755
 756 static void rtl_udelay(unsigned int d)
 757 {
 758         udelay(d);
 759 }
 760
 761 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
 762                           void (*delay)(unsigned int), unsigned int d, int n,
 763                           bool high)
 764 {
 765         int i;
 766
 767         for (i = 0; i < n; i++) {
 768                 delay(d);
 769                 if (c->check(tp) == high)
 770                         return true;
 771         }
 772         netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
 773                   c->msg, !high, n, d);
 774         return false;
 775 }
 776
 777 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
 778                                       const struct rtl_cond *c,
 779                                       unsigned int d, int n)
 780 {
 781         return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
 782 }
 783
 784 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
 785                                      const struct rtl_cond *c,
 786                                      unsigned int d, int n)
 787 {
 788         return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
 789 }
 790
 791 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
 792                                       const struct rtl_cond *c,
 793                                       unsigned int d, int n)
 794 {
 795         return rtl_loop_wait(tp, c, msleep, d, n, true);
 796 }
 797
 798 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
 799                                      const struct rtl_cond *c,
 800                                      unsigned int d, int n)
 801 {
 802         return rtl_loop_wait(tp, c, msleep, d, n, false);
 803 }
 804
 805 #define DECLARE_RTL_COND(name)                          \
 806 static bool name ## _check(struct rtl8169_private *);   \
 807                                                         \
 808 static const struct rtl_cond name = {                   \
 809         .check  = name ## _check,                       \
 810         .msg    = #name                                 \
 811 };                                                      \
 812                                                         \
 813 static bool name ## _check(struct rtl8169_private *tp)
 814
 815 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
 816 {
 817         if (reg & 0xffff0001) {
 818                 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
 819                 return true;
 820         }
 821         return false;
 822 }
 823
 824 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
 825 {
 826         return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
 827 }
 828
 829 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 830 {
 831         if (rtl_ocp_reg_failure(tp, reg))
 832                 return;
 833
 834         RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
 835
 836         rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
 837 }
 838
 839 static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
 840 {
 841         if (rtl_ocp_reg_failure(tp, reg))
 842                 return 0;
 843
 844         RTL_W32(tp, GPHY_OCP, reg << 15);
 845
 846         return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
 847                 (RTL_R32(tp, GPHY_OCP) & 0xffff) : ~0;
 848 }
 849
 850 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 851 {
 852         if (rtl_ocp_reg_failure(tp, reg))
 853                 return;
 854
 855         RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
 856 }
 857
 858 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
 859 {
 860         if (rtl_ocp_reg_failure(tp, reg))
 861                 return 0;
 862
 863         RTL_W32(tp, OCPDR, reg << 15);
 864
 865         return RTL_R32(tp, OCPDR);
 866 }
 867
 868 #define OCP_STD_PHY_BASE        0xa400
 869
 870 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
 871 {
 872         if (reg == 0x1f) {
 873                 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
 874                 return;
 875         }
 876
 877         if (tp->ocp_base != OCP_STD_PHY_BASE)
 878                 reg -= 0x10;
 879
 880         r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
 881 }
 882
 883 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
 884 {
 885         if (tp->ocp_base != OCP_STD_PHY_BASE)
 886                 reg -= 0x10;
 887
 888         return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
 889 }
 890
 891 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
 892 {
 893         if (reg == 0x1f) {
 894                 tp->ocp_base = value << 4;
 895                 return;
 896         }
 897
 898         r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
 899 }
 900
 901 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
 902 {
 903         return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
 904 }
 905
 906 DECLARE_RTL_COND(rtl_phyar_cond)
 907 {
 908         return RTL_R32(tp, PHYAR) & 0x80000000;
 909 }
 910
 911 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
 912 {
 913         RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
 914
 915         rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
 916         /*
 917          * According to hardware specs a 20us delay is required after write
 918          * complete indication, but before sending next command.
 919          */
 920         udelay(20);
 921 }
 922
 923 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
 924 {
 925         int value;
 926
 927         RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
 928
 929         value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
 930                 RTL_R32(tp, PHYAR) & 0xffff : ~0;
 931
 932         /*
 933          * According to hardware specs a 20us delay is required after read
 934          * complete indication, but before sending next command.
 935          */
 936         udelay(20);
 937
 938         return value;
 939 }
 940
 941 DECLARE_RTL_COND(rtl_ocpar_cond)
 942 {
 943         return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
 944 }
 945
 946 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
 947 {
 948         RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
 949         RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
 950         RTL_W32(tp, EPHY_RXER_NUM, 0);
 951
 952         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
 953 }
 954
 955 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
 956 {
 957         r8168dp_1_mdio_access(tp, reg,
 958                               OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
 959 }
 960
 961 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
 962 {
 963         r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
 964
 965         mdelay(1);
 966         RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
 967         RTL_W32(tp, EPHY_RXER_NUM, 0);
 968
 969         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
 970                 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : ~0;
 971 }
 972
 973 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
 974
 975 static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
 976 {
 977         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
 978 }
 979
 980 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
 981 {
 982         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
 983 }
 984
 985 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
 986 {
 987         r8168dp_2_mdio_start(tp);
 988
 989         r8169_mdio_write(tp, reg, value);
 990
 991         r8168dp_2_mdio_stop(tp);
 992 }
 993
 994 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
 995 {
 996         int value;
 997
 998         r8168dp_2_mdio_start(tp);
 999
1000         value = r8169_mdio_read(tp, reg);
1001
1002         r8168dp_2_mdio_stop(tp);
1003
1004         return value;
1005 }
1006
1007 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1008 {
1009         tp->mdio_ops.write(tp, location, val);
1010 }
1011
1012 static int rtl_readphy(struct rtl8169_private *tp, int location)
1013 {
1014         return tp->mdio_ops.read(tp, location);
1015 }
1016
1017 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1018 {
1019         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1020 }
1021
1022 static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1023 {
1024         int val;
1025
1026         val = rtl_readphy(tp, reg_addr);
1027         rtl_writephy(tp, reg_addr, (val & ~m) | p);
1028 }
1029
1030 DECLARE_RTL_COND(rtl_ephyar_cond)
1031 {
1032         return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1033 }
1034
1035 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1036 {
1037         RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1038                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1039
1040         rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1041
1042         udelay(10);
1043 }
1044
1045 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1046 {
1047         RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1048
1049         return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1050                 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1051 }
1052
1053 DECLARE_RTL_COND(rtl_eriar_cond)
1054 {
1055         return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
1056 }
1057
1058 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1059                           u32 val, int type)
1060 {
1061         BUG_ON((addr & 3) || (mask == 0));
1062         RTL_W32(tp, ERIDR, val);
1063         RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1064
1065         rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1066 }
1067
1068 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1069 {
1070         RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1071
1072         return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1073                 RTL_R32(tp, ERIDR) : ~0;
1074 }
1075
1076 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1077                          u32 m, int type)
1078 {
1079         u32 val;
1080
1081         val = rtl_eri_read(tp, addr, type);
1082         rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
1083 }
1084
1085 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1086 {
1087         RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1088         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1089                 RTL_R32(tp, OCPDR) : ~0;
1090 }
1091
1092 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1093 {
1094         return rtl_eri_read(tp, reg, ERIAR_OOB);
1095 }
1096
1097 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1098                               u32 data)
1099 {
1100         RTL_W32(tp, OCPDR, data);
1101         RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1102         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1103 }
1104
1105 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1106                               u32 data)
1107 {
1108         rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1109                       data, ERIAR_OOB);
1110 }
1111
1112 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd)
1113 {
1114         rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd, ERIAR_EXGMAC);
1115
1116         r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001);
1117 }
1118
1119 #define OOB_CMD_RESET           0x00
1120 #define OOB_CMD_DRIVER_START    0x05
1121 #define OOB_CMD_DRIVER_STOP     0x06
1122
1123 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1124 {
1125         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1126 }
1127
1128 DECLARE_RTL_COND(rtl_dp_ocp_read_cond)
1129 {
1130         u16 reg;
1131
1132         reg = rtl8168_get_ocp_reg(tp);
1133
1134         return r8168dp_ocp_read(tp, 0x0f, reg) & 0x00000800;
1135 }
1136
1137 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1138 {
1139         return r8168ep_ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1140 }
1141
1142 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1143 {
1144         return RTL_R8(tp, IBISR0) & 0x20;
1145 }
1146
1147 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1148 {
1149         RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1150         rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000);
1151         RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1152         RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1153 }
1154
1155 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1156 {
1157         r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START);
1158         rtl_msleep_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10, 10);
1159 }
1160
1161 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1162 {
1163         r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1164         r8168ep_ocp_write(tp, 0x01, 0x30,
1165                           r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
1166         rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1167 }
1168
1169 static void rtl8168_driver_start(struct rtl8169_private *tp)
1170 {
1171         switch (tp->mac_version) {
1172         case RTL_GIGA_MAC_VER_27:
1173         case RTL_GIGA_MAC_VER_28:
1174         case RTL_GIGA_MAC_VER_31:
1175                 rtl8168dp_driver_start(tp);
1176                 break;
1177         case RTL_GIGA_MAC_VER_49:
1178         case RTL_GIGA_MAC_VER_50:
1179         case RTL_GIGA_MAC_VER_51:
1180                 rtl8168ep_driver_start(tp);
1181                 break;
1182         default:
1183                 BUG();
1184                 break;
1185         }
1186 }
1187
1188 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1189 {
1190         r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1191         rtl_msleep_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10, 10);
1192 }
1193
1194 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1195 {
1196         rtl8168ep_stop_cmac(tp);
1197         r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1198         r8168ep_ocp_write(tp, 0x01, 0x30,
1199                           r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
1200         rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1201 }
1202
1203 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1204 {
1205         switch (tp->mac_version) {
1206         case RTL_GIGA_MAC_VER_27:
1207         case RTL_GIGA_MAC_VER_28:
1208         case RTL_GIGA_MAC_VER_31:
1209                 rtl8168dp_driver_stop(tp);
1210                 break;
1211         case RTL_GIGA_MAC_VER_49:
1212         case RTL_GIGA_MAC_VER_50:
1213         case RTL_GIGA_MAC_VER_51:
1214                 rtl8168ep_driver_stop(tp);
1215                 break;
1216         default:
1217                 BUG();
1218                 break;
1219         }
1220 }
1221
1222 static bool r8168dp_check_dash(struct rtl8169_private *tp)
1223 {
1224         u16 reg = rtl8168_get_ocp_reg(tp);
1225
1226         return !!(r8168dp_ocp_read(tp, 0x0f, reg) & 0x00008000);
1227 }
1228
1229 static bool r8168ep_check_dash(struct rtl8169_private *tp)
1230 {
1231         return !!(r8168ep_ocp_read(tp, 0x0f, 0x128) & 0x00000001);
1232 }
1233
1234 static bool r8168_check_dash(struct rtl8169_private *tp)
1235 {
1236         switch (tp->mac_version) {
1237         case RTL_GIGA_MAC_VER_27:
1238         case RTL_GIGA_MAC_VER_28:
1239         case RTL_GIGA_MAC_VER_31:
1240                 return r8168dp_check_dash(tp);
1241         case RTL_GIGA_MAC_VER_49:
1242         case RTL_GIGA_MAC_VER_50:
1243         case RTL_GIGA_MAC_VER_51:
1244                 return r8168ep_check_dash(tp);
1245         default:
1246                 return false;
1247         }
1248 }
1249
1250 struct exgmac_reg {
1251         u16 addr;
1252         u16 mask;
1253         u32 val;
1254 };
1255
1256 static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
1257                                    const struct exgmac_reg *r, int len)
1258 {
1259         while (len-- > 0) {
1260                 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1261                 r++;
1262         }
1263 }
1264
1265 DECLARE_RTL_COND(rtl_efusear_cond)
1266 {
1267         return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1268 }
1269
1270 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1271 {
1272         RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1273
1274         return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1275                 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1276 }
1277
1278 static u16 rtl_get_events(struct rtl8169_private *tp)
1279 {
1280         return RTL_R16(tp, IntrStatus);
1281 }
1282
1283 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1284 {
1285         RTL_W16(tp, IntrStatus, bits);
1286 }
1287
1288 static void rtl_irq_disable(struct rtl8169_private *tp)
1289 {
1290         RTL_W16(tp, IntrMask, 0);
1291 }
1292
1293 #define RTL_EVENT_NAPI_RX       (RxOK | RxErr)
1294 #define RTL_EVENT_NAPI_TX       (TxOK | TxErr)
1295 #define RTL_EVENT_NAPI          (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1296
1297 static void rtl_irq_enable(struct rtl8169_private *tp)
1298 {
1299         RTL_W16(tp, IntrMask, tp->irq_mask);
1300 }
1301
1302 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1303 {
1304         rtl_irq_disable(tp);
1305         rtl_ack_events(tp, 0xffff);
1306         /* PCI commit */
1307         RTL_R8(tp, ChipCmd);
1308 }
1309
1310 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1311 {
1312         struct net_device *dev = tp->dev;
1313         struct phy_device *phydev = dev->phydev;
1314
1315         if (!netif_running(dev))
1316                 return;
1317
1318         if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1319             tp->mac_version == RTL_GIGA_MAC_VER_38) {
1320                 if (phydev->speed == SPEED_1000) {
1321                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1322                                       ERIAR_EXGMAC);
1323                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1324                                       ERIAR_EXGMAC);
1325                 } else if (phydev->speed == SPEED_100) {
1326                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1327                                       ERIAR_EXGMAC);
1328                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1329                                       ERIAR_EXGMAC);
1330                 } else {
1331                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1332                                       ERIAR_EXGMAC);
1333                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1334                                       ERIAR_EXGMAC);
1335                 }
1336                 /* Reset packet filter */
1337                 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1338                              ERIAR_EXGMAC);
1339                 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1340                              ERIAR_EXGMAC);
1341         } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1342                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
1343                 if (phydev->speed == SPEED_1000) {
1344                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1345                                       ERIAR_EXGMAC);
1346                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1347                                       ERIAR_EXGMAC);
1348                 } else {
1349                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1350                                       ERIAR_EXGMAC);
1351                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1352                                       ERIAR_EXGMAC);
1353                 }
1354         } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1355                 if (phydev->speed == SPEED_10) {
1356                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1357                                       ERIAR_EXGMAC);
1358                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1359                                       ERIAR_EXGMAC);
1360                 } else {
1361                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1362                                       ERIAR_EXGMAC);
1363                 }
1364         }
1365 }
1366
1367 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1368
1369 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1370 {
1371         u8 options;
1372         u32 wolopts = 0;
1373
1374         options = RTL_R8(tp, Config1);
1375         if (!(options & PMEnable))
1376                 return 0;
1377
1378         options = RTL_R8(tp, Config3);
1379         if (options & LinkUp)
1380                 wolopts |= WAKE_PHY;
1381         switch (tp->mac_version) {
1382         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
1383         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1384                 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
1385                         wolopts |= WAKE_MAGIC;
1386                 break;
1387         default:
1388                 if (options & MagicPacket)
1389                         wolopts |= WAKE_MAGIC;
1390                 break;
1391         }
1392
1393         options = RTL_R8(tp, Config5);
1394         if (options & UWF)
1395                 wolopts |= WAKE_UCAST;
1396         if (options & BWF)
1397                 wolopts |= WAKE_BCAST;
1398         if (options & MWF)
1399                 wolopts |= WAKE_MCAST;
1400
1401         return wolopts;
1402 }
1403
1404 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1405 {
1406         struct rtl8169_private *tp = netdev_priv(dev);
1407
1408         rtl_lock_work(tp);
1409         wol->supported = WAKE_ANY;
1410         wol->wolopts = tp->saved_wolopts;
1411         rtl_unlock_work(tp);
1412 }
1413
1414 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1415 {
1416         unsigned int i, tmp;
1417         static const struct {
1418                 u32 opt;
1419                 u16 reg;
1420                 u8  mask;
1421         } cfg[] = {
1422                 { WAKE_PHY,   Config3, LinkUp },
1423                 { WAKE_UCAST, Config5, UWF },
1424                 { WAKE_BCAST, Config5, BWF },
1425                 { WAKE_MCAST, Config5, MWF },
1426                 { WAKE_ANY,   Config5, LanWake },
1427                 { WAKE_MAGIC, Config3, MagicPacket }
1428         };
1429         u8 options;
1430
1431         RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
1432
1433         switch (tp->mac_version) {
1434         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
1435         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1436                 tmp = ARRAY_SIZE(cfg) - 1;
1437                 if (wolopts & WAKE_MAGIC)
1438                         rtl_w0w1_eri(tp,
1439                                      0x0dc,
1440                                      ERIAR_MASK_0100,
1441                                      MagicPacket_v2,
1442                                      0x0000,
1443                                      ERIAR_EXGMAC);
1444                 else
1445                         rtl_w0w1_eri(tp,
1446                                      0x0dc,
1447                                      ERIAR_MASK_0100,
1448                                      0x0000,
1449                                      MagicPacket_v2,
1450                                      ERIAR_EXGMAC);
1451                 break;
1452         default:
1453                 tmp = ARRAY_SIZE(cfg);
1454                 break;
1455         }
1456
1457         for (i = 0; i < tmp; i++) {
1458                 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
1459                 if (wolopts & cfg[i].opt)
1460                         options |= cfg[i].mask;
1461                 RTL_W8(tp, cfg[i].reg, options);
1462         }
1463
1464         switch (tp->mac_version) {
1465         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1466                 options = RTL_R8(tp, Config1) & ~PMEnable;
1467                 if (wolopts)
1468                         options |= PMEnable;
1469                 RTL_W8(tp, Config1, options);
1470                 break;
1471         default:
1472                 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
1473                 if (wolopts)
1474                         options |= PME_SIGNAL;
1475                 RTL_W8(tp, Config2, options);
1476                 break;
1477         }
1478
1479         RTL_W8(tp, Cfg9346, Cfg9346_Lock);
1480
1481         device_set_wakeup_enable(tp_to_dev(tp), wolopts);
1482 }
1483
1484 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1485 {
1486         struct rtl8169_private *tp = netdev_priv(dev);
1487         struct device *d = tp_to_dev(tp);
1488
1489         if (wol->wolopts & ~WAKE_ANY)
1490                 return -EINVAL;
1491
1492         pm_runtime_get_noresume(d);
1493
1494         rtl_lock_work(tp);
1495
1496         tp->saved_wolopts = wol->wolopts;
1497
1498         if (pm_runtime_active(d))
1499                 __rtl8169_set_wol(tp, tp->saved_wolopts);
1500
1501         rtl_unlock_work(tp);
1502
1503         pm_runtime_put_noidle(d);
1504
1505         return 0;
1506 }
1507
1508 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1509 {
1510         return rtl_chip_infos[tp->mac_version].fw_name;
1511 }
1512
1513 static void rtl8169_get_drvinfo(struct net_device *dev,
1514                                 struct ethtool_drvinfo *info)
1515 {
1516         struct rtl8169_private *tp = netdev_priv(dev);
1517         struct rtl_fw *rtl_fw = tp->rtl_fw;
1518
1519         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1520         strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1521         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1522         if (!IS_ERR_OR_NULL(rtl_fw))
1523                 strlcpy(info->fw_version, rtl_fw->version,
1524                         sizeof(info->fw_version));
1525 }
1526
1527 static int rtl8169_get_regs_len(struct net_device *dev)
1528 {
1529         return R8169_REGS_SIZE;
1530 }
1531
1532 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1533         netdev_features_t features)
1534 {
1535         struct rtl8169_private *tp = netdev_priv(dev);
1536
1537         if (dev->mtu > TD_MSS_MAX)
1538                 features &= ~NETIF_F_ALL_TSO;
1539
1540         if (dev->mtu > JUMBO_1K &&
1541             tp->mac_version > RTL_GIGA_MAC_VER_06)
1542                 features &= ~NETIF_F_IP_CSUM;
1543
1544         return features;
1545 }
1546
1547 static int rtl8169_set_features(struct net_device *dev,
1548                                 netdev_features_t features)
1549 {
1550         struct rtl8169_private *tp = netdev_priv(dev);
1551         u32 rx_config;
1552
1553         rtl_lock_work(tp);
1554
1555         rx_config = RTL_R32(tp, RxConfig);
1556         if (features & NETIF_F_RXALL)
1557                 rx_config |= (AcceptErr | AcceptRunt);
1558         else
1559                 rx_config &= ~(AcceptErr | AcceptRunt);
1560
1561         RTL_W32(tp, RxConfig, rx_config);
1562
1563         if (features & NETIF_F_RXCSUM)
1564                 tp->cp_cmd |= RxChkSum;
1565         else
1566                 tp->cp_cmd &= ~RxChkSum;
1567
1568         if (features & NETIF_F_HW_VLAN_CTAG_RX)
1569                 tp->cp_cmd |= RxVlan;
1570         else
1571                 tp->cp_cmd &= ~RxVlan;
1572
1573         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1574         RTL_R16(tp, CPlusCmd);
1575
1576         rtl_unlock_work(tp);
1577
1578         return 0;
1579 }
1580
1581 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1582 {
1583         return (skb_vlan_tag_present(skb)) ?
1584                 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1585 }
1586
1587 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1588 {
1589         u32 opts2 = le32_to_cpu(desc->opts2);
1590
1591         if (opts2 & RxVlanTag)
1592                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1593 }
1594
1595 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1596                              void *p)
1597 {
1598         struct rtl8169_private *tp = netdev_priv(dev);
1599         u32 __iomem *data = tp->mmio_addr;
1600         u32 *dw = p;
1601         int i;
1602
1603         rtl_lock_work(tp);
1604         for (i = 0; i < R8169_REGS_SIZE; i += 4)
1605                 memcpy_fromio(dw++, data++, 4);
1606         rtl_unlock_work(tp);
1607 }
1608
1609 static u32 rtl8169_get_msglevel(struct net_device *dev)
1610 {
1611         struct rtl8169_private *tp = netdev_priv(dev);
1612
1613         return tp->msg_enable;
1614 }
1615
1616 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1617 {
1618         struct rtl8169_private *tp = netdev_priv(dev);
1619
1620         tp->msg_enable = value;
1621 }
1622
1623 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1624         "tx_packets",
1625         "rx_packets",
1626         "tx_errors",
1627         "rx_errors",
1628         "rx_missed",
1629         "align_errors",
1630         "tx_single_collisions",
1631         "tx_multi_collisions",
1632         "unicast",
1633         "broadcast",
1634         "multicast",
1635         "tx_aborted",
1636         "tx_underrun",
1637 };
1638
1639 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1640 {
1641         switch (sset) {
1642         case ETH_SS_STATS:
1643                 return ARRAY_SIZE(rtl8169_gstrings);
1644         default:
1645                 return -EOPNOTSUPP;
1646         }
1647 }
1648
1649 DECLARE_RTL_COND(rtl_counters_cond)
1650 {
1651         return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
1652 }
1653
1654 static bool rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
1655 {
1656         dma_addr_t paddr = tp->counters_phys_addr;
1657         u32 cmd;
1658
1659         RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
1660         RTL_R32(tp, CounterAddrHigh);
1661         cmd = (u64)paddr & DMA_BIT_MASK(32);
1662         RTL_W32(tp, CounterAddrLow, cmd);
1663         RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
1664
1665         return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
1666 }
1667
1668 static bool rtl8169_reset_counters(struct rtl8169_private *tp)
1669 {
1670         /*
1671          * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
1672          * tally counters.
1673          */
1674         if (tp->mac_version < RTL_GIGA_MAC_VER_19)
1675                 return true;
1676
1677         return rtl8169_do_counters(tp, CounterReset);
1678 }
1679
1680 static bool rtl8169_update_counters(struct rtl8169_private *tp)
1681 {
1682         /*
1683          * Some chips are unable to dump tally counters when the receiver
1684          * is disabled.
1685          */
1686         if ((RTL_R8(tp, ChipCmd) & CmdRxEnb) == 0)
1687                 return true;
1688
1689         return rtl8169_do_counters(tp, CounterDump);
1690 }
1691
1692 static bool rtl8169_init_counter_offsets(struct rtl8169_private *tp)
1693 {
1694         struct rtl8169_counters *counters = tp->counters;
1695         bool ret = false;
1696
1697         /*
1698          * rtl8169_init_counter_offsets is called from rtl_open.  On chip
1699          * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1700          * reset by a power cycle, while the counter values collected by the
1701          * driver are reset at every driver unload/load cycle.
1702          *
1703          * To make sure the HW values returned by @get_stats64 match the SW
1704          * values, we collect the initial values at first open(*) and use them
1705          * as offsets to normalize the values returned by @get_stats64.
1706          *
1707          * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1708          * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1709          * set at open time by rtl_hw_start.
1710          */
1711
1712         if (tp->tc_offset.inited)
1713                 return true;
1714
1715         /* If both, reset and update fail, propagate to caller. */
1716         if (rtl8169_reset_counters(tp))
1717                 ret = true;
1718
1719         if (rtl8169_update_counters(tp))
1720                 ret = true;
1721
1722         tp->tc_offset.tx_errors = counters->tx_errors;
1723         tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1724         tp->tc_offset.tx_aborted = counters->tx_aborted;
1725         tp->tc_offset.inited = true;
1726
1727         return ret;
1728 }
1729
1730 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1731                                       struct ethtool_stats *stats, u64 *data)
1732 {
1733         struct rtl8169_private *tp = netdev_priv(dev);
1734         struct device *d = tp_to_dev(tp);
1735         struct rtl8169_counters *counters = tp->counters;
1736
1737         ASSERT_RTNL();
1738
1739         pm_runtime_get_noresume(d);
1740
1741         if (pm_runtime_active(d))
1742                 rtl8169_update_counters(tp);
1743
1744         pm_runtime_put_noidle(d);
1745
1746         data[0] = le64_to_cpu(counters->tx_packets);
1747         data[1] = le64_to_cpu(counters->rx_packets);
1748         data[2] = le64_to_cpu(counters->tx_errors);
1749         data[3] = le32_to_cpu(counters->rx_errors);
1750         data[4] = le16_to_cpu(counters->rx_missed);
1751         data[5] = le16_to_cpu(counters->align_errors);
1752         data[6] = le32_to_cpu(counters->tx_one_collision);
1753         data[7] = le32_to_cpu(counters->tx_multi_collision);
1754         data[8] = le64_to_cpu(counters->rx_unicast);
1755         data[9] = le64_to_cpu(counters->rx_broadcast);
1756         data[10] = le32_to_cpu(counters->rx_multicast);
1757         data[11] = le16_to_cpu(counters->tx_aborted);
1758         data[12] = le16_to_cpu(counters->tx_underun);
1759 }
1760
1761 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1762 {
1763         switch(stringset) {
1764         case ETH_SS_STATS:
1765                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1766                 break;
1767         }
1768 }
1769
1770 /*
1771  * Interrupt coalescing
1772  *
1773  * > 1 - the availability of the IntrMitigate (0xe2) register through the
1774  * >     8169, 8168 and 810x line of chipsets
1775  *
1776  * 8169, 8168, and 8136(810x) serial chipsets support it.
1777  *
1778  * > 2 - the Tx timer unit at gigabit speed
1779  *
1780  * The unit of the timer depends on both the speed and the setting of CPlusCmd
1781  * (0xe0) bit 1 and bit 0.
1782  *
1783  * For 8169
1784  * bit[1:0] \ speed        1000M           100M            10M
1785  * 0 0                     320ns           2.56us          40.96us
1786  * 0 1                     2.56us          20.48us         327.7us
1787  * 1 0                     5.12us          40.96us         655.4us
1788  * 1 1                     10.24us         81.92us         1.31ms
1789  *
1790  * For the other
1791  * bit[1:0] \ speed        1000M           100M            10M
1792  * 0 0                     5us             2.56us          40.96us
1793  * 0 1                     40us            20.48us         327.7us
1794  * 1 0                     80us            40.96us         655.4us
1795  * 1 1                     160us           81.92us         1.31ms
1796  */
1797
1798 /* rx/tx scale factors for one particular CPlusCmd[0:1] value */
1799 struct rtl_coalesce_scale {
1800         /* Rx / Tx */
1801         u32 nsecs[2];
1802 };
1803
1804 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
1805 struct rtl_coalesce_info {
1806         u32 speed;
1807         struct rtl_coalesce_scale scalev[4];    /* each CPlusCmd[0:1] case */
1808 };
1809
1810 /* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */
1811 #define rxtx_x1822(r, t) {              \
1812         {{(r),          (t)}},          \
1813         {{(r)*8,        (t)*8}},        \
1814         {{(r)*8*2,      (t)*8*2}},      \
1815         {{(r)*8*2*2,    (t)*8*2*2}},    \
1816 }
1817 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1818         /* speed        delays:     rx00   tx00 */
1819         { SPEED_10,     rxtx_x1822(40960, 40960)        },
1820         { SPEED_100,    rxtx_x1822( 2560,  2560)        },
1821         { SPEED_1000,   rxtx_x1822(  320,   320)        },
1822         { 0 },
1823 };
1824
1825 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1826         /* speed        delays:     rx00   tx00 */
1827         { SPEED_10,     rxtx_x1822(40960, 40960)        },
1828         { SPEED_100,    rxtx_x1822( 2560,  2560)        },
1829         { SPEED_1000,   rxtx_x1822( 5000,  5000)        },
1830         { 0 },
1831 };
1832 #undef rxtx_x1822
1833
1834 /* get rx/tx scale vector corresponding to current speed */
1835 static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev)
1836 {
1837         struct rtl8169_private *tp = netdev_priv(dev);
1838         struct ethtool_link_ksettings ecmd;
1839         const struct rtl_coalesce_info *ci;
1840         int rc;
1841
1842         rc = phy_ethtool_get_link_ksettings(dev, &ecmd);
1843         if (rc < 0)
1844                 return ERR_PTR(rc);
1845
1846         for (ci = tp->coalesce_info; ci->speed != 0; ci++) {
1847                 if (ecmd.base.speed == ci->speed) {
1848                         return ci;
1849                 }
1850         }
1851
1852         return ERR_PTR(-ELNRNG);
1853 }
1854
1855 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1856 {
1857         struct rtl8169_private *tp = netdev_priv(dev);
1858         const struct rtl_coalesce_info *ci;
1859         const struct rtl_coalesce_scale *scale;
1860         struct {
1861                 u32 *max_frames;
1862                 u32 *usecs;
1863         } coal_settings [] = {
1864                 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs },
1865                 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs }
1866         }, *p = coal_settings;
1867         int i;
1868         u16 w;
1869
1870         memset(ec, 0, sizeof(*ec));
1871
1872         /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1873         ci = rtl_coalesce_info(dev);
1874         if (IS_ERR(ci))
1875                 return PTR_ERR(ci);
1876
1877         scale = &ci->scalev[tp->cp_cmd & INTT_MASK];
1878
1879         /* read IntrMitigate and adjust according to scale */
1880         for (w = RTL_R16(tp, IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) {
1881                 *p->max_frames = (w & RTL_COALESCE_MASK) << 2;
1882                 w >>= RTL_COALESCE_SHIFT;
1883                 *p->usecs = w & RTL_COALESCE_MASK;
1884         }
1885
1886         for (i = 0; i < 2; i++) {
1887                 p = coal_settings + i;
1888                 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000;
1889
1890                 /*
1891                  * ethtool_coalesce says it is illegal to set both usecs and
1892                  * max_frames to 0.
1893                  */
1894                 if (!*p->usecs && !*p->max_frames)
1895                         *p->max_frames = 1;
1896         }
1897
1898         return 0;
1899 }
1900
1901 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */
1902 static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale(
1903                         struct net_device *dev, u32 nsec, u16 *cp01)
1904 {
1905         const struct rtl_coalesce_info *ci;
1906         u16 i;
1907
1908         ci = rtl_coalesce_info(dev);
1909         if (IS_ERR(ci))
1910                 return ERR_CAST(ci);
1911
1912         for (i = 0; i < 4; i++) {
1913                 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0],
1914                                         ci->scalev[i].nsecs[1]);
1915                 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) {
1916                         *cp01 = i;
1917                         return &ci->scalev[i];
1918                 }
1919         }
1920
1921         return ERR_PTR(-EINVAL);
1922 }
1923
1924 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1925 {
1926         struct rtl8169_private *tp = netdev_priv(dev);
1927         const struct rtl_coalesce_scale *scale;
1928         struct {
1929                 u32 frames;
1930                 u32 usecs;
1931         } coal_settings [] = {
1932                 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs },
1933                 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs }
1934         }, *p = coal_settings;
1935         u16 w = 0, cp01;
1936         int i;
1937
1938         scale = rtl_coalesce_choose_scale(dev,
1939                         max(p[0].usecs, p[1].usecs) * 1000, &cp01);
1940         if (IS_ERR(scale))
1941                 return PTR_ERR(scale);
1942
1943         for (i = 0; i < 2; i++, p++) {
1944                 u32 units;
1945
1946                 /*
1947                  * accept max_frames=1 we returned in rtl_get_coalesce.
1948                  * accept it not only when usecs=0 because of e.g. the following scenario:
1949                  *
1950                  * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
1951                  * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
1952                  * - then user does `ethtool -C eth0 rx-usecs 100`
1953                  *
1954                  * since ethtool sends to kernel whole ethtool_coalesce
1955                  * settings, if we do not handle rx_usecs=!0, rx_frames=1
1956                  * we'll reject it below in `frames % 4 != 0`.
1957                  */
1958                 if (p->frames == 1) {
1959                         p->frames = 0;
1960                 }
1961
1962                 units = p->usecs * 1000 / scale->nsecs[i];
1963                 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4)
1964                         return -EINVAL;
1965
1966                 w <<= RTL_COALESCE_SHIFT;
1967                 w |= units;
1968                 w <<= RTL_COALESCE_SHIFT;
1969                 w |= p->frames >> 2;
1970         }
1971
1972         rtl_lock_work(tp);
1973
1974         RTL_W16(tp, IntrMitigate, swab16(w));
1975
1976         tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
1977         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1978         RTL_R16(tp, CPlusCmd);
1979
1980         rtl_unlock_work(tp);
1981
1982         return 0;
1983 }
1984
1985 static const struct ethtool_ops rtl8169_ethtool_ops = {
1986         .get_drvinfo            = rtl8169_get_drvinfo,
1987         .get_regs_len           = rtl8169_get_regs_len,
1988         .get_link               = ethtool_op_get_link,
1989         .get_coalesce           = rtl_get_coalesce,
1990         .set_coalesce           = rtl_set_coalesce,
1991         .get_msglevel           = rtl8169_get_msglevel,
1992         .set_msglevel           = rtl8169_set_msglevel,
1993         .get_regs               = rtl8169_get_regs,
1994         .get_wol                = rtl8169_get_wol,
1995         .set_wol                = rtl8169_set_wol,
1996         .get_strings            = rtl8169_get_strings,
1997         .get_sset_count         = rtl8169_get_sset_count,
1998         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
1999         .get_ts_info            = ethtool_op_get_ts_info,
2000         .nway_reset             = phy_ethtool_nway_reset,
2001         .get_link_ksettings     = phy_ethtool_get_link_ksettings,
2002         .set_link_ksettings     = phy_ethtool_set_link_ksettings,
2003 };
2004
2005 static void rtl8169_get_mac_version(struct rtl8169_private *tp)
2006 {
2007         /*
2008          * The driver currently handles the 8168Bf and the 8168Be identically
2009          * but they can be identified more specifically through the test below
2010          * if needed:
2011          *
2012          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2013          *
2014          * Same thing for the 8101Eb and the 8101Ec:
2015          *
2016          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2017          */
2018         static const struct rtl_mac_info {
2019                 u16 mask;
2020                 u16 val;
2021                 u16 mac_version;
2022         } mac_info[] = {
2023                 /* 8168EP family. */
2024                 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 },
2025                 { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 },
2026                 { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 },
2027
2028                 /* 8168H family. */
2029                 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 },
2030                 { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 },
2031
2032                 /* 8168G family. */
2033                 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 },
2034                 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 },
2035                 { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 },
2036                 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 },
2037
2038                 /* 8168F family. */
2039                 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 },
2040                 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 },
2041                 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 },
2042
2043                 /* 8168E family. */
2044                 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 },
2045                 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 },
2046                 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 },
2047
2048                 /* 8168D family. */
2049                 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 },
2050                 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 },
2051
2052                 /* 8168DP family. */
2053                 { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 },
2054                 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 },
2055                 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 },
2056
2057                 /* 8168C family. */
2058                 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 },
2059                 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 },
2060                 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 },
2061                 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 },
2062                 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 },
2063                 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 },
2064                 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 },
2065
2066                 /* 8168B family. */
2067                 { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12 },
2068                 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 },
2069                 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 },
2070
2071                 /* 8101 family. */
2072                 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 },
2073                 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 },
2074                 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 },
2075                 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 },
2076                 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 },
2077                 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 },
2078                 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 },
2079                 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 },
2080                 { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13 },
2081                 { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10 },
2082                 { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16 },
2083                 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 },
2084                 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 },
2085                 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16 },
2086                 /* FIXME: where did these entries come from ? -- FR */
2087                 { 0xfc8, 0x388, RTL_GIGA_MAC_VER_15 },
2088                 { 0xfc8, 0x308, RTL_GIGA_MAC_VER_14 },
2089
2090                 /* 8110 family. */
2091                 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 },
2092                 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 },
2093                 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 },
2094                 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 },
2095                 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 },
2096                 { 0xfc8, 0x000, RTL_GIGA_MAC_VER_01 },
2097
2098                 /* Catch-all */
2099                 { 0x000, 0x000, RTL_GIGA_MAC_NONE   }
2100         };
2101         const struct rtl_mac_info *p = mac_info;
2102         u16 reg = RTL_R32(tp, TxConfig) >> 20;
2103
2104         while ((reg & p->mask) != p->val)
2105                 p++;
2106         tp->mac_version = p->mac_version;
2107
2108         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2109                 dev_err(tp_to_dev(tp), "unknown chip XID %03x\n", reg & 0xfcf);
2110         } else if (!tp->supports_gmii) {
2111                 if (tp->mac_version == RTL_GIGA_MAC_VER_42)
2112                         tp->mac_version = RTL_GIGA_MAC_VER_43;
2113                 else if (tp->mac_version == RTL_GIGA_MAC_VER_45)
2114                         tp->mac_version = RTL_GIGA_MAC_VER_47;
2115                 else if (tp->mac_version == RTL_GIGA_MAC_VER_46)
2116                         tp->mac_version = RTL_GIGA_MAC_VER_48;
2117         }
2118 }
2119
2120 struct phy_reg {
2121         u16 reg;
2122         u16 val;
2123 };
2124
2125 static void rtl_writephy_batch(struct rtl8169_private *tp,
2126                                const struct phy_reg *regs, int len)
2127 {
2128         while (len-- > 0) {
2129                 rtl_writephy(tp, regs->reg, regs->val);
2130                 regs++;
2131         }
2132 }
2133
2134 #define PHY_READ                0x00000000
2135 #define PHY_DATA_OR             0x10000000
2136 #define PHY_DATA_AND            0x20000000
2137 #define PHY_BJMPN               0x30000000
2138 #define PHY_MDIO_CHG            0x40000000
2139 #define PHY_CLEAR_READCOUNT     0x70000000
2140 #define PHY_WRITE               0x80000000
2141 #define PHY_READCOUNT_EQ_SKIP   0x90000000
2142 #define PHY_COMP_EQ_SKIPN       0xa0000000
2143 #define PHY_COMP_NEQ_SKIPN      0xb0000000
2144 #define PHY_WRITE_PREVIOUS      0xc0000000
2145 #define PHY_SKIPN               0xd0000000
2146 #define PHY_DELAY_MS            0xe0000000
2147
2148 struct fw_info {
2149         u32     magic;
2150         char    version[RTL_VER_SIZE];
2151         __le32  fw_start;
2152         __le32  fw_len;
2153         u8      chksum;
2154 } __packed;
2155
2156 #define FW_OPCODE_SIZE  sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2157
2158 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2159 {
2160         const struct firmware *fw = rtl_fw->fw;
2161         struct fw_info *fw_info = (struct fw_info *)fw->data;
2162         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2163         char *version = rtl_fw->version;
2164         bool rc = false;
2165
2166         if (fw->size < FW_OPCODE_SIZE)
2167                 goto out;
2168
2169         if (!fw_info->magic) {
2170                 size_t i, size, start;
2171                 u8 checksum = 0;
2172
2173                 if (fw->size < sizeof(*fw_info))
2174                         goto out;
2175
2176                 for (i = 0; i < fw->size; i++)
2177                         checksum += fw->data[i];
2178                 if (checksum != 0)
2179                         goto out;
2180
2181                 start = le32_to_cpu(fw_info->fw_start);
2182                 if (start > fw->size)
2183                         goto out;
2184
2185                 size = le32_to_cpu(fw_info->fw_len);
2186                 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2187                         goto out;
2188
2189                 memcpy(version, fw_info->version, RTL_VER_SIZE);
2190
2191                 pa->code = (__le32 *)(fw->data + start);
2192                 pa->size = size;
2193         } else {
2194                 if (fw->size % FW_OPCODE_SIZE)
2195                         goto out;
2196
2197                 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2198
2199                 pa->code = (__le32 *)fw->data;
2200                 pa->size = fw->size / FW_OPCODE_SIZE;
2201         }
2202         version[RTL_VER_SIZE - 1] = 0;
2203
2204         rc = true;
2205 out:
2206         return rc;
2207 }
2208
2209 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2210                            struct rtl_fw_phy_action *pa)
2211 {
2212         bool rc = false;
2213         size_t index;
2214
2215         for (index = 0; index < pa->size; index++) {
2216                 u32 action = le32_to_cpu(pa->code[index]);
2217                 u32 regno = (action & 0x0fff0000) >> 16;
2218
2219                 switch(action & 0xf0000000) {
2220                 case PHY_READ:
2221                 case PHY_DATA_OR:
2222                 case PHY_DATA_AND:
2223                 case PHY_MDIO_CHG:
2224                 case PHY_CLEAR_READCOUNT:
2225                 case PHY_WRITE:
2226                 case PHY_WRITE_PREVIOUS:
2227                 case PHY_DELAY_MS:
2228                         break;
2229
2230                 case PHY_BJMPN:
2231                         if (regno > index) {
2232                                 netif_err(tp, ifup, tp->dev,
2233                                           "Out of range of firmware\n");
2234                                 goto out;
2235                         }
2236                         break;
2237                 case PHY_READCOUNT_EQ_SKIP:
2238                         if (index + 2 >= pa->size) {
2239                                 netif_err(tp, ifup, tp->dev,
2240                                           "Out of range of firmware\n");
2241                                 goto out;
2242                         }
2243                         break;
2244                 case PHY_COMP_EQ_SKIPN:
2245                 case PHY_COMP_NEQ_SKIPN:
2246                 case PHY_SKIPN:
2247                         if (index + 1 + regno >= pa->size) {
2248                                 netif_err(tp, ifup, tp->dev,
2249                                           "Out of range of firmware\n");
2250                                 goto out;
2251                         }
2252                         break;
2253
2254                 default:
2255                         netif_err(tp, ifup, tp->dev,
2256                                   "Invalid action 0x%08x\n", action);
2257                         goto out;
2258                 }
2259         }
2260         rc = true;
2261 out:
2262         return rc;
2263 }
2264
2265 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2266 {
2267         struct net_device *dev = tp->dev;
2268         int rc = -EINVAL;
2269
2270         if (!rtl_fw_format_ok(tp, rtl_fw)) {
2271                 netif_err(tp, ifup, dev, "invalid firmware\n");
2272                 goto out;
2273         }
2274
2275         if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2276                 rc = 0;
2277 out:
2278         return rc;
2279 }
2280
2281 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2282 {
2283         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2284         struct mdio_ops org, *ops = &tp->mdio_ops;
2285         u32 predata, count;
2286         size_t index;
2287
2288         predata = count = 0;
2289         org.write = ops->write;
2290         org.read = ops->read;
2291
2292         for (index = 0; index < pa->size; ) {
2293                 u32 action = le32_to_cpu(pa->code[index]);
2294                 u32 data = action & 0x0000ffff;
2295                 u32 regno = (action & 0x0fff0000) >> 16;
2296
2297                 if (!action)
2298                         break;
2299
2300                 switch(action & 0xf0000000) {
2301                 case PHY_READ:
2302                         predata = rtl_readphy(tp, regno);
2303                         count++;
2304                         index++;
2305                         break;
2306                 case PHY_DATA_OR:
2307                         predata |= data;
2308                         index++;
2309                         break;
2310                 case PHY_DATA_AND:
2311                         predata &= data;
2312                         index++;
2313                         break;
2314                 case PHY_BJMPN:
2315                         index -= regno;
2316                         break;
2317                 case PHY_MDIO_CHG:
2318                         if (data == 0) {
2319                                 ops->write = org.write;
2320                                 ops->read = org.read;
2321                         } else if (data == 1) {
2322                                 ops->write = mac_mcu_write;
2323                                 ops->read = mac_mcu_read;
2324                         }
2325
2326                         index++;
2327                         break;
2328                 case PHY_CLEAR_READCOUNT:
2329                         count = 0;
2330                         index++;
2331                         break;
2332                 case PHY_WRITE:
2333                         rtl_writephy(tp, regno, data);
2334                         index++;
2335                         break;
2336                 case PHY_READCOUNT_EQ_SKIP:
2337                         index += (count == data) ? 2 : 1;
2338                         break;
2339                 case PHY_COMP_EQ_SKIPN:
2340                         if (predata == data)
2341                                 index += regno;
2342                         index++;
2343                         break;
2344                 case PHY_COMP_NEQ_SKIPN:
2345                         if (predata != data)
2346                                 index += regno;
2347                         index++;
2348                         break;
2349                 case PHY_WRITE_PREVIOUS:
2350                         rtl_writephy(tp, regno, predata);
2351                         index++;
2352                         break;
2353                 case PHY_SKIPN:
2354                         index += regno + 1;
2355                         break;
2356                 case PHY_DELAY_MS:
2357                         mdelay(data);
2358                         index++;
2359                         break;
2360
2361                 default:
2362                         BUG();
2363                 }
2364         }
2365
2366         ops->write = org.write;
2367         ops->read = org.read;
2368 }
2369
2370 static void rtl_release_firmware(struct rtl8169_private *tp)
2371 {
2372         if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2373                 release_firmware(tp->rtl_fw->fw);
2374                 kfree(tp->rtl_fw);
2375         }
2376         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2377 }
2378
2379 static void rtl_apply_firmware(struct rtl8169_private *tp)
2380 {
2381         struct rtl_fw *rtl_fw = tp->rtl_fw;
2382
2383         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2384         if (!IS_ERR_OR_NULL(rtl_fw))
2385                 rtl_phy_write_fw(tp, rtl_fw);
2386 }
2387
2388 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2389 {
2390         if (rtl_readphy(tp, reg) != val)
2391                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2392         else
2393                 rtl_apply_firmware(tp);
2394 }
2395
2396 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2397 {
2398         static const struct phy_reg phy_reg_init[] = {
2399                 { 0x1f, 0x0001 },
2400                 { 0x06, 0x006e },
2401                 { 0x08, 0x0708 },
2402                 { 0x15, 0x4000 },
2403                 { 0x18, 0x65c7 },
2404
2405                 { 0x1f, 0x0001 },
2406                 { 0x03, 0x00a1 },
2407                 { 0x02, 0x0008 },
2408                 { 0x01, 0x0120 },
2409                 { 0x00, 0x1000 },
2410                 { 0x04, 0x0800 },
2411                 { 0x04, 0x0000 },
2412
2413                 { 0x03, 0xff41 },
2414                 { 0x02, 0xdf60 },
2415                 { 0x01, 0x0140 },
2416                 { 0x00, 0x0077 },
2417                 { 0x04, 0x7800 },
2418                 { 0x04, 0x7000 },
2419
2420                 { 0x03, 0x802f },
2421                 { 0x02, 0x4f02 },
2422                 { 0x01, 0x0409 },
2423                 { 0x00, 0xf0f9 },
2424                 { 0x04, 0x9800 },
2425                 { 0x04, 0x9000 },
2426
2427                 { 0x03, 0xdf01 },
2428                 { 0x02, 0xdf20 },
2429                 { 0x01, 0xff95 },
2430                 { 0x00, 0xba00 },
2431                 { 0x04, 0xa800 },
2432                 { 0x04, 0xa000 },
2433
2434                 { 0x03, 0xff41 },
2435                 { 0x02, 0xdf20 },
2436                 { 0x01, 0x0140 },
2437                 { 0x00, 0x00bb },
2438                 { 0x04, 0xb800 },
2439                 { 0x04, 0xb000 },
2440
2441                 { 0x03, 0xdf41 },
2442                 { 0x02, 0xdc60 },
2443                 { 0x01, 0x6340 },
2444                 { 0x00, 0x007d },
2445                 { 0x04, 0xd800 },
2446                 { 0x04, 0xd000 },
2447
2448                 { 0x03, 0xdf01 },
2449                 { 0x02, 0xdf20 },
2450                 { 0x01, 0x100a },
2451                 { 0x00, 0xa0ff },
2452                 { 0x04, 0xf800 },
2453                 { 0x04, 0xf000 },
2454
2455                 { 0x1f, 0x0000 },
2456                 { 0x0b, 0x0000 },
2457                 { 0x00, 0x9200 }
2458         };
2459
2460         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2461 }
2462
2463 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2464 {
2465         static const struct phy_reg phy_reg_init[] = {
2466                 { 0x1f, 0x0002 },
2467                 { 0x01, 0x90d0 },
2468                 { 0x1f, 0x0000 }
2469         };
2470
2471         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2472 }
2473
2474 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2475 {
2476         struct pci_dev *pdev = tp->pci_dev;
2477
2478         if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2479             (pdev->subsystem_device != 0xe000))
2480                 return;
2481
2482         rtl_writephy(tp, 0x1f, 0x0001);
2483         rtl_writephy(tp, 0x10, 0xf01b);
2484         rtl_writephy(tp, 0x1f, 0x0000);
2485 }
2486
2487 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2488 {
2489         static const struct phy_reg phy_reg_init[] = {
2490                 { 0x1f, 0x0001 },
2491                 { 0x04, 0x0000 },
2492                 { 0x03, 0x00a1 },
2493                 { 0x02, 0x0008 },
2494                 { 0x01, 0x0120 },
2495                 { 0x00, 0x1000 },
2496                 { 0x04, 0x0800 },
2497                 { 0x04, 0x9000 },
2498                 { 0x03, 0x802f },
2499                 { 0x02, 0x4f02 },
2500                 { 0x01, 0x0409 },
2501                 { 0x00, 0xf099 },
2502                 { 0x04, 0x9800 },
2503                 { 0x04, 0xa000 },
2504                 { 0x03, 0xdf01 },
2505                 { 0x02, 0xdf20 },
2506                 { 0x01, 0xff95 },
2507                 { 0x00, 0xba00 },
2508                 { 0x04, 0xa800 },
2509                 { 0x04, 0xf000 },
2510                 { 0x03, 0xdf01 },
2511                 { 0x02, 0xdf20 },
2512                 { 0x01, 0x101a },
2513                 { 0x00, 0xa0ff },
2514                 { 0x04, 0xf800 },
2515                 { 0x04, 0x0000 },
2516                 { 0x1f, 0x0000 },
2517
2518                 { 0x1f, 0x0001 },
2519                 { 0x10, 0xf41b },
2520                 { 0x14, 0xfb54 },
2521                 { 0x18, 0xf5c7 },
2522                 { 0x1f, 0x0000 },
2523
2524                 { 0x1f, 0x0001 },
2525                 { 0x17, 0x0cc0 },
2526                 { 0x1f, 0x0000 }
2527         };
2528
2529         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2530
2531         rtl8169scd_hw_phy_config_quirk(tp);
2532 }
2533
2534 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2535 {
2536         static const struct phy_reg phy_reg_init[] = {
2537                 { 0x1f, 0x0001 },
2538                 { 0x04, 0x0000 },
2539                 { 0x03, 0x00a1 },
2540                 { 0x02, 0x0008 },
2541                 { 0x01, 0x0120 },
2542                 { 0x00, 0x1000 },
2543                 { 0x04, 0x0800 },
2544                 { 0x04, 0x9000 },
2545                 { 0x03, 0x802f },
2546                 { 0x02, 0x4f02 },
2547                 { 0x01, 0x0409 },
2548                 { 0x00, 0xf099 },
2549                 { 0x04, 0x9800 },
2550                 { 0x04, 0xa000 },
2551                 { 0x03, 0xdf01 },
2552                 { 0x02, 0xdf20 },
2553                 { 0x01, 0xff95 },
2554                 { 0x00, 0xba00 },
2555                 { 0x04, 0xa800 },
2556                 { 0x04, 0xf000 },
2557                 { 0x03, 0xdf01 },
2558                 { 0x02, 0xdf20 },
2559                 { 0x01, 0x101a },
2560                 { 0x00, 0xa0ff },
2561                 { 0x04, 0xf800 },
2562                 { 0x04, 0x0000 },
2563                 { 0x1f, 0x0000 },
2564
2565                 { 0x1f, 0x0001 },
2566                 { 0x0b, 0x8480 },
2567                 { 0x1f, 0x0000 },
2568
2569                 { 0x1f, 0x0001 },
2570                 { 0x18, 0x67c7 },
2571                 { 0x04, 0x2000 },
2572                 { 0x03, 0x002f },
2573                 { 0x02, 0x4360 },
2574                 { 0x01, 0x0109 },
2575                 { 0x00, 0x3022 },
2576                 { 0x04, 0x2800 },
2577                 { 0x1f, 0x0000 },
2578
2579                 { 0x1f, 0x0001 },
2580                 { 0x17, 0x0cc0 },
2581                 { 0x1f, 0x0000 }
2582         };
2583
2584         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2585 }
2586
2587 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2588 {
2589         static const struct phy_reg phy_reg_init[] = {
2590                 { 0x10, 0xf41b },
2591                 { 0x1f, 0x0000 }
2592         };
2593
2594         rtl_writephy(tp, 0x1f, 0x0001);
2595         rtl_patchphy(tp, 0x16, 1 << 0);
2596
2597         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2598 }
2599
2600 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2601 {
2602         static const struct phy_reg phy_reg_init[] = {
2603                 { 0x1f, 0x0001 },
2604                 { 0x10, 0xf41b },
2605                 { 0x1f, 0x0000 }
2606         };
2607
2608         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2609 }
2610
2611 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2612 {
2613         static const struct phy_reg phy_reg_init[] = {
2614                 { 0x1f, 0x0000 },
2615                 { 0x1d, 0x0f00 },
2616                 { 0x1f, 0x0002 },
2617                 { 0x0c, 0x1ec8 },
2618                 { 0x1f, 0x0000 }
2619         };
2620
2621         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2622 }
2623
2624 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2625 {
2626         static const struct phy_reg phy_reg_init[] = {
2627                 { 0x1f, 0x0001 },
2628                 { 0x1d, 0x3d98 },
2629                 { 0x1f, 0x0000 }
2630         };
2631
2632         rtl_writephy(tp, 0x1f, 0x0000);
2633         rtl_patchphy(tp, 0x14, 1 << 5);
2634         rtl_patchphy(tp, 0x0d, 1 << 5);
2635
2636         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2637 }
2638
2639 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2640 {
2641         static const struct phy_reg phy_reg_init[] = {
2642                 { 0x1f, 0x0001 },
2643                 { 0x12, 0x2300 },
2644                 { 0x1f, 0x0002 },
2645                 { 0x00, 0x88d4 },
2646                 { 0x01, 0x82b1 },
2647                 { 0x03, 0x7002 },
2648                 { 0x08, 0x9e30 },
2649                 { 0x09, 0x01f0 },
2650                 { 0x0a, 0x5500 },
2651                 { 0x0c, 0x00c8 },
2652                 { 0x1f, 0x0003 },
2653                 { 0x12, 0xc096 },
2654                 { 0x16, 0x000a },
2655                 { 0x1f, 0x0000 },
2656                 { 0x1f, 0x0000 },
2657                 { 0x09, 0x2000 },
2658                 { 0x09, 0x0000 }
2659         };
2660
2661         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2662
2663         rtl_patchphy(tp, 0x14, 1 << 5);
2664         rtl_patchphy(tp, 0x0d, 1 << 5);
2665         rtl_writephy(tp, 0x1f, 0x0000);
2666 }
2667
2668 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2669 {
2670         static const struct phy_reg phy_reg_init[] = {
2671                 { 0x1f, 0x0001 },
2672                 { 0x12, 0x2300 },
2673                 { 0x03, 0x802f },
2674                 { 0x02, 0x4f02 },
2675                 { 0x01, 0x0409 },
2676                 { 0x00, 0xf099 },
2677                 { 0x04, 0x9800 },
2678                 { 0x04, 0x9000 },
2679                 { 0x1d, 0x3d98 },
2680                 { 0x1f, 0x0002 },
2681                 { 0x0c, 0x7eb8 },
2682                 { 0x06, 0x0761 },
2683                 { 0x1f, 0x0003 },
2684                 { 0x16, 0x0f0a },
2685                 { 0x1f, 0x0000 }
2686         };
2687
2688         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2689
2690         rtl_patchphy(tp, 0x16, 1 << 0);
2691         rtl_patchphy(tp, 0x14, 1 << 5);
2692         rtl_patchphy(tp, 0x0d, 1 << 5);
2693         rtl_writephy(tp, 0x1f, 0x0000);
2694 }
2695
2696 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2697 {
2698         static const struct phy_reg phy_reg_init[] = {
2699                 { 0x1f, 0x0001 },
2700                 { 0x12, 0x2300 },
2701                 { 0x1d, 0x3d98 },
2702                 { 0x1f, 0x0002 },
2703                 { 0x0c, 0x7eb8 },
2704                 { 0x06, 0x5461 },
2705                 { 0x1f, 0x0003 },
2706                 { 0x16, 0x0f0a },
2707                 { 0x1f, 0x0000 }
2708         };
2709
2710         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2711
2712         rtl_patchphy(tp, 0x16, 1 << 0);
2713         rtl_patchphy(tp, 0x14, 1 << 5);
2714         rtl_patchphy(tp, 0x0d, 1 << 5);
2715         rtl_writephy(tp, 0x1f, 0x0000);
2716 }
2717
2718 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2719 {
2720         rtl8168c_3_hw_phy_config(tp);
2721 }
2722
2723 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2724 {
2725         static const struct phy_reg phy_reg_init_0[] = {
2726                 /* Channel Estimation */
2727                 { 0x1f, 0x0001 },
2728                 { 0x06, 0x4064 },
2729                 { 0x07, 0x2863 },
2730                 { 0x08, 0x059c },
2731                 { 0x09, 0x26b4 },
2732                 { 0x0a, 0x6a19 },
2733                 { 0x0b, 0xdcc8 },
2734                 { 0x10, 0xf06d },
2735                 { 0x14, 0x7f68 },
2736                 { 0x18, 0x7fd9 },
2737                 { 0x1c, 0xf0ff },
2738                 { 0x1d, 0x3d9c },
2739                 { 0x1f, 0x0003 },
2740                 { 0x12, 0xf49f },
2741                 { 0x13, 0x070b },
2742                 { 0x1a, 0x05ad },
2743                 { 0x14, 0x94c0 },
2744
2745                 /*
2746                  * Tx Error Issue
2747                  * Enhance line driver power
2748                  */
2749                 { 0x1f, 0x0002 },
2750                 { 0x06, 0x5561 },
2751                 { 0x1f, 0x0005 },
2752                 { 0x05, 0x8332 },
2753                 { 0x06, 0x5561 },
2754
2755                 /*
2756                  * Can not link to 1Gbps with bad cable
2757                  * Decrease SNR threshold form 21.07dB to 19.04dB
2758                  */
2759                 { 0x1f, 0x0001 },
2760                 { 0x17, 0x0cc0 },
2761
2762                 { 0x1f, 0x0000 },
2763                 { 0x0d, 0xf880 }
2764         };
2765
2766         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2767
2768         /*
2769          * Rx Error Issue
2770          * Fine Tune Switching regulator parameter
2771          */
2772         rtl_writephy(tp, 0x1f, 0x0002);
2773         rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
2774         rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
2775
2776         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2777                 static const struct phy_reg phy_reg_init[] = {
2778                         { 0x1f, 0x0002 },
2779                         { 0x05, 0x669a },
2780                         { 0x1f, 0x0005 },
2781                         { 0x05, 0x8330 },
2782                         { 0x06, 0x669a },
2783                         { 0x1f, 0x0002 }
2784                 };
2785                 int val;
2786
2787                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2788
2789                 val = rtl_readphy(tp, 0x0d);
2790
2791                 if ((val & 0x00ff) != 0x006c) {
2792                         static const u32 set[] = {
2793                                 0x0065, 0x0066, 0x0067, 0x0068,
2794                                 0x0069, 0x006a, 0x006b, 0x006c
2795                         };
2796                         int i;
2797
2798                         rtl_writephy(tp, 0x1f, 0x0002);
2799
2800                         val &= 0xff00;
2801                         for (i = 0; i < ARRAY_SIZE(set); i++)
2802                                 rtl_writephy(tp, 0x0d, val | set[i]);
2803                 }
2804         } else {
2805                 static const struct phy_reg phy_reg_init[] = {
2806                         { 0x1f, 0x0002 },
2807                         { 0x05, 0x6662 },
2808                         { 0x1f, 0x0005 },
2809                         { 0x05, 0x8330 },
2810                         { 0x06, 0x6662 }
2811                 };
2812
2813                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2814         }
2815
2816         /* RSET couple improve */
2817         rtl_writephy(tp, 0x1f, 0x0002);
2818         rtl_patchphy(tp, 0x0d, 0x0300);
2819         rtl_patchphy(tp, 0x0f, 0x0010);
2820
2821         /* Fine tune PLL performance */
2822         rtl_writephy(tp, 0x1f, 0x0002);
2823         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2824         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
2825
2826         rtl_writephy(tp, 0x1f, 0x0005);
2827         rtl_writephy(tp, 0x05, 0x001b);
2828
2829         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2830
2831         rtl_writephy(tp, 0x1f, 0x0000);
2832 }
2833
2834 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2835 {
2836         static const struct phy_reg phy_reg_init_0[] = {
2837                 /* Channel Estimation */
2838                 { 0x1f, 0x0001 },
2839                 { 0x06, 0x4064 },
2840                 { 0x07, 0x2863 },
2841                 { 0x08, 0x059c },
2842                 { 0x09, 0x26b4 },
2843                 { 0x0a, 0x6a19 },
2844                 { 0x0b, 0xdcc8 },
2845                 { 0x10, 0xf06d },
2846                 { 0x14, 0x7f68 },
2847                 { 0x18, 0x7fd9 },
2848                 { 0x1c, 0xf0ff },
2849                 { 0x1d, 0x3d9c },
2850                 { 0x1f, 0x0003 },
2851                 { 0x12, 0xf49f },
2852                 { 0x13, 0x070b },
2853                 { 0x1a, 0x05ad },
2854                 { 0x14, 0x94c0 },
2855
2856                 /*
2857                  * Tx Error Issue
2858                  * Enhance line driver power
2859                  */
2860                 { 0x1f, 0x0002 },
2861                 { 0x06, 0x5561 },
2862                 { 0x1f, 0x0005 },
2863                 { 0x05, 0x8332 },
2864                 { 0x06, 0x5561 },
2865
2866                 /*
2867                  * Can not link to 1Gbps with bad cable
2868                  * Decrease SNR threshold form 21.07dB to 19.04dB
2869                  */
2870                 { 0x1f, 0x0001 },
2871                 { 0x17, 0x0cc0 },
2872
2873                 { 0x1f, 0x0000 },
2874                 { 0x0d, 0xf880 }
2875         };
2876
2877         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2878
2879         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2880                 static const struct phy_reg phy_reg_init[] = {
2881                         { 0x1f, 0x0002 },
2882                         { 0x05, 0x669a },
2883                         { 0x1f, 0x0005 },
2884                         { 0x05, 0x8330 },
2885                         { 0x06, 0x669a },
2886
2887                         { 0x1f, 0x0002 }
2888                 };
2889                 int val;
2890
2891                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2892
2893                 val = rtl_readphy(tp, 0x0d);
2894                 if ((val & 0x00ff) != 0x006c) {
2895                         static const u32 set[] = {
2896                                 0x0065, 0x0066, 0x0067, 0x0068,
2897                                 0x0069, 0x006a, 0x006b, 0x006c
2898                         };
2899                         int i;
2900
2901                         rtl_writephy(tp, 0x1f, 0x0002);
2902
2903                         val &= 0xff00;
2904                         for (i = 0; i < ARRAY_SIZE(set); i++)
2905                                 rtl_writephy(tp, 0x0d, val | set[i]);
2906                 }
2907         } else {
2908                 static const struct phy_reg phy_reg_init[] = {
2909                         { 0x1f, 0x0002 },
2910                         { 0x05, 0x2642 },
2911                         { 0x1f, 0x0005 },
2912                         { 0x05, 0x8330 },
2913                         { 0x06, 0x2642 }
2914                 };
2915
2916                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2917         }
2918
2919         /* Fine tune PLL performance */
2920         rtl_writephy(tp, 0x1f, 0x0002);
2921         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2922         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
2923
2924         /* Switching regulator Slew rate */
2925         rtl_writephy(tp, 0x1f, 0x0002);
2926         rtl_patchphy(tp, 0x0f, 0x0017);
2927
2928         rtl_writephy(tp, 0x1f, 0x0005);
2929         rtl_writephy(tp, 0x05, 0x001b);
2930
2931         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2932
2933         rtl_writephy(tp, 0x1f, 0x0000);
2934 }
2935
2936 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2937 {
2938         static const struct phy_reg phy_reg_init[] = {
2939                 { 0x1f, 0x0002 },
2940                 { 0x10, 0x0008 },
2941                 { 0x0d, 0x006c },
2942
2943                 { 0x1f, 0x0000 },
2944                 { 0x0d, 0xf880 },
2945
2946                 { 0x1f, 0x0001 },
2947                 { 0x17, 0x0cc0 },
2948
2949                 { 0x1f, 0x0001 },
2950                 { 0x0b, 0xa4d8 },
2951                 { 0x09, 0x281c },
2952                 { 0x07, 0x2883 },
2953                 { 0x0a, 0x6b35 },
2954                 { 0x1d, 0x3da4 },
2955                 { 0x1c, 0xeffd },
2956                 { 0x14, 0x7f52 },
2957                 { 0x18, 0x7fc6 },
2958                 { 0x08, 0x0601 },
2959                 { 0x06, 0x4063 },
2960                 { 0x10, 0xf074 },
2961                 { 0x1f, 0x0003 },
2962                 { 0x13, 0x0789 },
2963                 { 0x12, 0xf4bd },
2964                 { 0x1a, 0x04fd },
2965                 { 0x14, 0x84b0 },
2966                 { 0x1f, 0x0000 },
2967                 { 0x00, 0x9200 },
2968
2969                 { 0x1f, 0x0005 },
2970                 { 0x01, 0x0340 },
2971                 { 0x1f, 0x0001 },
2972                 { 0x04, 0x4000 },
2973                 { 0x03, 0x1d21 },
2974                 { 0x02, 0x0c32 },
2975                 { 0x01, 0x0200 },
2976                 { 0x00, 0x5554 },
2977                 { 0x04, 0x4800 },
2978                 { 0x04, 0x4000 },
2979                 { 0x04, 0xf000 },
2980                 { 0x03, 0xdf01 },
2981                 { 0x02, 0xdf20 },
2982                 { 0x01, 0x101a },
2983                 { 0x00, 0xa0ff },
2984                 { 0x04, 0xf800 },
2985                 { 0x04, 0xf000 },
2986                 { 0x1f, 0x0000 },
2987
2988                 { 0x1f, 0x0007 },
2989                 { 0x1e, 0x0023 },
2990                 { 0x16, 0x0000 },
2991                 { 0x1f, 0x0000 }
2992         };
2993
2994         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2995 }
2996
2997 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2998 {
2999         static const struct phy_reg phy_reg_init[] = {
3000                 { 0x1f, 0x0001 },
3001                 { 0x17, 0x0cc0 },
3002
3003                 { 0x1f, 0x0007 },
3004                 { 0x1e, 0x002d },
3005                 { 0x18, 0x0040 },
3006                 { 0x1f, 0x0000 }
3007         };
3008
3009         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3010         rtl_patchphy(tp, 0x0d, 1 << 5);
3011 }
3012
3013 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
3014 {
3015         static const struct phy_reg phy_reg_init[] = {
3016                 /* Enable Delay cap */
3017                 { 0x1f, 0x0005 },
3018                 { 0x05, 0x8b80 },
3019                 { 0x06, 0xc896 },
3020                 { 0x1f, 0x0000 },
3021
3022                 /* Channel estimation fine tune */
3023                 { 0x1f, 0x0001 },
3024                 { 0x0b, 0x6c20 },
3025                 { 0x07, 0x2872 },
3026                 { 0x1c, 0xefff },
3027                 { 0x1f, 0x0003 },
3028                 { 0x14, 0x6420 },
3029                 { 0x1f, 0x0000 },
3030
3031                 /* Update PFM & 10M TX idle timer */
3032                 { 0x1f, 0x0007 },
3033                 { 0x1e, 0x002f },
3034                 { 0x15, 0x1919 },
3035                 { 0x1f, 0x0000 },
3036
3037                 { 0x1f, 0x0007 },
3038                 { 0x1e, 0x00ac },
3039                 { 0x18, 0x0006 },
3040                 { 0x1f, 0x0000 }
3041         };
3042
3043         rtl_apply_firmware(tp);
3044
3045         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3046
3047         /* DCO enable for 10M IDLE Power */
3048         rtl_writephy(tp, 0x1f, 0x0007);
3049         rtl_writephy(tp, 0x1e, 0x0023);
3050         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3051         rtl_writephy(tp, 0x1f, 0x0000);
3052
3053         /* For impedance matching */
3054         rtl_writephy(tp, 0x1f, 0x0002);
3055         rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
3056         rtl_writephy(tp, 0x1f, 0x0000);
3057
3058         /* PHY auto speed down */
3059         rtl_writephy(tp, 0x1f, 0x0007);
3060         rtl_writephy(tp, 0x1e, 0x002d);
3061         rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
3062         rtl_writephy(tp, 0x1f, 0x0000);
3063         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3064
3065         rtl_writephy(tp, 0x1f, 0x0005);
3066         rtl_writephy(tp, 0x05, 0x8b86);
3067         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3068         rtl_writephy(tp, 0x1f, 0x0000);
3069
3070         rtl_writephy(tp, 0x1f, 0x0005);
3071         rtl_writephy(tp, 0x05, 0x8b85);
3072         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3073         rtl_writephy(tp, 0x1f, 0x0007);
3074         rtl_writephy(tp, 0x1e, 0x0020);
3075         rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
3076         rtl_writephy(tp, 0x1f, 0x0006);
3077         rtl_writephy(tp, 0x00, 0x5a00);
3078         rtl_writephy(tp, 0x1f, 0x0000);
3079         rtl_writephy(tp, 0x0d, 0x0007);
3080         rtl_writephy(tp, 0x0e, 0x003c);
3081         rtl_writephy(tp, 0x0d, 0x4007);
3082         rtl_writephy(tp, 0x0e, 0x0000);
3083         rtl_writephy(tp, 0x0d, 0x0000);
3084 }
3085
3086 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3087 {
3088         const u16 w[] = {
3089                 addr[0] | (addr[1] << 8),
3090                 addr[2] | (addr[3] << 8),
3091                 addr[4] | (addr[5] << 8)
3092         };
3093         const struct exgmac_reg e[] = {
3094                 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3095                 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3096                 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3097                 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3098         };
3099
3100         rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3101 }
3102
3103 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3104 {
3105         static const struct phy_reg phy_reg_init[] = {
3106                 /* Enable Delay cap */
3107                 { 0x1f, 0x0004 },
3108                 { 0x1f, 0x0007 },
3109                 { 0x1e, 0x00ac },
3110                 { 0x18, 0x0006 },
3111                 { 0x1f, 0x0002 },
3112                 { 0x1f, 0x0000 },
3113                 { 0x1f, 0x0000 },
3114
3115                 /* Channel estimation fine tune */
3116                 { 0x1f, 0x0003 },
3117                 { 0x09, 0xa20f },
3118                 { 0x1f, 0x0000 },
3119                 { 0x1f, 0x0000 },
3120
3121                 /* Green Setting */
3122                 { 0x1f, 0x0005 },
3123                 { 0x05, 0x8b5b },
3124                 { 0x06, 0x9222 },
3125                 { 0x05, 0x8b6d },
3126                 { 0x06, 0x8000 },
3127                 { 0x05, 0x8b76 },
3128                 { 0x06, 0x8000 },
3129                 { 0x1f, 0x0000 }
3130         };
3131
3132         rtl_apply_firmware(tp);
3133
3134         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3135
3136         /* For 4-corner performance improve */
3137         rtl_writephy(tp, 0x1f, 0x0005);
3138         rtl_writephy(tp, 0x05, 0x8b80);
3139         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3140         rtl_writephy(tp, 0x1f, 0x0000);
3141
3142         /* PHY auto speed down */
3143         rtl_writephy(tp, 0x1f, 0x0004);
3144         rtl_writephy(tp, 0x1f, 0x0007);
3145         rtl_writephy(tp, 0x1e, 0x002d);
3146         rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3147         rtl_writephy(tp, 0x1f, 0x0002);
3148         rtl_writephy(tp, 0x1f, 0x0000);
3149         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3150
3151         /* improve 10M EEE waveform */
3152         rtl_writephy(tp, 0x1f, 0x0005);
3153         rtl_writephy(tp, 0x05, 0x8b86);
3154         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3155         rtl_writephy(tp, 0x1f, 0x0000);
3156
3157         /* Improve 2-pair detection performance */
3158         rtl_writephy(tp, 0x1f, 0x0005);
3159         rtl_writephy(tp, 0x05, 0x8b85);
3160         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3161         rtl_writephy(tp, 0x1f, 0x0000);
3162
3163         /* EEE setting */
3164         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0003, 0x0000, ERIAR_EXGMAC);
3165         rtl_writephy(tp, 0x1f, 0x0005);
3166         rtl_writephy(tp, 0x05, 0x8b85);
3167         rtl_w0w1_phy(tp, 0x06, 0x2000, 0x0000);
3168         rtl_writephy(tp, 0x1f, 0x0004);
3169         rtl_writephy(tp, 0x1f, 0x0007);
3170         rtl_writephy(tp, 0x1e, 0x0020);
3171         rtl_w0w1_phy(tp, 0x15, 0x0100, 0x0000);
3172         rtl_writephy(tp, 0x1f, 0x0002);
3173         rtl_writephy(tp, 0x1f, 0x0000);
3174         rtl_writephy(tp, 0x0d, 0x0007);
3175         rtl_writephy(tp, 0x0e, 0x003c);
3176         rtl_writephy(tp, 0x0d, 0x4007);
3177         rtl_writephy(tp, 0x0e, 0x0006);
3178         rtl_writephy(tp, 0x0d, 0x0000);
3179
3180         /* Green feature */
3181         rtl_writephy(tp, 0x1f, 0x0003);
3182         rtl_w0w1_phy(tp, 0x19, 0x0001, 0x0000);
3183         rtl_w0w1_phy(tp, 0x10, 0x0400, 0x0000);
3184         rtl_writephy(tp, 0x1f, 0x0000);
3185         rtl_writephy(tp, 0x1f, 0x0005);
3186         rtl_w0w1_phy(tp, 0x01, 0x0100, 0x0000);
3187         rtl_writephy(tp, 0x1f, 0x0000);
3188
3189         /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3190         rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3191 }
3192
3193 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3194 {
3195         /* For 4-corner performance improve */
3196         rtl_writephy(tp, 0x1f, 0x0005);
3197         rtl_writephy(tp, 0x05, 0x8b80);
3198         rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
3199         rtl_writephy(tp, 0x1f, 0x0000);
3200
3201         /* PHY auto speed down */
3202         rtl_writephy(tp, 0x1f, 0x0007);
3203         rtl_writephy(tp, 0x1e, 0x002d);
3204         rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3205         rtl_writephy(tp, 0x1f, 0x0000);
3206         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3207
3208         /* Improve 10M EEE waveform */
3209         rtl_writephy(tp, 0x1f, 0x0005);
3210         rtl_writephy(tp, 0x05, 0x8b86);
3211         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3212         rtl_writephy(tp, 0x1f, 0x0000);
3213 }
3214
3215 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3216 {
3217         static const struct phy_reg phy_reg_init[] = {
3218                 /* Channel estimation fine tune */
3219                 { 0x1f, 0x0003 },
3220                 { 0x09, 0xa20f },
3221                 { 0x1f, 0x0000 },
3222
3223                 /* Modify green table for giga & fnet */
3224                 { 0x1f, 0x0005 },
3225                 { 0x05, 0x8b55 },
3226                 { 0x06, 0x0000 },
3227                 { 0x05, 0x8b5e },
3228                 { 0x06, 0x0000 },
3229                 { 0x05, 0x8b67 },
3230                 { 0x06, 0x0000 },
3231                 { 0x05, 0x8b70 },
3232                 { 0x06, 0x0000 },
3233                 { 0x1f, 0x0000 },
3234                 { 0x1f, 0x0007 },
3235                 { 0x1e, 0x0078 },
3236                 { 0x17, 0x0000 },
3237                 { 0x19, 0x00fb },
3238                 { 0x1f, 0x0000 },
3239
3240                 /* Modify green table for 10M */
3241                 { 0x1f, 0x0005 },
3242                 { 0x05, 0x8b79 },
3243                 { 0x06, 0xaa00 },
3244                 { 0x1f, 0x0000 },
3245
3246                 /* Disable hiimpedance detection (RTCT) */
3247                 { 0x1f, 0x0003 },
3248                 { 0x01, 0x328a },
3249                 { 0x1f, 0x0000 }
3250         };
3251
3252         rtl_apply_firmware(tp);
3253
3254         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3255
3256         rtl8168f_hw_phy_config(tp);
3257
3258         /* Improve 2-pair detection performance */
3259         rtl_writephy(tp, 0x1f, 0x0005);
3260         rtl_writephy(tp, 0x05, 0x8b85);
3261         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3262         rtl_writephy(tp, 0x1f, 0x0000);
3263 }
3264
3265 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3266 {
3267         rtl_apply_firmware(tp);
3268
3269         rtl8168f_hw_phy_config(tp);
3270 }
3271
3272 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3273 {
3274         static const struct phy_reg phy_reg_init[] = {
3275                 /* Channel estimation fine tune */
3276                 { 0x1f, 0x0003 },
3277                 { 0x09, 0xa20f },
3278                 { 0x1f, 0x0000 },
3279
3280                 /* Modify green table for giga & fnet */
3281                 { 0x1f, 0x0005 },
3282                 { 0x05, 0x8b55 },
3283                 { 0x06, 0x0000 },
3284                 { 0x05, 0x8b5e },
3285                 { 0x06, 0x0000 },
3286                 { 0x05, 0x8b67 },
3287                 { 0x06, 0x0000 },
3288                 { 0x05, 0x8b70 },
3289                 { 0x06, 0x0000 },
3290                 { 0x1f, 0x0000 },
3291                 { 0x1f, 0x0007 },
3292                 { 0x1e, 0x0078 },
3293                 { 0x17, 0x0000 },
3294                 { 0x19, 0x00aa },
3295                 { 0x1f, 0x0000 },
3296
3297                 /* Modify green table for 10M */
3298                 { 0x1f, 0x0005 },
3299                 { 0x05, 0x8b79 },
3300                 { 0x06, 0xaa00 },
3301                 { 0x1f, 0x0000 },
3302
3303                 /* Disable hiimpedance detection (RTCT) */
3304                 { 0x1f, 0x0003 },
3305                 { 0x01, 0x328a },
3306                 { 0x1f, 0x0000 }
3307         };
3308
3309
3310         rtl_apply_firmware(tp);
3311
3312         rtl8168f_hw_phy_config(tp);
3313
3314         /* Improve 2-pair detection performance */
3315         rtl_writephy(tp, 0x1f, 0x0005);
3316         rtl_writephy(tp, 0x05, 0x8b85);
3317         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3318         rtl_writephy(tp, 0x1f, 0x0000);
3319
3320         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3321
3322         /* Modify green table for giga */
3323         rtl_writephy(tp, 0x1f, 0x0005);
3324         rtl_writephy(tp, 0x05, 0x8b54);
3325         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3326         rtl_writephy(tp, 0x05, 0x8b5d);
3327         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3328         rtl_writephy(tp, 0x05, 0x8a7c);
3329         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3330         rtl_writephy(tp, 0x05, 0x8a7f);
3331         rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
3332         rtl_writephy(tp, 0x05, 0x8a82);
3333         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3334         rtl_writephy(tp, 0x05, 0x8a85);
3335         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3336         rtl_writephy(tp, 0x05, 0x8a88);
3337         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3338         rtl_writephy(tp, 0x1f, 0x0000);
3339
3340         /* uc same-seed solution */
3341         rtl_writephy(tp, 0x1f, 0x0005);
3342         rtl_writephy(tp, 0x05, 0x8b85);
3343         rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
3344         rtl_writephy(tp, 0x1f, 0x0000);
3345
3346         /* eee setting */
3347         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
3348         rtl_writephy(tp, 0x1f, 0x0005);
3349         rtl_writephy(tp, 0x05, 0x8b85);
3350         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3351         rtl_writephy(tp, 0x1f, 0x0004);
3352         rtl_writephy(tp, 0x1f, 0x0007);
3353         rtl_writephy(tp, 0x1e, 0x0020);
3354         rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
3355         rtl_writephy(tp, 0x1f, 0x0000);
3356         rtl_writephy(tp, 0x0d, 0x0007);
3357         rtl_writephy(tp, 0x0e, 0x003c);
3358         rtl_writephy(tp, 0x0d, 0x4007);
3359         rtl_writephy(tp, 0x0e, 0x0000);
3360         rtl_writephy(tp, 0x0d, 0x0000);
3361
3362         /* Green feature */
3363         rtl_writephy(tp, 0x1f, 0x0003);
3364         rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3365         rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3366         rtl_writephy(tp, 0x1f, 0x0000);
3367 }
3368
3369 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3370 {
3371         rtl_apply_firmware(tp);
3372
3373         rtl_writephy(tp, 0x1f, 0x0a46);
3374         if (rtl_readphy(tp, 0x10) & 0x0100) {
3375                 rtl_writephy(tp, 0x1f, 0x0bcc);
3376                 rtl_w0w1_phy(tp, 0x12, 0x0000, 0x8000);
3377         } else {
3378                 rtl_writephy(tp, 0x1f, 0x0bcc);
3379                 rtl_w0w1_phy(tp, 0x12, 0x8000, 0x0000);
3380         }
3381
3382         rtl_writephy(tp, 0x1f, 0x0a46);
3383         if (rtl_readphy(tp, 0x13) & 0x0100) {
3384                 rtl_writephy(tp, 0x1f, 0x0c41);
3385                 rtl_w0w1_phy(tp, 0x15, 0x0002, 0x0000);
3386         } else {
3387                 rtl_writephy(tp, 0x1f, 0x0c41);
3388                 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0002);
3389         }
3390
3391         /* Enable PHY auto speed down */
3392         rtl_writephy(tp, 0x1f, 0x0a44);
3393         rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3394
3395         rtl_writephy(tp, 0x1f, 0x0bcc);
3396         rtl_w0w1_phy(tp, 0x14, 0x0100, 0x0000);
3397         rtl_writephy(tp, 0x1f, 0x0a44);
3398         rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3399         rtl_writephy(tp, 0x1f, 0x0a43);
3400         rtl_writephy(tp, 0x13, 0x8084);
3401         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3402         rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3403
3404         /* EEE auto-fallback function */
3405         rtl_writephy(tp, 0x1f, 0x0a4b);
3406         rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3407
3408         /* Enable UC LPF tune function */
3409         rtl_writephy(tp, 0x1f, 0x0a43);
3410         rtl_writephy(tp, 0x13, 0x8012);
3411         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3412
3413         rtl_writephy(tp, 0x1f, 0x0c42);
3414         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3415
3416         /* Improve SWR Efficiency */
3417         rtl_writephy(tp, 0x1f, 0x0bcd);
3418         rtl_writephy(tp, 0x14, 0x5065);
3419         rtl_writephy(tp, 0x14, 0xd065);
3420         rtl_writephy(tp, 0x1f, 0x0bc8);
3421         rtl_writephy(tp, 0x11, 0x5655);
3422         rtl_writephy(tp, 0x1f, 0x0bcd);
3423         rtl_writephy(tp, 0x14, 0x1065);
3424         rtl_writephy(tp, 0x14, 0x9065);
3425         rtl_writephy(tp, 0x14, 0x1065);
3426
3427         /* Check ALDPS bit, disable it if enabled */
3428         rtl_writephy(tp, 0x1f, 0x0a43);
3429         if (rtl_readphy(tp, 0x10) & 0x0004)
3430                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3431
3432         rtl_writephy(tp, 0x1f, 0x0000);
3433 }
3434
3435 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3436 {
3437         rtl_apply_firmware(tp);
3438 }
3439
3440 static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3441 {
3442         u16 dout_tapbin;
3443         u32 data;
3444
3445         rtl_apply_firmware(tp);
3446
3447         /* CHN EST parameters adjust - giga master */
3448         rtl_writephy(tp, 0x1f, 0x0a43);
3449         rtl_writephy(tp, 0x13, 0x809b);
3450         rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
3451         rtl_writephy(tp, 0x13, 0x80a2);
3452         rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
3453         rtl_writephy(tp, 0x13, 0x80a4);
3454         rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
3455         rtl_writephy(tp, 0x13, 0x809c);
3456         rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
3457         rtl_writephy(tp, 0x1f, 0x0000);
3458
3459         /* CHN EST parameters adjust - giga slave */
3460         rtl_writephy(tp, 0x1f, 0x0a43);
3461         rtl_writephy(tp, 0x13, 0x80ad);
3462         rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
3463         rtl_writephy(tp, 0x13, 0x80b4);
3464         rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
3465         rtl_writephy(tp, 0x13, 0x80ac);
3466         rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
3467         rtl_writephy(tp, 0x1f, 0x0000);
3468
3469         /* CHN EST parameters adjust - fnet */
3470         rtl_writephy(tp, 0x1f, 0x0a43);
3471         rtl_writephy(tp, 0x13, 0x808e);
3472         rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
3473         rtl_writephy(tp, 0x13, 0x8090);
3474         rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
3475         rtl_writephy(tp, 0x13, 0x8092);
3476         rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
3477         rtl_writephy(tp, 0x1f, 0x0000);
3478
3479         /* enable R-tune & PGA-retune function */
3480         dout_tapbin = 0;
3481         rtl_writephy(tp, 0x1f, 0x0a46);
3482         data = rtl_readphy(tp, 0x13);
3483         data &= 3;
3484         data <<= 2;
3485         dout_tapbin |= data;
3486         data = rtl_readphy(tp, 0x12);
3487         data &= 0xc000;
3488         data >>= 14;
3489         dout_tapbin |= data;
3490         dout_tapbin = ~(dout_tapbin^0x08);
3491         dout_tapbin <<= 12;
3492         dout_tapbin &= 0xf000;
3493         rtl_writephy(tp, 0x1f, 0x0a43);
3494         rtl_writephy(tp, 0x13, 0x827a);
3495         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3496         rtl_writephy(tp, 0x13, 0x827b);
3497         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3498         rtl_writephy(tp, 0x13, 0x827c);
3499         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3500         rtl_writephy(tp, 0x13, 0x827d);
3501         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3502
3503         rtl_writephy(tp, 0x1f, 0x0a43);
3504         rtl_writephy(tp, 0x13, 0x0811);
3505         rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3506         rtl_writephy(tp, 0x1f, 0x0a42);
3507         rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3508         rtl_writephy(tp, 0x1f, 0x0000);
3509
3510         /* enable GPHY 10M */
3511         rtl_writephy(tp, 0x1f, 0x0a44);
3512         rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3513         rtl_writephy(tp, 0x1f, 0x0000);
3514
3515         /* SAR ADC performance */
3516         rtl_writephy(tp, 0x1f, 0x0bca);
3517         rtl_w0w1_phy(tp, 0x17, 0x4000, 0x3000);
3518         rtl_writephy(tp, 0x1f, 0x0000);
3519
3520         rtl_writephy(tp, 0x1f, 0x0a43);
3521         rtl_writephy(tp, 0x13, 0x803f);
3522         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3523         rtl_writephy(tp, 0x13, 0x8047);
3524         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3525         rtl_writephy(tp, 0x13, 0x804f);
3526         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3527         rtl_writephy(tp, 0x13, 0x8057);
3528         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3529         rtl_writephy(tp, 0x13, 0x805f);
3530         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3531         rtl_writephy(tp, 0x13, 0x8067);
3532         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3533         rtl_writephy(tp, 0x13, 0x806f);
3534         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3535         rtl_writephy(tp, 0x1f, 0x0000);
3536
3537         /* disable phy pfm mode */
3538         rtl_writephy(tp, 0x1f, 0x0a44);
3539         rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
3540         rtl_writephy(tp, 0x1f, 0x0000);
3541
3542         /* Check ALDPS bit, disable it if enabled */
3543         rtl_writephy(tp, 0x1f, 0x0a43);
3544         if (rtl_readphy(tp, 0x10) & 0x0004)
3545                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3546
3547         rtl_writephy(tp, 0x1f, 0x0000);
3548 }
3549
3550 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3551 {
3552         u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3553         u16 rlen;
3554         u32 data;
3555
3556         rtl_apply_firmware(tp);
3557
3558         /* CHIN EST parameter update */
3559         rtl_writephy(tp, 0x1f, 0x0a43);
3560         rtl_writephy(tp, 0x13, 0x808a);
3561         rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
3562         rtl_writephy(tp, 0x1f, 0x0000);
3563
3564         /* enable R-tune & PGA-retune function */
3565         rtl_writephy(tp, 0x1f, 0x0a43);
3566         rtl_writephy(tp, 0x13, 0x0811);
3567         rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3568         rtl_writephy(tp, 0x1f, 0x0a42);
3569         rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3570         rtl_writephy(tp, 0x1f, 0x0000);
3571
3572         /* enable GPHY 10M */
3573         rtl_writephy(tp, 0x1f, 0x0a44);
3574         rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3575         rtl_writephy(tp, 0x1f, 0x0000);
3576
3577         r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3578         data = r8168_mac_ocp_read(tp, 0xdd02);
3579         ioffset_p3 = ((data & 0x80)>>7);
3580         ioffset_p3 <<= 3;
3581
3582         data = r8168_mac_ocp_read(tp, 0xdd00);
3583         ioffset_p3 |= ((data & (0xe000))>>13);
3584         ioffset_p2 = ((data & (0x1e00))>>9);
3585         ioffset_p1 = ((data & (0x01e0))>>5);
3586         ioffset_p0 = ((data & 0x0010)>>4);
3587         ioffset_p0 <<= 3;
3588         ioffset_p0 |= (data & (0x07));
3589         data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3590
3591         if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
3592             (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) {
3593                 rtl_writephy(tp, 0x1f, 0x0bcf);
3594                 rtl_writephy(tp, 0x16, data);
3595                 rtl_writephy(tp, 0x1f, 0x0000);
3596         }
3597
3598         /* Modify rlen (TX LPF corner frequency) level */
3599         rtl_writephy(tp, 0x1f, 0x0bcd);
3600         data = rtl_readphy(tp, 0x16);
3601         data &= 0x000f;
3602         rlen = 0;
3603         if (data > 3)
3604                 rlen = data - 3;
3605         data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
3606         rtl_writephy(tp, 0x17, data);
3607         rtl_writephy(tp, 0x1f, 0x0bcd);
3608         rtl_writephy(tp, 0x1f, 0x0000);
3609
3610         /* disable phy pfm mode */
3611         rtl_writephy(tp, 0x1f, 0x0a44);
3612         rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
3613         rtl_writephy(tp, 0x1f, 0x0000);
3614
3615         /* Check ALDPS bit, disable it if enabled */
3616         rtl_writephy(tp, 0x1f, 0x0a43);
3617         if (rtl_readphy(tp, 0x10) & 0x0004)
3618                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3619
3620         rtl_writephy(tp, 0x1f, 0x0000);
3621 }
3622
3623 static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
3624 {
3625         /* Enable PHY auto speed down */
3626         rtl_writephy(tp, 0x1f, 0x0a44);
3627         rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3628         rtl_writephy(tp, 0x1f, 0x0000);
3629
3630         /* patch 10M & ALDPS */
3631         rtl_writephy(tp, 0x1f, 0x0bcc);
3632         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
3633         rtl_writephy(tp, 0x1f, 0x0a44);
3634         rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3635         rtl_writephy(tp, 0x1f, 0x0a43);
3636         rtl_writephy(tp, 0x13, 0x8084);
3637         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3638         rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3639         rtl_writephy(tp, 0x1f, 0x0000);
3640
3641         /* Enable EEE auto-fallback function */
3642         rtl_writephy(tp, 0x1f, 0x0a4b);
3643         rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3644         rtl_writephy(tp, 0x1f, 0x0000);
3645
3646         /* Enable UC LPF tune function */
3647         rtl_writephy(tp, 0x1f, 0x0a43);
3648         rtl_writephy(tp, 0x13, 0x8012);
3649         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3650         rtl_writephy(tp, 0x1f, 0x0000);
3651
3652         /* set rg_sel_sdm_rate */
3653         rtl_writephy(tp, 0x1f, 0x0c42);
3654         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3655         rtl_writephy(tp, 0x1f, 0x0000);
3656
3657         /* Check ALDPS bit, disable it if enabled */
3658         rtl_writephy(tp, 0x1f, 0x0a43);
3659         if (rtl_readphy(tp, 0x10) & 0x0004)
3660                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3661
3662         rtl_writephy(tp, 0x1f, 0x0000);
3663 }
3664
3665 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
3666 {
3667         /* patch 10M & ALDPS */
3668         rtl_writephy(tp, 0x1f, 0x0bcc);
3669         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
3670         rtl_writephy(tp, 0x1f, 0x0a44);
3671         rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3672         rtl_writephy(tp, 0x1f, 0x0a43);
3673         rtl_writephy(tp, 0x13, 0x8084);
3674         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3675         rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3676         rtl_writephy(tp, 0x1f, 0x0000);
3677
3678         /* Enable UC LPF tune function */
3679         rtl_writephy(tp, 0x1f, 0x0a43);
3680         rtl_writephy(tp, 0x13, 0x8012);
3681         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3682         rtl_writephy(tp, 0x1f, 0x0000);
3683
3684         /* Set rg_sel_sdm_rate */
3685         rtl_writephy(tp, 0x1f, 0x0c42);
3686         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3687         rtl_writephy(tp, 0x1f, 0x0000);
3688
3689         /* Channel estimation parameters */
3690         rtl_writephy(tp, 0x1f, 0x0a43);
3691         rtl_writephy(tp, 0x13, 0x80f3);
3692         rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
3693         rtl_writephy(tp, 0x13, 0x80f0);
3694         rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
3695         rtl_writephy(tp, 0x13, 0x80ef);
3696         rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
3697         rtl_writephy(tp, 0x13, 0x80f6);
3698         rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
3699         rtl_writephy(tp, 0x13, 0x80ec);
3700         rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
3701         rtl_writephy(tp, 0x13, 0x80ed);
3702         rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3703         rtl_writephy(tp, 0x13, 0x80f2);
3704         rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
3705         rtl_writephy(tp, 0x13, 0x80f4);
3706         rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
3707         rtl_writephy(tp, 0x1f, 0x0a43);
3708         rtl_writephy(tp, 0x13, 0x8110);
3709         rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
3710         rtl_writephy(tp, 0x13, 0x810f);
3711         rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
3712         rtl_writephy(tp, 0x13, 0x8111);
3713         rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
3714         rtl_writephy(tp, 0x13, 0x8113);
3715         rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
3716         rtl_writephy(tp, 0x13, 0x8115);
3717         rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
3718         rtl_writephy(tp, 0x13, 0x810e);
3719         rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
3720         rtl_writephy(tp, 0x13, 0x810c);
3721         rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3722         rtl_writephy(tp, 0x13, 0x810b);
3723         rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
3724         rtl_writephy(tp, 0x1f, 0x0a43);
3725         rtl_writephy(tp, 0x13, 0x80d1);
3726         rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
3727         rtl_writephy(tp, 0x13, 0x80cd);
3728         rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
3729         rtl_writephy(tp, 0x13, 0x80d3);
3730         rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
3731         rtl_writephy(tp, 0x13, 0x80d5);
3732         rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
3733         rtl_writephy(tp, 0x13, 0x80d7);
3734         rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
3735
3736         /* Force PWM-mode */
3737         rtl_writephy(tp, 0x1f, 0x0bcd);
3738         rtl_writephy(tp, 0x14, 0x5065);
3739         rtl_writephy(tp, 0x14, 0xd065);
3740         rtl_writephy(tp, 0x1f, 0x0bc8);
3741         rtl_writephy(tp, 0x12, 0x00ed);
3742         rtl_writephy(tp, 0x1f, 0x0bcd);
3743         rtl_writephy(tp, 0x14, 0x1065);
3744         rtl_writephy(tp, 0x14, 0x9065);
3745         rtl_writephy(tp, 0x14, 0x1065);
3746         rtl_writephy(tp, 0x1f, 0x0000);
3747
3748         /* Check ALDPS bit, disable it if enabled */
3749         rtl_writephy(tp, 0x1f, 0x0a43);
3750         if (rtl_readphy(tp, 0x10) & 0x0004)
3751                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3752
3753         rtl_writephy(tp, 0x1f, 0x0000);
3754 }
3755
3756 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3757 {
3758         static const struct phy_reg phy_reg_init[] = {
3759                 { 0x1f, 0x0003 },
3760                 { 0x08, 0x441d },
3761                 { 0x01, 0x9100 },
3762                 { 0x1f, 0x0000 }
3763         };
3764
3765         rtl_writephy(tp, 0x1f, 0x0000);
3766         rtl_patchphy(tp, 0x11, 1 << 12);
3767         rtl_patchphy(tp, 0x19, 1 << 13);
3768         rtl_patchphy(tp, 0x10, 1 << 15);
3769
3770         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3771 }
3772
3773 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3774 {
3775         static const struct phy_reg phy_reg_init[] = {
3776                 { 0x1f, 0x0005 },
3777                 { 0x1a, 0x0000 },
3778                 { 0x1f, 0x0000 },
3779
3780                 { 0x1f, 0x0004 },
3781                 { 0x1c, 0x0000 },
3782                 { 0x1f, 0x0000 },
3783
3784                 { 0x1f, 0x0001 },
3785                 { 0x15, 0x7701 },
3786                 { 0x1f, 0x0000 }
3787         };
3788
3789         /* Disable ALDPS before ram code */
3790         rtl_writephy(tp, 0x1f, 0x0000);
3791         rtl_writephy(tp, 0x18, 0x0310);
3792         msleep(100);
3793
3794         rtl_apply_firmware(tp);
3795
3796         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3797 }
3798
3799 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3800 {
3801         /* Disable ALDPS before setting firmware */
3802         rtl_writephy(tp, 0x1f, 0x0000);
3803         rtl_writephy(tp, 0x18, 0x0310);
3804         msleep(20);
3805
3806         rtl_apply_firmware(tp);
3807
3808         /* EEE setting */
3809         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3810         rtl_writephy(tp, 0x1f, 0x0004);
3811         rtl_writephy(tp, 0x10, 0x401f);
3812         rtl_writephy(tp, 0x19, 0x7030);
3813         rtl_writephy(tp, 0x1f, 0x0000);
3814 }
3815
3816 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3817 {
3818         static const struct phy_reg phy_reg_init[] = {
3819                 { 0x1f, 0x0004 },
3820                 { 0x10, 0xc07f },
3821                 { 0x19, 0x7030 },
3822                 { 0x1f, 0x0000 }
3823         };
3824
3825         /* Disable ALDPS before ram code */
3826         rtl_writephy(tp, 0x1f, 0x0000);
3827         rtl_writephy(tp, 0x18, 0x0310);
3828         msleep(100);
3829
3830         rtl_apply_firmware(tp);
3831
3832         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3833         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3834
3835         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3836 }
3837
3838 static void rtl_hw_phy_config(struct net_device *dev)
3839 {
3840         struct rtl8169_private *tp = netdev_priv(dev);
3841
3842         switch (tp->mac_version) {
3843         case RTL_GIGA_MAC_VER_01:
3844                 break;
3845         case RTL_GIGA_MAC_VER_02:
3846         case RTL_GIGA_MAC_VER_03:
3847                 rtl8169s_hw_phy_config(tp);
3848                 break;
3849         case RTL_GIGA_MAC_VER_04:
3850                 rtl8169sb_hw_phy_config(tp);
3851                 break;
3852         case RTL_GIGA_MAC_VER_05:
3853                 rtl8169scd_hw_phy_config(tp);
3854                 break;
3855         case RTL_GIGA_MAC_VER_06:
3856                 rtl8169sce_hw_phy_config(tp);
3857                 break;
3858         case RTL_GIGA_MAC_VER_07:
3859         case RTL_GIGA_MAC_VER_08:
3860         case RTL_GIGA_MAC_VER_09:
3861                 rtl8102e_hw_phy_config(tp);
3862                 break;
3863         case RTL_GIGA_MAC_VER_11:
3864                 rtl8168bb_hw_phy_config(tp);
3865                 break;
3866         case RTL_GIGA_MAC_VER_12:
3867                 rtl8168bef_hw_phy_config(tp);
3868                 break;
3869         case RTL_GIGA_MAC_VER_17:
3870                 rtl8168bef_hw_phy_config(tp);
3871                 break;
3872         case RTL_GIGA_MAC_VER_18:
3873                 rtl8168cp_1_hw_phy_config(tp);
3874                 break;
3875         case RTL_GIGA_MAC_VER_19:
3876                 rtl8168c_1_hw_phy_config(tp);
3877                 break;
3878         case RTL_GIGA_MAC_VER_20:
3879                 rtl8168c_2_hw_phy_config(tp);
3880                 break;
3881         case RTL_GIGA_MAC_VER_21:
3882                 rtl8168c_3_hw_phy_config(tp);
3883                 break;
3884         case RTL_GIGA_MAC_VER_22:
3885                 rtl8168c_4_hw_phy_config(tp);
3886                 break;
3887         case RTL_GIGA_MAC_VER_23:
3888         case RTL_GIGA_MAC_VER_24:
3889                 rtl8168cp_2_hw_phy_config(tp);
3890                 break;
3891         case RTL_GIGA_MAC_VER_25:
3892                 rtl8168d_1_hw_phy_config(tp);
3893                 break;
3894         case RTL_GIGA_MAC_VER_26:
3895                 rtl8168d_2_hw_phy_config(tp);
3896                 break;
3897         case RTL_GIGA_MAC_VER_27:
3898                 rtl8168d_3_hw_phy_config(tp);
3899                 break;
3900         case RTL_GIGA_MAC_VER_28:
3901                 rtl8168d_4_hw_phy_config(tp);
3902                 break;
3903         case RTL_GIGA_MAC_VER_29:
3904         case RTL_GIGA_MAC_VER_30:
3905                 rtl8105e_hw_phy_config(tp);
3906                 break;
3907         case RTL_GIGA_MAC_VER_31:
3908                 /* None. */
3909                 break;
3910         case RTL_GIGA_MAC_VER_32:
3911         case RTL_GIGA_MAC_VER_33:
3912                 rtl8168e_1_hw_phy_config(tp);
3913                 break;
3914         case RTL_GIGA_MAC_VER_34:
3915                 rtl8168e_2_hw_phy_config(tp);
3916                 break;
3917         case RTL_GIGA_MAC_VER_35:
3918                 rtl8168f_1_hw_phy_config(tp);
3919                 break;
3920         case RTL_GIGA_MAC_VER_36:
3921                 rtl8168f_2_hw_phy_config(tp);
3922                 break;
3923
3924         case RTL_GIGA_MAC_VER_37:
3925                 rtl8402_hw_phy_config(tp);
3926                 break;
3927
3928         case RTL_GIGA_MAC_VER_38:
3929                 rtl8411_hw_phy_config(tp);
3930                 break;
3931
3932         case RTL_GIGA_MAC_VER_39:
3933                 rtl8106e_hw_phy_config(tp);
3934                 break;
3935
3936         case RTL_GIGA_MAC_VER_40:
3937                 rtl8168g_1_hw_phy_config(tp);
3938                 break;
3939         case RTL_GIGA_MAC_VER_42:
3940         case RTL_GIGA_MAC_VER_43:
3941         case RTL_GIGA_MAC_VER_44:
3942                 rtl8168g_2_hw_phy_config(tp);
3943                 break;
3944         case RTL_GIGA_MAC_VER_45:
3945         case RTL_GIGA_MAC_VER_47:
3946                 rtl8168h_1_hw_phy_config(tp);
3947                 break;
3948         case RTL_GIGA_MAC_VER_46:
3949         case RTL_GIGA_MAC_VER_48:
3950                 rtl8168h_2_hw_phy_config(tp);
3951                 break;
3952
3953         case RTL_GIGA_MAC_VER_49:
3954                 rtl8168ep_1_hw_phy_config(tp);
3955                 break;
3956         case RTL_GIGA_MAC_VER_50:
3957         case RTL_GIGA_MAC_VER_51:
3958                 rtl8168ep_2_hw_phy_config(tp);
3959                 break;
3960
3961         case RTL_GIGA_MAC_VER_41:
3962         default:
3963                 break;
3964         }
3965 }
3966
3967 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3968 {
3969         if (!test_and_set_bit(flag, tp->wk.flags))
3970                 schedule_work(&tp->wk.work);
3971 }
3972
3973 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
3974 {
3975         return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
3976                (RTL_R8(tp, PHYstatus) & TBI_Enable);
3977 }
3978
3979 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3980 {
3981         rtl_hw_phy_config(dev);
3982
3983         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3984                 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3985                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
3986                 netif_dbg(tp, drv, dev,
3987                           "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3988                 RTL_W8(tp, 0x82, 0x01);
3989         }
3990
3991         /* We may have called phy_speed_down before */
3992         phy_speed_up(dev->phydev);
3993
3994         genphy_soft_reset(dev->phydev);
3995
3996         /* It was reported that several chips end up with 10MBit/Half on a
3997          * 1GBit link after resuming from S3. For whatever reason the PHY on
3998          * these chips doesn't properly start a renegotiation when soft-reset.
3999          * Explicitly requesting a renegotiation fixes this.
4000          */
4001         if (dev->phydev->autoneg == AUTONEG_ENABLE)
4002                 phy_restart_aneg(dev->phydev);
4003 }
4004
4005 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
4006 {
4007         rtl_lock_work(tp);
4008
4009         RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4010
4011         RTL_W32(tp, MAC4, addr[4] | addr[5] << 8);
4012         RTL_R32(tp, MAC4);
4013
4014         RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
4015         RTL_R32(tp, MAC0);
4016
4017         if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4018                 rtl_rar_exgmac_set(tp, addr);
4019
4020         RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4021
4022         rtl_unlock_work(tp);
4023 }
4024
4025 static int rtl_set_mac_address(struct net_device *dev, void *p)
4026 {
4027         struct rtl8169_private *tp = netdev_priv(dev);
4028         struct device *d = tp_to_dev(tp);
4029         int ret;
4030
4031         ret = eth_mac_addr(dev, p);
4032         if (ret)
4033                 return ret;
4034
4035         pm_runtime_get_noresume(d);
4036
4037         if (pm_runtime_active(d))
4038                 rtl_rar_set(tp, dev->dev_addr);
4039
4040         pm_runtime_put_noidle(d);
4041
4042         return 0;
4043 }
4044
4045 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4046 {
4047         if (!netif_running(dev))
4048                 return -ENODEV;
4049
4050         return phy_mii_ioctl(dev->phydev, ifr, cmd);
4051 }
4052
4053 static void rtl_init_mdio_ops(struct rtl8169_private *tp)
4054 {
4055         struct mdio_ops *ops = &tp->mdio_ops;
4056
4057         switch (tp->mac_version) {
4058         case RTL_GIGA_MAC_VER_27:
4059                 ops->write      = r8168dp_1_mdio_write;
4060                 ops->read       = r8168dp_1_mdio_read;
4061                 break;
4062         case RTL_GIGA_MAC_VER_28:
4063         case RTL_GIGA_MAC_VER_31:
4064                 ops->write      = r8168dp_2_mdio_write;
4065                 ops->read       = r8168dp_2_mdio_read;
4066                 break;
4067         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4068                 ops->write      = r8168g_mdio_write;
4069                 ops->read       = r8168g_mdio_read;
4070                 break;
4071         default:
4072                 ops->write      = r8169_mdio_write;
4073                 ops->read       = r8169_mdio_read;
4074                 break;
4075         }
4076 }
4077
4078 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
4079 {
4080         switch (tp->mac_version) {
4081         case RTL_GIGA_MAC_VER_25:
4082         case RTL_GIGA_MAC_VER_26:
4083         case RTL_GIGA_MAC_VER_29:
4084         case RTL_GIGA_MAC_VER_30:
4085         case RTL_GIGA_MAC_VER_32:
4086         case RTL_GIGA_MAC_VER_33:
4087         case RTL_GIGA_MAC_VER_34:
4088         case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_51:
4089                 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
4090                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
4091                 break;
4092         default:
4093                 break;
4094         }
4095 }
4096
4097 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
4098 {
4099         struct phy_device *phydev;
4100
4101         if (!__rtl8169_get_wol(tp))
4102                 return false;
4103
4104         /* phydev may not be attached to netdevice */
4105         phydev = mdiobus_get_phy(tp->mii_bus, 0);
4106
4107         phy_speed_down(phydev, false);
4108         rtl_wol_suspend_quirk(tp);
4109
4110         return true;
4111 }
4112
4113 static void r8168_pll_power_down(struct rtl8169_private *tp)
4114 {
4115         if (r8168_check_dash(tp))
4116                 return;
4117
4118         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4119             tp->mac_version == RTL_GIGA_MAC_VER_33)
4120                 rtl_ephy_write(tp, 0x19, 0xff64);
4121
4122         if (rtl_wol_pll_power_down(tp))
4123                 return;
4124
4125         switch (tp->mac_version) {
4126         case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
4127         case RTL_GIGA_MAC_VER_37:
4128         case RTL_GIGA_MAC_VER_39:
4129         case RTL_GIGA_MAC_VER_43:
4130         case RTL_GIGA_MAC_VER_44:
4131         case RTL_GIGA_MAC_VER_45:
4132         case RTL_GIGA_MAC_VER_46:
4133         case RTL_GIGA_MAC_VER_47:
4134         case RTL_GIGA_MAC_VER_48:
4135         case RTL_GIGA_MAC_VER_50:
4136         case RTL_GIGA_MAC_VER_51:
4137                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
4138                 break;
4139         case RTL_GIGA_MAC_VER_40:
4140         case RTL_GIGA_MAC_VER_41:
4141         case RTL_GIGA_MAC_VER_49:
4142                 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
4143                              0xfc000000, ERIAR_EXGMAC);
4144                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
4145                 break;
4146         }
4147 }
4148
4149 static void r8168_pll_power_up(struct rtl8169_private *tp)
4150 {
4151         switch (tp->mac_version) {
4152         case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
4153         case RTL_GIGA_MAC_VER_37:
4154         case RTL_GIGA_MAC_VER_39:
4155         case RTL_GIGA_MAC_VER_43:
4156                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);
4157                 break;
4158         case RTL_GIGA_MAC_VER_44:
4159         case RTL_GIGA_MAC_VER_45:
4160         case RTL_GIGA_MAC_VER_46:
4161         case RTL_GIGA_MAC_VER_47:
4162         case RTL_GIGA_MAC_VER_48:
4163         case RTL_GIGA_MAC_VER_50:
4164         case RTL_GIGA_MAC_VER_51:
4165                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
4166                 break;
4167         case RTL_GIGA_MAC_VER_40:
4168         case RTL_GIGA_MAC_VER_41:
4169         case RTL_GIGA_MAC_VER_49:
4170                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
4171                 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
4172                              0x00000000, ERIAR_EXGMAC);
4173                 break;
4174         }
4175
4176         phy_resume(tp->dev->phydev);
4177         /* give MAC/PHY some time to resume */
4178         msleep(20);
4179 }
4180
4181 static void rtl_pll_power_down(struct rtl8169_private *tp)
4182 {
4183         switch (tp->mac_version) {
4184         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4185         case RTL_GIGA_MAC_VER_13 ... RTL_GIGA_MAC_VER_15:
4186                 break;
4187         default:
4188                 r8168_pll_power_down(tp);
4189         }
4190 }
4191
4192 static void rtl_pll_power_up(struct rtl8169_private *tp)
4193 {
4194         switch (tp->mac_version) {
4195         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4196         case RTL_GIGA_MAC_VER_13 ... RTL_GIGA_MAC_VER_15:
4197                 break;
4198         default:
4199                 r8168_pll_power_up(tp);
4200         }
4201 }
4202
4203 static void rtl_init_rxcfg(struct rtl8169_private *tp)
4204 {
4205         switch (tp->mac_version) {
4206         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4207         case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
4208                 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4209                 break;
4210         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
4211         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
4212         case RTL_GIGA_MAC_VER_38:
4213                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4214                 break;
4215         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4216                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
4217                 break;
4218         default:
4219                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
4220                 break;
4221         }
4222 }
4223
4224 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4225 {
4226         tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
4227 }
4228
4229 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4230 {
4231         if (tp->jumbo_ops.enable) {
4232                 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4233                 tp->jumbo_ops.enable(tp);
4234                 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4235         }
4236 }
4237
4238 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4239 {
4240         if (tp->jumbo_ops.disable) {
4241                 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4242                 tp->jumbo_ops.disable(tp);
4243                 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4244         }
4245 }
4246
4247 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4248 {
4249         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4250         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
4251         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
4252 }
4253
4254 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4255 {
4256         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4257         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
4258         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4259 }
4260
4261 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4262 {
4263         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4264 }
4265
4266 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4267 {
4268         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4269 }
4270
4271 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4272 {
4273         RTL_W8(tp, MaxTxPacketSize, 0x3f);
4274         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4275         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
4276         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
4277 }
4278
4279 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4280 {
4281         RTL_W8(tp, MaxTxPacketSize, 0x0c);
4282         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4283         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
4284         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4285 }
4286
4287 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4288 {
4289         rtl_tx_performance_tweak(tp,
4290                 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
4291 }
4292
4293 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4294 {
4295         rtl_tx_performance_tweak(tp,
4296                 PCI_EXP_DEVCTL_READRQ_4096B | PCI_EXP_DEVCTL_NOSNOOP_EN);
4297 }
4298
4299 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4300 {
4301         r8168b_0_hw_jumbo_enable(tp);
4302
4303         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
4304 }
4305
4306 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4307 {
4308         r8168b_0_hw_jumbo_disable(tp);
4309
4310         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4311 }
4312
4313 static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
4314 {
4315         struct jumbo_ops *ops = &tp->jumbo_ops;
4316
4317         switch (tp->mac_version) {
4318         case RTL_GIGA_MAC_VER_11:
4319                 ops->disable    = r8168b_0_hw_jumbo_disable;
4320                 ops->enable     = r8168b_0_hw_jumbo_enable;
4321                 break;
4322         case RTL_GIGA_MAC_VER_12:
4323         case RTL_GIGA_MAC_VER_17:
4324                 ops->disable    = r8168b_1_hw_jumbo_disable;
4325                 ops->enable     = r8168b_1_hw_jumbo_enable;
4326                 break;
4327         case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
4328         case RTL_GIGA_MAC_VER_19:
4329         case RTL_GIGA_MAC_VER_20:
4330         case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
4331         case RTL_GIGA_MAC_VER_22:
4332         case RTL_GIGA_MAC_VER_23:
4333         case RTL_GIGA_MAC_VER_24:
4334         case RTL_GIGA_MAC_VER_25:
4335         case RTL_GIGA_MAC_VER_26:
4336                 ops->disable    = r8168c_hw_jumbo_disable;
4337                 ops->enable     = r8168c_hw_jumbo_enable;
4338                 break;
4339         case RTL_GIGA_MAC_VER_27:
4340         case RTL_GIGA_MAC_VER_28:
4341                 ops->disable    = r8168dp_hw_jumbo_disable;
4342                 ops->enable     = r8168dp_hw_jumbo_enable;
4343                 break;
4344         case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
4345         case RTL_GIGA_MAC_VER_32:
4346         case RTL_GIGA_MAC_VER_33:
4347         case RTL_GIGA_MAC_VER_34:
4348                 ops->disable    = r8168e_hw_jumbo_disable;
4349                 ops->enable     = r8168e_hw_jumbo_enable;
4350                 break;
4351
4352         /*
4353          * No action needed for jumbo frames with 8169.
4354          * No jumbo for 810x at all.
4355          */
4356         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4357         default:
4358                 ops->disable    = NULL;
4359                 ops->enable     = NULL;
4360                 break;
4361         }
4362 }
4363
4364 DECLARE_RTL_COND(rtl_chipcmd_cond)
4365 {
4366         return RTL_R8(tp, ChipCmd) & CmdReset;
4367 }
4368
4369 static void rtl_hw_reset(struct rtl8169_private *tp)
4370 {
4371         RTL_W8(tp, ChipCmd, CmdReset);
4372
4373         rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
4374 }
4375
4376 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
4377 {
4378         struct rtl_fw *rtl_fw;
4379         const char *name;
4380         int rc = -ENOMEM;
4381
4382         name = rtl_lookup_firmware_name(tp);
4383         if (!name)
4384                 goto out_no_firmware;
4385
4386         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4387         if (!rtl_fw)
4388                 goto err_warn;
4389
4390         rc = request_firmware(&rtl_fw->fw, name, tp_to_dev(tp));
4391         if (rc < 0)
4392                 goto err_free;
4393
4394         rc = rtl_check_firmware(tp, rtl_fw);
4395         if (rc < 0)
4396                 goto err_release_firmware;
4397
4398         tp->rtl_fw = rtl_fw;
4399 out:
4400         return;
4401
4402 err_release_firmware:
4403         release_firmware(rtl_fw->fw);
4404 err_free:
4405         kfree(rtl_fw);
4406 err_warn:
4407         netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4408                    name, rc);
4409 out_no_firmware:
4410         tp->rtl_fw = NULL;
4411         goto out;
4412 }
4413
4414 static void rtl_request_firmware(struct rtl8169_private *tp)
4415 {
4416         if (IS_ERR(tp->rtl_fw))
4417                 rtl_request_uncached_firmware(tp);
4418 }
4419
4420 static void rtl_rx_close(struct rtl8169_private *tp)
4421 {
4422         RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
4423 }
4424
4425 DECLARE_RTL_COND(rtl_npq_cond)
4426 {
4427         return RTL_R8(tp, TxPoll) & NPQ;
4428 }
4429
4430 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4431 {
4432         return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
4433 }
4434
4435 static void rtl8169_hw_reset(struct rtl8169_private *tp)
4436 {
4437         /* Disable interrupts */
4438         rtl8169_irq_mask_and_ack(tp);
4439
4440         rtl_rx_close(tp);
4441
4442         switch (tp->mac_version) {
4443         case RTL_GIGA_MAC_VER_27:
4444         case RTL_GIGA_MAC_VER_28:
4445         case RTL_GIGA_MAC_VER_31:
4446                 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
4447                 break;
4448         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
4449         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4450                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4451                 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
4452                 break;
4453         default:
4454                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4455                 udelay(100);
4456                 break;
4457         }
4458
4459         rtl_hw_reset(tp);
4460 }
4461
4462 static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
4463 {
4464         u32 val = TX_DMA_BURST << TxDMAShift |
4465                   InterFrameGap << TxInterFrameGapShift;
4466
4467         if (tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
4468             tp->mac_version != RTL_GIGA_MAC_VER_39)
4469                 val |= TXCFG_AUTO_FIFO;
4470
4471         RTL_W32(tp, TxConfig, val);
4472 }
4473
4474 static void rtl_set_rx_max_size(struct rtl8169_private *tp)
4475 {
4476         /* Low hurts. Let's disable the filtering. */
4477         RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
4478 }
4479
4480 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
4481 {
4482         /*
4483          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4484          * register to be written before TxDescAddrLow to work.
4485          * Switching from MMIO to I/O access fixes the issue as well.
4486          */
4487         RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4488         RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4489         RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4490         RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4491 }
4492
4493 static void rtl8169_set_magic_reg(struct rtl8169_private *tp, unsigned mac_version)
4494 {
4495         u32 val;
4496
4497         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4498                 val = 0x000fff00;
4499         else if (tp->mac_version == RTL_GIGA_MAC_VER_06)
4500                 val = 0x00ffff00;
4501         else
4502                 return;
4503
4504         if (RTL_R8(tp, Config2) & PCI_Clock_66MHz)
4505                 val |= 0xff;
4506
4507         RTL_W32(tp, 0x7c, val);
4508 }
4509
4510 static void rtl_set_rx_mode(struct net_device *dev)
4511 {
4512         struct rtl8169_private *tp = netdev_priv(dev);
4513         u32 mc_filter[2];       /* Multicast hash filter */
4514         int rx_mode;
4515         u32 tmp = 0;
4516
4517         if (dev->flags & IFF_PROMISC) {
4518                 /* Unconditionally log net taps. */
4519                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4520                 rx_mode =
4521                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4522                     AcceptAllPhys;
4523                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4524         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4525                    (dev->flags & IFF_ALLMULTI)) {
4526                 /* Too many to filter perfectly -- accept all multicasts. */
4527                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4528                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4529         } else {
4530                 struct netdev_hw_addr *ha;
4531
4532                 rx_mode = AcceptBroadcast | AcceptMyPhys;
4533                 mc_filter[1] = mc_filter[0] = 0;
4534                 netdev_for_each_mc_addr(ha, dev) {
4535                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4536                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4537                         rx_mode |= AcceptMulticast;
4538                 }
4539         }
4540
4541         if (dev->features & NETIF_F_RXALL)
4542                 rx_mode |= (AcceptErr | AcceptRunt);
4543
4544         tmp = (RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4545
4546         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4547                 u32 data = mc_filter[0];
4548
4549                 mc_filter[0] = swab32(mc_filter[1]);
4550                 mc_filter[1] = swab32(data);
4551         }
4552
4553         if (tp->mac_version == RTL_GIGA_MAC_VER_35)
4554                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4555
4556         RTL_W32(tp, MAR0 + 4, mc_filter[1]);
4557         RTL_W32(tp, MAR0 + 0, mc_filter[0]);
4558
4559         RTL_W32(tp, RxConfig, tmp);
4560 }
4561
4562 static void rtl_hw_start(struct  rtl8169_private *tp)
4563 {
4564         RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4565
4566         tp->hw_start(tp);
4567
4568         rtl_set_rx_max_size(tp);
4569         rtl_set_rx_tx_desc_registers(tp);
4570         RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4571
4572         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4573         RTL_R8(tp, IntrMask);
4574         RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
4575         rtl_init_rxcfg(tp);
4576         rtl_set_tx_config_registers(tp);
4577
4578         rtl_set_rx_mode(tp->dev);
4579         /* no early-rx interrupts */
4580         RTL_W16(tp, MultiIntr, RTL_R16(tp, MultiIntr) & 0xf000);
4581         rtl_irq_enable(tp);
4582 }
4583
4584 static void rtl_hw_start_8169(struct rtl8169_private *tp)
4585 {
4586         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4587                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4588
4589         RTL_W8(tp, EarlyTxThres, NoEarlyTx);
4590
4591         tp->cp_cmd |= PCIMulRW;
4592
4593         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4594             tp->mac_version == RTL_GIGA_MAC_VER_03) {
4595                 netif_dbg(tp, drv, tp->dev,
4596                           "Set MAC Reg C+CR Offset 0xe0. Bit 3 and Bit 14 MUST be 1\n");
4597                 tp->cp_cmd |= (1 << 14);
4598         }
4599
4600         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4601
4602         rtl8169_set_magic_reg(tp, tp->mac_version);
4603
4604         /*
4605          * Undocumented corner. Supposedly:
4606          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4607          */
4608         RTL_W16(tp, IntrMitigate, 0x0000);
4609
4610         RTL_W32(tp, RxMissed, 0);
4611 }
4612
4613 DECLARE_RTL_COND(rtl_csiar_cond)
4614 {
4615         return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
4616 }
4617
4618 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
4619 {
4620         u32 func = PCI_FUNC(tp->pci_dev->devfn);
4621
4622         RTL_W32(tp, CSIDR, value);
4623         RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4624                 CSIAR_BYTE_ENABLE | func << 16);
4625
4626         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4627 }
4628
4629 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
4630 {
4631         u32 func = PCI_FUNC(tp->pci_dev->devfn);
4632
4633         RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
4634                 CSIAR_BYTE_ENABLE);
4635
4636         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4637                 RTL_R32(tp, CSIDR) : ~0;
4638 }
4639
4640 static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val)
4641 {
4642         struct pci_dev *pdev = tp->pci_dev;
4643         u32 csi;
4644
4645         /* According to Realtek the value at config space address 0x070f
4646          * controls the L0s/L1 entrance latency. We try standard ECAM access
4647          * first and if it fails fall back to CSI.
4648          */
4649         if (pdev->cfg_size > 0x070f &&
4650             pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
4651                 return;
4652
4653         netdev_notice_once(tp->dev,
4654                 "No native access to PCI extended config space, falling back to CSI\n");
4655         csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4656         rtl_csi_write(tp, 0x070c, csi | val << 24);
4657 }
4658
4659 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
4660 {
4661         rtl_csi_access_enable(tp, 0x27);
4662 }
4663
4664 struct ephy_info {
4665         unsigned int offset;
4666         u16 mask;
4667         u16 bits;
4668 };
4669
4670 static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
4671                           int len)
4672 {
4673         u16 w;
4674
4675         while (len-- > 0) {
4676                 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4677                 rtl_ephy_write(tp, e->offset, w);
4678                 e++;
4679         }
4680 }
4681
4682 static void rtl_disable_clock_request(struct rtl8169_private *tp)
4683 {
4684         pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
4685                                    PCI_EXP_LNKCTL_CLKREQ_EN);
4686 }
4687
4688 static void rtl_enable_clock_request(struct rtl8169_private *tp)
4689 {
4690         pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
4691                                  PCI_EXP_LNKCTL_CLKREQ_EN);
4692 }
4693
4694 static void rtl_pcie_state_l2l3_enable(struct rtl8169_private *tp, bool enable)
4695 {
4696         u8 data;
4697
4698         data = RTL_R8(tp, Config3);
4699
4700         if (enable)
4701                 data |= Rdy_to_L23;
4702         else
4703                 data &= ~Rdy_to_L23;
4704
4705         RTL_W8(tp, Config3, data);
4706 }
4707
4708 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
4709 {
4710         if (enable) {
4711                 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);
4712                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);
4713         } else {
4714                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
4715                 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
4716         }
4717
4718         udelay(10);
4719 }
4720
4721 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
4722 {
4723         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4724
4725         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4726         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4727
4728         if (tp->dev->mtu <= ETH_DATA_LEN) {
4729                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B |
4730                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
4731         }
4732 }
4733
4734 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
4735 {
4736         rtl_hw_start_8168bb(tp);
4737
4738         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4739
4740         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4741 }
4742
4743 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
4744 {
4745         RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
4746
4747         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4748
4749         if (tp->dev->mtu <= ETH_DATA_LEN)
4750                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4751
4752         rtl_disable_clock_request(tp);
4753
4754         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4755         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4756 }
4757
4758 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
4759 {
4760         static const struct ephy_info e_info_8168cp[] = {
4761                 { 0x01, 0,      0x0001 },
4762                 { 0x02, 0x0800, 0x1000 },
4763                 { 0x03, 0,      0x0042 },
4764                 { 0x06, 0x0080, 0x0000 },
4765                 { 0x07, 0,      0x2000 }
4766         };
4767
4768         rtl_set_def_aspm_entry_latency(tp);
4769
4770         rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4771
4772         __rtl_hw_start_8168cp(tp);
4773 }
4774
4775 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
4776 {
4777         rtl_set_def_aspm_entry_latency(tp);
4778
4779         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4780
4781         if (tp->dev->mtu <= ETH_DATA_LEN)
4782                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4783
4784         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4785         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4786 }
4787
4788 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
4789 {
4790         rtl_set_def_aspm_entry_latency(tp);
4791
4792         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4793
4794         /* Magic. */
4795         RTL_W8(tp, DBG_REG, 0x20);
4796
4797         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4798
4799         if (tp->dev->mtu <= ETH_DATA_LEN)
4800                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4801
4802         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4803         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4804 }
4805
4806 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
4807 {
4808         static const struct ephy_info e_info_8168c_1[] = {
4809                 { 0x02, 0x0800, 0x1000 },
4810                 { 0x03, 0,      0x0002 },
4811                 { 0x06, 0x0080, 0x0000 }
4812         };
4813
4814         rtl_set_def_aspm_entry_latency(tp);
4815
4816         RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4817
4818         rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4819
4820         __rtl_hw_start_8168cp(tp);
4821 }
4822
4823 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
4824 {
4825         static const struct ephy_info e_info_8168c_2[] = {
4826                 { 0x01, 0,      0x0001 },
4827                 { 0x03, 0x0400, 0x0220 }
4828         };
4829
4830         rtl_set_def_aspm_entry_latency(tp);
4831
4832         rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4833
4834         __rtl_hw_start_8168cp(tp);
4835 }
4836
4837 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
4838 {
4839         rtl_hw_start_8168c_2(tp);
4840 }
4841
4842 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
4843 {
4844         rtl_set_def_aspm_entry_latency(tp);
4845
4846         __rtl_hw_start_8168cp(tp);
4847 }
4848
4849 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
4850 {
4851         rtl_set_def_aspm_entry_latency(tp);
4852
4853         rtl_disable_clock_request(tp);
4854
4855         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4856
4857         if (tp->dev->mtu <= ETH_DATA_LEN)
4858                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4859
4860         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4861         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4862 }
4863
4864 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4865 {
4866         rtl_set_def_aspm_entry_latency(tp);
4867
4868         if (tp->dev->mtu <= ETH_DATA_LEN)
4869                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4870
4871         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4872
4873         rtl_disable_clock_request(tp);
4874 }
4875
4876 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
4877 {
4878         static const struct ephy_info e_info_8168d_4[] = {
4879                 { 0x0b, 0x0000, 0x0048 },
4880                 { 0x19, 0x0020, 0x0050 },
4881                 { 0x0c, 0x0100, 0x0020 }
4882         };
4883
4884         rtl_set_def_aspm_entry_latency(tp);
4885
4886         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4887
4888         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4889
4890         rtl_ephy_init(tp, e_info_8168d_4, ARRAY_SIZE(e_info_8168d_4));
4891
4892         rtl_enable_clock_request(tp);
4893 }
4894
4895 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
4896 {
4897         static const struct ephy_info e_info_8168e_1[] = {
4898                 { 0x00, 0x0200, 0x0100 },
4899                 { 0x00, 0x0000, 0x0004 },
4900                 { 0x06, 0x0002, 0x0001 },
4901                 { 0x06, 0x0000, 0x0030 },
4902                 { 0x07, 0x0000, 0x2000 },
4903                 { 0x00, 0x0000, 0x0020 },
4904                 { 0x03, 0x5800, 0x2000 },
4905                 { 0x03, 0x0000, 0x0001 },
4906                 { 0x01, 0x0800, 0x1000 },
4907                 { 0x07, 0x0000, 0x4000 },
4908                 { 0x1e, 0x0000, 0x2000 },
4909                 { 0x19, 0xffff, 0xfe6c },
4910                 { 0x0a, 0x0000, 0x0040 }
4911         };
4912
4913         rtl_set_def_aspm_entry_latency(tp);
4914
4915         rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
4916
4917         if (tp->dev->mtu <= ETH_DATA_LEN)
4918                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4919
4920         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4921
4922         rtl_disable_clock_request(tp);
4923
4924         /* Reset tx FIFO pointer */
4925         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
4926         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
4927
4928         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4929 }
4930
4931 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
4932 {
4933         static const struct ephy_info e_info_8168e_2[] = {
4934                 { 0x09, 0x0000, 0x0080 },
4935                 { 0x19, 0x0000, 0x0224 }
4936         };
4937
4938         rtl_set_def_aspm_entry_latency(tp);
4939
4940         rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
4941
4942         if (tp->dev->mtu <= ETH_DATA_LEN)
4943                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4944
4945         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4946         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4947         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4948         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4949         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4950         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
4951         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4952         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
4953
4954         RTL_W8(tp, MaxTxPacketSize, EarlySize);
4955
4956         rtl_disable_clock_request(tp);
4957
4958         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
4959
4960         /* Adjust EEE LED frequency */
4961         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
4962
4963         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
4964         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
4965         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4966
4967         rtl_hw_aspm_clkreq_enable(tp, true);
4968 }
4969
4970 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
4971 {
4972         rtl_set_def_aspm_entry_latency(tp);
4973
4974         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4975
4976         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4977         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4978         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4979         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4980         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
4981         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
4982         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4983         rtl_w0w1_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4984         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4985         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
4986
4987         RTL_W8(tp, MaxTxPacketSize, EarlySize);
4988
4989         rtl_disable_clock_request(tp);
4990
4991         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
4992         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
4993         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
4994         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4995 }
4996
4997 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
4998 {
4999         static const struct ephy_info e_info_8168f_1[] = {
5000                 { 0x06, 0x00c0, 0x0020 },
5001                 { 0x08, 0x0001, 0x0002 },
5002                 { 0x09, 0x0000, 0x0080 },
5003                 { 0x19, 0x0000, 0x0224 }
5004         };
5005
5006         rtl_hw_start_8168f(tp);
5007
5008         rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5009
5010         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5011
5012         /* Adjust EEE LED frequency */
5013         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5014 }
5015
5016 static void rtl_hw_start_8411(struct rtl8169_private *tp)
5017 {
5018         static const struct ephy_info e_info_8168f_1[] = {
5019                 { 0x06, 0x00c0, 0x0020 },
5020                 { 0x0f, 0xffff, 0x5200 },
5021                 { 0x1e, 0x0000, 0x4000 },
5022                 { 0x19, 0x0000, 0x0224 }
5023         };
5024
5025         rtl_hw_start_8168f(tp);
5026         rtl_pcie_state_l2l3_enable(tp, false);
5027
5028         rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5029
5030         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
5031 }
5032
5033 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
5034 {
5035         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
5036         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5037         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5038         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5039
5040         rtl_set_def_aspm_entry_latency(tp);
5041
5042         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5043
5044         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5045         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5046         rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
5047
5048         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5049         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5050
5051         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5052         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5053
5054         /* Adjust EEE LED frequency */
5055         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5056
5057         rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5058         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
5059
5060         rtl_pcie_state_l2l3_enable(tp, false);
5061 }
5062
5063 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
5064 {
5065         static const struct ephy_info e_info_8168g_1[] = {
5066                 { 0x00, 0x0000, 0x0008 },
5067                 { 0x0c, 0x37d0, 0x0820 },
5068                 { 0x1e, 0x0000, 0x0001 },
5069                 { 0x19, 0x8000, 0x0000 }
5070         };
5071
5072         rtl_hw_start_8168g(tp);
5073
5074         /* disable aspm and clock request before access ephy */
5075         rtl_hw_aspm_clkreq_enable(tp, false);
5076         rtl_ephy_init(tp, e_info_8168g_1, ARRAY_SIZE(e_info_8168g_1));
5077         rtl_hw_aspm_clkreq_enable(tp, true);
5078 }
5079
5080 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
5081 {
5082         static const struct ephy_info e_info_8168g_2[] = {
5083                 { 0x00, 0x0000, 0x0008 },
5084                 { 0x0c, 0x3df0, 0x0200 },
5085                 { 0x19, 0xffff, 0xfc00 },
5086                 { 0x1e, 0xffff, 0x20eb }
5087         };
5088
5089         rtl_hw_start_8168g(tp);
5090
5091         /* disable aspm and clock request before access ephy */
5092         RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
5093         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
5094         rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
5095 }
5096
5097 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
5098 {
5099         static const struct ephy_info e_info_8411_2[] = {
5100                 { 0x00, 0x0000, 0x0008 },
5101                 { 0x0c, 0x3df0, 0x0200 },
5102                 { 0x0f, 0xffff, 0x5200 },
5103                 { 0x19, 0x0020, 0x0000 },
5104                 { 0x1e, 0x0000, 0x2000 }
5105         };
5106
5107         rtl_hw_start_8168g(tp);
5108
5109         /* disable aspm and clock request before access ephy */
5110         rtl_hw_aspm_clkreq_enable(tp, false);
5111         rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
5112         rtl_hw_aspm_clkreq_enable(tp, true);
5113 }
5114
5115 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
5116 {
5117         int rg_saw_cnt;
5118         u32 data;
5119         static const struct ephy_info e_info_8168h_1[] = {
5120                 { 0x1e, 0x0800, 0x0001 },
5121                 { 0x1d, 0x0000, 0x0800 },
5122                 { 0x05, 0xffff, 0x2089 },
5123                 { 0x06, 0xffff, 0x5881 },
5124                 { 0x04, 0xffff, 0x154a },
5125                 { 0x01, 0xffff, 0x068b }
5126         };
5127
5128         /* disable aspm and clock request before access ephy */
5129         rtl_hw_aspm_clkreq_enable(tp, false);
5130         rtl_ephy_init(tp, e_info_8168h_1, ARRAY_SIZE(e_info_8168h_1));
5131
5132         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
5133         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5134         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5135         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5136
5137         rtl_set_def_aspm_entry_latency(tp);
5138
5139         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5140
5141         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5142         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5143
5144         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_1111, 0x0010, 0x00, ERIAR_EXGMAC);
5145
5146         rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f00, 0x00, ERIAR_EXGMAC);
5147
5148         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
5149
5150         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5151         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5152
5153         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5154         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5155
5156         /* Adjust EEE LED frequency */
5157         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5158
5159         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5160         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5161
5162         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
5163
5164         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
5165
5166         rtl_pcie_state_l2l3_enable(tp, false);
5167
5168         rtl_writephy(tp, 0x1f, 0x0c42);
5169         rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
5170         rtl_writephy(tp, 0x1f, 0x0000);
5171         if (rg_saw_cnt > 0) {
5172                 u16 sw_cnt_1ms_ini;
5173
5174                 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
5175                 sw_cnt_1ms_ini &= 0x0fff;
5176                 data = r8168_mac_ocp_read(tp, 0xd412);
5177                 data &= ~0x0fff;
5178                 data |= sw_cnt_1ms_ini;
5179                 r8168_mac_ocp_write(tp, 0xd412, data);
5180         }
5181
5182         data = r8168_mac_ocp_read(tp, 0xe056);
5183         data &= ~0xf0;
5184         data |= 0x70;
5185         r8168_mac_ocp_write(tp, 0xe056, data);
5186
5187         data = r8168_mac_ocp_read(tp, 0xe052);
5188         data &= ~0x6000;
5189         data |= 0x8008;
5190         r8168_mac_ocp_write(tp, 0xe052, data);
5191
5192         data = r8168_mac_ocp_read(tp, 0xe0d6);
5193         data &= ~0x01ff;
5194         data |= 0x017f;
5195         r8168_mac_ocp_write(tp, 0xe0d6, data);
5196
5197         data = r8168_mac_ocp_read(tp, 0xd420);
5198         data &= ~0x0fff;
5199         data |= 0x047f;
5200         r8168_mac_ocp_write(tp, 0xd420, data);
5201
5202         r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
5203         r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
5204         r8168_mac_ocp_write(tp, 0xc094, 0x0000);
5205         r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
5206
5207         rtl_hw_aspm_clkreq_enable(tp, true);
5208 }
5209
5210 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
5211 {
5212         rtl8168ep_stop_cmac(tp);
5213
5214         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
5215         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x2f, ERIAR_EXGMAC);
5216         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x5f, ERIAR_EXGMAC);
5217         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5218
5219         rtl_set_def_aspm_entry_latency(tp);
5220
5221         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5222
5223         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5224         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5225
5226         rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f80, 0x00, ERIAR_EXGMAC);
5227
5228         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
5229
5230         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5231         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5232
5233         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5234         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5235
5236         /* Adjust EEE LED frequency */
5237         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5238
5239         rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5240
5241         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
5242
5243         rtl_pcie_state_l2l3_enable(tp, false);
5244 }
5245
5246 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
5247 {
5248         static const struct ephy_info e_info_8168ep_1[] = {
5249                 { 0x00, 0xffff, 0x10ab },
5250                 { 0x06, 0xffff, 0xf030 },
5251                 { 0x08, 0xffff, 0x2006 },
5252                 { 0x0d, 0xffff, 0x1666 },
5253                 { 0x0c, 0x3ff0, 0x0000 }
5254         };
5255
5256         /* disable aspm and clock request before access ephy */
5257         rtl_hw_aspm_clkreq_enable(tp, false);
5258         rtl_ephy_init(tp, e_info_8168ep_1, ARRAY_SIZE(e_info_8168ep_1));
5259
5260         rtl_hw_start_8168ep(tp);
5261
5262         rtl_hw_aspm_clkreq_enable(tp, true);
5263 }
5264
5265 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
5266 {
5267         static const struct ephy_info e_info_8168ep_2[] = {
5268                 { 0x00, 0xffff, 0x10a3 },
5269                 { 0x19, 0xffff, 0xfc00 },
5270                 { 0x1e, 0xffff, 0x20ea }
5271         };
5272
5273         /* disable aspm and clock request before access ephy */
5274         rtl_hw_aspm_clkreq_enable(tp, false);
5275         rtl_ephy_init(tp, e_info_8168ep_2, ARRAY_SIZE(e_info_8168ep_2));
5276
5277         rtl_hw_start_8168ep(tp);
5278
5279         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5280         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5281
5282         rtl_hw_aspm_clkreq_enable(tp, true);
5283 }
5284
5285 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
5286 {
5287         u32 data;
5288         static const struct ephy_info e_info_8168ep_3[] = {
5289                 { 0x00, 0xffff, 0x10a3 },
5290                 { 0x19, 0xffff, 0x7c00 },
5291                 { 0x1e, 0xffff, 0x20eb },
5292                 { 0x0d, 0xffff, 0x1666 }
5293         };
5294
5295         /* disable aspm and clock request before access ephy */
5296         rtl_hw_aspm_clkreq_enable(tp, false);
5297         rtl_ephy_init(tp, e_info_8168ep_3, ARRAY_SIZE(e_info_8168ep_3));
5298
5299         rtl_hw_start_8168ep(tp);
5300
5301         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5302         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5303
5304         data = r8168_mac_ocp_read(tp, 0xd3e2);
5305         data &= 0xf000;
5306         data |= 0x0271;
5307         r8168_mac_ocp_write(tp, 0xd3e2, data);
5308
5309         data = r8168_mac_ocp_read(tp, 0xd3e4);
5310         data &= 0xff00;
5311         r8168_mac_ocp_write(tp, 0xd3e4, data);
5312
5313         data = r8168_mac_ocp_read(tp, 0xe860);
5314         data |= 0x0080;
5315         r8168_mac_ocp_write(tp, 0xe860, data);
5316
5317         rtl_hw_aspm_clkreq_enable(tp, true);
5318 }
5319
5320 static void rtl_hw_start_8168(struct rtl8169_private *tp)
5321 {
5322         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5323
5324         tp->cp_cmd &= ~INTT_MASK;
5325         tp->cp_cmd |= PktCntrDisable | INTT_1;
5326         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5327
5328         RTL_W16(tp, IntrMitigate, 0x5151);
5329
5330         /* Work around for RxFIFO overflow. */
5331         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
5332                 tp->irq_mask |= RxFIFOOver;
5333                 tp->irq_mask &= ~RxOverflow;
5334         }
5335
5336         switch (tp->mac_version) {
5337         case RTL_GIGA_MAC_VER_11:
5338                 rtl_hw_start_8168bb(tp);
5339                 break;
5340
5341         case RTL_GIGA_MAC_VER_12:
5342         case RTL_GIGA_MAC_VER_17:
5343                 rtl_hw_start_8168bef(tp);
5344                 break;
5345
5346         case RTL_GIGA_MAC_VER_18:
5347                 rtl_hw_start_8168cp_1(tp);
5348                 break;
5349
5350         case RTL_GIGA_MAC_VER_19:
5351                 rtl_hw_start_8168c_1(tp);
5352                 break;
5353
5354         case RTL_GIGA_MAC_VER_20:
5355                 rtl_hw_start_8168c_2(tp);
5356                 break;
5357
5358         case RTL_GIGA_MAC_VER_21:
5359                 rtl_hw_start_8168c_3(tp);
5360                 break;
5361
5362         case RTL_GIGA_MAC_VER_22:
5363                 rtl_hw_start_8168c_4(tp);
5364                 break;
5365
5366         case RTL_GIGA_MAC_VER_23:
5367                 rtl_hw_start_8168cp_2(tp);
5368                 break;
5369
5370         case RTL_GIGA_MAC_VER_24:
5371                 rtl_hw_start_8168cp_3(tp);
5372                 break;
5373
5374         case RTL_GIGA_MAC_VER_25:
5375         case RTL_GIGA_MAC_VER_26:
5376         case RTL_GIGA_MAC_VER_27:
5377                 rtl_hw_start_8168d(tp);
5378                 break;
5379
5380         case RTL_GIGA_MAC_VER_28:
5381                 rtl_hw_start_8168d_4(tp);
5382                 break;
5383
5384         case RTL_GIGA_MAC_VER_31:
5385                 rtl_hw_start_8168dp(tp);
5386                 break;
5387
5388         case RTL_GIGA_MAC_VER_32:
5389         case RTL_GIGA_MAC_VER_33:
5390                 rtl_hw_start_8168e_1(tp);
5391                 break;
5392         case RTL_GIGA_MAC_VER_34:
5393                 rtl_hw_start_8168e_2(tp);
5394                 break;
5395
5396         case RTL_GIGA_MAC_VER_35:
5397         case RTL_GIGA_MAC_VER_36:
5398                 rtl_hw_start_8168f_1(tp);
5399                 break;
5400
5401         case RTL_GIGA_MAC_VER_38:
5402                 rtl_hw_start_8411(tp);
5403                 break;
5404
5405         case RTL_GIGA_MAC_VER_40:
5406         case RTL_GIGA_MAC_VER_41:
5407                 rtl_hw_start_8168g_1(tp);
5408                 break;
5409         case RTL_GIGA_MAC_VER_42:
5410                 rtl_hw_start_8168g_2(tp);
5411                 break;
5412
5413         case RTL_GIGA_MAC_VER_44:
5414                 rtl_hw_start_8411_2(tp);
5415                 break;
5416
5417         case RTL_GIGA_MAC_VER_45:
5418         case RTL_GIGA_MAC_VER_46:
5419                 rtl_hw_start_8168h_1(tp);
5420                 break;
5421
5422         case RTL_GIGA_MAC_VER_49:
5423                 rtl_hw_start_8168ep_1(tp);
5424                 break;
5425
5426         case RTL_GIGA_MAC_VER_50:
5427                 rtl_hw_start_8168ep_2(tp);
5428                 break;
5429
5430         case RTL_GIGA_MAC_VER_51:
5431                 rtl_hw_start_8168ep_3(tp);
5432                 break;
5433
5434         default:
5435                 netif_err(tp, drv, tp->dev,
5436                           "unknown chipset (mac_version = %d)\n",
5437                           tp->mac_version);
5438                 break;
5439         }
5440 }
5441
5442 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
5443 {
5444         static const struct ephy_info e_info_8102e_1[] = {
5445                 { 0x01, 0, 0x6e65 },
5446                 { 0x02, 0, 0x091f },
5447                 { 0x03, 0, 0xc2f9 },
5448                 { 0x06, 0, 0xafb5 },
5449                 { 0x07, 0, 0x0e00 },
5450                 { 0x19, 0, 0xec80 },
5451                 { 0x01, 0, 0x2e65 },
5452                 { 0x01, 0, 0x6e65 }
5453         };
5454         u8 cfg1;
5455
5456         rtl_set_def_aspm_entry_latency(tp);
5457
5458         RTL_W8(tp, DBG_REG, FIX_NAK_1);
5459
5460         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5461
5462         RTL_W8(tp, Config1,
5463                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5464         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5465
5466         cfg1 = RTL_R8(tp, Config1);
5467         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5468                 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
5469
5470         rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
5471 }
5472
5473 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
5474 {
5475         rtl_set_def_aspm_entry_latency(tp);
5476
5477         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5478
5479         RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
5480         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5481 }
5482
5483 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
5484 {
5485         rtl_hw_start_8102e_2(tp);
5486
5487         rtl_ephy_write(tp, 0x03, 0xc2f9);
5488 }
5489
5490 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5491 {
5492         static const struct ephy_info e_info_8105e_1[] = {
5493                 { 0x07, 0, 0x4000 },
5494                 { 0x19, 0, 0x0200 },
5495                 { 0x19, 0, 0x0020 },
5496                 { 0x1e, 0, 0x2000 },
5497                 { 0x03, 0, 0x0001 },
5498                 { 0x19, 0, 0x0100 },
5499                 { 0x19, 0, 0x0004 },
5500                 { 0x0a, 0, 0x0020 }
5501         };
5502
5503         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5504         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5505
5506         /* Disable Early Tally Counter */
5507         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
5508
5509         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5510         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5511
5512         rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
5513
5514         rtl_pcie_state_l2l3_enable(tp, false);
5515 }
5516
5517 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5518 {
5519         rtl_hw_start_8105e_1(tp);
5520         rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5521 }
5522
5523 static void rtl_hw_start_8402(struct rtl8169_private *tp)
5524 {
5525         static const struct ephy_info e_info_8402[] = {
5526                 { 0x19, 0xffff, 0xff64 },
5527                 { 0x1e, 0, 0x4000 }
5528         };
5529
5530         rtl_set_def_aspm_entry_latency(tp);
5531
5532         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5533         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5534
5535         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5536
5537         rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
5538
5539         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5540
5541         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
5542         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
5543         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5544         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5545         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5546         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5547         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
5548
5549         rtl_pcie_state_l2l3_enable(tp, false);
5550 }
5551
5552 static void rtl_hw_start_8106(struct rtl8169_private *tp)
5553 {
5554         rtl_hw_aspm_clkreq_enable(tp, false);
5555
5556         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5557         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5558
5559         RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5560         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5561         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5562
5563         rtl_pcie_state_l2l3_enable(tp, false);
5564         rtl_hw_aspm_clkreq_enable(tp, true);
5565 }
5566
5567 static void rtl_hw_start_8101(struct rtl8169_private *tp)
5568 {
5569         if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
5570                 tp->irq_mask &= ~RxFIFOOver;
5571
5572         if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
5573             tp->mac_version == RTL_GIGA_MAC_VER_16)
5574                 pcie_capability_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
5575                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
5576
5577         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5578
5579         tp->cp_cmd &= CPCMD_QUIRK_MASK;
5580         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5581
5582         switch (tp->mac_version) {
5583         case RTL_GIGA_MAC_VER_07:
5584                 rtl_hw_start_8102e_1(tp);
5585                 break;
5586
5587         case RTL_GIGA_MAC_VER_08:
5588                 rtl_hw_start_8102e_3(tp);
5589                 break;
5590
5591         case RTL_GIGA_MAC_VER_09:
5592                 rtl_hw_start_8102e_2(tp);
5593                 break;
5594
5595         case RTL_GIGA_MAC_VER_29:
5596                 rtl_hw_start_8105e_1(tp);
5597                 break;
5598         case RTL_GIGA_MAC_VER_30:
5599                 rtl_hw_start_8105e_2(tp);
5600                 break;
5601
5602         case RTL_GIGA_MAC_VER_37:
5603                 rtl_hw_start_8402(tp);
5604                 break;
5605
5606         case RTL_GIGA_MAC_VER_39:
5607                 rtl_hw_start_8106(tp);
5608                 break;
5609         case RTL_GIGA_MAC_VER_43:
5610                 rtl_hw_start_8168g_2(tp);
5611                 break;
5612         case RTL_GIGA_MAC_VER_47:
5613         case RTL_GIGA_MAC_VER_48:
5614                 rtl_hw_start_8168h_1(tp);
5615                 break;
5616         }
5617
5618         RTL_W16(tp, IntrMitigate, 0x0000);
5619 }
5620
5621 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5622 {
5623         struct rtl8169_private *tp = netdev_priv(dev);
5624
5625         if (new_mtu > ETH_DATA_LEN)
5626                 rtl_hw_jumbo_enable(tp);
5627         else
5628                 rtl_hw_jumbo_disable(tp);
5629
5630         dev->mtu = new_mtu;
5631         netdev_update_features(dev);
5632
5633         return 0;
5634 }
5635
5636 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5637 {
5638         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
5639         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5640 }
5641
5642 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5643                                      void **data_buff, struct RxDesc *desc)
5644 {
5645         dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr),
5646                          R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
5647
5648         kfree(*data_buff);
5649         *data_buff = NULL;
5650         rtl8169_make_unusable_by_asic(desc);
5651 }
5652
5653 static inline void rtl8169_mark_to_asic(struct RxDesc *desc)
5654 {
5655         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5656
5657         /* Force memory writes to complete before releasing descriptor */
5658         dma_wmb();
5659
5660         desc->opts1 = cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE);
5661 }
5662
5663 static inline void *rtl8169_align(void *data)
5664 {
5665         return (void *)ALIGN((long)data, 16);
5666 }
5667
5668 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5669                                              struct RxDesc *desc)
5670 {
5671         void *data;
5672         dma_addr_t mapping;
5673         struct device *d = tp_to_dev(tp);
5674         int node = dev_to_node(d);
5675
5676         data = kmalloc_node(R8169_RX_BUF_SIZE, GFP_KERNEL, node);
5677         if (!data)
5678                 return NULL;
5679
5680         if (rtl8169_align(data) != data) {
5681                 kfree(data);
5682                 data = kmalloc_node(R8169_RX_BUF_SIZE + 15, GFP_KERNEL, node);
5683                 if (!data)
5684                         return NULL;
5685         }
5686
5687         mapping = dma_map_single(d, rtl8169_align(data), R8169_RX_BUF_SIZE,
5688                                  DMA_FROM_DEVICE);
5689         if (unlikely(dma_mapping_error(d, mapping))) {
5690                 if (net_ratelimit())
5691                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
5692                 goto err_out;
5693         }
5694
5695         desc->addr = cpu_to_le64(mapping);
5696         rtl8169_mark_to_asic(desc);
5697         return data;
5698
5699 err_out:
5700         kfree(data);
5701         return NULL;
5702 }
5703
5704 static void rtl8169_rx_clear(struct rtl8169_private *tp)
5705 {
5706         unsigned int i;
5707
5708         for (i = 0; i < NUM_RX_DESC; i++) {
5709                 if (tp->Rx_databuff[i]) {
5710                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
5711                                             tp->RxDescArray + i);
5712                 }
5713         }
5714 }
5715
5716 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
5717 {
5718         desc->opts1 |= cpu_to_le32(RingEnd);
5719 }
5720
5721 static int rtl8169_rx_fill(struct rtl8169_private *tp)
5722 {
5723         unsigned int i;
5724
5725         for (i = 0; i < NUM_RX_DESC; i++) {
5726                 void *data;
5727
5728                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
5729                 if (!data) {
5730                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
5731                         goto err_out;
5732                 }
5733                 tp->Rx_databuff[i] = data;
5734         }
5735
5736         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5737         return 0;
5738
5739 err_out:
5740         rtl8169_rx_clear(tp);
5741         return -ENOMEM;
5742 }
5743
5744 static int rtl8169_init_ring(struct rtl8169_private *tp)
5745 {
5746         rtl8169_init_ring_indexes(tp);
5747
5748         memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
5749         memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
5750
5751         return rtl8169_rx_fill(tp);
5752 }
5753
5754 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
5755                                  struct TxDesc *desc)
5756 {
5757         unsigned int len = tx_skb->len;
5758
5759         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5760
5761         desc->opts1 = 0x00;
5762         desc->opts2 = 0x00;
5763         desc->addr = 0x00;
5764         tx_skb->len = 0;
5765 }
5766
5767 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5768                                    unsigned int n)
5769 {
5770         unsigned int i;
5771
5772         for (i = 0; i < n; i++) {
5773                 unsigned int entry = (start + i) % NUM_TX_DESC;
5774                 struct ring_info *tx_skb = tp->tx_skb + entry;
5775                 unsigned int len = tx_skb->len;
5776
5777                 if (len) {
5778                         struct sk_buff *skb = tx_skb->skb;
5779
5780                         rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
5781                                              tp->TxDescArray + entry);
5782                         if (skb) {
5783                                 dev_consume_skb_any(skb);
5784                                 tx_skb->skb = NULL;
5785                         }
5786                 }
5787         }
5788 }
5789
5790 static void rtl8169_tx_clear(struct rtl8169_private *tp)
5791 {
5792         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
5793         tp->cur_tx = tp->dirty_tx = 0;
5794         netdev_reset_queue(tp->dev);
5795 }
5796
5797 static void rtl_reset_work(struct rtl8169_private *tp)
5798 {
5799         struct net_device *dev = tp->dev;
5800         int i;
5801
5802         napi_disable(&tp->napi);
5803         netif_stop_queue(dev);
5804         synchronize_rcu();
5805
5806         rtl8169_hw_reset(tp);
5807
5808         for (i = 0; i < NUM_RX_DESC; i++)
5809                 rtl8169_mark_to_asic(tp->RxDescArray + i);
5810
5811         rtl8169_tx_clear(tp);
5812         rtl8169_init_ring_indexes(tp);
5813
5814         napi_enable(&tp->napi);
5815         rtl_hw_start(tp);
5816         netif_wake_queue(dev);
5817 }
5818
5819 static void rtl8169_tx_timeout(struct net_device *dev)
5820 {
5821         struct rtl8169_private *tp = netdev_priv(dev);
5822
5823         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5824 }
5825
5826 static __le32 rtl8169_get_txd_opts1(u32 opts0, u32 len, unsigned int entry)
5827 {
5828         u32 status = opts0 | len;
5829
5830         if (entry == NUM_TX_DESC - 1)
5831                 status |= RingEnd;
5832
5833         return cpu_to_le32(status);
5834 }
5835
5836 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5837                               u32 *opts)
5838 {
5839         struct skb_shared_info *info = skb_shinfo(skb);
5840         unsigned int cur_frag, entry;
5841         struct TxDesc *uninitialized_var(txd);
5842         struct device *d = tp_to_dev(tp);
5843
5844         entry = tp->cur_tx;
5845         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5846                 const skb_frag_t *frag = info->frags + cur_frag;
5847                 dma_addr_t mapping;
5848                 u32 len;
5849                 void *addr;
5850
5851                 entry = (entry + 1) % NUM_TX_DESC;
5852
5853                 txd = tp->TxDescArray + entry;
5854                 len = skb_frag_size(frag);
5855                 addr = skb_frag_address(frag);
5856                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5857                 if (unlikely(dma_mapping_error(d, mapping))) {
5858                         if (net_ratelimit())
5859                                 netif_err(tp, drv, tp->dev,
5860                                           "Failed to map TX fragments DMA!\n");
5861                         goto err_out;
5862                 }
5863
5864                 txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry);
5865                 txd->opts2 = cpu_to_le32(opts[1]);
5866                 txd->addr = cpu_to_le64(mapping);
5867
5868                 tp->tx_skb[entry].len = len;
5869         }
5870
5871         if (cur_frag) {
5872                 tp->tx_skb[entry].skb = skb;
5873                 txd->opts1 |= cpu_to_le32(LastFrag);
5874         }
5875
5876         return cur_frag;
5877
5878 err_out:
5879         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5880         return -EIO;
5881 }
5882
5883 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
5884 {
5885         return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
5886 }
5887
5888 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5889                                       struct net_device *dev);
5890 /* r8169_csum_workaround()
5891  * The hw limites the value the transport offset. When the offset is out of the
5892  * range, calculate the checksum by sw.
5893  */
5894 static void r8169_csum_workaround(struct rtl8169_private *tp,
5895                                   struct sk_buff *skb)
5896 {
5897         if (skb_shinfo(skb)->gso_size) {
5898                 netdev_features_t features = tp->dev->features;
5899                 struct sk_buff *segs, *nskb;
5900
5901                 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
5902                 segs = skb_gso_segment(skb, features);
5903                 if (IS_ERR(segs) || !segs)
5904                         goto drop;
5905
5906                 do {
5907                         nskb = segs;
5908                         segs = segs->next;
5909                         nskb->next = NULL;
5910                         rtl8169_start_xmit(nskb, tp->dev);
5911                 } while (segs);
5912
5913                 dev_consume_skb_any(skb);
5914         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5915                 if (skb_checksum_help(skb) < 0)
5916                         goto drop;
5917
5918                 rtl8169_start_xmit(skb, tp->dev);
5919         } else {
5920                 struct net_device_stats *stats;
5921
5922 drop:
5923                 stats = &tp->dev->stats;
5924                 stats->tx_dropped++;
5925                 dev_kfree_skb_any(skb);
5926         }
5927 }
5928
5929 /* msdn_giant_send_check()
5930  * According to the document of microsoft, the TCP Pseudo Header excludes the
5931  * packet length for IPv6 TCP large packets.
5932  */
5933 static int msdn_giant_send_check(struct sk_buff *skb)
5934 {
5935         const struct ipv6hdr *ipv6h;
5936         struct tcphdr *th;
5937         int ret;
5938
5939         ret = skb_cow_head(skb, 0);
5940         if (ret)
5941                 return ret;
5942
5943         ipv6h = ipv6_hdr(skb);
5944         th = tcp_hdr(skb);
5945
5946         th->check = 0;
5947         th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
5948
5949         return ret;
5950 }
5951
5952 static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp,
5953                                 struct sk_buff *skb, u32 *opts)
5954 {
5955         u32 mss = skb_shinfo(skb)->gso_size;
5956
5957         if (mss) {
5958                 opts[0] |= TD_LSO;
5959                 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
5960         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5961                 const struct iphdr *ip = ip_hdr(skb);
5962
5963                 if (ip->protocol == IPPROTO_TCP)
5964                         opts[0] |= TD0_IP_CS | TD0_TCP_CS;
5965                 else if (ip->protocol == IPPROTO_UDP)
5966                         opts[0] |= TD0_IP_CS | TD0_UDP_CS;
5967                 else
5968                         WARN_ON_ONCE(1);
5969         }
5970
5971         return true;
5972 }
5973
5974 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
5975                                 struct sk_buff *skb, u32 *opts)
5976 {
5977         u32 transport_offset = (u32)skb_transport_offset(skb);
5978         u32 mss = skb_shinfo(skb)->gso_size;
5979
5980         if (mss) {
5981                 if (transport_offset > GTTCPHO_MAX) {
5982                         netif_warn(tp, tx_err, tp->dev,
5983                                    "Invalid transport offset 0x%x for TSO\n",
5984                                    transport_offset);
5985                         return false;
5986                 }
5987
5988                 switch (vlan_get_protocol(skb)) {
5989                 case htons(ETH_P_IP):
5990                         opts[0] |= TD1_GTSENV4;
5991                         break;
5992
5993                 case htons(ETH_P_IPV6):
5994                         if (msdn_giant_send_check(skb))
5995                                 return false;
5996
5997                         opts[0] |= TD1_GTSENV6;
5998                         break;
5999
6000                 default:
6001                         WARN_ON_ONCE(1);
6002                         break;
6003                 }
6004
6005                 opts[0] |= transport_offset << GTTCPHO_SHIFT;
6006                 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
6007         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6008                 u8 ip_protocol;
6009
6010                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
6011                         return !(skb_checksum_help(skb) || eth_skb_pad(skb));
6012
6013                 if (transport_offset > TCPHO_MAX) {
6014                         netif_warn(tp, tx_err, tp->dev,
6015                                    "Invalid transport offset 0x%x\n",
6016                                    transport_offset);
6017                         return false;
6018                 }
6019
6020                 switch (vlan_get_protocol(skb)) {
6021                 case htons(ETH_P_IP):
6022                         opts[1] |= TD1_IPv4_CS;
6023                         ip_protocol = ip_hdr(skb)->protocol;
6024                         break;
6025
6026                 case htons(ETH_P_IPV6):
6027                         opts[1] |= TD1_IPv6_CS;
6028                         ip_protocol = ipv6_hdr(skb)->nexthdr;
6029                         break;
6030
6031                 default:
6032                         ip_protocol = IPPROTO_RAW;
6033                         break;
6034                 }
6035
6036                 if (ip_protocol == IPPROTO_TCP)
6037                         opts[1] |= TD1_TCP_CS;
6038                 else if (ip_protocol == IPPROTO_UDP)
6039                         opts[1] |= TD1_UDP_CS;
6040                 else
6041                         WARN_ON_ONCE(1);
6042
6043                 opts[1] |= transport_offset << TCPHO_SHIFT;
6044         } else {
6045                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
6046                         return !eth_skb_pad(skb);
6047         }
6048
6049         return true;
6050 }
6051
6052 static bool rtl_tx_slots_avail(struct rtl8169_private *tp,
6053                                unsigned int nr_frags)
6054 {
6055         unsigned int slots_avail = tp->dirty_tx + NUM_TX_DESC - tp->cur_tx;
6056
6057         /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
6058         return slots_avail > nr_frags;
6059 }
6060
6061 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6062                                       struct net_device *dev)
6063 {
6064         struct rtl8169_private *tp = netdev_priv(dev);
6065         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
6066         struct TxDesc *txd = tp->TxDescArray + entry;
6067         struct device *d = tp_to_dev(tp);
6068         dma_addr_t mapping;
6069         u32 opts[2], len;
6070         bool stop_queue;
6071         int frags;
6072
6073         if (unlikely(!rtl_tx_slots_avail(tp, skb_shinfo(skb)->nr_frags))) {
6074                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
6075                 goto err_stop_0;
6076         }
6077
6078         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
6079                 goto err_stop_0;
6080
6081         opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
6082         opts[0] = DescOwn;
6083
6084         if (!tp->tso_csum(tp, skb, opts)) {
6085                 r8169_csum_workaround(tp, skb);
6086                 return NETDEV_TX_OK;
6087         }
6088
6089         len = skb_headlen(skb);
6090         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
6091         if (unlikely(dma_mapping_error(d, mapping))) {
6092                 if (net_ratelimit())
6093                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
6094                 goto err_dma_0;
6095         }
6096
6097         tp->tx_skb[entry].len = len;
6098         txd->addr = cpu_to_le64(mapping);
6099
6100         frags = rtl8169_xmit_frags(tp, skb, opts);
6101         if (frags < 0)
6102                 goto err_dma_1;
6103         else if (frags)
6104                 opts[0] |= FirstFrag;
6105         else {
6106                 opts[0] |= FirstFrag | LastFrag;
6107                 tp->tx_skb[entry].skb = skb;
6108         }
6109
6110         txd->opts2 = cpu_to_le32(opts[1]);
6111
6112         skb_tx_timestamp(skb);
6113
6114         /* Force memory writes to complete before releasing descriptor */
6115         dma_wmb();
6116
6117         txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry);
6118
6119         /* Force all memory writes to complete before notifying device */
6120         wmb();
6121
6122         tp->cur_tx += frags + 1;
6123
6124         stop_queue = !rtl_tx_slots_avail(tp, MAX_SKB_FRAGS);
6125         if (unlikely(stop_queue))
6126                 netif_stop_queue(dev);
6127
6128         if (__netdev_sent_queue(dev, skb->len, skb->xmit_more))
6129                 RTL_W8(tp, TxPoll, NPQ);
6130
6131         if (unlikely(stop_queue)) {
6132                 /* Sync with rtl_tx:
6133                  * - publish queue status and cur_tx ring index (write barrier)
6134                  * - refresh dirty_tx ring index (read barrier).
6135                  * May the current thread have a pessimistic view of the ring
6136                  * status and forget to wake up queue, a racing rtl_tx thread
6137                  * can't.
6138                  */
6139                 smp_mb();
6140                 if (rtl_tx_slots_avail(tp, MAX_SKB_FRAGS))
6141                         netif_wake_queue(dev);
6142         }
6143
6144         return NETDEV_TX_OK;
6145
6146 err_dma_1:
6147         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
6148 err_dma_0:
6149         dev_kfree_skb_any(skb);
6150         dev->stats.tx_dropped++;
6151         return NETDEV_TX_OK;
6152
6153 err_stop_0:
6154         netif_stop_queue(dev);
6155         dev->stats.tx_dropped++;
6156         return NETDEV_TX_BUSY;
6157 }
6158
6159 static void rtl8169_pcierr_interrupt(struct net_device *dev)
6160 {
6161         struct rtl8169_private *tp = netdev_priv(dev);
6162         struct pci_dev *pdev = tp->pci_dev;
6163         u16 pci_status, pci_cmd;
6164
6165         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
6166         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
6167
6168         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
6169                   pci_cmd, pci_status);
6170
6171         /*
6172          * The recovery sequence below admits a very elaborated explanation:
6173          * - it seems to work;
6174          * - I did not see what else could be done;
6175          * - it makes iop3xx happy.
6176          *
6177          * Feel free to adjust to your needs.
6178          */
6179         if (pdev->broken_parity_status)
6180                 pci_cmd &= ~PCI_COMMAND_PARITY;
6181         else
6182                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
6183
6184         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
6185
6186         pci_write_config_word(pdev, PCI_STATUS,
6187                 pci_status & (PCI_STATUS_DETECTED_PARITY |
6188                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
6189                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
6190
6191         /* The infamous DAC f*ckup only happens at boot time */
6192         if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
6193                 netif_info(tp, intr, dev, "disabling PCI DAC\n");
6194                 tp->cp_cmd &= ~PCIDAC;
6195                 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
6196                 dev->features &= ~NETIF_F_HIGHDMA;
6197         }
6198
6199         rtl8169_hw_reset(tp);
6200
6201         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6202 }
6203
6204 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp,
6205                    int budget)
6206 {
6207         unsigned int dirty_tx, tx_left, bytes_compl = 0, pkts_compl = 0;
6208
6209         dirty_tx = tp->dirty_tx;
6210         smp_rmb();
6211         tx_left = tp->cur_tx - dirty_tx;
6212
6213         while (tx_left > 0) {
6214                 unsigned int entry = dirty_tx % NUM_TX_DESC;
6215                 struct ring_info *tx_skb = tp->tx_skb + entry;
6216                 u32 status;
6217
6218                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
6219                 if (status & DescOwn)
6220                         break;
6221
6222                 /* This barrier is needed to keep us from reading
6223                  * any other fields out of the Tx descriptor until
6224                  * we know the status of DescOwn
6225                  */
6226                 dma_rmb();
6227
6228                 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
6229                                      tp->TxDescArray + entry);
6230                 if (status & LastFrag) {
6231                         pkts_compl++;
6232                         bytes_compl += tx_skb->skb->len;
6233                         napi_consume_skb(tx_skb->skb, budget);
6234                         tx_skb->skb = NULL;
6235                 }
6236                 dirty_tx++;
6237                 tx_left--;
6238         }
6239
6240         if (tp->dirty_tx != dirty_tx) {
6241                 netdev_completed_queue(dev, pkts_compl, bytes_compl);
6242
6243                 u64_stats_update_begin(&tp->tx_stats.syncp);
6244                 tp->tx_stats.packets += pkts_compl;
6245                 tp->tx_stats.bytes += bytes_compl;
6246                 u64_stats_update_end(&tp->tx_stats.syncp);
6247
6248                 tp->dirty_tx = dirty_tx;
6249                 /* Sync with rtl8169_start_xmit:
6250                  * - publish dirty_tx ring index (write barrier)
6251                  * - refresh cur_tx ring index and queue status (read barrier)
6252                  * May the current thread miss the stopped queue condition,
6253                  * a racing xmit thread can only have a right view of the
6254                  * ring status.
6255                  */
6256                 smp_mb();
6257                 if (netif_queue_stopped(dev) &&
6258                     rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) {
6259                         netif_wake_queue(dev);
6260                 }
6261                 /*
6262                  * 8168 hack: TxPoll requests are lost when the Tx packets are
6263                  * too close. Let's kick an extra TxPoll request when a burst
6264                  * of start_xmit activity is detected (if it is not detected,
6265                  * it is slow enough). -- FR
6266                  */
6267                 if (tp->cur_tx != dirty_tx)
6268                         RTL_W8(tp, TxPoll, NPQ);
6269         }
6270 }
6271
6272 static inline int rtl8169_fragmented_frame(u32 status)
6273 {
6274         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
6275 }
6276
6277 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
6278 {
6279         u32 status = opts1 & RxProtoMask;
6280
6281         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
6282             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
6283                 skb->ip_summed = CHECKSUM_UNNECESSARY;
6284         else
6285                 skb_checksum_none_assert(skb);
6286 }
6287
6288 static struct sk_buff *rtl8169_try_rx_copy(void *data,
6289                                            struct rtl8169_private *tp,
6290                                            int pkt_size,
6291                                            dma_addr_t addr)
6292 {
6293         struct sk_buff *skb;
6294         struct device *d = tp_to_dev(tp);
6295
6296         data = rtl8169_align(data);
6297         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6298         prefetch(data);
6299         skb = napi_alloc_skb(&tp->napi, pkt_size);
6300         if (skb)
6301                 skb_copy_to_linear_data(skb, data, pkt_size);
6302         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
6303
6304         return skb;
6305 }
6306
6307 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
6308 {
6309         unsigned int cur_rx, rx_left;
6310         unsigned int count;
6311
6312         cur_rx = tp->cur_rx;
6313
6314         for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
6315                 unsigned int entry = cur_rx % NUM_RX_DESC;
6316                 struct RxDesc *desc = tp->RxDescArray + entry;
6317                 u32 status;
6318
6319                 status = le32_to_cpu(desc->opts1);
6320                 if (status & DescOwn)
6321                         break;
6322
6323                 /* This barrier is needed to keep us from reading
6324                  * any other fields out of the Rx descriptor until
6325                  * we know the status of DescOwn
6326                  */
6327                 dma_rmb();
6328
6329                 if (unlikely(status & RxRES)) {
6330                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
6331                                    status);
6332                         dev->stats.rx_errors++;
6333                         if (status & (RxRWT | RxRUNT))
6334                                 dev->stats.rx_length_errors++;
6335                         if (status & RxCRC)
6336                                 dev->stats.rx_crc_errors++;
6337                         /* RxFOVF is a reserved bit on later chip versions */
6338                         if (tp->mac_version == RTL_GIGA_MAC_VER_01 &&
6339                             status & RxFOVF) {
6340                                 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6341                                 dev->stats.rx_fifo_errors++;
6342                         } else if (status & (RxRUNT | RxCRC) &&
6343                                    !(status & RxRWT) &&
6344                                    dev->features & NETIF_F_RXALL) {
6345                                 goto process_pkt;
6346                         }
6347                 } else {
6348                         struct sk_buff *skb;
6349                         dma_addr_t addr;
6350                         int pkt_size;
6351
6352 process_pkt:
6353                         addr = le64_to_cpu(desc->addr);
6354                         if (likely(!(dev->features & NETIF_F_RXFCS)))
6355                                 pkt_size = (status & 0x00003fff) - 4;
6356                         else
6357                                 pkt_size = status & 0x00003fff;
6358
6359                         /*
6360                          * The driver does not support incoming fragmented
6361                          * frames. They are seen as a symptom of over-mtu
6362                          * sized frames.
6363                          */
6364                         if (unlikely(rtl8169_fragmented_frame(status))) {
6365                                 dev->stats.rx_dropped++;
6366                                 dev->stats.rx_length_errors++;
6367                                 goto release_descriptor;
6368                         }
6369
6370                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
6371                                                   tp, pkt_size, addr);
6372                         if (!skb) {
6373                                 dev->stats.rx_dropped++;
6374                                 goto release_descriptor;
6375                         }
6376
6377                         rtl8169_rx_csum(skb, status);
6378                         skb_put(skb, pkt_size);
6379                         skb->protocol = eth_type_trans(skb, dev);
6380
6381                         rtl8169_rx_vlan_tag(desc, skb);
6382
6383                         if (skb->pkt_type == PACKET_MULTICAST)
6384                                 dev->stats.multicast++;
6385
6386                         napi_gro_receive(&tp->napi, skb);
6387
6388                         u64_stats_update_begin(&tp->rx_stats.syncp);
6389                         tp->rx_stats.packets++;
6390                         tp->rx_stats.bytes += pkt_size;
6391                         u64_stats_update_end(&tp->rx_stats.syncp);
6392                 }
6393 release_descriptor:
6394                 desc->opts2 = 0;
6395                 rtl8169_mark_to_asic(desc);
6396         }
6397
6398         count = cur_rx - tp->cur_rx;
6399         tp->cur_rx = cur_rx;
6400
6401         return count;
6402 }
6403
6404 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
6405 {
6406         struct rtl8169_private *tp = dev_instance;
6407         u16 status = rtl_get_events(tp);
6408         u16 irq_mask = RTL_R16(tp, IntrMask);
6409
6410         if (status == 0xffff || !(status & irq_mask))
6411                 return IRQ_NONE;
6412
6413         if (unlikely(status & SYSErr)) {
6414                 rtl8169_pcierr_interrupt(tp->dev);
6415                 goto out;
6416         }
6417
6418         if (status & LinkChg && tp->dev->phydev)
6419                 phy_mac_interrupt(tp->dev->phydev);
6420
6421         if (unlikely(status & RxFIFOOver &&
6422             tp->mac_version == RTL_GIGA_MAC_VER_11)) {
6423                 netif_stop_queue(tp->dev);
6424                 /* XXX - Hack alert. See rtl_task(). */
6425                 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
6426         }
6427
6428         if (status & RTL_EVENT_NAPI) {
6429                 rtl_irq_disable(tp);
6430                 napi_schedule_irqoff(&tp->napi);
6431         }
6432 out:
6433         rtl_ack_events(tp, status);
6434
6435         return IRQ_HANDLED;
6436 }
6437
6438 static void rtl_task(struct work_struct *work)
6439 {
6440         static const struct {
6441                 int bitnr;
6442                 void (*action)(struct rtl8169_private *);
6443         } rtl_work[] = {
6444                 { RTL_FLAG_TASK_RESET_PENDING,  rtl_reset_work },
6445         };
6446         struct rtl8169_private *tp =
6447                 container_of(work, struct rtl8169_private, wk.work);
6448         struct net_device *dev = tp->dev;
6449         int i;
6450
6451         rtl_lock_work(tp);
6452
6453         if (!netif_running(dev) ||
6454             !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
6455                 goto out_unlock;
6456
6457         for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
6458                 bool pending;
6459
6460                 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
6461                 if (pending)
6462                         rtl_work[i].action(tp);
6463         }
6464
6465 out_unlock:
6466         rtl_unlock_work(tp);
6467 }
6468
6469 static int rtl8169_poll(struct napi_struct *napi, int budget)
6470 {
6471         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
6472         struct net_device *dev = tp->dev;
6473         int work_done;
6474
6475         work_done = rtl_rx(dev, tp, (u32) budget);
6476
6477         rtl_tx(dev, tp, budget);
6478
6479         if (work_done < budget) {
6480                 napi_complete_done(napi, work_done);
6481                 rtl_irq_enable(tp);
6482         }
6483
6484         return work_done;
6485 }
6486
6487 static void rtl8169_rx_missed(struct net_device *dev)
6488 {
6489         struct rtl8169_private *tp = netdev_priv(dev);
6490
6491         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
6492                 return;
6493
6494         dev->stats.rx_missed_errors += RTL_R32(tp, RxMissed) & 0xffffff;
6495         RTL_W32(tp, RxMissed, 0);
6496 }
6497
6498 static void r8169_phylink_handler(struct net_device *ndev)
6499 {
6500         struct rtl8169_private *tp = netdev_priv(ndev);
6501
6502         if (netif_carrier_ok(ndev)) {
6503                 rtl_link_chg_patch(tp);
6504                 pm_request_resume(&tp->pci_dev->dev);
6505         } else {
6506                 pm_runtime_idle(&tp->pci_dev->dev);
6507         }
6508
6509         if (net_ratelimit())
6510                 phy_print_status(ndev->phydev);
6511 }
6512
6513 static int r8169_phy_connect(struct rtl8169_private *tp)
6514 {
6515         struct phy_device *phydev = mdiobus_get_phy(tp->mii_bus, 0);
6516         phy_interface_t phy_mode;
6517         int ret;
6518
6519         phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
6520                    PHY_INTERFACE_MODE_MII;
6521
6522         ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
6523                                  phy_mode);
6524         if (ret)
6525                 return ret;
6526
6527         if (!tp->supports_gmii)
6528                 phy_set_max_speed(phydev, SPEED_100);
6529
6530         /* Ensure to advertise everything, incl. pause */
6531         linkmode_copy(phydev->advertising, phydev->supported);
6532
6533         phy_attached_info(phydev);
6534
6535         return 0;
6536 }
6537
6538 static void rtl8169_down(struct net_device *dev)
6539 {
6540         struct rtl8169_private *tp = netdev_priv(dev);
6541
6542         phy_stop(dev->phydev);
6543
6544         napi_disable(&tp->napi);
6545         netif_stop_queue(dev);
6546
6547         rtl8169_hw_reset(tp);
6548         /*
6549          * At this point device interrupts can not be enabled in any function,
6550          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6551          * and napi is disabled (rtl8169_poll).
6552          */
6553         rtl8169_rx_missed(dev);
6554
6555         /* Give a racing hard_start_xmit a few cycles to complete. */
6556         synchronize_rcu();
6557
6558         rtl8169_tx_clear(tp);
6559
6560         rtl8169_rx_clear(tp);
6561
6562         rtl_pll_power_down(tp);
6563 }
6564
6565 static int rtl8169_close(struct net_device *dev)
6566 {
6567         struct rtl8169_private *tp = netdev_priv(dev);
6568         struct pci_dev *pdev = tp->pci_dev;
6569
6570         pm_runtime_get_sync(&pdev->dev);
6571
6572         /* Update counters before going down */
6573         rtl8169_update_counters(tp);
6574
6575         rtl_lock_work(tp);
6576         /* Clear all task flags */
6577         bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6578
6579         rtl8169_down(dev);
6580         rtl_unlock_work(tp);
6581
6582         cancel_work_sync(&tp->wk.work);
6583
6584         phy_disconnect(dev->phydev);
6585
6586         pci_free_irq(pdev, 0, tp);
6587
6588         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6589                           tp->RxPhyAddr);
6590         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6591                           tp->TxPhyAddr);
6592         tp->TxDescArray = NULL;
6593         tp->RxDescArray = NULL;
6594
6595         pm_runtime_put_sync(&pdev->dev);
6596
6597         return 0;
6598 }
6599
6600 #ifdef CONFIG_NET_POLL_CONTROLLER
6601 static void rtl8169_netpoll(struct net_device *dev)
6602 {
6603         struct rtl8169_private *tp = netdev_priv(dev);
6604
6605         rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp);
6606 }
6607 #endif
6608
6609 static int rtl_open(struct net_device *dev)
6610 {
6611         struct rtl8169_private *tp = netdev_priv(dev);
6612         struct pci_dev *pdev = tp->pci_dev;
6613         int retval = -ENOMEM;
6614
6615         pm_runtime_get_sync(&pdev->dev);
6616
6617         /*
6618          * Rx and Tx descriptors needs 256 bytes alignment.
6619          * dma_alloc_coherent provides more.
6620          */
6621         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6622                                              &tp->TxPhyAddr, GFP_KERNEL);
6623         if (!tp->TxDescArray)
6624                 goto err_pm_runtime_put;
6625
6626         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6627                                              &tp->RxPhyAddr, GFP_KERNEL);
6628         if (!tp->RxDescArray)
6629                 goto err_free_tx_0;
6630
6631         retval = rtl8169_init_ring(tp);
6632         if (retval < 0)
6633                 goto err_free_rx_1;
6634
6635         INIT_WORK(&tp->wk.work, rtl_task);
6636
6637         smp_mb();
6638
6639         rtl_request_firmware(tp);
6640
6641         retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, tp,
6642                                  dev->name);
6643         if (retval < 0)
6644                 goto err_release_fw_2;
6645
6646         retval = r8169_phy_connect(tp);
6647         if (retval)
6648                 goto err_free_irq;
6649
6650         rtl_lock_work(tp);
6651
6652         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6653
6654         napi_enable(&tp->napi);
6655
6656         rtl8169_init_phy(dev, tp);
6657
6658         rtl_pll_power_up(tp);
6659
6660         rtl_hw_start(tp);
6661
6662         if (!rtl8169_init_counter_offsets(tp))
6663                 netif_warn(tp, hw, dev, "counter reset/update failed\n");
6664
6665         phy_start(dev->phydev);
6666         netif_start_queue(dev);
6667
6668         rtl_unlock_work(tp);
6669
6670         pm_runtime_put_sync(&pdev->dev);
6671 out:
6672         return retval;
6673
6674 err_free_irq:
6675         pci_free_irq(pdev, 0, tp);
6676 err_release_fw_2:
6677         rtl_release_firmware(tp);
6678         rtl8169_rx_clear(tp);
6679 err_free_rx_1:
6680         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6681                           tp->RxPhyAddr);
6682         tp->RxDescArray = NULL;
6683 err_free_tx_0:
6684         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6685                           tp->TxPhyAddr);
6686         tp->TxDescArray = NULL;
6687 err_pm_runtime_put:
6688         pm_runtime_put_noidle(&pdev->dev);
6689         goto out;
6690 }
6691
6692 static void
6693 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
6694 {
6695         struct rtl8169_private *tp = netdev_priv(dev);
6696         struct pci_dev *pdev = tp->pci_dev;
6697         struct rtl8169_counters *counters = tp->counters;
6698         unsigned int start;
6699
6700         pm_runtime_get_noresume(&pdev->dev);
6701
6702         if (netif_running(dev) && pm_runtime_active(&pdev->dev))
6703                 rtl8169_rx_missed(dev);
6704
6705         do {
6706                 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
6707                 stats->rx_packets = tp->rx_stats.packets;
6708                 stats->rx_bytes = tp->rx_stats.bytes;
6709         } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
6710
6711         do {
6712                 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
6713                 stats->tx_packets = tp->tx_stats.packets;
6714                 stats->tx_bytes = tp->tx_stats.bytes;
6715         } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
6716
6717         stats->rx_dropped       = dev->stats.rx_dropped;
6718         stats->tx_dropped       = dev->stats.tx_dropped;
6719         stats->rx_length_errors = dev->stats.rx_length_errors;
6720         stats->rx_errors        = dev->stats.rx_errors;
6721         stats->rx_crc_errors    = dev->stats.rx_crc_errors;
6722         stats->rx_fifo_errors   = dev->stats.rx_fifo_errors;
6723         stats->rx_missed_errors = dev->stats.rx_missed_errors;
6724         stats->multicast        = dev->stats.multicast;
6725
6726         /*
6727          * Fetch additonal counter values missing in stats collected by driver
6728          * from tally counters.
6729          */
6730         if (pm_runtime_active(&pdev->dev))
6731                 rtl8169_update_counters(tp);
6732
6733         /*
6734          * Subtract values fetched during initalization.
6735          * See rtl8169_init_counter_offsets for a description why we do that.
6736          */
6737         stats->tx_errors = le64_to_cpu(counters->tx_errors) -
6738                 le64_to_cpu(tp->tc_offset.tx_errors);
6739         stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
6740                 le32_to_cpu(tp->tc_offset.tx_multi_collision);
6741         stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
6742                 le16_to_cpu(tp->tc_offset.tx_aborted);
6743
6744         pm_runtime_put_noidle(&pdev->dev);
6745 }
6746
6747 static void rtl8169_net_suspend(struct net_device *dev)
6748 {
6749         struct rtl8169_private *tp = netdev_priv(dev);
6750
6751         if (!netif_running(dev))
6752                 return;
6753
6754         phy_stop(dev->phydev);
6755         netif_device_detach(dev);
6756
6757         rtl_lock_work(tp);
6758         napi_disable(&tp->napi);
6759         /* Clear all task flags */
6760         bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6761
6762         rtl_unlock_work(tp);
6763
6764         rtl_pll_power_down(tp);
6765 }
6766
6767 #ifdef CONFIG_PM
6768
6769 static int rtl8169_suspend(struct device *device)
6770 {
6771         struct net_device *dev = dev_get_drvdata(device);
6772         struct rtl8169_private *tp = netdev_priv(dev);
6773
6774         rtl8169_net_suspend(dev);
6775         clk_disable_unprepare(tp->clk);
6776
6777         return 0;
6778 }
6779
6780 static void __rtl8169_resume(struct net_device *dev)
6781 {
6782         struct rtl8169_private *tp = netdev_priv(dev);
6783
6784         netif_device_attach(dev);
6785
6786         rtl_pll_power_up(tp);
6787         rtl8169_init_phy(dev, tp);
6788
6789         phy_start(tp->dev->phydev);
6790
6791         rtl_lock_work(tp);
6792         napi_enable(&tp->napi);
6793         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6794         rtl_unlock_work(tp);
6795
6796         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6797 }
6798
6799 static int rtl8169_resume(struct device *device)
6800 {
6801         struct net_device *dev = dev_get_drvdata(device);
6802         struct rtl8169_private *tp = netdev_priv(dev);
6803
6804         clk_prepare_enable(tp->clk);
6805
6806         if (netif_running(dev))
6807                 __rtl8169_resume(dev);
6808
6809         return 0;
6810 }
6811
6812 static int rtl8169_runtime_suspend(struct device *device)
6813 {
6814         struct net_device *dev = dev_get_drvdata(device);
6815         struct rtl8169_private *tp = netdev_priv(dev);
6816
6817         if (!tp->TxDescArray)
6818                 return 0;
6819
6820         rtl_lock_work(tp);
6821         __rtl8169_set_wol(tp, WAKE_ANY);
6822         rtl_unlock_work(tp);
6823
6824         rtl8169_net_suspend(dev);
6825
6826         /* Update counters before going runtime suspend */
6827         rtl8169_rx_missed(dev);
6828         rtl8169_update_counters(tp);
6829
6830         return 0;
6831 }
6832
6833 static int rtl8169_runtime_resume(struct device *device)
6834 {
6835         struct net_device *dev = dev_get_drvdata(device);
6836         struct rtl8169_private *tp = netdev_priv(dev);
6837         rtl_rar_set(tp, dev->dev_addr);
6838
6839         if (!tp->TxDescArray)
6840                 return 0;
6841
6842         rtl_lock_work(tp);
6843         __rtl8169_set_wol(tp, tp->saved_wolopts);
6844         rtl_unlock_work(tp);
6845
6846         __rtl8169_resume(dev);
6847
6848         return 0;
6849 }
6850
6851 static int rtl8169_runtime_idle(struct device *device)
6852 {
6853         struct net_device *dev = dev_get_drvdata(device);
6854
6855         if (!netif_running(dev) || !netif_carrier_ok(dev))
6856                 pm_schedule_suspend(device, 10000);
6857
6858         return -EBUSY;
6859 }
6860
6861 static const struct dev_pm_ops rtl8169_pm_ops = {
6862         .suspend                = rtl8169_suspend,
6863         .resume                 = rtl8169_resume,
6864         .freeze                 = rtl8169_suspend,
6865         .thaw                   = rtl8169_resume,
6866         .poweroff               = rtl8169_suspend,
6867         .restore                = rtl8169_resume,
6868         .runtime_suspend        = rtl8169_runtime_suspend,
6869         .runtime_resume         = rtl8169_runtime_resume,
6870         .runtime_idle           = rtl8169_runtime_idle,
6871 };
6872
6873 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
6874
6875 #else /* !CONFIG_PM */
6876
6877 #define RTL8169_PM_OPS  NULL
6878
6879 #endif /* !CONFIG_PM */
6880
6881 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6882 {
6883         /* WoL fails with 8168b when the receiver is disabled. */
6884         switch (tp->mac_version) {
6885         case RTL_GIGA_MAC_VER_11:
6886         case RTL_GIGA_MAC_VER_12:
6887         case RTL_GIGA_MAC_VER_17:
6888                 pci_clear_master(tp->pci_dev);
6889
6890                 RTL_W8(tp, ChipCmd, CmdRxEnb);
6891                 /* PCI commit */
6892                 RTL_R8(tp, ChipCmd);
6893                 break;
6894         default:
6895                 break;
6896         }
6897 }
6898
6899 static void rtl_shutdown(struct pci_dev *pdev)
6900 {
6901         struct net_device *dev = pci_get_drvdata(pdev);
6902         struct rtl8169_private *tp = netdev_priv(dev);
6903
6904         rtl8169_net_suspend(dev);
6905
6906         /* Restore original MAC address */
6907         rtl_rar_set(tp, dev->perm_addr);
6908
6909         rtl8169_hw_reset(tp);
6910
6911         if (system_state == SYSTEM_POWER_OFF) {
6912                 if (tp->saved_wolopts) {
6913                         rtl_wol_suspend_quirk(tp);
6914                         rtl_wol_shutdown_quirk(tp);
6915                 }
6916
6917                 pci_wake_from_d3(pdev, true);
6918                 pci_set_power_state(pdev, PCI_D3hot);
6919         }
6920 }
6921
6922 static void rtl_remove_one(struct pci_dev *pdev)
6923 {
6924         struct net_device *dev = pci_get_drvdata(pdev);
6925         struct rtl8169_private *tp = netdev_priv(dev);
6926
6927         if (r8168_check_dash(tp))
6928                 rtl8168_driver_stop(tp);
6929
6930         netif_napi_del(&tp->napi);
6931
6932         unregister_netdev(dev);
6933         mdiobus_unregister(tp->mii_bus);
6934
6935         rtl_release_firmware(tp);
6936
6937         if (pci_dev_run_wake(pdev))
6938                 pm_runtime_get_noresume(&pdev->dev);
6939
6940         /* restore original MAC address */
6941         rtl_rar_set(tp, dev->perm_addr);
6942 }
6943
6944 static const struct net_device_ops rtl_netdev_ops = {
6945         .ndo_open               = rtl_open,
6946         .ndo_stop               = rtl8169_close,
6947         .ndo_get_stats64        = rtl8169_get_stats64,
6948         .ndo_start_xmit         = rtl8169_start_xmit,
6949         .ndo_tx_timeout         = rtl8169_tx_timeout,
6950         .ndo_validate_addr      = eth_validate_addr,
6951         .ndo_change_mtu         = rtl8169_change_mtu,
6952         .ndo_fix_features       = rtl8169_fix_features,
6953         .ndo_set_features       = rtl8169_set_features,
6954         .ndo_set_mac_address    = rtl_set_mac_address,
6955         .ndo_do_ioctl           = rtl8169_ioctl,
6956         .ndo_set_rx_mode        = rtl_set_rx_mode,
6957 #ifdef CONFIG_NET_POLL_CONTROLLER
6958         .ndo_poll_controller    = rtl8169_netpoll,
6959 #endif
6960
6961 };
6962
6963 static const struct rtl_cfg_info {
6964         void (*hw_start)(struct rtl8169_private *tp);
6965         u16 irq_mask;
6966         unsigned int has_gmii:1;
6967         const struct rtl_coalesce_info *coalesce_info;
6968 } rtl_cfg_infos [] = {
6969         [RTL_CFG_0] = {
6970                 .hw_start       = rtl_hw_start_8169,
6971                 .irq_mask       = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
6972                 .has_gmii       = 1,
6973                 .coalesce_info  = rtl_coalesce_info_8169,
6974         },
6975         [RTL_CFG_1] = {
6976                 .hw_start       = rtl_hw_start_8168,
6977                 .irq_mask       = LinkChg | RxOverflow,
6978                 .has_gmii       = 1,
6979                 .coalesce_info  = rtl_coalesce_info_8168_8136,
6980         },
6981         [RTL_CFG_2] = {
6982                 .hw_start       = rtl_hw_start_8101,
6983                 .irq_mask       = LinkChg | RxOverflow | RxFIFOOver,
6984                 .coalesce_info  = rtl_coalesce_info_8168_8136,
6985         }
6986 };
6987
6988 static int rtl_alloc_irq(struct rtl8169_private *tp)
6989 {
6990         unsigned int flags;
6991
6992         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
6993                 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
6994                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
6995                 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
6996                 flags = PCI_IRQ_LEGACY;
6997         } else {
6998                 flags = PCI_IRQ_ALL_TYPES;
6999         }
7000
7001         return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
7002 }
7003
7004 DECLARE_RTL_COND(rtl_link_list_ready_cond)
7005 {
7006         return RTL_R8(tp, MCU) & LINK_LIST_RDY;
7007 }
7008
7009 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
7010 {
7011         return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
7012 }
7013
7014 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
7015 {
7016         struct rtl8169_private *tp = mii_bus->priv;
7017
7018         if (phyaddr > 0)
7019                 return -ENODEV;
7020
7021         return rtl_readphy(tp, phyreg);
7022 }
7023
7024 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
7025                                 int phyreg, u16 val)
7026 {
7027         struct rtl8169_private *tp = mii_bus->priv;
7028
7029         if (phyaddr > 0)
7030                 return -ENODEV;
7031
7032         rtl_writephy(tp, phyreg, val);
7033
7034         return 0;
7035 }
7036
7037 static int r8169_mdio_register(struct rtl8169_private *tp)
7038 {
7039         struct pci_dev *pdev = tp->pci_dev;
7040         struct phy_device *phydev;
7041         struct mii_bus *new_bus;
7042         int ret;
7043
7044         new_bus = devm_mdiobus_alloc(&pdev->dev);
7045         if (!new_bus)
7046                 return -ENOMEM;
7047
7048         new_bus->name = "r8169";
7049         new_bus->priv = tp;
7050         new_bus->parent = &pdev->dev;
7051         new_bus->irq[0] = PHY_IGNORE_INTERRUPT;
7052         snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x",
7053                  PCI_DEVID(pdev->bus->number, pdev->devfn));
7054
7055         new_bus->read = r8169_mdio_read_reg;
7056         new_bus->write = r8169_mdio_write_reg;
7057
7058         ret = mdiobus_register(new_bus);
7059         if (ret)
7060                 return ret;
7061
7062         phydev = mdiobus_get_phy(new_bus, 0);
7063         if (!phydev) {
7064                 mdiobus_unregister(new_bus);
7065                 return -ENODEV;
7066         }
7067
7068         /* PHY will be woken up in rtl_open() */
7069         phy_suspend(phydev);
7070
7071         tp->mii_bus = new_bus;
7072
7073         return 0;
7074 }
7075
7076 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
7077 {
7078         u32 data;
7079
7080         tp->ocp_base = OCP_STD_PHY_BASE;
7081
7082         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
7083
7084         if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
7085                 return;
7086
7087         if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
7088                 return;
7089
7090         RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
7091         msleep(1);
7092         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
7093
7094         data = r8168_mac_ocp_read(tp, 0xe8de);
7095         data &= ~(1 << 14);
7096         r8168_mac_ocp_write(tp, 0xe8de, data);
7097
7098         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7099                 return;
7100
7101         data = r8168_mac_ocp_read(tp, 0xe8de);
7102         data |= (1 << 15);
7103         r8168_mac_ocp_write(tp, 0xe8de, data);
7104
7105         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7106                 return;
7107 }
7108
7109 static void rtl_hw_init_8168ep(struct rtl8169_private *tp)
7110 {
7111         rtl8168ep_stop_cmac(tp);
7112         rtl_hw_init_8168g(tp);
7113 }
7114
7115 static void rtl_hw_initialize(struct rtl8169_private *tp)
7116 {
7117         switch (tp->mac_version) {
7118         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
7119                 rtl_hw_init_8168g(tp);
7120                 break;
7121         case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_51:
7122                 rtl_hw_init_8168ep(tp);
7123                 break;
7124         default:
7125                 break;
7126         }
7127 }
7128
7129 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */
7130 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
7131 {
7132         switch (tp->mac_version) {
7133         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
7134         case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
7135                 return false;
7136         default:
7137                 return true;
7138         }
7139 }
7140
7141 static int rtl_jumbo_max(struct rtl8169_private *tp)
7142 {
7143         /* Non-GBit versions don't support jumbo frames */
7144         if (!tp->supports_gmii)
7145                 return JUMBO_1K;
7146
7147         switch (tp->mac_version) {
7148         /* RTL8169 */
7149         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
7150                 return JUMBO_7K;
7151         /* RTL8168b */
7152         case RTL_GIGA_MAC_VER_11:
7153         case RTL_GIGA_MAC_VER_12:
7154         case RTL_GIGA_MAC_VER_17:
7155                 return JUMBO_4K;
7156         /* RTL8168c */
7157         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
7158                 return JUMBO_6K;
7159         default:
7160                 return JUMBO_9K;
7161         }
7162 }
7163
7164 static void rtl_disable_clk(void *data)
7165 {
7166         clk_disable_unprepare(data);
7167 }
7168
7169 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7170 {
7171         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
7172         struct rtl8169_private *tp;
7173         struct net_device *dev;
7174         int chipset, region, i;
7175         int jumbo_max, rc;
7176
7177         dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
7178         if (!dev)
7179                 return -ENOMEM;
7180
7181         SET_NETDEV_DEV(dev, &pdev->dev);
7182         dev->netdev_ops = &rtl_netdev_ops;
7183         tp = netdev_priv(dev);
7184         tp->dev = dev;
7185         tp->pci_dev = pdev;
7186         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
7187         tp->supports_gmii = cfg->has_gmii;
7188
7189         /* Get the *optional* external "ether_clk" used on some boards */
7190         tp->clk = devm_clk_get(&pdev->dev, "ether_clk");
7191         if (IS_ERR(tp->clk)) {
7192                 rc = PTR_ERR(tp->clk);
7193                 if (rc == -ENOENT) {
7194                         /* clk-core allows NULL (for suspend / resume) */
7195                         tp->clk = NULL;
7196                 } else if (rc == -EPROBE_DEFER) {
7197                         return rc;
7198                 } else {
7199                         dev_err(&pdev->dev, "failed to get clk: %d\n", rc);
7200                         return rc;
7201                 }
7202         } else {
7203                 rc = clk_prepare_enable(tp->clk);
7204                 if (rc) {
7205                         dev_err(&pdev->dev, "failed to enable clk: %d\n", rc);
7206                         return rc;
7207                 }
7208
7209                 rc = devm_add_action_or_reset(&pdev->dev, rtl_disable_clk,
7210                                               tp->clk);
7211                 if (rc)
7212                         return rc;
7213         }
7214
7215         /* enable device (incl. PCI PM wakeup and hotplug setup) */
7216         rc = pcim_enable_device(pdev);
7217         if (rc < 0) {
7218                 dev_err(&pdev->dev, "enable failure\n");
7219                 return rc;
7220         }
7221
7222         if (pcim_set_mwi(pdev) < 0)
7223                 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
7224
7225         /* use first MMIO region */
7226         region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
7227         if (region < 0) {
7228                 dev_err(&pdev->dev, "no MMIO resource found\n");
7229                 return -ENODEV;
7230         }
7231
7232         /* check for weird/broken PCI region reporting */
7233         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
7234                 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
7235                 return -ENODEV;
7236         }
7237
7238         rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME);
7239         if (rc < 0) {
7240                 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
7241                 return rc;
7242         }
7243
7244         tp->mmio_addr = pcim_iomap_table(pdev)[region];
7245
7246         /* Identify chip attached to board */
7247         rtl8169_get_mac_version(tp);
7248         if (tp->mac_version == RTL_GIGA_MAC_NONE)
7249                 return -ENODEV;
7250
7251         if (rtl_tbi_enabled(tp)) {
7252                 dev_err(&pdev->dev, "TBI fiber mode not supported\n");
7253                 return -ENODEV;
7254         }
7255
7256         tp->cp_cmd = RTL_R16(tp, CPlusCmd);
7257
7258         if (sizeof(dma_addr_t) > 4 && (use_dac == 1 || (use_dac == -1 &&
7259             tp->mac_version >= RTL_GIGA_MAC_VER_18)) &&
7260             !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
7261
7262                 /* CPlusCmd Dual Access Cycle is only needed for non-PCIe */
7263                 if (!pci_is_pcie(pdev))
7264                         tp->cp_cmd |= PCIDAC;
7265                 dev->features |= NETIF_F_HIGHDMA;
7266         } else {
7267                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
7268                 if (rc < 0) {
7269                         dev_err(&pdev->dev, "DMA configuration failed\n");
7270                         return rc;
7271                 }
7272         }
7273
7274         rtl_init_rxcfg(tp);
7275
7276         rtl8169_irq_mask_and_ack(tp);
7277
7278         rtl_hw_initialize(tp);
7279
7280         rtl_hw_reset(tp);
7281
7282         pci_set_master(pdev);
7283
7284         rtl_init_mdio_ops(tp);
7285         rtl_init_jumbo_ops(tp);
7286
7287         chipset = tp->mac_version;
7288
7289         rc = rtl_alloc_irq(tp);
7290         if (rc < 0) {
7291                 dev_err(&pdev->dev, "Can't allocate interrupt\n");
7292                 return rc;
7293         }
7294
7295         tp->saved_wolopts = __rtl8169_get_wol(tp);
7296
7297         mutex_init(&tp->wk.mutex);
7298         u64_stats_init(&tp->rx_stats.syncp);
7299         u64_stats_init(&tp->tx_stats.syncp);
7300
7301         /* Get MAC address */
7302         switch (tp->mac_version) {
7303                 u8 mac_addr[ETH_ALEN] __aligned(4);
7304         case RTL_GIGA_MAC_VER_35 ... RTL_GIGA_MAC_VER_38:
7305         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
7306                 *(u32 *)&mac_addr[0] = rtl_eri_read(tp, 0xe0, ERIAR_EXGMAC);
7307                 *(u16 *)&mac_addr[4] = rtl_eri_read(tp, 0xe4, ERIAR_EXGMAC);
7308
7309                 if (is_valid_ether_addr(mac_addr))
7310                         rtl_rar_set(tp, mac_addr);
7311                 break;
7312         default:
7313                 break;
7314         }
7315         for (i = 0; i < ETH_ALEN; i++)
7316                 dev->dev_addr[i] = RTL_R8(tp, MAC0 + i);
7317
7318         dev->ethtool_ops = &rtl8169_ethtool_ops;
7319
7320         netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT);
7321
7322         /* don't enable SG, IP_CSUM and TSO by default - it might not work
7323          * properly for all devices */
7324         dev->features |= NETIF_F_RXCSUM |
7325                 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
7326
7327         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7328                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
7329                 NETIF_F_HW_VLAN_CTAG_RX;
7330         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7331                 NETIF_F_HIGHDMA;
7332         dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
7333
7334         tp->cp_cmd |= RxChkSum | RxVlan;
7335
7336         /*
7337          * Pretend we are using VLANs; This bypasses a nasty bug where
7338          * Interrupts stop flowing on high load on 8110SCd controllers.
7339          */
7340         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
7341                 /* Disallow toggling */
7342                 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
7343
7344         if (rtl_chip_supports_csum_v2(tp)) {
7345                 tp->tso_csum = rtl8169_tso_csum_v2;
7346                 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
7347         } else {
7348                 tp->tso_csum = rtl8169_tso_csum_v1;
7349         }
7350
7351         dev->hw_features |= NETIF_F_RXALL;
7352         dev->hw_features |= NETIF_F_RXFCS;
7353
7354         /* MTU range: 60 - hw-specific max */
7355         dev->min_mtu = ETH_ZLEN;
7356         jumbo_max = rtl_jumbo_max(tp);
7357         dev->max_mtu = jumbo_max;
7358
7359         tp->hw_start = cfg->hw_start;
7360         tp->irq_mask = RTL_EVENT_NAPI | cfg->irq_mask;
7361         tp->coalesce_info = cfg->coalesce_info;
7362
7363         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
7364
7365         tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
7366                                             &tp->counters_phys_addr,
7367                                             GFP_KERNEL);
7368         if (!tp->counters)
7369                 return -ENOMEM;
7370
7371         pci_set_drvdata(pdev, dev);
7372
7373         rc = r8169_mdio_register(tp);
7374         if (rc)
7375                 return rc;
7376
7377         /* chip gets powered up in rtl_open() */
7378         rtl_pll_power_down(tp);
7379
7380         rc = register_netdev(dev);
7381         if (rc)
7382                 goto err_mdio_unregister;
7383
7384         netif_info(tp, probe, dev, "%s, %pM, XID %03x, IRQ %d\n",
7385                    rtl_chip_infos[chipset].name, dev->dev_addr,
7386                    (RTL_R32(tp, TxConfig) >> 20) & 0xfcf,
7387                    pci_irq_vector(pdev, 0));
7388
7389         if (jumbo_max > JUMBO_1K)
7390                 netif_info(tp, probe, dev,
7391                            "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
7392                            jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?
7393                            "ok" : "ko");
7394
7395         if (r8168_check_dash(tp))
7396                 rtl8168_driver_start(tp);
7397
7398         if (pci_dev_run_wake(pdev))
7399                 pm_runtime_put_sync(&pdev->dev);
7400
7401         return 0;
7402
7403 err_mdio_unregister:
7404         mdiobus_unregister(tp->mii_bus);
7405         return rc;
7406 }
7407
7408 static struct pci_driver rtl8169_pci_driver = {
7409         .name           = MODULENAME,
7410         .id_table       = rtl8169_pci_tbl,
7411         .probe          = rtl_init_one,
7412         .remove         = rtl_remove_one,
7413         .shutdown       = rtl_shutdown,
7414         .driver.pm      = RTL8169_PM_OPS,
7415 };
7416
7417 module_pci_driver(rtl8169_pci_driver);