2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
8 * See MAINTAINERS file for support contact information.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
23 #include <linux/tcp.h>
24 #include <linux/interrupt.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/firmware.h>
28 #include <linux/pci-aspm.h>
29 #include <linux/prefetch.h>
30 #include <linux/ipv6.h>
31 #include <net/ip6_checksum.h>
36 #define RTL8169_VERSION "2.3LK-NAPI"
37 #define MODULENAME "r8169"
38 #define PFX MODULENAME ": "
40 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
41 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
42 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
43 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
44 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
45 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
46 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
47 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
48 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
49 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
50 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
51 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
52 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
53 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
54 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
55 #define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw"
56 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw"
57 #define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw"
58 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw"
61 #define assert(expr) \
63 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
64 #expr,__FILE__,__func__,__LINE__); \
66 #define dprintk(fmt, args...) \
67 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
69 #define assert(expr) do {} while (0)
70 #define dprintk(fmt, args...) do {} while (0)
71 #endif /* RTL8169_DEBUG */
73 #define R8169_MSG_DEFAULT \
74 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
76 #define TX_SLOTS_AVAIL(tp) \
77 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
79 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
80 #define TX_FRAGS_READY_FOR(tp,nr_frags) \
81 (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
83 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
84 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
85 static const int multicast_filter_limit = 32;
87 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
88 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
90 #define R8169_REGS_SIZE 256
91 #define R8169_RX_BUF_SIZE (SZ_16K - 1)
92 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
93 #define NUM_RX_DESC 256U /* Number of Rx descriptor registers */
94 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
95 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
97 #define RTL8169_TX_TIMEOUT (6*HZ)
98 #define RTL8169_PHY_TIMEOUT (10*HZ)
100 /* write/read MMIO register */
101 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg))
102 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
103 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
104 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg))
105 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg))
106 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg))
109 RTL_GIGA_MAC_VER_01 = 0,
160 RTL_GIGA_MAC_NONE = 0xff,
163 enum rtl_tx_desc_version {
168 #define JUMBO_1K ETH_DATA_LEN
169 #define JUMBO_4K (4*1024 - ETH_HLEN - 2)
170 #define JUMBO_6K (6*1024 - ETH_HLEN - 2)
171 #define JUMBO_7K (7*1024 - ETH_HLEN - 2)
172 #define JUMBO_9K (9*1024 - ETH_HLEN - 2)
174 #define _R(NAME,TD,FW,SZ) { \
181 static const struct {
183 enum rtl_tx_desc_version txd_version;
186 } rtl_chip_infos[] = {
188 [RTL_GIGA_MAC_VER_01] =
189 _R("RTL8169", RTL_TD_0, NULL, JUMBO_7K),
190 [RTL_GIGA_MAC_VER_02] =
191 _R("RTL8169s", RTL_TD_0, NULL, JUMBO_7K),
192 [RTL_GIGA_MAC_VER_03] =
193 _R("RTL8110s", RTL_TD_0, NULL, JUMBO_7K),
194 [RTL_GIGA_MAC_VER_04] =
195 _R("RTL8169sb/8110sb", RTL_TD_0, NULL, JUMBO_7K),
196 [RTL_GIGA_MAC_VER_05] =
197 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K),
198 [RTL_GIGA_MAC_VER_06] =
199 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K),
201 [RTL_GIGA_MAC_VER_07] =
202 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K),
203 [RTL_GIGA_MAC_VER_08] =
204 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K),
205 [RTL_GIGA_MAC_VER_09] =
206 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K),
207 [RTL_GIGA_MAC_VER_10] =
208 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K),
209 [RTL_GIGA_MAC_VER_11] =
210 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K),
211 [RTL_GIGA_MAC_VER_12] =
212 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K),
213 [RTL_GIGA_MAC_VER_13] =
214 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K),
215 [RTL_GIGA_MAC_VER_14] =
216 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K),
217 [RTL_GIGA_MAC_VER_15] =
218 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K),
219 [RTL_GIGA_MAC_VER_16] =
220 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K),
221 [RTL_GIGA_MAC_VER_17] =
222 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K),
223 [RTL_GIGA_MAC_VER_18] =
224 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K),
225 [RTL_GIGA_MAC_VER_19] =
226 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K),
227 [RTL_GIGA_MAC_VER_20] =
228 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K),
229 [RTL_GIGA_MAC_VER_21] =
230 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K),
231 [RTL_GIGA_MAC_VER_22] =
232 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K),
233 [RTL_GIGA_MAC_VER_23] =
234 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K),
235 [RTL_GIGA_MAC_VER_24] =
236 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K),
237 [RTL_GIGA_MAC_VER_25] =
238 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1, JUMBO_9K),
239 [RTL_GIGA_MAC_VER_26] =
240 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2, JUMBO_9K),
241 [RTL_GIGA_MAC_VER_27] =
242 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K),
243 [RTL_GIGA_MAC_VER_28] =
244 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K),
245 [RTL_GIGA_MAC_VER_29] =
246 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1, JUMBO_1K),
247 [RTL_GIGA_MAC_VER_30] =
248 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1, JUMBO_1K),
249 [RTL_GIGA_MAC_VER_31] =
250 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K),
251 [RTL_GIGA_MAC_VER_32] =
252 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1, JUMBO_9K),
253 [RTL_GIGA_MAC_VER_33] =
254 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2, JUMBO_9K),
255 [RTL_GIGA_MAC_VER_34] =
256 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3, JUMBO_9K),
257 [RTL_GIGA_MAC_VER_35] =
258 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_1, JUMBO_9K),
259 [RTL_GIGA_MAC_VER_36] =
260 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_2, JUMBO_9K),
261 [RTL_GIGA_MAC_VER_37] =
262 _R("RTL8402", RTL_TD_1, FIRMWARE_8402_1, JUMBO_1K),
263 [RTL_GIGA_MAC_VER_38] =
264 _R("RTL8411", RTL_TD_1, FIRMWARE_8411_1, JUMBO_9K),
265 [RTL_GIGA_MAC_VER_39] =
266 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_1, JUMBO_1K),
267 [RTL_GIGA_MAC_VER_40] =
268 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_2, JUMBO_9K),
269 [RTL_GIGA_MAC_VER_41] =
270 _R("RTL8168g/8111g", RTL_TD_1, NULL, JUMBO_9K),
271 [RTL_GIGA_MAC_VER_42] =
272 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_3, JUMBO_9K),
273 [RTL_GIGA_MAC_VER_43] =
274 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_2, JUMBO_1K),
275 [RTL_GIGA_MAC_VER_44] =
276 _R("RTL8411", RTL_TD_1, FIRMWARE_8411_2, JUMBO_9K),
277 [RTL_GIGA_MAC_VER_45] =
278 _R("RTL8168h/8111h", RTL_TD_1, FIRMWARE_8168H_1, JUMBO_9K),
279 [RTL_GIGA_MAC_VER_46] =
280 _R("RTL8168h/8111h", RTL_TD_1, FIRMWARE_8168H_2, JUMBO_9K),
281 [RTL_GIGA_MAC_VER_47] =
282 _R("RTL8107e", RTL_TD_1, FIRMWARE_8107E_1, JUMBO_1K),
283 [RTL_GIGA_MAC_VER_48] =
284 _R("RTL8107e", RTL_TD_1, FIRMWARE_8107E_2, JUMBO_1K),
285 [RTL_GIGA_MAC_VER_49] =
286 _R("RTL8168ep/8111ep", RTL_TD_1, NULL, JUMBO_9K),
287 [RTL_GIGA_MAC_VER_50] =
288 _R("RTL8168ep/8111ep", RTL_TD_1, NULL, JUMBO_9K),
289 [RTL_GIGA_MAC_VER_51] =
290 _R("RTL8168ep/8111ep", RTL_TD_1, NULL, JUMBO_9K),
300 static const struct pci_device_id rtl8169_pci_tbl[] = {
301 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
302 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
303 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8161), 0, 0, RTL_CFG_1 },
304 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
305 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
306 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
307 { PCI_VENDOR_ID_DLINK, 0x4300,
308 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 },
309 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
310 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 },
311 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
312 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
313 { PCI_VENDOR_ID_LINKSYS, 0x1032,
314 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
316 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
320 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
322 static int use_dac = -1;
328 MAC0 = 0, /* Ethernet hardware address. */
330 MAR0 = 8, /* Multicast filter. */
331 CounterAddrLow = 0x10,
332 CounterAddrHigh = 0x14,
333 TxDescStartAddrLow = 0x20,
334 TxDescStartAddrHigh = 0x24,
335 TxHDescStartAddrLow = 0x28,
336 TxHDescStartAddrHigh = 0x2c,
345 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
346 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
349 #define RX128_INT_EN (1 << 15) /* 8111c and later */
350 #define RX_MULTI_EN (1 << 14) /* 8111c only */
351 #define RXCFG_FIFO_SHIFT 13
352 /* No threshold before first PCI xfer */
353 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
354 #define RX_EARLY_OFF (1 << 11)
355 #define RXCFG_DMA_SHIFT 8
356 /* Unlimited maximum PCI burst. */
357 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
364 #define PME_SIGNAL (1 << 5) /* 8168c and later */
376 #define RTL_COALESCE_MASK 0x0f
377 #define RTL_COALESCE_SHIFT 4
378 #define RTL_COALESCE_T_MAX (RTL_COALESCE_MASK)
379 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_MASK << 2)
381 RxDescAddrLow = 0xe4,
382 RxDescAddrHigh = 0xe8,
383 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
385 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
387 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
389 #define TxPacketMax (8064 >> 7)
390 #define EarlySize 0x27
393 FuncEventMask = 0xf4,
394 FuncPresetState = 0xf8,
399 FuncForceEvent = 0xfc,
402 enum rtl8110_registers {
408 enum rtl8168_8101_registers {
411 #define CSIAR_FLAG 0x80000000
412 #define CSIAR_WRITE_CMD 0x80000000
413 #define CSIAR_BYTE_ENABLE 0x0000f000
414 #define CSIAR_ADDR_MASK 0x00000fff
417 #define EPHYAR_FLAG 0x80000000
418 #define EPHYAR_WRITE_CMD 0x80000000
419 #define EPHYAR_REG_MASK 0x1f
420 #define EPHYAR_REG_SHIFT 16
421 #define EPHYAR_DATA_MASK 0xffff
423 #define PFM_EN (1 << 6)
424 #define TX_10M_PS_EN (1 << 7)
426 #define FIX_NAK_1 (1 << 4)
427 #define FIX_NAK_2 (1 << 3)
430 #define NOW_IS_OOB (1 << 7)
431 #define TX_EMPTY (1 << 5)
432 #define RX_EMPTY (1 << 4)
433 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
434 #define EN_NDP (1 << 3)
435 #define EN_OOB_RESET (1 << 2)
436 #define LINK_LIST_RDY (1 << 1)
438 #define EFUSEAR_FLAG 0x80000000
439 #define EFUSEAR_WRITE_CMD 0x80000000
440 #define EFUSEAR_READ_CMD 0x00000000
441 #define EFUSEAR_REG_MASK 0x03ff
442 #define EFUSEAR_REG_SHIFT 8
443 #define EFUSEAR_DATA_MASK 0xff
445 #define PFM_D3COLD_EN (1 << 6)
448 enum rtl8168_registers {
453 #define ERIAR_FLAG 0x80000000
454 #define ERIAR_WRITE_CMD 0x80000000
455 #define ERIAR_READ_CMD 0x00000000
456 #define ERIAR_ADDR_BYTE_ALIGN 4
457 #define ERIAR_TYPE_SHIFT 16
458 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
459 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
460 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
461 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT)
462 #define ERIAR_MASK_SHIFT 12
463 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
464 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
465 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
466 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
467 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
468 EPHY_RXER_NUM = 0x7c,
469 OCPDR = 0xb0, /* OCP GPHY access */
470 #define OCPDR_WRITE_CMD 0x80000000
471 #define OCPDR_READ_CMD 0x00000000
472 #define OCPDR_REG_MASK 0x7f
473 #define OCPDR_GPHY_REG_SHIFT 16
474 #define OCPDR_DATA_MASK 0xffff
476 #define OCPAR_FLAG 0x80000000
477 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
478 #define OCPAR_GPHY_READ_CMD 0x0000f060
480 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
481 MISC = 0xf0, /* 8168e only. */
482 #define TXPLA_RST (1 << 29)
483 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
484 #define PWM_EN (1 << 22)
485 #define RXDV_GATED_EN (1 << 19)
486 #define EARLY_TALLY_EN (1 << 16)
489 enum rtl_register_content {
490 /* InterruptStatusBits */
494 TxDescUnavail = 0x0080,
518 /* TXPoll register p.5 */
519 HPQ = 0x80, /* Poll cmd on the high prio queue */
520 NPQ = 0x40, /* Poll cmd on the low prio queue */
521 FSWInt = 0x01, /* Forced software interrupt */
525 Cfg9346_Unlock = 0xc0,
530 AcceptBroadcast = 0x08,
531 AcceptMulticast = 0x04,
533 AcceptAllPhys = 0x01,
534 #define RX_CONFIG_ACCEPT_MASK 0x3f
537 TxInterFrameGapShift = 24,
538 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
540 /* Config1 register p.24 */
543 Speed_down = (1 << 4),
547 PMEnable = (1 << 0), /* Power Management Enable */
549 /* Config2 register p. 25 */
550 ClkReqEn = (1 << 7), /* Clock Request Enable */
551 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
552 PCI_Clock_66MHz = 0x01,
553 PCI_Clock_33MHz = 0x00,
555 /* Config3 register p.25 */
556 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
557 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
558 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
559 Rdy_to_L23 = (1 << 1), /* L23 Enable */
560 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
562 /* Config4 register */
563 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
565 /* Config5 register p.27 */
566 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
567 MWF = (1 << 5), /* Accept Multicast wakeup frame */
568 UWF = (1 << 4), /* Accept Unicast wakeup frame */
570 LanWake = (1 << 1), /* LanWake enable/disable */
571 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
572 ASPM_en = (1 << 0), /* ASPM enable */
575 TBIReset = 0x80000000,
576 TBILoopback = 0x40000000,
577 TBINwEnable = 0x20000000,
578 TBINwRestart = 0x10000000,
579 TBILinkOk = 0x02000000,
580 TBINwComplete = 0x01000000,
583 EnableBist = (1 << 15), // 8168 8101
584 Mac_dbgo_oe = (1 << 14), // 8168 8101
585 Normal_mode = (1 << 13), // unused
586 Force_half_dup = (1 << 12), // 8168 8101
587 Force_rxflow_en = (1 << 11), // 8168 8101
588 Force_txflow_en = (1 << 10), // 8168 8101
589 Cxpl_dbg_sel = (1 << 9), // 8168 8101
590 ASF = (1 << 8), // 8168 8101
591 PktCntrDisable = (1 << 7), // 8168 8101
592 Mac_dbgo_sel = 0x001c, // 8168
597 #define INTT_MASK GENMASK(1, 0)
598 INTT_0 = 0x0000, // 8168
599 INTT_1 = 0x0001, // 8168
600 INTT_2 = 0x0002, // 8168
601 INTT_3 = 0x0003, // 8168
603 /* rtl8169_PHYstatus */
614 TBILinkOK = 0x02000000,
616 /* ResetCounterCommand */
619 /* DumpCounterCommand */
622 /* magic enable v2 */
623 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */
627 /* First doubleword. */
628 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
629 RingEnd = (1 << 30), /* End of descriptor ring */
630 FirstFrag = (1 << 29), /* First segment of a packet */
631 LastFrag = (1 << 28), /* Final segment of a packet */
635 enum rtl_tx_desc_bit {
636 /* First doubleword. */
637 TD_LSO = (1 << 27), /* Large Send Offload */
638 #define TD_MSS_MAX 0x07ffu /* MSS value */
640 /* Second doubleword. */
641 TxVlanTag = (1 << 17), /* Add VLAN tag */
644 /* 8169, 8168b and 810x except 8102e. */
645 enum rtl_tx_desc_bit_0 {
646 /* First doubleword. */
647 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
648 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
649 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
650 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
653 /* 8102e, 8168c and beyond. */
654 enum rtl_tx_desc_bit_1 {
655 /* First doubleword. */
656 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */
657 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */
658 #define GTTCPHO_SHIFT 18
659 #define GTTCPHO_MAX 0x7fU
661 /* Second doubleword. */
662 #define TCPHO_SHIFT 18
663 #define TCPHO_MAX 0x3ffU
664 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
665 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */
666 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */
667 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
668 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
671 enum rtl_rx_desc_bit {
673 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
674 PID0 = (1 << 17), /* Protocol ID bit 0/2 */
676 #define RxProtoUDP (PID1)
677 #define RxProtoTCP (PID0)
678 #define RxProtoIP (PID1 | PID0)
679 #define RxProtoMask RxProtoIP
681 IPFail = (1 << 16), /* IP checksum failed */
682 UDPFail = (1 << 15), /* UDP/IP checksum failed */
683 TCPFail = (1 << 14), /* TCP/IP checksum failed */
684 RxVlanTag = (1 << 16), /* VLAN tag available */
687 #define RsvdMask 0x3fffc000
688 #define CPCMD_QUIRK_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
705 u8 __pad[sizeof(void *) - sizeof(u32)];
708 struct rtl8169_counters {
715 __le32 tx_one_collision;
716 __le32 tx_multi_collision;
724 struct rtl8169_tc_offsets {
727 __le32 tx_multi_collision;
732 RTL_FLAG_TASK_ENABLED,
733 RTL_FLAG_TASK_SLOW_PENDING,
734 RTL_FLAG_TASK_RESET_PENDING,
735 RTL_FLAG_TASK_PHY_PENDING,
739 struct rtl8169_stats {
742 struct u64_stats_sync syncp;
745 struct rtl8169_private {
746 void __iomem *mmio_addr; /* memory map physical address */
747 struct pci_dev *pci_dev;
748 struct net_device *dev;
749 struct napi_struct napi;
752 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
753 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
755 struct rtl8169_stats rx_stats;
756 struct rtl8169_stats tx_stats;
757 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
758 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
759 dma_addr_t TxPhyAddr;
760 dma_addr_t RxPhyAddr;
761 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
762 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
763 struct timer_list timer;
767 const struct rtl_coalesce_info *coalesce_info;
770 void (*write)(struct rtl8169_private *, int, int);
771 int (*read)(struct rtl8169_private *, int);
775 void (*enable)(struct rtl8169_private *);
776 void (*disable)(struct rtl8169_private *);
779 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
780 int (*get_link_ksettings)(struct net_device *,
781 struct ethtool_link_ksettings *);
782 void (*phy_reset_enable)(struct rtl8169_private *tp);
783 void (*hw_start)(struct rtl8169_private *tp);
784 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
785 unsigned int (*link_ok)(struct rtl8169_private *tp);
786 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
787 bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
790 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
792 struct work_struct work;
795 struct mii_if_info mii;
796 dma_addr_t counters_phys_addr;
797 struct rtl8169_counters *counters;
798 struct rtl8169_tc_offsets tc_offset;
802 const struct firmware *fw;
804 #define RTL_VER_SIZE 32
806 char version[RTL_VER_SIZE];
808 struct rtl_fw_phy_action {
813 #define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
818 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
819 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
820 module_param(use_dac, int, 0);
821 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
822 module_param_named(debug, debug.msg_enable, int, 0);
823 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
824 MODULE_LICENSE("GPL");
825 MODULE_VERSION(RTL8169_VERSION);
826 MODULE_FIRMWARE(FIRMWARE_8168D_1);
827 MODULE_FIRMWARE(FIRMWARE_8168D_2);
828 MODULE_FIRMWARE(FIRMWARE_8168E_1);
829 MODULE_FIRMWARE(FIRMWARE_8168E_2);
830 MODULE_FIRMWARE(FIRMWARE_8168E_3);
831 MODULE_FIRMWARE(FIRMWARE_8105E_1);
832 MODULE_FIRMWARE(FIRMWARE_8168F_1);
833 MODULE_FIRMWARE(FIRMWARE_8168F_2);
834 MODULE_FIRMWARE(FIRMWARE_8402_1);
835 MODULE_FIRMWARE(FIRMWARE_8411_1);
836 MODULE_FIRMWARE(FIRMWARE_8411_2);
837 MODULE_FIRMWARE(FIRMWARE_8106E_1);
838 MODULE_FIRMWARE(FIRMWARE_8106E_2);
839 MODULE_FIRMWARE(FIRMWARE_8168G_2);
840 MODULE_FIRMWARE(FIRMWARE_8168G_3);
841 MODULE_FIRMWARE(FIRMWARE_8168H_1);
842 MODULE_FIRMWARE(FIRMWARE_8168H_2);
843 MODULE_FIRMWARE(FIRMWARE_8107E_1);
844 MODULE_FIRMWARE(FIRMWARE_8107E_2);
846 static inline struct device *tp_to_dev(struct rtl8169_private *tp)
848 return &tp->pci_dev->dev;
851 static void rtl_lock_work(struct rtl8169_private *tp)
853 mutex_lock(&tp->wk.mutex);
856 static void rtl_unlock_work(struct rtl8169_private *tp)
858 mutex_unlock(&tp->wk.mutex);
861 static void rtl_tx_performance_tweak(struct rtl8169_private *tp, u16 force)
863 pcie_capability_clear_and_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
864 PCI_EXP_DEVCTL_READRQ, force);
868 bool (*check)(struct rtl8169_private *);
872 static void rtl_udelay(unsigned int d)
877 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
878 void (*delay)(unsigned int), unsigned int d, int n,
883 for (i = 0; i < n; i++) {
885 if (c->check(tp) == high)
888 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
889 c->msg, !high, n, d);
893 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
894 const struct rtl_cond *c,
895 unsigned int d, int n)
897 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
900 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
901 const struct rtl_cond *c,
902 unsigned int d, int n)
904 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
907 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
908 const struct rtl_cond *c,
909 unsigned int d, int n)
911 return rtl_loop_wait(tp, c, msleep, d, n, true);
914 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
915 const struct rtl_cond *c,
916 unsigned int d, int n)
918 return rtl_loop_wait(tp, c, msleep, d, n, false);
921 #define DECLARE_RTL_COND(name) \
922 static bool name ## _check(struct rtl8169_private *); \
924 static const struct rtl_cond name = { \
925 .check = name ## _check, \
929 static bool name ## _check(struct rtl8169_private *tp)
931 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
933 if (reg & 0xffff0001) {
934 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
940 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
942 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
945 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
947 if (rtl_ocp_reg_failure(tp, reg))
950 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
952 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
955 static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
957 if (rtl_ocp_reg_failure(tp, reg))
960 RTL_W32(tp, GPHY_OCP, reg << 15);
962 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
963 (RTL_R32(tp, GPHY_OCP) & 0xffff) : ~0;
966 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
968 if (rtl_ocp_reg_failure(tp, reg))
971 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
974 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
976 if (rtl_ocp_reg_failure(tp, reg))
979 RTL_W32(tp, OCPDR, reg << 15);
981 return RTL_R32(tp, OCPDR);
984 #define OCP_STD_PHY_BASE 0xa400
986 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
989 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
993 if (tp->ocp_base != OCP_STD_PHY_BASE)
996 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
999 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
1001 if (tp->ocp_base != OCP_STD_PHY_BASE)
1004 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
1007 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
1010 tp->ocp_base = value << 4;
1014 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
1017 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
1019 return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
1022 DECLARE_RTL_COND(rtl_phyar_cond)
1024 return RTL_R32(tp, PHYAR) & 0x80000000;
1027 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1029 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1031 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
1033 * According to hardware specs a 20us delay is required after write
1034 * complete indication, but before sending next command.
1039 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1043 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
1045 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1046 RTL_R32(tp, PHYAR) & 0xffff : ~0;
1049 * According to hardware specs a 20us delay is required after read
1050 * complete indication, but before sending next command.
1057 DECLARE_RTL_COND(rtl_ocpar_cond)
1059 return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
1062 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
1064 RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
1065 RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
1066 RTL_W32(tp, EPHY_RXER_NUM, 0);
1068 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
1071 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
1073 r8168dp_1_mdio_access(tp, reg,
1074 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
1077 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
1079 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
1082 RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
1083 RTL_W32(tp, EPHY_RXER_NUM, 0);
1085 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1086 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : ~0;
1089 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
1091 static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
1093 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1096 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
1098 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1101 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
1103 r8168dp_2_mdio_start(tp);
1105 r8169_mdio_write(tp, reg, value);
1107 r8168dp_2_mdio_stop(tp);
1110 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1114 r8168dp_2_mdio_start(tp);
1116 value = r8169_mdio_read(tp, reg);
1118 r8168dp_2_mdio_stop(tp);
1123 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1125 tp->mdio_ops.write(tp, location, val);
1128 static int rtl_readphy(struct rtl8169_private *tp, int location)
1130 return tp->mdio_ops.read(tp, location);
1133 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1135 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1138 static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1142 val = rtl_readphy(tp, reg_addr);
1143 rtl_writephy(tp, reg_addr, (val & ~m) | p);
1146 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1149 struct rtl8169_private *tp = netdev_priv(dev);
1151 rtl_writephy(tp, location, val);
1154 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1156 struct rtl8169_private *tp = netdev_priv(dev);
1158 return rtl_readphy(tp, location);
1161 DECLARE_RTL_COND(rtl_ephyar_cond)
1163 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1166 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1168 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1169 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1171 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1176 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1178 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1180 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1181 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1184 DECLARE_RTL_COND(rtl_eriar_cond)
1186 return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
1189 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1192 BUG_ON((addr & 3) || (mask == 0));
1193 RTL_W32(tp, ERIDR, val);
1194 RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1196 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1199 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1201 RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1203 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1204 RTL_R32(tp, ERIDR) : ~0;
1207 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1212 val = rtl_eri_read(tp, addr, type);
1213 rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
1216 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1218 RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1219 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1220 RTL_R32(tp, OCPDR) : ~0;
1223 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1225 return rtl_eri_read(tp, reg, ERIAR_OOB);
1228 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1230 switch (tp->mac_version) {
1231 case RTL_GIGA_MAC_VER_27:
1232 case RTL_GIGA_MAC_VER_28:
1233 case RTL_GIGA_MAC_VER_31:
1234 return r8168dp_ocp_read(tp, mask, reg);
1235 case RTL_GIGA_MAC_VER_49:
1236 case RTL_GIGA_MAC_VER_50:
1237 case RTL_GIGA_MAC_VER_51:
1238 return r8168ep_ocp_read(tp, mask, reg);
1245 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1248 RTL_W32(tp, OCPDR, data);
1249 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1250 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1253 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1256 rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1260 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
1262 switch (tp->mac_version) {
1263 case RTL_GIGA_MAC_VER_27:
1264 case RTL_GIGA_MAC_VER_28:
1265 case RTL_GIGA_MAC_VER_31:
1266 r8168dp_ocp_write(tp, mask, reg, data);
1268 case RTL_GIGA_MAC_VER_49:
1269 case RTL_GIGA_MAC_VER_50:
1270 case RTL_GIGA_MAC_VER_51:
1271 r8168ep_ocp_write(tp, mask, reg, data);
1279 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
1281 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd, ERIAR_EXGMAC);
1283 ocp_write(tp, 0x1, 0x30, 0x00000001);
1286 #define OOB_CMD_RESET 0x00
1287 #define OOB_CMD_DRIVER_START 0x05
1288 #define OOB_CMD_DRIVER_STOP 0x06
1290 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1292 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1295 DECLARE_RTL_COND(rtl_ocp_read_cond)
1299 reg = rtl8168_get_ocp_reg(tp);
1301 return ocp_read(tp, 0x0f, reg) & 0x00000800;
1304 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1306 return ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1309 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1311 return RTL_R8(tp, IBISR0) & 0x20;
1314 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1316 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1317 rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000);
1318 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1319 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1322 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1324 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
1325 rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
1328 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1330 ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1331 ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1332 rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1335 static void rtl8168_driver_start(struct rtl8169_private *tp)
1337 switch (tp->mac_version) {
1338 case RTL_GIGA_MAC_VER_27:
1339 case RTL_GIGA_MAC_VER_28:
1340 case RTL_GIGA_MAC_VER_31:
1341 rtl8168dp_driver_start(tp);
1343 case RTL_GIGA_MAC_VER_49:
1344 case RTL_GIGA_MAC_VER_50:
1345 case RTL_GIGA_MAC_VER_51:
1346 rtl8168ep_driver_start(tp);
1354 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1356 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1357 rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
1360 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1362 rtl8168ep_stop_cmac(tp);
1363 ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1364 ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1365 rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1368 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1370 switch (tp->mac_version) {
1371 case RTL_GIGA_MAC_VER_27:
1372 case RTL_GIGA_MAC_VER_28:
1373 case RTL_GIGA_MAC_VER_31:
1374 rtl8168dp_driver_stop(tp);
1376 case RTL_GIGA_MAC_VER_49:
1377 case RTL_GIGA_MAC_VER_50:
1378 case RTL_GIGA_MAC_VER_51:
1379 rtl8168ep_driver_stop(tp);
1387 static bool r8168dp_check_dash(struct rtl8169_private *tp)
1389 u16 reg = rtl8168_get_ocp_reg(tp);
1391 return !!(ocp_read(tp, 0x0f, reg) & 0x00008000);
1394 static bool r8168ep_check_dash(struct rtl8169_private *tp)
1396 return !!(ocp_read(tp, 0x0f, 0x128) & 0x00000001);
1399 static bool r8168_check_dash(struct rtl8169_private *tp)
1401 switch (tp->mac_version) {
1402 case RTL_GIGA_MAC_VER_27:
1403 case RTL_GIGA_MAC_VER_28:
1404 case RTL_GIGA_MAC_VER_31:
1405 return r8168dp_check_dash(tp);
1406 case RTL_GIGA_MAC_VER_49:
1407 case RTL_GIGA_MAC_VER_50:
1408 case RTL_GIGA_MAC_VER_51:
1409 return r8168ep_check_dash(tp);
1421 static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
1422 const struct exgmac_reg *r, int len)
1425 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1430 DECLARE_RTL_COND(rtl_efusear_cond)
1432 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1435 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1437 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1439 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1440 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1443 static u16 rtl_get_events(struct rtl8169_private *tp)
1445 return RTL_R16(tp, IntrStatus);
1448 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1450 RTL_W16(tp, IntrStatus, bits);
1454 static void rtl_irq_disable(struct rtl8169_private *tp)
1456 RTL_W16(tp, IntrMask, 0);
1460 static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1462 RTL_W16(tp, IntrMask, bits);
1465 #define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1466 #define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1467 #define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1469 static void rtl_irq_enable_all(struct rtl8169_private *tp)
1471 rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1474 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1476 rtl_irq_disable(tp);
1477 rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
1478 RTL_R8(tp, ChipCmd);
1481 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1483 return RTL_R32(tp, TBICSR) & TBIReset;
1486 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1488 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1491 static unsigned int rtl8169_tbi_link_ok(struct rtl8169_private *tp)
1493 return RTL_R32(tp, TBICSR) & TBILinkOk;
1496 static unsigned int rtl8169_xmii_link_ok(struct rtl8169_private *tp)
1498 return RTL_R8(tp, PHYstatus) & LinkStatus;
1501 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1503 RTL_W32(tp, TBICSR, RTL_R32(tp, TBICSR) | TBIReset);
1506 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1510 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1511 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1514 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1516 struct net_device *dev = tp->dev;
1518 if (!netif_running(dev))
1521 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1522 tp->mac_version == RTL_GIGA_MAC_VER_38) {
1523 if (RTL_R8(tp, PHYstatus) & _1000bpsF) {
1524 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1526 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1528 } else if (RTL_R8(tp, PHYstatus) & _100bps) {
1529 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1531 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1534 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1536 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1539 /* Reset packet filter */
1540 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1542 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1544 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1545 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1546 if (RTL_R8(tp, PHYstatus) & _1000bpsF) {
1547 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1549 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1552 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1554 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1557 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1558 if (RTL_R8(tp, PHYstatus) & _10bps) {
1559 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1561 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1564 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1570 static void rtl8169_check_link_status(struct net_device *dev,
1571 struct rtl8169_private *tp)
1573 struct device *d = tp_to_dev(tp);
1575 if (tp->link_ok(tp)) {
1576 rtl_link_chg_patch(tp);
1577 /* This is to cancel a scheduled suspend if there's one. */
1578 pm_request_resume(d);
1579 netif_carrier_on(dev);
1580 if (net_ratelimit())
1581 netif_info(tp, ifup, dev, "link up\n");
1583 netif_carrier_off(dev);
1584 netif_info(tp, ifdown, dev, "link down\n");
1589 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1591 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1596 options = RTL_R8(tp, Config1);
1597 if (!(options & PMEnable))
1600 options = RTL_R8(tp, Config3);
1601 if (options & LinkUp)
1602 wolopts |= WAKE_PHY;
1603 switch (tp->mac_version) {
1604 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
1605 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1606 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
1607 wolopts |= WAKE_MAGIC;
1610 if (options & MagicPacket)
1611 wolopts |= WAKE_MAGIC;
1615 options = RTL_R8(tp, Config5);
1617 wolopts |= WAKE_UCAST;
1619 wolopts |= WAKE_BCAST;
1621 wolopts |= WAKE_MCAST;
1626 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1628 struct rtl8169_private *tp = netdev_priv(dev);
1629 struct device *d = tp_to_dev(tp);
1631 pm_runtime_get_noresume(d);
1635 wol->supported = WAKE_ANY;
1636 if (pm_runtime_active(d))
1637 wol->wolopts = __rtl8169_get_wol(tp);
1639 wol->wolopts = tp->saved_wolopts;
1641 rtl_unlock_work(tp);
1643 pm_runtime_put_noidle(d);
1646 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1648 unsigned int i, tmp;
1649 static const struct {
1654 { WAKE_PHY, Config3, LinkUp },
1655 { WAKE_UCAST, Config5, UWF },
1656 { WAKE_BCAST, Config5, BWF },
1657 { WAKE_MCAST, Config5, MWF },
1658 { WAKE_ANY, Config5, LanWake },
1659 { WAKE_MAGIC, Config3, MagicPacket }
1663 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
1665 switch (tp->mac_version) {
1666 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
1667 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1668 tmp = ARRAY_SIZE(cfg) - 1;
1669 if (wolopts & WAKE_MAGIC)
1685 tmp = ARRAY_SIZE(cfg);
1689 for (i = 0; i < tmp; i++) {
1690 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
1691 if (wolopts & cfg[i].opt)
1692 options |= cfg[i].mask;
1693 RTL_W8(tp, cfg[i].reg, options);
1696 switch (tp->mac_version) {
1697 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1698 options = RTL_R8(tp, Config1) & ~PMEnable;
1700 options |= PMEnable;
1701 RTL_W8(tp, Config1, options);
1704 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
1706 options |= PME_SIGNAL;
1707 RTL_W8(tp, Config2, options);
1711 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
1714 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1716 struct rtl8169_private *tp = netdev_priv(dev);
1717 struct device *d = tp_to_dev(tp);
1719 pm_runtime_get_noresume(d);
1723 if (pm_runtime_active(d))
1724 __rtl8169_set_wol(tp, wol->wolopts);
1726 tp->saved_wolopts = wol->wolopts;
1728 rtl_unlock_work(tp);
1730 device_set_wakeup_enable(d, wol->wolopts);
1732 pm_runtime_put_noidle(d);
1737 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1739 return rtl_chip_infos[tp->mac_version].fw_name;
1742 static void rtl8169_get_drvinfo(struct net_device *dev,
1743 struct ethtool_drvinfo *info)
1745 struct rtl8169_private *tp = netdev_priv(dev);
1746 struct rtl_fw *rtl_fw = tp->rtl_fw;
1748 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1749 strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1750 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1751 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1752 if (!IS_ERR_OR_NULL(rtl_fw))
1753 strlcpy(info->fw_version, rtl_fw->version,
1754 sizeof(info->fw_version));
1757 static int rtl8169_get_regs_len(struct net_device *dev)
1759 return R8169_REGS_SIZE;
1762 static int rtl8169_set_speed_tbi(struct net_device *dev,
1763 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1765 struct rtl8169_private *tp = netdev_priv(dev);
1769 reg = RTL_R32(tp, TBICSR);
1770 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1771 (duplex == DUPLEX_FULL)) {
1772 RTL_W32(tp, TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1773 } else if (autoneg == AUTONEG_ENABLE)
1774 RTL_W32(tp, TBICSR, reg | TBINwEnable | TBINwRestart);
1776 netif_warn(tp, link, dev,
1777 "incorrect speed setting refused in TBI mode\n");
1784 static int rtl8169_set_speed_xmii(struct net_device *dev,
1785 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1787 struct rtl8169_private *tp = netdev_priv(dev);
1788 int giga_ctrl, bmcr;
1791 rtl_writephy(tp, 0x1f, 0x0000);
1793 if (autoneg == AUTONEG_ENABLE) {
1796 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1797 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1798 ADVERTISE_100HALF | ADVERTISE_100FULL);
1800 if (adv & ADVERTISED_10baseT_Half)
1801 auto_nego |= ADVERTISE_10HALF;
1802 if (adv & ADVERTISED_10baseT_Full)
1803 auto_nego |= ADVERTISE_10FULL;
1804 if (adv & ADVERTISED_100baseT_Half)
1805 auto_nego |= ADVERTISE_100HALF;
1806 if (adv & ADVERTISED_100baseT_Full)
1807 auto_nego |= ADVERTISE_100FULL;
1809 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1811 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1812 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1814 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1815 if (tp->mii.supports_gmii) {
1816 if (adv & ADVERTISED_1000baseT_Half)
1817 giga_ctrl |= ADVERTISE_1000HALF;
1818 if (adv & ADVERTISED_1000baseT_Full)
1819 giga_ctrl |= ADVERTISE_1000FULL;
1820 } else if (adv & (ADVERTISED_1000baseT_Half |
1821 ADVERTISED_1000baseT_Full)) {
1822 netif_info(tp, link, dev,
1823 "PHY does not support 1000Mbps\n");
1827 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1829 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1830 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1832 if (speed == SPEED_10)
1834 else if (speed == SPEED_100)
1835 bmcr = BMCR_SPEED100;
1839 if (duplex == DUPLEX_FULL)
1840 bmcr |= BMCR_FULLDPLX;
1843 rtl_writephy(tp, MII_BMCR, bmcr);
1845 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1846 tp->mac_version == RTL_GIGA_MAC_VER_03) {
1847 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1848 rtl_writephy(tp, 0x17, 0x2138);
1849 rtl_writephy(tp, 0x0e, 0x0260);
1851 rtl_writephy(tp, 0x17, 0x2108);
1852 rtl_writephy(tp, 0x0e, 0x0000);
1861 static int rtl8169_set_speed(struct net_device *dev,
1862 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1864 struct rtl8169_private *tp = netdev_priv(dev);
1867 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1871 if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1872 (advertising & ADVERTISED_1000baseT_Full) &&
1873 !pci_is_pcie(tp->pci_dev)) {
1874 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1880 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1881 netdev_features_t features)
1883 struct rtl8169_private *tp = netdev_priv(dev);
1885 if (dev->mtu > TD_MSS_MAX)
1886 features &= ~NETIF_F_ALL_TSO;
1888 if (dev->mtu > JUMBO_1K &&
1889 tp->mac_version > RTL_GIGA_MAC_VER_06)
1890 features &= ~NETIF_F_IP_CSUM;
1895 static int rtl8169_set_features(struct net_device *dev,
1896 netdev_features_t features)
1898 struct rtl8169_private *tp = netdev_priv(dev);
1903 rx_config = RTL_R32(tp, RxConfig);
1904 if (features & NETIF_F_RXALL)
1905 rx_config |= (AcceptErr | AcceptRunt);
1907 rx_config &= ~(AcceptErr | AcceptRunt);
1909 RTL_W32(tp, RxConfig, rx_config);
1911 if (features & NETIF_F_RXCSUM)
1912 tp->cp_cmd |= RxChkSum;
1914 tp->cp_cmd &= ~RxChkSum;
1916 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1917 tp->cp_cmd |= RxVlan;
1919 tp->cp_cmd &= ~RxVlan;
1921 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1922 RTL_R16(tp, CPlusCmd);
1924 rtl_unlock_work(tp);
1929 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1931 return (skb_vlan_tag_present(skb)) ?
1932 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1935 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1937 u32 opts2 = le32_to_cpu(desc->opts2);
1939 if (opts2 & RxVlanTag)
1940 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1943 static int rtl8169_get_link_ksettings_tbi(struct net_device *dev,
1944 struct ethtool_link_ksettings *cmd)
1946 struct rtl8169_private *tp = netdev_priv(dev);
1948 u32 supported, advertising;
1951 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1952 cmd->base.port = PORT_FIBRE;
1954 status = RTL_R32(tp, TBICSR);
1955 advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1956 cmd->base.autoneg = !!(status & TBINwEnable);
1958 cmd->base.speed = SPEED_1000;
1959 cmd->base.duplex = DUPLEX_FULL; /* Always set */
1961 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
1963 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
1969 static int rtl8169_get_link_ksettings_xmii(struct net_device *dev,
1970 struct ethtool_link_ksettings *cmd)
1972 struct rtl8169_private *tp = netdev_priv(dev);
1974 mii_ethtool_get_link_ksettings(&tp->mii, cmd);
1979 static int rtl8169_get_link_ksettings(struct net_device *dev,
1980 struct ethtool_link_ksettings *cmd)
1982 struct rtl8169_private *tp = netdev_priv(dev);
1986 rc = tp->get_link_ksettings(dev, cmd);
1987 rtl_unlock_work(tp);
1992 static int rtl8169_set_link_ksettings(struct net_device *dev,
1993 const struct ethtool_link_ksettings *cmd)
1995 struct rtl8169_private *tp = netdev_priv(dev);
1999 if (!ethtool_convert_link_mode_to_legacy_u32(&advertising,
2000 cmd->link_modes.advertising))
2003 del_timer_sync(&tp->timer);
2006 rc = rtl8169_set_speed(dev, cmd->base.autoneg, cmd->base.speed,
2007 cmd->base.duplex, advertising);
2008 rtl_unlock_work(tp);
2013 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2016 struct rtl8169_private *tp = netdev_priv(dev);
2017 u32 __iomem *data = tp->mmio_addr;
2022 for (i = 0; i < R8169_REGS_SIZE; i += 4)
2023 memcpy_fromio(dw++, data++, 4);
2024 rtl_unlock_work(tp);
2027 static u32 rtl8169_get_msglevel(struct net_device *dev)
2029 struct rtl8169_private *tp = netdev_priv(dev);
2031 return tp->msg_enable;
2034 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
2036 struct rtl8169_private *tp = netdev_priv(dev);
2038 tp->msg_enable = value;
2041 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
2048 "tx_single_collisions",
2049 "tx_multi_collisions",
2057 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
2061 return ARRAY_SIZE(rtl8169_gstrings);
2067 DECLARE_RTL_COND(rtl_counters_cond)
2069 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
2072 static bool rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
2074 dma_addr_t paddr = tp->counters_phys_addr;
2077 RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
2078 RTL_R32(tp, CounterAddrHigh);
2079 cmd = (u64)paddr & DMA_BIT_MASK(32);
2080 RTL_W32(tp, CounterAddrLow, cmd);
2081 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
2083 return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
2086 static bool rtl8169_reset_counters(struct rtl8169_private *tp)
2089 * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
2092 if (tp->mac_version < RTL_GIGA_MAC_VER_19)
2095 return rtl8169_do_counters(tp, CounterReset);
2098 static bool rtl8169_update_counters(struct rtl8169_private *tp)
2101 * Some chips are unable to dump tally counters when the receiver
2104 if ((RTL_R8(tp, ChipCmd) & CmdRxEnb) == 0)
2107 return rtl8169_do_counters(tp, CounterDump);
2110 static bool rtl8169_init_counter_offsets(struct rtl8169_private *tp)
2112 struct rtl8169_counters *counters = tp->counters;
2116 * rtl8169_init_counter_offsets is called from rtl_open. On chip
2117 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
2118 * reset by a power cycle, while the counter values collected by the
2119 * driver are reset at every driver unload/load cycle.
2121 * To make sure the HW values returned by @get_stats64 match the SW
2122 * values, we collect the initial values at first open(*) and use them
2123 * as offsets to normalize the values returned by @get_stats64.
2125 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
2126 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
2127 * set at open time by rtl_hw_start.
2130 if (tp->tc_offset.inited)
2133 /* If both, reset and update fail, propagate to caller. */
2134 if (rtl8169_reset_counters(tp))
2137 if (rtl8169_update_counters(tp))
2140 tp->tc_offset.tx_errors = counters->tx_errors;
2141 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
2142 tp->tc_offset.tx_aborted = counters->tx_aborted;
2143 tp->tc_offset.inited = true;
2148 static void rtl8169_get_ethtool_stats(struct net_device *dev,
2149 struct ethtool_stats *stats, u64 *data)
2151 struct rtl8169_private *tp = netdev_priv(dev);
2152 struct device *d = tp_to_dev(tp);
2153 struct rtl8169_counters *counters = tp->counters;
2157 pm_runtime_get_noresume(d);
2159 if (pm_runtime_active(d))
2160 rtl8169_update_counters(tp);
2162 pm_runtime_put_noidle(d);
2164 data[0] = le64_to_cpu(counters->tx_packets);
2165 data[1] = le64_to_cpu(counters->rx_packets);
2166 data[2] = le64_to_cpu(counters->tx_errors);
2167 data[3] = le32_to_cpu(counters->rx_errors);
2168 data[4] = le16_to_cpu(counters->rx_missed);
2169 data[5] = le16_to_cpu(counters->align_errors);
2170 data[6] = le32_to_cpu(counters->tx_one_collision);
2171 data[7] = le32_to_cpu(counters->tx_multi_collision);
2172 data[8] = le64_to_cpu(counters->rx_unicast);
2173 data[9] = le64_to_cpu(counters->rx_broadcast);
2174 data[10] = le32_to_cpu(counters->rx_multicast);
2175 data[11] = le16_to_cpu(counters->tx_aborted);
2176 data[12] = le16_to_cpu(counters->tx_underun);
2179 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2183 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
2188 static int rtl8169_nway_reset(struct net_device *dev)
2190 struct rtl8169_private *tp = netdev_priv(dev);
2192 return mii_nway_restart(&tp->mii);
2196 * Interrupt coalescing
2198 * > 1 - the availability of the IntrMitigate (0xe2) register through the
2199 * > 8169, 8168 and 810x line of chipsets
2201 * 8169, 8168, and 8136(810x) serial chipsets support it.
2203 * > 2 - the Tx timer unit at gigabit speed
2205 * The unit of the timer depends on both the speed and the setting of CPlusCmd
2206 * (0xe0) bit 1 and bit 0.
2209 * bit[1:0] \ speed 1000M 100M 10M
2210 * 0 0 320ns 2.56us 40.96us
2211 * 0 1 2.56us 20.48us 327.7us
2212 * 1 0 5.12us 40.96us 655.4us
2213 * 1 1 10.24us 81.92us 1.31ms
2216 * bit[1:0] \ speed 1000M 100M 10M
2217 * 0 0 5us 2.56us 40.96us
2218 * 0 1 40us 20.48us 327.7us
2219 * 1 0 80us 40.96us 655.4us
2220 * 1 1 160us 81.92us 1.31ms
2223 /* rx/tx scale factors for one particular CPlusCmd[0:1] value */
2224 struct rtl_coalesce_scale {
2229 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
2230 struct rtl_coalesce_info {
2232 struct rtl_coalesce_scale scalev[4]; /* each CPlusCmd[0:1] case */
2235 /* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */
2236 #define rxtx_x1822(r, t) { \
2239 {{(r)*8*2, (t)*8*2}}, \
2240 {{(r)*8*2*2, (t)*8*2*2}}, \
2242 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
2243 /* speed delays: rx00 tx00 */
2244 { SPEED_10, rxtx_x1822(40960, 40960) },
2245 { SPEED_100, rxtx_x1822( 2560, 2560) },
2246 { SPEED_1000, rxtx_x1822( 320, 320) },
2250 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
2251 /* speed delays: rx00 tx00 */
2252 { SPEED_10, rxtx_x1822(40960, 40960) },
2253 { SPEED_100, rxtx_x1822( 2560, 2560) },
2254 { SPEED_1000, rxtx_x1822( 5000, 5000) },
2259 /* get rx/tx scale vector corresponding to current speed */
2260 static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev)
2262 struct rtl8169_private *tp = netdev_priv(dev);
2263 struct ethtool_link_ksettings ecmd;
2264 const struct rtl_coalesce_info *ci;
2267 rc = rtl8169_get_link_ksettings(dev, &ecmd);
2271 for (ci = tp->coalesce_info; ci->speed != 0; ci++) {
2272 if (ecmd.base.speed == ci->speed) {
2277 return ERR_PTR(-ELNRNG);
2280 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
2282 struct rtl8169_private *tp = netdev_priv(dev);
2283 const struct rtl_coalesce_info *ci;
2284 const struct rtl_coalesce_scale *scale;
2288 } coal_settings [] = {
2289 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs },
2290 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs }
2291 }, *p = coal_settings;
2295 memset(ec, 0, sizeof(*ec));
2297 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
2298 ci = rtl_coalesce_info(dev);
2302 scale = &ci->scalev[tp->cp_cmd & INTT_MASK];
2304 /* read IntrMitigate and adjust according to scale */
2305 for (w = RTL_R16(tp, IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) {
2306 *p->max_frames = (w & RTL_COALESCE_MASK) << 2;
2307 w >>= RTL_COALESCE_SHIFT;
2308 *p->usecs = w & RTL_COALESCE_MASK;
2311 for (i = 0; i < 2; i++) {
2312 p = coal_settings + i;
2313 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000;
2316 * ethtool_coalesce says it is illegal to set both usecs and
2319 if (!*p->usecs && !*p->max_frames)
2326 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */
2327 static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale(
2328 struct net_device *dev, u32 nsec, u16 *cp01)
2330 const struct rtl_coalesce_info *ci;
2333 ci = rtl_coalesce_info(dev);
2335 return ERR_CAST(ci);
2337 for (i = 0; i < 4; i++) {
2338 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0],
2339 ci->scalev[i].nsecs[1]);
2340 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) {
2342 return &ci->scalev[i];
2346 return ERR_PTR(-EINVAL);
2349 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
2351 struct rtl8169_private *tp = netdev_priv(dev);
2352 const struct rtl_coalesce_scale *scale;
2356 } coal_settings [] = {
2357 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs },
2358 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs }
2359 }, *p = coal_settings;
2363 scale = rtl_coalesce_choose_scale(dev,
2364 max(p[0].usecs, p[1].usecs) * 1000, &cp01);
2366 return PTR_ERR(scale);
2368 for (i = 0; i < 2; i++, p++) {
2372 * accept max_frames=1 we returned in rtl_get_coalesce.
2373 * accept it not only when usecs=0 because of e.g. the following scenario:
2375 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
2376 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
2377 * - then user does `ethtool -C eth0 rx-usecs 100`
2379 * since ethtool sends to kernel whole ethtool_coalesce
2380 * settings, if we do not handle rx_usecs=!0, rx_frames=1
2381 * we'll reject it below in `frames % 4 != 0`.
2383 if (p->frames == 1) {
2387 units = p->usecs * 1000 / scale->nsecs[i];
2388 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4)
2391 w <<= RTL_COALESCE_SHIFT;
2393 w <<= RTL_COALESCE_SHIFT;
2394 w |= p->frames >> 2;
2399 RTL_W16(tp, IntrMitigate, swab16(w));
2401 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
2402 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
2403 RTL_R16(tp, CPlusCmd);
2405 rtl_unlock_work(tp);
2410 static const struct ethtool_ops rtl8169_ethtool_ops = {
2411 .get_drvinfo = rtl8169_get_drvinfo,
2412 .get_regs_len = rtl8169_get_regs_len,
2413 .get_link = ethtool_op_get_link,
2414 .get_coalesce = rtl_get_coalesce,
2415 .set_coalesce = rtl_set_coalesce,
2416 .get_msglevel = rtl8169_get_msglevel,
2417 .set_msglevel = rtl8169_set_msglevel,
2418 .get_regs = rtl8169_get_regs,
2419 .get_wol = rtl8169_get_wol,
2420 .set_wol = rtl8169_set_wol,
2421 .get_strings = rtl8169_get_strings,
2422 .get_sset_count = rtl8169_get_sset_count,
2423 .get_ethtool_stats = rtl8169_get_ethtool_stats,
2424 .get_ts_info = ethtool_op_get_ts_info,
2425 .nway_reset = rtl8169_nway_reset,
2426 .get_link_ksettings = rtl8169_get_link_ksettings,
2427 .set_link_ksettings = rtl8169_set_link_ksettings,
2430 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
2434 * The driver currently handles the 8168Bf and the 8168Be identically
2435 * but they can be identified more specifically through the test below
2438 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2440 * Same thing for the 8101Eb and the 8101Ec:
2442 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2444 static const struct rtl_mac_info {
2449 /* 8168EP family. */
2450 { 0x7cf00000, 0x50200000, RTL_GIGA_MAC_VER_51 },
2451 { 0x7cf00000, 0x50100000, RTL_GIGA_MAC_VER_50 },
2452 { 0x7cf00000, 0x50000000, RTL_GIGA_MAC_VER_49 },
2455 { 0x7cf00000, 0x54100000, RTL_GIGA_MAC_VER_46 },
2456 { 0x7cf00000, 0x54000000, RTL_GIGA_MAC_VER_45 },
2459 { 0x7cf00000, 0x5c800000, RTL_GIGA_MAC_VER_44 },
2460 { 0x7cf00000, 0x50900000, RTL_GIGA_MAC_VER_42 },
2461 { 0x7cf00000, 0x4c100000, RTL_GIGA_MAC_VER_41 },
2462 { 0x7cf00000, 0x4c000000, RTL_GIGA_MAC_VER_40 },
2465 { 0x7c800000, 0x48800000, RTL_GIGA_MAC_VER_38 },
2466 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 },
2467 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 },
2470 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
2471 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
2472 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
2475 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
2476 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
2478 /* 8168DP family. */
2479 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
2480 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
2481 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
2484 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
2485 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
2486 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
2487 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
2488 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
2489 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
2490 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
2493 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
2494 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
2495 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
2498 { 0x7c800000, 0x44800000, RTL_GIGA_MAC_VER_39 },
2499 { 0x7c800000, 0x44000000, RTL_GIGA_MAC_VER_37 },
2500 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
2501 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
2502 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
2503 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
2504 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
2505 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
2506 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2507 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
2508 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2509 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
2510 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
2511 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
2512 /* FIXME: where did these entries come from ? -- FR */
2513 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
2514 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
2517 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
2518 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
2519 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
2520 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
2521 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
2522 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
2525 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
2527 const struct rtl_mac_info *p = mac_info;
2530 reg = RTL_R32(tp, TxConfig);
2531 while ((reg & p->mask) != p->val)
2533 tp->mac_version = p->mac_version;
2535 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2536 dev_notice(tp_to_dev(tp),
2537 "unknown MAC, using family default\n");
2538 tp->mac_version = default_version;
2539 } else if (tp->mac_version == RTL_GIGA_MAC_VER_42) {
2540 tp->mac_version = tp->mii.supports_gmii ?
2541 RTL_GIGA_MAC_VER_42 :
2542 RTL_GIGA_MAC_VER_43;
2543 } else if (tp->mac_version == RTL_GIGA_MAC_VER_45) {
2544 tp->mac_version = tp->mii.supports_gmii ?
2545 RTL_GIGA_MAC_VER_45 :
2546 RTL_GIGA_MAC_VER_47;
2547 } else if (tp->mac_version == RTL_GIGA_MAC_VER_46) {
2548 tp->mac_version = tp->mii.supports_gmii ?
2549 RTL_GIGA_MAC_VER_46 :
2550 RTL_GIGA_MAC_VER_48;
2554 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2556 dprintk("mac_version = 0x%02x\n", tp->mac_version);
2564 static void rtl_writephy_batch(struct rtl8169_private *tp,
2565 const struct phy_reg *regs, int len)
2568 rtl_writephy(tp, regs->reg, regs->val);
2573 #define PHY_READ 0x00000000
2574 #define PHY_DATA_OR 0x10000000
2575 #define PHY_DATA_AND 0x20000000
2576 #define PHY_BJMPN 0x30000000
2577 #define PHY_MDIO_CHG 0x40000000
2578 #define PHY_CLEAR_READCOUNT 0x70000000
2579 #define PHY_WRITE 0x80000000
2580 #define PHY_READCOUNT_EQ_SKIP 0x90000000
2581 #define PHY_COMP_EQ_SKIPN 0xa0000000
2582 #define PHY_COMP_NEQ_SKIPN 0xb0000000
2583 #define PHY_WRITE_PREVIOUS 0xc0000000
2584 #define PHY_SKIPN 0xd0000000
2585 #define PHY_DELAY_MS 0xe0000000
2589 char version[RTL_VER_SIZE];
2595 #define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2597 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2599 const struct firmware *fw = rtl_fw->fw;
2600 struct fw_info *fw_info = (struct fw_info *)fw->data;
2601 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2602 char *version = rtl_fw->version;
2605 if (fw->size < FW_OPCODE_SIZE)
2608 if (!fw_info->magic) {
2609 size_t i, size, start;
2612 if (fw->size < sizeof(*fw_info))
2615 for (i = 0; i < fw->size; i++)
2616 checksum += fw->data[i];
2620 start = le32_to_cpu(fw_info->fw_start);
2621 if (start > fw->size)
2624 size = le32_to_cpu(fw_info->fw_len);
2625 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2628 memcpy(version, fw_info->version, RTL_VER_SIZE);
2630 pa->code = (__le32 *)(fw->data + start);
2633 if (fw->size % FW_OPCODE_SIZE)
2636 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2638 pa->code = (__le32 *)fw->data;
2639 pa->size = fw->size / FW_OPCODE_SIZE;
2641 version[RTL_VER_SIZE - 1] = 0;
2648 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2649 struct rtl_fw_phy_action *pa)
2654 for (index = 0; index < pa->size; index++) {
2655 u32 action = le32_to_cpu(pa->code[index]);
2656 u32 regno = (action & 0x0fff0000) >> 16;
2658 switch(action & 0xf0000000) {
2663 case PHY_CLEAR_READCOUNT:
2665 case PHY_WRITE_PREVIOUS:
2670 if (regno > index) {
2671 netif_err(tp, ifup, tp->dev,
2672 "Out of range of firmware\n");
2676 case PHY_READCOUNT_EQ_SKIP:
2677 if (index + 2 >= pa->size) {
2678 netif_err(tp, ifup, tp->dev,
2679 "Out of range of firmware\n");
2683 case PHY_COMP_EQ_SKIPN:
2684 case PHY_COMP_NEQ_SKIPN:
2686 if (index + 1 + regno >= pa->size) {
2687 netif_err(tp, ifup, tp->dev,
2688 "Out of range of firmware\n");
2694 netif_err(tp, ifup, tp->dev,
2695 "Invalid action 0x%08x\n", action);
2704 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2706 struct net_device *dev = tp->dev;
2709 if (!rtl_fw_format_ok(tp, rtl_fw)) {
2710 netif_err(tp, ifup, dev, "invalid firmware\n");
2714 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2720 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2722 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2723 struct mdio_ops org, *ops = &tp->mdio_ops;
2727 predata = count = 0;
2728 org.write = ops->write;
2729 org.read = ops->read;
2731 for (index = 0; index < pa->size; ) {
2732 u32 action = le32_to_cpu(pa->code[index]);
2733 u32 data = action & 0x0000ffff;
2734 u32 regno = (action & 0x0fff0000) >> 16;
2739 switch(action & 0xf0000000) {
2741 predata = rtl_readphy(tp, regno);
2758 ops->write = org.write;
2759 ops->read = org.read;
2760 } else if (data == 1) {
2761 ops->write = mac_mcu_write;
2762 ops->read = mac_mcu_read;
2767 case PHY_CLEAR_READCOUNT:
2772 rtl_writephy(tp, regno, data);
2775 case PHY_READCOUNT_EQ_SKIP:
2776 index += (count == data) ? 2 : 1;
2778 case PHY_COMP_EQ_SKIPN:
2779 if (predata == data)
2783 case PHY_COMP_NEQ_SKIPN:
2784 if (predata != data)
2788 case PHY_WRITE_PREVIOUS:
2789 rtl_writephy(tp, regno, predata);
2805 ops->write = org.write;
2806 ops->read = org.read;
2809 static void rtl_release_firmware(struct rtl8169_private *tp)
2811 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2812 release_firmware(tp->rtl_fw->fw);
2815 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2818 static void rtl_apply_firmware(struct rtl8169_private *tp)
2820 struct rtl_fw *rtl_fw = tp->rtl_fw;
2822 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2823 if (!IS_ERR_OR_NULL(rtl_fw))
2824 rtl_phy_write_fw(tp, rtl_fw);
2827 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2829 if (rtl_readphy(tp, reg) != val)
2830 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2832 rtl_apply_firmware(tp);
2835 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2837 static const struct phy_reg phy_reg_init[] = {
2899 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2902 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2904 static const struct phy_reg phy_reg_init[] = {
2910 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2913 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2915 struct pci_dev *pdev = tp->pci_dev;
2917 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2918 (pdev->subsystem_device != 0xe000))
2921 rtl_writephy(tp, 0x1f, 0x0001);
2922 rtl_writephy(tp, 0x10, 0xf01b);
2923 rtl_writephy(tp, 0x1f, 0x0000);
2926 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2928 static const struct phy_reg phy_reg_init[] = {
2968 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2970 rtl8169scd_hw_phy_config_quirk(tp);
2973 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2975 static const struct phy_reg phy_reg_init[] = {
3023 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3026 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
3028 static const struct phy_reg phy_reg_init[] = {
3033 rtl_writephy(tp, 0x1f, 0x0001);
3034 rtl_patchphy(tp, 0x16, 1 << 0);
3036 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3039 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
3041 static const struct phy_reg phy_reg_init[] = {
3047 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3050 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
3052 static const struct phy_reg phy_reg_init[] = {
3060 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3063 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
3065 static const struct phy_reg phy_reg_init[] = {
3071 rtl_writephy(tp, 0x1f, 0x0000);
3072 rtl_patchphy(tp, 0x14, 1 << 5);
3073 rtl_patchphy(tp, 0x0d, 1 << 5);
3075 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3078 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
3080 static const struct phy_reg phy_reg_init[] = {
3100 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3102 rtl_patchphy(tp, 0x14, 1 << 5);
3103 rtl_patchphy(tp, 0x0d, 1 << 5);
3104 rtl_writephy(tp, 0x1f, 0x0000);
3107 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
3109 static const struct phy_reg phy_reg_init[] = {
3127 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3129 rtl_patchphy(tp, 0x16, 1 << 0);
3130 rtl_patchphy(tp, 0x14, 1 << 5);
3131 rtl_patchphy(tp, 0x0d, 1 << 5);
3132 rtl_writephy(tp, 0x1f, 0x0000);
3135 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
3137 static const struct phy_reg phy_reg_init[] = {
3149 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3151 rtl_patchphy(tp, 0x16, 1 << 0);
3152 rtl_patchphy(tp, 0x14, 1 << 5);
3153 rtl_patchphy(tp, 0x0d, 1 << 5);
3154 rtl_writephy(tp, 0x1f, 0x0000);
3157 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
3159 rtl8168c_3_hw_phy_config(tp);
3162 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
3164 static const struct phy_reg phy_reg_init_0[] = {
3165 /* Channel Estimation */
3186 * Enhance line driver power
3195 * Can not link to 1Gbps with bad cable
3196 * Decrease SNR threshold form 21.07dB to 19.04dB
3205 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
3209 * Fine Tune Switching regulator parameter
3211 rtl_writephy(tp, 0x1f, 0x0002);
3212 rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
3213 rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
3215 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
3216 static const struct phy_reg phy_reg_init[] = {
3226 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3228 val = rtl_readphy(tp, 0x0d);
3230 if ((val & 0x00ff) != 0x006c) {
3231 static const u32 set[] = {
3232 0x0065, 0x0066, 0x0067, 0x0068,
3233 0x0069, 0x006a, 0x006b, 0x006c
3237 rtl_writephy(tp, 0x1f, 0x0002);
3240 for (i = 0; i < ARRAY_SIZE(set); i++)
3241 rtl_writephy(tp, 0x0d, val | set[i]);
3244 static const struct phy_reg phy_reg_init[] = {
3252 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3255 /* RSET couple improve */
3256 rtl_writephy(tp, 0x1f, 0x0002);
3257 rtl_patchphy(tp, 0x0d, 0x0300);
3258 rtl_patchphy(tp, 0x0f, 0x0010);
3260 /* Fine tune PLL performance */
3261 rtl_writephy(tp, 0x1f, 0x0002);
3262 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3263 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3265 rtl_writephy(tp, 0x1f, 0x0005);
3266 rtl_writephy(tp, 0x05, 0x001b);
3268 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
3270 rtl_writephy(tp, 0x1f, 0x0000);
3273 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
3275 static const struct phy_reg phy_reg_init_0[] = {
3276 /* Channel Estimation */
3297 * Enhance line driver power
3306 * Can not link to 1Gbps with bad cable
3307 * Decrease SNR threshold form 21.07dB to 19.04dB
3316 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
3318 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
3319 static const struct phy_reg phy_reg_init[] = {
3330 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3332 val = rtl_readphy(tp, 0x0d);
3333 if ((val & 0x00ff) != 0x006c) {
3334 static const u32 set[] = {
3335 0x0065, 0x0066, 0x0067, 0x0068,
3336 0x0069, 0x006a, 0x006b, 0x006c
3340 rtl_writephy(tp, 0x1f, 0x0002);
3343 for (i = 0; i < ARRAY_SIZE(set); i++)
3344 rtl_writephy(tp, 0x0d, val | set[i]);
3347 static const struct phy_reg phy_reg_init[] = {
3355 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3358 /* Fine tune PLL performance */
3359 rtl_writephy(tp, 0x1f, 0x0002);
3360 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3361 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3363 /* Switching regulator Slew rate */
3364 rtl_writephy(tp, 0x1f, 0x0002);
3365 rtl_patchphy(tp, 0x0f, 0x0017);
3367 rtl_writephy(tp, 0x1f, 0x0005);
3368 rtl_writephy(tp, 0x05, 0x001b);
3370 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
3372 rtl_writephy(tp, 0x1f, 0x0000);
3375 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
3377 static const struct phy_reg phy_reg_init[] = {
3433 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3436 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3438 static const struct phy_reg phy_reg_init[] = {
3448 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3449 rtl_patchphy(tp, 0x0d, 1 << 5);
3452 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
3454 static const struct phy_reg phy_reg_init[] = {
3455 /* Enable Delay cap */
3461 /* Channel estimation fine tune */
3470 /* Update PFM & 10M TX idle timer */
3482 rtl_apply_firmware(tp);
3484 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3486 /* DCO enable for 10M IDLE Power */
3487 rtl_writephy(tp, 0x1f, 0x0007);
3488 rtl_writephy(tp, 0x1e, 0x0023);
3489 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3490 rtl_writephy(tp, 0x1f, 0x0000);
3492 /* For impedance matching */
3493 rtl_writephy(tp, 0x1f, 0x0002);
3494 rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
3495 rtl_writephy(tp, 0x1f, 0x0000);
3497 /* PHY auto speed down */
3498 rtl_writephy(tp, 0x1f, 0x0007);
3499 rtl_writephy(tp, 0x1e, 0x002d);
3500 rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
3501 rtl_writephy(tp, 0x1f, 0x0000);
3502 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3504 rtl_writephy(tp, 0x1f, 0x0005);
3505 rtl_writephy(tp, 0x05, 0x8b86);
3506 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3507 rtl_writephy(tp, 0x1f, 0x0000);
3509 rtl_writephy(tp, 0x1f, 0x0005);
3510 rtl_writephy(tp, 0x05, 0x8b85);
3511 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3512 rtl_writephy(tp, 0x1f, 0x0007);
3513 rtl_writephy(tp, 0x1e, 0x0020);
3514 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
3515 rtl_writephy(tp, 0x1f, 0x0006);
3516 rtl_writephy(tp, 0x00, 0x5a00);
3517 rtl_writephy(tp, 0x1f, 0x0000);
3518 rtl_writephy(tp, 0x0d, 0x0007);
3519 rtl_writephy(tp, 0x0e, 0x003c);
3520 rtl_writephy(tp, 0x0d, 0x4007);
3521 rtl_writephy(tp, 0x0e, 0x0000);
3522 rtl_writephy(tp, 0x0d, 0x0000);
3525 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3528 addr[0] | (addr[1] << 8),
3529 addr[2] | (addr[3] << 8),
3530 addr[4] | (addr[5] << 8)
3532 const struct exgmac_reg e[] = {
3533 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3534 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3535 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3536 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3539 rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3542 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3544 static const struct phy_reg phy_reg_init[] = {
3545 /* Enable Delay cap */
3554 /* Channel estimation fine tune */
3571 rtl_apply_firmware(tp);
3573 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3575 /* For 4-corner performance improve */
3576 rtl_writephy(tp, 0x1f, 0x0005);
3577 rtl_writephy(tp, 0x05, 0x8b80);
3578 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3579 rtl_writephy(tp, 0x1f, 0x0000);
3581 /* PHY auto speed down */
3582 rtl_writephy(tp, 0x1f, 0x0004);
3583 rtl_writephy(tp, 0x1f, 0x0007);
3584 rtl_writephy(tp, 0x1e, 0x002d);
3585 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3586 rtl_writephy(tp, 0x1f, 0x0002);
3587 rtl_writephy(tp, 0x1f, 0x0000);
3588 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3590 /* improve 10M EEE waveform */
3591 rtl_writephy(tp, 0x1f, 0x0005);
3592 rtl_writephy(tp, 0x05, 0x8b86);
3593 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3594 rtl_writephy(tp, 0x1f, 0x0000);
3596 /* Improve 2-pair detection performance */
3597 rtl_writephy(tp, 0x1f, 0x0005);
3598 rtl_writephy(tp, 0x05, 0x8b85);
3599 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3600 rtl_writephy(tp, 0x1f, 0x0000);
3603 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0003, 0x0000, ERIAR_EXGMAC);
3604 rtl_writephy(tp, 0x1f, 0x0005);
3605 rtl_writephy(tp, 0x05, 0x8b85);
3606 rtl_w0w1_phy(tp, 0x06, 0x2000, 0x0000);
3607 rtl_writephy(tp, 0x1f, 0x0004);
3608 rtl_writephy(tp, 0x1f, 0x0007);
3609 rtl_writephy(tp, 0x1e, 0x0020);
3610 rtl_w0w1_phy(tp, 0x15, 0x0100, 0x0000);
3611 rtl_writephy(tp, 0x1f, 0x0002);
3612 rtl_writephy(tp, 0x1f, 0x0000);
3613 rtl_writephy(tp, 0x0d, 0x0007);
3614 rtl_writephy(tp, 0x0e, 0x003c);
3615 rtl_writephy(tp, 0x0d, 0x4007);
3616 rtl_writephy(tp, 0x0e, 0x0006);
3617 rtl_writephy(tp, 0x0d, 0x0000);
3620 rtl_writephy(tp, 0x1f, 0x0003);
3621 rtl_w0w1_phy(tp, 0x19, 0x0001, 0x0000);
3622 rtl_w0w1_phy(tp, 0x10, 0x0400, 0x0000);
3623 rtl_writephy(tp, 0x1f, 0x0000);
3624 rtl_writephy(tp, 0x1f, 0x0005);
3625 rtl_w0w1_phy(tp, 0x01, 0x0100, 0x0000);
3626 rtl_writephy(tp, 0x1f, 0x0000);
3628 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3629 rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3632 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3634 /* For 4-corner performance improve */
3635 rtl_writephy(tp, 0x1f, 0x0005);
3636 rtl_writephy(tp, 0x05, 0x8b80);
3637 rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
3638 rtl_writephy(tp, 0x1f, 0x0000);
3640 /* PHY auto speed down */
3641 rtl_writephy(tp, 0x1f, 0x0007);
3642 rtl_writephy(tp, 0x1e, 0x002d);
3643 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3644 rtl_writephy(tp, 0x1f, 0x0000);
3645 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3647 /* Improve 10M EEE waveform */
3648 rtl_writephy(tp, 0x1f, 0x0005);
3649 rtl_writephy(tp, 0x05, 0x8b86);
3650 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3651 rtl_writephy(tp, 0x1f, 0x0000);
3654 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3656 static const struct phy_reg phy_reg_init[] = {
3657 /* Channel estimation fine tune */
3662 /* Modify green table for giga & fnet */
3679 /* Modify green table for 10M */
3685 /* Disable hiimpedance detection (RTCT) */
3691 rtl_apply_firmware(tp);
3693 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3695 rtl8168f_hw_phy_config(tp);
3697 /* Improve 2-pair detection performance */
3698 rtl_writephy(tp, 0x1f, 0x0005);
3699 rtl_writephy(tp, 0x05, 0x8b85);
3700 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3701 rtl_writephy(tp, 0x1f, 0x0000);
3704 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3706 rtl_apply_firmware(tp);
3708 rtl8168f_hw_phy_config(tp);
3711 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3713 static const struct phy_reg phy_reg_init[] = {
3714 /* Channel estimation fine tune */
3719 /* Modify green table for giga & fnet */
3736 /* Modify green table for 10M */
3742 /* Disable hiimpedance detection (RTCT) */
3749 rtl_apply_firmware(tp);
3751 rtl8168f_hw_phy_config(tp);
3753 /* Improve 2-pair detection performance */
3754 rtl_writephy(tp, 0x1f, 0x0005);
3755 rtl_writephy(tp, 0x05, 0x8b85);
3756 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3757 rtl_writephy(tp, 0x1f, 0x0000);
3759 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3761 /* Modify green table for giga */
3762 rtl_writephy(tp, 0x1f, 0x0005);
3763 rtl_writephy(tp, 0x05, 0x8b54);
3764 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3765 rtl_writephy(tp, 0x05, 0x8b5d);
3766 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3767 rtl_writephy(tp, 0x05, 0x8a7c);
3768 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3769 rtl_writephy(tp, 0x05, 0x8a7f);
3770 rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
3771 rtl_writephy(tp, 0x05, 0x8a82);
3772 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3773 rtl_writephy(tp, 0x05, 0x8a85);
3774 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3775 rtl_writephy(tp, 0x05, 0x8a88);
3776 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3777 rtl_writephy(tp, 0x1f, 0x0000);
3779 /* uc same-seed solution */
3780 rtl_writephy(tp, 0x1f, 0x0005);
3781 rtl_writephy(tp, 0x05, 0x8b85);
3782 rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
3783 rtl_writephy(tp, 0x1f, 0x0000);
3786 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
3787 rtl_writephy(tp, 0x1f, 0x0005);
3788 rtl_writephy(tp, 0x05, 0x8b85);
3789 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3790 rtl_writephy(tp, 0x1f, 0x0004);
3791 rtl_writephy(tp, 0x1f, 0x0007);
3792 rtl_writephy(tp, 0x1e, 0x0020);
3793 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
3794 rtl_writephy(tp, 0x1f, 0x0000);
3795 rtl_writephy(tp, 0x0d, 0x0007);
3796 rtl_writephy(tp, 0x0e, 0x003c);
3797 rtl_writephy(tp, 0x0d, 0x4007);
3798 rtl_writephy(tp, 0x0e, 0x0000);
3799 rtl_writephy(tp, 0x0d, 0x0000);
3802 rtl_writephy(tp, 0x1f, 0x0003);
3803 rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3804 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3805 rtl_writephy(tp, 0x1f, 0x0000);
3808 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3810 rtl_apply_firmware(tp);
3812 rtl_writephy(tp, 0x1f, 0x0a46);
3813 if (rtl_readphy(tp, 0x10) & 0x0100) {
3814 rtl_writephy(tp, 0x1f, 0x0bcc);
3815 rtl_w0w1_phy(tp, 0x12, 0x0000, 0x8000);
3817 rtl_writephy(tp, 0x1f, 0x0bcc);
3818 rtl_w0w1_phy(tp, 0x12, 0x8000, 0x0000);
3821 rtl_writephy(tp, 0x1f, 0x0a46);
3822 if (rtl_readphy(tp, 0x13) & 0x0100) {
3823 rtl_writephy(tp, 0x1f, 0x0c41);
3824 rtl_w0w1_phy(tp, 0x15, 0x0002, 0x0000);
3826 rtl_writephy(tp, 0x1f, 0x0c41);
3827 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0002);
3830 /* Enable PHY auto speed down */
3831 rtl_writephy(tp, 0x1f, 0x0a44);
3832 rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3834 rtl_writephy(tp, 0x1f, 0x0bcc);
3835 rtl_w0w1_phy(tp, 0x14, 0x0100, 0x0000);
3836 rtl_writephy(tp, 0x1f, 0x0a44);
3837 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3838 rtl_writephy(tp, 0x1f, 0x0a43);
3839 rtl_writephy(tp, 0x13, 0x8084);
3840 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3841 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3843 /* EEE auto-fallback function */
3844 rtl_writephy(tp, 0x1f, 0x0a4b);
3845 rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3847 /* Enable UC LPF tune function */
3848 rtl_writephy(tp, 0x1f, 0x0a43);
3849 rtl_writephy(tp, 0x13, 0x8012);
3850 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3852 rtl_writephy(tp, 0x1f, 0x0c42);
3853 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3855 /* Improve SWR Efficiency */
3856 rtl_writephy(tp, 0x1f, 0x0bcd);
3857 rtl_writephy(tp, 0x14, 0x5065);
3858 rtl_writephy(tp, 0x14, 0xd065);
3859 rtl_writephy(tp, 0x1f, 0x0bc8);
3860 rtl_writephy(tp, 0x11, 0x5655);
3861 rtl_writephy(tp, 0x1f, 0x0bcd);
3862 rtl_writephy(tp, 0x14, 0x1065);
3863 rtl_writephy(tp, 0x14, 0x9065);
3864 rtl_writephy(tp, 0x14, 0x1065);
3866 /* Check ALDPS bit, disable it if enabled */
3867 rtl_writephy(tp, 0x1f, 0x0a43);
3868 if (rtl_readphy(tp, 0x10) & 0x0004)
3869 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3871 rtl_writephy(tp, 0x1f, 0x0000);
3874 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3876 rtl_apply_firmware(tp);
3879 static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3884 rtl_apply_firmware(tp);
3886 /* CHN EST parameters adjust - giga master */
3887 rtl_writephy(tp, 0x1f, 0x0a43);
3888 rtl_writephy(tp, 0x13, 0x809b);
3889 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
3890 rtl_writephy(tp, 0x13, 0x80a2);
3891 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
3892 rtl_writephy(tp, 0x13, 0x80a4);
3893 rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
3894 rtl_writephy(tp, 0x13, 0x809c);
3895 rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
3896 rtl_writephy(tp, 0x1f, 0x0000);
3898 /* CHN EST parameters adjust - giga slave */
3899 rtl_writephy(tp, 0x1f, 0x0a43);
3900 rtl_writephy(tp, 0x13, 0x80ad);
3901 rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
3902 rtl_writephy(tp, 0x13, 0x80b4);
3903 rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
3904 rtl_writephy(tp, 0x13, 0x80ac);
3905 rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
3906 rtl_writephy(tp, 0x1f, 0x0000);
3908 /* CHN EST parameters adjust - fnet */
3909 rtl_writephy(tp, 0x1f, 0x0a43);
3910 rtl_writephy(tp, 0x13, 0x808e);
3911 rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
3912 rtl_writephy(tp, 0x13, 0x8090);
3913 rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
3914 rtl_writephy(tp, 0x13, 0x8092);
3915 rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
3916 rtl_writephy(tp, 0x1f, 0x0000);
3918 /* enable R-tune & PGA-retune function */
3920 rtl_writephy(tp, 0x1f, 0x0a46);
3921 data = rtl_readphy(tp, 0x13);
3924 dout_tapbin |= data;
3925 data = rtl_readphy(tp, 0x12);
3928 dout_tapbin |= data;
3929 dout_tapbin = ~(dout_tapbin^0x08);
3931 dout_tapbin &= 0xf000;
3932 rtl_writephy(tp, 0x1f, 0x0a43);
3933 rtl_writephy(tp, 0x13, 0x827a);
3934 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3935 rtl_writephy(tp, 0x13, 0x827b);
3936 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3937 rtl_writephy(tp, 0x13, 0x827c);
3938 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3939 rtl_writephy(tp, 0x13, 0x827d);
3940 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3942 rtl_writephy(tp, 0x1f, 0x0a43);
3943 rtl_writephy(tp, 0x13, 0x0811);
3944 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3945 rtl_writephy(tp, 0x1f, 0x0a42);
3946 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3947 rtl_writephy(tp, 0x1f, 0x0000);
3949 /* enable GPHY 10M */
3950 rtl_writephy(tp, 0x1f, 0x0a44);
3951 rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3952 rtl_writephy(tp, 0x1f, 0x0000);
3954 /* SAR ADC performance */
3955 rtl_writephy(tp, 0x1f, 0x0bca);
3956 rtl_w0w1_phy(tp, 0x17, 0x4000, 0x3000);
3957 rtl_writephy(tp, 0x1f, 0x0000);
3959 rtl_writephy(tp, 0x1f, 0x0a43);
3960 rtl_writephy(tp, 0x13, 0x803f);
3961 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3962 rtl_writephy(tp, 0x13, 0x8047);
3963 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3964 rtl_writephy(tp, 0x13, 0x804f);
3965 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3966 rtl_writephy(tp, 0x13, 0x8057);
3967 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3968 rtl_writephy(tp, 0x13, 0x805f);
3969 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3970 rtl_writephy(tp, 0x13, 0x8067);
3971 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3972 rtl_writephy(tp, 0x13, 0x806f);
3973 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3974 rtl_writephy(tp, 0x1f, 0x0000);
3976 /* disable phy pfm mode */
3977 rtl_writephy(tp, 0x1f, 0x0a44);
3978 rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
3979 rtl_writephy(tp, 0x1f, 0x0000);
3981 /* Check ALDPS bit, disable it if enabled */
3982 rtl_writephy(tp, 0x1f, 0x0a43);
3983 if (rtl_readphy(tp, 0x10) & 0x0004)
3984 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3986 rtl_writephy(tp, 0x1f, 0x0000);
3989 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3991 u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3995 rtl_apply_firmware(tp);
3997 /* CHIN EST parameter update */
3998 rtl_writephy(tp, 0x1f, 0x0a43);
3999 rtl_writephy(tp, 0x13, 0x808a);
4000 rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
4001 rtl_writephy(tp, 0x1f, 0x0000);
4003 /* enable R-tune & PGA-retune function */
4004 rtl_writephy(tp, 0x1f, 0x0a43);
4005 rtl_writephy(tp, 0x13, 0x0811);
4006 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
4007 rtl_writephy(tp, 0x1f, 0x0a42);
4008 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
4009 rtl_writephy(tp, 0x1f, 0x0000);
4011 /* enable GPHY 10M */
4012 rtl_writephy(tp, 0x1f, 0x0a44);
4013 rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
4014 rtl_writephy(tp, 0x1f, 0x0000);
4016 r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
4017 data = r8168_mac_ocp_read(tp, 0xdd02);
4018 ioffset_p3 = ((data & 0x80)>>7);
4021 data = r8168_mac_ocp_read(tp, 0xdd00);
4022 ioffset_p3 |= ((data & (0xe000))>>13);
4023 ioffset_p2 = ((data & (0x1e00))>>9);
4024 ioffset_p1 = ((data & (0x01e0))>>5);
4025 ioffset_p0 = ((data & 0x0010)>>4);
4027 ioffset_p0 |= (data & (0x07));
4028 data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
4030 if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
4031 (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) {
4032 rtl_writephy(tp, 0x1f, 0x0bcf);
4033 rtl_writephy(tp, 0x16, data);
4034 rtl_writephy(tp, 0x1f, 0x0000);
4037 /* Modify rlen (TX LPF corner frequency) level */
4038 rtl_writephy(tp, 0x1f, 0x0bcd);
4039 data = rtl_readphy(tp, 0x16);
4044 data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
4045 rtl_writephy(tp, 0x17, data);
4046 rtl_writephy(tp, 0x1f, 0x0bcd);
4047 rtl_writephy(tp, 0x1f, 0x0000);
4049 /* disable phy pfm mode */
4050 rtl_writephy(tp, 0x1f, 0x0a44);
4051 rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
4052 rtl_writephy(tp, 0x1f, 0x0000);
4054 /* Check ALDPS bit, disable it if enabled */
4055 rtl_writephy(tp, 0x1f, 0x0a43);
4056 if (rtl_readphy(tp, 0x10) & 0x0004)
4057 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4059 rtl_writephy(tp, 0x1f, 0x0000);
4062 static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
4064 /* Enable PHY auto speed down */
4065 rtl_writephy(tp, 0x1f, 0x0a44);
4066 rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
4067 rtl_writephy(tp, 0x1f, 0x0000);
4069 /* patch 10M & ALDPS */
4070 rtl_writephy(tp, 0x1f, 0x0bcc);
4071 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
4072 rtl_writephy(tp, 0x1f, 0x0a44);
4073 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
4074 rtl_writephy(tp, 0x1f, 0x0a43);
4075 rtl_writephy(tp, 0x13, 0x8084);
4076 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
4077 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
4078 rtl_writephy(tp, 0x1f, 0x0000);
4080 /* Enable EEE auto-fallback function */
4081 rtl_writephy(tp, 0x1f, 0x0a4b);
4082 rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
4083 rtl_writephy(tp, 0x1f, 0x0000);
4085 /* Enable UC LPF tune function */
4086 rtl_writephy(tp, 0x1f, 0x0a43);
4087 rtl_writephy(tp, 0x13, 0x8012);
4088 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
4089 rtl_writephy(tp, 0x1f, 0x0000);
4091 /* set rg_sel_sdm_rate */
4092 rtl_writephy(tp, 0x1f, 0x0c42);
4093 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
4094 rtl_writephy(tp, 0x1f, 0x0000);
4096 /* Check ALDPS bit, disable it if enabled */
4097 rtl_writephy(tp, 0x1f, 0x0a43);
4098 if (rtl_readphy(tp, 0x10) & 0x0004)
4099 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4101 rtl_writephy(tp, 0x1f, 0x0000);
4104 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
4106 /* patch 10M & ALDPS */
4107 rtl_writephy(tp, 0x1f, 0x0bcc);
4108 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
4109 rtl_writephy(tp, 0x1f, 0x0a44);
4110 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
4111 rtl_writephy(tp, 0x1f, 0x0a43);
4112 rtl_writephy(tp, 0x13, 0x8084);
4113 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
4114 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
4115 rtl_writephy(tp, 0x1f, 0x0000);
4117 /* Enable UC LPF tune function */
4118 rtl_writephy(tp, 0x1f, 0x0a43);
4119 rtl_writephy(tp, 0x13, 0x8012);
4120 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
4121 rtl_writephy(tp, 0x1f, 0x0000);
4123 /* Set rg_sel_sdm_rate */
4124 rtl_writephy(tp, 0x1f, 0x0c42);
4125 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
4126 rtl_writephy(tp, 0x1f, 0x0000);
4128 /* Channel estimation parameters */
4129 rtl_writephy(tp, 0x1f, 0x0a43);
4130 rtl_writephy(tp, 0x13, 0x80f3);
4131 rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
4132 rtl_writephy(tp, 0x13, 0x80f0);
4133 rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
4134 rtl_writephy(tp, 0x13, 0x80ef);
4135 rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
4136 rtl_writephy(tp, 0x13, 0x80f6);
4137 rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
4138 rtl_writephy(tp, 0x13, 0x80ec);
4139 rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
4140 rtl_writephy(tp, 0x13, 0x80ed);
4141 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
4142 rtl_writephy(tp, 0x13, 0x80f2);
4143 rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
4144 rtl_writephy(tp, 0x13, 0x80f4);
4145 rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
4146 rtl_writephy(tp, 0x1f, 0x0a43);
4147 rtl_writephy(tp, 0x13, 0x8110);
4148 rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
4149 rtl_writephy(tp, 0x13, 0x810f);
4150 rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
4151 rtl_writephy(tp, 0x13, 0x8111);
4152 rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
4153 rtl_writephy(tp, 0x13, 0x8113);
4154 rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
4155 rtl_writephy(tp, 0x13, 0x8115);
4156 rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
4157 rtl_writephy(tp, 0x13, 0x810e);
4158 rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
4159 rtl_writephy(tp, 0x13, 0x810c);
4160 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
4161 rtl_writephy(tp, 0x13, 0x810b);
4162 rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
4163 rtl_writephy(tp, 0x1f, 0x0a43);
4164 rtl_writephy(tp, 0x13, 0x80d1);
4165 rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
4166 rtl_writephy(tp, 0x13, 0x80cd);
4167 rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
4168 rtl_writephy(tp, 0x13, 0x80d3);
4169 rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
4170 rtl_writephy(tp, 0x13, 0x80d5);
4171 rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
4172 rtl_writephy(tp, 0x13, 0x80d7);
4173 rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
4175 /* Force PWM-mode */
4176 rtl_writephy(tp, 0x1f, 0x0bcd);
4177 rtl_writephy(tp, 0x14, 0x5065);
4178 rtl_writephy(tp, 0x14, 0xd065);
4179 rtl_writephy(tp, 0x1f, 0x0bc8);
4180 rtl_writephy(tp, 0x12, 0x00ed);
4181 rtl_writephy(tp, 0x1f, 0x0bcd);
4182 rtl_writephy(tp, 0x14, 0x1065);
4183 rtl_writephy(tp, 0x14, 0x9065);
4184 rtl_writephy(tp, 0x14, 0x1065);
4185 rtl_writephy(tp, 0x1f, 0x0000);
4187 /* Check ALDPS bit, disable it if enabled */
4188 rtl_writephy(tp, 0x1f, 0x0a43);
4189 if (rtl_readphy(tp, 0x10) & 0x0004)
4190 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4192 rtl_writephy(tp, 0x1f, 0x0000);
4195 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
4197 static const struct phy_reg phy_reg_init[] = {
4204 rtl_writephy(tp, 0x1f, 0x0000);
4205 rtl_patchphy(tp, 0x11, 1 << 12);
4206 rtl_patchphy(tp, 0x19, 1 << 13);
4207 rtl_patchphy(tp, 0x10, 1 << 15);
4209 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4212 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
4214 static const struct phy_reg phy_reg_init[] = {
4228 /* Disable ALDPS before ram code */
4229 rtl_writephy(tp, 0x1f, 0x0000);
4230 rtl_writephy(tp, 0x18, 0x0310);
4233 rtl_apply_firmware(tp);
4235 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4238 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
4240 /* Disable ALDPS before setting firmware */
4241 rtl_writephy(tp, 0x1f, 0x0000);
4242 rtl_writephy(tp, 0x18, 0x0310);
4245 rtl_apply_firmware(tp);
4248 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4249 rtl_writephy(tp, 0x1f, 0x0004);
4250 rtl_writephy(tp, 0x10, 0x401f);
4251 rtl_writephy(tp, 0x19, 0x7030);
4252 rtl_writephy(tp, 0x1f, 0x0000);
4255 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
4257 static const struct phy_reg phy_reg_init[] = {
4264 /* Disable ALDPS before ram code */
4265 rtl_writephy(tp, 0x1f, 0x0000);
4266 rtl_writephy(tp, 0x18, 0x0310);
4269 rtl_apply_firmware(tp);
4271 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4272 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4274 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4277 static void rtl_hw_phy_config(struct net_device *dev)
4279 struct rtl8169_private *tp = netdev_priv(dev);
4281 rtl8169_print_mac_version(tp);
4283 switch (tp->mac_version) {
4284 case RTL_GIGA_MAC_VER_01:
4286 case RTL_GIGA_MAC_VER_02:
4287 case RTL_GIGA_MAC_VER_03:
4288 rtl8169s_hw_phy_config(tp);
4290 case RTL_GIGA_MAC_VER_04:
4291 rtl8169sb_hw_phy_config(tp);
4293 case RTL_GIGA_MAC_VER_05:
4294 rtl8169scd_hw_phy_config(tp);
4296 case RTL_GIGA_MAC_VER_06:
4297 rtl8169sce_hw_phy_config(tp);
4299 case RTL_GIGA_MAC_VER_07:
4300 case RTL_GIGA_MAC_VER_08:
4301 case RTL_GIGA_MAC_VER_09:
4302 rtl8102e_hw_phy_config(tp);
4304 case RTL_GIGA_MAC_VER_11:
4305 rtl8168bb_hw_phy_config(tp);
4307 case RTL_GIGA_MAC_VER_12:
4308 rtl8168bef_hw_phy_config(tp);
4310 case RTL_GIGA_MAC_VER_17:
4311 rtl8168bef_hw_phy_config(tp);
4313 case RTL_GIGA_MAC_VER_18:
4314 rtl8168cp_1_hw_phy_config(tp);
4316 case RTL_GIGA_MAC_VER_19:
4317 rtl8168c_1_hw_phy_config(tp);
4319 case RTL_GIGA_MAC_VER_20:
4320 rtl8168c_2_hw_phy_config(tp);
4322 case RTL_GIGA_MAC_VER_21:
4323 rtl8168c_3_hw_phy_config(tp);
4325 case RTL_GIGA_MAC_VER_22:
4326 rtl8168c_4_hw_phy_config(tp);
4328 case RTL_GIGA_MAC_VER_23:
4329 case RTL_GIGA_MAC_VER_24:
4330 rtl8168cp_2_hw_phy_config(tp);
4332 case RTL_GIGA_MAC_VER_25:
4333 rtl8168d_1_hw_phy_config(tp);
4335 case RTL_GIGA_MAC_VER_26:
4336 rtl8168d_2_hw_phy_config(tp);
4338 case RTL_GIGA_MAC_VER_27:
4339 rtl8168d_3_hw_phy_config(tp);
4341 case RTL_GIGA_MAC_VER_28:
4342 rtl8168d_4_hw_phy_config(tp);
4344 case RTL_GIGA_MAC_VER_29:
4345 case RTL_GIGA_MAC_VER_30:
4346 rtl8105e_hw_phy_config(tp);
4348 case RTL_GIGA_MAC_VER_31:
4351 case RTL_GIGA_MAC_VER_32:
4352 case RTL_GIGA_MAC_VER_33:
4353 rtl8168e_1_hw_phy_config(tp);
4355 case RTL_GIGA_MAC_VER_34:
4356 rtl8168e_2_hw_phy_config(tp);
4358 case RTL_GIGA_MAC_VER_35:
4359 rtl8168f_1_hw_phy_config(tp);
4361 case RTL_GIGA_MAC_VER_36:
4362 rtl8168f_2_hw_phy_config(tp);
4365 case RTL_GIGA_MAC_VER_37:
4366 rtl8402_hw_phy_config(tp);
4369 case RTL_GIGA_MAC_VER_38:
4370 rtl8411_hw_phy_config(tp);
4373 case RTL_GIGA_MAC_VER_39:
4374 rtl8106e_hw_phy_config(tp);
4377 case RTL_GIGA_MAC_VER_40:
4378 rtl8168g_1_hw_phy_config(tp);
4380 case RTL_GIGA_MAC_VER_42:
4381 case RTL_GIGA_MAC_VER_43:
4382 case RTL_GIGA_MAC_VER_44:
4383 rtl8168g_2_hw_phy_config(tp);
4385 case RTL_GIGA_MAC_VER_45:
4386 case RTL_GIGA_MAC_VER_47:
4387 rtl8168h_1_hw_phy_config(tp);
4389 case RTL_GIGA_MAC_VER_46:
4390 case RTL_GIGA_MAC_VER_48:
4391 rtl8168h_2_hw_phy_config(tp);
4394 case RTL_GIGA_MAC_VER_49:
4395 rtl8168ep_1_hw_phy_config(tp);
4397 case RTL_GIGA_MAC_VER_50:
4398 case RTL_GIGA_MAC_VER_51:
4399 rtl8168ep_2_hw_phy_config(tp);
4402 case RTL_GIGA_MAC_VER_41:
4408 static void rtl_phy_work(struct rtl8169_private *tp)
4410 struct timer_list *timer = &tp->timer;
4411 unsigned long timeout = RTL8169_PHY_TIMEOUT;
4413 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
4415 if (tp->phy_reset_pending(tp)) {
4417 * A busy loop could burn quite a few cycles on nowadays CPU.
4418 * Let's delay the execution of the timer for a few ticks.
4424 if (tp->link_ok(tp))
4427 netif_dbg(tp, link, tp->dev, "PHY reset until link up\n");
4429 tp->phy_reset_enable(tp);
4432 mod_timer(timer, jiffies + timeout);
4435 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
4437 if (!test_and_set_bit(flag, tp->wk.flags))
4438 schedule_work(&tp->wk.work);
4441 static void rtl8169_phy_timer(struct timer_list *t)
4443 struct rtl8169_private *tp = from_timer(tp, t, timer);
4445 rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
4448 DECLARE_RTL_COND(rtl_phy_reset_cond)
4450 return tp->phy_reset_pending(tp);
4453 static void rtl8169_phy_reset(struct net_device *dev,
4454 struct rtl8169_private *tp)
4456 tp->phy_reset_enable(tp);
4457 rtl_msleep_loop_wait_low(tp, &rtl_phy_reset_cond, 1, 100);
4460 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
4462 return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
4463 (RTL_R8(tp, PHYstatus) & TBI_Enable);
4466 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
4468 rtl_hw_phy_config(dev);
4470 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
4471 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4472 RTL_W8(tp, 0x82, 0x01);
4475 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
4477 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
4478 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4480 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4481 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4482 RTL_W8(tp, 0x82, 0x01);
4483 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4484 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4487 rtl8169_phy_reset(dev, tp);
4489 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
4490 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4491 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
4492 (tp->mii.supports_gmii ?
4493 ADVERTISED_1000baseT_Half |
4494 ADVERTISED_1000baseT_Full : 0));
4496 if (rtl_tbi_enabled(tp))
4497 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4500 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
4504 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4506 RTL_W32(tp, MAC4, addr[4] | addr[5] << 8);
4509 RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
4512 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4513 rtl_rar_exgmac_set(tp, addr);
4515 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4517 rtl_unlock_work(tp);
4520 static int rtl_set_mac_address(struct net_device *dev, void *p)
4522 struct rtl8169_private *tp = netdev_priv(dev);
4523 struct device *d = tp_to_dev(tp);
4526 ret = eth_mac_addr(dev, p);
4530 pm_runtime_get_noresume(d);
4532 if (pm_runtime_active(d))
4533 rtl_rar_set(tp, dev->dev_addr);
4535 pm_runtime_put_noidle(d);
4540 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4542 struct rtl8169_private *tp = netdev_priv(dev);
4543 struct mii_ioctl_data *data = if_mii(ifr);
4545 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
4548 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
4549 struct mii_ioctl_data *data, int cmd)
4553 data->phy_id = 32; /* Internal PHY */
4557 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
4561 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
4567 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
4572 static void rtl_init_mdio_ops(struct rtl8169_private *tp)
4574 struct mdio_ops *ops = &tp->mdio_ops;
4576 switch (tp->mac_version) {
4577 case RTL_GIGA_MAC_VER_27:
4578 ops->write = r8168dp_1_mdio_write;
4579 ops->read = r8168dp_1_mdio_read;
4581 case RTL_GIGA_MAC_VER_28:
4582 case RTL_GIGA_MAC_VER_31:
4583 ops->write = r8168dp_2_mdio_write;
4584 ops->read = r8168dp_2_mdio_read;
4586 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4587 ops->write = r8168g_mdio_write;
4588 ops->read = r8168g_mdio_read;
4591 ops->write = r8169_mdio_write;
4592 ops->read = r8169_mdio_read;
4597 static void rtl_speed_down(struct rtl8169_private *tp)
4602 rtl_writephy(tp, 0x1f, 0x0000);
4603 lpa = rtl_readphy(tp, MII_LPA);
4605 if (lpa & (LPA_10HALF | LPA_10FULL))
4606 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
4607 else if (lpa & (LPA_100HALF | LPA_100FULL))
4608 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4609 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4611 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4612 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
4613 (tp->mii.supports_gmii ?
4614 ADVERTISED_1000baseT_Half |
4615 ADVERTISED_1000baseT_Full : 0);
4617 rtl8169_set_speed(tp->dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
4621 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
4623 switch (tp->mac_version) {
4624 case RTL_GIGA_MAC_VER_25:
4625 case RTL_GIGA_MAC_VER_26:
4626 case RTL_GIGA_MAC_VER_29:
4627 case RTL_GIGA_MAC_VER_30:
4628 case RTL_GIGA_MAC_VER_32:
4629 case RTL_GIGA_MAC_VER_33:
4630 case RTL_GIGA_MAC_VER_34:
4631 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_51:
4632 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
4633 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
4640 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
4642 if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
4646 rtl_wol_suspend_quirk(tp);
4651 static void r8168_phy_power_up(struct rtl8169_private *tp)
4653 rtl_writephy(tp, 0x1f, 0x0000);
4654 switch (tp->mac_version) {
4655 case RTL_GIGA_MAC_VER_11:
4656 case RTL_GIGA_MAC_VER_12:
4657 case RTL_GIGA_MAC_VER_17 ... RTL_GIGA_MAC_VER_28:
4658 case RTL_GIGA_MAC_VER_31:
4659 rtl_writephy(tp, 0x0e, 0x0000);
4664 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4666 /* give MAC/PHY some time to resume */
4670 static void r8168_phy_power_down(struct rtl8169_private *tp)
4672 rtl_writephy(tp, 0x1f, 0x0000);
4673 switch (tp->mac_version) {
4674 case RTL_GIGA_MAC_VER_32:
4675 case RTL_GIGA_MAC_VER_33:
4676 case RTL_GIGA_MAC_VER_40:
4677 case RTL_GIGA_MAC_VER_41:
4678 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
4681 case RTL_GIGA_MAC_VER_11:
4682 case RTL_GIGA_MAC_VER_12:
4683 case RTL_GIGA_MAC_VER_17 ... RTL_GIGA_MAC_VER_28:
4684 case RTL_GIGA_MAC_VER_31:
4685 rtl_writephy(tp, 0x0e, 0x0200);
4687 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4692 static void r8168_pll_power_down(struct rtl8169_private *tp)
4694 if (r8168_check_dash(tp))
4697 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4698 tp->mac_version == RTL_GIGA_MAC_VER_33)
4699 rtl_ephy_write(tp, 0x19, 0xff64);
4701 if (rtl_wol_pll_power_down(tp))
4704 r8168_phy_power_down(tp);
4706 switch (tp->mac_version) {
4707 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
4708 case RTL_GIGA_MAC_VER_37:
4709 case RTL_GIGA_MAC_VER_39:
4710 case RTL_GIGA_MAC_VER_43:
4711 case RTL_GIGA_MAC_VER_44:
4712 case RTL_GIGA_MAC_VER_45:
4713 case RTL_GIGA_MAC_VER_46:
4714 case RTL_GIGA_MAC_VER_47:
4715 case RTL_GIGA_MAC_VER_48:
4716 case RTL_GIGA_MAC_VER_50:
4717 case RTL_GIGA_MAC_VER_51:
4718 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
4720 case RTL_GIGA_MAC_VER_40:
4721 case RTL_GIGA_MAC_VER_41:
4722 case RTL_GIGA_MAC_VER_49:
4723 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
4724 0xfc000000, ERIAR_EXGMAC);
4725 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
4730 static void r8168_pll_power_up(struct rtl8169_private *tp)
4732 switch (tp->mac_version) {
4733 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
4734 case RTL_GIGA_MAC_VER_37:
4735 case RTL_GIGA_MAC_VER_39:
4736 case RTL_GIGA_MAC_VER_43:
4737 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);
4739 case RTL_GIGA_MAC_VER_44:
4740 case RTL_GIGA_MAC_VER_45:
4741 case RTL_GIGA_MAC_VER_46:
4742 case RTL_GIGA_MAC_VER_47:
4743 case RTL_GIGA_MAC_VER_48:
4744 case RTL_GIGA_MAC_VER_50:
4745 case RTL_GIGA_MAC_VER_51:
4746 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
4748 case RTL_GIGA_MAC_VER_40:
4749 case RTL_GIGA_MAC_VER_41:
4750 case RTL_GIGA_MAC_VER_49:
4751 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
4752 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
4753 0x00000000, ERIAR_EXGMAC);
4757 r8168_phy_power_up(tp);
4760 static void rtl_pll_power_down(struct rtl8169_private *tp)
4762 switch (tp->mac_version) {
4763 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4764 case RTL_GIGA_MAC_VER_13 ... RTL_GIGA_MAC_VER_15:
4767 r8168_pll_power_down(tp);
4771 static void rtl_pll_power_up(struct rtl8169_private *tp)
4773 switch (tp->mac_version) {
4774 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4775 case RTL_GIGA_MAC_VER_13 ... RTL_GIGA_MAC_VER_15:
4778 r8168_pll_power_up(tp);
4782 static void rtl_init_rxcfg(struct rtl8169_private *tp)
4784 switch (tp->mac_version) {
4785 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4786 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
4787 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4789 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
4790 case RTL_GIGA_MAC_VER_34:
4791 case RTL_GIGA_MAC_VER_35:
4792 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4794 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4795 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
4798 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
4803 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4805 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
4808 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4810 if (tp->jumbo_ops.enable) {
4811 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4812 tp->jumbo_ops.enable(tp);
4813 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4817 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4819 if (tp->jumbo_ops.disable) {
4820 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4821 tp->jumbo_ops.disable(tp);
4822 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4826 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4828 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4829 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
4830 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
4833 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4835 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4836 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
4837 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4840 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4842 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4845 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4847 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4850 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4852 RTL_W8(tp, MaxTxPacketSize, 0x3f);
4853 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4854 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
4855 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
4858 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4860 RTL_W8(tp, MaxTxPacketSize, 0x0c);
4861 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4862 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
4863 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4866 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4868 rtl_tx_performance_tweak(tp,
4869 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
4872 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4874 rtl_tx_performance_tweak(tp,
4875 PCI_EXP_DEVCTL_READRQ_4096B | PCI_EXP_DEVCTL_NOSNOOP_EN);
4878 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4880 r8168b_0_hw_jumbo_enable(tp);
4882 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
4885 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4887 r8168b_0_hw_jumbo_disable(tp);
4889 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4892 static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
4894 struct jumbo_ops *ops = &tp->jumbo_ops;
4896 switch (tp->mac_version) {
4897 case RTL_GIGA_MAC_VER_11:
4898 ops->disable = r8168b_0_hw_jumbo_disable;
4899 ops->enable = r8168b_0_hw_jumbo_enable;
4901 case RTL_GIGA_MAC_VER_12:
4902 case RTL_GIGA_MAC_VER_17:
4903 ops->disable = r8168b_1_hw_jumbo_disable;
4904 ops->enable = r8168b_1_hw_jumbo_enable;
4906 case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
4907 case RTL_GIGA_MAC_VER_19:
4908 case RTL_GIGA_MAC_VER_20:
4909 case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
4910 case RTL_GIGA_MAC_VER_22:
4911 case RTL_GIGA_MAC_VER_23:
4912 case RTL_GIGA_MAC_VER_24:
4913 case RTL_GIGA_MAC_VER_25:
4914 case RTL_GIGA_MAC_VER_26:
4915 ops->disable = r8168c_hw_jumbo_disable;
4916 ops->enable = r8168c_hw_jumbo_enable;
4918 case RTL_GIGA_MAC_VER_27:
4919 case RTL_GIGA_MAC_VER_28:
4920 ops->disable = r8168dp_hw_jumbo_disable;
4921 ops->enable = r8168dp_hw_jumbo_enable;
4923 case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
4924 case RTL_GIGA_MAC_VER_32:
4925 case RTL_GIGA_MAC_VER_33:
4926 case RTL_GIGA_MAC_VER_34:
4927 ops->disable = r8168e_hw_jumbo_disable;
4928 ops->enable = r8168e_hw_jumbo_enable;
4932 * No action needed for jumbo frames with 8169.
4933 * No jumbo for 810x at all.
4935 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4937 ops->disable = NULL;
4943 DECLARE_RTL_COND(rtl_chipcmd_cond)
4945 return RTL_R8(tp, ChipCmd) & CmdReset;
4948 static void rtl_hw_reset(struct rtl8169_private *tp)
4950 RTL_W8(tp, ChipCmd, CmdReset);
4952 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
4955 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
4957 struct rtl_fw *rtl_fw;
4961 name = rtl_lookup_firmware_name(tp);
4963 goto out_no_firmware;
4965 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4969 rc = request_firmware(&rtl_fw->fw, name, tp_to_dev(tp));
4973 rc = rtl_check_firmware(tp, rtl_fw);
4975 goto err_release_firmware;
4977 tp->rtl_fw = rtl_fw;
4981 err_release_firmware:
4982 release_firmware(rtl_fw->fw);
4986 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4993 static void rtl_request_firmware(struct rtl8169_private *tp)
4995 if (IS_ERR(tp->rtl_fw))
4996 rtl_request_uncached_firmware(tp);
4999 static void rtl_rx_close(struct rtl8169_private *tp)
5001 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
5004 DECLARE_RTL_COND(rtl_npq_cond)
5006 return RTL_R8(tp, TxPoll) & NPQ;
5009 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
5011 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
5014 static void rtl8169_hw_reset(struct rtl8169_private *tp)
5016 /* Disable interrupts */
5017 rtl8169_irq_mask_and_ack(tp);
5021 switch (tp->mac_version) {
5022 case RTL_GIGA_MAC_VER_27:
5023 case RTL_GIGA_MAC_VER_28:
5024 case RTL_GIGA_MAC_VER_31:
5025 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
5027 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
5028 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
5029 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
5030 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
5033 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
5041 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
5043 /* Set DMA burst size and Interframe Gap Time */
5044 RTL_W32(tp, TxConfig, (TX_DMA_BURST << TxDMAShift) |
5045 (InterFrameGap << TxInterFrameGapShift));
5048 static void rtl_set_rx_max_size(struct rtl8169_private *tp)
5050 /* Low hurts. Let's disable the filtering. */
5051 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
5054 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
5057 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
5058 * register to be written before TxDescAddrLow to work.
5059 * Switching from MMIO to I/O access fixes the issue as well.
5061 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
5062 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
5063 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
5064 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
5067 static void rtl8169_set_magic_reg(struct rtl8169_private *tp, unsigned mac_version)
5069 static const struct rtl_cfg2_info {
5074 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
5075 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
5076 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
5077 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
5079 const struct rtl_cfg2_info *p = cfg2_info;
5083 clk = RTL_R8(tp, Config2) & PCI_Clock_66MHz;
5084 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
5085 if ((p->mac_version == mac_version) && (p->clk == clk)) {
5086 RTL_W32(tp, 0x7c, p->val);
5092 static void rtl_set_rx_mode(struct net_device *dev)
5094 struct rtl8169_private *tp = netdev_priv(dev);
5095 u32 mc_filter[2]; /* Multicast hash filter */
5099 if (dev->flags & IFF_PROMISC) {
5100 /* Unconditionally log net taps. */
5101 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
5103 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
5105 mc_filter[1] = mc_filter[0] = 0xffffffff;
5106 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
5107 (dev->flags & IFF_ALLMULTI)) {
5108 /* Too many to filter perfectly -- accept all multicasts. */
5109 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
5110 mc_filter[1] = mc_filter[0] = 0xffffffff;
5112 struct netdev_hw_addr *ha;
5114 rx_mode = AcceptBroadcast | AcceptMyPhys;
5115 mc_filter[1] = mc_filter[0] = 0;
5116 netdev_for_each_mc_addr(ha, dev) {
5117 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
5118 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
5119 rx_mode |= AcceptMulticast;
5123 if (dev->features & NETIF_F_RXALL)
5124 rx_mode |= (AcceptErr | AcceptRunt);
5126 tmp = (RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
5128 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
5129 u32 data = mc_filter[0];
5131 mc_filter[0] = swab32(mc_filter[1]);
5132 mc_filter[1] = swab32(data);
5135 if (tp->mac_version == RTL_GIGA_MAC_VER_35)
5136 mc_filter[1] = mc_filter[0] = 0xffffffff;
5138 RTL_W32(tp, MAR0 + 4, mc_filter[1]);
5139 RTL_W32(tp, MAR0 + 0, mc_filter[0]);
5141 RTL_W32(tp, RxConfig, tmp);
5144 static void rtl_hw_start(struct rtl8169_private *tp)
5146 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
5150 rtl_set_rx_max_size(tp);
5151 rtl_set_rx_tx_desc_registers(tp);
5152 rtl_set_rx_tx_config_registers(tp);
5153 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
5155 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
5156 RTL_R8(tp, IntrMask);
5157 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
5158 rtl_set_rx_mode(tp->dev);
5159 /* no early-rx interrupts */
5160 RTL_W16(tp, MultiIntr, RTL_R16(tp, MultiIntr) & 0xf000);
5161 rtl_irq_enable_all(tp);
5164 static void rtl_hw_start_8169(struct rtl8169_private *tp)
5166 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
5167 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
5169 RTL_W8(tp, EarlyTxThres, NoEarlyTx);
5171 tp->cp_cmd |= PCIMulRW;
5173 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5174 tp->mac_version == RTL_GIGA_MAC_VER_03) {
5175 dprintk("Set MAC Reg C+CR Offset 0xe0. "
5176 "Bit-3 and bit-14 MUST be 1\n");
5177 tp->cp_cmd |= (1 << 14);
5180 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5182 rtl8169_set_magic_reg(tp, tp->mac_version);
5185 * Undocumented corner. Supposedly:
5186 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
5188 RTL_W16(tp, IntrMitigate, 0x0000);
5190 RTL_W32(tp, RxMissed, 0);
5193 DECLARE_RTL_COND(rtl_csiar_cond)
5195 return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
5198 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
5200 u32 func = PCI_FUNC(tp->pci_dev->devfn);
5202 RTL_W32(tp, CSIDR, value);
5203 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5204 CSIAR_BYTE_ENABLE | func << 16);
5206 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5209 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
5211 u32 func = PCI_FUNC(tp->pci_dev->devfn);
5213 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
5216 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5217 RTL_R32(tp, CSIDR) : ~0;
5220 static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val)
5222 struct pci_dev *pdev = tp->pci_dev;
5225 /* According to Realtek the value at config space address 0x070f
5226 * controls the L0s/L1 entrance latency. We try standard ECAM access
5227 * first and if it fails fall back to CSI.
5229 if (pdev->cfg_size > 0x070f &&
5230 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
5233 netdev_notice_once(tp->dev,
5234 "No native access to PCI extended config space, falling back to CSI\n");
5235 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
5236 rtl_csi_write(tp, 0x070c, csi | val << 24);
5239 static void rtl_csi_access_enable_1(struct rtl8169_private *tp)
5241 rtl_csi_access_enable(tp, 0x17);
5244 static void rtl_csi_access_enable_2(struct rtl8169_private *tp)
5246 rtl_csi_access_enable(tp, 0x27);
5250 unsigned int offset;
5255 static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
5261 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
5262 rtl_ephy_write(tp, e->offset, w);
5267 static void rtl_disable_clock_request(struct rtl8169_private *tp)
5269 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
5270 PCI_EXP_LNKCTL_CLKREQ_EN);
5273 static void rtl_enable_clock_request(struct rtl8169_private *tp)
5275 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
5276 PCI_EXP_LNKCTL_CLKREQ_EN);
5279 static void rtl_pcie_state_l2l3_enable(struct rtl8169_private *tp, bool enable)
5283 data = RTL_R8(tp, Config3);
5288 data &= ~Rdy_to_L23;
5290 RTL_W8(tp, Config3, data);
5293 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
5295 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5297 tp->cp_cmd &= CPCMD_QUIRK_MASK;
5298 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5300 if (tp->dev->mtu <= ETH_DATA_LEN) {
5301 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B |
5302 PCI_EXP_DEVCTL_NOSNOOP_EN);
5306 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
5308 rtl_hw_start_8168bb(tp);
5310 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5312 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
5315 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
5317 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
5319 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5321 if (tp->dev->mtu <= ETH_DATA_LEN)
5322 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5324 rtl_disable_clock_request(tp);
5326 tp->cp_cmd &= CPCMD_QUIRK_MASK;
5327 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5330 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
5332 static const struct ephy_info e_info_8168cp[] = {
5333 { 0x01, 0, 0x0001 },
5334 { 0x02, 0x0800, 0x1000 },
5335 { 0x03, 0, 0x0042 },
5336 { 0x06, 0x0080, 0x0000 },
5340 rtl_csi_access_enable_2(tp);
5342 rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
5344 __rtl_hw_start_8168cp(tp);
5347 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
5349 rtl_csi_access_enable_2(tp);
5351 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5353 if (tp->dev->mtu <= ETH_DATA_LEN)
5354 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5356 tp->cp_cmd &= CPCMD_QUIRK_MASK;
5357 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5360 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
5362 rtl_csi_access_enable_2(tp);
5364 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5367 RTL_W8(tp, DBG_REG, 0x20);
5369 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5371 if (tp->dev->mtu <= ETH_DATA_LEN)
5372 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5374 tp->cp_cmd &= CPCMD_QUIRK_MASK;
5375 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5378 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
5380 static const struct ephy_info e_info_8168c_1[] = {
5381 { 0x02, 0x0800, 0x1000 },
5382 { 0x03, 0, 0x0002 },
5383 { 0x06, 0x0080, 0x0000 }
5386 rtl_csi_access_enable_2(tp);
5388 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
5390 rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
5392 __rtl_hw_start_8168cp(tp);
5395 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
5397 static const struct ephy_info e_info_8168c_2[] = {
5398 { 0x01, 0, 0x0001 },
5399 { 0x03, 0x0400, 0x0220 }
5402 rtl_csi_access_enable_2(tp);
5404 rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
5406 __rtl_hw_start_8168cp(tp);
5409 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
5411 rtl_hw_start_8168c_2(tp);
5414 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
5416 rtl_csi_access_enable_2(tp);
5418 __rtl_hw_start_8168cp(tp);
5421 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
5423 rtl_csi_access_enable_2(tp);
5425 rtl_disable_clock_request(tp);
5427 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5429 if (tp->dev->mtu <= ETH_DATA_LEN)
5430 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5432 tp->cp_cmd &= CPCMD_QUIRK_MASK;
5433 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5436 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
5438 rtl_csi_access_enable_1(tp);
5440 if (tp->dev->mtu <= ETH_DATA_LEN)
5441 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5443 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5445 rtl_disable_clock_request(tp);
5448 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
5450 static const struct ephy_info e_info_8168d_4[] = {
5451 { 0x0b, 0x0000, 0x0048 },
5452 { 0x19, 0x0020, 0x0050 },
5453 { 0x0c, 0x0100, 0x0020 }
5456 rtl_csi_access_enable_1(tp);
5458 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5460 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5462 rtl_ephy_init(tp, e_info_8168d_4, ARRAY_SIZE(e_info_8168d_4));
5464 rtl_enable_clock_request(tp);
5467 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
5469 static const struct ephy_info e_info_8168e_1[] = {
5470 { 0x00, 0x0200, 0x0100 },
5471 { 0x00, 0x0000, 0x0004 },
5472 { 0x06, 0x0002, 0x0001 },
5473 { 0x06, 0x0000, 0x0030 },
5474 { 0x07, 0x0000, 0x2000 },
5475 { 0x00, 0x0000, 0x0020 },
5476 { 0x03, 0x5800, 0x2000 },
5477 { 0x03, 0x0000, 0x0001 },
5478 { 0x01, 0x0800, 0x1000 },
5479 { 0x07, 0x0000, 0x4000 },
5480 { 0x1e, 0x0000, 0x2000 },
5481 { 0x19, 0xffff, 0xfe6c },
5482 { 0x0a, 0x0000, 0x0040 }
5485 rtl_csi_access_enable_2(tp);
5487 rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
5489 if (tp->dev->mtu <= ETH_DATA_LEN)
5490 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5492 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5494 rtl_disable_clock_request(tp);
5496 /* Reset tx FIFO pointer */
5497 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
5498 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
5500 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
5503 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
5505 static const struct ephy_info e_info_8168e_2[] = {
5506 { 0x09, 0x0000, 0x0080 },
5507 { 0x19, 0x0000, 0x0224 }
5510 rtl_csi_access_enable_1(tp);
5512 rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
5514 if (tp->dev->mtu <= ETH_DATA_LEN)
5515 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5517 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5518 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5519 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5520 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5521 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5522 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
5523 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5524 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5526 RTL_W8(tp, MaxTxPacketSize, EarlySize);
5528 rtl_disable_clock_request(tp);
5530 RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
5531 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5533 /* Adjust EEE LED frequency */
5534 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5536 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5537 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
5538 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
5541 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
5543 rtl_csi_access_enable_2(tp);
5545 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5547 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5548 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5549 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5550 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5551 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5552 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5553 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5554 rtl_w0w1_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5555 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5556 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
5558 RTL_W8(tp, MaxTxPacketSize, EarlySize);
5560 rtl_disable_clock_request(tp);
5562 RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
5563 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5564 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5565 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
5566 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
5569 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5571 static const struct ephy_info e_info_8168f_1[] = {
5572 { 0x06, 0x00c0, 0x0020 },
5573 { 0x08, 0x0001, 0x0002 },
5574 { 0x09, 0x0000, 0x0080 },
5575 { 0x19, 0x0000, 0x0224 }
5578 rtl_hw_start_8168f(tp);
5580 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5582 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5584 /* Adjust EEE LED frequency */
5585 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5588 static void rtl_hw_start_8411(struct rtl8169_private *tp)
5590 static const struct ephy_info e_info_8168f_1[] = {
5591 { 0x06, 0x00c0, 0x0020 },
5592 { 0x0f, 0xffff, 0x5200 },
5593 { 0x1e, 0x0000, 0x4000 },
5594 { 0x19, 0x0000, 0x0224 }
5597 rtl_hw_start_8168f(tp);
5598 rtl_pcie_state_l2l3_enable(tp, false);
5600 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5602 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
5605 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
5607 RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
5609 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
5610 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5611 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5612 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5614 rtl_csi_access_enable_1(tp);
5616 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5618 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5619 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5620 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
5622 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5623 RTL_W8(tp, MaxTxPacketSize, EarlySize);
5625 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5626 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5628 /* Adjust EEE LED frequency */
5629 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5631 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5632 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
5634 rtl_pcie_state_l2l3_enable(tp, false);
5637 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
5639 static const struct ephy_info e_info_8168g_1[] = {
5640 { 0x00, 0x0000, 0x0008 },
5641 { 0x0c, 0x37d0, 0x0820 },
5642 { 0x1e, 0x0000, 0x0001 },
5643 { 0x19, 0x8000, 0x0000 }
5646 rtl_hw_start_8168g(tp);
5648 /* disable aspm and clock request before access ephy */
5649 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
5650 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
5651 rtl_ephy_init(tp, e_info_8168g_1, ARRAY_SIZE(e_info_8168g_1));
5654 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
5656 static const struct ephy_info e_info_8168g_2[] = {
5657 { 0x00, 0x0000, 0x0008 },
5658 { 0x0c, 0x3df0, 0x0200 },
5659 { 0x19, 0xffff, 0xfc00 },
5660 { 0x1e, 0xffff, 0x20eb }
5663 rtl_hw_start_8168g(tp);
5665 /* disable aspm and clock request before access ephy */
5666 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
5667 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
5668 rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
5671 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
5673 static const struct ephy_info e_info_8411_2[] = {
5674 { 0x00, 0x0000, 0x0008 },
5675 { 0x0c, 0x3df0, 0x0200 },
5676 { 0x0f, 0xffff, 0x5200 },
5677 { 0x19, 0x0020, 0x0000 },
5678 { 0x1e, 0x0000, 0x2000 }
5681 rtl_hw_start_8168g(tp);
5683 /* disable aspm and clock request before access ephy */
5684 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
5685 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
5686 rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
5689 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
5693 static const struct ephy_info e_info_8168h_1[] = {
5694 { 0x1e, 0x0800, 0x0001 },
5695 { 0x1d, 0x0000, 0x0800 },
5696 { 0x05, 0xffff, 0x2089 },
5697 { 0x06, 0xffff, 0x5881 },
5698 { 0x04, 0xffff, 0x154a },
5699 { 0x01, 0xffff, 0x068b }
5702 /* disable aspm and clock request before access ephy */
5703 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
5704 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
5705 rtl_ephy_init(tp, e_info_8168h_1, ARRAY_SIZE(e_info_8168h_1));
5707 RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
5709 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
5710 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5711 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5712 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5714 rtl_csi_access_enable_1(tp);
5716 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5718 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5719 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5721 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_1111, 0x0010, 0x00, ERIAR_EXGMAC);
5723 rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f00, 0x00, ERIAR_EXGMAC);
5725 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
5727 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5728 RTL_W8(tp, MaxTxPacketSize, EarlySize);
5730 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5731 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5733 /* Adjust EEE LED frequency */
5734 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5736 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5737 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5739 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
5741 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
5743 rtl_pcie_state_l2l3_enable(tp, false);
5745 rtl_writephy(tp, 0x1f, 0x0c42);
5746 rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
5747 rtl_writephy(tp, 0x1f, 0x0000);
5748 if (rg_saw_cnt > 0) {
5751 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
5752 sw_cnt_1ms_ini &= 0x0fff;
5753 data = r8168_mac_ocp_read(tp, 0xd412);
5755 data |= sw_cnt_1ms_ini;
5756 r8168_mac_ocp_write(tp, 0xd412, data);
5759 data = r8168_mac_ocp_read(tp, 0xe056);
5762 r8168_mac_ocp_write(tp, 0xe056, data);
5764 data = r8168_mac_ocp_read(tp, 0xe052);
5767 r8168_mac_ocp_write(tp, 0xe052, data);
5769 data = r8168_mac_ocp_read(tp, 0xe0d6);
5772 r8168_mac_ocp_write(tp, 0xe0d6, data);
5774 data = r8168_mac_ocp_read(tp, 0xd420);
5777 r8168_mac_ocp_write(tp, 0xd420, data);
5779 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
5780 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
5781 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
5782 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
5785 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
5787 rtl8168ep_stop_cmac(tp);
5789 RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
5791 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
5792 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x2f, ERIAR_EXGMAC);
5793 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x5f, ERIAR_EXGMAC);
5794 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5796 rtl_csi_access_enable_1(tp);
5798 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5800 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5801 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5803 rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f80, 0x00, ERIAR_EXGMAC);
5805 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
5807 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5808 RTL_W8(tp, MaxTxPacketSize, EarlySize);
5810 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5811 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5813 /* Adjust EEE LED frequency */
5814 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5816 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5818 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
5820 rtl_pcie_state_l2l3_enable(tp, false);
5823 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
5825 static const struct ephy_info e_info_8168ep_1[] = {
5826 { 0x00, 0xffff, 0x10ab },
5827 { 0x06, 0xffff, 0xf030 },
5828 { 0x08, 0xffff, 0x2006 },
5829 { 0x0d, 0xffff, 0x1666 },
5830 { 0x0c, 0x3ff0, 0x0000 }
5833 /* disable aspm and clock request before access ephy */
5834 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
5835 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
5836 rtl_ephy_init(tp, e_info_8168ep_1, ARRAY_SIZE(e_info_8168ep_1));
5838 rtl_hw_start_8168ep(tp);
5841 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
5843 static const struct ephy_info e_info_8168ep_2[] = {
5844 { 0x00, 0xffff, 0x10a3 },
5845 { 0x19, 0xffff, 0xfc00 },
5846 { 0x1e, 0xffff, 0x20ea }
5849 /* disable aspm and clock request before access ephy */
5850 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
5851 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
5852 rtl_ephy_init(tp, e_info_8168ep_2, ARRAY_SIZE(e_info_8168ep_2));
5854 rtl_hw_start_8168ep(tp);
5856 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5857 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5860 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
5863 static const struct ephy_info e_info_8168ep_3[] = {
5864 { 0x00, 0xffff, 0x10a3 },
5865 { 0x19, 0xffff, 0x7c00 },
5866 { 0x1e, 0xffff, 0x20eb },
5867 { 0x0d, 0xffff, 0x1666 }
5870 /* disable aspm and clock request before access ephy */
5871 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
5872 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
5873 rtl_ephy_init(tp, e_info_8168ep_3, ARRAY_SIZE(e_info_8168ep_3));
5875 rtl_hw_start_8168ep(tp);
5877 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5878 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5880 data = r8168_mac_ocp_read(tp, 0xd3e2);
5883 r8168_mac_ocp_write(tp, 0xd3e2, data);
5885 data = r8168_mac_ocp_read(tp, 0xd3e4);
5887 r8168_mac_ocp_write(tp, 0xd3e4, data);
5889 data = r8168_mac_ocp_read(tp, 0xe860);
5891 r8168_mac_ocp_write(tp, 0xe860, data);
5894 static void rtl_hw_start_8168(struct rtl8169_private *tp)
5896 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5898 tp->cp_cmd &= ~INTT_MASK;
5899 tp->cp_cmd |= PktCntrDisable | INTT_1;
5900 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5902 RTL_W16(tp, IntrMitigate, 0x5151);
5904 /* Work around for RxFIFO overflow. */
5905 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
5906 tp->event_slow |= RxFIFOOver | PCSTimeout;
5907 tp->event_slow &= ~RxOverflow;
5910 switch (tp->mac_version) {
5911 case RTL_GIGA_MAC_VER_11:
5912 rtl_hw_start_8168bb(tp);
5915 case RTL_GIGA_MAC_VER_12:
5916 case RTL_GIGA_MAC_VER_17:
5917 rtl_hw_start_8168bef(tp);
5920 case RTL_GIGA_MAC_VER_18:
5921 rtl_hw_start_8168cp_1(tp);
5924 case RTL_GIGA_MAC_VER_19:
5925 rtl_hw_start_8168c_1(tp);
5928 case RTL_GIGA_MAC_VER_20:
5929 rtl_hw_start_8168c_2(tp);
5932 case RTL_GIGA_MAC_VER_21:
5933 rtl_hw_start_8168c_3(tp);
5936 case RTL_GIGA_MAC_VER_22:
5937 rtl_hw_start_8168c_4(tp);
5940 case RTL_GIGA_MAC_VER_23:
5941 rtl_hw_start_8168cp_2(tp);
5944 case RTL_GIGA_MAC_VER_24:
5945 rtl_hw_start_8168cp_3(tp);
5948 case RTL_GIGA_MAC_VER_25:
5949 case RTL_GIGA_MAC_VER_26:
5950 case RTL_GIGA_MAC_VER_27:
5951 rtl_hw_start_8168d(tp);
5954 case RTL_GIGA_MAC_VER_28:
5955 rtl_hw_start_8168d_4(tp);
5958 case RTL_GIGA_MAC_VER_31:
5959 rtl_hw_start_8168dp(tp);
5962 case RTL_GIGA_MAC_VER_32:
5963 case RTL_GIGA_MAC_VER_33:
5964 rtl_hw_start_8168e_1(tp);
5966 case RTL_GIGA_MAC_VER_34:
5967 rtl_hw_start_8168e_2(tp);
5970 case RTL_GIGA_MAC_VER_35:
5971 case RTL_GIGA_MAC_VER_36:
5972 rtl_hw_start_8168f_1(tp);
5975 case RTL_GIGA_MAC_VER_38:
5976 rtl_hw_start_8411(tp);
5979 case RTL_GIGA_MAC_VER_40:
5980 case RTL_GIGA_MAC_VER_41:
5981 rtl_hw_start_8168g_1(tp);
5983 case RTL_GIGA_MAC_VER_42:
5984 rtl_hw_start_8168g_2(tp);
5987 case RTL_GIGA_MAC_VER_44:
5988 rtl_hw_start_8411_2(tp);
5991 case RTL_GIGA_MAC_VER_45:
5992 case RTL_GIGA_MAC_VER_46:
5993 rtl_hw_start_8168h_1(tp);
5996 case RTL_GIGA_MAC_VER_49:
5997 rtl_hw_start_8168ep_1(tp);
6000 case RTL_GIGA_MAC_VER_50:
6001 rtl_hw_start_8168ep_2(tp);
6004 case RTL_GIGA_MAC_VER_51:
6005 rtl_hw_start_8168ep_3(tp);
6009 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
6010 tp->dev->name, tp->mac_version);
6015 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
6017 static const struct ephy_info e_info_8102e_1[] = {
6018 { 0x01, 0, 0x6e65 },
6019 { 0x02, 0, 0x091f },
6020 { 0x03, 0, 0xc2f9 },
6021 { 0x06, 0, 0xafb5 },
6022 { 0x07, 0, 0x0e00 },
6023 { 0x19, 0, 0xec80 },
6024 { 0x01, 0, 0x2e65 },
6029 rtl_csi_access_enable_2(tp);
6031 RTL_W8(tp, DBG_REG, FIX_NAK_1);
6033 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
6036 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
6037 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
6039 cfg1 = RTL_R8(tp, Config1);
6040 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
6041 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
6043 rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
6046 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
6048 rtl_csi_access_enable_2(tp);
6050 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
6052 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
6053 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
6056 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
6058 rtl_hw_start_8102e_2(tp);
6060 rtl_ephy_write(tp, 0x03, 0xc2f9);
6063 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
6065 static const struct ephy_info e_info_8105e_1[] = {
6066 { 0x07, 0, 0x4000 },
6067 { 0x19, 0, 0x0200 },
6068 { 0x19, 0, 0x0020 },
6069 { 0x1e, 0, 0x2000 },
6070 { 0x03, 0, 0x0001 },
6071 { 0x19, 0, 0x0100 },
6072 { 0x19, 0, 0x0004 },
6076 /* Force LAN exit from ASPM if Rx/Tx are not idle */
6077 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
6079 /* Disable Early Tally Counter */
6080 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
6082 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
6083 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
6085 rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
6087 rtl_pcie_state_l2l3_enable(tp, false);
6090 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
6092 rtl_hw_start_8105e_1(tp);
6093 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
6096 static void rtl_hw_start_8402(struct rtl8169_private *tp)
6098 static const struct ephy_info e_info_8402[] = {
6099 { 0x19, 0xffff, 0xff64 },
6103 rtl_csi_access_enable_2(tp);
6105 /* Force LAN exit from ASPM if Rx/Tx are not idle */
6106 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
6108 RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
6109 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
6111 rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
6113 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
6115 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
6116 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
6117 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6118 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6119 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6120 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6121 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
6123 rtl_pcie_state_l2l3_enable(tp, false);
6126 static void rtl_hw_start_8106(struct rtl8169_private *tp)
6128 /* Force LAN exit from ASPM if Rx/Tx are not idle */
6129 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
6131 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
6132 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
6133 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
6135 rtl_pcie_state_l2l3_enable(tp, false);
6138 static void rtl_hw_start_8101(struct rtl8169_private *tp)
6140 if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
6141 tp->event_slow &= ~RxFIFOOver;
6143 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
6144 tp->mac_version == RTL_GIGA_MAC_VER_16)
6145 pcie_capability_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
6146 PCI_EXP_DEVCTL_NOSNOOP_EN);
6148 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
6150 tp->cp_cmd &= CPCMD_QUIRK_MASK;
6151 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
6153 switch (tp->mac_version) {
6154 case RTL_GIGA_MAC_VER_07:
6155 rtl_hw_start_8102e_1(tp);
6158 case RTL_GIGA_MAC_VER_08:
6159 rtl_hw_start_8102e_3(tp);
6162 case RTL_GIGA_MAC_VER_09:
6163 rtl_hw_start_8102e_2(tp);
6166 case RTL_GIGA_MAC_VER_29:
6167 rtl_hw_start_8105e_1(tp);
6169 case RTL_GIGA_MAC_VER_30:
6170 rtl_hw_start_8105e_2(tp);
6173 case RTL_GIGA_MAC_VER_37:
6174 rtl_hw_start_8402(tp);
6177 case RTL_GIGA_MAC_VER_39:
6178 rtl_hw_start_8106(tp);
6180 case RTL_GIGA_MAC_VER_43:
6181 rtl_hw_start_8168g_2(tp);
6183 case RTL_GIGA_MAC_VER_47:
6184 case RTL_GIGA_MAC_VER_48:
6185 rtl_hw_start_8168h_1(tp);
6189 RTL_W16(tp, IntrMitigate, 0x0000);
6192 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
6194 struct rtl8169_private *tp = netdev_priv(dev);
6196 if (new_mtu > ETH_DATA_LEN)
6197 rtl_hw_jumbo_enable(tp);
6199 rtl_hw_jumbo_disable(tp);
6202 netdev_update_features(dev);
6207 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
6209 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
6210 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
6213 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
6214 void **data_buff, struct RxDesc *desc)
6216 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr),
6217 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
6221 rtl8169_make_unusable_by_asic(desc);
6224 static inline void rtl8169_mark_to_asic(struct RxDesc *desc)
6226 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
6228 /* Force memory writes to complete before releasing descriptor */
6231 desc->opts1 = cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE);
6234 static inline void *rtl8169_align(void *data)
6236 return (void *)ALIGN((long)data, 16);
6239 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
6240 struct RxDesc *desc)
6244 struct device *d = tp_to_dev(tp);
6245 int node = dev_to_node(d);
6247 data = kmalloc_node(R8169_RX_BUF_SIZE, GFP_KERNEL, node);
6251 if (rtl8169_align(data) != data) {
6253 data = kmalloc_node(R8169_RX_BUF_SIZE + 15, GFP_KERNEL, node);
6258 mapping = dma_map_single(d, rtl8169_align(data), R8169_RX_BUF_SIZE,
6260 if (unlikely(dma_mapping_error(d, mapping))) {
6261 if (net_ratelimit())
6262 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
6266 desc->addr = cpu_to_le64(mapping);
6267 rtl8169_mark_to_asic(desc);
6275 static void rtl8169_rx_clear(struct rtl8169_private *tp)
6279 for (i = 0; i < NUM_RX_DESC; i++) {
6280 if (tp->Rx_databuff[i]) {
6281 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
6282 tp->RxDescArray + i);
6287 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
6289 desc->opts1 |= cpu_to_le32(RingEnd);
6292 static int rtl8169_rx_fill(struct rtl8169_private *tp)
6296 for (i = 0; i < NUM_RX_DESC; i++) {
6299 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6301 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
6304 tp->Rx_databuff[i] = data;
6307 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
6311 rtl8169_rx_clear(tp);
6315 static int rtl8169_init_ring(struct rtl8169_private *tp)
6317 rtl8169_init_ring_indexes(tp);
6319 memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
6320 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
6322 return rtl8169_rx_fill(tp);
6325 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
6326 struct TxDesc *desc)
6328 unsigned int len = tx_skb->len;
6330 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
6338 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
6343 for (i = 0; i < n; i++) {
6344 unsigned int entry = (start + i) % NUM_TX_DESC;
6345 struct ring_info *tx_skb = tp->tx_skb + entry;
6346 unsigned int len = tx_skb->len;
6349 struct sk_buff *skb = tx_skb->skb;
6351 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
6352 tp->TxDescArray + entry);
6354 dev_consume_skb_any(skb);
6361 static void rtl8169_tx_clear(struct rtl8169_private *tp)
6363 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
6364 tp->cur_tx = tp->dirty_tx = 0;
6367 static void rtl_reset_work(struct rtl8169_private *tp)
6369 struct net_device *dev = tp->dev;
6372 napi_disable(&tp->napi);
6373 netif_stop_queue(dev);
6374 synchronize_sched();
6376 rtl8169_hw_reset(tp);
6378 for (i = 0; i < NUM_RX_DESC; i++)
6379 rtl8169_mark_to_asic(tp->RxDescArray + i);
6381 rtl8169_tx_clear(tp);
6382 rtl8169_init_ring_indexes(tp);
6384 napi_enable(&tp->napi);
6386 netif_wake_queue(dev);
6387 rtl8169_check_link_status(dev, tp);
6390 static void rtl8169_tx_timeout(struct net_device *dev)
6392 struct rtl8169_private *tp = netdev_priv(dev);
6394 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6397 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
6400 struct skb_shared_info *info = skb_shinfo(skb);
6401 unsigned int cur_frag, entry;
6402 struct TxDesc *uninitialized_var(txd);
6403 struct device *d = tp_to_dev(tp);
6406 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
6407 const skb_frag_t *frag = info->frags + cur_frag;
6412 entry = (entry + 1) % NUM_TX_DESC;
6414 txd = tp->TxDescArray + entry;
6415 len = skb_frag_size(frag);
6416 addr = skb_frag_address(frag);
6417 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
6418 if (unlikely(dma_mapping_error(d, mapping))) {
6419 if (net_ratelimit())
6420 netif_err(tp, drv, tp->dev,
6421 "Failed to map TX fragments DMA!\n");
6425 /* Anti gcc 2.95.3 bugware (sic) */
6426 status = opts[0] | len |
6427 (RingEnd * !((entry + 1) % NUM_TX_DESC));
6429 txd->opts1 = cpu_to_le32(status);
6430 txd->opts2 = cpu_to_le32(opts[1]);
6431 txd->addr = cpu_to_le64(mapping);
6433 tp->tx_skb[entry].len = len;
6437 tp->tx_skb[entry].skb = skb;
6438 txd->opts1 |= cpu_to_le32(LastFrag);
6444 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
6448 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
6450 return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
6453 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6454 struct net_device *dev);
6455 /* r8169_csum_workaround()
6456 * The hw limites the value the transport offset. When the offset is out of the
6457 * range, calculate the checksum by sw.
6459 static void r8169_csum_workaround(struct rtl8169_private *tp,
6460 struct sk_buff *skb)
6462 if (skb_shinfo(skb)->gso_size) {
6463 netdev_features_t features = tp->dev->features;
6464 struct sk_buff *segs, *nskb;
6466 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
6467 segs = skb_gso_segment(skb, features);
6468 if (IS_ERR(segs) || !segs)
6475 rtl8169_start_xmit(nskb, tp->dev);
6478 dev_consume_skb_any(skb);
6479 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6480 if (skb_checksum_help(skb) < 0)
6483 rtl8169_start_xmit(skb, tp->dev);
6485 struct net_device_stats *stats;
6488 stats = &tp->dev->stats;
6489 stats->tx_dropped++;
6490 dev_kfree_skb_any(skb);
6494 /* msdn_giant_send_check()
6495 * According to the document of microsoft, the TCP Pseudo Header excludes the
6496 * packet length for IPv6 TCP large packets.
6498 static int msdn_giant_send_check(struct sk_buff *skb)
6500 const struct ipv6hdr *ipv6h;
6504 ret = skb_cow_head(skb, 0);
6508 ipv6h = ipv6_hdr(skb);
6512 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
6517 static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp,
6518 struct sk_buff *skb, u32 *opts)
6520 u32 mss = skb_shinfo(skb)->gso_size;
6524 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
6525 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6526 const struct iphdr *ip = ip_hdr(skb);
6528 if (ip->protocol == IPPROTO_TCP)
6529 opts[0] |= TD0_IP_CS | TD0_TCP_CS;
6530 else if (ip->protocol == IPPROTO_UDP)
6531 opts[0] |= TD0_IP_CS | TD0_UDP_CS;
6539 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
6540 struct sk_buff *skb, u32 *opts)
6542 u32 transport_offset = (u32)skb_transport_offset(skb);
6543 u32 mss = skb_shinfo(skb)->gso_size;
6546 if (transport_offset > GTTCPHO_MAX) {
6547 netif_warn(tp, tx_err, tp->dev,
6548 "Invalid transport offset 0x%x for TSO\n",
6553 switch (vlan_get_protocol(skb)) {
6554 case htons(ETH_P_IP):
6555 opts[0] |= TD1_GTSENV4;
6558 case htons(ETH_P_IPV6):
6559 if (msdn_giant_send_check(skb))
6562 opts[0] |= TD1_GTSENV6;
6570 opts[0] |= transport_offset << GTTCPHO_SHIFT;
6571 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
6572 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6575 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
6576 return !(skb_checksum_help(skb) || eth_skb_pad(skb));
6578 if (transport_offset > TCPHO_MAX) {
6579 netif_warn(tp, tx_err, tp->dev,
6580 "Invalid transport offset 0x%x\n",
6585 switch (vlan_get_protocol(skb)) {
6586 case htons(ETH_P_IP):
6587 opts[1] |= TD1_IPv4_CS;
6588 ip_protocol = ip_hdr(skb)->protocol;
6591 case htons(ETH_P_IPV6):
6592 opts[1] |= TD1_IPv6_CS;
6593 ip_protocol = ipv6_hdr(skb)->nexthdr;
6597 ip_protocol = IPPROTO_RAW;
6601 if (ip_protocol == IPPROTO_TCP)
6602 opts[1] |= TD1_TCP_CS;
6603 else if (ip_protocol == IPPROTO_UDP)
6604 opts[1] |= TD1_UDP_CS;
6608 opts[1] |= transport_offset << TCPHO_SHIFT;
6610 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
6611 return !eth_skb_pad(skb);
6617 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6618 struct net_device *dev)
6620 struct rtl8169_private *tp = netdev_priv(dev);
6621 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
6622 struct TxDesc *txd = tp->TxDescArray + entry;
6623 struct device *d = tp_to_dev(tp);
6629 if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
6630 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
6634 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
6637 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
6640 if (!tp->tso_csum(tp, skb, opts)) {
6641 r8169_csum_workaround(tp, skb);
6642 return NETDEV_TX_OK;
6645 len = skb_headlen(skb);
6646 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
6647 if (unlikely(dma_mapping_error(d, mapping))) {
6648 if (net_ratelimit())
6649 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
6653 tp->tx_skb[entry].len = len;
6654 txd->addr = cpu_to_le64(mapping);
6656 frags = rtl8169_xmit_frags(tp, skb, opts);
6660 opts[0] |= FirstFrag;
6662 opts[0] |= FirstFrag | LastFrag;
6663 tp->tx_skb[entry].skb = skb;
6666 txd->opts2 = cpu_to_le32(opts[1]);
6668 skb_tx_timestamp(skb);
6670 /* Force memory writes to complete before releasing descriptor */
6673 /* Anti gcc 2.95.3 bugware (sic) */
6674 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
6675 txd->opts1 = cpu_to_le32(status);
6677 /* Force all memory writes to complete before notifying device */
6680 tp->cur_tx += frags + 1;
6682 RTL_W8(tp, TxPoll, NPQ);
6686 if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
6687 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
6688 * not miss a ring update when it notices a stopped queue.
6691 netif_stop_queue(dev);
6692 /* Sync with rtl_tx:
6693 * - publish queue status and cur_tx ring index (write barrier)
6694 * - refresh dirty_tx ring index (read barrier).
6695 * May the current thread have a pessimistic view of the ring
6696 * status and forget to wake up queue, a racing rtl_tx thread
6700 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
6701 netif_wake_queue(dev);
6704 return NETDEV_TX_OK;
6707 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
6709 dev_kfree_skb_any(skb);
6710 dev->stats.tx_dropped++;
6711 return NETDEV_TX_OK;
6714 netif_stop_queue(dev);
6715 dev->stats.tx_dropped++;
6716 return NETDEV_TX_BUSY;
6719 static void rtl8169_pcierr_interrupt(struct net_device *dev)
6721 struct rtl8169_private *tp = netdev_priv(dev);
6722 struct pci_dev *pdev = tp->pci_dev;
6723 u16 pci_status, pci_cmd;
6725 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
6726 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
6728 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
6729 pci_cmd, pci_status);
6732 * The recovery sequence below admits a very elaborated explanation:
6733 * - it seems to work;
6734 * - I did not see what else could be done;
6735 * - it makes iop3xx happy.
6737 * Feel free to adjust to your needs.
6739 if (pdev->broken_parity_status)
6740 pci_cmd &= ~PCI_COMMAND_PARITY;
6742 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
6744 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
6746 pci_write_config_word(pdev, PCI_STATUS,
6747 pci_status & (PCI_STATUS_DETECTED_PARITY |
6748 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
6749 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
6751 /* The infamous DAC f*ckup only happens at boot time */
6752 if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
6753 netif_info(tp, intr, dev, "disabling PCI DAC\n");
6754 tp->cp_cmd &= ~PCIDAC;
6755 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
6756 dev->features &= ~NETIF_F_HIGHDMA;
6759 rtl8169_hw_reset(tp);
6761 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6764 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
6766 unsigned int dirty_tx, tx_left;
6768 dirty_tx = tp->dirty_tx;
6770 tx_left = tp->cur_tx - dirty_tx;
6772 while (tx_left > 0) {
6773 unsigned int entry = dirty_tx % NUM_TX_DESC;
6774 struct ring_info *tx_skb = tp->tx_skb + entry;
6777 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
6778 if (status & DescOwn)
6781 /* This barrier is needed to keep us from reading
6782 * any other fields out of the Tx descriptor until
6783 * we know the status of DescOwn
6787 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
6788 tp->TxDescArray + entry);
6789 if (status & LastFrag) {
6790 u64_stats_update_begin(&tp->tx_stats.syncp);
6791 tp->tx_stats.packets++;
6792 tp->tx_stats.bytes += tx_skb->skb->len;
6793 u64_stats_update_end(&tp->tx_stats.syncp);
6794 dev_consume_skb_any(tx_skb->skb);
6801 if (tp->dirty_tx != dirty_tx) {
6802 tp->dirty_tx = dirty_tx;
6803 /* Sync with rtl8169_start_xmit:
6804 * - publish dirty_tx ring index (write barrier)
6805 * - refresh cur_tx ring index and queue status (read barrier)
6806 * May the current thread miss the stopped queue condition,
6807 * a racing xmit thread can only have a right view of the
6811 if (netif_queue_stopped(dev) &&
6812 TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
6813 netif_wake_queue(dev);
6816 * 8168 hack: TxPoll requests are lost when the Tx packets are
6817 * too close. Let's kick an extra TxPoll request when a burst
6818 * of start_xmit activity is detected (if it is not detected,
6819 * it is slow enough). -- FR
6821 if (tp->cur_tx != dirty_tx)
6822 RTL_W8(tp, TxPoll, NPQ);
6826 static inline int rtl8169_fragmented_frame(u32 status)
6828 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
6831 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
6833 u32 status = opts1 & RxProtoMask;
6835 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
6836 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
6837 skb->ip_summed = CHECKSUM_UNNECESSARY;
6839 skb_checksum_none_assert(skb);
6842 static struct sk_buff *rtl8169_try_rx_copy(void *data,
6843 struct rtl8169_private *tp,
6847 struct sk_buff *skb;
6848 struct device *d = tp_to_dev(tp);
6850 data = rtl8169_align(data);
6851 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6853 skb = napi_alloc_skb(&tp->napi, pkt_size);
6855 skb_copy_to_linear_data(skb, data, pkt_size);
6856 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
6861 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
6863 unsigned int cur_rx, rx_left;
6866 cur_rx = tp->cur_rx;
6868 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
6869 unsigned int entry = cur_rx % NUM_RX_DESC;
6870 struct RxDesc *desc = tp->RxDescArray + entry;
6873 status = le32_to_cpu(desc->opts1);
6874 if (status & DescOwn)
6877 /* This barrier is needed to keep us from reading
6878 * any other fields out of the Rx descriptor until
6879 * we know the status of DescOwn
6883 if (unlikely(status & RxRES)) {
6884 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
6886 dev->stats.rx_errors++;
6887 if (status & (RxRWT | RxRUNT))
6888 dev->stats.rx_length_errors++;
6890 dev->stats.rx_crc_errors++;
6891 /* RxFOVF is a reserved bit on later chip versions */
6892 if (tp->mac_version == RTL_GIGA_MAC_VER_01 &&
6894 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6895 dev->stats.rx_fifo_errors++;
6896 } else if (status & (RxRUNT | RxCRC) &&
6897 !(status & RxRWT) &&
6898 dev->features & NETIF_F_RXALL) {
6902 struct sk_buff *skb;
6907 addr = le64_to_cpu(desc->addr);
6908 if (likely(!(dev->features & NETIF_F_RXFCS)))
6909 pkt_size = (status & 0x00003fff) - 4;
6911 pkt_size = status & 0x00003fff;
6914 * The driver does not support incoming fragmented
6915 * frames. They are seen as a symptom of over-mtu
6918 if (unlikely(rtl8169_fragmented_frame(status))) {
6919 dev->stats.rx_dropped++;
6920 dev->stats.rx_length_errors++;
6921 goto release_descriptor;
6924 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
6925 tp, pkt_size, addr);
6927 dev->stats.rx_dropped++;
6928 goto release_descriptor;
6931 rtl8169_rx_csum(skb, status);
6932 skb_put(skb, pkt_size);
6933 skb->protocol = eth_type_trans(skb, dev);
6935 rtl8169_rx_vlan_tag(desc, skb);
6937 if (skb->pkt_type == PACKET_MULTICAST)
6938 dev->stats.multicast++;
6940 napi_gro_receive(&tp->napi, skb);
6942 u64_stats_update_begin(&tp->rx_stats.syncp);
6943 tp->rx_stats.packets++;
6944 tp->rx_stats.bytes += pkt_size;
6945 u64_stats_update_end(&tp->rx_stats.syncp);
6949 rtl8169_mark_to_asic(desc);
6952 count = cur_rx - tp->cur_rx;
6953 tp->cur_rx = cur_rx;
6958 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
6960 struct rtl8169_private *tp = dev_instance;
6964 status = rtl_get_events(tp);
6965 if (status && status != 0xffff) {
6966 status &= RTL_EVENT_NAPI | tp->event_slow;
6970 rtl_irq_disable(tp);
6971 napi_schedule_irqoff(&tp->napi);
6974 return IRQ_RETVAL(handled);
6978 * Workqueue context.
6980 static void rtl_slow_event_work(struct rtl8169_private *tp)
6982 struct net_device *dev = tp->dev;
6985 status = rtl_get_events(tp) & tp->event_slow;
6986 rtl_ack_events(tp, status);
6988 if (unlikely(status & RxFIFOOver)) {
6989 switch (tp->mac_version) {
6990 /* Work around for rx fifo overflow */
6991 case RTL_GIGA_MAC_VER_11:
6992 netif_stop_queue(dev);
6993 /* XXX - Hack alert. See rtl_task(). */
6994 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
7000 if (unlikely(status & SYSErr))
7001 rtl8169_pcierr_interrupt(dev);
7003 if (status & LinkChg)
7004 rtl8169_check_link_status(dev, tp);
7006 rtl_irq_enable_all(tp);
7009 static void rtl_task(struct work_struct *work)
7011 static const struct {
7013 void (*action)(struct rtl8169_private *);
7015 /* XXX - keep rtl_slow_event_work() as first element. */
7016 { RTL_FLAG_TASK_SLOW_PENDING, rtl_slow_event_work },
7017 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
7018 { RTL_FLAG_TASK_PHY_PENDING, rtl_phy_work }
7020 struct rtl8169_private *tp =
7021 container_of(work, struct rtl8169_private, wk.work);
7022 struct net_device *dev = tp->dev;
7027 if (!netif_running(dev) ||
7028 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
7031 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
7034 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
7036 rtl_work[i].action(tp);
7040 rtl_unlock_work(tp);
7043 static int rtl8169_poll(struct napi_struct *napi, int budget)
7045 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
7046 struct net_device *dev = tp->dev;
7047 u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
7051 status = rtl_get_events(tp);
7052 rtl_ack_events(tp, status & ~tp->event_slow);
7054 if (status & RTL_EVENT_NAPI_RX)
7055 work_done = rtl_rx(dev, tp, (u32) budget);
7057 if (status & RTL_EVENT_NAPI_TX)
7060 if (status & tp->event_slow) {
7061 enable_mask &= ~tp->event_slow;
7063 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
7066 if (work_done < budget) {
7067 napi_complete_done(napi, work_done);
7069 rtl_irq_enable(tp, enable_mask);
7076 static void rtl8169_rx_missed(struct net_device *dev)
7078 struct rtl8169_private *tp = netdev_priv(dev);
7080 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
7083 dev->stats.rx_missed_errors += RTL_R32(tp, RxMissed) & 0xffffff;
7084 RTL_W32(tp, RxMissed, 0);
7087 static void rtl8169_down(struct net_device *dev)
7089 struct rtl8169_private *tp = netdev_priv(dev);
7091 del_timer_sync(&tp->timer);
7093 napi_disable(&tp->napi);
7094 netif_stop_queue(dev);
7096 rtl8169_hw_reset(tp);
7098 * At this point device interrupts can not be enabled in any function,
7099 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
7100 * and napi is disabled (rtl8169_poll).
7102 rtl8169_rx_missed(dev);
7104 /* Give a racing hard_start_xmit a few cycles to complete. */
7105 synchronize_sched();
7107 rtl8169_tx_clear(tp);
7109 rtl8169_rx_clear(tp);
7111 rtl_pll_power_down(tp);
7114 static int rtl8169_close(struct net_device *dev)
7116 struct rtl8169_private *tp = netdev_priv(dev);
7117 struct pci_dev *pdev = tp->pci_dev;
7119 pm_runtime_get_sync(&pdev->dev);
7121 /* Update counters before going down */
7122 rtl8169_update_counters(tp);
7125 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7128 rtl_unlock_work(tp);
7130 cancel_work_sync(&tp->wk.work);
7132 pci_free_irq(pdev, 0, tp);
7134 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
7136 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
7138 tp->TxDescArray = NULL;
7139 tp->RxDescArray = NULL;
7141 pm_runtime_put_sync(&pdev->dev);
7146 #ifdef CONFIG_NET_POLL_CONTROLLER
7147 static void rtl8169_netpoll(struct net_device *dev)
7149 struct rtl8169_private *tp = netdev_priv(dev);
7151 rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp);
7155 static int rtl_open(struct net_device *dev)
7157 struct rtl8169_private *tp = netdev_priv(dev);
7158 struct pci_dev *pdev = tp->pci_dev;
7159 int retval = -ENOMEM;
7161 pm_runtime_get_sync(&pdev->dev);
7164 * Rx and Tx descriptors needs 256 bytes alignment.
7165 * dma_alloc_coherent provides more.
7167 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
7168 &tp->TxPhyAddr, GFP_KERNEL);
7169 if (!tp->TxDescArray)
7170 goto err_pm_runtime_put;
7172 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
7173 &tp->RxPhyAddr, GFP_KERNEL);
7174 if (!tp->RxDescArray)
7177 retval = rtl8169_init_ring(tp);
7181 INIT_WORK(&tp->wk.work, rtl_task);
7185 rtl_request_firmware(tp);
7187 retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, tp,
7190 goto err_release_fw_2;
7194 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7196 napi_enable(&tp->napi);
7198 rtl8169_init_phy(dev, tp);
7200 rtl_pll_power_up(tp);
7204 if (!rtl8169_init_counter_offsets(tp))
7205 netif_warn(tp, hw, dev, "counter reset/update failed\n");
7207 netif_start_queue(dev);
7209 rtl_unlock_work(tp);
7211 tp->saved_wolopts = 0;
7212 pm_runtime_put_sync(&pdev->dev);
7214 rtl8169_check_link_status(dev, tp);
7219 rtl_release_firmware(tp);
7220 rtl8169_rx_clear(tp);
7222 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
7224 tp->RxDescArray = NULL;
7226 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
7228 tp->TxDescArray = NULL;
7230 pm_runtime_put_noidle(&pdev->dev);
7235 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
7237 struct rtl8169_private *tp = netdev_priv(dev);
7238 struct pci_dev *pdev = tp->pci_dev;
7239 struct rtl8169_counters *counters = tp->counters;
7242 pm_runtime_get_noresume(&pdev->dev);
7244 if (netif_running(dev) && pm_runtime_active(&pdev->dev))
7245 rtl8169_rx_missed(dev);
7248 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
7249 stats->rx_packets = tp->rx_stats.packets;
7250 stats->rx_bytes = tp->rx_stats.bytes;
7251 } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
7254 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
7255 stats->tx_packets = tp->tx_stats.packets;
7256 stats->tx_bytes = tp->tx_stats.bytes;
7257 } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
7259 stats->rx_dropped = dev->stats.rx_dropped;
7260 stats->tx_dropped = dev->stats.tx_dropped;
7261 stats->rx_length_errors = dev->stats.rx_length_errors;
7262 stats->rx_errors = dev->stats.rx_errors;
7263 stats->rx_crc_errors = dev->stats.rx_crc_errors;
7264 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
7265 stats->rx_missed_errors = dev->stats.rx_missed_errors;
7266 stats->multicast = dev->stats.multicast;
7269 * Fetch additonal counter values missing in stats collected by driver
7270 * from tally counters.
7272 if (pm_runtime_active(&pdev->dev))
7273 rtl8169_update_counters(tp);
7276 * Subtract values fetched during initalization.
7277 * See rtl8169_init_counter_offsets for a description why we do that.
7279 stats->tx_errors = le64_to_cpu(counters->tx_errors) -
7280 le64_to_cpu(tp->tc_offset.tx_errors);
7281 stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
7282 le32_to_cpu(tp->tc_offset.tx_multi_collision);
7283 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
7284 le16_to_cpu(tp->tc_offset.tx_aborted);
7286 pm_runtime_put_noidle(&pdev->dev);
7289 static void rtl8169_net_suspend(struct net_device *dev)
7291 struct rtl8169_private *tp = netdev_priv(dev);
7293 if (!netif_running(dev))
7296 netif_device_detach(dev);
7297 netif_stop_queue(dev);
7300 napi_disable(&tp->napi);
7301 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7302 rtl_unlock_work(tp);
7304 rtl_pll_power_down(tp);
7309 static int rtl8169_suspend(struct device *device)
7311 struct pci_dev *pdev = to_pci_dev(device);
7312 struct net_device *dev = pci_get_drvdata(pdev);
7314 rtl8169_net_suspend(dev);
7319 static void __rtl8169_resume(struct net_device *dev)
7321 struct rtl8169_private *tp = netdev_priv(dev);
7323 netif_device_attach(dev);
7325 rtl_pll_power_up(tp);
7328 napi_enable(&tp->napi);
7329 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7330 rtl_unlock_work(tp);
7332 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
7335 static int rtl8169_resume(struct device *device)
7337 struct pci_dev *pdev = to_pci_dev(device);
7338 struct net_device *dev = pci_get_drvdata(pdev);
7339 struct rtl8169_private *tp = netdev_priv(dev);
7341 rtl8169_init_phy(dev, tp);
7343 if (netif_running(dev))
7344 __rtl8169_resume(dev);
7349 static int rtl8169_runtime_suspend(struct device *device)
7351 struct pci_dev *pdev = to_pci_dev(device);
7352 struct net_device *dev = pci_get_drvdata(pdev);
7353 struct rtl8169_private *tp = netdev_priv(dev);
7355 if (!tp->TxDescArray) {
7356 rtl_pll_power_down(tp);
7361 tp->saved_wolopts = __rtl8169_get_wol(tp);
7362 __rtl8169_set_wol(tp, WAKE_ANY);
7363 rtl_unlock_work(tp);
7365 rtl8169_net_suspend(dev);
7367 /* Update counters before going runtime suspend */
7368 rtl8169_rx_missed(dev);
7369 rtl8169_update_counters(tp);
7374 static int rtl8169_runtime_resume(struct device *device)
7376 struct pci_dev *pdev = to_pci_dev(device);
7377 struct net_device *dev = pci_get_drvdata(pdev);
7378 struct rtl8169_private *tp = netdev_priv(dev);
7379 rtl_rar_set(tp, dev->dev_addr);
7381 if (!tp->TxDescArray)
7385 __rtl8169_set_wol(tp, tp->saved_wolopts);
7386 tp->saved_wolopts = 0;
7387 rtl_unlock_work(tp);
7389 rtl8169_init_phy(dev, tp);
7391 __rtl8169_resume(dev);
7396 static int rtl8169_runtime_idle(struct device *device)
7398 struct pci_dev *pdev = to_pci_dev(device);
7399 struct net_device *dev = pci_get_drvdata(pdev);
7401 if (!netif_running(dev) || !netif_carrier_ok(dev))
7402 pm_schedule_suspend(device, 10000);
7407 static const struct dev_pm_ops rtl8169_pm_ops = {
7408 .suspend = rtl8169_suspend,
7409 .resume = rtl8169_resume,
7410 .freeze = rtl8169_suspend,
7411 .thaw = rtl8169_resume,
7412 .poweroff = rtl8169_suspend,
7413 .restore = rtl8169_resume,
7414 .runtime_suspend = rtl8169_runtime_suspend,
7415 .runtime_resume = rtl8169_runtime_resume,
7416 .runtime_idle = rtl8169_runtime_idle,
7419 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
7421 #else /* !CONFIG_PM */
7423 #define RTL8169_PM_OPS NULL
7425 #endif /* !CONFIG_PM */
7427 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
7429 /* WoL fails with 8168b when the receiver is disabled. */
7430 switch (tp->mac_version) {
7431 case RTL_GIGA_MAC_VER_11:
7432 case RTL_GIGA_MAC_VER_12:
7433 case RTL_GIGA_MAC_VER_17:
7434 pci_clear_master(tp->pci_dev);
7436 RTL_W8(tp, ChipCmd, CmdRxEnb);
7438 RTL_R8(tp, ChipCmd);
7445 static void rtl_shutdown(struct pci_dev *pdev)
7447 struct net_device *dev = pci_get_drvdata(pdev);
7448 struct rtl8169_private *tp = netdev_priv(dev);
7450 rtl8169_net_suspend(dev);
7452 /* Restore original MAC address */
7453 rtl_rar_set(tp, dev->perm_addr);
7455 rtl8169_hw_reset(tp);
7457 if (system_state == SYSTEM_POWER_OFF) {
7458 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
7459 rtl_wol_suspend_quirk(tp);
7460 rtl_wol_shutdown_quirk(tp);
7463 pci_wake_from_d3(pdev, true);
7464 pci_set_power_state(pdev, PCI_D3hot);
7468 static void rtl_remove_one(struct pci_dev *pdev)
7470 struct net_device *dev = pci_get_drvdata(pdev);
7471 struct rtl8169_private *tp = netdev_priv(dev);
7473 if (r8168_check_dash(tp))
7474 rtl8168_driver_stop(tp);
7476 netif_napi_del(&tp->napi);
7478 unregister_netdev(dev);
7480 rtl_release_firmware(tp);
7482 if (pci_dev_run_wake(pdev))
7483 pm_runtime_get_noresume(&pdev->dev);
7485 /* restore original MAC address */
7486 rtl_rar_set(tp, dev->perm_addr);
7489 static const struct net_device_ops rtl_netdev_ops = {
7490 .ndo_open = rtl_open,
7491 .ndo_stop = rtl8169_close,
7492 .ndo_get_stats64 = rtl8169_get_stats64,
7493 .ndo_start_xmit = rtl8169_start_xmit,
7494 .ndo_tx_timeout = rtl8169_tx_timeout,
7495 .ndo_validate_addr = eth_validate_addr,
7496 .ndo_change_mtu = rtl8169_change_mtu,
7497 .ndo_fix_features = rtl8169_fix_features,
7498 .ndo_set_features = rtl8169_set_features,
7499 .ndo_set_mac_address = rtl_set_mac_address,
7500 .ndo_do_ioctl = rtl8169_ioctl,
7501 .ndo_set_rx_mode = rtl_set_rx_mode,
7502 #ifdef CONFIG_NET_POLL_CONTROLLER
7503 .ndo_poll_controller = rtl8169_netpoll,
7508 static const struct rtl_cfg_info {
7509 void (*hw_start)(struct rtl8169_private *tp);
7511 unsigned int has_gmii:1;
7512 const struct rtl_coalesce_info *coalesce_info;
7514 } rtl_cfg_infos [] = {
7516 .hw_start = rtl_hw_start_8169,
7517 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
7519 .coalesce_info = rtl_coalesce_info_8169,
7520 .default_ver = RTL_GIGA_MAC_VER_01,
7523 .hw_start = rtl_hw_start_8168,
7524 .event_slow = SYSErr | LinkChg | RxOverflow,
7526 .coalesce_info = rtl_coalesce_info_8168_8136,
7527 .default_ver = RTL_GIGA_MAC_VER_11,
7530 .hw_start = rtl_hw_start_8101,
7531 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
7533 .coalesce_info = rtl_coalesce_info_8168_8136,
7534 .default_ver = RTL_GIGA_MAC_VER_13,
7538 static int rtl_alloc_irq(struct rtl8169_private *tp)
7542 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
7543 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
7544 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
7545 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
7546 flags = PCI_IRQ_LEGACY;
7548 flags = PCI_IRQ_ALL_TYPES;
7551 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
7554 DECLARE_RTL_COND(rtl_link_list_ready_cond)
7556 return RTL_R8(tp, MCU) & LINK_LIST_RDY;
7559 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
7561 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
7564 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
7568 tp->ocp_base = OCP_STD_PHY_BASE;
7570 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
7572 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
7575 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
7578 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
7580 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
7582 data = r8168_mac_ocp_read(tp, 0xe8de);
7584 r8168_mac_ocp_write(tp, 0xe8de, data);
7586 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7589 data = r8168_mac_ocp_read(tp, 0xe8de);
7591 r8168_mac_ocp_write(tp, 0xe8de, data);
7593 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7597 static void rtl_hw_init_8168ep(struct rtl8169_private *tp)
7599 rtl8168ep_stop_cmac(tp);
7600 rtl_hw_init_8168g(tp);
7603 static void rtl_hw_initialize(struct rtl8169_private *tp)
7605 switch (tp->mac_version) {
7606 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
7607 rtl_hw_init_8168g(tp);
7609 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_51:
7610 rtl_hw_init_8168ep(tp);
7617 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7619 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
7620 struct rtl8169_private *tp;
7621 struct mii_if_info *mii;
7622 struct net_device *dev;
7623 int chipset, region, i;
7626 if (netif_msg_drv(&debug)) {
7627 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
7628 MODULENAME, RTL8169_VERSION);
7631 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
7635 SET_NETDEV_DEV(dev, &pdev->dev);
7636 dev->netdev_ops = &rtl_netdev_ops;
7637 tp = netdev_priv(dev);
7640 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
7644 mii->mdio_read = rtl_mdio_read;
7645 mii->mdio_write = rtl_mdio_write;
7646 mii->phy_id_mask = 0x1f;
7647 mii->reg_num_mask = 0x1f;
7648 mii->supports_gmii = cfg->has_gmii;
7650 /* disable ASPM completely as that cause random device stop working
7651 * problems as well as full system hangs for some PCIe devices users */
7652 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
7653 PCIE_LINK_STATE_CLKPM);
7655 /* enable device (incl. PCI PM wakeup and hotplug setup) */
7656 rc = pcim_enable_device(pdev);
7658 dev_err(&pdev->dev, "enable failure\n");
7662 if (pcim_set_mwi(pdev) < 0)
7663 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
7665 /* use first MMIO region */
7666 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
7668 dev_err(&pdev->dev, "no MMIO resource found\n");
7672 /* check for weird/broken PCI region reporting */
7673 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
7674 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
7678 rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME);
7680 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
7684 tp->mmio_addr = pcim_iomap_table(pdev)[region];
7686 if (!pci_is_pcie(pdev))
7687 dev_info(&pdev->dev, "not PCI Express\n");
7689 /* Identify chip attached to board */
7690 rtl8169_get_mac_version(tp, cfg->default_ver);
7692 tp->cp_cmd = RTL_R16(tp, CPlusCmd);
7694 if ((sizeof(dma_addr_t) > 4) &&
7695 (use_dac == 1 || (use_dac == -1 && pci_is_pcie(pdev) &&
7696 tp->mac_version >= RTL_GIGA_MAC_VER_18)) &&
7697 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
7698 !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
7700 /* CPlusCmd Dual Access Cycle is only needed for non-PCIe */
7701 if (!pci_is_pcie(pdev))
7702 tp->cp_cmd |= PCIDAC;
7703 dev->features |= NETIF_F_HIGHDMA;
7705 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
7707 dev_err(&pdev->dev, "DMA configuration failed\n");
7714 rtl_irq_disable(tp);
7716 rtl_hw_initialize(tp);
7720 rtl_ack_events(tp, 0xffff);
7722 pci_set_master(pdev);
7724 rtl_init_mdio_ops(tp);
7725 rtl_init_jumbo_ops(tp);
7727 rtl8169_print_mac_version(tp);
7729 chipset = tp->mac_version;
7731 rc = rtl_alloc_irq(tp);
7733 dev_err(&pdev->dev, "Can't allocate interrupt\n");
7737 /* override BIOS settings, use userspace tools to enable WOL */
7738 __rtl8169_set_wol(tp, 0);
7740 if (rtl_tbi_enabled(tp)) {
7741 tp->set_speed = rtl8169_set_speed_tbi;
7742 tp->get_link_ksettings = rtl8169_get_link_ksettings_tbi;
7743 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
7744 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
7745 tp->link_ok = rtl8169_tbi_link_ok;
7746 tp->do_ioctl = rtl_tbi_ioctl;
7748 tp->set_speed = rtl8169_set_speed_xmii;
7749 tp->get_link_ksettings = rtl8169_get_link_ksettings_xmii;
7750 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
7751 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
7752 tp->link_ok = rtl8169_xmii_link_ok;
7753 tp->do_ioctl = rtl_xmii_ioctl;
7756 mutex_init(&tp->wk.mutex);
7757 u64_stats_init(&tp->rx_stats.syncp);
7758 u64_stats_init(&tp->tx_stats.syncp);
7760 /* Get MAC address */
7761 switch (tp->mac_version) {
7762 u8 mac_addr[ETH_ALEN] __aligned(4);
7763 case RTL_GIGA_MAC_VER_35 ... RTL_GIGA_MAC_VER_38:
7764 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
7765 *(u32 *)&mac_addr[0] = rtl_eri_read(tp, 0xe0, ERIAR_EXGMAC);
7766 *(u16 *)&mac_addr[4] = rtl_eri_read(tp, 0xe4, ERIAR_EXGMAC);
7768 if (is_valid_ether_addr(mac_addr))
7769 rtl_rar_set(tp, mac_addr);
7774 for (i = 0; i < ETH_ALEN; i++)
7775 dev->dev_addr[i] = RTL_R8(tp, MAC0 + i);
7777 dev->ethtool_ops = &rtl8169_ethtool_ops;
7778 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
7780 netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT);
7782 /* don't enable SG, IP_CSUM and TSO by default - it might not work
7783 * properly for all devices */
7784 dev->features |= NETIF_F_RXCSUM |
7785 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
7787 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7788 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
7789 NETIF_F_HW_VLAN_CTAG_RX;
7790 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7792 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
7794 tp->cp_cmd |= RxChkSum | RxVlan;
7797 * Pretend we are using VLANs; This bypasses a nasty bug where
7798 * Interrupts stop flowing on high load on 8110SCd controllers.
7800 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
7801 /* Disallow toggling */
7802 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
7804 switch (rtl_chip_infos[chipset].txd_version) {
7806 tp->tso_csum = rtl8169_tso_csum_v1;
7809 tp->tso_csum = rtl8169_tso_csum_v2;
7810 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
7816 dev->hw_features |= NETIF_F_RXALL;
7817 dev->hw_features |= NETIF_F_RXFCS;
7819 /* MTU range: 60 - hw-specific max */
7820 dev->min_mtu = ETH_ZLEN;
7821 dev->max_mtu = rtl_chip_infos[chipset].jumbo_max;
7823 tp->hw_start = cfg->hw_start;
7824 tp->event_slow = cfg->event_slow;
7825 tp->coalesce_info = cfg->coalesce_info;
7827 timer_setup(&tp->timer, rtl8169_phy_timer, 0);
7829 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
7831 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
7832 &tp->counters_phys_addr,
7837 pci_set_drvdata(pdev, dev);
7839 rc = register_netdev(dev);
7843 netif_info(tp, probe, dev, "%s, %pM, XID %08x, IRQ %d\n",
7844 rtl_chip_infos[chipset].name, dev->dev_addr,
7845 (u32)(RTL_R32(tp, TxConfig) & 0xfcf0f8ff),
7846 pci_irq_vector(pdev, 0));
7847 if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
7848 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
7849 "tx checksumming: %s]\n",
7850 rtl_chip_infos[chipset].jumbo_max,
7851 tp->mac_version <= RTL_GIGA_MAC_VER_06 ? "ok" : "ko");
7854 if (r8168_check_dash(tp))
7855 rtl8168_driver_start(tp);
7857 netif_carrier_off(dev);
7859 if (pci_dev_run_wake(pdev))
7860 pm_runtime_put_sync(&pdev->dev);
7865 static struct pci_driver rtl8169_pci_driver = {
7867 .id_table = rtl8169_pci_tbl,
7868 .probe = rtl_init_one,
7869 .remove = rtl_remove_one,
7870 .shutdown = rtl_shutdown,
7871 .driver.pm = RTL8169_PM_OPS,
7874 module_pci_driver(rtl8169_pci_driver);