drivers/net/ethernet/realtek/r8169.c

   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/clk.h>
  17 #include <linux/delay.h>
  18 #include <linux/ethtool.h>
  19 #include <linux/phy.h>
  20 #include <linux/if_vlan.h>
  21 #include <linux/crc32.h>
  22 #include <linux/in.h>
  23 #include <linux/io.h>
  24 #include <linux/ip.h>
  25 #include <linux/tcp.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/dma-mapping.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/firmware.h>
  30 #include <linux/prefetch.h>
  31 #include <linux/ipv6.h>
  32 #include <net/ip6_checksum.h>
  33
  34 #define MODULENAME "r8169"
  35
  36 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  37 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  38 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  39 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  40 #define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
  41 #define FIRMWARE_8168F_1        "rtl_nic/rtl8168f-1.fw"
  42 #define FIRMWARE_8168F_2        "rtl_nic/rtl8168f-2.fw"
  43 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  44 #define FIRMWARE_8402_1         "rtl_nic/rtl8402-1.fw"
  45 #define FIRMWARE_8411_1         "rtl_nic/rtl8411-1.fw"
  46 #define FIRMWARE_8411_2         "rtl_nic/rtl8411-2.fw"
  47 #define FIRMWARE_8106E_1        "rtl_nic/rtl8106e-1.fw"
  48 #define FIRMWARE_8106E_2        "rtl_nic/rtl8106e-2.fw"
  49 #define FIRMWARE_8168G_2        "rtl_nic/rtl8168g-2.fw"
  50 #define FIRMWARE_8168G_3        "rtl_nic/rtl8168g-3.fw"
  51 #define FIRMWARE_8168H_1        "rtl_nic/rtl8168h-1.fw"
  52 #define FIRMWARE_8168H_2        "rtl_nic/rtl8168h-2.fw"
  53 #define FIRMWARE_8107E_1        "rtl_nic/rtl8107e-1.fw"
  54 #define FIRMWARE_8107E_2        "rtl_nic/rtl8107e-2.fw"
  55
  56 #define R8169_MSG_DEFAULT \
  57         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  58
  59 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  60    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  61 static const int multicast_filter_limit = 32;
  62
  63 #define TX_DMA_BURST    7       /* Maximum PCI burst, '7' is unlimited */
  64 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  65
  66 #define R8169_REGS_SIZE         256
  67 #define R8169_RX_BUF_SIZE       (SZ_16K - 1)
  68 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  69 #define NUM_RX_DESC     256U    /* Number of Rx descriptor registers */
  70 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  71 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  72
  73 /* write/read MMIO register */
  74 #define RTL_W8(tp, reg, val8)   writeb((val8), tp->mmio_addr + (reg))
  75 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
  76 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
  77 #define RTL_R8(tp, reg)         readb(tp->mmio_addr + (reg))
  78 #define RTL_R16(tp, reg)                readw(tp->mmio_addr + (reg))
  79 #define RTL_R32(tp, reg)                readl(tp->mmio_addr + (reg))
  80
  81 enum mac_version {
  82         RTL_GIGA_MAC_VER_01 = 0,
  83         RTL_GIGA_MAC_VER_02,
  84         RTL_GIGA_MAC_VER_03,
  85         RTL_GIGA_MAC_VER_04,
  86         RTL_GIGA_MAC_VER_05,
  87         RTL_GIGA_MAC_VER_06,
  88         RTL_GIGA_MAC_VER_07,
  89         RTL_GIGA_MAC_VER_08,
  90         RTL_GIGA_MAC_VER_09,
  91         RTL_GIGA_MAC_VER_10,
  92         RTL_GIGA_MAC_VER_11,
  93         RTL_GIGA_MAC_VER_12,
  94         RTL_GIGA_MAC_VER_13,
  95         RTL_GIGA_MAC_VER_14,
  96         RTL_GIGA_MAC_VER_15,
  97         RTL_GIGA_MAC_VER_16,
  98         RTL_GIGA_MAC_VER_17,
  99         RTL_GIGA_MAC_VER_18,
 100         RTL_GIGA_MAC_VER_19,
 101         RTL_GIGA_MAC_VER_20,
 102         RTL_GIGA_MAC_VER_21,
 103         RTL_GIGA_MAC_VER_22,
 104         RTL_GIGA_MAC_VER_23,
 105         RTL_GIGA_MAC_VER_24,
 106         RTL_GIGA_MAC_VER_25,
 107         RTL_GIGA_MAC_VER_26,
 108         RTL_GIGA_MAC_VER_27,
 109         RTL_GIGA_MAC_VER_28,
 110         RTL_GIGA_MAC_VER_29,
 111         RTL_GIGA_MAC_VER_30,
 112         RTL_GIGA_MAC_VER_31,
 113         RTL_GIGA_MAC_VER_32,
 114         RTL_GIGA_MAC_VER_33,
 115         RTL_GIGA_MAC_VER_34,
 116         RTL_GIGA_MAC_VER_35,
 117         RTL_GIGA_MAC_VER_36,
 118         RTL_GIGA_MAC_VER_37,
 119         RTL_GIGA_MAC_VER_38,
 120         RTL_GIGA_MAC_VER_39,
 121         RTL_GIGA_MAC_VER_40,
 122         RTL_GIGA_MAC_VER_41,
 123         RTL_GIGA_MAC_VER_42,
 124         RTL_GIGA_MAC_VER_43,
 125         RTL_GIGA_MAC_VER_44,
 126         RTL_GIGA_MAC_VER_45,
 127         RTL_GIGA_MAC_VER_46,
 128         RTL_GIGA_MAC_VER_47,
 129         RTL_GIGA_MAC_VER_48,
 130         RTL_GIGA_MAC_VER_49,
 131         RTL_GIGA_MAC_VER_50,
 132         RTL_GIGA_MAC_VER_51,
 133         RTL_GIGA_MAC_NONE   = 0xff,
 134 };
 135
 136 #define JUMBO_1K        ETH_DATA_LEN
 137 #define JUMBO_4K        (4*1024 - ETH_HLEN - 2)
 138 #define JUMBO_6K        (6*1024 - ETH_HLEN - 2)
 139 #define JUMBO_7K        (7*1024 - ETH_HLEN - 2)
 140 #define JUMBO_9K        (9*1024 - ETH_HLEN - 2)
 141
 142 static const struct {
 143         const char *name;
 144         const char *fw_name;
 145 } rtl_chip_infos[] = {
 146         /* PCI devices. */
 147         [RTL_GIGA_MAC_VER_01] = {"RTL8169"                              },
 148         [RTL_GIGA_MAC_VER_02] = {"RTL8169s"                             },
 149         [RTL_GIGA_MAC_VER_03] = {"RTL8110s"                             },
 150         [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb"                     },
 151         [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc"                     },
 152         [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc"                     },
 153         /* PCI-E devices. */
 154         [RTL_GIGA_MAC_VER_07] = {"RTL8102e"                             },
 155         [RTL_GIGA_MAC_VER_08] = {"RTL8102e"                             },
 156         [RTL_GIGA_MAC_VER_09] = {"RTL8102e"                             },
 157         [RTL_GIGA_MAC_VER_10] = {"RTL8101e"                             },
 158         [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b"                       },
 159         [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b"                       },
 160         [RTL_GIGA_MAC_VER_13] = {"RTL8101e"                             },
 161         [RTL_GIGA_MAC_VER_14] = {"RTL8100e"                             },
 162         [RTL_GIGA_MAC_VER_15] = {"RTL8100e"                             },
 163         [RTL_GIGA_MAC_VER_16] = {"RTL8101e"                             },
 164         [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b"                       },
 165         [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp"                     },
 166         [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c"                       },
 167         [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c"                       },
 168         [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c"                       },
 169         [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c"                       },
 170         [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp"                     },
 171         [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp"                     },
 172         [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d",      FIRMWARE_8168D_1},
 173         [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d",      FIRMWARE_8168D_2},
 174         [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp"                     },
 175         [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp"                     },
 176         [RTL_GIGA_MAC_VER_29] = {"RTL8105e",            FIRMWARE_8105E_1},
 177         [RTL_GIGA_MAC_VER_30] = {"RTL8105e",            FIRMWARE_8105E_1},
 178         [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp"                     },
 179         [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e",      FIRMWARE_8168E_1},
 180         [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e",      FIRMWARE_8168E_2},
 181         [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl",  FIRMWARE_8168E_3},
 182         [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f",      FIRMWARE_8168F_1},
 183         [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f",      FIRMWARE_8168F_2},
 184         [RTL_GIGA_MAC_VER_37] = {"RTL8402",             FIRMWARE_8402_1 },
 185         [RTL_GIGA_MAC_VER_38] = {"RTL8411",             FIRMWARE_8411_1 },
 186         [RTL_GIGA_MAC_VER_39] = {"RTL8106e",            FIRMWARE_8106E_1},
 187         [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g",      FIRMWARE_8168G_2},
 188         [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g"                       },
 189         [RTL_GIGA_MAC_VER_42] = {"RTL8168g/8111g",      FIRMWARE_8168G_3},
 190         [RTL_GIGA_MAC_VER_43] = {"RTL8106e",            FIRMWARE_8106E_2},
 191         [RTL_GIGA_MAC_VER_44] = {"RTL8411",             FIRMWARE_8411_2 },
 192         [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h",      FIRMWARE_8168H_1},
 193         [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h",      FIRMWARE_8168H_2},
 194         [RTL_GIGA_MAC_VER_47] = {"RTL8107e",            FIRMWARE_8107E_1},
 195         [RTL_GIGA_MAC_VER_48] = {"RTL8107e",            FIRMWARE_8107E_2},
 196         [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep"                     },
 197         [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep"                     },
 198         [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep"                     },
 199 };
 200
 201 enum cfg_version {
 202         RTL_CFG_0 = 0x00,
 203         RTL_CFG_1,
 204         RTL_CFG_2
 205 };
 206
 207 static const struct pci_device_id rtl8169_pci_tbl[] = {
 208         { PCI_VDEVICE(REALTEK,  0x2502), RTL_CFG_1 },
 209         { PCI_VDEVICE(REALTEK,  0x2600), RTL_CFG_1 },
 210         { PCI_VDEVICE(REALTEK,  0x8129), RTL_CFG_0 },
 211         { PCI_VDEVICE(REALTEK,  0x8136), RTL_CFG_2 },
 212         { PCI_VDEVICE(REALTEK,  0x8161), RTL_CFG_1 },
 213         { PCI_VDEVICE(REALTEK,  0x8167), RTL_CFG_0 },
 214         { PCI_VDEVICE(REALTEK,  0x8168), RTL_CFG_1 },
 215         { PCI_VDEVICE(NCUBE,    0x8168), RTL_CFG_1 },
 216         { PCI_VDEVICE(REALTEK,  0x8169), RTL_CFG_0 },
 217         { PCI_VENDOR_ID_DLINK,  0x4300,
 218                 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 },
 219         { PCI_VDEVICE(DLINK,    0x4300), RTL_CFG_0 },
 220         { PCI_VDEVICE(DLINK,    0x4302), RTL_CFG_0 },
 221         { PCI_VDEVICE(AT,       0xc107), RTL_CFG_0 },
 222         { PCI_VDEVICE(USR,      0x0116), RTL_CFG_0 },
 223         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 224                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 225         { 0x0001,                               0x8168,
 226                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 227         {}
 228 };
 229
 230 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 231
 232 static struct {
 233         u32 msg_enable;
 234 } debug = { -1 };
 235
 236 enum rtl_registers {
 237         MAC0            = 0,    /* Ethernet hardware address. */
 238         MAC4            = 4,
 239         MAR0            = 8,    /* Multicast filter. */
 240         CounterAddrLow          = 0x10,
 241         CounterAddrHigh         = 0x14,
 242         TxDescStartAddrLow      = 0x20,
 243         TxDescStartAddrHigh     = 0x24,
 244         TxHDescStartAddrLow     = 0x28,
 245         TxHDescStartAddrHigh    = 0x2c,
 246         FLASH           = 0x30,
 247         ERSR            = 0x36,
 248         ChipCmd         = 0x37,
 249         TxPoll          = 0x38,
 250         IntrMask        = 0x3c,
 251         IntrStatus      = 0x3e,
 252
 253         TxConfig        = 0x40,
 254 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 255 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 256
 257         RxConfig        = 0x44,
 258 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 259 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 260 #define RXCFG_FIFO_SHIFT                13
 261                                         /* No threshold before first PCI xfer */
 262 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 263 #define RX_EARLY_OFF                    (1 << 11)
 264 #define RXCFG_DMA_SHIFT                 8
 265                                         /* Unlimited maximum PCI burst. */
 266 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 267
 268         RxMissed        = 0x4c,
 269         Cfg9346         = 0x50,
 270         Config0         = 0x51,
 271         Config1         = 0x52,
 272         Config2         = 0x53,
 273 #define PME_SIGNAL                      (1 << 5)        /* 8168c and later */
 274
 275         Config3         = 0x54,
 276         Config4         = 0x55,
 277         Config5         = 0x56,
 278         MultiIntr       = 0x5c,
 279         PHYAR           = 0x60,
 280         PHYstatus       = 0x6c,
 281         RxMaxSize       = 0xda,
 282         CPlusCmd        = 0xe0,
 283         IntrMitigate    = 0xe2,
 284
 285 #define RTL_COALESCE_MASK       0x0f
 286 #define RTL_COALESCE_SHIFT      4
 287 #define RTL_COALESCE_T_MAX      (RTL_COALESCE_MASK)
 288 #define RTL_COALESCE_FRAME_MAX  (RTL_COALESCE_MASK << 2)
 289
 290         RxDescAddrLow   = 0xe4,
 291         RxDescAddrHigh  = 0xe8,
 292         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 293
 294 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 295
 296         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 297
 298 #define TxPacketMax     (8064 >> 7)
 299 #define EarlySize       0x27
 300
 301         FuncEvent       = 0xf0,
 302         FuncEventMask   = 0xf4,
 303         FuncPresetState = 0xf8,
 304         IBCR0           = 0xf8,
 305         IBCR2           = 0xf9,
 306         IBIMR0          = 0xfa,
 307         IBISR0          = 0xfb,
 308         FuncForceEvent  = 0xfc,
 309 };
 310
 311 enum rtl8168_8101_registers {
 312         CSIDR                   = 0x64,
 313         CSIAR                   = 0x68,
 314 #define CSIAR_FLAG                      0x80000000
 315 #define CSIAR_WRITE_CMD                 0x80000000
 316 #define CSIAR_BYTE_ENABLE               0x0000f000
 317 #define CSIAR_ADDR_MASK                 0x00000fff
 318         PMCH                    = 0x6f,
 319         EPHYAR                  = 0x80,
 320 #define EPHYAR_FLAG                     0x80000000
 321 #define EPHYAR_WRITE_CMD                0x80000000
 322 #define EPHYAR_REG_MASK                 0x1f
 323 #define EPHYAR_REG_SHIFT                16
 324 #define EPHYAR_DATA_MASK                0xffff
 325         DLLPR                   = 0xd0,
 326 #define PFM_EN                          (1 << 6)
 327 #define TX_10M_PS_EN                    (1 << 7)
 328         DBG_REG                 = 0xd1,
 329 #define FIX_NAK_1                       (1 << 4)
 330 #define FIX_NAK_2                       (1 << 3)
 331         TWSI                    = 0xd2,
 332         MCU                     = 0xd3,
 333 #define NOW_IS_OOB                      (1 << 7)
 334 #define TX_EMPTY                        (1 << 5)
 335 #define RX_EMPTY                        (1 << 4)
 336 #define RXTX_EMPTY                      (TX_EMPTY | RX_EMPTY)
 337 #define EN_NDP                          (1 << 3)
 338 #define EN_OOB_RESET                    (1 << 2)
 339 #define LINK_LIST_RDY                   (1 << 1)
 340         EFUSEAR                 = 0xdc,
 341 #define EFUSEAR_FLAG                    0x80000000
 342 #define EFUSEAR_WRITE_CMD               0x80000000
 343 #define EFUSEAR_READ_CMD                0x00000000
 344 #define EFUSEAR_REG_MASK                0x03ff
 345 #define EFUSEAR_REG_SHIFT               8
 346 #define EFUSEAR_DATA_MASK               0xff
 347         MISC_1                  = 0xf2,
 348 #define PFM_D3COLD_EN                   (1 << 6)
 349 };
 350
 351 enum rtl8168_registers {
 352         LED_FREQ                = 0x1a,
 353         EEE_LED                 = 0x1b,
 354         ERIDR                   = 0x70,
 355         ERIAR                   = 0x74,
 356 #define ERIAR_FLAG                      0x80000000
 357 #define ERIAR_WRITE_CMD                 0x80000000
 358 #define ERIAR_READ_CMD                  0x00000000
 359 #define ERIAR_ADDR_BYTE_ALIGN           4
 360 #define ERIAR_TYPE_SHIFT                16
 361 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 362 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 363 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 364 #define ERIAR_OOB                       (0x02 << ERIAR_TYPE_SHIFT)
 365 #define ERIAR_MASK_SHIFT                12
 366 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 367 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 368 #define ERIAR_MASK_0100                 (0x4 << ERIAR_MASK_SHIFT)
 369 #define ERIAR_MASK_0101                 (0x5 << ERIAR_MASK_SHIFT)
 370 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 371         EPHY_RXER_NUM           = 0x7c,
 372         OCPDR                   = 0xb0, /* OCP GPHY access */
 373 #define OCPDR_WRITE_CMD                 0x80000000
 374 #define OCPDR_READ_CMD                  0x00000000
 375 #define OCPDR_REG_MASK                  0x7f
 376 #define OCPDR_GPHY_REG_SHIFT            16
 377 #define OCPDR_DATA_MASK                 0xffff
 378         OCPAR                   = 0xb4,
 379 #define OCPAR_FLAG                      0x80000000
 380 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 381 #define OCPAR_GPHY_READ_CMD             0x0000f060
 382         GPHY_OCP                = 0xb8,
 383         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 384         MISC                    = 0xf0, /* 8168e only. */
 385 #define TXPLA_RST                       (1 << 29)
 386 #define DISABLE_LAN_EN                  (1 << 23) /* Enable GPIO pin */
 387 #define PWM_EN                          (1 << 22)
 388 #define RXDV_GATED_EN                   (1 << 19)
 389 #define EARLY_TALLY_EN                  (1 << 16)
 390 };
 391
 392 enum rtl_register_content {
 393         /* InterruptStatusBits */
 394         SYSErr          = 0x8000,
 395         PCSTimeout      = 0x4000,
 396         SWInt           = 0x0100,
 397         TxDescUnavail   = 0x0080,
 398         RxFIFOOver      = 0x0040,
 399         LinkChg         = 0x0020,
 400         RxOverflow      = 0x0010,
 401         TxErr           = 0x0008,
 402         TxOK            = 0x0004,
 403         RxErr           = 0x0002,
 404         RxOK            = 0x0001,
 405
 406         /* RxStatusDesc */
 407         RxBOVF  = (1 << 24),
 408         RxFOVF  = (1 << 23),
 409         RxRWT   = (1 << 22),
 410         RxRES   = (1 << 21),
 411         RxRUNT  = (1 << 20),
 412         RxCRC   = (1 << 19),
 413
 414         /* ChipCmdBits */
 415         StopReq         = 0x80,
 416         CmdReset        = 0x10,
 417         CmdRxEnb        = 0x08,
 418         CmdTxEnb        = 0x04,
 419         RxBufEmpty      = 0x01,
 420
 421         /* TXPoll register p.5 */
 422         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 423         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 424         FSWInt          = 0x01,         /* Forced software interrupt */
 425
 426         /* Cfg9346Bits */
 427         Cfg9346_Lock    = 0x00,
 428         Cfg9346_Unlock  = 0xc0,
 429
 430         /* rx_mode_bits */
 431         AcceptErr       = 0x20,
 432         AcceptRunt      = 0x10,
 433         AcceptBroadcast = 0x08,
 434         AcceptMulticast = 0x04,
 435         AcceptMyPhys    = 0x02,
 436         AcceptAllPhys   = 0x01,
 437 #define RX_CONFIG_ACCEPT_MASK           0x3f
 438
 439         /* TxConfigBits */
 440         TxInterFrameGapShift = 24,
 441         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 442
 443         /* Config1 register p.24 */
 444         LEDS1           = (1 << 7),
 445         LEDS0           = (1 << 6),
 446         Speed_down      = (1 << 4),
 447         MEMMAP          = (1 << 3),
 448         IOMAP           = (1 << 2),
 449         VPD             = (1 << 1),
 450         PMEnable        = (1 << 0),     /* Power Management Enable */
 451
 452         /* Config2 register p. 25 */
 453         ClkReqEn        = (1 << 7),     /* Clock Request Enable */
 454         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
 455         PCI_Clock_66MHz = 0x01,
 456         PCI_Clock_33MHz = 0x00,
 457
 458         /* Config3 register p.25 */
 459         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 460         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 461         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
 462         Rdy_to_L23      = (1 << 1),     /* L23 Enable */
 463         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 464
 465         /* Config4 register */
 466         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
 467
 468         /* Config5 register p.27 */
 469         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 470         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 471         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 472         Spi_en          = (1 << 3),
 473         LanWake         = (1 << 1),     /* LanWake enable/disable */
 474         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 475         ASPM_en         = (1 << 0),     /* ASPM enable */
 476
 477         /* CPlusCmd p.31 */
 478         EnableBist      = (1 << 15),    // 8168 8101
 479         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 480         Normal_mode     = (1 << 13),    // unused
 481         Force_half_dup  = (1 << 12),    // 8168 8101
 482         Force_rxflow_en = (1 << 11),    // 8168 8101
 483         Force_txflow_en = (1 << 10),    // 8168 8101
 484         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 485         ASF             = (1 << 8),     // 8168 8101
 486         PktCntrDisable  = (1 << 7),     // 8168 8101
 487         Mac_dbgo_sel    = 0x001c,       // 8168
 488         RxVlan          = (1 << 6),
 489         RxChkSum        = (1 << 5),
 490         PCIDAC          = (1 << 4),
 491         PCIMulRW        = (1 << 3),
 492 #define INTT_MASK       GENMASK(1, 0)
 493         INTT_0          = 0x0000,       // 8168
 494         INTT_1          = 0x0001,       // 8168
 495         INTT_2          = 0x0002,       // 8168
 496         INTT_3          = 0x0003,       // 8168
 497
 498         /* rtl8169_PHYstatus */
 499         TBI_Enable      = 0x80,
 500         TxFlowCtrl      = 0x40,
 501         RxFlowCtrl      = 0x20,
 502         _1000bpsF       = 0x10,
 503         _100bps         = 0x08,
 504         _10bps          = 0x04,
 505         LinkStatus      = 0x02,
 506         FullDup         = 0x01,
 507
 508         /* _TBICSRBit */
 509         TBILinkOK       = 0x02000000,
 510
 511         /* ResetCounterCommand */
 512         CounterReset    = 0x1,
 513
 514         /* DumpCounterCommand */
 515         CounterDump     = 0x8,
 516
 517         /* magic enable v2 */
 518         MagicPacket_v2  = (1 << 16),    /* Wake up when receives a Magic Packet */
 519 };
 520
 521 enum rtl_desc_bit {
 522         /* First doubleword. */
 523         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 524         RingEnd         = (1 << 30), /* End of descriptor ring */
 525         FirstFrag       = (1 << 29), /* First segment of a packet */
 526         LastFrag        = (1 << 28), /* Final segment of a packet */
 527 };
 528
 529 /* Generic case. */
 530 enum rtl_tx_desc_bit {
 531         /* First doubleword. */
 532         TD_LSO          = (1 << 27),            /* Large Send Offload */
 533 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 534
 535         /* Second doubleword. */
 536         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 537 };
 538
 539 /* 8169, 8168b and 810x except 8102e. */
 540 enum rtl_tx_desc_bit_0 {
 541         /* First doubleword. */
 542 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 543         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 544         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 545         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 546 };
 547
 548 /* 8102e, 8168c and beyond. */
 549 enum rtl_tx_desc_bit_1 {
 550         /* First doubleword. */
 551         TD1_GTSENV4     = (1 << 26),            /* Giant Send for IPv4 */
 552         TD1_GTSENV6     = (1 << 25),            /* Giant Send for IPv6 */
 553 #define GTTCPHO_SHIFT                   18
 554 #define GTTCPHO_MAX                     0x7fU
 555
 556         /* Second doubleword. */
 557 #define TCPHO_SHIFT                     18
 558 #define TCPHO_MAX                       0x3ffU
 559 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 560         TD1_IPv6_CS     = (1 << 28),            /* Calculate IPv6 checksum */
 561         TD1_IPv4_CS     = (1 << 29),            /* Calculate IPv4 checksum */
 562         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 563         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 564 };
 565
 566 enum rtl_rx_desc_bit {
 567         /* Rx private */
 568         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 569         PID0            = (1 << 17), /* Protocol ID bit 0/2 */
 570
 571 #define RxProtoUDP      (PID1)
 572 #define RxProtoTCP      (PID0)
 573 #define RxProtoIP       (PID1 | PID0)
 574 #define RxProtoMask     RxProtoIP
 575
 576         IPFail          = (1 << 16), /* IP checksum failed */
 577         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 578         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 579         RxVlanTag       = (1 << 16), /* VLAN tag available */
 580 };
 581
 582 #define RsvdMask        0x3fffc000
 583 #define CPCMD_QUIRK_MASK        (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
 584
 585 struct TxDesc {
 586         __le32 opts1;
 587         __le32 opts2;
 588         __le64 addr;
 589 };
 590
 591 struct RxDesc {
 592         __le32 opts1;
 593         __le32 opts2;
 594         __le64 addr;
 595 };
 596
 597 struct ring_info {
 598         struct sk_buff  *skb;
 599         u32             len;
 600 };
 601
 602 struct rtl8169_counters {
 603         __le64  tx_packets;
 604         __le64  rx_packets;
 605         __le64  tx_errors;
 606         __le32  rx_errors;
 607         __le16  rx_missed;
 608         __le16  align_errors;
 609         __le32  tx_one_collision;
 610         __le32  tx_multi_collision;
 611         __le64  rx_unicast;
 612         __le64  rx_broadcast;
 613         __le32  rx_multicast;
 614         __le16  tx_aborted;
 615         __le16  tx_underun;
 616 };
 617
 618 struct rtl8169_tc_offsets {
 619         bool    inited;
 620         __le64  tx_errors;
 621         __le32  tx_multi_collision;
 622         __le16  tx_aborted;
 623 };
 624
 625 enum rtl_flag {
 626         RTL_FLAG_TASK_ENABLED = 0,
 627         RTL_FLAG_TASK_RESET_PENDING,
 628         RTL_FLAG_MAX
 629 };
 630
 631 struct rtl8169_stats {
 632         u64                     packets;
 633         u64                     bytes;
 634         struct u64_stats_sync   syncp;
 635 };
 636
 637 struct rtl8169_private {
 638         void __iomem *mmio_addr;        /* memory map physical address */
 639         struct pci_dev *pci_dev;
 640         struct net_device *dev;
 641         struct phy_device *phydev;
 642         struct napi_struct napi;
 643         u32 msg_enable;
 644         u16 mac_version;
 645         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 646         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 647         u32 dirty_tx;
 648         struct rtl8169_stats rx_stats;
 649         struct rtl8169_stats tx_stats;
 650         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 651         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 652         dma_addr_t TxPhyAddr;
 653         dma_addr_t RxPhyAddr;
 654         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
 655         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 656         u16 cp_cmd;
 657
 658         u16 irq_mask;
 659         const struct rtl_coalesce_info *coalesce_info;
 660         struct clk *clk;
 661
 662         struct mdio_ops {
 663                 void (*write)(struct rtl8169_private *, int, int);
 664                 int (*read)(struct rtl8169_private *, int);
 665         } mdio_ops;
 666
 667         struct jumbo_ops {
 668                 void (*enable)(struct rtl8169_private *);
 669                 void (*disable)(struct rtl8169_private *);
 670         } jumbo_ops;
 671
 672         void (*hw_start)(struct rtl8169_private *tp);
 673         bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
 674
 675         struct {
 676                 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
 677                 struct mutex mutex;
 678                 struct work_struct work;
 679         } wk;
 680
 681         unsigned irq_enabled:1;
 682         unsigned supports_gmii:1;
 683         dma_addr_t counters_phys_addr;
 684         struct rtl8169_counters *counters;
 685         struct rtl8169_tc_offsets tc_offset;
 686         u32 saved_wolopts;
 687
 688         const char *fw_name;
 689         struct rtl_fw {
 690                 const struct firmware *fw;
 691
 692 #define RTL_VER_SIZE            32
 693
 694                 char version[RTL_VER_SIZE];
 695
 696                 struct rtl_fw_phy_action {
 697                         __le32 *code;
 698                         size_t size;
 699                 } phy_action;
 700         } *rtl_fw;
 701
 702         u32 ocp_base;
 703 };
 704
 705 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 706 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 707 module_param_named(debug, debug.msg_enable, int, 0);
 708 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 709 MODULE_SOFTDEP("pre: realtek");
 710 MODULE_LICENSE("GPL");
 711 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 712 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 713 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 714 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 715 MODULE_FIRMWARE(FIRMWARE_8168E_3);
 716 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 717 MODULE_FIRMWARE(FIRMWARE_8168F_1);
 718 MODULE_FIRMWARE(FIRMWARE_8168F_2);
 719 MODULE_FIRMWARE(FIRMWARE_8402_1);
 720 MODULE_FIRMWARE(FIRMWARE_8411_1);
 721 MODULE_FIRMWARE(FIRMWARE_8411_2);
 722 MODULE_FIRMWARE(FIRMWARE_8106E_1);
 723 MODULE_FIRMWARE(FIRMWARE_8106E_2);
 724 MODULE_FIRMWARE(FIRMWARE_8168G_2);
 725 MODULE_FIRMWARE(FIRMWARE_8168G_3);
 726 MODULE_FIRMWARE(FIRMWARE_8168H_1);
 727 MODULE_FIRMWARE(FIRMWARE_8168H_2);
 728 MODULE_FIRMWARE(FIRMWARE_8107E_1);
 729 MODULE_FIRMWARE(FIRMWARE_8107E_2);
 730
 731 static inline struct device *tp_to_dev(struct rtl8169_private *tp)
 732 {
 733         return &tp->pci_dev->dev;
 734 }
 735
 736 static void rtl_lock_work(struct rtl8169_private *tp)
 737 {
 738         mutex_lock(&tp->wk.mutex);
 739 }
 740
 741 static void rtl_unlock_work(struct rtl8169_private *tp)
 742 {
 743         mutex_unlock(&tp->wk.mutex);
 744 }
 745
 746 static void rtl_lock_config_regs(struct rtl8169_private *tp)
 747 {
 748         RTL_W8(tp, Cfg9346, Cfg9346_Lock);
 749 }
 750
 751 static void rtl_unlock_config_regs(struct rtl8169_private *tp)
 752 {
 753         RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
 754 }
 755
 756 static void rtl_tx_performance_tweak(struct rtl8169_private *tp, u16 force)
 757 {
 758         pcie_capability_clear_and_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
 759                                            PCI_EXP_DEVCTL_READRQ, force);
 760 }
 761
 762 struct rtl_cond {
 763         bool (*check)(struct rtl8169_private *);
 764         const char *msg;
 765 };
 766
 767 static void rtl_udelay(unsigned int d)
 768 {
 769         udelay(d);
 770 }
 771
 772 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
 773                           void (*delay)(unsigned int), unsigned int d, int n,
 774                           bool high)
 775 {
 776         int i;
 777
 778         for (i = 0; i < n; i++) {
 779                 delay(d);
 780                 if (c->check(tp) == high)
 781                         return true;
 782         }
 783         netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
 784                   c->msg, !high, n, d);
 785         return false;
 786 }
 787
 788 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
 789                                       const struct rtl_cond *c,
 790                                       unsigned int d, int n)
 791 {
 792         return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
 793 }
 794
 795 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
 796                                      const struct rtl_cond *c,
 797                                      unsigned int d, int n)
 798 {
 799         return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
 800 }
 801
 802 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
 803                                       const struct rtl_cond *c,
 804                                       unsigned int d, int n)
 805 {
 806         return rtl_loop_wait(tp, c, msleep, d, n, true);
 807 }
 808
 809 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
 810                                      const struct rtl_cond *c,
 811                                      unsigned int d, int n)
 812 {
 813         return rtl_loop_wait(tp, c, msleep, d, n, false);
 814 }
 815
 816 #define DECLARE_RTL_COND(name)                          \
 817 static bool name ## _check(struct rtl8169_private *);   \
 818                                                         \
 819 static const struct rtl_cond name = {                   \
 820         .check  = name ## _check,                       \
 821         .msg    = #name                                 \
 822 };                                                      \
 823                                                         \
 824 static bool name ## _check(struct rtl8169_private *tp)
 825
 826 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
 827 {
 828         if (reg & 0xffff0001) {
 829                 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
 830                 return true;
 831         }
 832         return false;
 833 }
 834
 835 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
 836 {
 837         return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
 838 }
 839
 840 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 841 {
 842         if (rtl_ocp_reg_failure(tp, reg))
 843                 return;
 844
 845         RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
 846
 847         rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
 848 }
 849
 850 static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
 851 {
 852         if (rtl_ocp_reg_failure(tp, reg))
 853                 return 0;
 854
 855         RTL_W32(tp, GPHY_OCP, reg << 15);
 856
 857         return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
 858                 (RTL_R32(tp, GPHY_OCP) & 0xffff) : ~0;
 859 }
 860
 861 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 862 {
 863         if (rtl_ocp_reg_failure(tp, reg))
 864                 return;
 865
 866         RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
 867 }
 868
 869 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
 870 {
 871         if (rtl_ocp_reg_failure(tp, reg))
 872                 return 0;
 873
 874         RTL_W32(tp, OCPDR, reg << 15);
 875
 876         return RTL_R32(tp, OCPDR);
 877 }
 878
 879 #define OCP_STD_PHY_BASE        0xa400
 880
 881 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
 882 {
 883         if (reg == 0x1f) {
 884                 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
 885                 return;
 886         }
 887
 888         if (tp->ocp_base != OCP_STD_PHY_BASE)
 889                 reg -= 0x10;
 890
 891         r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
 892 }
 893
 894 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
 895 {
 896         if (tp->ocp_base != OCP_STD_PHY_BASE)
 897                 reg -= 0x10;
 898
 899         return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
 900 }
 901
 902 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
 903 {
 904         if (reg == 0x1f) {
 905                 tp->ocp_base = value << 4;
 906                 return;
 907         }
 908
 909         r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
 910 }
 911
 912 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
 913 {
 914         return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
 915 }
 916
 917 DECLARE_RTL_COND(rtl_phyar_cond)
 918 {
 919         return RTL_R32(tp, PHYAR) & 0x80000000;
 920 }
 921
 922 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
 923 {
 924         RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
 925
 926         rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
 927         /*
 928          * According to hardware specs a 20us delay is required after write
 929          * complete indication, but before sending next command.
 930          */
 931         udelay(20);
 932 }
 933
 934 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
 935 {
 936         int value;
 937
 938         RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
 939
 940         value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
 941                 RTL_R32(tp, PHYAR) & 0xffff : ~0;
 942
 943         /*
 944          * According to hardware specs a 20us delay is required after read
 945          * complete indication, but before sending next command.
 946          */
 947         udelay(20);
 948
 949         return value;
 950 }
 951
 952 DECLARE_RTL_COND(rtl_ocpar_cond)
 953 {
 954         return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
 955 }
 956
 957 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
 958 {
 959         RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
 960         RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
 961         RTL_W32(tp, EPHY_RXER_NUM, 0);
 962
 963         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
 964 }
 965
 966 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
 967 {
 968         r8168dp_1_mdio_access(tp, reg,
 969                               OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
 970 }
 971
 972 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
 973 {
 974         r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
 975
 976         mdelay(1);
 977         RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
 978         RTL_W32(tp, EPHY_RXER_NUM, 0);
 979
 980         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
 981                 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : ~0;
 982 }
 983
 984 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
 985
 986 static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
 987 {
 988         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
 989 }
 990
 991 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
 992 {
 993         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
 994 }
 995
 996 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
 997 {
 998         r8168dp_2_mdio_start(tp);
 999
1000         r8169_mdio_write(tp, reg, value);
1001
1002         r8168dp_2_mdio_stop(tp);
1003 }
1004
1005 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1006 {
1007         int value;
1008
1009         r8168dp_2_mdio_start(tp);
1010
1011         value = r8169_mdio_read(tp, reg);
1012
1013         r8168dp_2_mdio_stop(tp);
1014
1015         return value;
1016 }
1017
1018 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1019 {
1020         tp->mdio_ops.write(tp, location, val);
1021 }
1022
1023 static int rtl_readphy(struct rtl8169_private *tp, int location)
1024 {
1025         return tp->mdio_ops.read(tp, location);
1026 }
1027
1028 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1029 {
1030         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1031 }
1032
1033 static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1034 {
1035         int val;
1036
1037         val = rtl_readphy(tp, reg_addr);
1038         rtl_writephy(tp, reg_addr, (val & ~m) | p);
1039 }
1040
1041 DECLARE_RTL_COND(rtl_ephyar_cond)
1042 {
1043         return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1044 }
1045
1046 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1047 {
1048         RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1049                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1050
1051         rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1052
1053         udelay(10);
1054 }
1055
1056 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1057 {
1058         RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1059
1060         return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1061                 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1062 }
1063
1064 DECLARE_RTL_COND(rtl_eriar_cond)
1065 {
1066         return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
1067 }
1068
1069 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1070                           u32 val, int type)
1071 {
1072         BUG_ON((addr & 3) || (mask == 0));
1073         RTL_W32(tp, ERIDR, val);
1074         RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1075
1076         rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1077 }
1078
1079 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1080 {
1081         RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1082
1083         return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1084                 RTL_R32(tp, ERIDR) : ~0;
1085 }
1086
1087 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1088                          u32 m, int type)
1089 {
1090         u32 val;
1091
1092         val = rtl_eri_read(tp, addr, type);
1093         rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
1094 }
1095
1096 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1097 {
1098         RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1099         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1100                 RTL_R32(tp, OCPDR) : ~0;
1101 }
1102
1103 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1104 {
1105         return rtl_eri_read(tp, reg, ERIAR_OOB);
1106 }
1107
1108 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1109                               u32 data)
1110 {
1111         RTL_W32(tp, OCPDR, data);
1112         RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1113         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1114 }
1115
1116 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1117                               u32 data)
1118 {
1119         rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1120                       data, ERIAR_OOB);
1121 }
1122
1123 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd)
1124 {
1125         rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd, ERIAR_EXGMAC);
1126
1127         r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001);
1128 }
1129
1130 #define OOB_CMD_RESET           0x00
1131 #define OOB_CMD_DRIVER_START    0x05
1132 #define OOB_CMD_DRIVER_STOP     0x06
1133
1134 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1135 {
1136         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1137 }
1138
1139 DECLARE_RTL_COND(rtl_dp_ocp_read_cond)
1140 {
1141         u16 reg;
1142
1143         reg = rtl8168_get_ocp_reg(tp);
1144
1145         return r8168dp_ocp_read(tp, 0x0f, reg) & 0x00000800;
1146 }
1147
1148 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1149 {
1150         return r8168ep_ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1151 }
1152
1153 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1154 {
1155         return RTL_R8(tp, IBISR0) & 0x20;
1156 }
1157
1158 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1159 {
1160         RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1161         rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000);
1162         RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1163         RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1164 }
1165
1166 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1167 {
1168         r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START);
1169         rtl_msleep_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10, 10);
1170 }
1171
1172 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1173 {
1174         r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1175         r8168ep_ocp_write(tp, 0x01, 0x30,
1176                           r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
1177         rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1178 }
1179
1180 static void rtl8168_driver_start(struct rtl8169_private *tp)
1181 {
1182         switch (tp->mac_version) {
1183         case RTL_GIGA_MAC_VER_27:
1184         case RTL_GIGA_MAC_VER_28:
1185         case RTL_GIGA_MAC_VER_31:
1186                 rtl8168dp_driver_start(tp);
1187                 break;
1188         case RTL_GIGA_MAC_VER_49:
1189         case RTL_GIGA_MAC_VER_50:
1190         case RTL_GIGA_MAC_VER_51:
1191                 rtl8168ep_driver_start(tp);
1192                 break;
1193         default:
1194                 BUG();
1195                 break;
1196         }
1197 }
1198
1199 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1200 {
1201         r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1202         rtl_msleep_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10, 10);
1203 }
1204
1205 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1206 {
1207         rtl8168ep_stop_cmac(tp);
1208         r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1209         r8168ep_ocp_write(tp, 0x01, 0x30,
1210                           r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
1211         rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1212 }
1213
1214 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1215 {
1216         switch (tp->mac_version) {
1217         case RTL_GIGA_MAC_VER_27:
1218         case RTL_GIGA_MAC_VER_28:
1219         case RTL_GIGA_MAC_VER_31:
1220                 rtl8168dp_driver_stop(tp);
1221                 break;
1222         case RTL_GIGA_MAC_VER_49:
1223         case RTL_GIGA_MAC_VER_50:
1224         case RTL_GIGA_MAC_VER_51:
1225                 rtl8168ep_driver_stop(tp);
1226                 break;
1227         default:
1228                 BUG();
1229                 break;
1230         }
1231 }
1232
1233 static bool r8168dp_check_dash(struct rtl8169_private *tp)
1234 {
1235         u16 reg = rtl8168_get_ocp_reg(tp);
1236
1237         return !!(r8168dp_ocp_read(tp, 0x0f, reg) & 0x00008000);
1238 }
1239
1240 static bool r8168ep_check_dash(struct rtl8169_private *tp)
1241 {
1242         return !!(r8168ep_ocp_read(tp, 0x0f, 0x128) & 0x00000001);
1243 }
1244
1245 static bool r8168_check_dash(struct rtl8169_private *tp)
1246 {
1247         switch (tp->mac_version) {
1248         case RTL_GIGA_MAC_VER_27:
1249         case RTL_GIGA_MAC_VER_28:
1250         case RTL_GIGA_MAC_VER_31:
1251                 return r8168dp_check_dash(tp);
1252         case RTL_GIGA_MAC_VER_49:
1253         case RTL_GIGA_MAC_VER_50:
1254         case RTL_GIGA_MAC_VER_51:
1255                 return r8168ep_check_dash(tp);
1256         default:
1257                 return false;
1258         }
1259 }
1260
1261 struct exgmac_reg {
1262         u16 addr;
1263         u16 mask;
1264         u32 val;
1265 };
1266
1267 static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
1268                                    const struct exgmac_reg *r, int len)
1269 {
1270         while (len-- > 0) {
1271                 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1272                 r++;
1273         }
1274 }
1275
1276 DECLARE_RTL_COND(rtl_efusear_cond)
1277 {
1278         return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1279 }
1280
1281 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1282 {
1283         RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1284
1285         return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1286                 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1287 }
1288
1289 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1290 {
1291         RTL_W16(tp, IntrStatus, bits);
1292 }
1293
1294 static void rtl_irq_disable(struct rtl8169_private *tp)
1295 {
1296         RTL_W16(tp, IntrMask, 0);
1297         tp->irq_enabled = 0;
1298 }
1299
1300 #define RTL_EVENT_NAPI_RX       (RxOK | RxErr)
1301 #define RTL_EVENT_NAPI_TX       (TxOK | TxErr)
1302 #define RTL_EVENT_NAPI          (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1303
1304 static void rtl_irq_enable(struct rtl8169_private *tp)
1305 {
1306         tp->irq_enabled = 1;
1307         RTL_W16(tp, IntrMask, tp->irq_mask);
1308 }
1309
1310 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1311 {
1312         rtl_irq_disable(tp);
1313         rtl_ack_events(tp, 0xffff);
1314         /* PCI commit */
1315         RTL_R8(tp, ChipCmd);
1316 }
1317
1318 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1319 {
1320         struct net_device *dev = tp->dev;
1321         struct phy_device *phydev = tp->phydev;
1322
1323         if (!netif_running(dev))
1324                 return;
1325
1326         if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1327             tp->mac_version == RTL_GIGA_MAC_VER_38) {
1328                 if (phydev->speed == SPEED_1000) {
1329                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1330                                       ERIAR_EXGMAC);
1331                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1332                                       ERIAR_EXGMAC);
1333                 } else if (phydev->speed == SPEED_100) {
1334                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1335                                       ERIAR_EXGMAC);
1336                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1337                                       ERIAR_EXGMAC);
1338                 } else {
1339                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1340                                       ERIAR_EXGMAC);
1341                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1342                                       ERIAR_EXGMAC);
1343                 }
1344                 /* Reset packet filter */
1345                 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1346                              ERIAR_EXGMAC);
1347                 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1348                              ERIAR_EXGMAC);
1349         } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1350                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
1351                 if (phydev->speed == SPEED_1000) {
1352                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1353                                       ERIAR_EXGMAC);
1354                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1355                                       ERIAR_EXGMAC);
1356                 } else {
1357                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1358                                       ERIAR_EXGMAC);
1359                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1360                                       ERIAR_EXGMAC);
1361                 }
1362         } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1363                 if (phydev->speed == SPEED_10) {
1364                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1365                                       ERIAR_EXGMAC);
1366                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1367                                       ERIAR_EXGMAC);
1368                 } else {
1369                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1370                                       ERIAR_EXGMAC);
1371                 }
1372         }
1373 }
1374
1375 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1376
1377 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1378 {
1379         struct rtl8169_private *tp = netdev_priv(dev);
1380
1381         rtl_lock_work(tp);
1382         wol->supported = WAKE_ANY;
1383         wol->wolopts = tp->saved_wolopts;
1384         rtl_unlock_work(tp);
1385 }
1386
1387 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1388 {
1389         unsigned int i, tmp;
1390         static const struct {
1391                 u32 opt;
1392                 u16 reg;
1393                 u8  mask;
1394         } cfg[] = {
1395                 { WAKE_PHY,   Config3, LinkUp },
1396                 { WAKE_UCAST, Config5, UWF },
1397                 { WAKE_BCAST, Config5, BWF },
1398                 { WAKE_MCAST, Config5, MWF },
1399                 { WAKE_ANY,   Config5, LanWake },
1400                 { WAKE_MAGIC, Config3, MagicPacket }
1401         };
1402         u8 options;
1403
1404         rtl_unlock_config_regs(tp);
1405
1406         switch (tp->mac_version) {
1407         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
1408         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1409                 tmp = ARRAY_SIZE(cfg) - 1;
1410                 if (wolopts & WAKE_MAGIC)
1411                         rtl_w0w1_eri(tp,
1412                                      0x0dc,
1413                                      ERIAR_MASK_0100,
1414                                      MagicPacket_v2,
1415                                      0x0000,
1416                                      ERIAR_EXGMAC);
1417                 else
1418                         rtl_w0w1_eri(tp,
1419                                      0x0dc,
1420                                      ERIAR_MASK_0100,
1421                                      0x0000,
1422                                      MagicPacket_v2,
1423                                      ERIAR_EXGMAC);
1424                 break;
1425         default:
1426                 tmp = ARRAY_SIZE(cfg);
1427                 break;
1428         }
1429
1430         for (i = 0; i < tmp; i++) {
1431                 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
1432                 if (wolopts & cfg[i].opt)
1433                         options |= cfg[i].mask;
1434                 RTL_W8(tp, cfg[i].reg, options);
1435         }
1436
1437         switch (tp->mac_version) {
1438         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1439                 options = RTL_R8(tp, Config1) & ~PMEnable;
1440                 if (wolopts)
1441                         options |= PMEnable;
1442                 RTL_W8(tp, Config1, options);
1443                 break;
1444         default:
1445                 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
1446                 if (wolopts)
1447                         options |= PME_SIGNAL;
1448                 RTL_W8(tp, Config2, options);
1449                 break;
1450         }
1451
1452         rtl_lock_config_regs(tp);
1453
1454         device_set_wakeup_enable(tp_to_dev(tp), wolopts);
1455 }
1456
1457 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1458 {
1459         struct rtl8169_private *tp = netdev_priv(dev);
1460         struct device *d = tp_to_dev(tp);
1461
1462         if (wol->wolopts & ~WAKE_ANY)
1463                 return -EINVAL;
1464
1465         pm_runtime_get_noresume(d);
1466
1467         rtl_lock_work(tp);
1468
1469         tp->saved_wolopts = wol->wolopts;
1470
1471         if (pm_runtime_active(d))
1472                 __rtl8169_set_wol(tp, tp->saved_wolopts);
1473
1474         rtl_unlock_work(tp);
1475
1476         pm_runtime_put_noidle(d);
1477
1478         return 0;
1479 }
1480
1481 static void rtl8169_get_drvinfo(struct net_device *dev,
1482                                 struct ethtool_drvinfo *info)
1483 {
1484         struct rtl8169_private *tp = netdev_priv(dev);
1485         struct rtl_fw *rtl_fw = tp->rtl_fw;
1486
1487         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1488         strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1489         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1490         if (rtl_fw)
1491                 strlcpy(info->fw_version, rtl_fw->version,
1492                         sizeof(info->fw_version));
1493 }
1494
1495 static int rtl8169_get_regs_len(struct net_device *dev)
1496 {
1497         return R8169_REGS_SIZE;
1498 }
1499
1500 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1501         netdev_features_t features)
1502 {
1503         struct rtl8169_private *tp = netdev_priv(dev);
1504
1505         if (dev->mtu > TD_MSS_MAX)
1506                 features &= ~NETIF_F_ALL_TSO;
1507
1508         if (dev->mtu > JUMBO_1K &&
1509             tp->mac_version > RTL_GIGA_MAC_VER_06)
1510                 features &= ~NETIF_F_IP_CSUM;
1511
1512         return features;
1513 }
1514
1515 static int rtl8169_set_features(struct net_device *dev,
1516                                 netdev_features_t features)
1517 {
1518         struct rtl8169_private *tp = netdev_priv(dev);
1519         u32 rx_config;
1520
1521         rtl_lock_work(tp);
1522
1523         rx_config = RTL_R32(tp, RxConfig);
1524         if (features & NETIF_F_RXALL)
1525                 rx_config |= (AcceptErr | AcceptRunt);
1526         else
1527                 rx_config &= ~(AcceptErr | AcceptRunt);
1528
1529         RTL_W32(tp, RxConfig, rx_config);
1530
1531         if (features & NETIF_F_RXCSUM)
1532                 tp->cp_cmd |= RxChkSum;
1533         else
1534                 tp->cp_cmd &= ~RxChkSum;
1535
1536         if (features & NETIF_F_HW_VLAN_CTAG_RX)
1537                 tp->cp_cmd |= RxVlan;
1538         else
1539                 tp->cp_cmd &= ~RxVlan;
1540
1541         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1542         RTL_R16(tp, CPlusCmd);
1543
1544         rtl_unlock_work(tp);
1545
1546         return 0;
1547 }
1548
1549 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1550 {
1551         return (skb_vlan_tag_present(skb)) ?
1552                 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1553 }
1554
1555 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1556 {
1557         u32 opts2 = le32_to_cpu(desc->opts2);
1558
1559         if (opts2 & RxVlanTag)
1560                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1561 }
1562
1563 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1564                              void *p)
1565 {
1566         struct rtl8169_private *tp = netdev_priv(dev);
1567         u32 __iomem *data = tp->mmio_addr;
1568         u32 *dw = p;
1569         int i;
1570
1571         rtl_lock_work(tp);
1572         for (i = 0; i < R8169_REGS_SIZE; i += 4)
1573                 memcpy_fromio(dw++, data++, 4);
1574         rtl_unlock_work(tp);
1575 }
1576
1577 static u32 rtl8169_get_msglevel(struct net_device *dev)
1578 {
1579         struct rtl8169_private *tp = netdev_priv(dev);
1580
1581         return tp->msg_enable;
1582 }
1583
1584 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1585 {
1586         struct rtl8169_private *tp = netdev_priv(dev);
1587
1588         tp->msg_enable = value;
1589 }
1590
1591 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1592         "tx_packets",
1593         "rx_packets",
1594         "tx_errors",
1595         "rx_errors",
1596         "rx_missed",
1597         "align_errors",
1598         "tx_single_collisions",
1599         "tx_multi_collisions",
1600         "unicast",
1601         "broadcast",
1602         "multicast",
1603         "tx_aborted",
1604         "tx_underrun",
1605 };
1606
1607 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1608 {
1609         switch (sset) {
1610         case ETH_SS_STATS:
1611                 return ARRAY_SIZE(rtl8169_gstrings);
1612         default:
1613                 return -EOPNOTSUPP;
1614         }
1615 }
1616
1617 DECLARE_RTL_COND(rtl_counters_cond)
1618 {
1619         return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
1620 }
1621
1622 static bool rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
1623 {
1624         dma_addr_t paddr = tp->counters_phys_addr;
1625         u32 cmd;
1626
1627         RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
1628         RTL_R32(tp, CounterAddrHigh);
1629         cmd = (u64)paddr & DMA_BIT_MASK(32);
1630         RTL_W32(tp, CounterAddrLow, cmd);
1631         RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
1632
1633         return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
1634 }
1635
1636 static bool rtl8169_reset_counters(struct rtl8169_private *tp)
1637 {
1638         /*
1639          * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
1640          * tally counters.
1641          */
1642         if (tp->mac_version < RTL_GIGA_MAC_VER_19)
1643                 return true;
1644
1645         return rtl8169_do_counters(tp, CounterReset);
1646 }
1647
1648 static bool rtl8169_update_counters(struct rtl8169_private *tp)
1649 {
1650         u8 val = RTL_R8(tp, ChipCmd);
1651
1652         /*
1653          * Some chips are unable to dump tally counters when the receiver
1654          * is disabled. If 0xff chip may be in a PCI power-save state.
1655          */
1656         if (!(val & CmdRxEnb) || val == 0xff)
1657                 return true;
1658
1659         return rtl8169_do_counters(tp, CounterDump);
1660 }
1661
1662 static bool rtl8169_init_counter_offsets(struct rtl8169_private *tp)
1663 {
1664         struct rtl8169_counters *counters = tp->counters;
1665         bool ret = false;
1666
1667         /*
1668          * rtl8169_init_counter_offsets is called from rtl_open.  On chip
1669          * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1670          * reset by a power cycle, while the counter values collected by the
1671          * driver are reset at every driver unload/load cycle.
1672          *
1673          * To make sure the HW values returned by @get_stats64 match the SW
1674          * values, we collect the initial values at first open(*) and use them
1675          * as offsets to normalize the values returned by @get_stats64.
1676          *
1677          * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1678          * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1679          * set at open time by rtl_hw_start.
1680          */
1681
1682         if (tp->tc_offset.inited)
1683                 return true;
1684
1685         /* If both, reset and update fail, propagate to caller. */
1686         if (rtl8169_reset_counters(tp))
1687                 ret = true;
1688
1689         if (rtl8169_update_counters(tp))
1690                 ret = true;
1691
1692         tp->tc_offset.tx_errors = counters->tx_errors;
1693         tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1694         tp->tc_offset.tx_aborted = counters->tx_aborted;
1695         tp->tc_offset.inited = true;
1696
1697         return ret;
1698 }
1699
1700 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1701                                       struct ethtool_stats *stats, u64 *data)
1702 {
1703         struct rtl8169_private *tp = netdev_priv(dev);
1704         struct device *d = tp_to_dev(tp);
1705         struct rtl8169_counters *counters = tp->counters;
1706
1707         ASSERT_RTNL();
1708
1709         pm_runtime_get_noresume(d);
1710
1711         if (pm_runtime_active(d))
1712                 rtl8169_update_counters(tp);
1713
1714         pm_runtime_put_noidle(d);
1715
1716         data[0] = le64_to_cpu(counters->tx_packets);
1717         data[1] = le64_to_cpu(counters->rx_packets);
1718         data[2] = le64_to_cpu(counters->tx_errors);
1719         data[3] = le32_to_cpu(counters->rx_errors);
1720         data[4] = le16_to_cpu(counters->rx_missed);
1721         data[5] = le16_to_cpu(counters->align_errors);
1722         data[6] = le32_to_cpu(counters->tx_one_collision);
1723         data[7] = le32_to_cpu(counters->tx_multi_collision);
1724         data[8] = le64_to_cpu(counters->rx_unicast);
1725         data[9] = le64_to_cpu(counters->rx_broadcast);
1726         data[10] = le32_to_cpu(counters->rx_multicast);
1727         data[11] = le16_to_cpu(counters->tx_aborted);
1728         data[12] = le16_to_cpu(counters->tx_underun);
1729 }
1730
1731 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1732 {
1733         switch(stringset) {
1734         case ETH_SS_STATS:
1735                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1736                 break;
1737         }
1738 }
1739
1740 /*
1741  * Interrupt coalescing
1742  *
1743  * > 1 - the availability of the IntrMitigate (0xe2) register through the
1744  * >     8169, 8168 and 810x line of chipsets
1745  *
1746  * 8169, 8168, and 8136(810x) serial chipsets support it.
1747  *
1748  * > 2 - the Tx timer unit at gigabit speed
1749  *
1750  * The unit of the timer depends on both the speed and the setting of CPlusCmd
1751  * (0xe0) bit 1 and bit 0.
1752  *
1753  * For 8169
1754  * bit[1:0] \ speed        1000M           100M            10M
1755  * 0 0                     320ns           2.56us          40.96us
1756  * 0 1                     2.56us          20.48us         327.7us
1757  * 1 0                     5.12us          40.96us         655.4us
1758  * 1 1                     10.24us         81.92us         1.31ms
1759  *
1760  * For the other
1761  * bit[1:0] \ speed        1000M           100M            10M
1762  * 0 0                     5us             2.56us          40.96us
1763  * 0 1                     40us            20.48us         327.7us
1764  * 1 0                     80us            40.96us         655.4us
1765  * 1 1                     160us           81.92us         1.31ms
1766  */
1767
1768 /* rx/tx scale factors for one particular CPlusCmd[0:1] value */
1769 struct rtl_coalesce_scale {
1770         /* Rx / Tx */
1771         u32 nsecs[2];
1772 };
1773
1774 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
1775 struct rtl_coalesce_info {
1776         u32 speed;
1777         struct rtl_coalesce_scale scalev[4];    /* each CPlusCmd[0:1] case */
1778 };
1779
1780 /* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */
1781 #define rxtx_x1822(r, t) {              \
1782         {{(r),          (t)}},          \
1783         {{(r)*8,        (t)*8}},        \
1784         {{(r)*8*2,      (t)*8*2}},      \
1785         {{(r)*8*2*2,    (t)*8*2*2}},    \
1786 }
1787 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1788         /* speed        delays:     rx00   tx00 */
1789         { SPEED_10,     rxtx_x1822(40960, 40960)        },
1790         { SPEED_100,    rxtx_x1822( 2560,  2560)        },
1791         { SPEED_1000,   rxtx_x1822(  320,   320)        },
1792         { 0 },
1793 };
1794
1795 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1796         /* speed        delays:     rx00   tx00 */
1797         { SPEED_10,     rxtx_x1822(40960, 40960)        },
1798         { SPEED_100,    rxtx_x1822( 2560,  2560)        },
1799         { SPEED_1000,   rxtx_x1822( 5000,  5000)        },
1800         { 0 },
1801 };
1802 #undef rxtx_x1822
1803
1804 /* get rx/tx scale vector corresponding to current speed */
1805 static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev)
1806 {
1807         struct rtl8169_private *tp = netdev_priv(dev);
1808         struct ethtool_link_ksettings ecmd;
1809         const struct rtl_coalesce_info *ci;
1810         int rc;
1811
1812         rc = phy_ethtool_get_link_ksettings(dev, &ecmd);
1813         if (rc < 0)
1814                 return ERR_PTR(rc);
1815
1816         for (ci = tp->coalesce_info; ci->speed != 0; ci++) {
1817                 if (ecmd.base.speed == ci->speed) {
1818                         return ci;
1819                 }
1820         }
1821
1822         return ERR_PTR(-ELNRNG);
1823 }
1824
1825 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1826 {
1827         struct rtl8169_private *tp = netdev_priv(dev);
1828         const struct rtl_coalesce_info *ci;
1829         const struct rtl_coalesce_scale *scale;
1830         struct {
1831                 u32 *max_frames;
1832                 u32 *usecs;
1833         } coal_settings [] = {
1834                 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs },
1835                 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs }
1836         }, *p = coal_settings;
1837         int i;
1838         u16 w;
1839
1840         memset(ec, 0, sizeof(*ec));
1841
1842         /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1843         ci = rtl_coalesce_info(dev);
1844         if (IS_ERR(ci))
1845                 return PTR_ERR(ci);
1846
1847         scale = &ci->scalev[tp->cp_cmd & INTT_MASK];
1848
1849         /* read IntrMitigate and adjust according to scale */
1850         for (w = RTL_R16(tp, IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) {
1851                 *p->max_frames = (w & RTL_COALESCE_MASK) << 2;
1852                 w >>= RTL_COALESCE_SHIFT;
1853                 *p->usecs = w & RTL_COALESCE_MASK;
1854         }
1855
1856         for (i = 0; i < 2; i++) {
1857                 p = coal_settings + i;
1858                 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000;
1859
1860                 /*
1861                  * ethtool_coalesce says it is illegal to set both usecs and
1862                  * max_frames to 0.
1863                  */
1864                 if (!*p->usecs && !*p->max_frames)
1865                         *p->max_frames = 1;
1866         }
1867
1868         return 0;
1869 }
1870
1871 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */
1872 static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale(
1873                         struct net_device *dev, u32 nsec, u16 *cp01)
1874 {
1875         const struct rtl_coalesce_info *ci;
1876         u16 i;
1877
1878         ci = rtl_coalesce_info(dev);
1879         if (IS_ERR(ci))
1880                 return ERR_CAST(ci);
1881
1882         for (i = 0; i < 4; i++) {
1883                 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0],
1884                                         ci->scalev[i].nsecs[1]);
1885                 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) {
1886                         *cp01 = i;
1887                         return &ci->scalev[i];
1888                 }
1889         }
1890
1891         return ERR_PTR(-EINVAL);
1892 }
1893
1894 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1895 {
1896         struct rtl8169_private *tp = netdev_priv(dev);
1897         const struct rtl_coalesce_scale *scale;
1898         struct {
1899                 u32 frames;
1900                 u32 usecs;
1901         } coal_settings [] = {
1902                 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs },
1903                 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs }
1904         }, *p = coal_settings;
1905         u16 w = 0, cp01;
1906         int i;
1907
1908         scale = rtl_coalesce_choose_scale(dev,
1909                         max(p[0].usecs, p[1].usecs) * 1000, &cp01);
1910         if (IS_ERR(scale))
1911                 return PTR_ERR(scale);
1912
1913         for (i = 0; i < 2; i++, p++) {
1914                 u32 units;
1915
1916                 /*
1917                  * accept max_frames=1 we returned in rtl_get_coalesce.
1918                  * accept it not only when usecs=0 because of e.g. the following scenario:
1919                  *
1920                  * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
1921                  * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
1922                  * - then user does `ethtool -C eth0 rx-usecs 100`
1923                  *
1924                  * since ethtool sends to kernel whole ethtool_coalesce
1925                  * settings, if we do not handle rx_usecs=!0, rx_frames=1
1926                  * we'll reject it below in `frames % 4 != 0`.
1927                  */
1928                 if (p->frames == 1) {
1929                         p->frames = 0;
1930                 }
1931
1932                 units = p->usecs * 1000 / scale->nsecs[i];
1933                 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4)
1934                         return -EINVAL;
1935
1936                 w <<= RTL_COALESCE_SHIFT;
1937                 w |= units;
1938                 w <<= RTL_COALESCE_SHIFT;
1939                 w |= p->frames >> 2;
1940         }
1941
1942         rtl_lock_work(tp);
1943
1944         RTL_W16(tp, IntrMitigate, swab16(w));
1945
1946         tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
1947         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1948         RTL_R16(tp, CPlusCmd);
1949
1950         rtl_unlock_work(tp);
1951
1952         return 0;
1953 }
1954
1955 static int rtl_get_eee_supp(struct rtl8169_private *tp)
1956 {
1957         struct phy_device *phydev = tp->phydev;
1958         int ret;
1959
1960         switch (tp->mac_version) {
1961         case RTL_GIGA_MAC_VER_34:
1962         case RTL_GIGA_MAC_VER_35:
1963         case RTL_GIGA_MAC_VER_36:
1964         case RTL_GIGA_MAC_VER_38:
1965                 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
1966                 break;
1967         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1968                 phy_write(phydev, 0x1f, 0x0a5c);
1969                 ret = phy_read(phydev, 0x12);
1970                 phy_write(phydev, 0x1f, 0x0000);
1971                 break;
1972         default:
1973                 ret = -EPROTONOSUPPORT;
1974                 break;
1975         }
1976
1977         return ret;
1978 }
1979
1980 static int rtl_get_eee_lpadv(struct rtl8169_private *tp)
1981 {
1982         struct phy_device *phydev = tp->phydev;
1983         int ret;
1984
1985         switch (tp->mac_version) {
1986         case RTL_GIGA_MAC_VER_34:
1987         case RTL_GIGA_MAC_VER_35:
1988         case RTL_GIGA_MAC_VER_36:
1989         case RTL_GIGA_MAC_VER_38:
1990                 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
1991                 break;
1992         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1993                 phy_write(phydev, 0x1f, 0x0a5d);
1994                 ret = phy_read(phydev, 0x11);
1995                 phy_write(phydev, 0x1f, 0x0000);
1996                 break;
1997         default:
1998                 ret = -EPROTONOSUPPORT;
1999                 break;
2000         }
2001
2002         return ret;
2003 }
2004
2005 static int rtl_get_eee_adv(struct rtl8169_private *tp)
2006 {
2007         struct phy_device *phydev = tp->phydev;
2008         int ret;
2009
2010         switch (tp->mac_version) {
2011         case RTL_GIGA_MAC_VER_34:
2012         case RTL_GIGA_MAC_VER_35:
2013         case RTL_GIGA_MAC_VER_36:
2014         case RTL_GIGA_MAC_VER_38:
2015                 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
2016                 break;
2017         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
2018                 phy_write(phydev, 0x1f, 0x0a5d);
2019                 ret = phy_read(phydev, 0x10);
2020                 phy_write(phydev, 0x1f, 0x0000);
2021                 break;
2022         default:
2023                 ret = -EPROTONOSUPPORT;
2024                 break;
2025         }
2026
2027         return ret;
2028 }
2029
2030 static int rtl_set_eee_adv(struct rtl8169_private *tp, int val)
2031 {
2032         struct phy_device *phydev = tp->phydev;
2033         int ret = 0;
2034
2035         switch (tp->mac_version) {
2036         case RTL_GIGA_MAC_VER_34:
2037         case RTL_GIGA_MAC_VER_35:
2038         case RTL_GIGA_MAC_VER_36:
2039         case RTL_GIGA_MAC_VER_38:
2040                 ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
2041                 break;
2042         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
2043                 phy_write(phydev, 0x1f, 0x0a5d);
2044                 phy_write(phydev, 0x10, val);
2045                 phy_write(phydev, 0x1f, 0x0000);
2046                 break;
2047         default:
2048                 ret = -EPROTONOSUPPORT;
2049                 break;
2050         }
2051
2052         return ret;
2053 }
2054
2055 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data)
2056 {
2057         struct rtl8169_private *tp = netdev_priv(dev);
2058         struct device *d = tp_to_dev(tp);
2059         int ret;
2060
2061         pm_runtime_get_noresume(d);
2062
2063         if (!pm_runtime_active(d)) {
2064                 ret = -EOPNOTSUPP;
2065                 goto out;
2066         }
2067
2068         /* Get Supported EEE */
2069         ret = rtl_get_eee_supp(tp);
2070         if (ret < 0)
2071                 goto out;
2072         data->supported = mmd_eee_cap_to_ethtool_sup_t(ret);
2073
2074         /* Get advertisement EEE */
2075         ret = rtl_get_eee_adv(tp);
2076         if (ret < 0)
2077                 goto out;
2078         data->advertised = mmd_eee_adv_to_ethtool_adv_t(ret);
2079         data->eee_enabled = !!data->advertised;
2080
2081         /* Get LP advertisement EEE */
2082         ret = rtl_get_eee_lpadv(tp);
2083         if (ret < 0)
2084                 goto out;
2085         data->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(ret);
2086         data->eee_active = !!(data->advertised & data->lp_advertised);
2087 out:
2088         pm_runtime_put_noidle(d);
2089         return ret < 0 ? ret : 0;
2090 }
2091
2092 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data)
2093 {
2094         struct rtl8169_private *tp = netdev_priv(dev);
2095         struct device *d = tp_to_dev(tp);
2096         int old_adv, adv = 0, cap, ret;
2097
2098         pm_runtime_get_noresume(d);
2099
2100         if (!dev->phydev || !pm_runtime_active(d)) {
2101                 ret = -EOPNOTSUPP;
2102                 goto out;
2103         }
2104
2105         if (dev->phydev->autoneg == AUTONEG_DISABLE ||
2106             dev->phydev->duplex != DUPLEX_FULL) {
2107                 ret = -EPROTONOSUPPORT;
2108                 goto out;
2109         }
2110
2111         /* Get Supported EEE */
2112         ret = rtl_get_eee_supp(tp);
2113         if (ret < 0)
2114                 goto out;
2115         cap = ret;
2116
2117         ret = rtl_get_eee_adv(tp);
2118         if (ret < 0)
2119                 goto out;
2120         old_adv = ret;
2121
2122         if (data->eee_enabled) {
2123                 adv = !data->advertised ? cap :
2124                       ethtool_adv_to_mmd_eee_adv_t(data->advertised) & cap;
2125                 /* Mask prohibited EEE modes */
2126                 adv &= ~dev->phydev->eee_broken_modes;
2127         }
2128
2129         if (old_adv != adv) {
2130                 ret = rtl_set_eee_adv(tp, adv);
2131                 if (ret < 0)
2132                         goto out;
2133
2134                 /* Restart autonegotiation so the new modes get sent to the
2135                  * link partner.
2136                  */
2137                 ret = phy_restart_aneg(dev->phydev);
2138         }
2139
2140 out:
2141         pm_runtime_put_noidle(d);
2142         return ret < 0 ? ret : 0;
2143 }
2144
2145 static const struct ethtool_ops rtl8169_ethtool_ops = {
2146         .get_drvinfo            = rtl8169_get_drvinfo,
2147         .get_regs_len           = rtl8169_get_regs_len,
2148         .get_link               = ethtool_op_get_link,
2149         .get_coalesce           = rtl_get_coalesce,
2150         .set_coalesce           = rtl_set_coalesce,
2151         .get_msglevel           = rtl8169_get_msglevel,
2152         .set_msglevel           = rtl8169_set_msglevel,
2153         .get_regs               = rtl8169_get_regs,
2154         .get_wol                = rtl8169_get_wol,
2155         .set_wol                = rtl8169_set_wol,
2156         .get_strings            = rtl8169_get_strings,
2157         .get_sset_count         = rtl8169_get_sset_count,
2158         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
2159         .get_ts_info            = ethtool_op_get_ts_info,
2160         .nway_reset             = phy_ethtool_nway_reset,
2161         .get_eee                = rtl8169_get_eee,
2162         .set_eee                = rtl8169_set_eee,
2163         .get_link_ksettings     = phy_ethtool_get_link_ksettings,
2164         .set_link_ksettings     = phy_ethtool_set_link_ksettings,
2165 };
2166
2167 static void rtl_enable_eee(struct rtl8169_private *tp)
2168 {
2169         int supported = rtl_get_eee_supp(tp);
2170
2171         if (supported > 0)
2172                 rtl_set_eee_adv(tp, supported);
2173 }
2174
2175 static void rtl8169_get_mac_version(struct rtl8169_private *tp)
2176 {
2177         /*
2178          * The driver currently handles the 8168Bf and the 8168Be identically
2179          * but they can be identified more specifically through the test below
2180          * if needed:
2181          *
2182          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2183          *
2184          * Same thing for the 8101Eb and the 8101Ec:
2185          *
2186          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2187          */
2188         static const struct rtl_mac_info {
2189                 u16 mask;
2190                 u16 val;
2191                 u16 mac_version;
2192         } mac_info[] = {
2193                 /* 8168EP family. */
2194                 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 },
2195                 { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 },
2196                 { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 },
2197
2198                 /* 8168H family. */
2199                 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 },
2200                 { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 },
2201
2202                 /* 8168G family. */
2203                 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 },
2204                 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 },
2205                 { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 },
2206                 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 },
2207
2208                 /* 8168F family. */
2209                 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 },
2210                 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 },
2211                 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 },
2212
2213                 /* 8168E family. */
2214                 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 },
2215                 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 },
2216                 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 },
2217
2218                 /* 8168D family. */
2219                 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 },
2220                 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 },
2221
2222                 /* 8168DP family. */
2223                 { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 },
2224                 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 },
2225                 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 },
2226
2227                 /* 8168C family. */
2228                 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 },
2229                 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 },
2230                 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 },
2231                 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 },
2232                 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 },
2233                 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 },
2234                 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 },
2235
2236                 /* 8168B family. */
2237                 { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12 },
2238                 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 },
2239                 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 },
2240
2241                 /* 8101 family. */
2242                 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 },
2243                 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 },
2244                 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 },
2245                 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 },
2246                 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 },
2247                 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 },
2248                 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 },
2249                 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 },
2250                 { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13 },
2251                 { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10 },
2252                 { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16 },
2253                 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 },
2254                 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 },
2255                 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16 },
2256                 /* FIXME: where did these entries come from ? -- FR */
2257                 { 0xfc8, 0x388, RTL_GIGA_MAC_VER_15 },
2258                 { 0xfc8, 0x308, RTL_GIGA_MAC_VER_14 },
2259
2260                 /* 8110 family. */
2261                 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 },
2262                 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 },
2263                 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 },
2264                 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 },
2265                 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 },
2266                 { 0xfc8, 0x000, RTL_GIGA_MAC_VER_01 },
2267
2268                 /* Catch-all */
2269                 { 0x000, 0x000, RTL_GIGA_MAC_NONE   }
2270         };
2271         const struct rtl_mac_info *p = mac_info;
2272         u16 reg = RTL_R32(tp, TxConfig) >> 20;
2273
2274         while ((reg & p->mask) != p->val)
2275                 p++;
2276         tp->mac_version = p->mac_version;
2277
2278         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2279                 dev_err(tp_to_dev(tp), "unknown chip XID %03x\n", reg & 0xfcf);
2280         } else if (!tp->supports_gmii) {
2281                 if (tp->mac_version == RTL_GIGA_MAC_VER_42)
2282                         tp->mac_version = RTL_GIGA_MAC_VER_43;
2283                 else if (tp->mac_version == RTL_GIGA_MAC_VER_45)
2284                         tp->mac_version = RTL_GIGA_MAC_VER_47;
2285                 else if (tp->mac_version == RTL_GIGA_MAC_VER_46)
2286                         tp->mac_version = RTL_GIGA_MAC_VER_48;
2287         }
2288 }
2289
2290 struct phy_reg {
2291         u16 reg;
2292         u16 val;
2293 };
2294
2295 static void rtl_writephy_batch(struct rtl8169_private *tp,
2296                                const struct phy_reg *regs, int len)
2297 {
2298         while (len-- > 0) {
2299                 rtl_writephy(tp, regs->reg, regs->val);
2300                 regs++;
2301         }
2302 }
2303
2304 #define PHY_READ                0x00000000
2305 #define PHY_DATA_OR             0x10000000
2306 #define PHY_DATA_AND            0x20000000
2307 #define PHY_BJMPN               0x30000000
2308 #define PHY_MDIO_CHG            0x40000000
2309 #define PHY_CLEAR_READCOUNT     0x70000000
2310 #define PHY_WRITE               0x80000000
2311 #define PHY_READCOUNT_EQ_SKIP   0x90000000
2312 #define PHY_COMP_EQ_SKIPN       0xa0000000
2313 #define PHY_COMP_NEQ_SKIPN      0xb0000000
2314 #define PHY_WRITE_PREVIOUS      0xc0000000
2315 #define PHY_SKIPN               0xd0000000
2316 #define PHY_DELAY_MS            0xe0000000
2317
2318 struct fw_info {
2319         u32     magic;
2320         char    version[RTL_VER_SIZE];
2321         __le32  fw_start;
2322         __le32  fw_len;
2323         u8      chksum;
2324 } __packed;
2325
2326 #define FW_OPCODE_SIZE  sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2327
2328 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2329 {
2330         const struct firmware *fw = rtl_fw->fw;
2331         struct fw_info *fw_info = (struct fw_info *)fw->data;
2332         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2333         char *version = rtl_fw->version;
2334         bool rc = false;
2335
2336         if (fw->size < FW_OPCODE_SIZE)
2337                 goto out;
2338
2339         if (!fw_info->magic) {
2340                 size_t i, size, start;
2341                 u8 checksum = 0;
2342
2343                 if (fw->size < sizeof(*fw_info))
2344                         goto out;
2345
2346                 for (i = 0; i < fw->size; i++)
2347                         checksum += fw->data[i];
2348                 if (checksum != 0)
2349                         goto out;
2350
2351                 start = le32_to_cpu(fw_info->fw_start);
2352                 if (start > fw->size)
2353                         goto out;
2354
2355                 size = le32_to_cpu(fw_info->fw_len);
2356                 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2357                         goto out;
2358
2359                 memcpy(version, fw_info->version, RTL_VER_SIZE);
2360
2361                 pa->code = (__le32 *)(fw->data + start);
2362                 pa->size = size;
2363         } else {
2364                 if (fw->size % FW_OPCODE_SIZE)
2365                         goto out;
2366
2367                 strlcpy(version, tp->fw_name, RTL_VER_SIZE);
2368
2369                 pa->code = (__le32 *)fw->data;
2370                 pa->size = fw->size / FW_OPCODE_SIZE;
2371         }
2372         version[RTL_VER_SIZE - 1] = 0;
2373
2374         rc = true;
2375 out:
2376         return rc;
2377 }
2378
2379 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2380                            struct rtl_fw_phy_action *pa)
2381 {
2382         bool rc = false;
2383         size_t index;
2384
2385         for (index = 0; index < pa->size; index++) {
2386                 u32 action = le32_to_cpu(pa->code[index]);
2387                 u32 regno = (action & 0x0fff0000) >> 16;
2388
2389                 switch(action & 0xf0000000) {
2390                 case PHY_READ:
2391                 case PHY_DATA_OR:
2392                 case PHY_DATA_AND:
2393                 case PHY_MDIO_CHG:
2394                 case PHY_CLEAR_READCOUNT:
2395                 case PHY_WRITE:
2396                 case PHY_WRITE_PREVIOUS:
2397                 case PHY_DELAY_MS:
2398                         break;
2399
2400                 case PHY_BJMPN:
2401                         if (regno > index) {
2402                                 netif_err(tp, ifup, tp->dev,
2403                                           "Out of range of firmware\n");
2404                                 goto out;
2405                         }
2406                         break;
2407                 case PHY_READCOUNT_EQ_SKIP:
2408                         if (index + 2 >= pa->size) {
2409                                 netif_err(tp, ifup, tp->dev,
2410                                           "Out of range of firmware\n");
2411                                 goto out;
2412                         }
2413                         break;
2414                 case PHY_COMP_EQ_SKIPN:
2415                 case PHY_COMP_NEQ_SKIPN:
2416                 case PHY_SKIPN:
2417                         if (index + 1 + regno >= pa->size) {
2418                                 netif_err(tp, ifup, tp->dev,
2419                                           "Out of range of firmware\n");
2420                                 goto out;
2421                         }
2422                         break;
2423
2424                 default:
2425                         netif_err(tp, ifup, tp->dev,
2426                                   "Invalid action 0x%08x\n", action);
2427                         goto out;
2428                 }
2429         }
2430         rc = true;
2431 out:
2432         return rc;
2433 }
2434
2435 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2436 {
2437         struct net_device *dev = tp->dev;
2438         int rc = -EINVAL;
2439
2440         if (!rtl_fw_format_ok(tp, rtl_fw)) {
2441                 netif_err(tp, ifup, dev, "invalid firmware\n");
2442                 goto out;
2443         }
2444
2445         if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2446                 rc = 0;
2447 out:
2448         return rc;
2449 }
2450
2451 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2452 {
2453         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2454         struct mdio_ops org, *ops = &tp->mdio_ops;
2455         u32 predata, count;
2456         size_t index;
2457
2458         predata = count = 0;
2459         org.write = ops->write;
2460         org.read = ops->read;
2461
2462         for (index = 0; index < pa->size; ) {
2463                 u32 action = le32_to_cpu(pa->code[index]);
2464                 u32 data = action & 0x0000ffff;
2465                 u32 regno = (action & 0x0fff0000) >> 16;
2466
2467                 if (!action)
2468                         break;
2469
2470                 switch(action & 0xf0000000) {
2471                 case PHY_READ:
2472                         predata = rtl_readphy(tp, regno);
2473                         count++;
2474                         index++;
2475                         break;
2476                 case PHY_DATA_OR:
2477                         predata |= data;
2478                         index++;
2479                         break;
2480                 case PHY_DATA_AND:
2481                         predata &= data;
2482                         index++;
2483                         break;
2484                 case PHY_BJMPN:
2485                         index -= regno;
2486                         break;
2487                 case PHY_MDIO_CHG:
2488                         if (data == 0) {
2489                                 ops->write = org.write;
2490                                 ops->read = org.read;
2491                         } else if (data == 1) {
2492                                 ops->write = mac_mcu_write;
2493                                 ops->read = mac_mcu_read;
2494                         }
2495
2496                         index++;
2497                         break;
2498                 case PHY_CLEAR_READCOUNT:
2499                         count = 0;
2500                         index++;
2501                         break;
2502                 case PHY_WRITE:
2503                         rtl_writephy(tp, regno, data);
2504                         index++;
2505                         break;
2506                 case PHY_READCOUNT_EQ_SKIP:
2507                         index += (count == data) ? 2 : 1;
2508                         break;
2509                 case PHY_COMP_EQ_SKIPN:
2510                         if (predata == data)
2511                                 index += regno;
2512                         index++;
2513                         break;
2514                 case PHY_COMP_NEQ_SKIPN:
2515                         if (predata != data)
2516                                 index += regno;
2517                         index++;
2518                         break;
2519                 case PHY_WRITE_PREVIOUS:
2520                         rtl_writephy(tp, regno, predata);
2521                         index++;
2522                         break;
2523                 case PHY_SKIPN:
2524                         index += regno + 1;
2525                         break;
2526                 case PHY_DELAY_MS:
2527                         mdelay(data);
2528                         index++;
2529                         break;
2530
2531                 default:
2532                         BUG();
2533                 }
2534         }
2535
2536         ops->write = org.write;
2537         ops->read = org.read;
2538 }
2539
2540 static void rtl_release_firmware(struct rtl8169_private *tp)
2541 {
2542         if (tp->rtl_fw) {
2543                 release_firmware(tp->rtl_fw->fw);
2544                 kfree(tp->rtl_fw);
2545                 tp->rtl_fw = NULL;
2546         }
2547 }
2548
2549 static void rtl_apply_firmware(struct rtl8169_private *tp)
2550 {
2551         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2552         if (tp->rtl_fw)
2553                 rtl_phy_write_fw(tp, tp->rtl_fw);
2554 }
2555
2556 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2557 {
2558         if (rtl_readphy(tp, reg) != val)
2559                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2560         else
2561                 rtl_apply_firmware(tp);
2562 }
2563
2564 static void rtl8168_config_eee_mac(struct rtl8169_private *tp)
2565 {
2566         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0003, 0x0000, ERIAR_EXGMAC);
2567 }
2568
2569 static void rtl8168f_config_eee_phy(struct rtl8169_private *tp)
2570 {
2571         struct phy_device *phydev = tp->phydev;
2572
2573         phy_write(phydev, 0x1f, 0x0007);
2574         phy_write(phydev, 0x1e, 0x0020);
2575         phy_set_bits(phydev, 0x15, BIT(8));
2576
2577         phy_write(phydev, 0x1f, 0x0005);
2578         phy_write(phydev, 0x05, 0x8b85);
2579         phy_set_bits(phydev, 0x06, BIT(13));
2580
2581         phy_write(phydev, 0x1f, 0x0000);
2582 }
2583
2584 static void rtl8168g_config_eee_phy(struct rtl8169_private *tp)
2585 {
2586         phy_write(tp->phydev, 0x1f, 0x0a43);
2587         phy_set_bits(tp->phydev, 0x11, BIT(4));
2588         phy_write(tp->phydev, 0x1f, 0x0000);
2589 }
2590
2591 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2592 {
2593         static const struct phy_reg phy_reg_init[] = {
2594                 { 0x1f, 0x0001 },
2595                 { 0x06, 0x006e },
2596                 { 0x08, 0x0708 },
2597                 { 0x15, 0x4000 },
2598                 { 0x18, 0x65c7 },
2599
2600                 { 0x1f, 0x0001 },
2601                 { 0x03, 0x00a1 },
2602                 { 0x02, 0x0008 },
2603                 { 0x01, 0x0120 },
2604                 { 0x00, 0x1000 },
2605                 { 0x04, 0x0800 },
2606                 { 0x04, 0x0000 },
2607
2608                 { 0x03, 0xff41 },
2609                 { 0x02, 0xdf60 },
2610                 { 0x01, 0x0140 },
2611                 { 0x00, 0x0077 },
2612                 { 0x04, 0x7800 },
2613                 { 0x04, 0x7000 },
2614
2615                 { 0x03, 0x802f },
2616                 { 0x02, 0x4f02 },
2617                 { 0x01, 0x0409 },
2618                 { 0x00, 0xf0f9 },
2619                 { 0x04, 0x9800 },
2620                 { 0x04, 0x9000 },
2621
2622                 { 0x03, 0xdf01 },
2623                 { 0x02, 0xdf20 },
2624                 { 0x01, 0xff95 },
2625                 { 0x00, 0xba00 },
2626                 { 0x04, 0xa800 },
2627                 { 0x04, 0xa000 },
2628
2629                 { 0x03, 0xff41 },
2630                 { 0x02, 0xdf20 },
2631                 { 0x01, 0x0140 },
2632                 { 0x00, 0x00bb },
2633                 { 0x04, 0xb800 },
2634                 { 0x04, 0xb000 },
2635
2636                 { 0x03, 0xdf41 },
2637                 { 0x02, 0xdc60 },
2638                 { 0x01, 0x6340 },
2639                 { 0x00, 0x007d },
2640                 { 0x04, 0xd800 },
2641                 { 0x04, 0xd000 },
2642
2643                 { 0x03, 0xdf01 },
2644                 { 0x02, 0xdf20 },
2645                 { 0x01, 0x100a },
2646                 { 0x00, 0xa0ff },
2647                 { 0x04, 0xf800 },
2648                 { 0x04, 0xf000 },
2649
2650                 { 0x1f, 0x0000 },
2651                 { 0x0b, 0x0000 },
2652                 { 0x00, 0x9200 }
2653         };
2654
2655         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2656 }
2657
2658 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2659 {
2660         static const struct phy_reg phy_reg_init[] = {
2661                 { 0x1f, 0x0002 },
2662                 { 0x01, 0x90d0 },
2663                 { 0x1f, 0x0000 }
2664         };
2665
2666         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2667 }
2668
2669 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2670 {
2671         struct pci_dev *pdev = tp->pci_dev;
2672
2673         if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2674             (pdev->subsystem_device != 0xe000))
2675                 return;
2676
2677         rtl_writephy(tp, 0x1f, 0x0001);
2678         rtl_writephy(tp, 0x10, 0xf01b);
2679         rtl_writephy(tp, 0x1f, 0x0000);
2680 }
2681
2682 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2683 {
2684         static const struct phy_reg phy_reg_init[] = {
2685                 { 0x1f, 0x0001 },
2686                 { 0x04, 0x0000 },
2687                 { 0x03, 0x00a1 },
2688                 { 0x02, 0x0008 },
2689                 { 0x01, 0x0120 },
2690                 { 0x00, 0x1000 },
2691                 { 0x04, 0x0800 },
2692                 { 0x04, 0x9000 },
2693                 { 0x03, 0x802f },
2694                 { 0x02, 0x4f02 },
2695                 { 0x01, 0x0409 },
2696                 { 0x00, 0xf099 },
2697                 { 0x04, 0x9800 },
2698                 { 0x04, 0xa000 },
2699                 { 0x03, 0xdf01 },
2700                 { 0x02, 0xdf20 },
2701                 { 0x01, 0xff95 },
2702                 { 0x00, 0xba00 },
2703                 { 0x04, 0xa800 },
2704                 { 0x04, 0xf000 },
2705                 { 0x03, 0xdf01 },
2706                 { 0x02, 0xdf20 },
2707                 { 0x01, 0x101a },
2708                 { 0x00, 0xa0ff },
2709                 { 0x04, 0xf800 },
2710                 { 0x04, 0x0000 },
2711                 { 0x1f, 0x0000 },
2712
2713                 { 0x1f, 0x0001 },
2714                 { 0x10, 0xf41b },
2715                 { 0x14, 0xfb54 },
2716                 { 0x18, 0xf5c7 },
2717                 { 0x1f, 0x0000 },
2718
2719                 { 0x1f, 0x0001 },
2720                 { 0x17, 0x0cc0 },
2721                 { 0x1f, 0x0000 }
2722         };
2723
2724         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2725
2726         rtl8169scd_hw_phy_config_quirk(tp);
2727 }
2728
2729 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2730 {
2731         static const struct phy_reg phy_reg_init[] = {
2732                 { 0x1f, 0x0001 },
2733                 { 0x04, 0x0000 },
2734                 { 0x03, 0x00a1 },
2735                 { 0x02, 0x0008 },
2736                 { 0x01, 0x0120 },
2737                 { 0x00, 0x1000 },
2738                 { 0x04, 0x0800 },
2739                 { 0x04, 0x9000 },
2740                 { 0x03, 0x802f },
2741                 { 0x02, 0x4f02 },
2742                 { 0x01, 0x0409 },
2743                 { 0x00, 0xf099 },
2744                 { 0x04, 0x9800 },
2745                 { 0x04, 0xa000 },
2746                 { 0x03, 0xdf01 },
2747                 { 0x02, 0xdf20 },
2748                 { 0x01, 0xff95 },
2749                 { 0x00, 0xba00 },
2750                 { 0x04, 0xa800 },
2751                 { 0x04, 0xf000 },
2752                 { 0x03, 0xdf01 },
2753                 { 0x02, 0xdf20 },
2754                 { 0x01, 0x101a },
2755                 { 0x00, 0xa0ff },
2756                 { 0x04, 0xf800 },
2757                 { 0x04, 0x0000 },
2758                 { 0x1f, 0x0000 },
2759
2760                 { 0x1f, 0x0001 },
2761                 { 0x0b, 0x8480 },
2762                 { 0x1f, 0x0000 },
2763
2764                 { 0x1f, 0x0001 },
2765                 { 0x18, 0x67c7 },
2766                 { 0x04, 0x2000 },
2767                 { 0x03, 0x002f },
2768                 { 0x02, 0x4360 },
2769                 { 0x01, 0x0109 },
2770                 { 0x00, 0x3022 },
2771                 { 0x04, 0x2800 },
2772                 { 0x1f, 0x0000 },
2773
2774                 { 0x1f, 0x0001 },
2775                 { 0x17, 0x0cc0 },
2776                 { 0x1f, 0x0000 }
2777         };
2778
2779         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2780 }
2781
2782 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2783 {
2784         static const struct phy_reg phy_reg_init[] = {
2785                 { 0x10, 0xf41b },
2786                 { 0x1f, 0x0000 }
2787         };
2788
2789         rtl_writephy(tp, 0x1f, 0x0001);
2790         rtl_patchphy(tp, 0x16, 1 << 0);
2791
2792         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2793 }
2794
2795 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2796 {
2797         static const struct phy_reg phy_reg_init[] = {
2798                 { 0x1f, 0x0001 },
2799                 { 0x10, 0xf41b },
2800                 { 0x1f, 0x0000 }
2801         };
2802
2803         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2804 }
2805
2806 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2807 {
2808         static const struct phy_reg phy_reg_init[] = {
2809                 { 0x1f, 0x0000 },
2810                 { 0x1d, 0x0f00 },
2811                 { 0x1f, 0x0002 },
2812                 { 0x0c, 0x1ec8 },
2813                 { 0x1f, 0x0000 }
2814         };
2815
2816         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2817 }
2818
2819 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2820 {
2821         static const struct phy_reg phy_reg_init[] = {
2822                 { 0x1f, 0x0001 },
2823                 { 0x1d, 0x3d98 },
2824                 { 0x1f, 0x0000 }
2825         };
2826
2827         rtl_writephy(tp, 0x1f, 0x0000);
2828         rtl_patchphy(tp, 0x14, 1 << 5);
2829         rtl_patchphy(tp, 0x0d, 1 << 5);
2830
2831         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2832 }
2833
2834 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2835 {
2836         static const struct phy_reg phy_reg_init[] = {
2837                 { 0x1f, 0x0001 },
2838                 { 0x12, 0x2300 },
2839                 { 0x1f, 0x0002 },
2840                 { 0x00, 0x88d4 },
2841                 { 0x01, 0x82b1 },
2842                 { 0x03, 0x7002 },
2843                 { 0x08, 0x9e30 },
2844                 { 0x09, 0x01f0 },
2845                 { 0x0a, 0x5500 },
2846                 { 0x0c, 0x00c8 },
2847                 { 0x1f, 0x0003 },
2848                 { 0x12, 0xc096 },
2849                 { 0x16, 0x000a },
2850                 { 0x1f, 0x0000 },
2851                 { 0x1f, 0x0000 },
2852                 { 0x09, 0x2000 },
2853                 { 0x09, 0x0000 }
2854         };
2855
2856         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2857
2858         rtl_patchphy(tp, 0x14, 1 << 5);
2859         rtl_patchphy(tp, 0x0d, 1 << 5);
2860         rtl_writephy(tp, 0x1f, 0x0000);
2861 }
2862
2863 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2864 {
2865         static const struct phy_reg phy_reg_init[] = {
2866                 { 0x1f, 0x0001 },
2867                 { 0x12, 0x2300 },
2868                 { 0x03, 0x802f },
2869                 { 0x02, 0x4f02 },
2870                 { 0x01, 0x0409 },
2871                 { 0x00, 0xf099 },
2872                 { 0x04, 0x9800 },
2873                 { 0x04, 0x9000 },
2874                 { 0x1d, 0x3d98 },
2875                 { 0x1f, 0x0002 },
2876                 { 0x0c, 0x7eb8 },
2877                 { 0x06, 0x0761 },
2878                 { 0x1f, 0x0003 },
2879                 { 0x16, 0x0f0a },
2880                 { 0x1f, 0x0000 }
2881         };
2882
2883         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2884
2885         rtl_patchphy(tp, 0x16, 1 << 0);
2886         rtl_patchphy(tp, 0x14, 1 << 5);
2887         rtl_patchphy(tp, 0x0d, 1 << 5);
2888         rtl_writephy(tp, 0x1f, 0x0000);
2889 }
2890
2891 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2892 {
2893         static const struct phy_reg phy_reg_init[] = {
2894                 { 0x1f, 0x0001 },
2895                 { 0x12, 0x2300 },
2896                 { 0x1d, 0x3d98 },
2897                 { 0x1f, 0x0002 },
2898                 { 0x0c, 0x7eb8 },
2899                 { 0x06, 0x5461 },
2900                 { 0x1f, 0x0003 },
2901                 { 0x16, 0x0f0a },
2902                 { 0x1f, 0x0000 }
2903         };
2904
2905         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2906
2907         rtl_patchphy(tp, 0x16, 1 << 0);
2908         rtl_patchphy(tp, 0x14, 1 << 5);
2909         rtl_patchphy(tp, 0x0d, 1 << 5);
2910         rtl_writephy(tp, 0x1f, 0x0000);
2911 }
2912
2913 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2914 {
2915         rtl8168c_3_hw_phy_config(tp);
2916 }
2917
2918 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2919 {
2920         static const struct phy_reg phy_reg_init_0[] = {
2921                 /* Channel Estimation */
2922                 { 0x1f, 0x0001 },
2923                 { 0x06, 0x4064 },
2924                 { 0x07, 0x2863 },
2925                 { 0x08, 0x059c },
2926                 { 0x09, 0x26b4 },
2927                 { 0x0a, 0x6a19 },
2928                 { 0x0b, 0xdcc8 },
2929                 { 0x10, 0xf06d },
2930                 { 0x14, 0x7f68 },
2931                 { 0x18, 0x7fd9 },
2932                 { 0x1c, 0xf0ff },
2933                 { 0x1d, 0x3d9c },
2934                 { 0x1f, 0x0003 },
2935                 { 0x12, 0xf49f },
2936                 { 0x13, 0x070b },
2937                 { 0x1a, 0x05ad },
2938                 { 0x14, 0x94c0 },
2939
2940                 /*
2941                  * Tx Error Issue
2942                  * Enhance line driver power
2943                  */
2944                 { 0x1f, 0x0002 },
2945                 { 0x06, 0x5561 },
2946                 { 0x1f, 0x0005 },
2947                 { 0x05, 0x8332 },
2948                 { 0x06, 0x5561 },
2949
2950                 /*
2951                  * Can not link to 1Gbps with bad cable
2952                  * Decrease SNR threshold form 21.07dB to 19.04dB
2953                  */
2954                 { 0x1f, 0x0001 },
2955                 { 0x17, 0x0cc0 },
2956
2957                 { 0x1f, 0x0000 },
2958                 { 0x0d, 0xf880 }
2959         };
2960
2961         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2962
2963         /*
2964          * Rx Error Issue
2965          * Fine Tune Switching regulator parameter
2966          */
2967         rtl_writephy(tp, 0x1f, 0x0002);
2968         rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
2969         rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
2970
2971         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2972                 static const struct phy_reg phy_reg_init[] = {
2973                         { 0x1f, 0x0002 },
2974                         { 0x05, 0x669a },
2975                         { 0x1f, 0x0005 },
2976                         { 0x05, 0x8330 },
2977                         { 0x06, 0x669a },
2978                         { 0x1f, 0x0002 }
2979                 };
2980                 int val;
2981
2982                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2983
2984                 val = rtl_readphy(tp, 0x0d);
2985
2986                 if ((val & 0x00ff) != 0x006c) {
2987                         static const u32 set[] = {
2988                                 0x0065, 0x0066, 0x0067, 0x0068,
2989                                 0x0069, 0x006a, 0x006b, 0x006c
2990                         };
2991                         int i;
2992
2993                         rtl_writephy(tp, 0x1f, 0x0002);
2994
2995                         val &= 0xff00;
2996                         for (i = 0; i < ARRAY_SIZE(set); i++)
2997                                 rtl_writephy(tp, 0x0d, val | set[i]);
2998                 }
2999         } else {
3000                 static const struct phy_reg phy_reg_init[] = {
3001                         { 0x1f, 0x0002 },
3002                         { 0x05, 0x6662 },
3003                         { 0x1f, 0x0005 },
3004                         { 0x05, 0x8330 },
3005                         { 0x06, 0x6662 }
3006                 };
3007
3008                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3009         }
3010
3011         /* RSET couple improve */
3012         rtl_writephy(tp, 0x1f, 0x0002);
3013         rtl_patchphy(tp, 0x0d, 0x0300);
3014         rtl_patchphy(tp, 0x0f, 0x0010);
3015
3016         /* Fine tune PLL performance */
3017         rtl_writephy(tp, 0x1f, 0x0002);
3018         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3019         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3020
3021         rtl_writephy(tp, 0x1f, 0x0005);
3022         rtl_writephy(tp, 0x05, 0x001b);
3023
3024         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
3025
3026         rtl_writephy(tp, 0x1f, 0x0000);
3027 }
3028
3029 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
3030 {
3031         static const struct phy_reg phy_reg_init_0[] = {
3032                 /* Channel Estimation */
3033                 { 0x1f, 0x0001 },
3034                 { 0x06, 0x4064 },
3035                 { 0x07, 0x2863 },
3036                 { 0x08, 0x059c },
3037                 { 0x09, 0x26b4 },
3038                 { 0x0a, 0x6a19 },
3039                 { 0x0b, 0xdcc8 },
3040                 { 0x10, 0xf06d },
3041                 { 0x14, 0x7f68 },
3042                 { 0x18, 0x7fd9 },
3043                 { 0x1c, 0xf0ff },
3044                 { 0x1d, 0x3d9c },
3045                 { 0x1f, 0x0003 },
3046                 { 0x12, 0xf49f },
3047                 { 0x13, 0x070b },
3048                 { 0x1a, 0x05ad },
3049                 { 0x14, 0x94c0 },
3050
3051                 /*
3052                  * Tx Error Issue
3053                  * Enhance line driver power
3054                  */
3055                 { 0x1f, 0x0002 },
3056                 { 0x06, 0x5561 },
3057                 { 0x1f, 0x0005 },
3058                 { 0x05, 0x8332 },
3059                 { 0x06, 0x5561 },
3060
3061                 /*
3062                  * Can not link to 1Gbps with bad cable
3063                  * Decrease SNR threshold form 21.07dB to 19.04dB
3064                  */
3065                 { 0x1f, 0x0001 },
3066                 { 0x17, 0x0cc0 },
3067
3068                 { 0x1f, 0x0000 },
3069                 { 0x0d, 0xf880 }
3070         };
3071
3072         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
3073
3074         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
3075                 static const struct phy_reg phy_reg_init[] = {
3076                         { 0x1f, 0x0002 },
3077                         { 0x05, 0x669a },
3078                         { 0x1f, 0x0005 },
3079                         { 0x05, 0x8330 },
3080                         { 0x06, 0x669a },
3081
3082                         { 0x1f, 0x0002 }
3083                 };
3084                 int val;
3085
3086                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3087
3088                 val = rtl_readphy(tp, 0x0d);
3089                 if ((val & 0x00ff) != 0x006c) {
3090                         static const u32 set[] = {
3091                                 0x0065, 0x0066, 0x0067, 0x0068,
3092                                 0x0069, 0x006a, 0x006b, 0x006c
3093                         };
3094                         int i;
3095
3096                         rtl_writephy(tp, 0x1f, 0x0002);
3097
3098                         val &= 0xff00;
3099                         for (i = 0; i < ARRAY_SIZE(set); i++)
3100                                 rtl_writephy(tp, 0x0d, val | set[i]);
3101                 }
3102         } else {
3103                 static const struct phy_reg phy_reg_init[] = {
3104                         { 0x1f, 0x0002 },
3105                         { 0x05, 0x2642 },
3106                         { 0x1f, 0x0005 },
3107                         { 0x05, 0x8330 },
3108                         { 0x06, 0x2642 }
3109                 };
3110
3111                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3112         }
3113
3114         /* Fine tune PLL performance */
3115         rtl_writephy(tp, 0x1f, 0x0002);
3116         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3117         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3118
3119         /* Switching regulator Slew rate */
3120         rtl_writephy(tp, 0x1f, 0x0002);
3121         rtl_patchphy(tp, 0x0f, 0x0017);
3122
3123         rtl_writephy(tp, 0x1f, 0x0005);
3124         rtl_writephy(tp, 0x05, 0x001b);
3125
3126         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
3127
3128         rtl_writephy(tp, 0x1f, 0x0000);
3129 }
3130
3131 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
3132 {
3133         static const struct phy_reg phy_reg_init[] = {
3134                 { 0x1f, 0x0002 },
3135                 { 0x10, 0x0008 },
3136                 { 0x0d, 0x006c },
3137
3138                 { 0x1f, 0x0000 },
3139                 { 0x0d, 0xf880 },
3140
3141                 { 0x1f, 0x0001 },
3142                 { 0x17, 0x0cc0 },
3143
3144                 { 0x1f, 0x0001 },
3145                 { 0x0b, 0xa4d8 },
3146                 { 0x09, 0x281c },
3147                 { 0x07, 0x2883 },
3148                 { 0x0a, 0x6b35 },
3149                 { 0x1d, 0x3da4 },
3150                 { 0x1c, 0xeffd },
3151                 { 0x14, 0x7f52 },
3152                 { 0x18, 0x7fc6 },
3153                 { 0x08, 0x0601 },
3154                 { 0x06, 0x4063 },
3155                 { 0x10, 0xf074 },
3156                 { 0x1f, 0x0003 },
3157                 { 0x13, 0x0789 },
3158                 { 0x12, 0xf4bd },
3159                 { 0x1a, 0x04fd },
3160                 { 0x14, 0x84b0 },
3161                 { 0x1f, 0x0000 },
3162                 { 0x00, 0x9200 },
3163
3164                 { 0x1f, 0x0005 },
3165                 { 0x01, 0x0340 },
3166                 { 0x1f, 0x0001 },
3167                 { 0x04, 0x4000 },
3168                 { 0x03, 0x1d21 },
3169                 { 0x02, 0x0c32 },
3170                 { 0x01, 0x0200 },
3171                 { 0x00, 0x5554 },
3172                 { 0x04, 0x4800 },
3173                 { 0x04, 0x4000 },
3174                 { 0x04, 0xf000 },
3175                 { 0x03, 0xdf01 },
3176                 { 0x02, 0xdf20 },
3177                 { 0x01, 0x101a },
3178                 { 0x00, 0xa0ff },
3179                 { 0x04, 0xf800 },
3180                 { 0x04, 0xf000 },
3181                 { 0x1f, 0x0000 },
3182
3183                 { 0x1f, 0x0007 },
3184                 { 0x1e, 0x0023 },
3185                 { 0x16, 0x0000 },
3186                 { 0x1f, 0x0000 }
3187         };
3188
3189         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3190 }
3191
3192 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3193 {
3194         static const struct phy_reg phy_reg_init[] = {
3195                 { 0x1f, 0x0001 },
3196                 { 0x17, 0x0cc0 },
3197
3198                 { 0x1f, 0x0007 },
3199                 { 0x1e, 0x002d },
3200                 { 0x18, 0x0040 },
3201                 { 0x1f, 0x0000 }
3202         };
3203
3204         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3205         rtl_patchphy(tp, 0x0d, 1 << 5);
3206 }
3207
3208 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
3209 {
3210         static const struct phy_reg phy_reg_init[] = {
3211                 /* Enable Delay cap */
3212                 { 0x1f, 0x0005 },
3213                 { 0x05, 0x8b80 },
3214                 { 0x06, 0xc896 },
3215                 { 0x1f, 0x0000 },
3216
3217                 /* Channel estimation fine tune */
3218                 { 0x1f, 0x0001 },
3219                 { 0x0b, 0x6c20 },
3220                 { 0x07, 0x2872 },
3221                 { 0x1c, 0xefff },
3222                 { 0x1f, 0x0003 },
3223                 { 0x14, 0x6420 },
3224                 { 0x1f, 0x0000 },
3225
3226                 /* Update PFM & 10M TX idle timer */
3227                 { 0x1f, 0x0007 },
3228                 { 0x1e, 0x002f },
3229                 { 0x15, 0x1919 },
3230                 { 0x1f, 0x0000 },
3231
3232                 { 0x1f, 0x0007 },
3233                 { 0x1e, 0x00ac },
3234                 { 0x18, 0x0006 },
3235                 { 0x1f, 0x0000 }
3236         };
3237
3238         rtl_apply_firmware(tp);
3239
3240         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3241
3242         /* DCO enable for 10M IDLE Power */
3243         rtl_writephy(tp, 0x1f, 0x0007);
3244         rtl_writephy(tp, 0x1e, 0x0023);
3245         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3246         rtl_writephy(tp, 0x1f, 0x0000);
3247
3248         /* For impedance matching */
3249         rtl_writephy(tp, 0x1f, 0x0002);
3250         rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
3251         rtl_writephy(tp, 0x1f, 0x0000);
3252
3253         /* PHY auto speed down */
3254         rtl_writephy(tp, 0x1f, 0x0007);
3255         rtl_writephy(tp, 0x1e, 0x002d);
3256         rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
3257         rtl_writephy(tp, 0x1f, 0x0000);
3258         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3259
3260         rtl_writephy(tp, 0x1f, 0x0005);
3261         rtl_writephy(tp, 0x05, 0x8b86);
3262         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3263         rtl_writephy(tp, 0x1f, 0x0000);
3264
3265         rtl_writephy(tp, 0x1f, 0x0005);
3266         rtl_writephy(tp, 0x05, 0x8b85);
3267         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3268         rtl_writephy(tp, 0x1f, 0x0007);
3269         rtl_writephy(tp, 0x1e, 0x0020);
3270         rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
3271         rtl_writephy(tp, 0x1f, 0x0006);
3272         rtl_writephy(tp, 0x00, 0x5a00);
3273         rtl_writephy(tp, 0x1f, 0x0000);
3274         rtl_writephy(tp, 0x0d, 0x0007);
3275         rtl_writephy(tp, 0x0e, 0x003c);
3276         rtl_writephy(tp, 0x0d, 0x4007);
3277         rtl_writephy(tp, 0x0e, 0x0000);
3278         rtl_writephy(tp, 0x0d, 0x0000);
3279 }
3280
3281 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3282 {
3283         const u16 w[] = {
3284                 addr[0] | (addr[1] << 8),
3285                 addr[2] | (addr[3] << 8),
3286                 addr[4] | (addr[5] << 8)
3287         };
3288         const struct exgmac_reg e[] = {
3289                 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3290                 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3291                 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3292                 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3293         };
3294
3295         rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3296 }
3297
3298 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3299 {
3300         static const struct phy_reg phy_reg_init[] = {
3301                 /* Enable Delay cap */
3302                 { 0x1f, 0x0004 },
3303                 { 0x1f, 0x0007 },
3304                 { 0x1e, 0x00ac },
3305                 { 0x18, 0x0006 },
3306                 { 0x1f, 0x0002 },
3307                 { 0x1f, 0x0000 },
3308                 { 0x1f, 0x0000 },
3309
3310                 /* Channel estimation fine tune */
3311                 { 0x1f, 0x0003 },
3312                 { 0x09, 0xa20f },
3313                 { 0x1f, 0x0000 },
3314                 { 0x1f, 0x0000 },
3315
3316                 /* Green Setting */
3317                 { 0x1f, 0x0005 },
3318                 { 0x05, 0x8b5b },
3319                 { 0x06, 0x9222 },
3320                 { 0x05, 0x8b6d },
3321                 { 0x06, 0x8000 },
3322                 { 0x05, 0x8b76 },
3323                 { 0x06, 0x8000 },
3324                 { 0x1f, 0x0000 }
3325         };
3326
3327         rtl_apply_firmware(tp);
3328
3329         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3330
3331         /* For 4-corner performance improve */
3332         rtl_writephy(tp, 0x1f, 0x0005);
3333         rtl_writephy(tp, 0x05, 0x8b80);
3334         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3335         rtl_writephy(tp, 0x1f, 0x0000);
3336
3337         /* PHY auto speed down */
3338         rtl_writephy(tp, 0x1f, 0x0004);
3339         rtl_writephy(tp, 0x1f, 0x0007);
3340         rtl_writephy(tp, 0x1e, 0x002d);
3341         rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3342         rtl_writephy(tp, 0x1f, 0x0002);
3343         rtl_writephy(tp, 0x1f, 0x0000);
3344         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3345
3346         /* improve 10M EEE waveform */
3347         rtl_writephy(tp, 0x1f, 0x0005);
3348         rtl_writephy(tp, 0x05, 0x8b86);
3349         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3350         rtl_writephy(tp, 0x1f, 0x0000);
3351
3352         /* Improve 2-pair detection performance */
3353         rtl_writephy(tp, 0x1f, 0x0005);
3354         rtl_writephy(tp, 0x05, 0x8b85);
3355         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3356         rtl_writephy(tp, 0x1f, 0x0000);
3357
3358         rtl8168f_config_eee_phy(tp);
3359         rtl_enable_eee(tp);
3360
3361         /* Green feature */
3362         rtl_writephy(tp, 0x1f, 0x0003);
3363         rtl_w0w1_phy(tp, 0x19, 0x0001, 0x0000);
3364         rtl_w0w1_phy(tp, 0x10, 0x0400, 0x0000);
3365         rtl_writephy(tp, 0x1f, 0x0000);
3366         rtl_writephy(tp, 0x1f, 0x0005);
3367         rtl_w0w1_phy(tp, 0x01, 0x0100, 0x0000);
3368         rtl_writephy(tp, 0x1f, 0x0000);
3369
3370         /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3371         rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3372 }
3373
3374 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3375 {
3376         /* For 4-corner performance improve */
3377         rtl_writephy(tp, 0x1f, 0x0005);
3378         rtl_writephy(tp, 0x05, 0x8b80);
3379         rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
3380         rtl_writephy(tp, 0x1f, 0x0000);
3381
3382         /* PHY auto speed down */
3383         rtl_writephy(tp, 0x1f, 0x0007);
3384         rtl_writephy(tp, 0x1e, 0x002d);
3385         rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3386         rtl_writephy(tp, 0x1f, 0x0000);
3387         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3388
3389         /* Improve 10M EEE waveform */
3390         rtl_writephy(tp, 0x1f, 0x0005);
3391         rtl_writephy(tp, 0x05, 0x8b86);
3392         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3393         rtl_writephy(tp, 0x1f, 0x0000);
3394
3395         rtl8168f_config_eee_phy(tp);
3396         rtl_enable_eee(tp);
3397 }
3398
3399 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3400 {
3401         static const struct phy_reg phy_reg_init[] = {
3402                 /* Channel estimation fine tune */
3403                 { 0x1f, 0x0003 },
3404                 { 0x09, 0xa20f },
3405                 { 0x1f, 0x0000 },
3406
3407                 /* Modify green table for giga & fnet */
3408                 { 0x1f, 0x0005 },
3409                 { 0x05, 0x8b55 },
3410                 { 0x06, 0x0000 },
3411                 { 0x05, 0x8b5e },
3412                 { 0x06, 0x0000 },
3413                 { 0x05, 0x8b67 },
3414                 { 0x06, 0x0000 },
3415                 { 0x05, 0x8b70 },
3416                 { 0x06, 0x0000 },
3417                 { 0x1f, 0x0000 },
3418                 { 0x1f, 0x0007 },
3419                 { 0x1e, 0x0078 },
3420                 { 0x17, 0x0000 },
3421                 { 0x19, 0x00fb },
3422                 { 0x1f, 0x0000 },
3423
3424                 /* Modify green table for 10M */
3425                 { 0x1f, 0x0005 },
3426                 { 0x05, 0x8b79 },
3427                 { 0x06, 0xaa00 },
3428                 { 0x1f, 0x0000 },
3429
3430                 /* Disable hiimpedance detection (RTCT) */
3431                 { 0x1f, 0x0003 },
3432                 { 0x01, 0x328a },
3433                 { 0x1f, 0x0000 }
3434         };
3435
3436         rtl_apply_firmware(tp);
3437
3438         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3439
3440         rtl8168f_hw_phy_config(tp);
3441
3442         /* Improve 2-pair detection performance */
3443         rtl_writephy(tp, 0x1f, 0x0005);
3444         rtl_writephy(tp, 0x05, 0x8b85);
3445         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3446         rtl_writephy(tp, 0x1f, 0x0000);
3447 }
3448
3449 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3450 {
3451         rtl_apply_firmware(tp);
3452
3453         rtl8168f_hw_phy_config(tp);
3454 }
3455
3456 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3457 {
3458         static const struct phy_reg phy_reg_init[] = {
3459                 /* Channel estimation fine tune */
3460                 { 0x1f, 0x0003 },
3461                 { 0x09, 0xa20f },
3462                 { 0x1f, 0x0000 },
3463
3464                 /* Modify green table for giga & fnet */
3465                 { 0x1f, 0x0005 },
3466                 { 0x05, 0x8b55 },
3467                 { 0x06, 0x0000 },
3468                 { 0x05, 0x8b5e },
3469                 { 0x06, 0x0000 },
3470                 { 0x05, 0x8b67 },
3471                 { 0x06, 0x0000 },
3472                 { 0x05, 0x8b70 },
3473                 { 0x06, 0x0000 },
3474                 { 0x1f, 0x0000 },
3475                 { 0x1f, 0x0007 },
3476                 { 0x1e, 0x0078 },
3477                 { 0x17, 0x0000 },
3478                 { 0x19, 0x00aa },
3479                 { 0x1f, 0x0000 },
3480
3481                 /* Modify green table for 10M */
3482                 { 0x1f, 0x0005 },
3483                 { 0x05, 0x8b79 },
3484                 { 0x06, 0xaa00 },
3485                 { 0x1f, 0x0000 },
3486
3487                 /* Disable hiimpedance detection (RTCT) */
3488                 { 0x1f, 0x0003 },
3489                 { 0x01, 0x328a },
3490                 { 0x1f, 0x0000 }
3491         };
3492
3493
3494         rtl_apply_firmware(tp);
3495
3496         rtl8168f_hw_phy_config(tp);
3497
3498         /* Improve 2-pair detection performance */
3499         rtl_writephy(tp, 0x1f, 0x0005);
3500         rtl_writephy(tp, 0x05, 0x8b85);
3501         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3502         rtl_writephy(tp, 0x1f, 0x0000);
3503
3504         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3505
3506         /* Modify green table for giga */
3507         rtl_writephy(tp, 0x1f, 0x0005);
3508         rtl_writephy(tp, 0x05, 0x8b54);
3509         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3510         rtl_writephy(tp, 0x05, 0x8b5d);
3511         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3512         rtl_writephy(tp, 0x05, 0x8a7c);
3513         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3514         rtl_writephy(tp, 0x05, 0x8a7f);
3515         rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
3516         rtl_writephy(tp, 0x05, 0x8a82);
3517         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3518         rtl_writephy(tp, 0x05, 0x8a85);
3519         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3520         rtl_writephy(tp, 0x05, 0x8a88);
3521         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3522         rtl_writephy(tp, 0x1f, 0x0000);
3523
3524         /* uc same-seed solution */
3525         rtl_writephy(tp, 0x1f, 0x0005);
3526         rtl_writephy(tp, 0x05, 0x8b85);
3527         rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
3528         rtl_writephy(tp, 0x1f, 0x0000);
3529
3530         /* Green feature */
3531         rtl_writephy(tp, 0x1f, 0x0003);
3532         rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3533         rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3534         rtl_writephy(tp, 0x1f, 0x0000);
3535 }
3536
3537 static void rtl8168g_disable_aldps(struct rtl8169_private *tp)
3538 {
3539         phy_write(tp->phydev, 0x1f, 0x0a43);
3540         phy_clear_bits(tp->phydev, 0x10, BIT(2));
3541 }
3542
3543 static void rtl8168g_phy_adjust_10m_aldps(struct rtl8169_private *tp)
3544 {
3545         struct phy_device *phydev = tp->phydev;
3546
3547         phy_write(phydev, 0x1f, 0x0bcc);
3548         phy_clear_bits(phydev, 0x14, BIT(8));
3549
3550         phy_write(phydev, 0x1f, 0x0a44);
3551         phy_set_bits(phydev, 0x11, BIT(7) | BIT(6));
3552
3553         phy_write(phydev, 0x1f, 0x0a43);
3554         phy_write(phydev, 0x13, 0x8084);
3555         phy_clear_bits(phydev, 0x14, BIT(14) | BIT(13));
3556         phy_set_bits(phydev, 0x10, BIT(12) | BIT(1) | BIT(0));
3557
3558         phy_write(phydev, 0x1f, 0x0000);
3559 }
3560
3561 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3562 {
3563         rtl_apply_firmware(tp);
3564
3565         rtl_writephy(tp, 0x1f, 0x0a46);
3566         if (rtl_readphy(tp, 0x10) & 0x0100) {
3567                 rtl_writephy(tp, 0x1f, 0x0bcc);
3568                 rtl_w0w1_phy(tp, 0x12, 0x0000, 0x8000);
3569         } else {
3570                 rtl_writephy(tp, 0x1f, 0x0bcc);
3571                 rtl_w0w1_phy(tp, 0x12, 0x8000, 0x0000);
3572         }
3573
3574         rtl_writephy(tp, 0x1f, 0x0a46);
3575         if (rtl_readphy(tp, 0x13) & 0x0100) {
3576                 rtl_writephy(tp, 0x1f, 0x0c41);
3577                 rtl_w0w1_phy(tp, 0x15, 0x0002, 0x0000);
3578         } else {
3579                 rtl_writephy(tp, 0x1f, 0x0c41);
3580                 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0002);
3581         }
3582
3583         /* Enable PHY auto speed down */
3584         rtl_writephy(tp, 0x1f, 0x0a44);
3585         rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3586
3587         rtl8168g_phy_adjust_10m_aldps(tp);
3588
3589         /* EEE auto-fallback function */
3590         rtl_writephy(tp, 0x1f, 0x0a4b);
3591         rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3592
3593         /* Enable UC LPF tune function */
3594         rtl_writephy(tp, 0x1f, 0x0a43);
3595         rtl_writephy(tp, 0x13, 0x8012);
3596         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3597
3598         rtl_writephy(tp, 0x1f, 0x0c42);
3599         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3600
3601         /* Improve SWR Efficiency */
3602         rtl_writephy(tp, 0x1f, 0x0bcd);
3603         rtl_writephy(tp, 0x14, 0x5065);
3604         rtl_writephy(tp, 0x14, 0xd065);
3605         rtl_writephy(tp, 0x1f, 0x0bc8);
3606         rtl_writephy(tp, 0x11, 0x5655);
3607         rtl_writephy(tp, 0x1f, 0x0bcd);
3608         rtl_writephy(tp, 0x14, 0x1065);
3609         rtl_writephy(tp, 0x14, 0x9065);
3610         rtl_writephy(tp, 0x14, 0x1065);
3611
3612         rtl8168g_disable_aldps(tp);
3613         rtl8168g_config_eee_phy(tp);
3614         rtl_enable_eee(tp);
3615 }
3616
3617 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3618 {
3619         rtl_apply_firmware(tp);
3620         rtl8168g_config_eee_phy(tp);
3621         rtl_enable_eee(tp);
3622 }
3623
3624 static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3625 {
3626         u16 dout_tapbin;
3627         u32 data;
3628
3629         rtl_apply_firmware(tp);
3630
3631         /* CHN EST parameters adjust - giga master */
3632         rtl_writephy(tp, 0x1f, 0x0a43);
3633         rtl_writephy(tp, 0x13, 0x809b);
3634         rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
3635         rtl_writephy(tp, 0x13, 0x80a2);
3636         rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
3637         rtl_writephy(tp, 0x13, 0x80a4);
3638         rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
3639         rtl_writephy(tp, 0x13, 0x809c);
3640         rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
3641         rtl_writephy(tp, 0x1f, 0x0000);
3642
3643         /* CHN EST parameters adjust - giga slave */
3644         rtl_writephy(tp, 0x1f, 0x0a43);
3645         rtl_writephy(tp, 0x13, 0x80ad);
3646         rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
3647         rtl_writephy(tp, 0x13, 0x80b4);
3648         rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
3649         rtl_writephy(tp, 0x13, 0x80ac);
3650         rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
3651         rtl_writephy(tp, 0x1f, 0x0000);
3652
3653         /* CHN EST parameters adjust - fnet */
3654         rtl_writephy(tp, 0x1f, 0x0a43);
3655         rtl_writephy(tp, 0x13, 0x808e);
3656         rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
3657         rtl_writephy(tp, 0x13, 0x8090);
3658         rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
3659         rtl_writephy(tp, 0x13, 0x8092);
3660         rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
3661         rtl_writephy(tp, 0x1f, 0x0000);
3662
3663         /* enable R-tune & PGA-retune function */
3664         dout_tapbin = 0;
3665         rtl_writephy(tp, 0x1f, 0x0a46);
3666         data = rtl_readphy(tp, 0x13);
3667         data &= 3;
3668         data <<= 2;
3669         dout_tapbin |= data;
3670         data = rtl_readphy(tp, 0x12);
3671         data &= 0xc000;
3672         data >>= 14;
3673         dout_tapbin |= data;
3674         dout_tapbin = ~(dout_tapbin^0x08);
3675         dout_tapbin <<= 12;
3676         dout_tapbin &= 0xf000;
3677         rtl_writephy(tp, 0x1f, 0x0a43);
3678         rtl_writephy(tp, 0x13, 0x827a);
3679         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3680         rtl_writephy(tp, 0x13, 0x827b);
3681         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3682         rtl_writephy(tp, 0x13, 0x827c);
3683         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3684         rtl_writephy(tp, 0x13, 0x827d);
3685         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3686
3687         rtl_writephy(tp, 0x1f, 0x0a43);
3688         rtl_writephy(tp, 0x13, 0x0811);
3689         rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3690         rtl_writephy(tp, 0x1f, 0x0a42);
3691         rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3692         rtl_writephy(tp, 0x1f, 0x0000);
3693
3694         /* enable GPHY 10M */
3695         rtl_writephy(tp, 0x1f, 0x0a44);
3696         rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3697         rtl_writephy(tp, 0x1f, 0x0000);
3698
3699         /* SAR ADC performance */
3700         rtl_writephy(tp, 0x1f, 0x0bca);
3701         rtl_w0w1_phy(tp, 0x17, 0x4000, 0x3000);
3702         rtl_writephy(tp, 0x1f, 0x0000);
3703
3704         rtl_writephy(tp, 0x1f, 0x0a43);
3705         rtl_writephy(tp, 0x13, 0x803f);
3706         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3707         rtl_writephy(tp, 0x13, 0x8047);
3708         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3709         rtl_writephy(tp, 0x13, 0x804f);
3710         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3711         rtl_writephy(tp, 0x13, 0x8057);
3712         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3713         rtl_writephy(tp, 0x13, 0x805f);
3714         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3715         rtl_writephy(tp, 0x13, 0x8067);
3716         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3717         rtl_writephy(tp, 0x13, 0x806f);
3718         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3719         rtl_writephy(tp, 0x1f, 0x0000);
3720
3721         /* disable phy pfm mode */
3722         rtl_writephy(tp, 0x1f, 0x0a44);
3723         rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
3724         rtl_writephy(tp, 0x1f, 0x0000);
3725
3726         rtl8168g_disable_aldps(tp);
3727         rtl8168g_config_eee_phy(tp);
3728         rtl_enable_eee(tp);
3729 }
3730
3731 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3732 {
3733         u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3734         u16 rlen;
3735         u32 data;
3736
3737         rtl_apply_firmware(tp);
3738
3739         /* CHIN EST parameter update */
3740         rtl_writephy(tp, 0x1f, 0x0a43);
3741         rtl_writephy(tp, 0x13, 0x808a);
3742         rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
3743         rtl_writephy(tp, 0x1f, 0x0000);
3744
3745         /* enable R-tune & PGA-retune function */
3746         rtl_writephy(tp, 0x1f, 0x0a43);
3747         rtl_writephy(tp, 0x13, 0x0811);
3748         rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3749         rtl_writephy(tp, 0x1f, 0x0a42);
3750         rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3751         rtl_writephy(tp, 0x1f, 0x0000);
3752
3753         /* enable GPHY 10M */
3754         rtl_writephy(tp, 0x1f, 0x0a44);
3755         rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3756         rtl_writephy(tp, 0x1f, 0x0000);
3757
3758         r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3759         data = r8168_mac_ocp_read(tp, 0xdd02);
3760         ioffset_p3 = ((data & 0x80)>>7);
3761         ioffset_p3 <<= 3;
3762
3763         data = r8168_mac_ocp_read(tp, 0xdd00);
3764         ioffset_p3 |= ((data & (0xe000))>>13);
3765         ioffset_p2 = ((data & (0x1e00))>>9);
3766         ioffset_p1 = ((data & (0x01e0))>>5);
3767         ioffset_p0 = ((data & 0x0010)>>4);
3768         ioffset_p0 <<= 3;
3769         ioffset_p0 |= (data & (0x07));
3770         data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3771
3772         if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
3773             (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) {
3774                 rtl_writephy(tp, 0x1f, 0x0bcf);
3775                 rtl_writephy(tp, 0x16, data);
3776                 rtl_writephy(tp, 0x1f, 0x0000);
3777         }
3778
3779         /* Modify rlen (TX LPF corner frequency) level */
3780         rtl_writephy(tp, 0x1f, 0x0bcd);
3781         data = rtl_readphy(tp, 0x16);
3782         data &= 0x000f;
3783         rlen = 0;
3784         if (data > 3)
3785                 rlen = data - 3;
3786         data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
3787         rtl_writephy(tp, 0x17, data);
3788         rtl_writephy(tp, 0x1f, 0x0bcd);
3789         rtl_writephy(tp, 0x1f, 0x0000);
3790
3791         /* disable phy pfm mode */
3792         rtl_writephy(tp, 0x1f, 0x0a44);
3793         rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
3794         rtl_writephy(tp, 0x1f, 0x0000);
3795
3796         rtl8168g_disable_aldps(tp);
3797         rtl8168g_config_eee_phy(tp);
3798         rtl_enable_eee(tp);
3799 }
3800
3801 static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
3802 {
3803         /* Enable PHY auto speed down */
3804         rtl_writephy(tp, 0x1f, 0x0a44);
3805         rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3806         rtl_writephy(tp, 0x1f, 0x0000);
3807
3808         rtl8168g_phy_adjust_10m_aldps(tp);
3809
3810         /* Enable EEE auto-fallback function */
3811         rtl_writephy(tp, 0x1f, 0x0a4b);
3812         rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3813         rtl_writephy(tp, 0x1f, 0x0000);
3814
3815         /* Enable UC LPF tune function */
3816         rtl_writephy(tp, 0x1f, 0x0a43);
3817         rtl_writephy(tp, 0x13, 0x8012);
3818         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3819         rtl_writephy(tp, 0x1f, 0x0000);
3820
3821         /* set rg_sel_sdm_rate */
3822         rtl_writephy(tp, 0x1f, 0x0c42);
3823         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3824         rtl_writephy(tp, 0x1f, 0x0000);
3825
3826         rtl8168g_disable_aldps(tp);
3827         rtl8168g_config_eee_phy(tp);
3828         rtl_enable_eee(tp);
3829 }
3830
3831 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
3832 {
3833         rtl8168g_phy_adjust_10m_aldps(tp);
3834
3835         /* Enable UC LPF tune function */
3836         rtl_writephy(tp, 0x1f, 0x0a43);
3837         rtl_writephy(tp, 0x13, 0x8012);
3838         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3839         rtl_writephy(tp, 0x1f, 0x0000);
3840
3841         /* Set rg_sel_sdm_rate */
3842         rtl_writephy(tp, 0x1f, 0x0c42);
3843         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3844         rtl_writephy(tp, 0x1f, 0x0000);
3845
3846         /* Channel estimation parameters */
3847         rtl_writephy(tp, 0x1f, 0x0a43);
3848         rtl_writephy(tp, 0x13, 0x80f3);
3849         rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
3850         rtl_writephy(tp, 0x13, 0x80f0);
3851         rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
3852         rtl_writephy(tp, 0x13, 0x80ef);
3853         rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
3854         rtl_writephy(tp, 0x13, 0x80f6);
3855         rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
3856         rtl_writephy(tp, 0x13, 0x80ec);
3857         rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
3858         rtl_writephy(tp, 0x13, 0x80ed);
3859         rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3860         rtl_writephy(tp, 0x13, 0x80f2);
3861         rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
3862         rtl_writephy(tp, 0x13, 0x80f4);
3863         rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
3864         rtl_writephy(tp, 0x1f, 0x0a43);
3865         rtl_writephy(tp, 0x13, 0x8110);
3866         rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
3867         rtl_writephy(tp, 0x13, 0x810f);
3868         rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
3869         rtl_writephy(tp, 0x13, 0x8111);
3870         rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
3871         rtl_writephy(tp, 0x13, 0x8113);
3872         rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
3873         rtl_writephy(tp, 0x13, 0x8115);
3874         rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
3875         rtl_writephy(tp, 0x13, 0x810e);
3876         rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
3877         rtl_writephy(tp, 0x13, 0x810c);
3878         rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3879         rtl_writephy(tp, 0x13, 0x810b);
3880         rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
3881         rtl_writephy(tp, 0x1f, 0x0a43);
3882         rtl_writephy(tp, 0x13, 0x80d1);
3883         rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
3884         rtl_writephy(tp, 0x13, 0x80cd);
3885         rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
3886         rtl_writephy(tp, 0x13, 0x80d3);
3887         rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
3888         rtl_writephy(tp, 0x13, 0x80d5);
3889         rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
3890         rtl_writephy(tp, 0x13, 0x80d7);
3891         rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
3892
3893         /* Force PWM-mode */
3894         rtl_writephy(tp, 0x1f, 0x0bcd);
3895         rtl_writephy(tp, 0x14, 0x5065);
3896         rtl_writephy(tp, 0x14, 0xd065);
3897         rtl_writephy(tp, 0x1f, 0x0bc8);
3898         rtl_writephy(tp, 0x12, 0x00ed);
3899         rtl_writephy(tp, 0x1f, 0x0bcd);
3900         rtl_writephy(tp, 0x14, 0x1065);
3901         rtl_writephy(tp, 0x14, 0x9065);
3902         rtl_writephy(tp, 0x14, 0x1065);
3903         rtl_writephy(tp, 0x1f, 0x0000);
3904
3905         rtl8168g_disable_aldps(tp);
3906         rtl8168g_config_eee_phy(tp);
3907         rtl_enable_eee(tp);
3908 }
3909
3910 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3911 {
3912         static const struct phy_reg phy_reg_init[] = {
3913                 { 0x1f, 0x0003 },
3914                 { 0x08, 0x441d },
3915                 { 0x01, 0x9100 },
3916                 { 0x1f, 0x0000 }
3917         };
3918
3919         rtl_writephy(tp, 0x1f, 0x0000);
3920         rtl_patchphy(tp, 0x11, 1 << 12);
3921         rtl_patchphy(tp, 0x19, 1 << 13);
3922         rtl_patchphy(tp, 0x10, 1 << 15);
3923
3924         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3925 }
3926
3927 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3928 {
3929         static const struct phy_reg phy_reg_init[] = {
3930                 { 0x1f, 0x0005 },
3931                 { 0x1a, 0x0000 },
3932                 { 0x1f, 0x0000 },
3933
3934                 { 0x1f, 0x0004 },
3935                 { 0x1c, 0x0000 },
3936                 { 0x1f, 0x0000 },
3937
3938                 { 0x1f, 0x0001 },
3939                 { 0x15, 0x7701 },
3940                 { 0x1f, 0x0000 }
3941         };
3942
3943         /* Disable ALDPS before ram code */
3944         rtl_writephy(tp, 0x1f, 0x0000);
3945         rtl_writephy(tp, 0x18, 0x0310);
3946         msleep(100);
3947
3948         rtl_apply_firmware(tp);
3949
3950         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3951 }
3952
3953 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3954 {
3955         /* Disable ALDPS before setting firmware */
3956         rtl_writephy(tp, 0x1f, 0x0000);
3957         rtl_writephy(tp, 0x18, 0x0310);
3958         msleep(20);
3959
3960         rtl_apply_firmware(tp);
3961
3962         /* EEE setting */
3963         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3964         rtl_writephy(tp, 0x1f, 0x0004);
3965         rtl_writephy(tp, 0x10, 0x401f);
3966         rtl_writephy(tp, 0x19, 0x7030);
3967         rtl_writephy(tp, 0x1f, 0x0000);
3968 }
3969
3970 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3971 {
3972         static const struct phy_reg phy_reg_init[] = {
3973                 { 0x1f, 0x0004 },
3974                 { 0x10, 0xc07f },
3975                 { 0x19, 0x7030 },
3976                 { 0x1f, 0x0000 }
3977         };
3978
3979         /* Disable ALDPS before ram code */
3980         rtl_writephy(tp, 0x1f, 0x0000);
3981         rtl_writephy(tp, 0x18, 0x0310);
3982         msleep(100);
3983
3984         rtl_apply_firmware(tp);
3985
3986         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3987         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3988
3989         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3990 }
3991
3992 static void rtl_hw_phy_config(struct net_device *dev)
3993 {
3994         struct rtl8169_private *tp = netdev_priv(dev);
3995
3996         switch (tp->mac_version) {
3997         case RTL_GIGA_MAC_VER_01:
3998                 break;
3999         case RTL_GIGA_MAC_VER_02:
4000         case RTL_GIGA_MAC_VER_03:
4001                 rtl8169s_hw_phy_config(tp);
4002                 break;
4003         case RTL_GIGA_MAC_VER_04:
4004                 rtl8169sb_hw_phy_config(tp);
4005                 break;
4006         case RTL_GIGA_MAC_VER_05:
4007                 rtl8169scd_hw_phy_config(tp);
4008                 break;
4009         case RTL_GIGA_MAC_VER_06:
4010                 rtl8169sce_hw_phy_config(tp);
4011                 break;
4012         case RTL_GIGA_MAC_VER_07:
4013         case RTL_GIGA_MAC_VER_08:
4014         case RTL_GIGA_MAC_VER_09:
4015                 rtl8102e_hw_phy_config(tp);
4016                 break;
4017         case RTL_GIGA_MAC_VER_11:
4018                 rtl8168bb_hw_phy_config(tp);
4019                 break;
4020         case RTL_GIGA_MAC_VER_12:
4021                 rtl8168bef_hw_phy_config(tp);
4022                 break;
4023         case RTL_GIGA_MAC_VER_17:
4024                 rtl8168bef_hw_phy_config(tp);
4025                 break;
4026         case RTL_GIGA_MAC_VER_18:
4027                 rtl8168cp_1_hw_phy_config(tp);
4028                 break;
4029         case RTL_GIGA_MAC_VER_19:
4030                 rtl8168c_1_hw_phy_config(tp);
4031                 break;
4032         case RTL_GIGA_MAC_VER_20:
4033                 rtl8168c_2_hw_phy_config(tp);
4034                 break;
4035         case RTL_GIGA_MAC_VER_21:
4036                 rtl8168c_3_hw_phy_config(tp);
4037                 break;
4038         case RTL_GIGA_MAC_VER_22:
4039                 rtl8168c_4_hw_phy_config(tp);
4040                 break;
4041         case RTL_GIGA_MAC_VER_23:
4042         case RTL_GIGA_MAC_VER_24:
4043                 rtl8168cp_2_hw_phy_config(tp);
4044                 break;
4045         case RTL_GIGA_MAC_VER_25:
4046                 rtl8168d_1_hw_phy_config(tp);
4047                 break;
4048         case RTL_GIGA_MAC_VER_26:
4049                 rtl8168d_2_hw_phy_config(tp);
4050                 break;
4051         case RTL_GIGA_MAC_VER_27:
4052                 rtl8168d_3_hw_phy_config(tp);
4053                 break;
4054         case RTL_GIGA_MAC_VER_28:
4055                 rtl8168d_4_hw_phy_config(tp);
4056                 break;
4057         case RTL_GIGA_MAC_VER_29:
4058         case RTL_GIGA_MAC_VER_30:
4059                 rtl8105e_hw_phy_config(tp);
4060                 break;
4061         case RTL_GIGA_MAC_VER_31:
4062                 /* None. */
4063                 break;
4064         case RTL_GIGA_MAC_VER_32:
4065         case RTL_GIGA_MAC_VER_33:
4066                 rtl8168e_1_hw_phy_config(tp);
4067                 break;
4068         case RTL_GIGA_MAC_VER_34:
4069                 rtl8168e_2_hw_phy_config(tp);
4070                 break;
4071         case RTL_GIGA_MAC_VER_35:
4072                 rtl8168f_1_hw_phy_config(tp);
4073                 break;
4074         case RTL_GIGA_MAC_VER_36:
4075                 rtl8168f_2_hw_phy_config(tp);
4076                 break;
4077
4078         case RTL_GIGA_MAC_VER_37:
4079                 rtl8402_hw_phy_config(tp);
4080                 break;
4081
4082         case RTL_GIGA_MAC_VER_38:
4083                 rtl8411_hw_phy_config(tp);
4084                 break;
4085
4086         case RTL_GIGA_MAC_VER_39:
4087                 rtl8106e_hw_phy_config(tp);
4088                 break;
4089
4090         case RTL_GIGA_MAC_VER_40:
4091                 rtl8168g_1_hw_phy_config(tp);
4092                 break;
4093         case RTL_GIGA_MAC_VER_42:
4094         case RTL_GIGA_MAC_VER_43:
4095         case RTL_GIGA_MAC_VER_44:
4096                 rtl8168g_2_hw_phy_config(tp);
4097                 break;
4098         case RTL_GIGA_MAC_VER_45:
4099         case RTL_GIGA_MAC_VER_47:
4100                 rtl8168h_1_hw_phy_config(tp);
4101                 break;
4102         case RTL_GIGA_MAC_VER_46:
4103         case RTL_GIGA_MAC_VER_48:
4104                 rtl8168h_2_hw_phy_config(tp);
4105                 break;
4106
4107         case RTL_GIGA_MAC_VER_49:
4108                 rtl8168ep_1_hw_phy_config(tp);
4109                 break;
4110         case RTL_GIGA_MAC_VER_50:
4111         case RTL_GIGA_MAC_VER_51:
4112                 rtl8168ep_2_hw_phy_config(tp);
4113                 break;
4114
4115         case RTL_GIGA_MAC_VER_41:
4116         default:
4117                 break;
4118         }
4119 }
4120
4121 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
4122 {
4123         if (!test_and_set_bit(flag, tp->wk.flags))
4124                 schedule_work(&tp->wk.work);
4125 }
4126
4127 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
4128 {
4129         return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
4130                (RTL_R8(tp, PHYstatus) & TBI_Enable);
4131 }
4132
4133 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
4134 {
4135         rtl_hw_phy_config(dev);
4136
4137         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
4138                 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
4139                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4140                 netif_dbg(tp, drv, dev,
4141                           "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4142                 RTL_W8(tp, 0x82, 0x01);
4143         }
4144
4145         /* We may have called phy_speed_down before */
4146         phy_speed_up(tp->phydev);
4147
4148         genphy_soft_reset(tp->phydev);
4149
4150         /* It was reported that several chips end up with 10MBit/Half on a
4151          * 1GBit link after resuming from S3. For whatever reason the PHY on
4152          * these chips doesn't properly start a renegotiation when soft-reset.
4153          * Explicitly requesting a renegotiation fixes this.
4154          */
4155         if (tp->phydev->autoneg == AUTONEG_ENABLE)
4156                 phy_restart_aneg(tp->phydev);
4157 }
4158
4159 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
4160 {
4161         rtl_lock_work(tp);
4162
4163         rtl_unlock_config_regs(tp);
4164
4165         RTL_W32(tp, MAC4, addr[4] | addr[5] << 8);
4166         RTL_R32(tp, MAC4);
4167
4168         RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
4169         RTL_R32(tp, MAC0);
4170
4171         if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4172                 rtl_rar_exgmac_set(tp, addr);
4173
4174         rtl_lock_config_regs(tp);
4175
4176         rtl_unlock_work(tp);
4177 }
4178
4179 static int rtl_set_mac_address(struct net_device *dev, void *p)
4180 {
4181         struct rtl8169_private *tp = netdev_priv(dev);
4182         struct device *d = tp_to_dev(tp);
4183         int ret;
4184
4185         ret = eth_mac_addr(dev, p);
4186         if (ret)
4187                 return ret;
4188
4189         pm_runtime_get_noresume(d);
4190
4191         if (pm_runtime_active(d))
4192                 rtl_rar_set(tp, dev->dev_addr);
4193
4194         pm_runtime_put_noidle(d);
4195
4196         return 0;
4197 }
4198
4199 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4200 {
4201         struct rtl8169_private *tp = netdev_priv(dev);
4202
4203         if (!netif_running(dev))
4204                 return -ENODEV;
4205
4206         return phy_mii_ioctl(tp->phydev, ifr, cmd);
4207 }
4208
4209 static void rtl_init_mdio_ops(struct rtl8169_private *tp)
4210 {
4211         struct mdio_ops *ops = &tp->mdio_ops;
4212
4213         switch (tp->mac_version) {
4214         case RTL_GIGA_MAC_VER_27:
4215                 ops->write      = r8168dp_1_mdio_write;
4216                 ops->read       = r8168dp_1_mdio_read;
4217                 break;
4218         case RTL_GIGA_MAC_VER_28:
4219         case RTL_GIGA_MAC_VER_31:
4220                 ops->write      = r8168dp_2_mdio_write;
4221                 ops->read       = r8168dp_2_mdio_read;
4222                 break;
4223         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4224                 ops->write      = r8168g_mdio_write;
4225                 ops->read       = r8168g_mdio_read;
4226                 break;
4227         default:
4228                 ops->write      = r8169_mdio_write;
4229                 ops->read       = r8169_mdio_read;
4230                 break;
4231         }
4232 }
4233
4234 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
4235 {
4236         switch (tp->mac_version) {
4237         case RTL_GIGA_MAC_VER_25:
4238         case RTL_GIGA_MAC_VER_26:
4239         case RTL_GIGA_MAC_VER_29:
4240         case RTL_GIGA_MAC_VER_30:
4241         case RTL_GIGA_MAC_VER_32:
4242         case RTL_GIGA_MAC_VER_33:
4243         case RTL_GIGA_MAC_VER_34:
4244         case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_51:
4245                 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
4246                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
4247                 break;
4248         default:
4249                 break;
4250         }
4251 }
4252
4253 static void r8168_pll_power_down(struct rtl8169_private *tp)
4254 {
4255         if (r8168_check_dash(tp))
4256                 return;
4257
4258         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4259             tp->mac_version == RTL_GIGA_MAC_VER_33)
4260                 rtl_ephy_write(tp, 0x19, 0xff64);
4261
4262         if (device_may_wakeup(tp_to_dev(tp))) {
4263                 phy_speed_down(tp->phydev, false);
4264                 rtl_wol_suspend_quirk(tp);
4265                 return;
4266         }
4267
4268         switch (tp->mac_version) {
4269         case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
4270         case RTL_GIGA_MAC_VER_37:
4271         case RTL_GIGA_MAC_VER_39:
4272         case RTL_GIGA_MAC_VER_43:
4273         case RTL_GIGA_MAC_VER_44:
4274         case RTL_GIGA_MAC_VER_45:
4275         case RTL_GIGA_MAC_VER_46:
4276         case RTL_GIGA_MAC_VER_47:
4277         case RTL_GIGA_MAC_VER_48:
4278         case RTL_GIGA_MAC_VER_50:
4279         case RTL_GIGA_MAC_VER_51:
4280                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
4281                 break;
4282         case RTL_GIGA_MAC_VER_40:
4283         case RTL_GIGA_MAC_VER_41:
4284         case RTL_GIGA_MAC_VER_49:
4285                 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
4286                              0xfc000000, ERIAR_EXGMAC);
4287                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
4288                 break;
4289         }
4290 }
4291
4292 static void r8168_pll_power_up(struct rtl8169_private *tp)
4293 {
4294         switch (tp->mac_version) {
4295         case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
4296         case RTL_GIGA_MAC_VER_37:
4297         case RTL_GIGA_MAC_VER_39:
4298         case RTL_GIGA_MAC_VER_43:
4299                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);
4300                 break;
4301         case RTL_GIGA_MAC_VER_44:
4302         case RTL_GIGA_MAC_VER_45:
4303         case RTL_GIGA_MAC_VER_46:
4304         case RTL_GIGA_MAC_VER_47:
4305         case RTL_GIGA_MAC_VER_48:
4306         case RTL_GIGA_MAC_VER_50:
4307         case RTL_GIGA_MAC_VER_51:
4308                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
4309                 break;
4310         case RTL_GIGA_MAC_VER_40:
4311         case RTL_GIGA_MAC_VER_41:
4312         case RTL_GIGA_MAC_VER_49:
4313                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
4314                 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
4315                              0x00000000, ERIAR_EXGMAC);
4316                 break;
4317         }
4318
4319         phy_resume(tp->phydev);
4320         /* give MAC/PHY some time to resume */
4321         msleep(20);
4322 }
4323
4324 static void rtl_pll_power_down(struct rtl8169_private *tp)
4325 {
4326         switch (tp->mac_version) {
4327         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4328         case RTL_GIGA_MAC_VER_13 ... RTL_GIGA_MAC_VER_15:
4329                 break;
4330         default:
4331                 r8168_pll_power_down(tp);
4332         }
4333 }
4334
4335 static void rtl_pll_power_up(struct rtl8169_private *tp)
4336 {
4337         switch (tp->mac_version) {
4338         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4339         case RTL_GIGA_MAC_VER_13 ... RTL_GIGA_MAC_VER_15:
4340                 break;
4341         default:
4342                 r8168_pll_power_up(tp);
4343         }
4344 }
4345
4346 static void rtl_init_rxcfg(struct rtl8169_private *tp)
4347 {
4348         switch (tp->mac_version) {
4349         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4350         case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
4351                 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4352                 break;
4353         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
4354         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
4355         case RTL_GIGA_MAC_VER_38:
4356                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4357                 break;
4358         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4359                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
4360                 break;
4361         default:
4362                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
4363                 break;
4364         }
4365 }
4366
4367 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4368 {
4369         tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
4370 }
4371
4372 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4373 {
4374         if (tp->jumbo_ops.enable) {
4375                 rtl_unlock_config_regs(tp);
4376                 tp->jumbo_ops.enable(tp);
4377                 rtl_lock_config_regs(tp);
4378         }
4379 }
4380
4381 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4382 {
4383         if (tp->jumbo_ops.disable) {
4384                 rtl_unlock_config_regs(tp);
4385                 tp->jumbo_ops.disable(tp);
4386                 rtl_lock_config_regs(tp);
4387         }
4388 }
4389
4390 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4391 {
4392         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4393         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
4394         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
4395 }
4396
4397 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4398 {
4399         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4400         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
4401         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4402 }
4403
4404 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4405 {
4406         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4407 }
4408
4409 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4410 {
4411         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4412 }
4413
4414 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4415 {
4416         RTL_W8(tp, MaxTxPacketSize, 0x3f);
4417         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4418         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
4419         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
4420 }
4421
4422 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4423 {
4424         RTL_W8(tp, MaxTxPacketSize, 0x0c);
4425         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4426         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
4427         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4428 }
4429
4430 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4431 {
4432         rtl_tx_performance_tweak(tp,
4433                 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
4434 }
4435
4436 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4437 {
4438         rtl_tx_performance_tweak(tp,
4439                 PCI_EXP_DEVCTL_READRQ_4096B | PCI_EXP_DEVCTL_NOSNOOP_EN);
4440 }
4441
4442 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4443 {
4444         r8168b_0_hw_jumbo_enable(tp);
4445
4446         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
4447 }
4448
4449 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4450 {
4451         r8168b_0_hw_jumbo_disable(tp);
4452
4453         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4454 }
4455
4456 static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
4457 {
4458         struct jumbo_ops *ops = &tp->jumbo_ops;
4459
4460         switch (tp->mac_version) {
4461         case RTL_GIGA_MAC_VER_11:
4462                 ops->disable    = r8168b_0_hw_jumbo_disable;
4463                 ops->enable     = r8168b_0_hw_jumbo_enable;
4464                 break;
4465         case RTL_GIGA_MAC_VER_12:
4466         case RTL_GIGA_MAC_VER_17:
4467                 ops->disable    = r8168b_1_hw_jumbo_disable;
4468                 ops->enable     = r8168b_1_hw_jumbo_enable;
4469                 break;
4470         case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
4471         case RTL_GIGA_MAC_VER_19:
4472         case RTL_GIGA_MAC_VER_20:
4473         case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
4474         case RTL_GIGA_MAC_VER_22:
4475         case RTL_GIGA_MAC_VER_23:
4476         case RTL_GIGA_MAC_VER_24:
4477         case RTL_GIGA_MAC_VER_25:
4478         case RTL_GIGA_MAC_VER_26:
4479                 ops->disable    = r8168c_hw_jumbo_disable;
4480                 ops->enable     = r8168c_hw_jumbo_enable;
4481                 break;
4482         case RTL_GIGA_MAC_VER_27:
4483         case RTL_GIGA_MAC_VER_28:
4484                 ops->disable    = r8168dp_hw_jumbo_disable;
4485                 ops->enable     = r8168dp_hw_jumbo_enable;
4486                 break;
4487         case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
4488         case RTL_GIGA_MAC_VER_32:
4489         case RTL_GIGA_MAC_VER_33:
4490         case RTL_GIGA_MAC_VER_34:
4491                 ops->disable    = r8168e_hw_jumbo_disable;
4492                 ops->enable     = r8168e_hw_jumbo_enable;
4493                 break;
4494
4495         /*
4496          * No action needed for jumbo frames with 8169.
4497          * No jumbo for 810x at all.
4498          */
4499         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4500         default:
4501                 ops->disable    = NULL;
4502                 ops->enable     = NULL;
4503                 break;
4504         }
4505 }
4506
4507 DECLARE_RTL_COND(rtl_chipcmd_cond)
4508 {
4509         return RTL_R8(tp, ChipCmd) & CmdReset;
4510 }
4511
4512 static void rtl_hw_reset(struct rtl8169_private *tp)
4513 {
4514         RTL_W8(tp, ChipCmd, CmdReset);
4515
4516         rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
4517 }
4518
4519 static void rtl_request_firmware(struct rtl8169_private *tp)
4520 {
4521         struct rtl_fw *rtl_fw;
4522         int rc = -ENOMEM;
4523
4524         /* firmware loaded already or no firmware available */
4525         if (tp->rtl_fw || !tp->fw_name)
4526                 return;
4527
4528         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4529         if (!rtl_fw)
4530                 goto err_warn;
4531
4532         rc = request_firmware(&rtl_fw->fw, tp->fw_name, tp_to_dev(tp));
4533         if (rc < 0)
4534                 goto err_free;
4535
4536         rc = rtl_check_firmware(tp, rtl_fw);
4537         if (rc < 0)
4538                 goto err_release_firmware;
4539
4540         tp->rtl_fw = rtl_fw;
4541
4542         return;
4543
4544 err_release_firmware:
4545         release_firmware(rtl_fw->fw);
4546 err_free:
4547         kfree(rtl_fw);
4548 err_warn:
4549         netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4550                    tp->fw_name, rc);
4551 }
4552
4553 static void rtl_rx_close(struct rtl8169_private *tp)
4554 {
4555         RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
4556 }
4557
4558 DECLARE_RTL_COND(rtl_npq_cond)
4559 {
4560         return RTL_R8(tp, TxPoll) & NPQ;
4561 }
4562
4563 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4564 {
4565         return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
4566 }
4567
4568 static void rtl8169_hw_reset(struct rtl8169_private *tp)
4569 {
4570         /* Disable interrupts */
4571         rtl8169_irq_mask_and_ack(tp);
4572
4573         rtl_rx_close(tp);
4574
4575         switch (tp->mac_version) {
4576         case RTL_GIGA_MAC_VER_27:
4577         case RTL_GIGA_MAC_VER_28:
4578         case RTL_GIGA_MAC_VER_31:
4579                 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
4580                 break;
4581         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
4582         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4583                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4584                 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
4585                 break;
4586         default:
4587                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4588                 udelay(100);
4589                 break;
4590         }
4591
4592         rtl_hw_reset(tp);
4593 }
4594
4595 static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
4596 {
4597         u32 val = TX_DMA_BURST << TxDMAShift |
4598                   InterFrameGap << TxInterFrameGapShift;
4599
4600         if (tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
4601             tp->mac_version != RTL_GIGA_MAC_VER_39)
4602                 val |= TXCFG_AUTO_FIFO;
4603
4604         RTL_W32(tp, TxConfig, val);
4605 }
4606
4607 static void rtl_set_rx_max_size(struct rtl8169_private *tp)
4608 {
4609         /* Low hurts. Let's disable the filtering. */
4610         RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
4611 }
4612
4613 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
4614 {
4615         /*
4616          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4617          * register to be written before TxDescAddrLow to work.
4618          * Switching from MMIO to I/O access fixes the issue as well.
4619          */
4620         RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4621         RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4622         RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4623         RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4624 }
4625
4626 static void rtl8169_set_magic_reg(struct rtl8169_private *tp, unsigned mac_version)
4627 {
4628         u32 val;
4629
4630         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4631                 val = 0x000fff00;
4632         else if (tp->mac_version == RTL_GIGA_MAC_VER_06)
4633                 val = 0x00ffff00;
4634         else
4635                 return;
4636
4637         if (RTL_R8(tp, Config2) & PCI_Clock_66MHz)
4638                 val |= 0xff;
4639
4640         RTL_W32(tp, 0x7c, val);
4641 }
4642
4643 static void rtl_set_rx_mode(struct net_device *dev)
4644 {
4645         struct rtl8169_private *tp = netdev_priv(dev);
4646         u32 mc_filter[2];       /* Multicast hash filter */
4647         int rx_mode;
4648         u32 tmp = 0;
4649
4650         if (dev->flags & IFF_PROMISC) {
4651                 /* Unconditionally log net taps. */
4652                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4653                 rx_mode =
4654                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4655                     AcceptAllPhys;
4656                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4657         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4658                    (dev->flags & IFF_ALLMULTI)) {
4659                 /* Too many to filter perfectly -- accept all multicasts. */
4660                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4661                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4662         } else {
4663                 struct netdev_hw_addr *ha;
4664
4665                 rx_mode = AcceptBroadcast | AcceptMyPhys;
4666                 mc_filter[1] = mc_filter[0] = 0;
4667                 netdev_for_each_mc_addr(ha, dev) {
4668                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4669                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4670                         rx_mode |= AcceptMulticast;
4671                 }
4672         }
4673
4674         if (dev->features & NETIF_F_RXALL)
4675                 rx_mode |= (AcceptErr | AcceptRunt);
4676
4677         tmp = (RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4678
4679         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4680                 u32 data = mc_filter[0];
4681
4682                 mc_filter[0] = swab32(mc_filter[1]);
4683                 mc_filter[1] = swab32(data);
4684         }
4685
4686         if (tp->mac_version == RTL_GIGA_MAC_VER_35)
4687                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4688
4689         RTL_W32(tp, MAR0 + 4, mc_filter[1]);
4690         RTL_W32(tp, MAR0 + 0, mc_filter[0]);
4691
4692         RTL_W32(tp, RxConfig, tmp);
4693 }
4694
4695 static void rtl_hw_start(struct  rtl8169_private *tp)
4696 {
4697         rtl_unlock_config_regs(tp);
4698
4699         tp->hw_start(tp);
4700
4701         rtl_set_rx_max_size(tp);
4702         rtl_set_rx_tx_desc_registers(tp);
4703         rtl_lock_config_regs(tp);
4704
4705         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4706         RTL_R8(tp, IntrMask);
4707         RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
4708         rtl_init_rxcfg(tp);
4709         rtl_set_tx_config_registers(tp);
4710
4711         rtl_set_rx_mode(tp->dev);
4712         /* no early-rx interrupts */
4713         RTL_W16(tp, MultiIntr, RTL_R16(tp, MultiIntr) & 0xf000);
4714         rtl_irq_enable(tp);
4715 }
4716
4717 static void rtl_hw_start_8169(struct rtl8169_private *tp)
4718 {
4719         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4720                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4721
4722         RTL_W8(tp, EarlyTxThres, NoEarlyTx);
4723
4724         tp->cp_cmd |= PCIMulRW;
4725
4726         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4727             tp->mac_version == RTL_GIGA_MAC_VER_03) {
4728                 netif_dbg(tp, drv, tp->dev,
4729                           "Set MAC Reg C+CR Offset 0xe0. Bit 3 and Bit 14 MUST be 1\n");
4730                 tp->cp_cmd |= (1 << 14);
4731         }
4732
4733         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4734
4735         rtl8169_set_magic_reg(tp, tp->mac_version);
4736
4737         /*
4738          * Undocumented corner. Supposedly:
4739          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4740          */
4741         RTL_W16(tp, IntrMitigate, 0x0000);
4742
4743         RTL_W32(tp, RxMissed, 0);
4744 }
4745
4746 DECLARE_RTL_COND(rtl_csiar_cond)
4747 {
4748         return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
4749 }
4750
4751 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
4752 {
4753         u32 func = PCI_FUNC(tp->pci_dev->devfn);
4754
4755         RTL_W32(tp, CSIDR, value);
4756         RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4757                 CSIAR_BYTE_ENABLE | func << 16);
4758
4759         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4760 }
4761
4762 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
4763 {
4764         u32 func = PCI_FUNC(tp->pci_dev->devfn);
4765
4766         RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
4767                 CSIAR_BYTE_ENABLE);
4768
4769         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4770                 RTL_R32(tp, CSIDR) : ~0;
4771 }
4772
4773 static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val)
4774 {
4775         struct pci_dev *pdev = tp->pci_dev;
4776         u32 csi;
4777
4778         /* According to Realtek the value at config space address 0x070f
4779          * controls the L0s/L1 entrance latency. We try standard ECAM access
4780          * first and if it fails fall back to CSI.
4781          */
4782         if (pdev->cfg_size > 0x070f &&
4783             pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
4784                 return;
4785
4786         netdev_notice_once(tp->dev,
4787                 "No native access to PCI extended config space, falling back to CSI\n");
4788         csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4789         rtl_csi_write(tp, 0x070c, csi | val << 24);
4790 }
4791
4792 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
4793 {
4794         rtl_csi_access_enable(tp, 0x27);
4795 }
4796
4797 struct ephy_info {
4798         unsigned int offset;
4799         u16 mask;
4800         u16 bits;
4801 };
4802
4803 static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
4804                           int len)
4805 {
4806         u16 w;
4807
4808         while (len-- > 0) {
4809                 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4810                 rtl_ephy_write(tp, e->offset, w);
4811                 e++;
4812         }
4813 }
4814
4815 static void rtl_disable_clock_request(struct rtl8169_private *tp)
4816 {
4817         pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
4818                                    PCI_EXP_LNKCTL_CLKREQ_EN);
4819 }
4820
4821 static void rtl_enable_clock_request(struct rtl8169_private *tp)
4822 {
4823         pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
4824                                  PCI_EXP_LNKCTL_CLKREQ_EN);
4825 }
4826
4827 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp)
4828 {
4829         /* work around an issue when PCI reset occurs during L2/L3 state */
4830         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23);
4831 }
4832
4833 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
4834 {
4835         if (enable) {
4836                 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);
4837                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);
4838         } else {
4839                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
4840                 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
4841         }
4842
4843         udelay(10);
4844 }
4845
4846 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
4847 {
4848         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4849
4850         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4851         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4852
4853         if (tp->dev->mtu <= ETH_DATA_LEN) {
4854                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B |
4855                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
4856         }
4857 }
4858
4859 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
4860 {
4861         rtl_hw_start_8168bb(tp);
4862
4863         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4864
4865         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4866 }
4867
4868 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
4869 {
4870         RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
4871
4872         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4873
4874         if (tp->dev->mtu <= ETH_DATA_LEN)
4875                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4876
4877         rtl_disable_clock_request(tp);
4878
4879         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4880         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4881 }
4882
4883 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
4884 {
4885         static const struct ephy_info e_info_8168cp[] = {
4886                 { 0x01, 0,      0x0001 },
4887                 { 0x02, 0x0800, 0x1000 },
4888                 { 0x03, 0,      0x0042 },
4889                 { 0x06, 0x0080, 0x0000 },
4890                 { 0x07, 0,      0x2000 }
4891         };
4892
4893         rtl_set_def_aspm_entry_latency(tp);
4894
4895         rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4896
4897         __rtl_hw_start_8168cp(tp);
4898 }
4899
4900 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
4901 {
4902         rtl_set_def_aspm_entry_latency(tp);
4903
4904         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4905
4906         if (tp->dev->mtu <= ETH_DATA_LEN)
4907                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4908
4909         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4910         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4911 }
4912
4913 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
4914 {
4915         rtl_set_def_aspm_entry_latency(tp);
4916
4917         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4918
4919         /* Magic. */
4920         RTL_W8(tp, DBG_REG, 0x20);
4921
4922         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4923
4924         if (tp->dev->mtu <= ETH_DATA_LEN)
4925                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4926
4927         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4928         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4929 }
4930
4931 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
4932 {
4933         static const struct ephy_info e_info_8168c_1[] = {
4934                 { 0x02, 0x0800, 0x1000 },
4935                 { 0x03, 0,      0x0002 },
4936                 { 0x06, 0x0080, 0x0000 }
4937         };
4938
4939         rtl_set_def_aspm_entry_latency(tp);
4940
4941         RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4942
4943         rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4944
4945         __rtl_hw_start_8168cp(tp);
4946 }
4947
4948 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
4949 {
4950         static const struct ephy_info e_info_8168c_2[] = {
4951                 { 0x01, 0,      0x0001 },
4952                 { 0x03, 0x0400, 0x0220 }
4953         };
4954
4955         rtl_set_def_aspm_entry_latency(tp);
4956
4957         rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4958
4959         __rtl_hw_start_8168cp(tp);
4960 }
4961
4962 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
4963 {
4964         rtl_hw_start_8168c_2(tp);
4965 }
4966
4967 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
4968 {
4969         rtl_set_def_aspm_entry_latency(tp);
4970
4971         __rtl_hw_start_8168cp(tp);
4972 }
4973
4974 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
4975 {
4976         rtl_set_def_aspm_entry_latency(tp);
4977
4978         rtl_disable_clock_request(tp);
4979
4980         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4981
4982         if (tp->dev->mtu <= ETH_DATA_LEN)
4983                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4984
4985         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4986         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4987 }
4988
4989 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4990 {
4991         rtl_set_def_aspm_entry_latency(tp);
4992
4993         if (tp->dev->mtu <= ETH_DATA_LEN)
4994                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4995
4996         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4997
4998         rtl_disable_clock_request(tp);
4999 }
5000
5001 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
5002 {
5003         static const struct ephy_info e_info_8168d_4[] = {
5004                 { 0x0b, 0x0000, 0x0048 },
5005                 { 0x19, 0x0020, 0x0050 },
5006                 { 0x0c, 0x0100, 0x0020 }
5007         };
5008
5009         rtl_set_def_aspm_entry_latency(tp);
5010
5011         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5012
5013         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5014
5015         rtl_ephy_init(tp, e_info_8168d_4, ARRAY_SIZE(e_info_8168d_4));
5016
5017         rtl_enable_clock_request(tp);
5018 }
5019
5020 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
5021 {
5022         static const struct ephy_info e_info_8168e_1[] = {
5023                 { 0x00, 0x0200, 0x0100 },
5024                 { 0x00, 0x0000, 0x0004 },
5025                 { 0x06, 0x0002, 0x0001 },
5026                 { 0x06, 0x0000, 0x0030 },
5027                 { 0x07, 0x0000, 0x2000 },
5028                 { 0x00, 0x0000, 0x0020 },
5029                 { 0x03, 0x5800, 0x2000 },
5030                 { 0x03, 0x0000, 0x0001 },
5031                 { 0x01, 0x0800, 0x1000 },
5032                 { 0x07, 0x0000, 0x4000 },
5033                 { 0x1e, 0x0000, 0x2000 },
5034                 { 0x19, 0xffff, 0xfe6c },
5035                 { 0x0a, 0x0000, 0x0040 }
5036         };
5037
5038         rtl_set_def_aspm_entry_latency(tp);
5039
5040         rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
5041
5042         if (tp->dev->mtu <= ETH_DATA_LEN)
5043                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5044
5045         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5046
5047         rtl_disable_clock_request(tp);
5048
5049         /* Reset tx FIFO pointer */
5050         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
5051         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
5052
5053         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
5054 }
5055
5056 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
5057 {
5058         static const struct ephy_info e_info_8168e_2[] = {
5059                 { 0x09, 0x0000, 0x0080 },
5060                 { 0x19, 0x0000, 0x0224 }
5061         };
5062
5063         rtl_set_def_aspm_entry_latency(tp);
5064
5065         rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
5066
5067         if (tp->dev->mtu <= ETH_DATA_LEN)
5068                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5069
5070         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5071         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5072         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5073         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5074         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5075         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
5076         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5077         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5078
5079         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5080
5081         rtl_disable_clock_request(tp);
5082
5083         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5084
5085         /* Adjust EEE LED frequency */
5086         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5087
5088         rtl8168_config_eee_mac(tp);
5089
5090         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5091         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
5092         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
5093
5094         rtl_hw_aspm_clkreq_enable(tp, true);
5095 }
5096
5097 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
5098 {
5099         rtl_set_def_aspm_entry_latency(tp);
5100
5101         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5102
5103         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5104         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5105         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5106         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5107         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5108         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5109         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5110         rtl_w0w1_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5111         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5112         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
5113
5114         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5115
5116         rtl_disable_clock_request(tp);
5117
5118         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5119         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5120         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
5121         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
5122
5123         rtl8168_config_eee_mac(tp);
5124 }
5125
5126 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5127 {
5128         static const struct ephy_info e_info_8168f_1[] = {
5129                 { 0x06, 0x00c0, 0x0020 },
5130                 { 0x08, 0x0001, 0x0002 },
5131                 { 0x09, 0x0000, 0x0080 },
5132                 { 0x19, 0x0000, 0x0224 }
5133         };
5134
5135         rtl_hw_start_8168f(tp);
5136
5137         rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5138
5139         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5140
5141         /* Adjust EEE LED frequency */
5142         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5143 }
5144
5145 static void rtl_hw_start_8411(struct rtl8169_private *tp)
5146 {
5147         static const struct ephy_info e_info_8168f_1[] = {
5148                 { 0x06, 0x00c0, 0x0020 },
5149                 { 0x0f, 0xffff, 0x5200 },
5150                 { 0x1e, 0x0000, 0x4000 },
5151                 { 0x19, 0x0000, 0x0224 }
5152         };
5153
5154         rtl_hw_start_8168f(tp);
5155         rtl_pcie_state_l2l3_disable(tp);
5156
5157         rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5158
5159         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
5160 }
5161
5162 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
5163 {
5164         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
5165         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5166         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5167         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5168
5169         rtl_set_def_aspm_entry_latency(tp);
5170
5171         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5172
5173         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5174         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5175         rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
5176
5177         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5178         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5179
5180         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5181         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5182
5183         /* Adjust EEE LED frequency */
5184         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5185
5186         rtl8168_config_eee_mac(tp);
5187
5188         rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5189         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
5190
5191         rtl_pcie_state_l2l3_disable(tp);
5192 }
5193
5194 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
5195 {
5196         static const struct ephy_info e_info_8168g_1[] = {
5197                 { 0x00, 0x0000, 0x0008 },
5198                 { 0x0c, 0x37d0, 0x0820 },
5199                 { 0x1e, 0x0000, 0x0001 },
5200                 { 0x19, 0x8000, 0x0000 }
5201         };
5202
5203         rtl_hw_start_8168g(tp);
5204
5205         /* disable aspm and clock request before access ephy */
5206         rtl_hw_aspm_clkreq_enable(tp, false);
5207         rtl_ephy_init(tp, e_info_8168g_1, ARRAY_SIZE(e_info_8168g_1));
5208         rtl_hw_aspm_clkreq_enable(tp, true);
5209 }
5210
5211 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
5212 {
5213         static const struct ephy_info e_info_8168g_2[] = {
5214                 { 0x00, 0x0000, 0x0008 },
5215                 { 0x0c, 0x3df0, 0x0200 },
5216                 { 0x19, 0xffff, 0xfc00 },
5217                 { 0x1e, 0xffff, 0x20eb }
5218         };
5219
5220         rtl_hw_start_8168g(tp);
5221
5222         /* disable aspm and clock request before access ephy */
5223         RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
5224         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
5225         rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
5226 }
5227
5228 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
5229 {
5230         static const struct ephy_info e_info_8411_2[] = {
5231                 { 0x00, 0x0000, 0x0008 },
5232                 { 0x0c, 0x3df0, 0x0200 },
5233                 { 0x0f, 0xffff, 0x5200 },
5234                 { 0x19, 0x0020, 0x0000 },
5235                 { 0x1e, 0x0000, 0x2000 }
5236         };
5237
5238         rtl_hw_start_8168g(tp);
5239
5240         /* disable aspm and clock request before access ephy */
5241         rtl_hw_aspm_clkreq_enable(tp, false);
5242         rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
5243         rtl_hw_aspm_clkreq_enable(tp, true);
5244 }
5245
5246 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
5247 {
5248         int rg_saw_cnt;
5249         u32 data;
5250         static const struct ephy_info e_info_8168h_1[] = {
5251                 { 0x1e, 0x0800, 0x0001 },
5252                 { 0x1d, 0x0000, 0x0800 },
5253                 { 0x05, 0xffff, 0x2089 },
5254                 { 0x06, 0xffff, 0x5881 },
5255                 { 0x04, 0xffff, 0x154a },
5256                 { 0x01, 0xffff, 0x068b }
5257         };
5258
5259         /* disable aspm and clock request before access ephy */
5260         rtl_hw_aspm_clkreq_enable(tp, false);
5261         rtl_ephy_init(tp, e_info_8168h_1, ARRAY_SIZE(e_info_8168h_1));
5262
5263         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
5264         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5265         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5266         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5267
5268         rtl_set_def_aspm_entry_latency(tp);
5269
5270         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5271
5272         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5273         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5274
5275         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_1111, 0x0010, 0x00, ERIAR_EXGMAC);
5276
5277         rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f00, 0x00, ERIAR_EXGMAC);
5278
5279         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
5280
5281         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5282         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5283
5284         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5285         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5286
5287         /* Adjust EEE LED frequency */
5288         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5289
5290         rtl8168_config_eee_mac(tp);
5291
5292         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5293         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5294
5295         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
5296
5297         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
5298
5299         rtl_pcie_state_l2l3_disable(tp);
5300
5301         rtl_writephy(tp, 0x1f, 0x0c42);
5302         rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
5303         rtl_writephy(tp, 0x1f, 0x0000);
5304         if (rg_saw_cnt > 0) {
5305                 u16 sw_cnt_1ms_ini;
5306
5307                 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
5308                 sw_cnt_1ms_ini &= 0x0fff;
5309                 data = r8168_mac_ocp_read(tp, 0xd412);
5310                 data &= ~0x0fff;
5311                 data |= sw_cnt_1ms_ini;
5312                 r8168_mac_ocp_write(tp, 0xd412, data);
5313         }
5314
5315         data = r8168_mac_ocp_read(tp, 0xe056);
5316         data &= ~0xf0;
5317         data |= 0x70;
5318         r8168_mac_ocp_write(tp, 0xe056, data);
5319
5320         data = r8168_mac_ocp_read(tp, 0xe052);
5321         data &= ~0x6000;
5322         data |= 0x8008;
5323         r8168_mac_ocp_write(tp, 0xe052, data);
5324
5325         data = r8168_mac_ocp_read(tp, 0xe0d6);
5326         data &= ~0x01ff;
5327         data |= 0x017f;
5328         r8168_mac_ocp_write(tp, 0xe0d6, data);
5329
5330         data = r8168_mac_ocp_read(tp, 0xd420);
5331         data &= ~0x0fff;
5332         data |= 0x047f;
5333         r8168_mac_ocp_write(tp, 0xd420, data);
5334
5335         r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
5336         r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
5337         r8168_mac_ocp_write(tp, 0xc094, 0x0000);
5338         r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
5339
5340         rtl_hw_aspm_clkreq_enable(tp, true);
5341 }
5342
5343 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
5344 {
5345         rtl8168ep_stop_cmac(tp);
5346
5347         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
5348         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x2f, ERIAR_EXGMAC);
5349         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x5f, ERIAR_EXGMAC);
5350         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5351
5352         rtl_set_def_aspm_entry_latency(tp);
5353
5354         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5355
5356         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5357         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5358
5359         rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f80, 0x00, ERIAR_EXGMAC);
5360
5361         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
5362
5363         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5364         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5365
5366         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5367         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5368
5369         /* Adjust EEE LED frequency */
5370         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5371
5372         rtl8168_config_eee_mac(tp);
5373
5374         rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5375
5376         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
5377
5378         rtl_pcie_state_l2l3_disable(tp);
5379 }
5380
5381 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
5382 {
5383         static const struct ephy_info e_info_8168ep_1[] = {
5384                 { 0x00, 0xffff, 0x10ab },
5385                 { 0x06, 0xffff, 0xf030 },
5386                 { 0x08, 0xffff, 0x2006 },
5387                 { 0x0d, 0xffff, 0x1666 },
5388                 { 0x0c, 0x3ff0, 0x0000 }
5389         };
5390
5391         /* disable aspm and clock request before access ephy */
5392         rtl_hw_aspm_clkreq_enable(tp, false);
5393         rtl_ephy_init(tp, e_info_8168ep_1, ARRAY_SIZE(e_info_8168ep_1));
5394
5395         rtl_hw_start_8168ep(tp);
5396
5397         rtl_hw_aspm_clkreq_enable(tp, true);
5398 }
5399
5400 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
5401 {
5402         static const struct ephy_info e_info_8168ep_2[] = {
5403                 { 0x00, 0xffff, 0x10a3 },
5404                 { 0x19, 0xffff, 0xfc00 },
5405                 { 0x1e, 0xffff, 0x20ea }
5406         };
5407
5408         /* disable aspm and clock request before access ephy */
5409         rtl_hw_aspm_clkreq_enable(tp, false);
5410         rtl_ephy_init(tp, e_info_8168ep_2, ARRAY_SIZE(e_info_8168ep_2));
5411
5412         rtl_hw_start_8168ep(tp);
5413
5414         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5415         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5416
5417         rtl_hw_aspm_clkreq_enable(tp, true);
5418 }
5419
5420 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
5421 {
5422         u32 data;
5423         static const struct ephy_info e_info_8168ep_3[] = {
5424                 { 0x00, 0xffff, 0x10a3 },
5425                 { 0x19, 0xffff, 0x7c00 },
5426                 { 0x1e, 0xffff, 0x20eb },
5427                 { 0x0d, 0xffff, 0x1666 }
5428         };
5429
5430         /* disable aspm and clock request before access ephy */
5431         rtl_hw_aspm_clkreq_enable(tp, false);
5432         rtl_ephy_init(tp, e_info_8168ep_3, ARRAY_SIZE(e_info_8168ep_3));
5433
5434         rtl_hw_start_8168ep(tp);
5435
5436         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5437         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5438
5439         data = r8168_mac_ocp_read(tp, 0xd3e2);
5440         data &= 0xf000;
5441         data |= 0x0271;
5442         r8168_mac_ocp_write(tp, 0xd3e2, data);
5443
5444         data = r8168_mac_ocp_read(tp, 0xd3e4);
5445         data &= 0xff00;
5446         r8168_mac_ocp_write(tp, 0xd3e4, data);
5447
5448         data = r8168_mac_ocp_read(tp, 0xe860);
5449         data |= 0x0080;
5450         r8168_mac_ocp_write(tp, 0xe860, data);
5451
5452         rtl_hw_aspm_clkreq_enable(tp, true);
5453 }
5454
5455 static void rtl_hw_start_8168(struct rtl8169_private *tp)
5456 {
5457         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5458
5459         tp->cp_cmd &= ~INTT_MASK;
5460         tp->cp_cmd |= PktCntrDisable | INTT_1;
5461         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5462
5463         RTL_W16(tp, IntrMitigate, 0x5151);
5464
5465         /* Work around for RxFIFO overflow. */
5466         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
5467                 tp->irq_mask |= RxFIFOOver;
5468                 tp->irq_mask &= ~RxOverflow;
5469         }
5470
5471         switch (tp->mac_version) {
5472         case RTL_GIGA_MAC_VER_11:
5473                 rtl_hw_start_8168bb(tp);
5474                 break;
5475
5476         case RTL_GIGA_MAC_VER_12:
5477         case RTL_GIGA_MAC_VER_17:
5478                 rtl_hw_start_8168bef(tp);
5479                 break;
5480
5481         case RTL_GIGA_MAC_VER_18:
5482                 rtl_hw_start_8168cp_1(tp);
5483                 break;
5484
5485         case RTL_GIGA_MAC_VER_19:
5486                 rtl_hw_start_8168c_1(tp);
5487                 break;
5488
5489         case RTL_GIGA_MAC_VER_20:
5490                 rtl_hw_start_8168c_2(tp);
5491                 break;
5492
5493         case RTL_GIGA_MAC_VER_21:
5494                 rtl_hw_start_8168c_3(tp);
5495                 break;
5496
5497         case RTL_GIGA_MAC_VER_22:
5498                 rtl_hw_start_8168c_4(tp);
5499                 break;
5500
5501         case RTL_GIGA_MAC_VER_23:
5502                 rtl_hw_start_8168cp_2(tp);
5503                 break;
5504
5505         case RTL_GIGA_MAC_VER_24:
5506                 rtl_hw_start_8168cp_3(tp);
5507                 break;
5508
5509         case RTL_GIGA_MAC_VER_25:
5510         case RTL_GIGA_MAC_VER_26:
5511         case RTL_GIGA_MAC_VER_27:
5512                 rtl_hw_start_8168d(tp);
5513                 break;
5514
5515         case RTL_GIGA_MAC_VER_28:
5516                 rtl_hw_start_8168d_4(tp);
5517                 break;
5518
5519         case RTL_GIGA_MAC_VER_31:
5520                 rtl_hw_start_8168dp(tp);
5521                 break;
5522
5523         case RTL_GIGA_MAC_VER_32:
5524         case RTL_GIGA_MAC_VER_33:
5525                 rtl_hw_start_8168e_1(tp);
5526                 break;
5527         case RTL_GIGA_MAC_VER_34:
5528                 rtl_hw_start_8168e_2(tp);
5529                 break;
5530
5531         case RTL_GIGA_MAC_VER_35:
5532         case RTL_GIGA_MAC_VER_36:
5533                 rtl_hw_start_8168f_1(tp);
5534                 break;
5535
5536         case RTL_GIGA_MAC_VER_38:
5537                 rtl_hw_start_8411(tp);
5538                 break;
5539
5540         case RTL_GIGA_MAC_VER_40:
5541         case RTL_GIGA_MAC_VER_41:
5542                 rtl_hw_start_8168g_1(tp);
5543                 break;
5544         case RTL_GIGA_MAC_VER_42:
5545                 rtl_hw_start_8168g_2(tp);
5546                 break;
5547
5548         case RTL_GIGA_MAC_VER_44:
5549                 rtl_hw_start_8411_2(tp);
5550                 break;
5551
5552         case RTL_GIGA_MAC_VER_45:
5553         case RTL_GIGA_MAC_VER_46:
5554                 rtl_hw_start_8168h_1(tp);
5555                 break;
5556
5557         case RTL_GIGA_MAC_VER_49:
5558                 rtl_hw_start_8168ep_1(tp);
5559                 break;
5560
5561         case RTL_GIGA_MAC_VER_50:
5562                 rtl_hw_start_8168ep_2(tp);
5563                 break;
5564
5565         case RTL_GIGA_MAC_VER_51:
5566                 rtl_hw_start_8168ep_3(tp);
5567                 break;
5568
5569         default:
5570                 netif_err(tp, drv, tp->dev,
5571                           "unknown chipset (mac_version = %d)\n",
5572                           tp->mac_version);
5573                 break;
5574         }
5575 }
5576
5577 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
5578 {
5579         static const struct ephy_info e_info_8102e_1[] = {
5580                 { 0x01, 0, 0x6e65 },
5581                 { 0x02, 0, 0x091f },
5582                 { 0x03, 0, 0xc2f9 },
5583                 { 0x06, 0, 0xafb5 },
5584                 { 0x07, 0, 0x0e00 },
5585                 { 0x19, 0, 0xec80 },
5586                 { 0x01, 0, 0x2e65 },
5587                 { 0x01, 0, 0x6e65 }
5588         };
5589         u8 cfg1;
5590
5591         rtl_set_def_aspm_entry_latency(tp);
5592
5593         RTL_W8(tp, DBG_REG, FIX_NAK_1);
5594
5595         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5596
5597         RTL_W8(tp, Config1,
5598                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5599         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5600
5601         cfg1 = RTL_R8(tp, Config1);
5602         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5603                 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
5604
5605         rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
5606 }
5607
5608 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
5609 {
5610         rtl_set_def_aspm_entry_latency(tp);
5611
5612         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5613
5614         RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
5615         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5616 }
5617
5618 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
5619 {
5620         rtl_hw_start_8102e_2(tp);
5621
5622         rtl_ephy_write(tp, 0x03, 0xc2f9);
5623 }
5624
5625 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5626 {
5627         static const struct ephy_info e_info_8105e_1[] = {
5628                 { 0x07, 0, 0x4000 },
5629                 { 0x19, 0, 0x0200 },
5630                 { 0x19, 0, 0x0020 },
5631                 { 0x1e, 0, 0x2000 },
5632                 { 0x03, 0, 0x0001 },
5633                 { 0x19, 0, 0x0100 },
5634                 { 0x19, 0, 0x0004 },
5635                 { 0x0a, 0, 0x0020 }
5636         };
5637
5638         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5639         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5640
5641         /* Disable Early Tally Counter */
5642         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
5643
5644         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5645         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5646
5647         rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
5648
5649         rtl_pcie_state_l2l3_disable(tp);
5650 }
5651
5652 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5653 {
5654         rtl_hw_start_8105e_1(tp);
5655         rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5656 }
5657
5658 static void rtl_hw_start_8402(struct rtl8169_private *tp)
5659 {
5660         static const struct ephy_info e_info_8402[] = {
5661                 { 0x19, 0xffff, 0xff64 },
5662                 { 0x1e, 0, 0x4000 }
5663         };
5664
5665         rtl_set_def_aspm_entry_latency(tp);
5666
5667         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5668         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5669
5670         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5671
5672         rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
5673
5674         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5675
5676         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
5677         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
5678         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5679         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5680         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5681         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5682         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
5683
5684         rtl_pcie_state_l2l3_disable(tp);
5685 }
5686
5687 static void rtl_hw_start_8106(struct rtl8169_private *tp)
5688 {
5689         rtl_hw_aspm_clkreq_enable(tp, false);
5690
5691         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5692         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5693
5694         RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5695         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5696         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5697
5698         rtl_pcie_state_l2l3_disable(tp);
5699         rtl_hw_aspm_clkreq_enable(tp, true);
5700 }
5701
5702 static void rtl_hw_start_8101(struct rtl8169_private *tp)
5703 {
5704         if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
5705                 tp->irq_mask &= ~RxFIFOOver;
5706
5707         if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
5708             tp->mac_version == RTL_GIGA_MAC_VER_16)
5709                 pcie_capability_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
5710                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
5711
5712         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5713
5714         tp->cp_cmd &= CPCMD_QUIRK_MASK;
5715         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5716
5717         switch (tp->mac_version) {
5718         case RTL_GIGA_MAC_VER_07:
5719                 rtl_hw_start_8102e_1(tp);
5720                 break;
5721
5722         case RTL_GIGA_MAC_VER_08:
5723                 rtl_hw_start_8102e_3(tp);
5724                 break;
5725
5726         case RTL_GIGA_MAC_VER_09:
5727                 rtl_hw_start_8102e_2(tp);
5728                 break;
5729
5730         case RTL_GIGA_MAC_VER_29:
5731                 rtl_hw_start_8105e_1(tp);
5732                 break;
5733         case RTL_GIGA_MAC_VER_30:
5734                 rtl_hw_start_8105e_2(tp);
5735                 break;
5736
5737         case RTL_GIGA_MAC_VER_37:
5738                 rtl_hw_start_8402(tp);
5739                 break;
5740
5741         case RTL_GIGA_MAC_VER_39:
5742                 rtl_hw_start_8106(tp);
5743                 break;
5744         case RTL_GIGA_MAC_VER_43:
5745                 rtl_hw_start_8168g_2(tp);
5746                 break;
5747         case RTL_GIGA_MAC_VER_47:
5748         case RTL_GIGA_MAC_VER_48:
5749                 rtl_hw_start_8168h_1(tp);
5750                 break;
5751         }
5752
5753         RTL_W16(tp, IntrMitigate, 0x0000);
5754 }
5755
5756 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5757 {
5758         struct rtl8169_private *tp = netdev_priv(dev);
5759
5760         if (new_mtu > ETH_DATA_LEN)
5761                 rtl_hw_jumbo_enable(tp);
5762         else
5763                 rtl_hw_jumbo_disable(tp);
5764
5765         dev->mtu = new_mtu;
5766         netdev_update_features(dev);
5767
5768         return 0;
5769 }
5770
5771 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5772 {
5773         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
5774         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5775 }
5776
5777 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5778                                      void **data_buff, struct RxDesc *desc)
5779 {
5780         dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr),
5781                          R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
5782
5783         kfree(*data_buff);
5784         *data_buff = NULL;
5785         rtl8169_make_unusable_by_asic(desc);
5786 }
5787
5788 static inline void rtl8169_mark_to_asic(struct RxDesc *desc)
5789 {
5790         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5791
5792         /* Force memory writes to complete before releasing descriptor */
5793         dma_wmb();
5794
5795         desc->opts1 = cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE);
5796 }
5797
5798 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5799                                              struct RxDesc *desc)
5800 {
5801         void *data;
5802         dma_addr_t mapping;
5803         struct device *d = tp_to_dev(tp);
5804         int node = dev_to_node(d);
5805
5806         data = kmalloc_node(R8169_RX_BUF_SIZE, GFP_KERNEL, node);
5807         if (!data)
5808                 return NULL;
5809
5810         /* Memory should be properly aligned, but better check. */
5811         if (!IS_ALIGNED((unsigned long)data, 8)) {
5812                 netdev_err_once(tp->dev, "RX buffer not 8-byte-aligned\n");
5813                 goto err_out;
5814         }
5815
5816         mapping = dma_map_single(d, data, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
5817         if (unlikely(dma_mapping_error(d, mapping))) {
5818                 if (net_ratelimit())
5819                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
5820                 goto err_out;
5821         }
5822
5823         desc->addr = cpu_to_le64(mapping);
5824         rtl8169_mark_to_asic(desc);
5825         return data;
5826
5827 err_out:
5828         kfree(data);
5829         return NULL;
5830 }
5831
5832 static void rtl8169_rx_clear(struct rtl8169_private *tp)
5833 {
5834         unsigned int i;
5835
5836         for (i = 0; i < NUM_RX_DESC; i++) {
5837                 if (tp->Rx_databuff[i]) {
5838                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
5839                                             tp->RxDescArray + i);
5840                 }
5841         }
5842 }
5843
5844 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
5845 {
5846         desc->opts1 |= cpu_to_le32(RingEnd);
5847 }
5848
5849 static int rtl8169_rx_fill(struct rtl8169_private *tp)
5850 {
5851         unsigned int i;
5852
5853         for (i = 0; i < NUM_RX_DESC; i++) {
5854                 void *data;
5855
5856                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
5857                 if (!data) {
5858                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
5859                         goto err_out;
5860                 }
5861                 tp->Rx_databuff[i] = data;
5862         }
5863
5864         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5865         return 0;
5866
5867 err_out:
5868         rtl8169_rx_clear(tp);
5869         return -ENOMEM;
5870 }
5871
5872 static int rtl8169_init_ring(struct rtl8169_private *tp)
5873 {
5874         rtl8169_init_ring_indexes(tp);
5875
5876         memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
5877         memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
5878
5879         return rtl8169_rx_fill(tp);
5880 }
5881
5882 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
5883                                  struct TxDesc *desc)
5884 {
5885         unsigned int len = tx_skb->len;
5886
5887         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5888
5889         desc->opts1 = 0x00;
5890         desc->opts2 = 0x00;
5891         desc->addr = 0x00;
5892         tx_skb->len = 0;
5893 }
5894
5895 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5896                                    unsigned int n)
5897 {
5898         unsigned int i;
5899
5900         for (i = 0; i < n; i++) {
5901                 unsigned int entry = (start + i) % NUM_TX_DESC;
5902                 struct ring_info *tx_skb = tp->tx_skb + entry;
5903                 unsigned int len = tx_skb->len;
5904
5905                 if (len) {
5906                         struct sk_buff *skb = tx_skb->skb;
5907
5908                         rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
5909                                              tp->TxDescArray + entry);
5910                         if (skb) {
5911                                 dev_consume_skb_any(skb);
5912                                 tx_skb->skb = NULL;
5913                         }
5914                 }
5915         }
5916 }
5917
5918 static void rtl8169_tx_clear(struct rtl8169_private *tp)
5919 {
5920         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
5921         tp->cur_tx = tp->dirty_tx = 0;
5922         netdev_reset_queue(tp->dev);
5923 }
5924
5925 static void rtl_reset_work(struct rtl8169_private *tp)
5926 {
5927         struct net_device *dev = tp->dev;
5928         int i;
5929
5930         napi_disable(&tp->napi);
5931         netif_stop_queue(dev);
5932         synchronize_rcu();
5933
5934         rtl8169_hw_reset(tp);
5935
5936         for (i = 0; i < NUM_RX_DESC; i++)
5937                 rtl8169_mark_to_asic(tp->RxDescArray + i);
5938
5939         rtl8169_tx_clear(tp);
5940         rtl8169_init_ring_indexes(tp);
5941
5942         napi_enable(&tp->napi);
5943         rtl_hw_start(tp);
5944         netif_wake_queue(dev);
5945 }
5946
5947 static void rtl8169_tx_timeout(struct net_device *dev)
5948 {
5949         struct rtl8169_private *tp = netdev_priv(dev);
5950
5951         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5952 }
5953
5954 static __le32 rtl8169_get_txd_opts1(u32 opts0, u32 len, unsigned int entry)
5955 {
5956         u32 status = opts0 | len;
5957
5958         if (entry == NUM_TX_DESC - 1)
5959                 status |= RingEnd;
5960
5961         return cpu_to_le32(status);
5962 }
5963
5964 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5965                               u32 *opts)
5966 {
5967         struct skb_shared_info *info = skb_shinfo(skb);
5968         unsigned int cur_frag, entry;
5969         struct TxDesc *uninitialized_var(txd);
5970         struct device *d = tp_to_dev(tp);
5971
5972         entry = tp->cur_tx;
5973         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5974                 const skb_frag_t *frag = info->frags + cur_frag;
5975                 dma_addr_t mapping;
5976                 u32 len;
5977                 void *addr;
5978
5979                 entry = (entry + 1) % NUM_TX_DESC;
5980
5981                 txd = tp->TxDescArray + entry;
5982                 len = skb_frag_size(frag);
5983                 addr = skb_frag_address(frag);
5984                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5985                 if (unlikely(dma_mapping_error(d, mapping))) {
5986                         if (net_ratelimit())
5987                                 netif_err(tp, drv, tp->dev,
5988                                           "Failed to map TX fragments DMA!\n");
5989                         goto err_out;
5990                 }
5991
5992                 txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry);
5993                 txd->opts2 = cpu_to_le32(opts[1]);
5994                 txd->addr = cpu_to_le64(mapping);
5995
5996                 tp->tx_skb[entry].len = len;
5997         }
5998
5999         if (cur_frag) {
6000                 tp->tx_skb[entry].skb = skb;
6001                 txd->opts1 |= cpu_to_le32(LastFrag);
6002         }
6003
6004         return cur_frag;
6005
6006 err_out:
6007         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
6008         return -EIO;
6009 }
6010
6011 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
6012 {
6013         return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
6014 }
6015
6016 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6017                                       struct net_device *dev);
6018 /* r8169_csum_workaround()
6019  * The hw limites the value the transport offset. When the offset is out of the
6020  * range, calculate the checksum by sw.
6021  */
6022 static void r8169_csum_workaround(struct rtl8169_private *tp,
6023                                   struct sk_buff *skb)
6024 {
6025         if (skb_shinfo(skb)->gso_size) {
6026                 netdev_features_t features = tp->dev->features;
6027                 struct sk_buff *segs, *nskb;
6028
6029                 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
6030                 segs = skb_gso_segment(skb, features);
6031                 if (IS_ERR(segs) || !segs)
6032                         goto drop;
6033
6034                 do {
6035                         nskb = segs;
6036                         segs = segs->next;
6037                         nskb->next = NULL;
6038                         rtl8169_start_xmit(nskb, tp->dev);
6039                 } while (segs);
6040
6041                 dev_consume_skb_any(skb);
6042         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6043                 if (skb_checksum_help(skb) < 0)
6044                         goto drop;
6045
6046                 rtl8169_start_xmit(skb, tp->dev);
6047         } else {
6048                 struct net_device_stats *stats;
6049
6050 drop:
6051                 stats = &tp->dev->stats;
6052                 stats->tx_dropped++;
6053                 dev_kfree_skb_any(skb);
6054         }
6055 }
6056
6057 /* msdn_giant_send_check()
6058  * According to the document of microsoft, the TCP Pseudo Header excludes the
6059  * packet length for IPv6 TCP large packets.
6060  */
6061 static int msdn_giant_send_check(struct sk_buff *skb)
6062 {
6063         const struct ipv6hdr *ipv6h;
6064         struct tcphdr *th;
6065         int ret;
6066
6067         ret = skb_cow_head(skb, 0);
6068         if (ret)
6069                 return ret;
6070
6071         ipv6h = ipv6_hdr(skb);
6072         th = tcp_hdr(skb);
6073
6074         th->check = 0;
6075         th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
6076
6077         return ret;
6078 }
6079
6080 static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp,
6081                                 struct sk_buff *skb, u32 *opts)
6082 {
6083         u32 mss = skb_shinfo(skb)->gso_size;
6084
6085         if (mss) {
6086                 opts[0] |= TD_LSO;
6087                 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
6088         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6089                 const struct iphdr *ip = ip_hdr(skb);
6090
6091                 if (ip->protocol == IPPROTO_TCP)
6092                         opts[0] |= TD0_IP_CS | TD0_TCP_CS;
6093                 else if (ip->protocol == IPPROTO_UDP)
6094                         opts[0] |= TD0_IP_CS | TD0_UDP_CS;
6095                 else
6096                         WARN_ON_ONCE(1);
6097         }
6098
6099         return true;
6100 }
6101
6102 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
6103                                 struct sk_buff *skb, u32 *opts)
6104 {
6105         u32 transport_offset = (u32)skb_transport_offset(skb);
6106         u32 mss = skb_shinfo(skb)->gso_size;
6107
6108         if (mss) {
6109                 if (transport_offset > GTTCPHO_MAX) {
6110                         netif_warn(tp, tx_err, tp->dev,
6111                                    "Invalid transport offset 0x%x for TSO\n",
6112                                    transport_offset);
6113                         return false;
6114                 }
6115
6116                 switch (vlan_get_protocol(skb)) {
6117                 case htons(ETH_P_IP):
6118                         opts[0] |= TD1_GTSENV4;
6119                         break;
6120
6121                 case htons(ETH_P_IPV6):
6122                         if (msdn_giant_send_check(skb))
6123                                 return false;
6124
6125                         opts[0] |= TD1_GTSENV6;
6126                         break;
6127
6128                 default:
6129                         WARN_ON_ONCE(1);
6130                         break;
6131                 }
6132
6133                 opts[0] |= transport_offset << GTTCPHO_SHIFT;
6134                 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
6135         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6136                 u8 ip_protocol;
6137
6138                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
6139                         return !(skb_checksum_help(skb) || eth_skb_pad(skb));
6140
6141                 if (transport_offset > TCPHO_MAX) {
6142                         netif_warn(tp, tx_err, tp->dev,
6143                                    "Invalid transport offset 0x%x\n",
6144                                    transport_offset);
6145                         return false;
6146                 }
6147
6148                 switch (vlan_get_protocol(skb)) {
6149                 case htons(ETH_P_IP):
6150                         opts[1] |= TD1_IPv4_CS;
6151                         ip_protocol = ip_hdr(skb)->protocol;
6152                         break;
6153
6154                 case htons(ETH_P_IPV6):
6155                         opts[1] |= TD1_IPv6_CS;
6156                         ip_protocol = ipv6_hdr(skb)->nexthdr;
6157                         break;
6158
6159                 default:
6160                         ip_protocol = IPPROTO_RAW;
6161                         break;
6162                 }
6163
6164                 if (ip_protocol == IPPROTO_TCP)
6165                         opts[1] |= TD1_TCP_CS;
6166                 else if (ip_protocol == IPPROTO_UDP)
6167                         opts[1] |= TD1_UDP_CS;
6168                 else
6169                         WARN_ON_ONCE(1);
6170
6171                 opts[1] |= transport_offset << TCPHO_SHIFT;
6172         } else {
6173                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
6174                         return !eth_skb_pad(skb);
6175         }
6176
6177         return true;
6178 }
6179
6180 static bool rtl_tx_slots_avail(struct rtl8169_private *tp,
6181                                unsigned int nr_frags)
6182 {
6183         unsigned int slots_avail = tp->dirty_tx + NUM_TX_DESC - tp->cur_tx;
6184
6185         /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
6186         return slots_avail > nr_frags;
6187 }
6188
6189 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6190                                       struct net_device *dev)
6191 {
6192         struct rtl8169_private *tp = netdev_priv(dev);
6193         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
6194         struct TxDesc *txd = tp->TxDescArray + entry;
6195         struct device *d = tp_to_dev(tp);
6196         dma_addr_t mapping;
6197         u32 opts[2], len;
6198         int frags;
6199
6200         if (unlikely(!rtl_tx_slots_avail(tp, skb_shinfo(skb)->nr_frags))) {
6201                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
6202                 goto err_stop_0;
6203         }
6204
6205         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
6206                 goto err_stop_0;
6207
6208         opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
6209         opts[0] = DescOwn;
6210
6211         if (!tp->tso_csum(tp, skb, opts)) {
6212                 r8169_csum_workaround(tp, skb);
6213                 return NETDEV_TX_OK;
6214         }
6215
6216         len = skb_headlen(skb);
6217         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
6218         if (unlikely(dma_mapping_error(d, mapping))) {
6219                 if (net_ratelimit())
6220                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
6221                 goto err_dma_0;
6222         }
6223
6224         tp->tx_skb[entry].len = len;
6225         txd->addr = cpu_to_le64(mapping);
6226
6227         frags = rtl8169_xmit_frags(tp, skb, opts);
6228         if (frags < 0)
6229                 goto err_dma_1;
6230         else if (frags)
6231                 opts[0] |= FirstFrag;
6232         else {
6233                 opts[0] |= FirstFrag | LastFrag;
6234                 tp->tx_skb[entry].skb = skb;
6235         }
6236
6237         txd->opts2 = cpu_to_le32(opts[1]);
6238
6239         netdev_sent_queue(dev, skb->len);
6240
6241         skb_tx_timestamp(skb);
6242
6243         /* Force memory writes to complete before releasing descriptor */
6244         dma_wmb();
6245
6246         txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry);
6247
6248         /* Force all memory writes to complete before notifying device */
6249         wmb();
6250
6251         tp->cur_tx += frags + 1;
6252
6253         RTL_W8(tp, TxPoll, NPQ);
6254
6255         if (!rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) {
6256                 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
6257                  * not miss a ring update when it notices a stopped queue.
6258                  */
6259                 smp_wmb();
6260                 netif_stop_queue(dev);
6261                 /* Sync with rtl_tx:
6262                  * - publish queue status and cur_tx ring index (write barrier)
6263                  * - refresh dirty_tx ring index (read barrier).
6264                  * May the current thread have a pessimistic view of the ring
6265                  * status and forget to wake up queue, a racing rtl_tx thread
6266                  * can't.
6267                  */
6268                 smp_mb();
6269                 if (rtl_tx_slots_avail(tp, MAX_SKB_FRAGS))
6270                         netif_wake_queue(dev);
6271         }
6272
6273         return NETDEV_TX_OK;
6274
6275 err_dma_1:
6276         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
6277 err_dma_0:
6278         dev_kfree_skb_any(skb);
6279         dev->stats.tx_dropped++;
6280         return NETDEV_TX_OK;
6281
6282 err_stop_0:
6283         netif_stop_queue(dev);
6284         dev->stats.tx_dropped++;
6285         return NETDEV_TX_BUSY;
6286 }
6287
6288 static void rtl8169_pcierr_interrupt(struct net_device *dev)
6289 {
6290         struct rtl8169_private *tp = netdev_priv(dev);
6291         struct pci_dev *pdev = tp->pci_dev;
6292         u16 pci_status, pci_cmd;
6293
6294         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
6295         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
6296
6297         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
6298                   pci_cmd, pci_status);
6299
6300         /*
6301          * The recovery sequence below admits a very elaborated explanation:
6302          * - it seems to work;
6303          * - I did not see what else could be done;
6304          * - it makes iop3xx happy.
6305          *
6306          * Feel free to adjust to your needs.
6307          */
6308         if (pdev->broken_parity_status)
6309                 pci_cmd &= ~PCI_COMMAND_PARITY;
6310         else
6311                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
6312
6313         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
6314
6315         pci_write_config_word(pdev, PCI_STATUS,
6316                 pci_status & (PCI_STATUS_DETECTED_PARITY |
6317                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
6318                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
6319
6320         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6321 }
6322
6323 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp,
6324                    int budget)
6325 {
6326         unsigned int dirty_tx, tx_left, bytes_compl = 0, pkts_compl = 0;
6327
6328         dirty_tx = tp->dirty_tx;
6329         smp_rmb();
6330         tx_left = tp->cur_tx - dirty_tx;
6331
6332         while (tx_left > 0) {
6333                 unsigned int entry = dirty_tx % NUM_TX_DESC;
6334                 struct ring_info *tx_skb = tp->tx_skb + entry;
6335                 u32 status;
6336
6337                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
6338                 if (status & DescOwn)
6339                         break;
6340
6341                 /* This barrier is needed to keep us from reading
6342                  * any other fields out of the Tx descriptor until
6343                  * we know the status of DescOwn
6344                  */
6345                 dma_rmb();
6346
6347                 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
6348                                      tp->TxDescArray + entry);
6349                 if (status & LastFrag) {
6350                         pkts_compl++;
6351                         bytes_compl += tx_skb->skb->len;
6352                         napi_consume_skb(tx_skb->skb, budget);
6353                         tx_skb->skb = NULL;
6354                 }
6355                 dirty_tx++;
6356                 tx_left--;
6357         }
6358
6359         if (tp->dirty_tx != dirty_tx) {
6360                 netdev_completed_queue(dev, pkts_compl, bytes_compl);
6361
6362                 u64_stats_update_begin(&tp->tx_stats.syncp);
6363                 tp->tx_stats.packets += pkts_compl;
6364                 tp->tx_stats.bytes += bytes_compl;
6365                 u64_stats_update_end(&tp->tx_stats.syncp);
6366
6367                 tp->dirty_tx = dirty_tx;
6368                 /* Sync with rtl8169_start_xmit:
6369                  * - publish dirty_tx ring index (write barrier)
6370                  * - refresh cur_tx ring index and queue status (read barrier)
6371                  * May the current thread miss the stopped queue condition,
6372                  * a racing xmit thread can only have a right view of the
6373                  * ring status.
6374                  */
6375                 smp_mb();
6376                 if (netif_queue_stopped(dev) &&
6377                     rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) {
6378                         netif_wake_queue(dev);
6379                 }
6380                 /*
6381                  * 8168 hack: TxPoll requests are lost when the Tx packets are
6382                  * too close. Let's kick an extra TxPoll request when a burst
6383                  * of start_xmit activity is detected (if it is not detected,
6384                  * it is slow enough). -- FR
6385                  */
6386                 if (tp->cur_tx != dirty_tx)
6387                         RTL_W8(tp, TxPoll, NPQ);
6388         }
6389 }
6390
6391 static inline int rtl8169_fragmented_frame(u32 status)
6392 {
6393         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
6394 }
6395
6396 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
6397 {
6398         u32 status = opts1 & RxProtoMask;
6399
6400         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
6401             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
6402                 skb->ip_summed = CHECKSUM_UNNECESSARY;
6403         else
6404                 skb_checksum_none_assert(skb);
6405 }
6406
6407 static struct sk_buff *rtl8169_try_rx_copy(void *data,
6408                                            struct rtl8169_private *tp,
6409                                            int pkt_size,
6410                                            dma_addr_t addr)
6411 {
6412         struct sk_buff *skb;
6413         struct device *d = tp_to_dev(tp);
6414
6415         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6416         prefetch(data);
6417         skb = napi_alloc_skb(&tp->napi, pkt_size);
6418         if (skb)
6419                 skb_copy_to_linear_data(skb, data, pkt_size);
6420         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
6421
6422         return skb;
6423 }
6424
6425 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
6426 {
6427         unsigned int cur_rx, rx_left;
6428         unsigned int count;
6429
6430         cur_rx = tp->cur_rx;
6431
6432         for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
6433                 unsigned int entry = cur_rx % NUM_RX_DESC;
6434                 struct RxDesc *desc = tp->RxDescArray + entry;
6435                 u32 status;
6436
6437                 status = le32_to_cpu(desc->opts1);
6438                 if (status & DescOwn)
6439                         break;
6440
6441                 /* This barrier is needed to keep us from reading
6442                  * any other fields out of the Rx descriptor until
6443                  * we know the status of DescOwn
6444                  */
6445                 dma_rmb();
6446
6447                 if (unlikely(status & RxRES)) {
6448                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
6449                                    status);
6450                         dev->stats.rx_errors++;
6451                         if (status & (RxRWT | RxRUNT))
6452                                 dev->stats.rx_length_errors++;
6453                         if (status & RxCRC)
6454                                 dev->stats.rx_crc_errors++;
6455                         /* RxFOVF is a reserved bit on later chip versions */
6456                         if (tp->mac_version == RTL_GIGA_MAC_VER_01 &&
6457                             status & RxFOVF) {
6458                                 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6459                                 dev->stats.rx_fifo_errors++;
6460                         } else if (status & (RxRUNT | RxCRC) &&
6461                                    !(status & RxRWT) &&
6462                                    dev->features & NETIF_F_RXALL) {
6463                                 goto process_pkt;
6464                         }
6465                 } else {
6466                         struct sk_buff *skb;
6467                         dma_addr_t addr;
6468                         int pkt_size;
6469
6470 process_pkt:
6471                         addr = le64_to_cpu(desc->addr);
6472                         if (likely(!(dev->features & NETIF_F_RXFCS)))
6473                                 pkt_size = (status & 0x00003fff) - 4;
6474                         else
6475                                 pkt_size = status & 0x00003fff;
6476
6477                         /*
6478                          * The driver does not support incoming fragmented
6479                          * frames. They are seen as a symptom of over-mtu
6480                          * sized frames.
6481                          */
6482                         if (unlikely(rtl8169_fragmented_frame(status))) {
6483                                 dev->stats.rx_dropped++;
6484                                 dev->stats.rx_length_errors++;
6485                                 goto release_descriptor;
6486                         }
6487
6488                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
6489                                                   tp, pkt_size, addr);
6490                         if (!skb) {
6491                                 dev->stats.rx_dropped++;
6492                                 goto release_descriptor;
6493                         }
6494
6495                         rtl8169_rx_csum(skb, status);
6496                         skb_put(skb, pkt_size);
6497                         skb->protocol = eth_type_trans(skb, dev);
6498
6499                         rtl8169_rx_vlan_tag(desc, skb);
6500
6501                         if (skb->pkt_type == PACKET_MULTICAST)
6502                                 dev->stats.multicast++;
6503
6504                         napi_gro_receive(&tp->napi, skb);
6505
6506                         u64_stats_update_begin(&tp->rx_stats.syncp);
6507                         tp->rx_stats.packets++;
6508                         tp->rx_stats.bytes += pkt_size;
6509                         u64_stats_update_end(&tp->rx_stats.syncp);
6510                 }
6511 release_descriptor:
6512                 desc->opts2 = 0;
6513                 rtl8169_mark_to_asic(desc);
6514         }
6515
6516         count = cur_rx - tp->cur_rx;
6517         tp->cur_rx = cur_rx;
6518
6519         return count;
6520 }
6521
6522 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
6523 {
6524         struct rtl8169_private *tp = dev_instance;
6525         u16 status = RTL_R16(tp, IntrStatus);
6526
6527         if (!tp->irq_enabled || status == 0xffff || !(status & tp->irq_mask))
6528                 return IRQ_NONE;
6529
6530         if (unlikely(status & SYSErr)) {
6531                 rtl8169_pcierr_interrupt(tp->dev);
6532                 goto out;
6533         }
6534
6535         if (status & LinkChg)
6536                 phy_mac_interrupt(tp->phydev);
6537
6538         if (unlikely(status & RxFIFOOver &&
6539             tp->mac_version == RTL_GIGA_MAC_VER_11)) {
6540                 netif_stop_queue(tp->dev);
6541                 /* XXX - Hack alert. See rtl_task(). */
6542                 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
6543         }
6544
6545         if (status & (RTL_EVENT_NAPI | LinkChg)) {
6546                 rtl_irq_disable(tp);
6547                 napi_schedule_irqoff(&tp->napi);
6548         }
6549 out:
6550         rtl_ack_events(tp, status);
6551
6552         return IRQ_HANDLED;
6553 }
6554
6555 static void rtl_task(struct work_struct *work)
6556 {
6557         static const struct {
6558                 int bitnr;
6559                 void (*action)(struct rtl8169_private *);
6560         } rtl_work[] = {
6561                 { RTL_FLAG_TASK_RESET_PENDING,  rtl_reset_work },
6562         };
6563         struct rtl8169_private *tp =
6564                 container_of(work, struct rtl8169_private, wk.work);
6565         struct net_device *dev = tp->dev;
6566         int i;
6567
6568         rtl_lock_work(tp);
6569
6570         if (!netif_running(dev) ||
6571             !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
6572                 goto out_unlock;
6573
6574         for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
6575                 bool pending;
6576
6577                 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
6578                 if (pending)
6579                         rtl_work[i].action(tp);
6580         }
6581
6582 out_unlock:
6583         rtl_unlock_work(tp);
6584 }
6585
6586 static int rtl8169_poll(struct napi_struct *napi, int budget)
6587 {
6588         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
6589         struct net_device *dev = tp->dev;
6590         int work_done;
6591
6592         work_done = rtl_rx(dev, tp, (u32) budget);
6593
6594         rtl_tx(dev, tp, budget);
6595
6596         if (work_done < budget) {
6597                 napi_complete_done(napi, work_done);
6598                 rtl_irq_enable(tp);
6599         }
6600
6601         return work_done;
6602 }
6603
6604 static void rtl8169_rx_missed(struct net_device *dev)
6605 {
6606         struct rtl8169_private *tp = netdev_priv(dev);
6607
6608         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
6609                 return;
6610
6611         dev->stats.rx_missed_errors += RTL_R32(tp, RxMissed) & 0xffffff;
6612         RTL_W32(tp, RxMissed, 0);
6613 }
6614
6615 static void r8169_phylink_handler(struct net_device *ndev)
6616 {
6617         struct rtl8169_private *tp = netdev_priv(ndev);
6618
6619         if (netif_carrier_ok(ndev)) {
6620                 rtl_link_chg_patch(tp);
6621                 pm_request_resume(&tp->pci_dev->dev);
6622         } else {
6623                 pm_runtime_idle(&tp->pci_dev->dev);
6624         }
6625
6626         if (net_ratelimit())
6627                 phy_print_status(tp->phydev);
6628 }
6629
6630 static int r8169_phy_connect(struct rtl8169_private *tp)
6631 {
6632         struct phy_device *phydev = tp->phydev;
6633         phy_interface_t phy_mode;
6634         int ret;
6635
6636         phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
6637                    PHY_INTERFACE_MODE_MII;
6638
6639         ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
6640                                  phy_mode);
6641         if (ret)
6642                 return ret;
6643
6644         if (!tp->supports_gmii)
6645                 phy_set_max_speed(phydev, SPEED_100);
6646
6647         /* Ensure to advertise everything, incl. pause */
6648         linkmode_copy(phydev->advertising, phydev->supported);
6649
6650         phy_attached_info(phydev);
6651
6652         return 0;
6653 }
6654
6655 static void rtl8169_down(struct net_device *dev)
6656 {
6657         struct rtl8169_private *tp = netdev_priv(dev);
6658
6659         phy_stop(tp->phydev);
6660
6661         napi_disable(&tp->napi);
6662         netif_stop_queue(dev);
6663
6664         rtl8169_hw_reset(tp);
6665         /*
6666          * At this point device interrupts can not be enabled in any function,
6667          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6668          * and napi is disabled (rtl8169_poll).
6669          */
6670         rtl8169_rx_missed(dev);
6671
6672         /* Give a racing hard_start_xmit a few cycles to complete. */
6673         synchronize_rcu();
6674
6675         rtl8169_tx_clear(tp);
6676
6677         rtl8169_rx_clear(tp);
6678
6679         rtl_pll_power_down(tp);
6680 }
6681
6682 static int rtl8169_close(struct net_device *dev)
6683 {
6684         struct rtl8169_private *tp = netdev_priv(dev);
6685         struct pci_dev *pdev = tp->pci_dev;
6686
6687         pm_runtime_get_sync(&pdev->dev);
6688
6689         /* Update counters before going down */
6690         rtl8169_update_counters(tp);
6691
6692         rtl_lock_work(tp);
6693         /* Clear all task flags */
6694         bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6695
6696         rtl8169_down(dev);
6697         rtl_unlock_work(tp);
6698
6699         cancel_work_sync(&tp->wk.work);
6700
6701         phy_disconnect(tp->phydev);
6702
6703         pci_free_irq(pdev, 0, tp);
6704
6705         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6706                           tp->RxPhyAddr);
6707         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6708                           tp->TxPhyAddr);
6709         tp->TxDescArray = NULL;
6710         tp->RxDescArray = NULL;
6711
6712         pm_runtime_put_sync(&pdev->dev);
6713
6714         return 0;
6715 }
6716
6717 #ifdef CONFIG_NET_POLL_CONTROLLER
6718 static void rtl8169_netpoll(struct net_device *dev)
6719 {
6720         struct rtl8169_private *tp = netdev_priv(dev);
6721
6722         rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp);
6723 }
6724 #endif
6725
6726 static int rtl_open(struct net_device *dev)
6727 {
6728         struct rtl8169_private *tp = netdev_priv(dev);
6729         struct pci_dev *pdev = tp->pci_dev;
6730         int retval = -ENOMEM;
6731
6732         pm_runtime_get_sync(&pdev->dev);
6733
6734         /*
6735          * Rx and Tx descriptors needs 256 bytes alignment.
6736          * dma_alloc_coherent provides more.
6737          */
6738         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6739                                              &tp->TxPhyAddr, GFP_KERNEL);
6740         if (!tp->TxDescArray)
6741                 goto err_pm_runtime_put;
6742
6743         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6744                                              &tp->RxPhyAddr, GFP_KERNEL);
6745         if (!tp->RxDescArray)
6746                 goto err_free_tx_0;
6747
6748         retval = rtl8169_init_ring(tp);
6749         if (retval < 0)
6750                 goto err_free_rx_1;
6751
6752         rtl_request_firmware(tp);
6753
6754         retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, tp,
6755                                  dev->name);
6756         if (retval < 0)
6757                 goto err_release_fw_2;
6758
6759         retval = r8169_phy_connect(tp);
6760         if (retval)
6761                 goto err_free_irq;
6762
6763         rtl_lock_work(tp);
6764
6765         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6766
6767         napi_enable(&tp->napi);
6768
6769         rtl8169_init_phy(dev, tp);
6770
6771         rtl_pll_power_up(tp);
6772
6773         rtl_hw_start(tp);
6774
6775         if (!rtl8169_init_counter_offsets(tp))
6776                 netif_warn(tp, hw, dev, "counter reset/update failed\n");
6777
6778         phy_start(tp->phydev);
6779         netif_start_queue(dev);
6780
6781         rtl_unlock_work(tp);
6782
6783         pm_runtime_put_sync(&pdev->dev);
6784 out:
6785         return retval;
6786
6787 err_free_irq:
6788         pci_free_irq(pdev, 0, tp);
6789 err_release_fw_2:
6790         rtl_release_firmware(tp);
6791         rtl8169_rx_clear(tp);
6792 err_free_rx_1:
6793         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6794                           tp->RxPhyAddr);
6795         tp->RxDescArray = NULL;
6796 err_free_tx_0:
6797         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6798                           tp->TxPhyAddr);
6799         tp->TxDescArray = NULL;
6800 err_pm_runtime_put:
6801         pm_runtime_put_noidle(&pdev->dev);
6802         goto out;
6803 }
6804
6805 static void
6806 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
6807 {
6808         struct rtl8169_private *tp = netdev_priv(dev);
6809         struct pci_dev *pdev = tp->pci_dev;
6810         struct rtl8169_counters *counters = tp->counters;
6811         unsigned int start;
6812
6813         pm_runtime_get_noresume(&pdev->dev);
6814
6815         if (netif_running(dev) && pm_runtime_active(&pdev->dev))
6816                 rtl8169_rx_missed(dev);
6817
6818         do {
6819                 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
6820                 stats->rx_packets = tp->rx_stats.packets;
6821                 stats->rx_bytes = tp->rx_stats.bytes;
6822         } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
6823
6824         do {
6825                 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
6826                 stats->tx_packets = tp->tx_stats.packets;
6827                 stats->tx_bytes = tp->tx_stats.bytes;
6828         } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
6829
6830         stats->rx_dropped       = dev->stats.rx_dropped;
6831         stats->tx_dropped       = dev->stats.tx_dropped;
6832         stats->rx_length_errors = dev->stats.rx_length_errors;
6833         stats->rx_errors        = dev->stats.rx_errors;
6834         stats->rx_crc_errors    = dev->stats.rx_crc_errors;
6835         stats->rx_fifo_errors   = dev->stats.rx_fifo_errors;
6836         stats->rx_missed_errors = dev->stats.rx_missed_errors;
6837         stats->multicast        = dev->stats.multicast;
6838
6839         /*
6840          * Fetch additonal counter values missing in stats collected by driver
6841          * from tally counters.
6842          */
6843         if (pm_runtime_active(&pdev->dev))
6844                 rtl8169_update_counters(tp);
6845
6846         /*
6847          * Subtract values fetched during initalization.
6848          * See rtl8169_init_counter_offsets for a description why we do that.
6849          */
6850         stats->tx_errors = le64_to_cpu(counters->tx_errors) -
6851                 le64_to_cpu(tp->tc_offset.tx_errors);
6852         stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
6853                 le32_to_cpu(tp->tc_offset.tx_multi_collision);
6854         stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
6855                 le16_to_cpu(tp->tc_offset.tx_aborted);
6856
6857         pm_runtime_put_noidle(&pdev->dev);
6858 }
6859
6860 static void rtl8169_net_suspend(struct net_device *dev)
6861 {
6862         struct rtl8169_private *tp = netdev_priv(dev);
6863
6864         if (!netif_running(dev))
6865                 return;
6866
6867         phy_stop(tp->phydev);
6868         netif_device_detach(dev);
6869
6870         rtl_lock_work(tp);
6871         napi_disable(&tp->napi);
6872         /* Clear all task flags */
6873         bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6874
6875         rtl_unlock_work(tp);
6876
6877         rtl_pll_power_down(tp);
6878 }
6879
6880 #ifdef CONFIG_PM
6881
6882 static int rtl8169_suspend(struct device *device)
6883 {
6884         struct net_device *dev = dev_get_drvdata(device);
6885         struct rtl8169_private *tp = netdev_priv(dev);
6886
6887         rtl8169_net_suspend(dev);
6888         clk_disable_unprepare(tp->clk);
6889
6890         return 0;
6891 }
6892
6893 static void __rtl8169_resume(struct net_device *dev)
6894 {
6895         struct rtl8169_private *tp = netdev_priv(dev);
6896
6897         netif_device_attach(dev);
6898
6899         rtl_pll_power_up(tp);
6900         rtl8169_init_phy(dev, tp);
6901
6902         phy_start(tp->phydev);
6903
6904         rtl_lock_work(tp);
6905         napi_enable(&tp->napi);
6906         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6907         rtl_reset_work(tp);
6908         rtl_unlock_work(tp);
6909 }
6910
6911 static int rtl8169_resume(struct device *device)
6912 {
6913         struct net_device *dev = dev_get_drvdata(device);
6914         struct rtl8169_private *tp = netdev_priv(dev);
6915
6916         clk_prepare_enable(tp->clk);
6917
6918         if (netif_running(dev))
6919                 __rtl8169_resume(dev);
6920
6921         return 0;
6922 }
6923
6924 static int rtl8169_runtime_suspend(struct device *device)
6925 {
6926         struct net_device *dev = dev_get_drvdata(device);
6927         struct rtl8169_private *tp = netdev_priv(dev);
6928
6929         if (!tp->TxDescArray)
6930                 return 0;
6931
6932         rtl_lock_work(tp);
6933         __rtl8169_set_wol(tp, WAKE_ANY);
6934         rtl_unlock_work(tp);
6935
6936         rtl8169_net_suspend(dev);
6937
6938         /* Update counters before going runtime suspend */
6939         rtl8169_rx_missed(dev);
6940         rtl8169_update_counters(tp);
6941
6942         return 0;
6943 }
6944
6945 static int rtl8169_runtime_resume(struct device *device)
6946 {
6947         struct net_device *dev = dev_get_drvdata(device);
6948         struct rtl8169_private *tp = netdev_priv(dev);
6949         rtl_rar_set(tp, dev->dev_addr);
6950
6951         if (!tp->TxDescArray)
6952                 return 0;
6953
6954         rtl_lock_work(tp);
6955         __rtl8169_set_wol(tp, tp->saved_wolopts);
6956         rtl_unlock_work(tp);
6957
6958         __rtl8169_resume(dev);
6959
6960         return 0;
6961 }
6962
6963 static int rtl8169_runtime_idle(struct device *device)
6964 {
6965         struct net_device *dev = dev_get_drvdata(device);
6966
6967         if (!netif_running(dev) || !netif_carrier_ok(dev))
6968                 pm_schedule_suspend(device, 10000);
6969
6970         return -EBUSY;
6971 }
6972
6973 static const struct dev_pm_ops rtl8169_pm_ops = {
6974         .suspend                = rtl8169_suspend,
6975         .resume                 = rtl8169_resume,
6976         .freeze                 = rtl8169_suspend,
6977         .thaw                   = rtl8169_resume,
6978         .poweroff               = rtl8169_suspend,
6979         .restore                = rtl8169_resume,
6980         .runtime_suspend        = rtl8169_runtime_suspend,
6981         .runtime_resume         = rtl8169_runtime_resume,
6982         .runtime_idle           = rtl8169_runtime_idle,
6983 };
6984
6985 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
6986
6987 #else /* !CONFIG_PM */
6988
6989 #define RTL8169_PM_OPS  NULL
6990
6991 #endif /* !CONFIG_PM */
6992
6993 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6994 {
6995         /* WoL fails with 8168b when the receiver is disabled. */
6996         switch (tp->mac_version) {
6997         case RTL_GIGA_MAC_VER_11:
6998         case RTL_GIGA_MAC_VER_12:
6999         case RTL_GIGA_MAC_VER_17:
7000                 pci_clear_master(tp->pci_dev);
7001
7002                 RTL_W8(tp, ChipCmd, CmdRxEnb);
7003                 /* PCI commit */
7004                 RTL_R8(tp, ChipCmd);
7005                 break;
7006         default:
7007                 break;
7008         }
7009 }
7010
7011 static void rtl_shutdown(struct pci_dev *pdev)
7012 {
7013         struct net_device *dev = pci_get_drvdata(pdev);
7014         struct rtl8169_private *tp = netdev_priv(dev);
7015
7016         rtl8169_net_suspend(dev);
7017
7018         /* Restore original MAC address */
7019         rtl_rar_set(tp, dev->perm_addr);
7020
7021         rtl8169_hw_reset(tp);
7022
7023         if (system_state == SYSTEM_POWER_OFF) {
7024                 if (tp->saved_wolopts) {
7025                         rtl_wol_suspend_quirk(tp);
7026                         rtl_wol_shutdown_quirk(tp);
7027                 }
7028
7029                 pci_wake_from_d3(pdev, true);
7030                 pci_set_power_state(pdev, PCI_D3hot);
7031         }
7032 }
7033
7034 static void rtl_remove_one(struct pci_dev *pdev)
7035 {
7036         struct net_device *dev = pci_get_drvdata(pdev);
7037         struct rtl8169_private *tp = netdev_priv(dev);
7038
7039         if (r8168_check_dash(tp))
7040                 rtl8168_driver_stop(tp);
7041
7042         netif_napi_del(&tp->napi);
7043
7044         unregister_netdev(dev);
7045         mdiobus_unregister(tp->phydev->mdio.bus);
7046
7047         rtl_release_firmware(tp);
7048
7049         if (pci_dev_run_wake(pdev))
7050                 pm_runtime_get_noresume(&pdev->dev);
7051
7052         /* restore original MAC address */
7053         rtl_rar_set(tp, dev->perm_addr);
7054 }
7055
7056 static const struct net_device_ops rtl_netdev_ops = {
7057         .ndo_open               = rtl_open,
7058         .ndo_stop               = rtl8169_close,
7059         .ndo_get_stats64        = rtl8169_get_stats64,
7060         .ndo_start_xmit         = rtl8169_start_xmit,
7061         .ndo_tx_timeout         = rtl8169_tx_timeout,
7062         .ndo_validate_addr      = eth_validate_addr,
7063         .ndo_change_mtu         = rtl8169_change_mtu,
7064         .ndo_fix_features       = rtl8169_fix_features,
7065         .ndo_set_features       = rtl8169_set_features,
7066         .ndo_set_mac_address    = rtl_set_mac_address,
7067         .ndo_do_ioctl           = rtl8169_ioctl,
7068         .ndo_set_rx_mode        = rtl_set_rx_mode,
7069 #ifdef CONFIG_NET_POLL_CONTROLLER
7070         .ndo_poll_controller    = rtl8169_netpoll,
7071 #endif
7072
7073 };
7074
7075 static const struct rtl_cfg_info {
7076         void (*hw_start)(struct rtl8169_private *tp);
7077         u16 irq_mask;
7078         unsigned int has_gmii:1;
7079         const struct rtl_coalesce_info *coalesce_info;
7080 } rtl_cfg_infos [] = {
7081         [RTL_CFG_0] = {
7082                 .hw_start       = rtl_hw_start_8169,
7083                 .irq_mask       = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
7084                 .has_gmii       = 1,
7085                 .coalesce_info  = rtl_coalesce_info_8169,
7086         },
7087         [RTL_CFG_1] = {
7088                 .hw_start       = rtl_hw_start_8168,
7089                 .irq_mask       = LinkChg | RxOverflow,
7090                 .has_gmii       = 1,
7091                 .coalesce_info  = rtl_coalesce_info_8168_8136,
7092         },
7093         [RTL_CFG_2] = {
7094                 .hw_start       = rtl_hw_start_8101,
7095                 .irq_mask       = LinkChg | RxOverflow | RxFIFOOver,
7096                 .coalesce_info  = rtl_coalesce_info_8168_8136,
7097         }
7098 };
7099
7100 static int rtl_alloc_irq(struct rtl8169_private *tp)
7101 {
7102         unsigned int flags;
7103
7104         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
7105                 rtl_unlock_config_regs(tp);
7106                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
7107                 rtl_lock_config_regs(tp);
7108                 flags = PCI_IRQ_LEGACY;
7109         } else {
7110                 flags = PCI_IRQ_ALL_TYPES;
7111         }
7112
7113         return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
7114 }
7115
7116 static void rtl_read_mac_address(struct rtl8169_private *tp,
7117                                  u8 mac_addr[ETH_ALEN])
7118 {
7119         u32 value;
7120
7121         /* Get MAC address */
7122         switch (tp->mac_version) {
7123         case RTL_GIGA_MAC_VER_35 ... RTL_GIGA_MAC_VER_38:
7124         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
7125                 value = rtl_eri_read(tp, 0xe0, ERIAR_EXGMAC);
7126                 mac_addr[0] = (value >>  0) & 0xff;
7127                 mac_addr[1] = (value >>  8) & 0xff;
7128                 mac_addr[2] = (value >> 16) & 0xff;
7129                 mac_addr[3] = (value >> 24) & 0xff;
7130
7131                 value = rtl_eri_read(tp, 0xe4, ERIAR_EXGMAC);
7132                 mac_addr[4] = (value >>  0) & 0xff;
7133                 mac_addr[5] = (value >>  8) & 0xff;
7134                 break;
7135         default:
7136                 break;
7137         }
7138 }
7139
7140 DECLARE_RTL_COND(rtl_link_list_ready_cond)
7141 {
7142         return RTL_R8(tp, MCU) & LINK_LIST_RDY;
7143 }
7144
7145 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
7146 {
7147         return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
7148 }
7149
7150 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
7151 {
7152         struct rtl8169_private *tp = mii_bus->priv;
7153
7154         if (phyaddr > 0)
7155                 return -ENODEV;
7156
7157         return rtl_readphy(tp, phyreg);
7158 }
7159
7160 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
7161                                 int phyreg, u16 val)
7162 {
7163         struct rtl8169_private *tp = mii_bus->priv;
7164
7165         if (phyaddr > 0)
7166                 return -ENODEV;
7167
7168         rtl_writephy(tp, phyreg, val);
7169
7170         return 0;
7171 }
7172
7173 static int r8169_mdio_register(struct rtl8169_private *tp)
7174 {
7175         struct pci_dev *pdev = tp->pci_dev;
7176         struct mii_bus *new_bus;
7177         int ret;
7178
7179         new_bus = devm_mdiobus_alloc(&pdev->dev);
7180         if (!new_bus)
7181                 return -ENOMEM;
7182
7183         new_bus->name = "r8169";
7184         new_bus->priv = tp;
7185         new_bus->parent = &pdev->dev;
7186         new_bus->irq[0] = PHY_IGNORE_INTERRUPT;
7187         snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x",
7188                  PCI_DEVID(pdev->bus->number, pdev->devfn));
7189
7190         new_bus->read = r8169_mdio_read_reg;
7191         new_bus->write = r8169_mdio_write_reg;
7192
7193         ret = mdiobus_register(new_bus);
7194         if (ret)
7195                 return ret;
7196
7197         tp->phydev = mdiobus_get_phy(new_bus, 0);
7198         if (!tp->phydev) {
7199                 mdiobus_unregister(new_bus);
7200                 return -ENODEV;
7201         }
7202
7203         /* PHY will be woken up in rtl_open() */
7204         phy_suspend(tp->phydev);
7205
7206         return 0;
7207 }
7208
7209 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
7210 {
7211         u32 data;
7212
7213         tp->ocp_base = OCP_STD_PHY_BASE;
7214
7215         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
7216
7217         if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
7218                 return;
7219
7220         if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
7221                 return;
7222
7223         RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
7224         msleep(1);
7225         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
7226
7227         data = r8168_mac_ocp_read(tp, 0xe8de);
7228         data &= ~(1 << 14);
7229         r8168_mac_ocp_write(tp, 0xe8de, data);
7230
7231         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7232                 return;
7233
7234         data = r8168_mac_ocp_read(tp, 0xe8de);
7235         data |= (1 << 15);
7236         r8168_mac_ocp_write(tp, 0xe8de, data);
7237
7238         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7239                 return;
7240 }
7241
7242 static void rtl_hw_init_8168ep(struct rtl8169_private *tp)
7243 {
7244         rtl8168ep_stop_cmac(tp);
7245         rtl_hw_init_8168g(tp);
7246 }
7247
7248 static void rtl_hw_initialize(struct rtl8169_private *tp)
7249 {
7250         switch (tp->mac_version) {
7251         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
7252                 rtl_hw_init_8168g(tp);
7253                 break;
7254         case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_51:
7255                 rtl_hw_init_8168ep(tp);
7256                 break;
7257         default:
7258                 break;
7259         }
7260 }
7261
7262 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */
7263 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
7264 {
7265         switch (tp->mac_version) {
7266         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
7267         case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
7268                 return false;
7269         default:
7270                 return true;
7271         }
7272 }
7273
7274 static int rtl_jumbo_max(struct rtl8169_private *tp)
7275 {
7276         /* Non-GBit versions don't support jumbo frames */
7277         if (!tp->supports_gmii)
7278                 return JUMBO_1K;
7279
7280         switch (tp->mac_version) {
7281         /* RTL8169 */
7282         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
7283                 return JUMBO_7K;
7284         /* RTL8168b */
7285         case RTL_GIGA_MAC_VER_11:
7286         case RTL_GIGA_MAC_VER_12:
7287         case RTL_GIGA_MAC_VER_17:
7288                 return JUMBO_4K;
7289         /* RTL8168c */
7290         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
7291                 return JUMBO_6K;
7292         default:
7293                 return JUMBO_9K;
7294         }
7295 }
7296
7297 static void rtl_disable_clk(void *data)
7298 {
7299         clk_disable_unprepare(data);
7300 }
7301
7302 static int rtl_get_ether_clk(struct rtl8169_private *tp)
7303 {
7304         struct device *d = tp_to_dev(tp);
7305         struct clk *clk;
7306         int rc;
7307
7308         clk = devm_clk_get(d, "ether_clk");
7309         if (IS_ERR(clk)) {
7310                 rc = PTR_ERR(clk);
7311                 if (rc == -ENOENT)
7312                         /* clk-core allows NULL (for suspend / resume) */
7313                         rc = 0;
7314                 else if (rc != -EPROBE_DEFER)
7315                         dev_err(d, "failed to get clk: %d\n", rc);
7316         } else {
7317                 tp->clk = clk;
7318                 rc = clk_prepare_enable(clk);
7319                 if (rc)
7320                         dev_err(d, "failed to enable clk: %d\n", rc);
7321                 else
7322                         rc = devm_add_action_or_reset(d, rtl_disable_clk, clk);
7323         }
7324
7325         return rc;
7326 }
7327
7328 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7329 {
7330         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
7331         /* align to u16 for is_valid_ether_addr() */
7332         u8 mac_addr[ETH_ALEN] __aligned(2) = {};
7333         struct rtl8169_private *tp;
7334         struct net_device *dev;
7335         int chipset, region, i;
7336         int jumbo_max, rc;
7337
7338         dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
7339         if (!dev)
7340                 return -ENOMEM;
7341
7342         SET_NETDEV_DEV(dev, &pdev->dev);
7343         dev->netdev_ops = &rtl_netdev_ops;
7344         tp = netdev_priv(dev);
7345         tp->dev = dev;
7346         tp->pci_dev = pdev;
7347         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
7348         tp->supports_gmii = cfg->has_gmii;
7349
7350         /* Get the *optional* external "ether_clk" used on some boards */
7351         rc = rtl_get_ether_clk(tp);
7352         if (rc)
7353                 return rc;
7354
7355         /* enable device (incl. PCI PM wakeup and hotplug setup) */
7356         rc = pcim_enable_device(pdev);
7357         if (rc < 0) {
7358                 dev_err(&pdev->dev, "enable failure\n");
7359                 return rc;
7360         }
7361
7362         if (pcim_set_mwi(pdev) < 0)
7363                 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
7364
7365         /* use first MMIO region */
7366         region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
7367         if (region < 0) {
7368                 dev_err(&pdev->dev, "no MMIO resource found\n");
7369                 return -ENODEV;
7370         }
7371
7372         /* check for weird/broken PCI region reporting */
7373         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
7374                 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
7375                 return -ENODEV;
7376         }
7377
7378         rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME);
7379         if (rc < 0) {
7380                 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
7381                 return rc;
7382         }
7383
7384         tp->mmio_addr = pcim_iomap_table(pdev)[region];
7385
7386         /* Identify chip attached to board */
7387         rtl8169_get_mac_version(tp);
7388         if (tp->mac_version == RTL_GIGA_MAC_NONE)
7389                 return -ENODEV;
7390
7391         if (rtl_tbi_enabled(tp)) {
7392                 dev_err(&pdev->dev, "TBI fiber mode not supported\n");
7393                 return -ENODEV;
7394         }
7395
7396         tp->cp_cmd = RTL_R16(tp, CPlusCmd);
7397
7398         if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 &&
7399             !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
7400                 dev->features |= NETIF_F_HIGHDMA;
7401         } else {
7402                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
7403                 if (rc < 0) {
7404                         dev_err(&pdev->dev, "DMA configuration failed\n");
7405                         return rc;
7406                 }
7407         }
7408
7409         rtl_init_rxcfg(tp);
7410
7411         rtl8169_irq_mask_and_ack(tp);
7412
7413         rtl_hw_initialize(tp);
7414
7415         rtl_hw_reset(tp);
7416
7417         pci_set_master(pdev);
7418
7419         rtl_init_mdio_ops(tp);
7420         rtl_init_jumbo_ops(tp);
7421
7422         chipset = tp->mac_version;
7423
7424         rc = rtl_alloc_irq(tp);
7425         if (rc < 0) {
7426                 dev_err(&pdev->dev, "Can't allocate interrupt\n");
7427                 return rc;
7428         }
7429
7430         mutex_init(&tp->wk.mutex);
7431         INIT_WORK(&tp->wk.work, rtl_task);
7432         u64_stats_init(&tp->rx_stats.syncp);
7433         u64_stats_init(&tp->tx_stats.syncp);
7434
7435         /* get MAC address */
7436         rc = eth_platform_get_mac_address(&pdev->dev, mac_addr);
7437         if (rc)
7438                 rtl_read_mac_address(tp, mac_addr);
7439
7440         if (is_valid_ether_addr(mac_addr))
7441                 rtl_rar_set(tp, mac_addr);
7442
7443         for (i = 0; i < ETH_ALEN; i++)
7444                 dev->dev_addr[i] = RTL_R8(tp, MAC0 + i);
7445
7446         dev->ethtool_ops = &rtl8169_ethtool_ops;
7447
7448         netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT);
7449
7450         /* don't enable SG, IP_CSUM and TSO by default - it might not work
7451          * properly for all devices */
7452         dev->features |= NETIF_F_RXCSUM |
7453                 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
7454
7455         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7456                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
7457                 NETIF_F_HW_VLAN_CTAG_RX;
7458         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7459                 NETIF_F_HIGHDMA;
7460         dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
7461
7462         tp->cp_cmd |= RxChkSum | RxVlan;
7463
7464         /*
7465          * Pretend we are using VLANs; This bypasses a nasty bug where
7466          * Interrupts stop flowing on high load on 8110SCd controllers.
7467          */
7468         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
7469                 /* Disallow toggling */
7470                 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
7471
7472         if (rtl_chip_supports_csum_v2(tp)) {
7473                 tp->tso_csum = rtl8169_tso_csum_v2;
7474                 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
7475         } else {
7476                 tp->tso_csum = rtl8169_tso_csum_v1;
7477         }
7478
7479         dev->hw_features |= NETIF_F_RXALL;
7480         dev->hw_features |= NETIF_F_RXFCS;
7481
7482         /* MTU range: 60 - hw-specific max */
7483         dev->min_mtu = ETH_ZLEN;
7484         jumbo_max = rtl_jumbo_max(tp);
7485         dev->max_mtu = jumbo_max;
7486
7487         tp->hw_start = cfg->hw_start;
7488         tp->irq_mask = RTL_EVENT_NAPI | cfg->irq_mask;
7489         tp->coalesce_info = cfg->coalesce_info;
7490
7491         tp->fw_name = rtl_chip_infos[chipset].fw_name;
7492
7493         tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
7494                                             &tp->counters_phys_addr,
7495                                             GFP_KERNEL);
7496         if (!tp->counters)
7497                 return -ENOMEM;
7498
7499         pci_set_drvdata(pdev, dev);
7500
7501         rc = r8169_mdio_register(tp);
7502         if (rc)
7503                 return rc;
7504
7505         /* chip gets powered up in rtl_open() */
7506         rtl_pll_power_down(tp);
7507
7508         rc = register_netdev(dev);
7509         if (rc)
7510                 goto err_mdio_unregister;
7511
7512         netif_info(tp, probe, dev, "%s, %pM, XID %03x, IRQ %d\n",
7513                    rtl_chip_infos[chipset].name, dev->dev_addr,
7514                    (RTL_R32(tp, TxConfig) >> 20) & 0xfcf,
7515                    pci_irq_vector(pdev, 0));
7516
7517         if (jumbo_max > JUMBO_1K)
7518                 netif_info(tp, probe, dev,
7519                            "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
7520                            jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?
7521                            "ok" : "ko");
7522
7523         if (r8168_check_dash(tp))
7524                 rtl8168_driver_start(tp);
7525
7526         if (pci_dev_run_wake(pdev))
7527                 pm_runtime_put_sync(&pdev->dev);
7528
7529         return 0;
7530
7531 err_mdio_unregister:
7532         mdiobus_unregister(tp->phydev->mdio.bus);
7533         return rc;
7534 }
7535
7536 static struct pci_driver rtl8169_pci_driver = {
7537         .name           = MODULENAME,
7538         .id_table       = rtl8169_pci_tbl,
7539         .probe          = rtl_init_one,
7540         .remove         = rtl_remove_one,
7541         .shutdown       = rtl_shutdown,
7542         .driver.pm      = RTL8169_PM_OPS,
7543 };
7544
7545 module_pci_driver(rtl8169_pci_driver);