drivers/net/ethernet/realtek/r8169.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   4  *
   5  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   6  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   7  * Copyright (c) a lot of people too. Please respect their work.
   8  *
   9  * See MAINTAINERS file for support contact information.
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/moduleparam.h>
  14 #include <linux/pci.h>
  15 #include <linux/netdevice.h>
  16 #include <linux/etherdevice.h>
  17 #include <linux/clk.h>
  18 #include <linux/delay.h>
  19 #include <linux/ethtool.h>
  20 #include <linux/phy.h>
  21 #include <linux/if_vlan.h>
  22 #include <linux/crc32.h>
  23 #include <linux/in.h>
  24 #include <linux/io.h>
  25 #include <linux/ip.h>
  26 #include <linux/tcp.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/dma-mapping.h>
  29 #include <linux/pm_runtime.h>
  30 #include <linux/firmware.h>
  31 #include <linux/prefetch.h>
  32 #include <linux/pci-aspm.h>
  33 #include <linux/ipv6.h>
  34 #include <net/ip6_checksum.h>
  35
  36 #define MODULENAME "r8169"
  37
  38 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  39 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  40 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  41 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  42 #define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
  43 #define FIRMWARE_8168F_1        "rtl_nic/rtl8168f-1.fw"
  44 #define FIRMWARE_8168F_2        "rtl_nic/rtl8168f-2.fw"
  45 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  46 #define FIRMWARE_8402_1         "rtl_nic/rtl8402-1.fw"
  47 #define FIRMWARE_8411_1         "rtl_nic/rtl8411-1.fw"
  48 #define FIRMWARE_8411_2         "rtl_nic/rtl8411-2.fw"
  49 #define FIRMWARE_8106E_1        "rtl_nic/rtl8106e-1.fw"
  50 #define FIRMWARE_8106E_2        "rtl_nic/rtl8106e-2.fw"
  51 #define FIRMWARE_8168G_2        "rtl_nic/rtl8168g-2.fw"
  52 #define FIRMWARE_8168G_3        "rtl_nic/rtl8168g-3.fw"
  53 #define FIRMWARE_8168H_1        "rtl_nic/rtl8168h-1.fw"
  54 #define FIRMWARE_8168H_2        "rtl_nic/rtl8168h-2.fw"
  55 #define FIRMWARE_8107E_1        "rtl_nic/rtl8107e-1.fw"
  56 #define FIRMWARE_8107E_2        "rtl_nic/rtl8107e-2.fw"
  57
  58 #define R8169_MSG_DEFAULT \
  59         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  60
  61 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  62    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  63 static const int multicast_filter_limit = 32;
  64
  65 #define TX_DMA_BURST    7       /* Maximum PCI burst, '7' is unlimited */
  66 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  67
  68 #define R8169_REGS_SIZE         256
  69 #define R8169_RX_BUF_SIZE       (SZ_16K - 1)
  70 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  71 #define NUM_RX_DESC     256U    /* Number of Rx descriptor registers */
  72 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  73 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  74
  75 /* write/read MMIO register */
  76 #define RTL_W8(tp, reg, val8)   writeb((val8), tp->mmio_addr + (reg))
  77 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
  78 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
  79 #define RTL_R8(tp, reg)         readb(tp->mmio_addr + (reg))
  80 #define RTL_R16(tp, reg)                readw(tp->mmio_addr + (reg))
  81 #define RTL_R32(tp, reg)                readl(tp->mmio_addr + (reg))
  82
  83 enum mac_version {
  84         /* support for ancient RTL_GIGA_MAC_VER_01 has been removed */
  85         RTL_GIGA_MAC_VER_02,
  86         RTL_GIGA_MAC_VER_03,
  87         RTL_GIGA_MAC_VER_04,
  88         RTL_GIGA_MAC_VER_05,
  89         RTL_GIGA_MAC_VER_06,
  90         RTL_GIGA_MAC_VER_07,
  91         RTL_GIGA_MAC_VER_08,
  92         RTL_GIGA_MAC_VER_09,
  93         RTL_GIGA_MAC_VER_10,
  94         RTL_GIGA_MAC_VER_11,
  95         RTL_GIGA_MAC_VER_12,
  96         RTL_GIGA_MAC_VER_13,
  97         RTL_GIGA_MAC_VER_14,
  98         RTL_GIGA_MAC_VER_15,
  99         RTL_GIGA_MAC_VER_16,
 100         RTL_GIGA_MAC_VER_17,
 101         RTL_GIGA_MAC_VER_18,
 102         RTL_GIGA_MAC_VER_19,
 103         RTL_GIGA_MAC_VER_20,
 104         RTL_GIGA_MAC_VER_21,
 105         RTL_GIGA_MAC_VER_22,
 106         RTL_GIGA_MAC_VER_23,
 107         RTL_GIGA_MAC_VER_24,
 108         RTL_GIGA_MAC_VER_25,
 109         RTL_GIGA_MAC_VER_26,
 110         RTL_GIGA_MAC_VER_27,
 111         RTL_GIGA_MAC_VER_28,
 112         RTL_GIGA_MAC_VER_29,
 113         RTL_GIGA_MAC_VER_30,
 114         RTL_GIGA_MAC_VER_31,
 115         RTL_GIGA_MAC_VER_32,
 116         RTL_GIGA_MAC_VER_33,
 117         RTL_GIGA_MAC_VER_34,
 118         RTL_GIGA_MAC_VER_35,
 119         RTL_GIGA_MAC_VER_36,
 120         RTL_GIGA_MAC_VER_37,
 121         RTL_GIGA_MAC_VER_38,
 122         RTL_GIGA_MAC_VER_39,
 123         RTL_GIGA_MAC_VER_40,
 124         RTL_GIGA_MAC_VER_41,
 125         RTL_GIGA_MAC_VER_42,
 126         RTL_GIGA_MAC_VER_43,
 127         RTL_GIGA_MAC_VER_44,
 128         RTL_GIGA_MAC_VER_45,
 129         RTL_GIGA_MAC_VER_46,
 130         RTL_GIGA_MAC_VER_47,
 131         RTL_GIGA_MAC_VER_48,
 132         RTL_GIGA_MAC_VER_49,
 133         RTL_GIGA_MAC_VER_50,
 134         RTL_GIGA_MAC_VER_51,
 135         RTL_GIGA_MAC_NONE
 136 };
 137
 138 #define JUMBO_1K        ETH_DATA_LEN
 139 #define JUMBO_4K        (4*1024 - ETH_HLEN - 2)
 140 #define JUMBO_6K        (6*1024 - ETH_HLEN - 2)
 141 #define JUMBO_7K        (7*1024 - ETH_HLEN - 2)
 142 #define JUMBO_9K        (9*1024 - ETH_HLEN - 2)
 143
 144 static const struct {
 145         const char *name;
 146         const char *fw_name;
 147 } rtl_chip_infos[] = {
 148         /* PCI devices. */
 149         [RTL_GIGA_MAC_VER_02] = {"RTL8169s"                             },
 150         [RTL_GIGA_MAC_VER_03] = {"RTL8110s"                             },
 151         [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb"                     },
 152         [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc"                     },
 153         [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc"                     },
 154         /* PCI-E devices. */
 155         [RTL_GIGA_MAC_VER_07] = {"RTL8102e"                             },
 156         [RTL_GIGA_MAC_VER_08] = {"RTL8102e"                             },
 157         [RTL_GIGA_MAC_VER_09] = {"RTL8102e"                             },
 158         [RTL_GIGA_MAC_VER_10] = {"RTL8101e"                             },
 159         [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b"                       },
 160         [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b"                       },
 161         [RTL_GIGA_MAC_VER_13] = {"RTL8101e"                             },
 162         [RTL_GIGA_MAC_VER_14] = {"RTL8100e"                             },
 163         [RTL_GIGA_MAC_VER_15] = {"RTL8100e"                             },
 164         [RTL_GIGA_MAC_VER_16] = {"RTL8101e"                             },
 165         [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b"                       },
 166         [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp"                     },
 167         [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c"                       },
 168         [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c"                       },
 169         [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c"                       },
 170         [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c"                       },
 171         [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp"                     },
 172         [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp"                     },
 173         [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d",      FIRMWARE_8168D_1},
 174         [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d",      FIRMWARE_8168D_2},
 175         [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp"                     },
 176         [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp"                     },
 177         [RTL_GIGA_MAC_VER_29] = {"RTL8105e",            FIRMWARE_8105E_1},
 178         [RTL_GIGA_MAC_VER_30] = {"RTL8105e",            FIRMWARE_8105E_1},
 179         [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp"                     },
 180         [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e",      FIRMWARE_8168E_1},
 181         [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e",      FIRMWARE_8168E_2},
 182         [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl",  FIRMWARE_8168E_3},
 183         [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f",      FIRMWARE_8168F_1},
 184         [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f",      FIRMWARE_8168F_2},
 185         [RTL_GIGA_MAC_VER_37] = {"RTL8402",             FIRMWARE_8402_1 },
 186         [RTL_GIGA_MAC_VER_38] = {"RTL8411",             FIRMWARE_8411_1 },
 187         [RTL_GIGA_MAC_VER_39] = {"RTL8106e",            FIRMWARE_8106E_1},
 188         [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g",      FIRMWARE_8168G_2},
 189         [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g"                       },
 190         [RTL_GIGA_MAC_VER_42] = {"RTL8168g/8111g",      FIRMWARE_8168G_3},
 191         [RTL_GIGA_MAC_VER_43] = {"RTL8106e",            FIRMWARE_8106E_2},
 192         [RTL_GIGA_MAC_VER_44] = {"RTL8411",             FIRMWARE_8411_2 },
 193         [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h",      FIRMWARE_8168H_1},
 194         [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h",      FIRMWARE_8168H_2},
 195         [RTL_GIGA_MAC_VER_47] = {"RTL8107e",            FIRMWARE_8107E_1},
 196         [RTL_GIGA_MAC_VER_48] = {"RTL8107e",            FIRMWARE_8107E_2},
 197         [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep"                     },
 198         [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep"                     },
 199         [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep"                     },
 200 };
 201
 202 enum cfg_version {
 203         RTL_CFG_0 = 0x00,
 204         RTL_CFG_1,
 205         RTL_CFG_2
 206 };
 207
 208 static const struct pci_device_id rtl8169_pci_tbl[] = {
 209         { PCI_VDEVICE(REALTEK,  0x2502), RTL_CFG_1 },
 210         { PCI_VDEVICE(REALTEK,  0x2600), RTL_CFG_1 },
 211         { PCI_VDEVICE(REALTEK,  0x8129), RTL_CFG_0 },
 212         { PCI_VDEVICE(REALTEK,  0x8136), RTL_CFG_2 },
 213         { PCI_VDEVICE(REALTEK,  0x8161), RTL_CFG_1 },
 214         { PCI_VDEVICE(REALTEK,  0x8167), RTL_CFG_0 },
 215         { PCI_VDEVICE(REALTEK,  0x8168), RTL_CFG_1 },
 216         { PCI_VDEVICE(NCUBE,    0x8168), RTL_CFG_1 },
 217         { PCI_VDEVICE(REALTEK,  0x8169), RTL_CFG_0 },
 218         { PCI_VENDOR_ID_DLINK,  0x4300,
 219                 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 },
 220         { PCI_VDEVICE(DLINK,    0x4300), RTL_CFG_0 },
 221         { PCI_VDEVICE(DLINK,    0x4302), RTL_CFG_0 },
 222         { PCI_VDEVICE(AT,       0xc107), RTL_CFG_0 },
 223         { PCI_VDEVICE(USR,      0x0116), RTL_CFG_0 },
 224         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 225                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 226         { 0x0001,                               0x8168,
 227                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 228         {}
 229 };
 230
 231 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 232
 233 static struct {
 234         u32 msg_enable;
 235 } debug = { -1 };
 236
 237 enum rtl_registers {
 238         MAC0            = 0,    /* Ethernet hardware address. */
 239         MAC4            = 4,
 240         MAR0            = 8,    /* Multicast filter. */
 241         CounterAddrLow          = 0x10,
 242         CounterAddrHigh         = 0x14,
 243         TxDescStartAddrLow      = 0x20,
 244         TxDescStartAddrHigh     = 0x24,
 245         TxHDescStartAddrLow     = 0x28,
 246         TxHDescStartAddrHigh    = 0x2c,
 247         FLASH           = 0x30,
 248         ERSR            = 0x36,
 249         ChipCmd         = 0x37,
 250         TxPoll          = 0x38,
 251         IntrMask        = 0x3c,
 252         IntrStatus      = 0x3e,
 253
 254         TxConfig        = 0x40,
 255 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 256 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 257
 258         RxConfig        = 0x44,
 259 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 260 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 261 #define RXCFG_FIFO_SHIFT                13
 262                                         /* No threshold before first PCI xfer */
 263 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 264 #define RX_EARLY_OFF                    (1 << 11)
 265 #define RXCFG_DMA_SHIFT                 8
 266                                         /* Unlimited maximum PCI burst. */
 267 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 268
 269         RxMissed        = 0x4c,
 270         Cfg9346         = 0x50,
 271         Config0         = 0x51,
 272         Config1         = 0x52,
 273         Config2         = 0x53,
 274 #define PME_SIGNAL                      (1 << 5)        /* 8168c and later */
 275
 276         Config3         = 0x54,
 277         Config4         = 0x55,
 278         Config5         = 0x56,
 279         MultiIntr       = 0x5c,
 280         PHYAR           = 0x60,
 281         PHYstatus       = 0x6c,
 282         RxMaxSize       = 0xda,
 283         CPlusCmd        = 0xe0,
 284         IntrMitigate    = 0xe2,
 285
 286 #define RTL_COALESCE_MASK       0x0f
 287 #define RTL_COALESCE_SHIFT      4
 288 #define RTL_COALESCE_T_MAX      (RTL_COALESCE_MASK)
 289 #define RTL_COALESCE_FRAME_MAX  (RTL_COALESCE_MASK << 2)
 290
 291         RxDescAddrLow   = 0xe4,
 292         RxDescAddrHigh  = 0xe8,
 293         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 294
 295 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 296
 297         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 298
 299 #define TxPacketMax     (8064 >> 7)
 300 #define EarlySize       0x27
 301
 302         FuncEvent       = 0xf0,
 303         FuncEventMask   = 0xf4,
 304         FuncPresetState = 0xf8,
 305         IBCR0           = 0xf8,
 306         IBCR2           = 0xf9,
 307         IBIMR0          = 0xfa,
 308         IBISR0          = 0xfb,
 309         FuncForceEvent  = 0xfc,
 310 };
 311
 312 enum rtl8168_8101_registers {
 313         CSIDR                   = 0x64,
 314         CSIAR                   = 0x68,
 315 #define CSIAR_FLAG                      0x80000000
 316 #define CSIAR_WRITE_CMD                 0x80000000
 317 #define CSIAR_BYTE_ENABLE               0x0000f000
 318 #define CSIAR_ADDR_MASK                 0x00000fff
 319         PMCH                    = 0x6f,
 320         EPHYAR                  = 0x80,
 321 #define EPHYAR_FLAG                     0x80000000
 322 #define EPHYAR_WRITE_CMD                0x80000000
 323 #define EPHYAR_REG_MASK                 0x1f
 324 #define EPHYAR_REG_SHIFT                16
 325 #define EPHYAR_DATA_MASK                0xffff
 326         DLLPR                   = 0xd0,
 327 #define PFM_EN                          (1 << 6)
 328 #define TX_10M_PS_EN                    (1 << 7)
 329         DBG_REG                 = 0xd1,
 330 #define FIX_NAK_1                       (1 << 4)
 331 #define FIX_NAK_2                       (1 << 3)
 332         TWSI                    = 0xd2,
 333         MCU                     = 0xd3,
 334 #define NOW_IS_OOB                      (1 << 7)
 335 #define TX_EMPTY                        (1 << 5)
 336 #define RX_EMPTY                        (1 << 4)
 337 #define RXTX_EMPTY                      (TX_EMPTY | RX_EMPTY)
 338 #define EN_NDP                          (1 << 3)
 339 #define EN_OOB_RESET                    (1 << 2)
 340 #define LINK_LIST_RDY                   (1 << 1)
 341         EFUSEAR                 = 0xdc,
 342 #define EFUSEAR_FLAG                    0x80000000
 343 #define EFUSEAR_WRITE_CMD               0x80000000
 344 #define EFUSEAR_READ_CMD                0x00000000
 345 #define EFUSEAR_REG_MASK                0x03ff
 346 #define EFUSEAR_REG_SHIFT               8
 347 #define EFUSEAR_DATA_MASK               0xff
 348         MISC_1                  = 0xf2,
 349 #define PFM_D3COLD_EN                   (1 << 6)
 350 };
 351
 352 enum rtl8168_registers {
 353         LED_FREQ                = 0x1a,
 354         EEE_LED                 = 0x1b,
 355         ERIDR                   = 0x70,
 356         ERIAR                   = 0x74,
 357 #define ERIAR_FLAG                      0x80000000
 358 #define ERIAR_WRITE_CMD                 0x80000000
 359 #define ERIAR_READ_CMD                  0x00000000
 360 #define ERIAR_ADDR_BYTE_ALIGN           4
 361 #define ERIAR_TYPE_SHIFT                16
 362 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 363 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 364 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 365 #define ERIAR_OOB                       (0x02 << ERIAR_TYPE_SHIFT)
 366 #define ERIAR_MASK_SHIFT                12
 367 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 368 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 369 #define ERIAR_MASK_0100                 (0x4 << ERIAR_MASK_SHIFT)
 370 #define ERIAR_MASK_0101                 (0x5 << ERIAR_MASK_SHIFT)
 371 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 372         EPHY_RXER_NUM           = 0x7c,
 373         OCPDR                   = 0xb0, /* OCP GPHY access */
 374 #define OCPDR_WRITE_CMD                 0x80000000
 375 #define OCPDR_READ_CMD                  0x00000000
 376 #define OCPDR_REG_MASK                  0x7f
 377 #define OCPDR_GPHY_REG_SHIFT            16
 378 #define OCPDR_DATA_MASK                 0xffff
 379         OCPAR                   = 0xb4,
 380 #define OCPAR_FLAG                      0x80000000
 381 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 382 #define OCPAR_GPHY_READ_CMD             0x0000f060
 383         GPHY_OCP                = 0xb8,
 384         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 385         MISC                    = 0xf0, /* 8168e only. */
 386 #define TXPLA_RST                       (1 << 29)
 387 #define DISABLE_LAN_EN                  (1 << 23) /* Enable GPIO pin */
 388 #define PWM_EN                          (1 << 22)
 389 #define RXDV_GATED_EN                   (1 << 19)
 390 #define EARLY_TALLY_EN                  (1 << 16)
 391 };
 392
 393 enum rtl_register_content {
 394         /* InterruptStatusBits */
 395         SYSErr          = 0x8000,
 396         PCSTimeout      = 0x4000,
 397         SWInt           = 0x0100,
 398         TxDescUnavail   = 0x0080,
 399         RxFIFOOver      = 0x0040,
 400         LinkChg         = 0x0020,
 401         RxOverflow      = 0x0010,
 402         TxErr           = 0x0008,
 403         TxOK            = 0x0004,
 404         RxErr           = 0x0002,
 405         RxOK            = 0x0001,
 406
 407         /* RxStatusDesc */
 408         RxRWT   = (1 << 22),
 409         RxRES   = (1 << 21),
 410         RxRUNT  = (1 << 20),
 411         RxCRC   = (1 << 19),
 412
 413         /* ChipCmdBits */
 414         StopReq         = 0x80,
 415         CmdReset        = 0x10,
 416         CmdRxEnb        = 0x08,
 417         CmdTxEnb        = 0x04,
 418         RxBufEmpty      = 0x01,
 419
 420         /* TXPoll register p.5 */
 421         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 422         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 423         FSWInt          = 0x01,         /* Forced software interrupt */
 424
 425         /* Cfg9346Bits */
 426         Cfg9346_Lock    = 0x00,
 427         Cfg9346_Unlock  = 0xc0,
 428
 429         /* rx_mode_bits */
 430         AcceptErr       = 0x20,
 431         AcceptRunt      = 0x10,
 432         AcceptBroadcast = 0x08,
 433         AcceptMulticast = 0x04,
 434         AcceptMyPhys    = 0x02,
 435         AcceptAllPhys   = 0x01,
 436 #define RX_CONFIG_ACCEPT_MASK           0x3f
 437
 438         /* TxConfigBits */
 439         TxInterFrameGapShift = 24,
 440         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 441
 442         /* Config1 register p.24 */
 443         LEDS1           = (1 << 7),
 444         LEDS0           = (1 << 6),
 445         Speed_down      = (1 << 4),
 446         MEMMAP          = (1 << 3),
 447         IOMAP           = (1 << 2),
 448         VPD             = (1 << 1),
 449         PMEnable        = (1 << 0),     /* Power Management Enable */
 450
 451         /* Config2 register p. 25 */
 452         ClkReqEn        = (1 << 7),     /* Clock Request Enable */
 453         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
 454         PCI_Clock_66MHz = 0x01,
 455         PCI_Clock_33MHz = 0x00,
 456
 457         /* Config3 register p.25 */
 458         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 459         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 460         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
 461         Rdy_to_L23      = (1 << 1),     /* L23 Enable */
 462         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 463
 464         /* Config4 register */
 465         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
 466
 467         /* Config5 register p.27 */
 468         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 469         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 470         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 471         Spi_en          = (1 << 3),
 472         LanWake         = (1 << 1),     /* LanWake enable/disable */
 473         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 474         ASPM_en         = (1 << 0),     /* ASPM enable */
 475
 476         /* CPlusCmd p.31 */
 477         EnableBist      = (1 << 15),    // 8168 8101
 478         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 479         Normal_mode     = (1 << 13),    // unused
 480         Force_half_dup  = (1 << 12),    // 8168 8101
 481         Force_rxflow_en = (1 << 11),    // 8168 8101
 482         Force_txflow_en = (1 << 10),    // 8168 8101
 483         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 484         ASF             = (1 << 8),     // 8168 8101
 485         PktCntrDisable  = (1 << 7),     // 8168 8101
 486         Mac_dbgo_sel    = 0x001c,       // 8168
 487         RxVlan          = (1 << 6),
 488         RxChkSum        = (1 << 5),
 489         PCIDAC          = (1 << 4),
 490         PCIMulRW        = (1 << 3),
 491 #define INTT_MASK       GENMASK(1, 0)
 492
 493         /* rtl8169_PHYstatus */
 494         TBI_Enable      = 0x80,
 495         TxFlowCtrl      = 0x40,
 496         RxFlowCtrl      = 0x20,
 497         _1000bpsF       = 0x10,
 498         _100bps         = 0x08,
 499         _10bps          = 0x04,
 500         LinkStatus      = 0x02,
 501         FullDup         = 0x01,
 502
 503         /* ResetCounterCommand */
 504         CounterReset    = 0x1,
 505
 506         /* DumpCounterCommand */
 507         CounterDump     = 0x8,
 508
 509         /* magic enable v2 */
 510         MagicPacket_v2  = (1 << 16),    /* Wake up when receives a Magic Packet */
 511 };
 512
 513 enum rtl_desc_bit {
 514         /* First doubleword. */
 515         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 516         RingEnd         = (1 << 30), /* End of descriptor ring */
 517         FirstFrag       = (1 << 29), /* First segment of a packet */
 518         LastFrag        = (1 << 28), /* Final segment of a packet */
 519 };
 520
 521 /* Generic case. */
 522 enum rtl_tx_desc_bit {
 523         /* First doubleword. */
 524         TD_LSO          = (1 << 27),            /* Large Send Offload */
 525 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 526
 527         /* Second doubleword. */
 528         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 529 };
 530
 531 /* 8169, 8168b and 810x except 8102e. */
 532 enum rtl_tx_desc_bit_0 {
 533         /* First doubleword. */
 534 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 535         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 536         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 537         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 538 };
 539
 540 /* 8102e, 8168c and beyond. */
 541 enum rtl_tx_desc_bit_1 {
 542         /* First doubleword. */
 543         TD1_GTSENV4     = (1 << 26),            /* Giant Send for IPv4 */
 544         TD1_GTSENV6     = (1 << 25),            /* Giant Send for IPv6 */
 545 #define GTTCPHO_SHIFT                   18
 546 #define GTTCPHO_MAX                     0x7fU
 547
 548         /* Second doubleword. */
 549 #define TCPHO_SHIFT                     18
 550 #define TCPHO_MAX                       0x3ffU
 551 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 552         TD1_IPv6_CS     = (1 << 28),            /* Calculate IPv6 checksum */
 553         TD1_IPv4_CS     = (1 << 29),            /* Calculate IPv4 checksum */
 554         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 555         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 556 };
 557
 558 enum rtl_rx_desc_bit {
 559         /* Rx private */
 560         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 561         PID0            = (1 << 17), /* Protocol ID bit 0/2 */
 562
 563 #define RxProtoUDP      (PID1)
 564 #define RxProtoTCP      (PID0)
 565 #define RxProtoIP       (PID1 | PID0)
 566 #define RxProtoMask     RxProtoIP
 567
 568         IPFail          = (1 << 16), /* IP checksum failed */
 569         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 570         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 571         RxVlanTag       = (1 << 16), /* VLAN tag available */
 572 };
 573
 574 #define RsvdMask        0x3fffc000
 575 #define CPCMD_QUIRK_MASK        (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
 576
 577 struct TxDesc {
 578         __le32 opts1;
 579         __le32 opts2;
 580         __le64 addr;
 581 };
 582
 583 struct RxDesc {
 584         __le32 opts1;
 585         __le32 opts2;
 586         __le64 addr;
 587 };
 588
 589 struct ring_info {
 590         struct sk_buff  *skb;
 591         u32             len;
 592 };
 593
 594 struct rtl8169_counters {
 595         __le64  tx_packets;
 596         __le64  rx_packets;
 597         __le64  tx_errors;
 598         __le32  rx_errors;
 599         __le16  rx_missed;
 600         __le16  align_errors;
 601         __le32  tx_one_collision;
 602         __le32  tx_multi_collision;
 603         __le64  rx_unicast;
 604         __le64  rx_broadcast;
 605         __le32  rx_multicast;
 606         __le16  tx_aborted;
 607         __le16  tx_underun;
 608 };
 609
 610 struct rtl8169_tc_offsets {
 611         bool    inited;
 612         __le64  tx_errors;
 613         __le32  tx_multi_collision;
 614         __le16  tx_aborted;
 615 };
 616
 617 enum rtl_flag {
 618         RTL_FLAG_TASK_ENABLED = 0,
 619         RTL_FLAG_TASK_RESET_PENDING,
 620         RTL_FLAG_MAX
 621 };
 622
 623 struct rtl8169_stats {
 624         u64                     packets;
 625         u64                     bytes;
 626         struct u64_stats_sync   syncp;
 627 };
 628
 629 struct rtl8169_private {
 630         void __iomem *mmio_addr;        /* memory map physical address */
 631         struct pci_dev *pci_dev;
 632         struct net_device *dev;
 633         struct phy_device *phydev;
 634         struct napi_struct napi;
 635         u32 msg_enable;
 636         enum mac_version mac_version;
 637         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 638         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 639         u32 dirty_tx;
 640         struct rtl8169_stats rx_stats;
 641         struct rtl8169_stats tx_stats;
 642         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 643         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 644         dma_addr_t TxPhyAddr;
 645         dma_addr_t RxPhyAddr;
 646         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
 647         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 648         u16 cp_cmd;
 649
 650         u16 irq_mask;
 651         const struct rtl_coalesce_info *coalesce_info;
 652         struct clk *clk;
 653
 654         struct mdio_ops {
 655                 void (*write)(struct rtl8169_private *, int, int);
 656                 int (*read)(struct rtl8169_private *, int);
 657         } mdio_ops;
 658
 659         struct jumbo_ops {
 660                 void (*enable)(struct rtl8169_private *);
 661                 void (*disable)(struct rtl8169_private *);
 662         } jumbo_ops;
 663
 664         void (*hw_start)(struct rtl8169_private *tp);
 665         bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
 666
 667         struct {
 668                 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
 669                 struct mutex mutex;
 670                 struct work_struct work;
 671         } wk;
 672
 673         unsigned irq_enabled:1;
 674         unsigned supports_gmii:1;
 675         dma_addr_t counters_phys_addr;
 676         struct rtl8169_counters *counters;
 677         struct rtl8169_tc_offsets tc_offset;
 678         u32 saved_wolopts;
 679
 680         const char *fw_name;
 681         struct rtl_fw {
 682                 const struct firmware *fw;
 683
 684 #define RTL_VER_SIZE            32
 685
 686                 char version[RTL_VER_SIZE];
 687
 688                 struct rtl_fw_phy_action {
 689                         __le32 *code;
 690                         size_t size;
 691                 } phy_action;
 692         } *rtl_fw;
 693
 694         u32 ocp_base;
 695 };
 696
 697 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp);
 698
 699 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 700 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 701 module_param_named(debug, debug.msg_enable, int, 0);
 702 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 703 MODULE_SOFTDEP("pre: realtek");
 704 MODULE_LICENSE("GPL");
 705 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 706 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 707 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 708 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 709 MODULE_FIRMWARE(FIRMWARE_8168E_3);
 710 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 711 MODULE_FIRMWARE(FIRMWARE_8168F_1);
 712 MODULE_FIRMWARE(FIRMWARE_8168F_2);
 713 MODULE_FIRMWARE(FIRMWARE_8402_1);
 714 MODULE_FIRMWARE(FIRMWARE_8411_1);
 715 MODULE_FIRMWARE(FIRMWARE_8411_2);
 716 MODULE_FIRMWARE(FIRMWARE_8106E_1);
 717 MODULE_FIRMWARE(FIRMWARE_8106E_2);
 718 MODULE_FIRMWARE(FIRMWARE_8168G_2);
 719 MODULE_FIRMWARE(FIRMWARE_8168G_3);
 720 MODULE_FIRMWARE(FIRMWARE_8168H_1);
 721 MODULE_FIRMWARE(FIRMWARE_8168H_2);
 722 MODULE_FIRMWARE(FIRMWARE_8107E_1);
 723 MODULE_FIRMWARE(FIRMWARE_8107E_2);
 724
 725 static inline struct device *tp_to_dev(struct rtl8169_private *tp)
 726 {
 727         return &tp->pci_dev->dev;
 728 }
 729
 730 static void rtl_lock_work(struct rtl8169_private *tp)
 731 {
 732         mutex_lock(&tp->wk.mutex);
 733 }
 734
 735 static void rtl_unlock_work(struct rtl8169_private *tp)
 736 {
 737         mutex_unlock(&tp->wk.mutex);
 738 }
 739
 740 static void rtl_lock_config_regs(struct rtl8169_private *tp)
 741 {
 742         RTL_W8(tp, Cfg9346, Cfg9346_Lock);
 743 }
 744
 745 static void rtl_unlock_config_regs(struct rtl8169_private *tp)
 746 {
 747         RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
 748 }
 749
 750 static void rtl_tx_performance_tweak(struct rtl8169_private *tp, u16 force)
 751 {
 752         pcie_capability_clear_and_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
 753                                            PCI_EXP_DEVCTL_READRQ, force);
 754 }
 755
 756 struct rtl_cond {
 757         bool (*check)(struct rtl8169_private *);
 758         const char *msg;
 759 };
 760
 761 static void rtl_udelay(unsigned int d)
 762 {
 763         udelay(d);
 764 }
 765
 766 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
 767                           void (*delay)(unsigned int), unsigned int d, int n,
 768                           bool high)
 769 {
 770         int i;
 771
 772         for (i = 0; i < n; i++) {
 773                 if (c->check(tp) == high)
 774                         return true;
 775                 delay(d);
 776         }
 777         netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
 778                   c->msg, !high, n, d);
 779         return false;
 780 }
 781
 782 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
 783                                       const struct rtl_cond *c,
 784                                       unsigned int d, int n)
 785 {
 786         return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
 787 }
 788
 789 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
 790                                      const struct rtl_cond *c,
 791                                      unsigned int d, int n)
 792 {
 793         return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
 794 }
 795
 796 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
 797                                       const struct rtl_cond *c,
 798                                       unsigned int d, int n)
 799 {
 800         return rtl_loop_wait(tp, c, msleep, d, n, true);
 801 }
 802
 803 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
 804                                      const struct rtl_cond *c,
 805                                      unsigned int d, int n)
 806 {
 807         return rtl_loop_wait(tp, c, msleep, d, n, false);
 808 }
 809
 810 #define DECLARE_RTL_COND(name)                          \
 811 static bool name ## _check(struct rtl8169_private *);   \
 812                                                         \
 813 static const struct rtl_cond name = {                   \
 814         .check  = name ## _check,                       \
 815         .msg    = #name                                 \
 816 };                                                      \
 817                                                         \
 818 static bool name ## _check(struct rtl8169_private *tp)
 819
 820 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
 821 {
 822         if (reg & 0xffff0001) {
 823                 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
 824                 return true;
 825         }
 826         return false;
 827 }
 828
 829 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
 830 {
 831         return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
 832 }
 833
 834 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 835 {
 836         if (rtl_ocp_reg_failure(tp, reg))
 837                 return;
 838
 839         RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
 840
 841         rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
 842 }
 843
 844 static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
 845 {
 846         if (rtl_ocp_reg_failure(tp, reg))
 847                 return 0;
 848
 849         RTL_W32(tp, GPHY_OCP, reg << 15);
 850
 851         return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
 852                 (RTL_R32(tp, GPHY_OCP) & 0xffff) : ~0;
 853 }
 854
 855 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 856 {
 857         if (rtl_ocp_reg_failure(tp, reg))
 858                 return;
 859
 860         RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
 861 }
 862
 863 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
 864 {
 865         if (rtl_ocp_reg_failure(tp, reg))
 866                 return 0;
 867
 868         RTL_W32(tp, OCPDR, reg << 15);
 869
 870         return RTL_R32(tp, OCPDR);
 871 }
 872
 873 #define OCP_STD_PHY_BASE        0xa400
 874
 875 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
 876 {
 877         if (reg == 0x1f) {
 878                 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
 879                 return;
 880         }
 881
 882         if (tp->ocp_base != OCP_STD_PHY_BASE)
 883                 reg -= 0x10;
 884
 885         r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
 886 }
 887
 888 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
 889 {
 890         if (tp->ocp_base != OCP_STD_PHY_BASE)
 891                 reg -= 0x10;
 892
 893         return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
 894 }
 895
 896 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
 897 {
 898         if (reg == 0x1f) {
 899                 tp->ocp_base = value << 4;
 900                 return;
 901         }
 902
 903         r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
 904 }
 905
 906 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
 907 {
 908         return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
 909 }
 910
 911 DECLARE_RTL_COND(rtl_phyar_cond)
 912 {
 913         return RTL_R32(tp, PHYAR) & 0x80000000;
 914 }
 915
 916 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
 917 {
 918         RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
 919
 920         rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
 921         /*
 922          * According to hardware specs a 20us delay is required after write
 923          * complete indication, but before sending next command.
 924          */
 925         udelay(20);
 926 }
 927
 928 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
 929 {
 930         int value;
 931
 932         RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
 933
 934         value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
 935                 RTL_R32(tp, PHYAR) & 0xffff : ~0;
 936
 937         /*
 938          * According to hardware specs a 20us delay is required after read
 939          * complete indication, but before sending next command.
 940          */
 941         udelay(20);
 942
 943         return value;
 944 }
 945
 946 DECLARE_RTL_COND(rtl_ocpar_cond)
 947 {
 948         return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
 949 }
 950
 951 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
 952 {
 953         RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
 954         RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
 955         RTL_W32(tp, EPHY_RXER_NUM, 0);
 956
 957         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
 958 }
 959
 960 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
 961 {
 962         r8168dp_1_mdio_access(tp, reg,
 963                               OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
 964 }
 965
 966 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
 967 {
 968         r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
 969
 970         mdelay(1);
 971         RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
 972         RTL_W32(tp, EPHY_RXER_NUM, 0);
 973
 974         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
 975                 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : ~0;
 976 }
 977
 978 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
 979
 980 static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
 981 {
 982         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
 983 }
 984
 985 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
 986 {
 987         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
 988 }
 989
 990 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
 991 {
 992         r8168dp_2_mdio_start(tp);
 993
 994         r8169_mdio_write(tp, reg, value);
 995
 996         r8168dp_2_mdio_stop(tp);
 997 }
 998
 999 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1000 {
1001         int value;
1002
1003         r8168dp_2_mdio_start(tp);
1004
1005         value = r8169_mdio_read(tp, reg);
1006
1007         r8168dp_2_mdio_stop(tp);
1008
1009         return value;
1010 }
1011
1012 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1013 {
1014         tp->mdio_ops.write(tp, location, val);
1015 }
1016
1017 static int rtl_readphy(struct rtl8169_private *tp, int location)
1018 {
1019         return tp->mdio_ops.read(tp, location);
1020 }
1021
1022 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1023 {
1024         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1025 }
1026
1027 static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1028 {
1029         int val;
1030
1031         val = rtl_readphy(tp, reg_addr);
1032         rtl_writephy(tp, reg_addr, (val & ~m) | p);
1033 }
1034
1035 DECLARE_RTL_COND(rtl_ephyar_cond)
1036 {
1037         return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1038 }
1039
1040 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1041 {
1042         RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1043                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1044
1045         rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1046
1047         udelay(10);
1048 }
1049
1050 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1051 {
1052         RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1053
1054         return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1055                 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1056 }
1057
1058 DECLARE_RTL_COND(rtl_eriar_cond)
1059 {
1060         return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
1061 }
1062
1063 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1064                            u32 val, int type)
1065 {
1066         BUG_ON((addr & 3) || (mask == 0));
1067         RTL_W32(tp, ERIDR, val);
1068         RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1069
1070         rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1071 }
1072
1073 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1074                           u32 val)
1075 {
1076         _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC);
1077 }
1078
1079 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1080 {
1081         RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1082
1083         return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1084                 RTL_R32(tp, ERIDR) : ~0;
1085 }
1086
1087 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr)
1088 {
1089         return _rtl_eri_read(tp, addr, ERIAR_EXGMAC);
1090 }
1091
1092 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1093                          u32 m)
1094 {
1095         u32 val;
1096
1097         val = rtl_eri_read(tp, addr);
1098         rtl_eri_write(tp, addr, mask, (val & ~m) | p);
1099 }
1100
1101 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 mask,
1102                              u32 p)
1103 {
1104         rtl_w0w1_eri(tp, addr, mask, p, 0);
1105 }
1106
1107 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 mask,
1108                                u32 m)
1109 {
1110         rtl_w0w1_eri(tp, addr, mask, 0, m);
1111 }
1112
1113 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1114 {
1115         RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1116         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1117                 RTL_R32(tp, OCPDR) : ~0;
1118 }
1119
1120 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1121 {
1122         return _rtl_eri_read(tp, reg, ERIAR_OOB);
1123 }
1124
1125 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1126                               u32 data)
1127 {
1128         RTL_W32(tp, OCPDR, data);
1129         RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1130         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1131 }
1132
1133 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1134                               u32 data)
1135 {
1136         _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1137                        data, ERIAR_OOB);
1138 }
1139
1140 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd)
1141 {
1142         rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd);
1143
1144         r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001);
1145 }
1146
1147 #define OOB_CMD_RESET           0x00
1148 #define OOB_CMD_DRIVER_START    0x05
1149 #define OOB_CMD_DRIVER_STOP     0x06
1150
1151 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1152 {
1153         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1154 }
1155
1156 DECLARE_RTL_COND(rtl_dp_ocp_read_cond)
1157 {
1158         u16 reg;
1159
1160         reg = rtl8168_get_ocp_reg(tp);
1161
1162         return r8168dp_ocp_read(tp, 0x0f, reg) & 0x00000800;
1163 }
1164
1165 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1166 {
1167         return r8168ep_ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1168 }
1169
1170 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1171 {
1172         return RTL_R8(tp, IBISR0) & 0x20;
1173 }
1174
1175 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1176 {
1177         RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1178         rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000);
1179         RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1180         RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1181 }
1182
1183 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1184 {
1185         r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START);
1186         rtl_msleep_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10, 10);
1187 }
1188
1189 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1190 {
1191         r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1192         r8168ep_ocp_write(tp, 0x01, 0x30,
1193                           r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
1194         rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1195 }
1196
1197 static void rtl8168_driver_start(struct rtl8169_private *tp)
1198 {
1199         switch (tp->mac_version) {
1200         case RTL_GIGA_MAC_VER_27:
1201         case RTL_GIGA_MAC_VER_28:
1202         case RTL_GIGA_MAC_VER_31:
1203                 rtl8168dp_driver_start(tp);
1204                 break;
1205         case RTL_GIGA_MAC_VER_49:
1206         case RTL_GIGA_MAC_VER_50:
1207         case RTL_GIGA_MAC_VER_51:
1208                 rtl8168ep_driver_start(tp);
1209                 break;
1210         default:
1211                 BUG();
1212                 break;
1213         }
1214 }
1215
1216 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1217 {
1218         r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1219         rtl_msleep_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10, 10);
1220 }
1221
1222 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1223 {
1224         rtl8168ep_stop_cmac(tp);
1225         r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1226         r8168ep_ocp_write(tp, 0x01, 0x30,
1227                           r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
1228         rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1229 }
1230
1231 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1232 {
1233         switch (tp->mac_version) {
1234         case RTL_GIGA_MAC_VER_27:
1235         case RTL_GIGA_MAC_VER_28:
1236         case RTL_GIGA_MAC_VER_31:
1237                 rtl8168dp_driver_stop(tp);
1238                 break;
1239         case RTL_GIGA_MAC_VER_49:
1240         case RTL_GIGA_MAC_VER_50:
1241         case RTL_GIGA_MAC_VER_51:
1242                 rtl8168ep_driver_stop(tp);
1243                 break;
1244         default:
1245                 BUG();
1246                 break;
1247         }
1248 }
1249
1250 static bool r8168dp_check_dash(struct rtl8169_private *tp)
1251 {
1252         u16 reg = rtl8168_get_ocp_reg(tp);
1253
1254         return !!(r8168dp_ocp_read(tp, 0x0f, reg) & 0x00008000);
1255 }
1256
1257 static bool r8168ep_check_dash(struct rtl8169_private *tp)
1258 {
1259         return !!(r8168ep_ocp_read(tp, 0x0f, 0x128) & 0x00000001);
1260 }
1261
1262 static bool r8168_check_dash(struct rtl8169_private *tp)
1263 {
1264         switch (tp->mac_version) {
1265         case RTL_GIGA_MAC_VER_27:
1266         case RTL_GIGA_MAC_VER_28:
1267         case RTL_GIGA_MAC_VER_31:
1268                 return r8168dp_check_dash(tp);
1269         case RTL_GIGA_MAC_VER_49:
1270         case RTL_GIGA_MAC_VER_50:
1271         case RTL_GIGA_MAC_VER_51:
1272                 return r8168ep_check_dash(tp);
1273         default:
1274                 return false;
1275         }
1276 }
1277
1278 static void rtl_reset_packet_filter(struct rtl8169_private *tp)
1279 {
1280         rtl_eri_clear_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0));
1281         rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0));
1282 }
1283
1284 DECLARE_RTL_COND(rtl_efusear_cond)
1285 {
1286         return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1287 }
1288
1289 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1290 {
1291         RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1292
1293         return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1294                 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1295 }
1296
1297 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1298 {
1299         RTL_W16(tp, IntrStatus, bits);
1300 }
1301
1302 static void rtl_irq_disable(struct rtl8169_private *tp)
1303 {
1304         RTL_W16(tp, IntrMask, 0);
1305         tp->irq_enabled = 0;
1306 }
1307
1308 #define RTL_EVENT_NAPI_RX       (RxOK | RxErr)
1309 #define RTL_EVENT_NAPI_TX       (TxOK | TxErr)
1310 #define RTL_EVENT_NAPI          (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1311
1312 static void rtl_irq_enable(struct rtl8169_private *tp)
1313 {
1314         tp->irq_enabled = 1;
1315         RTL_W16(tp, IntrMask, tp->irq_mask);
1316 }
1317
1318 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1319 {
1320         rtl_irq_disable(tp);
1321         rtl_ack_events(tp, 0xffff);
1322         /* PCI commit */
1323         RTL_R8(tp, ChipCmd);
1324 }
1325
1326 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1327 {
1328         struct net_device *dev = tp->dev;
1329         struct phy_device *phydev = tp->phydev;
1330
1331         if (!netif_running(dev))
1332                 return;
1333
1334         if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1335             tp->mac_version == RTL_GIGA_MAC_VER_38) {
1336                 if (phydev->speed == SPEED_1000) {
1337                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1338                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1339                 } else if (phydev->speed == SPEED_100) {
1340                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1341                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1342                 } else {
1343                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1344                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1345                 }
1346                 rtl_reset_packet_filter(tp);
1347         } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1348                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
1349                 if (phydev->speed == SPEED_1000) {
1350                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1351                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1352                 } else {
1353                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1354                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1355                 }
1356         } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1357                 if (phydev->speed == SPEED_10) {
1358                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02);
1359                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a);
1360                 } else {
1361                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
1362                 }
1363         }
1364 }
1365
1366 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1367
1368 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1369 {
1370         struct rtl8169_private *tp = netdev_priv(dev);
1371
1372         rtl_lock_work(tp);
1373         wol->supported = WAKE_ANY;
1374         wol->wolopts = tp->saved_wolopts;
1375         rtl_unlock_work(tp);
1376 }
1377
1378 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1379 {
1380         unsigned int i, tmp;
1381         static const struct {
1382                 u32 opt;
1383                 u16 reg;
1384                 u8  mask;
1385         } cfg[] = {
1386                 { WAKE_PHY,   Config3, LinkUp },
1387                 { WAKE_UCAST, Config5, UWF },
1388                 { WAKE_BCAST, Config5, BWF },
1389                 { WAKE_MCAST, Config5, MWF },
1390                 { WAKE_ANY,   Config5, LanWake },
1391                 { WAKE_MAGIC, Config3, MagicPacket }
1392         };
1393         u8 options;
1394
1395         rtl_unlock_config_regs(tp);
1396
1397         switch (tp->mac_version) {
1398         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
1399         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1400                 tmp = ARRAY_SIZE(cfg) - 1;
1401                 if (wolopts & WAKE_MAGIC)
1402                         rtl_eri_set_bits(tp, 0x0dc, ERIAR_MASK_0100,
1403                                          MagicPacket_v2);
1404                 else
1405                         rtl_eri_clear_bits(tp, 0x0dc, ERIAR_MASK_0100,
1406                                            MagicPacket_v2);
1407                 break;
1408         default:
1409                 tmp = ARRAY_SIZE(cfg);
1410                 break;
1411         }
1412
1413         for (i = 0; i < tmp; i++) {
1414                 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
1415                 if (wolopts & cfg[i].opt)
1416                         options |= cfg[i].mask;
1417                 RTL_W8(tp, cfg[i].reg, options);
1418         }
1419
1420         switch (tp->mac_version) {
1421         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_17:
1422                 options = RTL_R8(tp, Config1) & ~PMEnable;
1423                 if (wolopts)
1424                         options |= PMEnable;
1425                 RTL_W8(tp, Config1, options);
1426                 break;
1427         default:
1428                 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
1429                 if (wolopts)
1430                         options |= PME_SIGNAL;
1431                 RTL_W8(tp, Config2, options);
1432                 break;
1433         }
1434
1435         rtl_lock_config_regs(tp);
1436
1437         device_set_wakeup_enable(tp_to_dev(tp), wolopts);
1438 }
1439
1440 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1441 {
1442         struct rtl8169_private *tp = netdev_priv(dev);
1443         struct device *d = tp_to_dev(tp);
1444
1445         if (wol->wolopts & ~WAKE_ANY)
1446                 return -EINVAL;
1447
1448         pm_runtime_get_noresume(d);
1449
1450         rtl_lock_work(tp);
1451
1452         tp->saved_wolopts = wol->wolopts;
1453
1454         if (pm_runtime_active(d))
1455                 __rtl8169_set_wol(tp, tp->saved_wolopts);
1456
1457         rtl_unlock_work(tp);
1458
1459         pm_runtime_put_noidle(d);
1460
1461         return 0;
1462 }
1463
1464 static void rtl8169_get_drvinfo(struct net_device *dev,
1465                                 struct ethtool_drvinfo *info)
1466 {
1467         struct rtl8169_private *tp = netdev_priv(dev);
1468         struct rtl_fw *rtl_fw = tp->rtl_fw;
1469
1470         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1471         strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1472         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1473         if (rtl_fw)
1474                 strlcpy(info->fw_version, rtl_fw->version,
1475                         sizeof(info->fw_version));
1476 }
1477
1478 static int rtl8169_get_regs_len(struct net_device *dev)
1479 {
1480         return R8169_REGS_SIZE;
1481 }
1482
1483 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1484         netdev_features_t features)
1485 {
1486         struct rtl8169_private *tp = netdev_priv(dev);
1487
1488         if (dev->mtu > TD_MSS_MAX)
1489                 features &= ~NETIF_F_ALL_TSO;
1490
1491         if (dev->mtu > JUMBO_1K &&
1492             tp->mac_version > RTL_GIGA_MAC_VER_06)
1493                 features &= ~NETIF_F_IP_CSUM;
1494
1495         return features;
1496 }
1497
1498 static int rtl8169_set_features(struct net_device *dev,
1499                                 netdev_features_t features)
1500 {
1501         struct rtl8169_private *tp = netdev_priv(dev);
1502         u32 rx_config;
1503
1504         rtl_lock_work(tp);
1505
1506         rx_config = RTL_R32(tp, RxConfig);
1507         if (features & NETIF_F_RXALL)
1508                 rx_config |= (AcceptErr | AcceptRunt);
1509         else
1510                 rx_config &= ~(AcceptErr | AcceptRunt);
1511
1512         RTL_W32(tp, RxConfig, rx_config);
1513
1514         if (features & NETIF_F_RXCSUM)
1515                 tp->cp_cmd |= RxChkSum;
1516         else
1517                 tp->cp_cmd &= ~RxChkSum;
1518
1519         if (features & NETIF_F_HW_VLAN_CTAG_RX)
1520                 tp->cp_cmd |= RxVlan;
1521         else
1522                 tp->cp_cmd &= ~RxVlan;
1523
1524         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1525         RTL_R16(tp, CPlusCmd);
1526
1527         rtl_unlock_work(tp);
1528
1529         return 0;
1530 }
1531
1532 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1533 {
1534         return (skb_vlan_tag_present(skb)) ?
1535                 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1536 }
1537
1538 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1539 {
1540         u32 opts2 = le32_to_cpu(desc->opts2);
1541
1542         if (opts2 & RxVlanTag)
1543                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1544 }
1545
1546 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1547                              void *p)
1548 {
1549         struct rtl8169_private *tp = netdev_priv(dev);
1550         u32 __iomem *data = tp->mmio_addr;
1551         u32 *dw = p;
1552         int i;
1553
1554         rtl_lock_work(tp);
1555         for (i = 0; i < R8169_REGS_SIZE; i += 4)
1556                 memcpy_fromio(dw++, data++, 4);
1557         rtl_unlock_work(tp);
1558 }
1559
1560 static u32 rtl8169_get_msglevel(struct net_device *dev)
1561 {
1562         struct rtl8169_private *tp = netdev_priv(dev);
1563
1564         return tp->msg_enable;
1565 }
1566
1567 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1568 {
1569         struct rtl8169_private *tp = netdev_priv(dev);
1570
1571         tp->msg_enable = value;
1572 }
1573
1574 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1575         "tx_packets",
1576         "rx_packets",
1577         "tx_errors",
1578         "rx_errors",
1579         "rx_missed",
1580         "align_errors",
1581         "tx_single_collisions",
1582         "tx_multi_collisions",
1583         "unicast",
1584         "broadcast",
1585         "multicast",
1586         "tx_aborted",
1587         "tx_underrun",
1588 };
1589
1590 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1591 {
1592         switch (sset) {
1593         case ETH_SS_STATS:
1594                 return ARRAY_SIZE(rtl8169_gstrings);
1595         default:
1596                 return -EOPNOTSUPP;
1597         }
1598 }
1599
1600 DECLARE_RTL_COND(rtl_counters_cond)
1601 {
1602         return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
1603 }
1604
1605 static bool rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
1606 {
1607         dma_addr_t paddr = tp->counters_phys_addr;
1608         u32 cmd;
1609
1610         RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
1611         RTL_R32(tp, CounterAddrHigh);
1612         cmd = (u64)paddr & DMA_BIT_MASK(32);
1613         RTL_W32(tp, CounterAddrLow, cmd);
1614         RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
1615
1616         return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
1617 }
1618
1619 static bool rtl8169_reset_counters(struct rtl8169_private *tp)
1620 {
1621         /*
1622          * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
1623          * tally counters.
1624          */
1625         if (tp->mac_version < RTL_GIGA_MAC_VER_19)
1626                 return true;
1627
1628         return rtl8169_do_counters(tp, CounterReset);
1629 }
1630
1631 static bool rtl8169_update_counters(struct rtl8169_private *tp)
1632 {
1633         u8 val = RTL_R8(tp, ChipCmd);
1634
1635         /*
1636          * Some chips are unable to dump tally counters when the receiver
1637          * is disabled. If 0xff chip may be in a PCI power-save state.
1638          */
1639         if (!(val & CmdRxEnb) || val == 0xff)
1640                 return true;
1641
1642         return rtl8169_do_counters(tp, CounterDump);
1643 }
1644
1645 static bool rtl8169_init_counter_offsets(struct rtl8169_private *tp)
1646 {
1647         struct rtl8169_counters *counters = tp->counters;
1648         bool ret = false;
1649
1650         /*
1651          * rtl8169_init_counter_offsets is called from rtl_open.  On chip
1652          * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1653          * reset by a power cycle, while the counter values collected by the
1654          * driver are reset at every driver unload/load cycle.
1655          *
1656          * To make sure the HW values returned by @get_stats64 match the SW
1657          * values, we collect the initial values at first open(*) and use them
1658          * as offsets to normalize the values returned by @get_stats64.
1659          *
1660          * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1661          * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1662          * set at open time by rtl_hw_start.
1663          */
1664
1665         if (tp->tc_offset.inited)
1666                 return true;
1667
1668         /* If both, reset and update fail, propagate to caller. */
1669         if (rtl8169_reset_counters(tp))
1670                 ret = true;
1671
1672         if (rtl8169_update_counters(tp))
1673                 ret = true;
1674
1675         tp->tc_offset.tx_errors = counters->tx_errors;
1676         tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1677         tp->tc_offset.tx_aborted = counters->tx_aborted;
1678         tp->tc_offset.inited = true;
1679
1680         return ret;
1681 }
1682
1683 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1684                                       struct ethtool_stats *stats, u64 *data)
1685 {
1686         struct rtl8169_private *tp = netdev_priv(dev);
1687         struct device *d = tp_to_dev(tp);
1688         struct rtl8169_counters *counters = tp->counters;
1689
1690         ASSERT_RTNL();
1691
1692         pm_runtime_get_noresume(d);
1693
1694         if (pm_runtime_active(d))
1695                 rtl8169_update_counters(tp);
1696
1697         pm_runtime_put_noidle(d);
1698
1699         data[0] = le64_to_cpu(counters->tx_packets);
1700         data[1] = le64_to_cpu(counters->rx_packets);
1701         data[2] = le64_to_cpu(counters->tx_errors);
1702         data[3] = le32_to_cpu(counters->rx_errors);
1703         data[4] = le16_to_cpu(counters->rx_missed);
1704         data[5] = le16_to_cpu(counters->align_errors);
1705         data[6] = le32_to_cpu(counters->tx_one_collision);
1706         data[7] = le32_to_cpu(counters->tx_multi_collision);
1707         data[8] = le64_to_cpu(counters->rx_unicast);
1708         data[9] = le64_to_cpu(counters->rx_broadcast);
1709         data[10] = le32_to_cpu(counters->rx_multicast);
1710         data[11] = le16_to_cpu(counters->tx_aborted);
1711         data[12] = le16_to_cpu(counters->tx_underun);
1712 }
1713
1714 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1715 {
1716         switch(stringset) {
1717         case ETH_SS_STATS:
1718                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1719                 break;
1720         }
1721 }
1722
1723 /*
1724  * Interrupt coalescing
1725  *
1726  * > 1 - the availability of the IntrMitigate (0xe2) register through the
1727  * >     8169, 8168 and 810x line of chipsets
1728  *
1729  * 8169, 8168, and 8136(810x) serial chipsets support it.
1730  *
1731  * > 2 - the Tx timer unit at gigabit speed
1732  *
1733  * The unit of the timer depends on both the speed and the setting of CPlusCmd
1734  * (0xe0) bit 1 and bit 0.
1735  *
1736  * For 8169
1737  * bit[1:0] \ speed        1000M           100M            10M
1738  * 0 0                     320ns           2.56us          40.96us
1739  * 0 1                     2.56us          20.48us         327.7us
1740  * 1 0                     5.12us          40.96us         655.4us
1741  * 1 1                     10.24us         81.92us         1.31ms
1742  *
1743  * For the other
1744  * bit[1:0] \ speed        1000M           100M            10M
1745  * 0 0                     5us             2.56us          40.96us
1746  * 0 1                     40us            20.48us         327.7us
1747  * 1 0                     80us            40.96us         655.4us
1748  * 1 1                     160us           81.92us         1.31ms
1749  */
1750
1751 /* rx/tx scale factors for one particular CPlusCmd[0:1] value */
1752 struct rtl_coalesce_scale {
1753         /* Rx / Tx */
1754         u32 nsecs[2];
1755 };
1756
1757 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
1758 struct rtl_coalesce_info {
1759         u32 speed;
1760         struct rtl_coalesce_scale scalev[4];    /* each CPlusCmd[0:1] case */
1761 };
1762
1763 /* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */
1764 #define rxtx_x1822(r, t) {              \
1765         {{(r),          (t)}},          \
1766         {{(r)*8,        (t)*8}},        \
1767         {{(r)*8*2,      (t)*8*2}},      \
1768         {{(r)*8*2*2,    (t)*8*2*2}},    \
1769 }
1770 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1771         /* speed        delays:     rx00   tx00 */
1772         { SPEED_10,     rxtx_x1822(40960, 40960)        },
1773         { SPEED_100,    rxtx_x1822( 2560,  2560)        },
1774         { SPEED_1000,   rxtx_x1822(  320,   320)        },
1775         { 0 },
1776 };
1777
1778 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1779         /* speed        delays:     rx00   tx00 */
1780         { SPEED_10,     rxtx_x1822(40960, 40960)        },
1781         { SPEED_100,    rxtx_x1822( 2560,  2560)        },
1782         { SPEED_1000,   rxtx_x1822( 5000,  5000)        },
1783         { 0 },
1784 };
1785 #undef rxtx_x1822
1786
1787 /* get rx/tx scale vector corresponding to current speed */
1788 static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev)
1789 {
1790         struct rtl8169_private *tp = netdev_priv(dev);
1791         struct ethtool_link_ksettings ecmd;
1792         const struct rtl_coalesce_info *ci;
1793         int rc;
1794
1795         rc = phy_ethtool_get_link_ksettings(dev, &ecmd);
1796         if (rc < 0)
1797                 return ERR_PTR(rc);
1798
1799         for (ci = tp->coalesce_info; ci->speed != 0; ci++) {
1800                 if (ecmd.base.speed == ci->speed) {
1801                         return ci;
1802                 }
1803         }
1804
1805         return ERR_PTR(-ELNRNG);
1806 }
1807
1808 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1809 {
1810         struct rtl8169_private *tp = netdev_priv(dev);
1811         const struct rtl_coalesce_info *ci;
1812         const struct rtl_coalesce_scale *scale;
1813         struct {
1814                 u32 *max_frames;
1815                 u32 *usecs;
1816         } coal_settings [] = {
1817                 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs },
1818                 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs }
1819         }, *p = coal_settings;
1820         int i;
1821         u16 w;
1822
1823         memset(ec, 0, sizeof(*ec));
1824
1825         /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1826         ci = rtl_coalesce_info(dev);
1827         if (IS_ERR(ci))
1828                 return PTR_ERR(ci);
1829
1830         scale = &ci->scalev[tp->cp_cmd & INTT_MASK];
1831
1832         /* read IntrMitigate and adjust according to scale */
1833         for (w = RTL_R16(tp, IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) {
1834                 *p->max_frames = (w & RTL_COALESCE_MASK) << 2;
1835                 w >>= RTL_COALESCE_SHIFT;
1836                 *p->usecs = w & RTL_COALESCE_MASK;
1837         }
1838
1839         for (i = 0; i < 2; i++) {
1840                 p = coal_settings + i;
1841                 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000;
1842
1843                 /*
1844                  * ethtool_coalesce says it is illegal to set both usecs and
1845                  * max_frames to 0.
1846                  */
1847                 if (!*p->usecs && !*p->max_frames)
1848                         *p->max_frames = 1;
1849         }
1850
1851         return 0;
1852 }
1853
1854 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */
1855 static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale(
1856                         struct net_device *dev, u32 nsec, u16 *cp01)
1857 {
1858         const struct rtl_coalesce_info *ci;
1859         u16 i;
1860
1861         ci = rtl_coalesce_info(dev);
1862         if (IS_ERR(ci))
1863                 return ERR_CAST(ci);
1864
1865         for (i = 0; i < 4; i++) {
1866                 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0],
1867                                         ci->scalev[i].nsecs[1]);
1868                 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) {
1869                         *cp01 = i;
1870                         return &ci->scalev[i];
1871                 }
1872         }
1873
1874         return ERR_PTR(-EINVAL);
1875 }
1876
1877 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1878 {
1879         struct rtl8169_private *tp = netdev_priv(dev);
1880         const struct rtl_coalesce_scale *scale;
1881         struct {
1882                 u32 frames;
1883                 u32 usecs;
1884         } coal_settings [] = {
1885                 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs },
1886                 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs }
1887         }, *p = coal_settings;
1888         u16 w = 0, cp01;
1889         int i;
1890
1891         scale = rtl_coalesce_choose_scale(dev,
1892                         max(p[0].usecs, p[1].usecs) * 1000, &cp01);
1893         if (IS_ERR(scale))
1894                 return PTR_ERR(scale);
1895
1896         for (i = 0; i < 2; i++, p++) {
1897                 u32 units;
1898
1899                 /*
1900                  * accept max_frames=1 we returned in rtl_get_coalesce.
1901                  * accept it not only when usecs=0 because of e.g. the following scenario:
1902                  *
1903                  * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
1904                  * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
1905                  * - then user does `ethtool -C eth0 rx-usecs 100`
1906                  *
1907                  * since ethtool sends to kernel whole ethtool_coalesce
1908                  * settings, if we do not handle rx_usecs=!0, rx_frames=1
1909                  * we'll reject it below in `frames % 4 != 0`.
1910                  */
1911                 if (p->frames == 1) {
1912                         p->frames = 0;
1913                 }
1914
1915                 units = p->usecs * 1000 / scale->nsecs[i];
1916                 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4)
1917                         return -EINVAL;
1918
1919                 w <<= RTL_COALESCE_SHIFT;
1920                 w |= units;
1921                 w <<= RTL_COALESCE_SHIFT;
1922                 w |= p->frames >> 2;
1923         }
1924
1925         rtl_lock_work(tp);
1926
1927         RTL_W16(tp, IntrMitigate, swab16(w));
1928
1929         tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
1930         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1931         RTL_R16(tp, CPlusCmd);
1932
1933         rtl_unlock_work(tp);
1934
1935         return 0;
1936 }
1937
1938 static int rtl_get_eee_supp(struct rtl8169_private *tp)
1939 {
1940         struct phy_device *phydev = tp->phydev;
1941         int ret;
1942
1943         switch (tp->mac_version) {
1944         case RTL_GIGA_MAC_VER_34:
1945         case RTL_GIGA_MAC_VER_35:
1946         case RTL_GIGA_MAC_VER_36:
1947         case RTL_GIGA_MAC_VER_38:
1948                 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
1949                 break;
1950         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1951                 phy_write(phydev, 0x1f, 0x0a5c);
1952                 ret = phy_read(phydev, 0x12);
1953                 phy_write(phydev, 0x1f, 0x0000);
1954                 break;
1955         default:
1956                 ret = -EPROTONOSUPPORT;
1957                 break;
1958         }
1959
1960         return ret;
1961 }
1962
1963 static int rtl_get_eee_lpadv(struct rtl8169_private *tp)
1964 {
1965         struct phy_device *phydev = tp->phydev;
1966         int ret;
1967
1968         switch (tp->mac_version) {
1969         case RTL_GIGA_MAC_VER_34:
1970         case RTL_GIGA_MAC_VER_35:
1971         case RTL_GIGA_MAC_VER_36:
1972         case RTL_GIGA_MAC_VER_38:
1973                 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
1974                 break;
1975         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1976                 phy_write(phydev, 0x1f, 0x0a5d);
1977                 ret = phy_read(phydev, 0x11);
1978                 phy_write(phydev, 0x1f, 0x0000);
1979                 break;
1980         default:
1981                 ret = -EPROTONOSUPPORT;
1982                 break;
1983         }
1984
1985         return ret;
1986 }
1987
1988 static int rtl_get_eee_adv(struct rtl8169_private *tp)
1989 {
1990         struct phy_device *phydev = tp->phydev;
1991         int ret;
1992
1993         switch (tp->mac_version) {
1994         case RTL_GIGA_MAC_VER_34:
1995         case RTL_GIGA_MAC_VER_35:
1996         case RTL_GIGA_MAC_VER_36:
1997         case RTL_GIGA_MAC_VER_38:
1998                 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
1999                 break;
2000         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
2001                 phy_write(phydev, 0x1f, 0x0a5d);
2002                 ret = phy_read(phydev, 0x10);
2003                 phy_write(phydev, 0x1f, 0x0000);
2004                 break;
2005         default:
2006                 ret = -EPROTONOSUPPORT;
2007                 break;
2008         }
2009
2010         return ret;
2011 }
2012
2013 static int rtl_set_eee_adv(struct rtl8169_private *tp, int val)
2014 {
2015         struct phy_device *phydev = tp->phydev;
2016         int ret = 0;
2017
2018         switch (tp->mac_version) {
2019         case RTL_GIGA_MAC_VER_34:
2020         case RTL_GIGA_MAC_VER_35:
2021         case RTL_GIGA_MAC_VER_36:
2022         case RTL_GIGA_MAC_VER_38:
2023                 ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
2024                 break;
2025         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
2026                 phy_write(phydev, 0x1f, 0x0a5d);
2027                 phy_write(phydev, 0x10, val);
2028                 phy_write(phydev, 0x1f, 0x0000);
2029                 break;
2030         default:
2031                 ret = -EPROTONOSUPPORT;
2032                 break;
2033         }
2034
2035         return ret;
2036 }
2037
2038 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data)
2039 {
2040         struct rtl8169_private *tp = netdev_priv(dev);
2041         struct device *d = tp_to_dev(tp);
2042         int ret;
2043
2044         pm_runtime_get_noresume(d);
2045
2046         if (!pm_runtime_active(d)) {
2047                 ret = -EOPNOTSUPP;
2048                 goto out;
2049         }
2050
2051         /* Get Supported EEE */
2052         ret = rtl_get_eee_supp(tp);
2053         if (ret < 0)
2054                 goto out;
2055         data->supported = mmd_eee_cap_to_ethtool_sup_t(ret);
2056
2057         /* Get advertisement EEE */
2058         ret = rtl_get_eee_adv(tp);
2059         if (ret < 0)
2060                 goto out;
2061         data->advertised = mmd_eee_adv_to_ethtool_adv_t(ret);
2062         data->eee_enabled = !!data->advertised;
2063
2064         /* Get LP advertisement EEE */
2065         ret = rtl_get_eee_lpadv(tp);
2066         if (ret < 0)
2067                 goto out;
2068         data->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(ret);
2069         data->eee_active = !!(data->advertised & data->lp_advertised);
2070 out:
2071         pm_runtime_put_noidle(d);
2072         return ret < 0 ? ret : 0;
2073 }
2074
2075 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data)
2076 {
2077         struct rtl8169_private *tp = netdev_priv(dev);
2078         struct device *d = tp_to_dev(tp);
2079         int old_adv, adv = 0, cap, ret;
2080
2081         pm_runtime_get_noresume(d);
2082
2083         if (!dev->phydev || !pm_runtime_active(d)) {
2084                 ret = -EOPNOTSUPP;
2085                 goto out;
2086         }
2087
2088         if (dev->phydev->autoneg == AUTONEG_DISABLE ||
2089             dev->phydev->duplex != DUPLEX_FULL) {
2090                 ret = -EPROTONOSUPPORT;
2091                 goto out;
2092         }
2093
2094         /* Get Supported EEE */
2095         ret = rtl_get_eee_supp(tp);
2096         if (ret < 0)
2097                 goto out;
2098         cap = ret;
2099
2100         ret = rtl_get_eee_adv(tp);
2101         if (ret < 0)
2102                 goto out;
2103         old_adv = ret;
2104
2105         if (data->eee_enabled) {
2106                 adv = !data->advertised ? cap :
2107                       ethtool_adv_to_mmd_eee_adv_t(data->advertised) & cap;
2108                 /* Mask prohibited EEE modes */
2109                 adv &= ~dev->phydev->eee_broken_modes;
2110         }
2111
2112         if (old_adv != adv) {
2113                 ret = rtl_set_eee_adv(tp, adv);
2114                 if (ret < 0)
2115                         goto out;
2116
2117                 /* Restart autonegotiation so the new modes get sent to the
2118                  * link partner.
2119                  */
2120                 ret = phy_restart_aneg(dev->phydev);
2121         }
2122
2123 out:
2124         pm_runtime_put_noidle(d);
2125         return ret < 0 ? ret : 0;
2126 }
2127
2128 static const struct ethtool_ops rtl8169_ethtool_ops = {
2129         .get_drvinfo            = rtl8169_get_drvinfo,
2130         .get_regs_len           = rtl8169_get_regs_len,
2131         .get_link               = ethtool_op_get_link,
2132         .get_coalesce           = rtl_get_coalesce,
2133         .set_coalesce           = rtl_set_coalesce,
2134         .get_msglevel           = rtl8169_get_msglevel,
2135         .set_msglevel           = rtl8169_set_msglevel,
2136         .get_regs               = rtl8169_get_regs,
2137         .get_wol                = rtl8169_get_wol,
2138         .set_wol                = rtl8169_set_wol,
2139         .get_strings            = rtl8169_get_strings,
2140         .get_sset_count         = rtl8169_get_sset_count,
2141         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
2142         .get_ts_info            = ethtool_op_get_ts_info,
2143         .nway_reset             = phy_ethtool_nway_reset,
2144         .get_eee                = rtl8169_get_eee,
2145         .set_eee                = rtl8169_set_eee,
2146         .get_link_ksettings     = phy_ethtool_get_link_ksettings,
2147         .set_link_ksettings     = phy_ethtool_set_link_ksettings,
2148 };
2149
2150 static void rtl_enable_eee(struct rtl8169_private *tp)
2151 {
2152         int supported = rtl_get_eee_supp(tp);
2153
2154         if (supported > 0)
2155                 rtl_set_eee_adv(tp, supported);
2156 }
2157
2158 static void rtl8169_get_mac_version(struct rtl8169_private *tp)
2159 {
2160         /*
2161          * The driver currently handles the 8168Bf and the 8168Be identically
2162          * but they can be identified more specifically through the test below
2163          * if needed:
2164          *
2165          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2166          *
2167          * Same thing for the 8101Eb and the 8101Ec:
2168          *
2169          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2170          */
2171         static const struct rtl_mac_info {
2172                 u16 mask;
2173                 u16 val;
2174                 u16 mac_version;
2175         } mac_info[] = {
2176                 /* 8168EP family. */
2177                 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 },
2178                 { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 },
2179                 { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 },
2180
2181                 /* 8168H family. */
2182                 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 },
2183                 { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 },
2184
2185                 /* 8168G family. */
2186                 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 },
2187                 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 },
2188                 { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 },
2189                 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 },
2190
2191                 /* 8168F family. */
2192                 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 },
2193                 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 },
2194                 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 },
2195
2196                 /* 8168E family. */
2197                 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 },
2198                 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 },
2199                 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 },
2200
2201                 /* 8168D family. */
2202                 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 },
2203                 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 },
2204
2205                 /* 8168DP family. */
2206                 { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 },
2207                 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 },
2208                 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 },
2209
2210                 /* 8168C family. */
2211                 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 },
2212                 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 },
2213                 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 },
2214                 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 },
2215                 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 },
2216                 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 },
2217                 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 },
2218
2219                 /* 8168B family. */
2220                 { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12 },
2221                 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 },
2222                 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 },
2223
2224                 /* 8101 family. */
2225                 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 },
2226                 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 },
2227                 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 },
2228                 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 },
2229                 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 },
2230                 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 },
2231                 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 },
2232                 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 },
2233                 { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13 },
2234                 { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10 },
2235                 { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16 },
2236                 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 },
2237                 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 },
2238                 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16 },
2239                 /* FIXME: where did these entries come from ? -- FR */
2240                 { 0xfc8, 0x388, RTL_GIGA_MAC_VER_15 },
2241                 { 0xfc8, 0x308, RTL_GIGA_MAC_VER_14 },
2242
2243                 /* 8110 family. */
2244                 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 },
2245                 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 },
2246                 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 },
2247                 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 },
2248                 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 },
2249
2250                 /* Catch-all */
2251                 { 0x000, 0x000, RTL_GIGA_MAC_NONE   }
2252         };
2253         const struct rtl_mac_info *p = mac_info;
2254         u16 reg = RTL_R32(tp, TxConfig) >> 20;
2255
2256         while ((reg & p->mask) != p->val)
2257                 p++;
2258         tp->mac_version = p->mac_version;
2259
2260         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2261                 dev_err(tp_to_dev(tp), "unknown chip XID %03x\n", reg & 0xfcf);
2262         } else if (!tp->supports_gmii) {
2263                 if (tp->mac_version == RTL_GIGA_MAC_VER_42)
2264                         tp->mac_version = RTL_GIGA_MAC_VER_43;
2265                 else if (tp->mac_version == RTL_GIGA_MAC_VER_45)
2266                         tp->mac_version = RTL_GIGA_MAC_VER_47;
2267                 else if (tp->mac_version == RTL_GIGA_MAC_VER_46)
2268                         tp->mac_version = RTL_GIGA_MAC_VER_48;
2269         }
2270 }
2271
2272 struct phy_reg {
2273         u16 reg;
2274         u16 val;
2275 };
2276
2277 static void __rtl_writephy_batch(struct rtl8169_private *tp,
2278                                  const struct phy_reg *regs, int len)
2279 {
2280         while (len-- > 0) {
2281                 rtl_writephy(tp, regs->reg, regs->val);
2282                 regs++;
2283         }
2284 }
2285
2286 #define rtl_writephy_batch(tp, a) __rtl_writephy_batch(tp, a, ARRAY_SIZE(a))
2287
2288 #define PHY_READ                0x00000000
2289 #define PHY_DATA_OR             0x10000000
2290 #define PHY_DATA_AND            0x20000000
2291 #define PHY_BJMPN               0x30000000
2292 #define PHY_MDIO_CHG            0x40000000
2293 #define PHY_CLEAR_READCOUNT     0x70000000
2294 #define PHY_WRITE               0x80000000
2295 #define PHY_READCOUNT_EQ_SKIP   0x90000000
2296 #define PHY_COMP_EQ_SKIPN       0xa0000000
2297 #define PHY_COMP_NEQ_SKIPN      0xb0000000
2298 #define PHY_WRITE_PREVIOUS      0xc0000000
2299 #define PHY_SKIPN               0xd0000000
2300 #define PHY_DELAY_MS            0xe0000000
2301
2302 struct fw_info {
2303         u32     magic;
2304         char    version[RTL_VER_SIZE];
2305         __le32  fw_start;
2306         __le32  fw_len;
2307         u8      chksum;
2308 } __packed;
2309
2310 #define FW_OPCODE_SIZE  sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2311
2312 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2313 {
2314         const struct firmware *fw = rtl_fw->fw;
2315         struct fw_info *fw_info = (struct fw_info *)fw->data;
2316         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2317         char *version = rtl_fw->version;
2318         bool rc = false;
2319
2320         if (fw->size < FW_OPCODE_SIZE)
2321                 goto out;
2322
2323         if (!fw_info->magic) {
2324                 size_t i, size, start;
2325                 u8 checksum = 0;
2326
2327                 if (fw->size < sizeof(*fw_info))
2328                         goto out;
2329
2330                 for (i = 0; i < fw->size; i++)
2331                         checksum += fw->data[i];
2332                 if (checksum != 0)
2333                         goto out;
2334
2335                 start = le32_to_cpu(fw_info->fw_start);
2336                 if (start > fw->size)
2337                         goto out;
2338
2339                 size = le32_to_cpu(fw_info->fw_len);
2340                 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2341                         goto out;
2342
2343                 memcpy(version, fw_info->version, RTL_VER_SIZE);
2344
2345                 pa->code = (__le32 *)(fw->data + start);
2346                 pa->size = size;
2347         } else {
2348                 if (fw->size % FW_OPCODE_SIZE)
2349                         goto out;
2350
2351                 strlcpy(version, tp->fw_name, RTL_VER_SIZE);
2352
2353                 pa->code = (__le32 *)fw->data;
2354                 pa->size = fw->size / FW_OPCODE_SIZE;
2355         }
2356         version[RTL_VER_SIZE - 1] = 0;
2357
2358         rc = true;
2359 out:
2360         return rc;
2361 }
2362
2363 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2364                            struct rtl_fw_phy_action *pa)
2365 {
2366         bool rc = false;
2367         size_t index;
2368
2369         for (index = 0; index < pa->size; index++) {
2370                 u32 action = le32_to_cpu(pa->code[index]);
2371                 u32 regno = (action & 0x0fff0000) >> 16;
2372
2373                 switch(action & 0xf0000000) {
2374                 case PHY_READ:
2375                 case PHY_DATA_OR:
2376                 case PHY_DATA_AND:
2377                 case PHY_MDIO_CHG:
2378                 case PHY_CLEAR_READCOUNT:
2379                 case PHY_WRITE:
2380                 case PHY_WRITE_PREVIOUS:
2381                 case PHY_DELAY_MS:
2382                         break;
2383
2384                 case PHY_BJMPN:
2385                         if (regno > index) {
2386                                 netif_err(tp, ifup, tp->dev,
2387                                           "Out of range of firmware\n");
2388                                 goto out;
2389                         }
2390                         break;
2391                 case PHY_READCOUNT_EQ_SKIP:
2392                         if (index + 2 >= pa->size) {
2393                                 netif_err(tp, ifup, tp->dev,
2394                                           "Out of range of firmware\n");
2395                                 goto out;
2396                         }
2397                         break;
2398                 case PHY_COMP_EQ_SKIPN:
2399                 case PHY_COMP_NEQ_SKIPN:
2400                 case PHY_SKIPN:
2401                         if (index + 1 + regno >= pa->size) {
2402                                 netif_err(tp, ifup, tp->dev,
2403                                           "Out of range of firmware\n");
2404                                 goto out;
2405                         }
2406                         break;
2407
2408                 default:
2409                         netif_err(tp, ifup, tp->dev,
2410                                   "Invalid action 0x%08x\n", action);
2411                         goto out;
2412                 }
2413         }
2414         rc = true;
2415 out:
2416         return rc;
2417 }
2418
2419 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2420 {
2421         struct net_device *dev = tp->dev;
2422         int rc = -EINVAL;
2423
2424         if (!rtl_fw_format_ok(tp, rtl_fw)) {
2425                 netif_err(tp, ifup, dev, "invalid firmware\n");
2426                 goto out;
2427         }
2428
2429         if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2430                 rc = 0;
2431 out:
2432         return rc;
2433 }
2434
2435 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2436 {
2437         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2438         struct mdio_ops org, *ops = &tp->mdio_ops;
2439         u32 predata, count;
2440         size_t index;
2441
2442         predata = count = 0;
2443         org.write = ops->write;
2444         org.read = ops->read;
2445
2446         for (index = 0; index < pa->size; ) {
2447                 u32 action = le32_to_cpu(pa->code[index]);
2448                 u32 data = action & 0x0000ffff;
2449                 u32 regno = (action & 0x0fff0000) >> 16;
2450
2451                 if (!action)
2452                         break;
2453
2454                 switch(action & 0xf0000000) {
2455                 case PHY_READ:
2456                         predata = rtl_readphy(tp, regno);
2457                         count++;
2458                         index++;
2459                         break;
2460                 case PHY_DATA_OR:
2461                         predata |= data;
2462                         index++;
2463                         break;
2464                 case PHY_DATA_AND:
2465                         predata &= data;
2466                         index++;
2467                         break;
2468                 case PHY_BJMPN:
2469                         index -= regno;
2470                         break;
2471                 case PHY_MDIO_CHG:
2472                         if (data == 0) {
2473                                 ops->write = org.write;
2474                                 ops->read = org.read;
2475                         } else if (data == 1) {
2476                                 ops->write = mac_mcu_write;
2477                                 ops->read = mac_mcu_read;
2478                         }
2479
2480                         index++;
2481                         break;
2482                 case PHY_CLEAR_READCOUNT:
2483                         count = 0;
2484                         index++;
2485                         break;
2486                 case PHY_WRITE:
2487                         rtl_writephy(tp, regno, data);
2488                         index++;
2489                         break;
2490                 case PHY_READCOUNT_EQ_SKIP:
2491                         index += (count == data) ? 2 : 1;
2492                         break;
2493                 case PHY_COMP_EQ_SKIPN:
2494                         if (predata == data)
2495                                 index += regno;
2496                         index++;
2497                         break;
2498                 case PHY_COMP_NEQ_SKIPN:
2499                         if (predata != data)
2500                                 index += regno;
2501                         index++;
2502                         break;
2503                 case PHY_WRITE_PREVIOUS:
2504                         rtl_writephy(tp, regno, predata);
2505                         index++;
2506                         break;
2507                 case PHY_SKIPN:
2508                         index += regno + 1;
2509                         break;
2510                 case PHY_DELAY_MS:
2511                         mdelay(data);
2512                         index++;
2513                         break;
2514
2515                 default:
2516                         BUG();
2517                 }
2518         }
2519
2520         ops->write = org.write;
2521         ops->read = org.read;
2522 }
2523
2524 static void rtl_release_firmware(struct rtl8169_private *tp)
2525 {
2526         if (tp->rtl_fw) {
2527                 release_firmware(tp->rtl_fw->fw);
2528                 kfree(tp->rtl_fw);
2529                 tp->rtl_fw = NULL;
2530         }
2531 }
2532
2533 static void rtl_apply_firmware(struct rtl8169_private *tp)
2534 {
2535         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2536         if (tp->rtl_fw)
2537                 rtl_phy_write_fw(tp, tp->rtl_fw);
2538 }
2539
2540 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2541 {
2542         if (rtl_readphy(tp, reg) != val)
2543                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2544         else
2545                 rtl_apply_firmware(tp);
2546 }
2547
2548 static void rtl8168_config_eee_mac(struct rtl8169_private *tp)
2549 {
2550         /* Adjust EEE LED frequency */
2551         if (tp->mac_version != RTL_GIGA_MAC_VER_38)
2552                 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
2553
2554         rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_1111, 0x0003);
2555 }
2556
2557 static void rtl8168f_config_eee_phy(struct rtl8169_private *tp)
2558 {
2559         struct phy_device *phydev = tp->phydev;
2560
2561         phy_write(phydev, 0x1f, 0x0007);
2562         phy_write(phydev, 0x1e, 0x0020);
2563         phy_set_bits(phydev, 0x15, BIT(8));
2564
2565         phy_write(phydev, 0x1f, 0x0005);
2566         phy_write(phydev, 0x05, 0x8b85);
2567         phy_set_bits(phydev, 0x06, BIT(13));
2568
2569         phy_write(phydev, 0x1f, 0x0000);
2570 }
2571
2572 static void rtl8168g_config_eee_phy(struct rtl8169_private *tp)
2573 {
2574         phy_write(tp->phydev, 0x1f, 0x0a43);
2575         phy_set_bits(tp->phydev, 0x11, BIT(4));
2576         phy_write(tp->phydev, 0x1f, 0x0000);
2577 }
2578
2579 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2580 {
2581         static const struct phy_reg phy_reg_init[] = {
2582                 { 0x1f, 0x0001 },
2583                 { 0x06, 0x006e },
2584                 { 0x08, 0x0708 },
2585                 { 0x15, 0x4000 },
2586                 { 0x18, 0x65c7 },
2587
2588                 { 0x1f, 0x0001 },
2589                 { 0x03, 0x00a1 },
2590                 { 0x02, 0x0008 },
2591                 { 0x01, 0x0120 },
2592                 { 0x00, 0x1000 },
2593                 { 0x04, 0x0800 },
2594                 { 0x04, 0x0000 },
2595
2596                 { 0x03, 0xff41 },
2597                 { 0x02, 0xdf60 },
2598                 { 0x01, 0x0140 },
2599                 { 0x00, 0x0077 },
2600                 { 0x04, 0x7800 },
2601                 { 0x04, 0x7000 },
2602
2603                 { 0x03, 0x802f },
2604                 { 0x02, 0x4f02 },
2605                 { 0x01, 0x0409 },
2606                 { 0x00, 0xf0f9 },
2607                 { 0x04, 0x9800 },
2608                 { 0x04, 0x9000 },
2609
2610                 { 0x03, 0xdf01 },
2611                 { 0x02, 0xdf20 },
2612                 { 0x01, 0xff95 },
2613                 { 0x00, 0xba00 },
2614                 { 0x04, 0xa800 },
2615                 { 0x04, 0xa000 },
2616
2617                 { 0x03, 0xff41 },
2618                 { 0x02, 0xdf20 },
2619                 { 0x01, 0x0140 },
2620                 { 0x00, 0x00bb },
2621                 { 0x04, 0xb800 },
2622                 { 0x04, 0xb000 },
2623
2624                 { 0x03, 0xdf41 },
2625                 { 0x02, 0xdc60 },
2626                 { 0x01, 0x6340 },
2627                 { 0x00, 0x007d },
2628                 { 0x04, 0xd800 },
2629                 { 0x04, 0xd000 },
2630
2631                 { 0x03, 0xdf01 },
2632                 { 0x02, 0xdf20 },
2633                 { 0x01, 0x100a },
2634                 { 0x00, 0xa0ff },
2635                 { 0x04, 0xf800 },
2636                 { 0x04, 0xf000 },
2637
2638                 { 0x1f, 0x0000 },
2639                 { 0x0b, 0x0000 },
2640                 { 0x00, 0x9200 }
2641         };
2642
2643         rtl_writephy_batch(tp, phy_reg_init);
2644 }
2645
2646 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2647 {
2648         static const struct phy_reg phy_reg_init[] = {
2649                 { 0x1f, 0x0002 },
2650                 { 0x01, 0x90d0 },
2651                 { 0x1f, 0x0000 }
2652         };
2653
2654         rtl_writephy_batch(tp, phy_reg_init);
2655 }
2656
2657 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2658 {
2659         struct pci_dev *pdev = tp->pci_dev;
2660
2661         if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2662             (pdev->subsystem_device != 0xe000))
2663                 return;
2664
2665         rtl_writephy(tp, 0x1f, 0x0001);
2666         rtl_writephy(tp, 0x10, 0xf01b);
2667         rtl_writephy(tp, 0x1f, 0x0000);
2668 }
2669
2670 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2671 {
2672         static const struct phy_reg phy_reg_init[] = {
2673                 { 0x1f, 0x0001 },
2674                 { 0x04, 0x0000 },
2675                 { 0x03, 0x00a1 },
2676                 { 0x02, 0x0008 },
2677                 { 0x01, 0x0120 },
2678                 { 0x00, 0x1000 },
2679                 { 0x04, 0x0800 },
2680                 { 0x04, 0x9000 },
2681                 { 0x03, 0x802f },
2682                 { 0x02, 0x4f02 },
2683                 { 0x01, 0x0409 },
2684                 { 0x00, 0xf099 },
2685                 { 0x04, 0x9800 },
2686                 { 0x04, 0xa000 },
2687                 { 0x03, 0xdf01 },
2688                 { 0x02, 0xdf20 },
2689                 { 0x01, 0xff95 },
2690                 { 0x00, 0xba00 },
2691                 { 0x04, 0xa800 },
2692                 { 0x04, 0xf000 },
2693                 { 0x03, 0xdf01 },
2694                 { 0x02, 0xdf20 },
2695                 { 0x01, 0x101a },
2696                 { 0x00, 0xa0ff },
2697                 { 0x04, 0xf800 },
2698                 { 0x04, 0x0000 },
2699                 { 0x1f, 0x0000 },
2700
2701                 { 0x1f, 0x0001 },
2702                 { 0x10, 0xf41b },
2703                 { 0x14, 0xfb54 },
2704                 { 0x18, 0xf5c7 },
2705                 { 0x1f, 0x0000 },
2706
2707                 { 0x1f, 0x0001 },
2708                 { 0x17, 0x0cc0 },
2709                 { 0x1f, 0x0000 }
2710         };
2711
2712         rtl_writephy_batch(tp, phy_reg_init);
2713
2714         rtl8169scd_hw_phy_config_quirk(tp);
2715 }
2716
2717 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2718 {
2719         static const struct phy_reg phy_reg_init[] = {
2720                 { 0x1f, 0x0001 },
2721                 { 0x04, 0x0000 },
2722                 { 0x03, 0x00a1 },
2723                 { 0x02, 0x0008 },
2724                 { 0x01, 0x0120 },
2725                 { 0x00, 0x1000 },
2726                 { 0x04, 0x0800 },
2727                 { 0x04, 0x9000 },
2728                 { 0x03, 0x802f },
2729                 { 0x02, 0x4f02 },
2730                 { 0x01, 0x0409 },
2731                 { 0x00, 0xf099 },
2732                 { 0x04, 0x9800 },
2733                 { 0x04, 0xa000 },
2734                 { 0x03, 0xdf01 },
2735                 { 0x02, 0xdf20 },
2736                 { 0x01, 0xff95 },
2737                 { 0x00, 0xba00 },
2738                 { 0x04, 0xa800 },
2739                 { 0x04, 0xf000 },
2740                 { 0x03, 0xdf01 },
2741                 { 0x02, 0xdf20 },
2742                 { 0x01, 0x101a },
2743                 { 0x00, 0xa0ff },
2744                 { 0x04, 0xf800 },
2745                 { 0x04, 0x0000 },
2746                 { 0x1f, 0x0000 },
2747
2748                 { 0x1f, 0x0001 },
2749                 { 0x0b, 0x8480 },
2750                 { 0x1f, 0x0000 },
2751
2752                 { 0x1f, 0x0001 },
2753                 { 0x18, 0x67c7 },
2754                 { 0x04, 0x2000 },
2755                 { 0x03, 0x002f },
2756                 { 0x02, 0x4360 },
2757                 { 0x01, 0x0109 },
2758                 { 0x00, 0x3022 },
2759                 { 0x04, 0x2800 },
2760                 { 0x1f, 0x0000 },
2761
2762                 { 0x1f, 0x0001 },
2763                 { 0x17, 0x0cc0 },
2764                 { 0x1f, 0x0000 }
2765         };
2766
2767         rtl_writephy_batch(tp, phy_reg_init);
2768 }
2769
2770 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2771 {
2772         static const struct phy_reg phy_reg_init[] = {
2773                 { 0x10, 0xf41b },
2774                 { 0x1f, 0x0000 }
2775         };
2776
2777         rtl_writephy(tp, 0x1f, 0x0001);
2778         rtl_patchphy(tp, 0x16, 1 << 0);
2779
2780         rtl_writephy_batch(tp, phy_reg_init);
2781 }
2782
2783 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2784 {
2785         static const struct phy_reg phy_reg_init[] = {
2786                 { 0x1f, 0x0001 },
2787                 { 0x10, 0xf41b },
2788                 { 0x1f, 0x0000 }
2789         };
2790
2791         rtl_writephy_batch(tp, phy_reg_init);
2792 }
2793
2794 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2795 {
2796         static const struct phy_reg phy_reg_init[] = {
2797                 { 0x1f, 0x0000 },
2798                 { 0x1d, 0x0f00 },
2799                 { 0x1f, 0x0002 },
2800                 { 0x0c, 0x1ec8 },
2801                 { 0x1f, 0x0000 }
2802         };
2803
2804         rtl_writephy_batch(tp, phy_reg_init);
2805 }
2806
2807 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2808 {
2809         static const struct phy_reg phy_reg_init[] = {
2810                 { 0x1f, 0x0001 },
2811                 { 0x1d, 0x3d98 },
2812                 { 0x1f, 0x0000 }
2813         };
2814
2815         rtl_writephy(tp, 0x1f, 0x0000);
2816         rtl_patchphy(tp, 0x14, 1 << 5);
2817         rtl_patchphy(tp, 0x0d, 1 << 5);
2818
2819         rtl_writephy_batch(tp, phy_reg_init);
2820 }
2821
2822 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2823 {
2824         static const struct phy_reg phy_reg_init[] = {
2825                 { 0x1f, 0x0001 },
2826                 { 0x12, 0x2300 },
2827                 { 0x1f, 0x0002 },
2828                 { 0x00, 0x88d4 },
2829                 { 0x01, 0x82b1 },
2830                 { 0x03, 0x7002 },
2831                 { 0x08, 0x9e30 },
2832                 { 0x09, 0x01f0 },
2833                 { 0x0a, 0x5500 },
2834                 { 0x0c, 0x00c8 },
2835                 { 0x1f, 0x0003 },
2836                 { 0x12, 0xc096 },
2837                 { 0x16, 0x000a },
2838                 { 0x1f, 0x0000 },
2839                 { 0x1f, 0x0000 },
2840                 { 0x09, 0x2000 },
2841                 { 0x09, 0x0000 }
2842         };
2843
2844         rtl_writephy_batch(tp, phy_reg_init);
2845
2846         rtl_patchphy(tp, 0x14, 1 << 5);
2847         rtl_patchphy(tp, 0x0d, 1 << 5);
2848         rtl_writephy(tp, 0x1f, 0x0000);
2849 }
2850
2851 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2852 {
2853         static const struct phy_reg phy_reg_init[] = {
2854                 { 0x1f, 0x0001 },
2855                 { 0x12, 0x2300 },
2856                 { 0x03, 0x802f },
2857                 { 0x02, 0x4f02 },
2858                 { 0x01, 0x0409 },
2859                 { 0x00, 0xf099 },
2860                 { 0x04, 0x9800 },
2861                 { 0x04, 0x9000 },
2862                 { 0x1d, 0x3d98 },
2863                 { 0x1f, 0x0002 },
2864                 { 0x0c, 0x7eb8 },
2865                 { 0x06, 0x0761 },
2866                 { 0x1f, 0x0003 },
2867                 { 0x16, 0x0f0a },
2868                 { 0x1f, 0x0000 }
2869         };
2870
2871         rtl_writephy_batch(tp, phy_reg_init);
2872
2873         rtl_patchphy(tp, 0x16, 1 << 0);
2874         rtl_patchphy(tp, 0x14, 1 << 5);
2875         rtl_patchphy(tp, 0x0d, 1 << 5);
2876         rtl_writephy(tp, 0x1f, 0x0000);
2877 }
2878
2879 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2880 {
2881         static const struct phy_reg phy_reg_init[] = {
2882                 { 0x1f, 0x0001 },
2883                 { 0x12, 0x2300 },
2884                 { 0x1d, 0x3d98 },
2885                 { 0x1f, 0x0002 },
2886                 { 0x0c, 0x7eb8 },
2887                 { 0x06, 0x5461 },
2888                 { 0x1f, 0x0003 },
2889                 { 0x16, 0x0f0a },
2890                 { 0x1f, 0x0000 }
2891         };
2892
2893         rtl_writephy_batch(tp, phy_reg_init);
2894
2895         rtl_patchphy(tp, 0x16, 1 << 0);
2896         rtl_patchphy(tp, 0x14, 1 << 5);
2897         rtl_patchphy(tp, 0x0d, 1 << 5);
2898         rtl_writephy(tp, 0x1f, 0x0000);
2899 }
2900
2901 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2902 {
2903         rtl8168c_3_hw_phy_config(tp);
2904 }
2905
2906 static const struct phy_reg rtl8168d_1_phy_reg_init_0[] = {
2907         /* Channel Estimation */
2908         { 0x1f, 0x0001 },
2909         { 0x06, 0x4064 },
2910         { 0x07, 0x2863 },
2911         { 0x08, 0x059c },
2912         { 0x09, 0x26b4 },
2913         { 0x0a, 0x6a19 },
2914         { 0x0b, 0xdcc8 },
2915         { 0x10, 0xf06d },
2916         { 0x14, 0x7f68 },
2917         { 0x18, 0x7fd9 },
2918         { 0x1c, 0xf0ff },
2919         { 0x1d, 0x3d9c },
2920         { 0x1f, 0x0003 },
2921         { 0x12, 0xf49f },
2922         { 0x13, 0x070b },
2923         { 0x1a, 0x05ad },
2924         { 0x14, 0x94c0 },
2925
2926         /*
2927          * Tx Error Issue
2928          * Enhance line driver power
2929          */
2930         { 0x1f, 0x0002 },
2931         { 0x06, 0x5561 },
2932         { 0x1f, 0x0005 },
2933         { 0x05, 0x8332 },
2934         { 0x06, 0x5561 },
2935
2936         /*
2937          * Can not link to 1Gbps with bad cable
2938          * Decrease SNR threshold form 21.07dB to 19.04dB
2939          */
2940         { 0x1f, 0x0001 },
2941         { 0x17, 0x0cc0 },
2942
2943         { 0x1f, 0x0000 },
2944         { 0x0d, 0xf880 }
2945 };
2946
2947 static const struct phy_reg rtl8168d_1_phy_reg_init_1[] = {
2948         { 0x1f, 0x0002 },
2949         { 0x05, 0x669a },
2950         { 0x1f, 0x0005 },
2951         { 0x05, 0x8330 },
2952         { 0x06, 0x669a },
2953         { 0x1f, 0x0002 }
2954 };
2955
2956 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2957 {
2958         rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_0);
2959
2960         /*
2961          * Rx Error Issue
2962          * Fine Tune Switching regulator parameter
2963          */
2964         rtl_writephy(tp, 0x1f, 0x0002);
2965         rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
2966         rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
2967
2968         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2969                 int val;
2970
2971                 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_1);
2972
2973                 val = rtl_readphy(tp, 0x0d);
2974
2975                 if ((val & 0x00ff) != 0x006c) {
2976                         static const u32 set[] = {
2977                                 0x0065, 0x0066, 0x0067, 0x0068,
2978                                 0x0069, 0x006a, 0x006b, 0x006c
2979                         };
2980                         int i;
2981
2982                         rtl_writephy(tp, 0x1f, 0x0002);
2983
2984                         val &= 0xff00;
2985                         for (i = 0; i < ARRAY_SIZE(set); i++)
2986                                 rtl_writephy(tp, 0x0d, val | set[i]);
2987                 }
2988         } else {
2989                 static const struct phy_reg phy_reg_init[] = {
2990                         { 0x1f, 0x0002 },
2991                         { 0x05, 0x6662 },
2992                         { 0x1f, 0x0005 },
2993                         { 0x05, 0x8330 },
2994                         { 0x06, 0x6662 }
2995                 };
2996
2997                 rtl_writephy_batch(tp, phy_reg_init);
2998         }
2999
3000         /* RSET couple improve */
3001         rtl_writephy(tp, 0x1f, 0x0002);
3002         rtl_patchphy(tp, 0x0d, 0x0300);
3003         rtl_patchphy(tp, 0x0f, 0x0010);
3004
3005         /* Fine tune PLL performance */
3006         rtl_writephy(tp, 0x1f, 0x0002);
3007         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3008         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3009
3010         rtl_writephy(tp, 0x1f, 0x0005);
3011         rtl_writephy(tp, 0x05, 0x001b);
3012
3013         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
3014
3015         rtl_writephy(tp, 0x1f, 0x0000);
3016 }
3017
3018 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
3019 {
3020         rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_0);
3021
3022         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
3023                 int val;
3024
3025                 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_1);
3026
3027                 val = rtl_readphy(tp, 0x0d);
3028                 if ((val & 0x00ff) != 0x006c) {
3029                         static const u32 set[] = {
3030                                 0x0065, 0x0066, 0x0067, 0x0068,
3031                                 0x0069, 0x006a, 0x006b, 0x006c
3032                         };
3033                         int i;
3034
3035                         rtl_writephy(tp, 0x1f, 0x0002);
3036
3037                         val &= 0xff00;
3038                         for (i = 0; i < ARRAY_SIZE(set); i++)
3039                                 rtl_writephy(tp, 0x0d, val | set[i]);
3040                 }
3041         } else {
3042                 static const struct phy_reg phy_reg_init[] = {
3043                         { 0x1f, 0x0002 },
3044                         { 0x05, 0x2642 },
3045                         { 0x1f, 0x0005 },
3046                         { 0x05, 0x8330 },
3047                         { 0x06, 0x2642 }
3048                 };
3049
3050                 rtl_writephy_batch(tp, phy_reg_init);
3051         }
3052
3053         /* Fine tune PLL performance */
3054         rtl_writephy(tp, 0x1f, 0x0002);
3055         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3056         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3057
3058         /* Switching regulator Slew rate */
3059         rtl_writephy(tp, 0x1f, 0x0002);
3060         rtl_patchphy(tp, 0x0f, 0x0017);
3061
3062         rtl_writephy(tp, 0x1f, 0x0005);
3063         rtl_writephy(tp, 0x05, 0x001b);
3064
3065         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
3066
3067         rtl_writephy(tp, 0x1f, 0x0000);
3068 }
3069
3070 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
3071 {
3072         static const struct phy_reg phy_reg_init[] = {
3073                 { 0x1f, 0x0002 },
3074                 { 0x10, 0x0008 },
3075                 { 0x0d, 0x006c },
3076
3077                 { 0x1f, 0x0000 },
3078                 { 0x0d, 0xf880 },
3079
3080                 { 0x1f, 0x0001 },
3081                 { 0x17, 0x0cc0 },
3082
3083                 { 0x1f, 0x0001 },
3084                 { 0x0b, 0xa4d8 },
3085                 { 0x09, 0x281c },
3086                 { 0x07, 0x2883 },
3087                 { 0x0a, 0x6b35 },
3088                 { 0x1d, 0x3da4 },
3089                 { 0x1c, 0xeffd },
3090                 { 0x14, 0x7f52 },
3091                 { 0x18, 0x7fc6 },
3092                 { 0x08, 0x0601 },
3093                 { 0x06, 0x4063 },
3094                 { 0x10, 0xf074 },
3095                 { 0x1f, 0x0003 },
3096                 { 0x13, 0x0789 },
3097                 { 0x12, 0xf4bd },
3098                 { 0x1a, 0x04fd },
3099                 { 0x14, 0x84b0 },
3100                 { 0x1f, 0x0000 },
3101                 { 0x00, 0x9200 },
3102
3103                 { 0x1f, 0x0005 },
3104                 { 0x01, 0x0340 },
3105                 { 0x1f, 0x0001 },
3106                 { 0x04, 0x4000 },
3107                 { 0x03, 0x1d21 },
3108                 { 0x02, 0x0c32 },
3109                 { 0x01, 0x0200 },
3110                 { 0x00, 0x5554 },
3111                 { 0x04, 0x4800 },
3112                 { 0x04, 0x4000 },
3113                 { 0x04, 0xf000 },
3114                 { 0x03, 0xdf01 },
3115                 { 0x02, 0xdf20 },
3116                 { 0x01, 0x101a },
3117                 { 0x00, 0xa0ff },
3118                 { 0x04, 0xf800 },
3119                 { 0x04, 0xf000 },
3120                 { 0x1f, 0x0000 },
3121
3122                 { 0x1f, 0x0007 },
3123                 { 0x1e, 0x0023 },
3124                 { 0x16, 0x0000 },
3125                 { 0x1f, 0x0000 }
3126         };
3127
3128         rtl_writephy_batch(tp, phy_reg_init);
3129 }
3130
3131 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3132 {
3133         static const struct phy_reg phy_reg_init[] = {
3134                 { 0x1f, 0x0001 },
3135                 { 0x17, 0x0cc0 },
3136
3137                 { 0x1f, 0x0007 },
3138                 { 0x1e, 0x002d },
3139                 { 0x18, 0x0040 },
3140                 { 0x1f, 0x0000 }
3141         };
3142
3143         rtl_writephy_batch(tp, phy_reg_init);
3144         rtl_patchphy(tp, 0x0d, 1 << 5);
3145 }
3146
3147 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
3148 {
3149         static const struct phy_reg phy_reg_init[] = {
3150                 /* Enable Delay cap */
3151                 { 0x1f, 0x0005 },
3152                 { 0x05, 0x8b80 },
3153                 { 0x06, 0xc896 },
3154                 { 0x1f, 0x0000 },
3155
3156                 /* Channel estimation fine tune */
3157                 { 0x1f, 0x0001 },
3158                 { 0x0b, 0x6c20 },
3159                 { 0x07, 0x2872 },
3160                 { 0x1c, 0xefff },
3161                 { 0x1f, 0x0003 },
3162                 { 0x14, 0x6420 },
3163                 { 0x1f, 0x0000 },
3164
3165                 /* Update PFM & 10M TX idle timer */
3166                 { 0x1f, 0x0007 },
3167                 { 0x1e, 0x002f },
3168                 { 0x15, 0x1919 },
3169                 { 0x1f, 0x0000 },
3170
3171                 { 0x1f, 0x0007 },
3172                 { 0x1e, 0x00ac },
3173                 { 0x18, 0x0006 },
3174                 { 0x1f, 0x0000 }
3175         };
3176
3177         rtl_apply_firmware(tp);
3178
3179         rtl_writephy_batch(tp, phy_reg_init);
3180
3181         /* DCO enable for 10M IDLE Power */
3182         rtl_writephy(tp, 0x1f, 0x0007);
3183         rtl_writephy(tp, 0x1e, 0x0023);
3184         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3185         rtl_writephy(tp, 0x1f, 0x0000);
3186
3187         /* For impedance matching */
3188         rtl_writephy(tp, 0x1f, 0x0002);
3189         rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
3190         rtl_writephy(tp, 0x1f, 0x0000);
3191
3192         /* PHY auto speed down */
3193         rtl_writephy(tp, 0x1f, 0x0007);
3194         rtl_writephy(tp, 0x1e, 0x002d);
3195         rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
3196         rtl_writephy(tp, 0x1f, 0x0000);
3197         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3198
3199         rtl_writephy(tp, 0x1f, 0x0005);
3200         rtl_writephy(tp, 0x05, 0x8b86);
3201         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3202         rtl_writephy(tp, 0x1f, 0x0000);
3203
3204         rtl_writephy(tp, 0x1f, 0x0005);
3205         rtl_writephy(tp, 0x05, 0x8b85);
3206         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3207         rtl_writephy(tp, 0x1f, 0x0007);
3208         rtl_writephy(tp, 0x1e, 0x0020);
3209         rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
3210         rtl_writephy(tp, 0x1f, 0x0006);
3211         rtl_writephy(tp, 0x00, 0x5a00);
3212         rtl_writephy(tp, 0x1f, 0x0000);
3213         rtl_writephy(tp, 0x0d, 0x0007);
3214         rtl_writephy(tp, 0x0e, 0x003c);
3215         rtl_writephy(tp, 0x0d, 0x4007);
3216         rtl_writephy(tp, 0x0e, 0x0000);
3217         rtl_writephy(tp, 0x0d, 0x0000);
3218 }
3219
3220 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3221 {
3222         const u16 w[] = {
3223                 addr[0] | (addr[1] << 8),
3224                 addr[2] | (addr[3] << 8),
3225                 addr[4] | (addr[5] << 8)
3226         };
3227
3228         rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, w[0] | (w[1] << 16));
3229         rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, w[2]);
3230         rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, w[0] << 16);
3231         rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, w[1] | (w[2] << 16));
3232 }
3233
3234 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3235 {
3236         static const struct phy_reg phy_reg_init[] = {
3237                 /* Enable Delay cap */
3238                 { 0x1f, 0x0004 },
3239                 { 0x1f, 0x0007 },
3240                 { 0x1e, 0x00ac },
3241                 { 0x18, 0x0006 },
3242                 { 0x1f, 0x0002 },
3243                 { 0x1f, 0x0000 },
3244                 { 0x1f, 0x0000 },
3245
3246                 /* Channel estimation fine tune */
3247                 { 0x1f, 0x0003 },
3248                 { 0x09, 0xa20f },
3249                 { 0x1f, 0x0000 },
3250                 { 0x1f, 0x0000 },
3251
3252                 /* Green Setting */
3253                 { 0x1f, 0x0005 },
3254                 { 0x05, 0x8b5b },
3255                 { 0x06, 0x9222 },
3256                 { 0x05, 0x8b6d },
3257                 { 0x06, 0x8000 },
3258                 { 0x05, 0x8b76 },
3259                 { 0x06, 0x8000 },
3260                 { 0x1f, 0x0000 }
3261         };
3262
3263         rtl_apply_firmware(tp);
3264
3265         rtl_writephy_batch(tp, phy_reg_init);
3266
3267         /* For 4-corner performance improve */
3268         rtl_writephy(tp, 0x1f, 0x0005);
3269         rtl_writephy(tp, 0x05, 0x8b80);
3270         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3271         rtl_writephy(tp, 0x1f, 0x0000);
3272
3273         /* PHY auto speed down */
3274         rtl_writephy(tp, 0x1f, 0x0004);
3275         rtl_writephy(tp, 0x1f, 0x0007);
3276         rtl_writephy(tp, 0x1e, 0x002d);
3277         rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3278         rtl_writephy(tp, 0x1f, 0x0002);
3279         rtl_writephy(tp, 0x1f, 0x0000);
3280         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3281
3282         /* improve 10M EEE waveform */
3283         rtl_writephy(tp, 0x1f, 0x0005);
3284         rtl_writephy(tp, 0x05, 0x8b86);
3285         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3286         rtl_writephy(tp, 0x1f, 0x0000);
3287
3288         /* Improve 2-pair detection performance */
3289         rtl_writephy(tp, 0x1f, 0x0005);
3290         rtl_writephy(tp, 0x05, 0x8b85);
3291         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3292         rtl_writephy(tp, 0x1f, 0x0000);
3293
3294         rtl8168f_config_eee_phy(tp);
3295         rtl_enable_eee(tp);
3296
3297         /* Green feature */
3298         rtl_writephy(tp, 0x1f, 0x0003);
3299         rtl_w0w1_phy(tp, 0x19, 0x0001, 0x0000);
3300         rtl_w0w1_phy(tp, 0x10, 0x0400, 0x0000);
3301         rtl_writephy(tp, 0x1f, 0x0000);
3302         rtl_writephy(tp, 0x1f, 0x0005);
3303         rtl_w0w1_phy(tp, 0x01, 0x0100, 0x0000);
3304         rtl_writephy(tp, 0x1f, 0x0000);
3305
3306         /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3307         rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3308 }
3309
3310 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3311 {
3312         /* For 4-corner performance improve */
3313         rtl_writephy(tp, 0x1f, 0x0005);
3314         rtl_writephy(tp, 0x05, 0x8b80);
3315         rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
3316         rtl_writephy(tp, 0x1f, 0x0000);
3317
3318         /* PHY auto speed down */
3319         rtl_writephy(tp, 0x1f, 0x0007);
3320         rtl_writephy(tp, 0x1e, 0x002d);
3321         rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3322         rtl_writephy(tp, 0x1f, 0x0000);
3323         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3324
3325         /* Improve 10M EEE waveform */
3326         rtl_writephy(tp, 0x1f, 0x0005);
3327         rtl_writephy(tp, 0x05, 0x8b86);
3328         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3329         rtl_writephy(tp, 0x1f, 0x0000);
3330
3331         rtl8168f_config_eee_phy(tp);
3332         rtl_enable_eee(tp);
3333 }
3334
3335 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3336 {
3337         static const struct phy_reg phy_reg_init[] = {
3338                 /* Channel estimation fine tune */
3339                 { 0x1f, 0x0003 },
3340                 { 0x09, 0xa20f },
3341                 { 0x1f, 0x0000 },
3342
3343                 /* Modify green table for giga & fnet */
3344                 { 0x1f, 0x0005 },
3345                 { 0x05, 0x8b55 },
3346                 { 0x06, 0x0000 },
3347                 { 0x05, 0x8b5e },
3348                 { 0x06, 0x0000 },
3349                 { 0x05, 0x8b67 },
3350                 { 0x06, 0x0000 },
3351                 { 0x05, 0x8b70 },
3352                 { 0x06, 0x0000 },
3353                 { 0x1f, 0x0000 },
3354                 { 0x1f, 0x0007 },
3355                 { 0x1e, 0x0078 },
3356                 { 0x17, 0x0000 },
3357                 { 0x19, 0x00fb },
3358                 { 0x1f, 0x0000 },
3359
3360                 /* Modify green table for 10M */
3361                 { 0x1f, 0x0005 },
3362                 { 0x05, 0x8b79 },
3363                 { 0x06, 0xaa00 },
3364                 { 0x1f, 0x0000 },
3365
3366                 /* Disable hiimpedance detection (RTCT) */
3367                 { 0x1f, 0x0003 },
3368                 { 0x01, 0x328a },
3369                 { 0x1f, 0x0000 }
3370         };
3371
3372         rtl_apply_firmware(tp);
3373
3374         rtl_writephy_batch(tp, phy_reg_init);
3375
3376         rtl8168f_hw_phy_config(tp);
3377
3378         /* Improve 2-pair detection performance */
3379         rtl_writephy(tp, 0x1f, 0x0005);
3380         rtl_writephy(tp, 0x05, 0x8b85);
3381         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3382         rtl_writephy(tp, 0x1f, 0x0000);
3383 }
3384
3385 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3386 {
3387         rtl_apply_firmware(tp);
3388
3389         rtl8168f_hw_phy_config(tp);
3390 }
3391
3392 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3393 {
3394         static const struct phy_reg phy_reg_init[] = {
3395                 /* Channel estimation fine tune */
3396                 { 0x1f, 0x0003 },
3397                 { 0x09, 0xa20f },
3398                 { 0x1f, 0x0000 },
3399
3400                 /* Modify green table for giga & fnet */
3401                 { 0x1f, 0x0005 },
3402                 { 0x05, 0x8b55 },
3403                 { 0x06, 0x0000 },
3404                 { 0x05, 0x8b5e },
3405                 { 0x06, 0x0000 },
3406                 { 0x05, 0x8b67 },
3407                 { 0x06, 0x0000 },
3408                 { 0x05, 0x8b70 },
3409                 { 0x06, 0x0000 },
3410                 { 0x1f, 0x0000 },
3411                 { 0x1f, 0x0007 },
3412                 { 0x1e, 0x0078 },
3413                 { 0x17, 0x0000 },
3414                 { 0x19, 0x00aa },
3415                 { 0x1f, 0x0000 },
3416
3417                 /* Modify green table for 10M */
3418                 { 0x1f, 0x0005 },
3419                 { 0x05, 0x8b79 },
3420                 { 0x06, 0xaa00 },
3421                 { 0x1f, 0x0000 },
3422
3423                 /* Disable hiimpedance detection (RTCT) */
3424                 { 0x1f, 0x0003 },
3425                 { 0x01, 0x328a },
3426                 { 0x1f, 0x0000 }
3427         };
3428
3429
3430         rtl_apply_firmware(tp);
3431
3432         rtl8168f_hw_phy_config(tp);
3433
3434         /* Improve 2-pair detection performance */
3435         rtl_writephy(tp, 0x1f, 0x0005);
3436         rtl_writephy(tp, 0x05, 0x8b85);
3437         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3438         rtl_writephy(tp, 0x1f, 0x0000);
3439
3440         rtl_writephy_batch(tp, phy_reg_init);
3441
3442         /* Modify green table for giga */
3443         rtl_writephy(tp, 0x1f, 0x0005);
3444         rtl_writephy(tp, 0x05, 0x8b54);
3445         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3446         rtl_writephy(tp, 0x05, 0x8b5d);
3447         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3448         rtl_writephy(tp, 0x05, 0x8a7c);
3449         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3450         rtl_writephy(tp, 0x05, 0x8a7f);
3451         rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
3452         rtl_writephy(tp, 0x05, 0x8a82);
3453         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3454         rtl_writephy(tp, 0x05, 0x8a85);
3455         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3456         rtl_writephy(tp, 0x05, 0x8a88);
3457         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3458         rtl_writephy(tp, 0x1f, 0x0000);
3459
3460         /* uc same-seed solution */
3461         rtl_writephy(tp, 0x1f, 0x0005);
3462         rtl_writephy(tp, 0x05, 0x8b85);
3463         rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
3464         rtl_writephy(tp, 0x1f, 0x0000);
3465
3466         /* Green feature */
3467         rtl_writephy(tp, 0x1f, 0x0003);
3468         rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3469         rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3470         rtl_writephy(tp, 0x1f, 0x0000);
3471 }
3472
3473 static void rtl8168g_disable_aldps(struct rtl8169_private *tp)
3474 {
3475         phy_write(tp->phydev, 0x1f, 0x0a43);
3476         phy_clear_bits(tp->phydev, 0x10, BIT(2));
3477 }
3478
3479 static void rtl8168g_phy_adjust_10m_aldps(struct rtl8169_private *tp)
3480 {
3481         struct phy_device *phydev = tp->phydev;
3482
3483         phy_write(phydev, 0x1f, 0x0bcc);
3484         phy_clear_bits(phydev, 0x14, BIT(8));
3485
3486         phy_write(phydev, 0x1f, 0x0a44);
3487         phy_set_bits(phydev, 0x11, BIT(7) | BIT(6));
3488
3489         phy_write(phydev, 0x1f, 0x0a43);
3490         phy_write(phydev, 0x13, 0x8084);
3491         phy_clear_bits(phydev, 0x14, BIT(14) | BIT(13));
3492         phy_set_bits(phydev, 0x10, BIT(12) | BIT(1) | BIT(0));
3493
3494         phy_write(phydev, 0x1f, 0x0000);
3495 }
3496
3497 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3498 {
3499         rtl_apply_firmware(tp);
3500
3501         rtl_writephy(tp, 0x1f, 0x0a46);
3502         if (rtl_readphy(tp, 0x10) & 0x0100) {
3503                 rtl_writephy(tp, 0x1f, 0x0bcc);
3504                 rtl_w0w1_phy(tp, 0x12, 0x0000, 0x8000);
3505         } else {
3506                 rtl_writephy(tp, 0x1f, 0x0bcc);
3507                 rtl_w0w1_phy(tp, 0x12, 0x8000, 0x0000);
3508         }
3509
3510         rtl_writephy(tp, 0x1f, 0x0a46);
3511         if (rtl_readphy(tp, 0x13) & 0x0100) {
3512                 rtl_writephy(tp, 0x1f, 0x0c41);
3513                 rtl_w0w1_phy(tp, 0x15, 0x0002, 0x0000);
3514         } else {
3515                 rtl_writephy(tp, 0x1f, 0x0c41);
3516                 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0002);
3517         }
3518
3519         /* Enable PHY auto speed down */
3520         rtl_writephy(tp, 0x1f, 0x0a44);
3521         rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3522
3523         rtl8168g_phy_adjust_10m_aldps(tp);
3524
3525         /* EEE auto-fallback function */
3526         rtl_writephy(tp, 0x1f, 0x0a4b);
3527         rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3528
3529         /* Enable UC LPF tune function */
3530         rtl_writephy(tp, 0x1f, 0x0a43);
3531         rtl_writephy(tp, 0x13, 0x8012);
3532         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3533
3534         rtl_writephy(tp, 0x1f, 0x0c42);
3535         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3536
3537         /* Improve SWR Efficiency */
3538         rtl_writephy(tp, 0x1f, 0x0bcd);
3539         rtl_writephy(tp, 0x14, 0x5065);
3540         rtl_writephy(tp, 0x14, 0xd065);
3541         rtl_writephy(tp, 0x1f, 0x0bc8);
3542         rtl_writephy(tp, 0x11, 0x5655);
3543         rtl_writephy(tp, 0x1f, 0x0bcd);
3544         rtl_writephy(tp, 0x14, 0x1065);
3545         rtl_writephy(tp, 0x14, 0x9065);
3546         rtl_writephy(tp, 0x14, 0x1065);
3547
3548         rtl8168g_disable_aldps(tp);
3549         rtl8168g_config_eee_phy(tp);
3550         rtl_enable_eee(tp);
3551 }
3552
3553 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3554 {
3555         rtl_apply_firmware(tp);
3556         rtl8168g_config_eee_phy(tp);
3557         rtl_enable_eee(tp);
3558 }
3559
3560 static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3561 {
3562         u16 dout_tapbin;
3563         u32 data;
3564
3565         rtl_apply_firmware(tp);
3566
3567         /* CHN EST parameters adjust - giga master */
3568         rtl_writephy(tp, 0x1f, 0x0a43);
3569         rtl_writephy(tp, 0x13, 0x809b);
3570         rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
3571         rtl_writephy(tp, 0x13, 0x80a2);
3572         rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
3573         rtl_writephy(tp, 0x13, 0x80a4);
3574         rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
3575         rtl_writephy(tp, 0x13, 0x809c);
3576         rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
3577         rtl_writephy(tp, 0x1f, 0x0000);
3578
3579         /* CHN EST parameters adjust - giga slave */
3580         rtl_writephy(tp, 0x1f, 0x0a43);
3581         rtl_writephy(tp, 0x13, 0x80ad);
3582         rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
3583         rtl_writephy(tp, 0x13, 0x80b4);
3584         rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
3585         rtl_writephy(tp, 0x13, 0x80ac);
3586         rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
3587         rtl_writephy(tp, 0x1f, 0x0000);
3588
3589         /* CHN EST parameters adjust - fnet */
3590         rtl_writephy(tp, 0x1f, 0x0a43);
3591         rtl_writephy(tp, 0x13, 0x808e);
3592         rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
3593         rtl_writephy(tp, 0x13, 0x8090);
3594         rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
3595         rtl_writephy(tp, 0x13, 0x8092);
3596         rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
3597         rtl_writephy(tp, 0x1f, 0x0000);
3598
3599         /* enable R-tune & PGA-retune function */
3600         dout_tapbin = 0;
3601         rtl_writephy(tp, 0x1f, 0x0a46);
3602         data = rtl_readphy(tp, 0x13);
3603         data &= 3;
3604         data <<= 2;
3605         dout_tapbin |= data;
3606         data = rtl_readphy(tp, 0x12);
3607         data &= 0xc000;
3608         data >>= 14;
3609         dout_tapbin |= data;
3610         dout_tapbin = ~(dout_tapbin^0x08);
3611         dout_tapbin <<= 12;
3612         dout_tapbin &= 0xf000;
3613         rtl_writephy(tp, 0x1f, 0x0a43);
3614         rtl_writephy(tp, 0x13, 0x827a);
3615         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3616         rtl_writephy(tp, 0x13, 0x827b);
3617         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3618         rtl_writephy(tp, 0x13, 0x827c);
3619         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3620         rtl_writephy(tp, 0x13, 0x827d);
3621         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3622
3623         rtl_writephy(tp, 0x1f, 0x0a43);
3624         rtl_writephy(tp, 0x13, 0x0811);
3625         rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3626         rtl_writephy(tp, 0x1f, 0x0a42);
3627         rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3628         rtl_writephy(tp, 0x1f, 0x0000);
3629
3630         /* enable GPHY 10M */
3631         rtl_writephy(tp, 0x1f, 0x0a44);
3632         rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3633         rtl_writephy(tp, 0x1f, 0x0000);
3634
3635         /* SAR ADC performance */
3636         rtl_writephy(tp, 0x1f, 0x0bca);
3637         rtl_w0w1_phy(tp, 0x17, 0x4000, 0x3000);
3638         rtl_writephy(tp, 0x1f, 0x0000);
3639
3640         rtl_writephy(tp, 0x1f, 0x0a43);
3641         rtl_writephy(tp, 0x13, 0x803f);
3642         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3643         rtl_writephy(tp, 0x13, 0x8047);
3644         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3645         rtl_writephy(tp, 0x13, 0x804f);
3646         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3647         rtl_writephy(tp, 0x13, 0x8057);
3648         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3649         rtl_writephy(tp, 0x13, 0x805f);
3650         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3651         rtl_writephy(tp, 0x13, 0x8067);
3652         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3653         rtl_writephy(tp, 0x13, 0x806f);
3654         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3655         rtl_writephy(tp, 0x1f, 0x0000);
3656
3657         /* disable phy pfm mode */
3658         rtl_writephy(tp, 0x1f, 0x0a44);
3659         rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
3660         rtl_writephy(tp, 0x1f, 0x0000);
3661
3662         rtl8168g_disable_aldps(tp);
3663         rtl8168g_config_eee_phy(tp);
3664         rtl_enable_eee(tp);
3665 }
3666
3667 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3668 {
3669         u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3670         u16 rlen;
3671         u32 data;
3672
3673         rtl_apply_firmware(tp);
3674
3675         /* CHIN EST parameter update */
3676         rtl_writephy(tp, 0x1f, 0x0a43);
3677         rtl_writephy(tp, 0x13, 0x808a);
3678         rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
3679         rtl_writephy(tp, 0x1f, 0x0000);
3680
3681         /* enable R-tune & PGA-retune function */
3682         rtl_writephy(tp, 0x1f, 0x0a43);
3683         rtl_writephy(tp, 0x13, 0x0811);
3684         rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3685         rtl_writephy(tp, 0x1f, 0x0a42);
3686         rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3687         rtl_writephy(tp, 0x1f, 0x0000);
3688
3689         /* enable GPHY 10M */
3690         rtl_writephy(tp, 0x1f, 0x0a44);
3691         rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3692         rtl_writephy(tp, 0x1f, 0x0000);
3693
3694         r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3695         data = r8168_mac_ocp_read(tp, 0xdd02);
3696         ioffset_p3 = ((data & 0x80)>>7);
3697         ioffset_p3 <<= 3;
3698
3699         data = r8168_mac_ocp_read(tp, 0xdd00);
3700         ioffset_p3 |= ((data & (0xe000))>>13);
3701         ioffset_p2 = ((data & (0x1e00))>>9);
3702         ioffset_p1 = ((data & (0x01e0))>>5);
3703         ioffset_p0 = ((data & 0x0010)>>4);
3704         ioffset_p0 <<= 3;
3705         ioffset_p0 |= (data & (0x07));
3706         data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3707
3708         if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
3709             (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) {
3710                 rtl_writephy(tp, 0x1f, 0x0bcf);
3711                 rtl_writephy(tp, 0x16, data);
3712                 rtl_writephy(tp, 0x1f, 0x0000);
3713         }
3714
3715         /* Modify rlen (TX LPF corner frequency) level */
3716         rtl_writephy(tp, 0x1f, 0x0bcd);
3717         data = rtl_readphy(tp, 0x16);
3718         data &= 0x000f;
3719         rlen = 0;
3720         if (data > 3)
3721                 rlen = data - 3;
3722         data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
3723         rtl_writephy(tp, 0x17, data);
3724         rtl_writephy(tp, 0x1f, 0x0bcd);
3725         rtl_writephy(tp, 0x1f, 0x0000);
3726
3727         /* disable phy pfm mode */
3728         rtl_writephy(tp, 0x1f, 0x0a44);
3729         rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
3730         rtl_writephy(tp, 0x1f, 0x0000);
3731
3732         rtl8168g_disable_aldps(tp);
3733         rtl8168g_config_eee_phy(tp);
3734         rtl_enable_eee(tp);
3735 }
3736
3737 static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
3738 {
3739         /* Enable PHY auto speed down */
3740         rtl_writephy(tp, 0x1f, 0x0a44);
3741         rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3742         rtl_writephy(tp, 0x1f, 0x0000);
3743
3744         rtl8168g_phy_adjust_10m_aldps(tp);
3745
3746         /* Enable EEE auto-fallback function */
3747         rtl_writephy(tp, 0x1f, 0x0a4b);
3748         rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3749         rtl_writephy(tp, 0x1f, 0x0000);
3750
3751         /* Enable UC LPF tune function */
3752         rtl_writephy(tp, 0x1f, 0x0a43);
3753         rtl_writephy(tp, 0x13, 0x8012);
3754         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3755         rtl_writephy(tp, 0x1f, 0x0000);
3756
3757         /* set rg_sel_sdm_rate */
3758         rtl_writephy(tp, 0x1f, 0x0c42);
3759         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3760         rtl_writephy(tp, 0x1f, 0x0000);
3761
3762         rtl8168g_disable_aldps(tp);
3763         rtl8168g_config_eee_phy(tp);
3764         rtl_enable_eee(tp);
3765 }
3766
3767 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
3768 {
3769         rtl8168g_phy_adjust_10m_aldps(tp);
3770
3771         /* Enable UC LPF tune function */
3772         rtl_writephy(tp, 0x1f, 0x0a43);
3773         rtl_writephy(tp, 0x13, 0x8012);
3774         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3775         rtl_writephy(tp, 0x1f, 0x0000);
3776
3777         /* Set rg_sel_sdm_rate */
3778         rtl_writephy(tp, 0x1f, 0x0c42);
3779         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3780         rtl_writephy(tp, 0x1f, 0x0000);
3781
3782         /* Channel estimation parameters */
3783         rtl_writephy(tp, 0x1f, 0x0a43);
3784         rtl_writephy(tp, 0x13, 0x80f3);
3785         rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
3786         rtl_writephy(tp, 0x13, 0x80f0);
3787         rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
3788         rtl_writephy(tp, 0x13, 0x80ef);
3789         rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
3790         rtl_writephy(tp, 0x13, 0x80f6);
3791         rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
3792         rtl_writephy(tp, 0x13, 0x80ec);
3793         rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
3794         rtl_writephy(tp, 0x13, 0x80ed);
3795         rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3796         rtl_writephy(tp, 0x13, 0x80f2);
3797         rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
3798         rtl_writephy(tp, 0x13, 0x80f4);
3799         rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
3800         rtl_writephy(tp, 0x1f, 0x0a43);
3801         rtl_writephy(tp, 0x13, 0x8110);
3802         rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
3803         rtl_writephy(tp, 0x13, 0x810f);
3804         rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
3805         rtl_writephy(tp, 0x13, 0x8111);
3806         rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
3807         rtl_writephy(tp, 0x13, 0x8113);
3808         rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
3809         rtl_writephy(tp, 0x13, 0x8115);
3810         rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
3811         rtl_writephy(tp, 0x13, 0x810e);
3812         rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
3813         rtl_writephy(tp, 0x13, 0x810c);
3814         rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3815         rtl_writephy(tp, 0x13, 0x810b);
3816         rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
3817         rtl_writephy(tp, 0x1f, 0x0a43);
3818         rtl_writephy(tp, 0x13, 0x80d1);
3819         rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
3820         rtl_writephy(tp, 0x13, 0x80cd);
3821         rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
3822         rtl_writephy(tp, 0x13, 0x80d3);
3823         rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
3824         rtl_writephy(tp, 0x13, 0x80d5);
3825         rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
3826         rtl_writephy(tp, 0x13, 0x80d7);
3827         rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
3828
3829         /* Force PWM-mode */
3830         rtl_writephy(tp, 0x1f, 0x0bcd);
3831         rtl_writephy(tp, 0x14, 0x5065);
3832         rtl_writephy(tp, 0x14, 0xd065);
3833         rtl_writephy(tp, 0x1f, 0x0bc8);
3834         rtl_writephy(tp, 0x12, 0x00ed);
3835         rtl_writephy(tp, 0x1f, 0x0bcd);
3836         rtl_writephy(tp, 0x14, 0x1065);
3837         rtl_writephy(tp, 0x14, 0x9065);
3838         rtl_writephy(tp, 0x14, 0x1065);
3839         rtl_writephy(tp, 0x1f, 0x0000);
3840
3841         rtl8168g_disable_aldps(tp);
3842         rtl8168g_config_eee_phy(tp);
3843         rtl_enable_eee(tp);
3844 }
3845
3846 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3847 {
3848         static const struct phy_reg phy_reg_init[] = {
3849                 { 0x1f, 0x0003 },
3850                 { 0x08, 0x441d },
3851                 { 0x01, 0x9100 },
3852                 { 0x1f, 0x0000 }
3853         };
3854
3855         rtl_writephy(tp, 0x1f, 0x0000);
3856         rtl_patchphy(tp, 0x11, 1 << 12);
3857         rtl_patchphy(tp, 0x19, 1 << 13);
3858         rtl_patchphy(tp, 0x10, 1 << 15);
3859
3860         rtl_writephy_batch(tp, phy_reg_init);
3861 }
3862
3863 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3864 {
3865         static const struct phy_reg phy_reg_init[] = {
3866                 { 0x1f, 0x0005 },
3867                 { 0x1a, 0x0000 },
3868                 { 0x1f, 0x0000 },
3869
3870                 { 0x1f, 0x0004 },
3871                 { 0x1c, 0x0000 },
3872                 { 0x1f, 0x0000 },
3873
3874                 { 0x1f, 0x0001 },
3875                 { 0x15, 0x7701 },
3876                 { 0x1f, 0x0000 }
3877         };
3878
3879         /* Disable ALDPS before ram code */
3880         rtl_writephy(tp, 0x1f, 0x0000);
3881         rtl_writephy(tp, 0x18, 0x0310);
3882         msleep(100);
3883
3884         rtl_apply_firmware(tp);
3885
3886         rtl_writephy_batch(tp, phy_reg_init);
3887 }
3888
3889 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3890 {
3891         /* Disable ALDPS before setting firmware */
3892         rtl_writephy(tp, 0x1f, 0x0000);
3893         rtl_writephy(tp, 0x18, 0x0310);
3894         msleep(20);
3895
3896         rtl_apply_firmware(tp);
3897
3898         /* EEE setting */
3899         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3900         rtl_writephy(tp, 0x1f, 0x0004);
3901         rtl_writephy(tp, 0x10, 0x401f);
3902         rtl_writephy(tp, 0x19, 0x7030);
3903         rtl_writephy(tp, 0x1f, 0x0000);
3904 }
3905
3906 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3907 {
3908         static const struct phy_reg phy_reg_init[] = {
3909                 { 0x1f, 0x0004 },
3910                 { 0x10, 0xc07f },
3911                 { 0x19, 0x7030 },
3912                 { 0x1f, 0x0000 }
3913         };
3914
3915         /* Disable ALDPS before ram code */
3916         rtl_writephy(tp, 0x1f, 0x0000);
3917         rtl_writephy(tp, 0x18, 0x0310);
3918         msleep(100);
3919
3920         rtl_apply_firmware(tp);
3921
3922         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3923         rtl_writephy_batch(tp, phy_reg_init);
3924
3925         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
3926 }
3927
3928 static void rtl_hw_phy_config(struct net_device *dev)
3929 {
3930         static const rtl_generic_fct phy_configs[] = {
3931                 /* PCI devices. */
3932                 [RTL_GIGA_MAC_VER_02] = rtl8169s_hw_phy_config,
3933                 [RTL_GIGA_MAC_VER_03] = rtl8169s_hw_phy_config,
3934                 [RTL_GIGA_MAC_VER_04] = rtl8169sb_hw_phy_config,
3935                 [RTL_GIGA_MAC_VER_05] = rtl8169scd_hw_phy_config,
3936                 [RTL_GIGA_MAC_VER_06] = rtl8169sce_hw_phy_config,
3937                 /* PCI-E devices. */
3938                 [RTL_GIGA_MAC_VER_07] = rtl8102e_hw_phy_config,
3939                 [RTL_GIGA_MAC_VER_08] = rtl8102e_hw_phy_config,
3940                 [RTL_GIGA_MAC_VER_09] = rtl8102e_hw_phy_config,
3941                 [RTL_GIGA_MAC_VER_10] = NULL,
3942                 [RTL_GIGA_MAC_VER_11] = rtl8168bb_hw_phy_config,
3943                 [RTL_GIGA_MAC_VER_12] = rtl8168bef_hw_phy_config,
3944                 [RTL_GIGA_MAC_VER_13] = NULL,
3945                 [RTL_GIGA_MAC_VER_14] = NULL,
3946                 [RTL_GIGA_MAC_VER_15] = NULL,
3947                 [RTL_GIGA_MAC_VER_16] = NULL,
3948                 [RTL_GIGA_MAC_VER_17] = rtl8168bef_hw_phy_config,
3949                 [RTL_GIGA_MAC_VER_18] = rtl8168cp_1_hw_phy_config,
3950                 [RTL_GIGA_MAC_VER_19] = rtl8168c_1_hw_phy_config,
3951                 [RTL_GIGA_MAC_VER_20] = rtl8168c_2_hw_phy_config,
3952                 [RTL_GIGA_MAC_VER_21] = rtl8168c_3_hw_phy_config,
3953                 [RTL_GIGA_MAC_VER_22] = rtl8168c_4_hw_phy_config,
3954                 [RTL_GIGA_MAC_VER_23] = rtl8168cp_2_hw_phy_config,
3955                 [RTL_GIGA_MAC_VER_24] = rtl8168cp_2_hw_phy_config,
3956                 [RTL_GIGA_MAC_VER_25] = rtl8168d_1_hw_phy_config,
3957                 [RTL_GIGA_MAC_VER_26] = rtl8168d_2_hw_phy_config,
3958                 [RTL_GIGA_MAC_VER_27] = rtl8168d_3_hw_phy_config,
3959                 [RTL_GIGA_MAC_VER_28] = rtl8168d_4_hw_phy_config,
3960                 [RTL_GIGA_MAC_VER_29] = rtl8105e_hw_phy_config,
3961                 [RTL_GIGA_MAC_VER_30] = rtl8105e_hw_phy_config,
3962                 [RTL_GIGA_MAC_VER_31] = NULL,
3963                 [RTL_GIGA_MAC_VER_32] = rtl8168e_1_hw_phy_config,
3964                 [RTL_GIGA_MAC_VER_33] = rtl8168e_1_hw_phy_config,
3965                 [RTL_GIGA_MAC_VER_34] = rtl8168e_2_hw_phy_config,
3966                 [RTL_GIGA_MAC_VER_35] = rtl8168f_1_hw_phy_config,
3967                 [RTL_GIGA_MAC_VER_36] = rtl8168f_2_hw_phy_config,
3968                 [RTL_GIGA_MAC_VER_37] = rtl8402_hw_phy_config,
3969                 [RTL_GIGA_MAC_VER_38] = rtl8411_hw_phy_config,
3970                 [RTL_GIGA_MAC_VER_39] = rtl8106e_hw_phy_config,
3971                 [RTL_GIGA_MAC_VER_40] = rtl8168g_1_hw_phy_config,
3972                 [RTL_GIGA_MAC_VER_41] = NULL,
3973                 [RTL_GIGA_MAC_VER_42] = rtl8168g_2_hw_phy_config,
3974                 [RTL_GIGA_MAC_VER_43] = rtl8168g_2_hw_phy_config,
3975                 [RTL_GIGA_MAC_VER_44] = rtl8168g_2_hw_phy_config,
3976                 [RTL_GIGA_MAC_VER_45] = rtl8168h_1_hw_phy_config,
3977                 [RTL_GIGA_MAC_VER_46] = rtl8168h_2_hw_phy_config,
3978                 [RTL_GIGA_MAC_VER_47] = rtl8168h_1_hw_phy_config,
3979                 [RTL_GIGA_MAC_VER_48] = rtl8168h_2_hw_phy_config,
3980                 [RTL_GIGA_MAC_VER_49] = rtl8168ep_1_hw_phy_config,
3981                 [RTL_GIGA_MAC_VER_50] = rtl8168ep_2_hw_phy_config,
3982                 [RTL_GIGA_MAC_VER_51] = rtl8168ep_2_hw_phy_config,
3983         };
3984         struct rtl8169_private *tp = netdev_priv(dev);
3985
3986         if (phy_configs[tp->mac_version])
3987                 phy_configs[tp->mac_version](tp);
3988 }
3989
3990 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3991 {
3992         if (!test_and_set_bit(flag, tp->wk.flags))
3993                 schedule_work(&tp->wk.work);
3994 }
3995
3996 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3997 {
3998         rtl_hw_phy_config(dev);
3999
4000         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
4001                 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
4002                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4003                 netif_dbg(tp, drv, dev,
4004                           "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4005                 RTL_W8(tp, 0x82, 0x01);
4006         }
4007
4008         /* We may have called phy_speed_down before */
4009         phy_speed_up(tp->phydev);
4010
4011         genphy_soft_reset(tp->phydev);
4012 }
4013
4014 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
4015 {
4016         rtl_lock_work(tp);
4017
4018         rtl_unlock_config_regs(tp);
4019
4020         RTL_W32(tp, MAC4, addr[4] | addr[5] << 8);
4021         RTL_R32(tp, MAC4);
4022
4023         RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
4024         RTL_R32(tp, MAC0);
4025
4026         if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4027                 rtl_rar_exgmac_set(tp, addr);
4028
4029         rtl_lock_config_regs(tp);
4030
4031         rtl_unlock_work(tp);
4032 }
4033
4034 static int rtl_set_mac_address(struct net_device *dev, void *p)
4035 {
4036         struct rtl8169_private *tp = netdev_priv(dev);
4037         struct device *d = tp_to_dev(tp);
4038         int ret;
4039
4040         ret = eth_mac_addr(dev, p);
4041         if (ret)
4042                 return ret;
4043
4044         pm_runtime_get_noresume(d);
4045
4046         if (pm_runtime_active(d))
4047                 rtl_rar_set(tp, dev->dev_addr);
4048
4049         pm_runtime_put_noidle(d);
4050
4051         return 0;
4052 }
4053
4054 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4055 {
4056         struct rtl8169_private *tp = netdev_priv(dev);
4057
4058         if (!netif_running(dev))
4059                 return -ENODEV;
4060
4061         return phy_mii_ioctl(tp->phydev, ifr, cmd);
4062 }
4063
4064 static void rtl_init_mdio_ops(struct rtl8169_private *tp)
4065 {
4066         struct mdio_ops *ops = &tp->mdio_ops;
4067
4068         switch (tp->mac_version) {
4069         case RTL_GIGA_MAC_VER_27:
4070                 ops->write      = r8168dp_1_mdio_write;
4071                 ops->read       = r8168dp_1_mdio_read;
4072                 break;
4073         case RTL_GIGA_MAC_VER_28:
4074         case RTL_GIGA_MAC_VER_31:
4075                 ops->write      = r8168dp_2_mdio_write;
4076                 ops->read       = r8168dp_2_mdio_read;
4077                 break;
4078         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4079                 ops->write      = r8168g_mdio_write;
4080                 ops->read       = r8168g_mdio_read;
4081                 break;
4082         default:
4083                 ops->write      = r8169_mdio_write;
4084                 ops->read       = r8169_mdio_read;
4085                 break;
4086         }
4087 }
4088
4089 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
4090 {
4091         switch (tp->mac_version) {
4092         case RTL_GIGA_MAC_VER_25:
4093         case RTL_GIGA_MAC_VER_26:
4094         case RTL_GIGA_MAC_VER_29:
4095         case RTL_GIGA_MAC_VER_30:
4096         case RTL_GIGA_MAC_VER_32:
4097         case RTL_GIGA_MAC_VER_33:
4098         case RTL_GIGA_MAC_VER_34:
4099         case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_51:
4100                 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
4101                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
4102                 break;
4103         default:
4104                 break;
4105         }
4106 }
4107
4108 static void r8168_pll_power_down(struct rtl8169_private *tp)
4109 {
4110         if (r8168_check_dash(tp))
4111                 return;
4112
4113         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4114             tp->mac_version == RTL_GIGA_MAC_VER_33)
4115                 rtl_ephy_write(tp, 0x19, 0xff64);
4116
4117         if (device_may_wakeup(tp_to_dev(tp))) {
4118                 phy_speed_down(tp->phydev, false);
4119                 rtl_wol_suspend_quirk(tp);
4120                 return;
4121         }
4122
4123         switch (tp->mac_version) {
4124         case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
4125         case RTL_GIGA_MAC_VER_37:
4126         case RTL_GIGA_MAC_VER_39:
4127         case RTL_GIGA_MAC_VER_43:
4128         case RTL_GIGA_MAC_VER_44:
4129         case RTL_GIGA_MAC_VER_45:
4130         case RTL_GIGA_MAC_VER_46:
4131         case RTL_GIGA_MAC_VER_47:
4132         case RTL_GIGA_MAC_VER_48:
4133         case RTL_GIGA_MAC_VER_50:
4134         case RTL_GIGA_MAC_VER_51:
4135                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
4136                 break;
4137         case RTL_GIGA_MAC_VER_40:
4138         case RTL_GIGA_MAC_VER_41:
4139         case RTL_GIGA_MAC_VER_49:
4140                 rtl_eri_clear_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000);
4141                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
4142                 break;
4143         default:
4144                 break;
4145         }
4146 }
4147
4148 static void r8168_pll_power_up(struct rtl8169_private *tp)
4149 {
4150         switch (tp->mac_version) {
4151         case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
4152         case RTL_GIGA_MAC_VER_37:
4153         case RTL_GIGA_MAC_VER_39:
4154         case RTL_GIGA_MAC_VER_43:
4155                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);
4156                 break;
4157         case RTL_GIGA_MAC_VER_44:
4158         case RTL_GIGA_MAC_VER_45:
4159         case RTL_GIGA_MAC_VER_46:
4160         case RTL_GIGA_MAC_VER_47:
4161         case RTL_GIGA_MAC_VER_48:
4162         case RTL_GIGA_MAC_VER_50:
4163         case RTL_GIGA_MAC_VER_51:
4164                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
4165                 break;
4166         case RTL_GIGA_MAC_VER_40:
4167         case RTL_GIGA_MAC_VER_41:
4168         case RTL_GIGA_MAC_VER_49:
4169                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
4170                 rtl_eri_set_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000);
4171                 break;
4172         default:
4173                 break;
4174         }
4175
4176         phy_resume(tp->phydev);
4177         /* give MAC/PHY some time to resume */
4178         msleep(20);
4179 }
4180
4181 static void rtl_pll_power_down(struct rtl8169_private *tp)
4182 {
4183         switch (tp->mac_version) {
4184         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
4185         case RTL_GIGA_MAC_VER_13 ... RTL_GIGA_MAC_VER_15:
4186                 break;
4187         default:
4188                 r8168_pll_power_down(tp);
4189         }
4190 }
4191
4192 static void rtl_pll_power_up(struct rtl8169_private *tp)
4193 {
4194         switch (tp->mac_version) {
4195         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
4196         case RTL_GIGA_MAC_VER_13 ... RTL_GIGA_MAC_VER_15:
4197                 break;
4198         default:
4199                 r8168_pll_power_up(tp);
4200         }
4201 }
4202
4203 static void rtl_init_rxcfg(struct rtl8169_private *tp)
4204 {
4205         switch (tp->mac_version) {
4206         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
4207         case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
4208                 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4209                 break;
4210         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
4211         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
4212         case RTL_GIGA_MAC_VER_38:
4213                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4214                 break;
4215         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4216                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
4217                 break;
4218         default:
4219                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
4220                 break;
4221         }
4222 }
4223
4224 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4225 {
4226         tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
4227 }
4228
4229 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4230 {
4231         if (tp->jumbo_ops.enable) {
4232                 rtl_unlock_config_regs(tp);
4233                 tp->jumbo_ops.enable(tp);
4234                 rtl_lock_config_regs(tp);
4235         }
4236 }
4237
4238 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4239 {
4240         if (tp->jumbo_ops.disable) {
4241                 rtl_unlock_config_regs(tp);
4242                 tp->jumbo_ops.disable(tp);
4243                 rtl_lock_config_regs(tp);
4244         }
4245 }
4246
4247 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4248 {
4249         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4250         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
4251         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
4252 }
4253
4254 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4255 {
4256         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4257         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
4258         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4259 }
4260
4261 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4262 {
4263         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4264 }
4265
4266 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4267 {
4268         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4269 }
4270
4271 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4272 {
4273         RTL_W8(tp, MaxTxPacketSize, 0x3f);
4274         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4275         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
4276         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
4277 }
4278
4279 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4280 {
4281         RTL_W8(tp, MaxTxPacketSize, 0x0c);
4282         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4283         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
4284         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4285 }
4286
4287 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4288 {
4289         rtl_tx_performance_tweak(tp,
4290                 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
4291 }
4292
4293 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4294 {
4295         rtl_tx_performance_tweak(tp,
4296                 PCI_EXP_DEVCTL_READRQ_4096B | PCI_EXP_DEVCTL_NOSNOOP_EN);
4297 }
4298
4299 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4300 {
4301         r8168b_0_hw_jumbo_enable(tp);
4302
4303         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
4304 }
4305
4306 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4307 {
4308         r8168b_0_hw_jumbo_disable(tp);
4309
4310         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4311 }
4312
4313 static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
4314 {
4315         struct jumbo_ops *ops = &tp->jumbo_ops;
4316
4317         switch (tp->mac_version) {
4318         case RTL_GIGA_MAC_VER_11:
4319                 ops->disable    = r8168b_0_hw_jumbo_disable;
4320                 ops->enable     = r8168b_0_hw_jumbo_enable;
4321                 break;
4322         case RTL_GIGA_MAC_VER_12:
4323         case RTL_GIGA_MAC_VER_17:
4324                 ops->disable    = r8168b_1_hw_jumbo_disable;
4325                 ops->enable     = r8168b_1_hw_jumbo_enable;
4326                 break;
4327         case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
4328         case RTL_GIGA_MAC_VER_19:
4329         case RTL_GIGA_MAC_VER_20:
4330         case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
4331         case RTL_GIGA_MAC_VER_22:
4332         case RTL_GIGA_MAC_VER_23:
4333         case RTL_GIGA_MAC_VER_24:
4334         case RTL_GIGA_MAC_VER_25:
4335         case RTL_GIGA_MAC_VER_26:
4336                 ops->disable    = r8168c_hw_jumbo_disable;
4337                 ops->enable     = r8168c_hw_jumbo_enable;
4338                 break;
4339         case RTL_GIGA_MAC_VER_27:
4340         case RTL_GIGA_MAC_VER_28:
4341                 ops->disable    = r8168dp_hw_jumbo_disable;
4342                 ops->enable     = r8168dp_hw_jumbo_enable;
4343                 break;
4344         case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
4345         case RTL_GIGA_MAC_VER_32:
4346         case RTL_GIGA_MAC_VER_33:
4347         case RTL_GIGA_MAC_VER_34:
4348                 ops->disable    = r8168e_hw_jumbo_disable;
4349                 ops->enable     = r8168e_hw_jumbo_enable;
4350                 break;
4351
4352         /*
4353          * No action needed for jumbo frames with 8169.
4354          * No jumbo for 810x at all.
4355          */
4356         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4357         default:
4358                 ops->disable    = NULL;
4359                 ops->enable     = NULL;
4360                 break;
4361         }
4362 }
4363
4364 DECLARE_RTL_COND(rtl_chipcmd_cond)
4365 {
4366         return RTL_R8(tp, ChipCmd) & CmdReset;
4367 }
4368
4369 static void rtl_hw_reset(struct rtl8169_private *tp)
4370 {
4371         RTL_W8(tp, ChipCmd, CmdReset);
4372
4373         rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
4374 }
4375
4376 static void rtl_request_firmware(struct rtl8169_private *tp)
4377 {
4378         struct rtl_fw *rtl_fw;
4379         int rc = -ENOMEM;
4380
4381         /* firmware loaded already or no firmware available */
4382         if (tp->rtl_fw || !tp->fw_name)
4383                 return;
4384
4385         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4386         if (!rtl_fw)
4387                 goto err_warn;
4388
4389         rc = request_firmware(&rtl_fw->fw, tp->fw_name, tp_to_dev(tp));
4390         if (rc < 0)
4391                 goto err_free;
4392
4393         rc = rtl_check_firmware(tp, rtl_fw);
4394         if (rc < 0)
4395                 goto err_release_firmware;
4396
4397         tp->rtl_fw = rtl_fw;
4398
4399         return;
4400
4401 err_release_firmware:
4402         release_firmware(rtl_fw->fw);
4403 err_free:
4404         kfree(rtl_fw);
4405 err_warn:
4406         netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4407                    tp->fw_name, rc);
4408 }
4409
4410 static void rtl_rx_close(struct rtl8169_private *tp)
4411 {
4412         RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
4413 }
4414
4415 DECLARE_RTL_COND(rtl_npq_cond)
4416 {
4417         return RTL_R8(tp, TxPoll) & NPQ;
4418 }
4419
4420 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4421 {
4422         return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
4423 }
4424
4425 static void rtl8169_hw_reset(struct rtl8169_private *tp)
4426 {
4427         /* Disable interrupts */
4428         rtl8169_irq_mask_and_ack(tp);
4429
4430         rtl_rx_close(tp);
4431
4432         switch (tp->mac_version) {
4433         case RTL_GIGA_MAC_VER_27:
4434         case RTL_GIGA_MAC_VER_28:
4435         case RTL_GIGA_MAC_VER_31:
4436                 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
4437                 break;
4438         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
4439         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4440                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4441                 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
4442                 break;
4443         default:
4444                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4445                 udelay(100);
4446                 break;
4447         }
4448
4449         rtl_hw_reset(tp);
4450 }
4451
4452 static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
4453 {
4454         u32 val = TX_DMA_BURST << TxDMAShift |
4455                   InterFrameGap << TxInterFrameGapShift;
4456
4457         if (tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
4458             tp->mac_version != RTL_GIGA_MAC_VER_39)
4459                 val |= TXCFG_AUTO_FIFO;
4460
4461         RTL_W32(tp, TxConfig, val);
4462 }
4463
4464 static void rtl_set_rx_max_size(struct rtl8169_private *tp)
4465 {
4466         /* Low hurts. Let's disable the filtering. */
4467         RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
4468 }
4469
4470 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
4471 {
4472         /*
4473          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4474          * register to be written before TxDescAddrLow to work.
4475          * Switching from MMIO to I/O access fixes the issue as well.
4476          */
4477         RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4478         RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4479         RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4480         RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4481 }
4482
4483 static void rtl8169_set_magic_reg(struct rtl8169_private *tp, unsigned mac_version)
4484 {
4485         u32 val;
4486
4487         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4488                 val = 0x000fff00;
4489         else if (tp->mac_version == RTL_GIGA_MAC_VER_06)
4490                 val = 0x00ffff00;
4491         else
4492                 return;
4493
4494         if (RTL_R8(tp, Config2) & PCI_Clock_66MHz)
4495                 val |= 0xff;
4496
4497         RTL_W32(tp, 0x7c, val);
4498 }
4499
4500 static void rtl_set_rx_mode(struct net_device *dev)
4501 {
4502         struct rtl8169_private *tp = netdev_priv(dev);
4503         u32 mc_filter[2];       /* Multicast hash filter */
4504         int rx_mode;
4505         u32 tmp = 0;
4506
4507         if (dev->flags & IFF_PROMISC) {
4508                 /* Unconditionally log net taps. */
4509                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4510                 rx_mode =
4511                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4512                     AcceptAllPhys;
4513                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4514         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4515                    (dev->flags & IFF_ALLMULTI)) {
4516                 /* Too many to filter perfectly -- accept all multicasts. */
4517                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4518                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4519         } else {
4520                 struct netdev_hw_addr *ha;
4521
4522                 rx_mode = AcceptBroadcast | AcceptMyPhys;
4523                 mc_filter[1] = mc_filter[0] = 0;
4524                 netdev_for_each_mc_addr(ha, dev) {
4525                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4526                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4527                         rx_mode |= AcceptMulticast;
4528                 }
4529         }
4530
4531         if (dev->features & NETIF_F_RXALL)
4532                 rx_mode |= (AcceptErr | AcceptRunt);
4533
4534         tmp = (RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4535
4536         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4537                 u32 data = mc_filter[0];
4538
4539                 mc_filter[0] = swab32(mc_filter[1]);
4540                 mc_filter[1] = swab32(data);
4541         }
4542
4543         if (tp->mac_version == RTL_GIGA_MAC_VER_35)
4544                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4545
4546         RTL_W32(tp, MAR0 + 4, mc_filter[1]);
4547         RTL_W32(tp, MAR0 + 0, mc_filter[0]);
4548
4549         RTL_W32(tp, RxConfig, tmp);
4550 }
4551
4552 static void rtl_hw_start(struct  rtl8169_private *tp)
4553 {
4554         rtl_unlock_config_regs(tp);
4555
4556         tp->hw_start(tp);
4557
4558         rtl_set_rx_max_size(tp);
4559         rtl_set_rx_tx_desc_registers(tp);
4560         rtl_lock_config_regs(tp);
4561
4562         /* disable interrupt coalescing */
4563         RTL_W16(tp, IntrMitigate, 0x0000);
4564         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4565         RTL_R8(tp, IntrMask);
4566         RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
4567         rtl_init_rxcfg(tp);
4568         rtl_set_tx_config_registers(tp);
4569
4570         rtl_set_rx_mode(tp->dev);
4571         /* no early-rx interrupts */
4572         RTL_W16(tp, MultiIntr, RTL_R16(tp, MultiIntr) & 0xf000);
4573         rtl_irq_enable(tp);
4574 }
4575
4576 static void rtl_hw_start_8169(struct rtl8169_private *tp)
4577 {
4578         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4579                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4580
4581         RTL_W8(tp, EarlyTxThres, NoEarlyTx);
4582
4583         tp->cp_cmd |= PCIMulRW;
4584
4585         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4586             tp->mac_version == RTL_GIGA_MAC_VER_03) {
4587                 netif_dbg(tp, drv, tp->dev,
4588                           "Set MAC Reg C+CR Offset 0xe0. Bit 3 and Bit 14 MUST be 1\n");
4589                 tp->cp_cmd |= (1 << 14);
4590         }
4591
4592         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4593
4594         rtl8169_set_magic_reg(tp, tp->mac_version);
4595
4596         RTL_W32(tp, RxMissed, 0);
4597 }
4598
4599 DECLARE_RTL_COND(rtl_csiar_cond)
4600 {
4601         return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
4602 }
4603
4604 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
4605 {
4606         u32 func = PCI_FUNC(tp->pci_dev->devfn);
4607
4608         RTL_W32(tp, CSIDR, value);
4609         RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4610                 CSIAR_BYTE_ENABLE | func << 16);
4611
4612         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4613 }
4614
4615 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
4616 {
4617         u32 func = PCI_FUNC(tp->pci_dev->devfn);
4618
4619         RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
4620                 CSIAR_BYTE_ENABLE);
4621
4622         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4623                 RTL_R32(tp, CSIDR) : ~0;
4624 }
4625
4626 static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val)
4627 {
4628         struct pci_dev *pdev = tp->pci_dev;
4629         u32 csi;
4630
4631         /* According to Realtek the value at config space address 0x070f
4632          * controls the L0s/L1 entrance latency. We try standard ECAM access
4633          * first and if it fails fall back to CSI.
4634          */
4635         if (pdev->cfg_size > 0x070f &&
4636             pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
4637                 return;
4638
4639         netdev_notice_once(tp->dev,
4640                 "No native access to PCI extended config space, falling back to CSI\n");
4641         csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4642         rtl_csi_write(tp, 0x070c, csi | val << 24);
4643 }
4644
4645 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
4646 {
4647         rtl_csi_access_enable(tp, 0x27);
4648 }
4649
4650 struct ephy_info {
4651         unsigned int offset;
4652         u16 mask;
4653         u16 bits;
4654 };
4655
4656 static void __rtl_ephy_init(struct rtl8169_private *tp,
4657                             const struct ephy_info *e, int len)
4658 {
4659         u16 w;
4660
4661         while (len-- > 0) {
4662                 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4663                 rtl_ephy_write(tp, e->offset, w);
4664                 e++;
4665         }
4666 }
4667
4668 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a))
4669
4670 static void rtl_disable_clock_request(struct rtl8169_private *tp)
4671 {
4672         pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
4673                                    PCI_EXP_LNKCTL_CLKREQ_EN);
4674 }
4675
4676 static void rtl_enable_clock_request(struct rtl8169_private *tp)
4677 {
4678         pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
4679                                  PCI_EXP_LNKCTL_CLKREQ_EN);
4680 }
4681
4682 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp)
4683 {
4684         /* work around an issue when PCI reset occurs during L2/L3 state */
4685         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23);
4686 }
4687
4688 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
4689 {
4690         if (enable) {
4691                 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);
4692                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);
4693         } else {
4694                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
4695                 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
4696         }
4697
4698         udelay(10);
4699 }
4700
4701 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat,
4702                               u16 tx_stat, u16 rx_dyn, u16 tx_dyn)
4703 {
4704         /* Usage of dynamic vs. static FIFO is controlled by bit
4705          * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known.
4706          */
4707         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn);
4708         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn);
4709 }
4710
4711 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp,
4712                                           u8 low, u8 high)
4713 {
4714         /* FIFO thresholds for pause flow control */
4715         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low);
4716         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high);
4717 }
4718
4719 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
4720 {
4721         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4722
4723         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4724         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4725
4726         if (tp->dev->mtu <= ETH_DATA_LEN) {
4727                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B |
4728                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
4729         }
4730 }
4731
4732 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
4733 {
4734         rtl_hw_start_8168bb(tp);
4735
4736         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4737
4738         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4739 }
4740
4741 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
4742 {
4743         RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
4744
4745         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4746
4747         if (tp->dev->mtu <= ETH_DATA_LEN)
4748                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4749
4750         rtl_disable_clock_request(tp);
4751
4752         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4753         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4754 }
4755
4756 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
4757 {
4758         static const struct ephy_info e_info_8168cp[] = {
4759                 { 0x01, 0,      0x0001 },
4760                 { 0x02, 0x0800, 0x1000 },
4761                 { 0x03, 0,      0x0042 },
4762                 { 0x06, 0x0080, 0x0000 },
4763                 { 0x07, 0,      0x2000 }
4764         };
4765
4766         rtl_set_def_aspm_entry_latency(tp);
4767
4768         rtl_ephy_init(tp, e_info_8168cp);
4769
4770         __rtl_hw_start_8168cp(tp);
4771 }
4772
4773 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
4774 {
4775         rtl_set_def_aspm_entry_latency(tp);
4776
4777         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4778
4779         if (tp->dev->mtu <= ETH_DATA_LEN)
4780                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4781
4782         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4783         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4784 }
4785
4786 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
4787 {
4788         rtl_set_def_aspm_entry_latency(tp);
4789
4790         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4791
4792         /* Magic. */
4793         RTL_W8(tp, DBG_REG, 0x20);
4794
4795         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4796
4797         if (tp->dev->mtu <= ETH_DATA_LEN)
4798                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4799
4800         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4801         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4802 }
4803
4804 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
4805 {
4806         static const struct ephy_info e_info_8168c_1[] = {
4807                 { 0x02, 0x0800, 0x1000 },
4808                 { 0x03, 0,      0x0002 },
4809                 { 0x06, 0x0080, 0x0000 }
4810         };
4811
4812         rtl_set_def_aspm_entry_latency(tp);
4813
4814         RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4815
4816         rtl_ephy_init(tp, e_info_8168c_1);
4817
4818         __rtl_hw_start_8168cp(tp);
4819 }
4820
4821 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
4822 {
4823         static const struct ephy_info e_info_8168c_2[] = {
4824                 { 0x01, 0,      0x0001 },
4825                 { 0x03, 0x0400, 0x0220 }
4826         };
4827
4828         rtl_set_def_aspm_entry_latency(tp);
4829
4830         rtl_ephy_init(tp, e_info_8168c_2);
4831
4832         __rtl_hw_start_8168cp(tp);
4833 }
4834
4835 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
4836 {
4837         rtl_hw_start_8168c_2(tp);
4838 }
4839
4840 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
4841 {
4842         rtl_set_def_aspm_entry_latency(tp);
4843
4844         __rtl_hw_start_8168cp(tp);
4845 }
4846
4847 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
4848 {
4849         rtl_set_def_aspm_entry_latency(tp);
4850
4851         rtl_disable_clock_request(tp);
4852
4853         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4854
4855         if (tp->dev->mtu <= ETH_DATA_LEN)
4856                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4857
4858         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4859         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4860 }
4861
4862 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4863 {
4864         rtl_set_def_aspm_entry_latency(tp);
4865
4866         if (tp->dev->mtu <= ETH_DATA_LEN)
4867                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4868
4869         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4870
4871         rtl_disable_clock_request(tp);
4872 }
4873
4874 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
4875 {
4876         static const struct ephy_info e_info_8168d_4[] = {
4877                 { 0x0b, 0x0000, 0x0048 },
4878                 { 0x19, 0x0020, 0x0050 },
4879                 { 0x0c, 0x0100, 0x0020 }
4880         };
4881
4882         rtl_set_def_aspm_entry_latency(tp);
4883
4884         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4885
4886         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4887
4888         rtl_ephy_init(tp, e_info_8168d_4);
4889
4890         rtl_enable_clock_request(tp);
4891 }
4892
4893 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
4894 {
4895         static const struct ephy_info e_info_8168e_1[] = {
4896                 { 0x00, 0x0200, 0x0100 },
4897                 { 0x00, 0x0000, 0x0004 },
4898                 { 0x06, 0x0002, 0x0001 },
4899                 { 0x06, 0x0000, 0x0030 },
4900                 { 0x07, 0x0000, 0x2000 },
4901                 { 0x00, 0x0000, 0x0020 },
4902                 { 0x03, 0x5800, 0x2000 },
4903                 { 0x03, 0x0000, 0x0001 },
4904                 { 0x01, 0x0800, 0x1000 },
4905                 { 0x07, 0x0000, 0x4000 },
4906                 { 0x1e, 0x0000, 0x2000 },
4907                 { 0x19, 0xffff, 0xfe6c },
4908                 { 0x0a, 0x0000, 0x0040 }
4909         };
4910
4911         rtl_set_def_aspm_entry_latency(tp);
4912
4913         rtl_ephy_init(tp, e_info_8168e_1);
4914
4915         if (tp->dev->mtu <= ETH_DATA_LEN)
4916                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4917
4918         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4919
4920         rtl_disable_clock_request(tp);
4921
4922         /* Reset tx FIFO pointer */
4923         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
4924         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
4925
4926         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4927 }
4928
4929 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
4930 {
4931         static const struct ephy_info e_info_8168e_2[] = {
4932                 { 0x09, 0x0000, 0x0080 },
4933                 { 0x19, 0x0000, 0x0224 }
4934         };
4935
4936         rtl_set_def_aspm_entry_latency(tp);
4937
4938         rtl_ephy_init(tp, e_info_8168e_2);
4939
4940         if (tp->dev->mtu <= ETH_DATA_LEN)
4941                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4942
4943         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4944         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4945         rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
4946         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
4947         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060);
4948         rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4));
4949         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00);
4950
4951         RTL_W8(tp, MaxTxPacketSize, EarlySize);
4952
4953         rtl_disable_clock_request(tp);
4954
4955         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
4956
4957         rtl8168_config_eee_mac(tp);
4958
4959         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
4960         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
4961         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4962
4963         rtl_hw_aspm_clkreq_enable(tp, true);
4964 }
4965
4966 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
4967 {
4968         rtl_set_def_aspm_entry_latency(tp);
4969
4970         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4971
4972         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4973         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4974         rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
4975         rtl_reset_packet_filter(tp);
4976         rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4));
4977         rtl_eri_set_bits(tp, 0x1d0, ERIAR_MASK_0001, BIT(4));
4978         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
4979         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060);
4980
4981         RTL_W8(tp, MaxTxPacketSize, EarlySize);
4982
4983         rtl_disable_clock_request(tp);
4984
4985         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
4986         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
4987         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
4988         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4989
4990         rtl8168_config_eee_mac(tp);
4991 }
4992
4993 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
4994 {
4995         static const struct ephy_info e_info_8168f_1[] = {
4996                 { 0x06, 0x00c0, 0x0020 },
4997                 { 0x08, 0x0001, 0x0002 },
4998                 { 0x09, 0x0000, 0x0080 },
4999                 { 0x19, 0x0000, 0x0224 }
5000         };
5001
5002         rtl_hw_start_8168f(tp);
5003
5004         rtl_ephy_init(tp, e_info_8168f_1);
5005
5006         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00);
5007 }
5008
5009 static void rtl_hw_start_8411(struct rtl8169_private *tp)
5010 {
5011         static const struct ephy_info e_info_8168f_1[] = {
5012                 { 0x06, 0x00c0, 0x0020 },
5013                 { 0x0f, 0xffff, 0x5200 },
5014                 { 0x1e, 0x0000, 0x4000 },
5015                 { 0x19, 0x0000, 0x0224 }
5016         };
5017
5018         rtl_hw_start_8168f(tp);
5019         rtl_pcie_state_l2l3_disable(tp);
5020
5021         rtl_ephy_init(tp, e_info_8168f_1);
5022
5023         rtl_eri_set_bits(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00);
5024 }
5025
5026 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
5027 {
5028         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
5029         rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
5030
5031         rtl_set_def_aspm_entry_latency(tp);
5032
5033         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5034
5035         rtl_reset_packet_filter(tp);
5036         rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f);
5037
5038         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5039         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5040
5041         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
5042         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
5043
5044         rtl8168_config_eee_mac(tp);
5045
5046         rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06);
5047         rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12));
5048
5049         rtl_pcie_state_l2l3_disable(tp);
5050 }
5051
5052 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
5053 {
5054         static const struct ephy_info e_info_8168g_1[] = {
5055                 { 0x00, 0x0000, 0x0008 },
5056                 { 0x0c, 0x37d0, 0x0820 },
5057                 { 0x1e, 0x0000, 0x0001 },
5058                 { 0x19, 0x8000, 0x0000 }
5059         };
5060
5061         rtl_hw_start_8168g(tp);
5062
5063         /* disable aspm and clock request before access ephy */
5064         rtl_hw_aspm_clkreq_enable(tp, false);
5065         rtl_ephy_init(tp, e_info_8168g_1);
5066         rtl_hw_aspm_clkreq_enable(tp, true);
5067 }
5068
5069 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
5070 {
5071         static const struct ephy_info e_info_8168g_2[] = {
5072                 { 0x00, 0x0000, 0x0008 },
5073                 { 0x0c, 0x3df0, 0x0200 },
5074                 { 0x19, 0xffff, 0xfc00 },
5075                 { 0x1e, 0xffff, 0x20eb }
5076         };
5077
5078         rtl_hw_start_8168g(tp);
5079
5080         /* disable aspm and clock request before access ephy */
5081         RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
5082         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
5083         rtl_ephy_init(tp, e_info_8168g_2);
5084 }
5085
5086 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
5087 {
5088         static const struct ephy_info e_info_8411_2[] = {
5089                 { 0x00, 0x0000, 0x0008 },
5090                 { 0x0c, 0x3df0, 0x0200 },
5091                 { 0x0f, 0xffff, 0x5200 },
5092                 { 0x19, 0x0020, 0x0000 },
5093                 { 0x1e, 0x0000, 0x2000 }
5094         };
5095
5096         rtl_hw_start_8168g(tp);
5097
5098         /* disable aspm and clock request before access ephy */
5099         rtl_hw_aspm_clkreq_enable(tp, false);
5100         rtl_ephy_init(tp, e_info_8411_2);
5101         rtl_hw_aspm_clkreq_enable(tp, true);
5102 }
5103
5104 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
5105 {
5106         int rg_saw_cnt;
5107         u32 data;
5108         static const struct ephy_info e_info_8168h_1[] = {
5109                 { 0x1e, 0x0800, 0x0001 },
5110                 { 0x1d, 0x0000, 0x0800 },
5111                 { 0x05, 0xffff, 0x2089 },
5112                 { 0x06, 0xffff, 0x5881 },
5113                 { 0x04, 0xffff, 0x154a },
5114                 { 0x01, 0xffff, 0x068b }
5115         };
5116
5117         /* disable aspm and clock request before access ephy */
5118         rtl_hw_aspm_clkreq_enable(tp, false);
5119         rtl_ephy_init(tp, e_info_8168h_1);
5120
5121         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
5122         rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
5123
5124         rtl_set_def_aspm_entry_latency(tp);
5125
5126         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5127
5128         rtl_reset_packet_filter(tp);
5129
5130         rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_1111, BIT(4));
5131
5132         rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f00);
5133
5134         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
5135
5136         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5137         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5138
5139         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
5140         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
5141
5142         rtl8168_config_eee_mac(tp);
5143
5144         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5145         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5146
5147         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
5148
5149         rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12));
5150
5151         rtl_pcie_state_l2l3_disable(tp);
5152
5153         rtl_writephy(tp, 0x1f, 0x0c42);
5154         rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
5155         rtl_writephy(tp, 0x1f, 0x0000);
5156         if (rg_saw_cnt > 0) {
5157                 u16 sw_cnt_1ms_ini;
5158
5159                 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
5160                 sw_cnt_1ms_ini &= 0x0fff;
5161                 data = r8168_mac_ocp_read(tp, 0xd412);
5162                 data &= ~0x0fff;
5163                 data |= sw_cnt_1ms_ini;
5164                 r8168_mac_ocp_write(tp, 0xd412, data);
5165         }
5166
5167         data = r8168_mac_ocp_read(tp, 0xe056);
5168         data &= ~0xf0;
5169         data |= 0x70;
5170         r8168_mac_ocp_write(tp, 0xe056, data);
5171
5172         data = r8168_mac_ocp_read(tp, 0xe052);
5173         data &= ~0x6000;
5174         data |= 0x8008;
5175         r8168_mac_ocp_write(tp, 0xe052, data);
5176
5177         data = r8168_mac_ocp_read(tp, 0xe0d6);
5178         data &= ~0x01ff;
5179         data |= 0x017f;
5180         r8168_mac_ocp_write(tp, 0xe0d6, data);
5181
5182         data = r8168_mac_ocp_read(tp, 0xd420);
5183         data &= ~0x0fff;
5184         data |= 0x047f;
5185         r8168_mac_ocp_write(tp, 0xd420, data);
5186
5187         r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
5188         r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
5189         r8168_mac_ocp_write(tp, 0xc094, 0x0000);
5190         r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
5191
5192         rtl_hw_aspm_clkreq_enable(tp, true);
5193 }
5194
5195 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
5196 {
5197         rtl8168ep_stop_cmac(tp);
5198
5199         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
5200         rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
5201
5202         rtl_set_def_aspm_entry_latency(tp);
5203
5204         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5205
5206         rtl_reset_packet_filter(tp);
5207
5208         rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f80);
5209
5210         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
5211
5212         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5213         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5214
5215         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
5216         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
5217
5218         rtl8168_config_eee_mac(tp);
5219
5220         rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06);
5221
5222         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
5223
5224         rtl_pcie_state_l2l3_disable(tp);
5225 }
5226
5227 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
5228 {
5229         static const struct ephy_info e_info_8168ep_1[] = {
5230                 { 0x00, 0xffff, 0x10ab },
5231                 { 0x06, 0xffff, 0xf030 },
5232                 { 0x08, 0xffff, 0x2006 },
5233                 { 0x0d, 0xffff, 0x1666 },
5234                 { 0x0c, 0x3ff0, 0x0000 }
5235         };
5236
5237         /* disable aspm and clock request before access ephy */
5238         rtl_hw_aspm_clkreq_enable(tp, false);
5239         rtl_ephy_init(tp, e_info_8168ep_1);
5240
5241         rtl_hw_start_8168ep(tp);
5242
5243         rtl_hw_aspm_clkreq_enable(tp, true);
5244 }
5245
5246 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
5247 {
5248         static const struct ephy_info e_info_8168ep_2[] = {
5249                 { 0x00, 0xffff, 0x10a3 },
5250                 { 0x19, 0xffff, 0xfc00 },
5251                 { 0x1e, 0xffff, 0x20ea }
5252         };
5253
5254         /* disable aspm and clock request before access ephy */
5255         rtl_hw_aspm_clkreq_enable(tp, false);
5256         rtl_ephy_init(tp, e_info_8168ep_2);
5257
5258         rtl_hw_start_8168ep(tp);
5259
5260         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5261         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5262
5263         rtl_hw_aspm_clkreq_enable(tp, true);
5264 }
5265
5266 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
5267 {
5268         u32 data;
5269         static const struct ephy_info e_info_8168ep_3[] = {
5270                 { 0x00, 0xffff, 0x10a3 },
5271                 { 0x19, 0xffff, 0x7c00 },
5272                 { 0x1e, 0xffff, 0x20eb },
5273                 { 0x0d, 0xffff, 0x1666 }
5274         };
5275
5276         /* disable aspm and clock request before access ephy */
5277         rtl_hw_aspm_clkreq_enable(tp, false);
5278         rtl_ephy_init(tp, e_info_8168ep_3);
5279
5280         rtl_hw_start_8168ep(tp);
5281
5282         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5283         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5284
5285         data = r8168_mac_ocp_read(tp, 0xd3e2);
5286         data &= 0xf000;
5287         data |= 0x0271;
5288         r8168_mac_ocp_write(tp, 0xd3e2, data);
5289
5290         data = r8168_mac_ocp_read(tp, 0xd3e4);
5291         data &= 0xff00;
5292         r8168_mac_ocp_write(tp, 0xd3e4, data);
5293
5294         data = r8168_mac_ocp_read(tp, 0xe860);
5295         data |= 0x0080;
5296         r8168_mac_ocp_write(tp, 0xe860, data);
5297
5298         rtl_hw_aspm_clkreq_enable(tp, true);
5299 }
5300
5301 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
5302 {
5303         static const struct ephy_info e_info_8102e_1[] = {
5304                 { 0x01, 0, 0x6e65 },
5305                 { 0x02, 0, 0x091f },
5306                 { 0x03, 0, 0xc2f9 },
5307                 { 0x06, 0, 0xafb5 },
5308                 { 0x07, 0, 0x0e00 },
5309                 { 0x19, 0, 0xec80 },
5310                 { 0x01, 0, 0x2e65 },
5311                 { 0x01, 0, 0x6e65 }
5312         };
5313         u8 cfg1;
5314
5315         rtl_set_def_aspm_entry_latency(tp);
5316
5317         RTL_W8(tp, DBG_REG, FIX_NAK_1);
5318
5319         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5320
5321         RTL_W8(tp, Config1,
5322                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5323         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5324
5325         cfg1 = RTL_R8(tp, Config1);
5326         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5327                 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
5328
5329         rtl_ephy_init(tp, e_info_8102e_1);
5330 }
5331
5332 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
5333 {
5334         rtl_set_def_aspm_entry_latency(tp);
5335
5336         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5337
5338         RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
5339         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5340 }
5341
5342 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
5343 {
5344         rtl_hw_start_8102e_2(tp);
5345
5346         rtl_ephy_write(tp, 0x03, 0xc2f9);
5347 }
5348
5349 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5350 {
5351         static const struct ephy_info e_info_8105e_1[] = {
5352                 { 0x07, 0, 0x4000 },
5353                 { 0x19, 0, 0x0200 },
5354                 { 0x19, 0, 0x0020 },
5355                 { 0x1e, 0, 0x2000 },
5356                 { 0x03, 0, 0x0001 },
5357                 { 0x19, 0, 0x0100 },
5358                 { 0x19, 0, 0x0004 },
5359                 { 0x0a, 0, 0x0020 }
5360         };
5361
5362         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5363         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5364
5365         /* Disable Early Tally Counter */
5366         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
5367
5368         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5369         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5370
5371         rtl_ephy_init(tp, e_info_8105e_1);
5372
5373         rtl_pcie_state_l2l3_disable(tp);
5374 }
5375
5376 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5377 {
5378         rtl_hw_start_8105e_1(tp);
5379         rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5380 }
5381
5382 static void rtl_hw_start_8402(struct rtl8169_private *tp)
5383 {
5384         static const struct ephy_info e_info_8402[] = {
5385                 { 0x19, 0xffff, 0xff64 },
5386                 { 0x1e, 0, 0x4000 }
5387         };
5388
5389         rtl_set_def_aspm_entry_latency(tp);
5390
5391         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5392         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5393
5394         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5395
5396         rtl_ephy_init(tp, e_info_8402);
5397
5398         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5399
5400         rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06);
5401         rtl_reset_packet_filter(tp);
5402         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
5403         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
5404         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00);
5405
5406         rtl_pcie_state_l2l3_disable(tp);
5407 }
5408
5409 static void rtl_hw_start_8106(struct rtl8169_private *tp)
5410 {
5411         rtl_hw_aspm_clkreq_enable(tp, false);
5412
5413         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5414         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5415
5416         RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5417         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5418         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5419
5420         rtl_pcie_state_l2l3_disable(tp);
5421         rtl_hw_aspm_clkreq_enable(tp, true);
5422 }
5423
5424 static void rtl_hw_config(struct rtl8169_private *tp)
5425 {
5426         static const rtl_generic_fct hw_configs[] = {
5427                 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1,
5428                 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3,
5429                 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2,
5430                 [RTL_GIGA_MAC_VER_10] = NULL,
5431                 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168bb,
5432                 [RTL_GIGA_MAC_VER_12] = rtl_hw_start_8168bef,
5433                 [RTL_GIGA_MAC_VER_13] = NULL,
5434                 [RTL_GIGA_MAC_VER_14] = NULL,
5435                 [RTL_GIGA_MAC_VER_15] = NULL,
5436                 [RTL_GIGA_MAC_VER_16] = NULL,
5437                 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168bef,
5438                 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1,
5439                 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1,
5440                 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2,
5441                 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_3,
5442                 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4,
5443                 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2,
5444                 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3,
5445                 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d,
5446                 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d,
5447                 [RTL_GIGA_MAC_VER_27] = rtl_hw_start_8168d,
5448                 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4,
5449                 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1,
5450                 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2,
5451                 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168dp,
5452                 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1,
5453                 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1,
5454                 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2,
5455                 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1,
5456                 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1,
5457                 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402,
5458                 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411,
5459                 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106,
5460                 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1,
5461                 [RTL_GIGA_MAC_VER_41] = rtl_hw_start_8168g_1,
5462                 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2,
5463                 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2,
5464                 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2,
5465                 [RTL_GIGA_MAC_VER_45] = rtl_hw_start_8168h_1,
5466                 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1,
5467                 [RTL_GIGA_MAC_VER_47] = rtl_hw_start_8168h_1,
5468                 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1,
5469                 [RTL_GIGA_MAC_VER_49] = rtl_hw_start_8168ep_1,
5470                 [RTL_GIGA_MAC_VER_50] = rtl_hw_start_8168ep_2,
5471                 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3,
5472         };
5473
5474         if (hw_configs[tp->mac_version])
5475                 hw_configs[tp->mac_version](tp);
5476 }
5477
5478 static void rtl_hw_start_8168(struct rtl8169_private *tp)
5479 {
5480         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5481
5482         /* Workaround for RxFIFO overflow. */
5483         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
5484                 tp->irq_mask |= RxFIFOOver;
5485                 tp->irq_mask &= ~RxOverflow;
5486         }
5487
5488         rtl_hw_config(tp);
5489 }
5490
5491 static void rtl_hw_start_8101(struct rtl8169_private *tp)
5492 {
5493         if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
5494                 tp->irq_mask &= ~RxFIFOOver;
5495
5496         if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
5497             tp->mac_version == RTL_GIGA_MAC_VER_16)
5498                 pcie_capability_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
5499                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
5500
5501         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5502
5503         tp->cp_cmd &= CPCMD_QUIRK_MASK;
5504         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5505
5506         rtl_hw_config(tp);
5507 }
5508
5509 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5510 {
5511         struct rtl8169_private *tp = netdev_priv(dev);
5512
5513         if (new_mtu > ETH_DATA_LEN)
5514                 rtl_hw_jumbo_enable(tp);
5515         else
5516                 rtl_hw_jumbo_disable(tp);
5517
5518         dev->mtu = new_mtu;
5519         netdev_update_features(dev);
5520
5521         return 0;
5522 }
5523
5524 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5525 {
5526         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
5527         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5528 }
5529
5530 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5531                                      void **data_buff, struct RxDesc *desc)
5532 {
5533         dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr),
5534                          R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
5535
5536         kfree(*data_buff);
5537         *data_buff = NULL;
5538         rtl8169_make_unusable_by_asic(desc);
5539 }
5540
5541 static inline void rtl8169_mark_to_asic(struct RxDesc *desc)
5542 {
5543         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5544
5545         /* Force memory writes to complete before releasing descriptor */
5546         dma_wmb();
5547
5548         desc->opts1 = cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE);
5549 }
5550
5551 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5552                                              struct RxDesc *desc)
5553 {
5554         void *data;
5555         dma_addr_t mapping;
5556         struct device *d = tp_to_dev(tp);
5557         int node = dev_to_node(d);
5558
5559         data = kmalloc_node(R8169_RX_BUF_SIZE, GFP_KERNEL, node);
5560         if (!data)
5561                 return NULL;
5562
5563         /* Memory should be properly aligned, but better check. */
5564         if (!IS_ALIGNED((unsigned long)data, 8)) {
5565                 netdev_err_once(tp->dev, "RX buffer not 8-byte-aligned\n");
5566                 goto err_out;
5567         }
5568
5569         mapping = dma_map_single(d, data, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
5570         if (unlikely(dma_mapping_error(d, mapping))) {
5571                 if (net_ratelimit())
5572                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
5573                 goto err_out;
5574         }
5575
5576         desc->addr = cpu_to_le64(mapping);
5577         rtl8169_mark_to_asic(desc);
5578         return data;
5579
5580 err_out:
5581         kfree(data);
5582         return NULL;
5583 }
5584
5585 static void rtl8169_rx_clear(struct rtl8169_private *tp)
5586 {
5587         unsigned int i;
5588
5589         for (i = 0; i < NUM_RX_DESC; i++) {
5590                 if (tp->Rx_databuff[i]) {
5591                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
5592                                             tp->RxDescArray + i);
5593                 }
5594         }
5595 }
5596
5597 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
5598 {
5599         desc->opts1 |= cpu_to_le32(RingEnd);
5600 }
5601
5602 static int rtl8169_rx_fill(struct rtl8169_private *tp)
5603 {
5604         unsigned int i;
5605
5606         for (i = 0; i < NUM_RX_DESC; i++) {
5607                 void *data;
5608
5609                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
5610                 if (!data) {
5611                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
5612                         goto err_out;
5613                 }
5614                 tp->Rx_databuff[i] = data;
5615         }
5616
5617         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5618         return 0;
5619
5620 err_out:
5621         rtl8169_rx_clear(tp);
5622         return -ENOMEM;
5623 }
5624
5625 static int rtl8169_init_ring(struct rtl8169_private *tp)
5626 {
5627         rtl8169_init_ring_indexes(tp);
5628
5629         memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
5630         memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
5631
5632         return rtl8169_rx_fill(tp);
5633 }
5634
5635 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
5636                                  struct TxDesc *desc)
5637 {
5638         unsigned int len = tx_skb->len;
5639
5640         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5641
5642         desc->opts1 = 0x00;
5643         desc->opts2 = 0x00;
5644         desc->addr = 0x00;
5645         tx_skb->len = 0;
5646 }
5647
5648 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5649                                    unsigned int n)
5650 {
5651         unsigned int i;
5652
5653         for (i = 0; i < n; i++) {
5654                 unsigned int entry = (start + i) % NUM_TX_DESC;
5655                 struct ring_info *tx_skb = tp->tx_skb + entry;
5656                 unsigned int len = tx_skb->len;
5657
5658                 if (len) {
5659                         struct sk_buff *skb = tx_skb->skb;
5660
5661                         rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
5662                                              tp->TxDescArray + entry);
5663                         if (skb) {
5664                                 dev_consume_skb_any(skb);
5665                                 tx_skb->skb = NULL;
5666                         }
5667                 }
5668         }
5669 }
5670
5671 static void rtl8169_tx_clear(struct rtl8169_private *tp)
5672 {
5673         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
5674         tp->cur_tx = tp->dirty_tx = 0;
5675         netdev_reset_queue(tp->dev);
5676 }
5677
5678 static void rtl_reset_work(struct rtl8169_private *tp)
5679 {
5680         struct net_device *dev = tp->dev;
5681         int i;
5682
5683         napi_disable(&tp->napi);
5684         netif_stop_queue(dev);
5685         synchronize_rcu();
5686
5687         rtl8169_hw_reset(tp);
5688
5689         for (i = 0; i < NUM_RX_DESC; i++)
5690                 rtl8169_mark_to_asic(tp->RxDescArray + i);
5691
5692         rtl8169_tx_clear(tp);
5693         rtl8169_init_ring_indexes(tp);
5694
5695         napi_enable(&tp->napi);
5696         rtl_hw_start(tp);
5697         netif_wake_queue(dev);
5698 }
5699
5700 static void rtl8169_tx_timeout(struct net_device *dev)
5701 {
5702         struct rtl8169_private *tp = netdev_priv(dev);
5703
5704         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5705 }
5706
5707 static __le32 rtl8169_get_txd_opts1(u32 opts0, u32 len, unsigned int entry)
5708 {
5709         u32 status = opts0 | len;
5710
5711         if (entry == NUM_TX_DESC - 1)
5712                 status |= RingEnd;
5713
5714         return cpu_to_le32(status);
5715 }
5716
5717 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5718                               u32 *opts)
5719 {
5720         struct skb_shared_info *info = skb_shinfo(skb);
5721         unsigned int cur_frag, entry;
5722         struct TxDesc *uninitialized_var(txd);
5723         struct device *d = tp_to_dev(tp);
5724
5725         entry = tp->cur_tx;
5726         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5727                 const skb_frag_t *frag = info->frags + cur_frag;
5728                 dma_addr_t mapping;
5729                 u32 len;
5730                 void *addr;
5731
5732                 entry = (entry + 1) % NUM_TX_DESC;
5733
5734                 txd = tp->TxDescArray + entry;
5735                 len = skb_frag_size(frag);
5736                 addr = skb_frag_address(frag);
5737                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5738                 if (unlikely(dma_mapping_error(d, mapping))) {
5739                         if (net_ratelimit())
5740                                 netif_err(tp, drv, tp->dev,
5741                                           "Failed to map TX fragments DMA!\n");
5742                         goto err_out;
5743                 }
5744
5745                 txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry);
5746                 txd->opts2 = cpu_to_le32(opts[1]);
5747                 txd->addr = cpu_to_le64(mapping);
5748
5749                 tp->tx_skb[entry].len = len;
5750         }
5751
5752         if (cur_frag) {
5753                 tp->tx_skb[entry].skb = skb;
5754                 txd->opts1 |= cpu_to_le32(LastFrag);
5755         }
5756
5757         return cur_frag;
5758
5759 err_out:
5760         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5761         return -EIO;
5762 }
5763
5764 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
5765 {
5766         return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
5767 }
5768
5769 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5770                                       struct net_device *dev);
5771 /* r8169_csum_workaround()
5772  * The hw limites the value the transport offset. When the offset is out of the
5773  * range, calculate the checksum by sw.
5774  */
5775 static void r8169_csum_workaround(struct rtl8169_private *tp,
5776                                   struct sk_buff *skb)
5777 {
5778         if (skb_shinfo(skb)->gso_size) {
5779                 netdev_features_t features = tp->dev->features;
5780                 struct sk_buff *segs, *nskb;
5781
5782                 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
5783                 segs = skb_gso_segment(skb, features);
5784                 if (IS_ERR(segs) || !segs)
5785                         goto drop;
5786
5787                 do {
5788                         nskb = segs;
5789                         segs = segs->next;
5790                         nskb->next = NULL;
5791                         rtl8169_start_xmit(nskb, tp->dev);
5792                 } while (segs);
5793
5794                 dev_consume_skb_any(skb);
5795         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5796                 if (skb_checksum_help(skb) < 0)
5797                         goto drop;
5798
5799                 rtl8169_start_xmit(skb, tp->dev);
5800         } else {
5801                 struct net_device_stats *stats;
5802
5803 drop:
5804                 stats = &tp->dev->stats;
5805                 stats->tx_dropped++;
5806                 dev_kfree_skb_any(skb);
5807         }
5808 }
5809
5810 /* msdn_giant_send_check()
5811  * According to the document of microsoft, the TCP Pseudo Header excludes the
5812  * packet length for IPv6 TCP large packets.
5813  */
5814 static int msdn_giant_send_check(struct sk_buff *skb)
5815 {
5816         const struct ipv6hdr *ipv6h;
5817         struct tcphdr *th;
5818         int ret;
5819
5820         ret = skb_cow_head(skb, 0);
5821         if (ret)
5822                 return ret;
5823
5824         ipv6h = ipv6_hdr(skb);
5825         th = tcp_hdr(skb);
5826
5827         th->check = 0;
5828         th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
5829
5830         return ret;
5831 }
5832
5833 static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp,
5834                                 struct sk_buff *skb, u32 *opts)
5835 {
5836         u32 mss = skb_shinfo(skb)->gso_size;
5837
5838         if (mss) {
5839                 opts[0] |= TD_LSO;
5840                 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
5841         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5842                 const struct iphdr *ip = ip_hdr(skb);
5843
5844                 if (ip->protocol == IPPROTO_TCP)
5845                         opts[0] |= TD0_IP_CS | TD0_TCP_CS;
5846                 else if (ip->protocol == IPPROTO_UDP)
5847                         opts[0] |= TD0_IP_CS | TD0_UDP_CS;
5848                 else
5849                         WARN_ON_ONCE(1);
5850         }
5851
5852         return true;
5853 }
5854
5855 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
5856                                 struct sk_buff *skb, u32 *opts)
5857 {
5858         u32 transport_offset = (u32)skb_transport_offset(skb);
5859         u32 mss = skb_shinfo(skb)->gso_size;
5860
5861         if (mss) {
5862                 if (transport_offset > GTTCPHO_MAX) {
5863                         netif_warn(tp, tx_err, tp->dev,
5864                                    "Invalid transport offset 0x%x for TSO\n",
5865                                    transport_offset);
5866                         return false;
5867                 }
5868
5869                 switch (vlan_get_protocol(skb)) {
5870                 case htons(ETH_P_IP):
5871                         opts[0] |= TD1_GTSENV4;
5872                         break;
5873
5874                 case htons(ETH_P_IPV6):
5875                         if (msdn_giant_send_check(skb))
5876                                 return false;
5877
5878                         opts[0] |= TD1_GTSENV6;
5879                         break;
5880
5881                 default:
5882                         WARN_ON_ONCE(1);
5883                         break;
5884                 }
5885
5886                 opts[0] |= transport_offset << GTTCPHO_SHIFT;
5887                 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
5888         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5889                 u8 ip_protocol;
5890
5891                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
5892                         return !(skb_checksum_help(skb) || eth_skb_pad(skb));
5893
5894                 if (transport_offset > TCPHO_MAX) {
5895                         netif_warn(tp, tx_err, tp->dev,
5896                                    "Invalid transport offset 0x%x\n",
5897                                    transport_offset);
5898                         return false;
5899                 }
5900
5901                 switch (vlan_get_protocol(skb)) {
5902                 case htons(ETH_P_IP):
5903                         opts[1] |= TD1_IPv4_CS;
5904                         ip_protocol = ip_hdr(skb)->protocol;
5905                         break;
5906
5907                 case htons(ETH_P_IPV6):
5908                         opts[1] |= TD1_IPv6_CS;
5909                         ip_protocol = ipv6_hdr(skb)->nexthdr;
5910                         break;
5911
5912                 default:
5913                         ip_protocol = IPPROTO_RAW;
5914                         break;
5915                 }
5916
5917                 if (ip_protocol == IPPROTO_TCP)
5918                         opts[1] |= TD1_TCP_CS;
5919                 else if (ip_protocol == IPPROTO_UDP)
5920                         opts[1] |= TD1_UDP_CS;
5921                 else
5922                         WARN_ON_ONCE(1);
5923
5924                 opts[1] |= transport_offset << TCPHO_SHIFT;
5925         } else {
5926                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
5927                         return !eth_skb_pad(skb);
5928         }
5929
5930         return true;
5931 }
5932
5933 static bool rtl_tx_slots_avail(struct rtl8169_private *tp,
5934                                unsigned int nr_frags)
5935 {
5936         unsigned int slots_avail = tp->dirty_tx + NUM_TX_DESC - tp->cur_tx;
5937
5938         /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
5939         return slots_avail > nr_frags;
5940 }
5941
5942 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5943                                       struct net_device *dev)
5944 {
5945         struct rtl8169_private *tp = netdev_priv(dev);
5946         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
5947         struct TxDesc *txd = tp->TxDescArray + entry;
5948         struct device *d = tp_to_dev(tp);
5949         dma_addr_t mapping;
5950         u32 opts[2], len;
5951         int frags;
5952
5953         if (unlikely(!rtl_tx_slots_avail(tp, skb_shinfo(skb)->nr_frags))) {
5954                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
5955                 goto err_stop_0;
5956         }
5957
5958         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
5959                 goto err_stop_0;
5960
5961         opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
5962         opts[0] = DescOwn;
5963
5964         if (!tp->tso_csum(tp, skb, opts)) {
5965                 r8169_csum_workaround(tp, skb);
5966                 return NETDEV_TX_OK;
5967         }
5968
5969         len = skb_headlen(skb);
5970         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
5971         if (unlikely(dma_mapping_error(d, mapping))) {
5972                 if (net_ratelimit())
5973                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
5974                 goto err_dma_0;
5975         }
5976
5977         tp->tx_skb[entry].len = len;
5978         txd->addr = cpu_to_le64(mapping);
5979
5980         frags = rtl8169_xmit_frags(tp, skb, opts);
5981         if (frags < 0)
5982                 goto err_dma_1;
5983         else if (frags)
5984                 opts[0] |= FirstFrag;
5985         else {
5986                 opts[0] |= FirstFrag | LastFrag;
5987                 tp->tx_skb[entry].skb = skb;
5988         }
5989
5990         txd->opts2 = cpu_to_le32(opts[1]);
5991
5992         netdev_sent_queue(dev, skb->len);
5993
5994         skb_tx_timestamp(skb);
5995
5996         /* Force memory writes to complete before releasing descriptor */
5997         dma_wmb();
5998
5999         txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry);
6000
6001         /* Force all memory writes to complete before notifying device */
6002         wmb();
6003
6004         tp->cur_tx += frags + 1;
6005
6006         RTL_W8(tp, TxPoll, NPQ);
6007
6008         if (!rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) {
6009                 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
6010                  * not miss a ring update when it notices a stopped queue.
6011                  */
6012                 smp_wmb();
6013                 netif_stop_queue(dev);
6014                 /* Sync with rtl_tx:
6015                  * - publish queue status and cur_tx ring index (write barrier)
6016                  * - refresh dirty_tx ring index (read barrier).
6017                  * May the current thread have a pessimistic view of the ring
6018                  * status and forget to wake up queue, a racing rtl_tx thread
6019                  * can't.
6020                  */
6021                 smp_mb();
6022                 if (rtl_tx_slots_avail(tp, MAX_SKB_FRAGS))
6023                         netif_start_queue(dev);
6024         }
6025
6026         return NETDEV_TX_OK;
6027
6028 err_dma_1:
6029         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
6030 err_dma_0:
6031         dev_kfree_skb_any(skb);
6032         dev->stats.tx_dropped++;
6033         return NETDEV_TX_OK;
6034
6035 err_stop_0:
6036         netif_stop_queue(dev);
6037         dev->stats.tx_dropped++;
6038         return NETDEV_TX_BUSY;
6039 }
6040
6041 static void rtl8169_pcierr_interrupt(struct net_device *dev)
6042 {
6043         struct rtl8169_private *tp = netdev_priv(dev);
6044         struct pci_dev *pdev = tp->pci_dev;
6045         u16 pci_status, pci_cmd;
6046
6047         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
6048         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
6049
6050         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
6051                   pci_cmd, pci_status);
6052
6053         /*
6054          * The recovery sequence below admits a very elaborated explanation:
6055          * - it seems to work;
6056          * - I did not see what else could be done;
6057          * - it makes iop3xx happy.
6058          *
6059          * Feel free to adjust to your needs.
6060          */
6061         if (pdev->broken_parity_status)
6062                 pci_cmd &= ~PCI_COMMAND_PARITY;
6063         else
6064                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
6065
6066         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
6067
6068         pci_write_config_word(pdev, PCI_STATUS,
6069                 pci_status & (PCI_STATUS_DETECTED_PARITY |
6070                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
6071                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
6072
6073         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6074 }
6075
6076 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp,
6077                    int budget)
6078 {
6079         unsigned int dirty_tx, tx_left, bytes_compl = 0, pkts_compl = 0;
6080
6081         dirty_tx = tp->dirty_tx;
6082         smp_rmb();
6083         tx_left = tp->cur_tx - dirty_tx;
6084
6085         while (tx_left > 0) {
6086                 unsigned int entry = dirty_tx % NUM_TX_DESC;
6087                 struct ring_info *tx_skb = tp->tx_skb + entry;
6088                 u32 status;
6089
6090                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
6091                 if (status & DescOwn)
6092                         break;
6093
6094                 /* This barrier is needed to keep us from reading
6095                  * any other fields out of the Tx descriptor until
6096                  * we know the status of DescOwn
6097                  */
6098                 dma_rmb();
6099
6100                 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
6101                                      tp->TxDescArray + entry);
6102                 if (status & LastFrag) {
6103                         pkts_compl++;
6104                         bytes_compl += tx_skb->skb->len;
6105                         napi_consume_skb(tx_skb->skb, budget);
6106                         tx_skb->skb = NULL;
6107                 }
6108                 dirty_tx++;
6109                 tx_left--;
6110         }
6111
6112         if (tp->dirty_tx != dirty_tx) {
6113                 netdev_completed_queue(dev, pkts_compl, bytes_compl);
6114
6115                 u64_stats_update_begin(&tp->tx_stats.syncp);
6116                 tp->tx_stats.packets += pkts_compl;
6117                 tp->tx_stats.bytes += bytes_compl;
6118                 u64_stats_update_end(&tp->tx_stats.syncp);
6119
6120                 tp->dirty_tx = dirty_tx;
6121                 /* Sync with rtl8169_start_xmit:
6122                  * - publish dirty_tx ring index (write barrier)
6123                  * - refresh cur_tx ring index and queue status (read barrier)
6124                  * May the current thread miss the stopped queue condition,
6125                  * a racing xmit thread can only have a right view of the
6126                  * ring status.
6127                  */
6128                 smp_mb();
6129                 if (netif_queue_stopped(dev) &&
6130                     rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) {
6131                         netif_wake_queue(dev);
6132                 }
6133                 /*
6134                  * 8168 hack: TxPoll requests are lost when the Tx packets are
6135                  * too close. Let's kick an extra TxPoll request when a burst
6136                  * of start_xmit activity is detected (if it is not detected,
6137                  * it is slow enough). -- FR
6138                  */
6139                 if (tp->cur_tx != dirty_tx)
6140                         RTL_W8(tp, TxPoll, NPQ);
6141         }
6142 }
6143
6144 static inline int rtl8169_fragmented_frame(u32 status)
6145 {
6146         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
6147 }
6148
6149 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
6150 {
6151         u32 status = opts1 & RxProtoMask;
6152
6153         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
6154             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
6155                 skb->ip_summed = CHECKSUM_UNNECESSARY;
6156         else
6157                 skb_checksum_none_assert(skb);
6158 }
6159
6160 static struct sk_buff *rtl8169_try_rx_copy(void *data,
6161                                            struct rtl8169_private *tp,
6162                                            int pkt_size,
6163                                            dma_addr_t addr)
6164 {
6165         struct sk_buff *skb;
6166         struct device *d = tp_to_dev(tp);
6167
6168         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6169         prefetch(data);
6170         skb = napi_alloc_skb(&tp->napi, pkt_size);
6171         if (skb)
6172                 skb_copy_to_linear_data(skb, data, pkt_size);
6173         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
6174
6175         return skb;
6176 }
6177
6178 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
6179 {
6180         unsigned int cur_rx, rx_left;
6181         unsigned int count;
6182
6183         cur_rx = tp->cur_rx;
6184
6185         for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
6186                 unsigned int entry = cur_rx % NUM_RX_DESC;
6187                 struct RxDesc *desc = tp->RxDescArray + entry;
6188                 u32 status;
6189
6190                 status = le32_to_cpu(desc->opts1);
6191                 if (status & DescOwn)
6192                         break;
6193
6194                 /* This barrier is needed to keep us from reading
6195                  * any other fields out of the Rx descriptor until
6196                  * we know the status of DescOwn
6197                  */
6198                 dma_rmb();
6199
6200                 if (unlikely(status & RxRES)) {
6201                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
6202                                    status);
6203                         dev->stats.rx_errors++;
6204                         if (status & (RxRWT | RxRUNT))
6205                                 dev->stats.rx_length_errors++;
6206                         if (status & RxCRC)
6207                                 dev->stats.rx_crc_errors++;
6208                         if (status & (RxRUNT | RxCRC) && !(status & RxRWT) &&
6209                             dev->features & NETIF_F_RXALL) {
6210                                 goto process_pkt;
6211                         }
6212                 } else {
6213                         struct sk_buff *skb;
6214                         dma_addr_t addr;
6215                         int pkt_size;
6216
6217 process_pkt:
6218                         addr = le64_to_cpu(desc->addr);
6219                         if (likely(!(dev->features & NETIF_F_RXFCS)))
6220                                 pkt_size = (status & 0x00003fff) - 4;
6221                         else
6222                                 pkt_size = status & 0x00003fff;
6223
6224                         /*
6225                          * The driver does not support incoming fragmented
6226                          * frames. They are seen as a symptom of over-mtu
6227                          * sized frames.
6228                          */
6229                         if (unlikely(rtl8169_fragmented_frame(status))) {
6230                                 dev->stats.rx_dropped++;
6231                                 dev->stats.rx_length_errors++;
6232                                 goto release_descriptor;
6233                         }
6234
6235                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
6236                                                   tp, pkt_size, addr);
6237                         if (!skb) {
6238                                 dev->stats.rx_dropped++;
6239                                 goto release_descriptor;
6240                         }
6241
6242                         rtl8169_rx_csum(skb, status);
6243                         skb_put(skb, pkt_size);
6244                         skb->protocol = eth_type_trans(skb, dev);
6245
6246                         rtl8169_rx_vlan_tag(desc, skb);
6247
6248                         if (skb->pkt_type == PACKET_MULTICAST)
6249                                 dev->stats.multicast++;
6250
6251                         napi_gro_receive(&tp->napi, skb);
6252
6253                         u64_stats_update_begin(&tp->rx_stats.syncp);
6254                         tp->rx_stats.packets++;
6255                         tp->rx_stats.bytes += pkt_size;
6256                         u64_stats_update_end(&tp->rx_stats.syncp);
6257                 }
6258 release_descriptor:
6259                 desc->opts2 = 0;
6260                 rtl8169_mark_to_asic(desc);
6261         }
6262
6263         count = cur_rx - tp->cur_rx;
6264         tp->cur_rx = cur_rx;
6265
6266         return count;
6267 }
6268
6269 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
6270 {
6271         struct rtl8169_private *tp = dev_instance;
6272         u16 status = RTL_R16(tp, IntrStatus);
6273
6274         if (!tp->irq_enabled || status == 0xffff || !(status & tp->irq_mask))
6275                 return IRQ_NONE;
6276
6277         if (unlikely(status & SYSErr)) {
6278                 rtl8169_pcierr_interrupt(tp->dev);
6279                 goto out;
6280         }
6281
6282         if (status & LinkChg)
6283                 phy_mac_interrupt(tp->phydev);
6284
6285         if (unlikely(status & RxFIFOOver &&
6286             tp->mac_version == RTL_GIGA_MAC_VER_11)) {
6287                 netif_stop_queue(tp->dev);
6288                 /* XXX - Hack alert. See rtl_task(). */
6289                 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
6290         }
6291
6292         rtl_irq_disable(tp);
6293         napi_schedule_irqoff(&tp->napi);
6294 out:
6295         rtl_ack_events(tp, status);
6296
6297         return IRQ_HANDLED;
6298 }
6299
6300 static void rtl_task(struct work_struct *work)
6301 {
6302         static const struct {
6303                 int bitnr;
6304                 void (*action)(struct rtl8169_private *);
6305         } rtl_work[] = {
6306                 { RTL_FLAG_TASK_RESET_PENDING,  rtl_reset_work },
6307         };
6308         struct rtl8169_private *tp =
6309                 container_of(work, struct rtl8169_private, wk.work);
6310         struct net_device *dev = tp->dev;
6311         int i;
6312
6313         rtl_lock_work(tp);
6314
6315         if (!netif_running(dev) ||
6316             !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
6317                 goto out_unlock;
6318
6319         for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
6320                 bool pending;
6321
6322                 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
6323                 if (pending)
6324                         rtl_work[i].action(tp);
6325         }
6326
6327 out_unlock:
6328         rtl_unlock_work(tp);
6329 }
6330
6331 static int rtl8169_poll(struct napi_struct *napi, int budget)
6332 {
6333         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
6334         struct net_device *dev = tp->dev;
6335         int work_done;
6336
6337         work_done = rtl_rx(dev, tp, (u32) budget);
6338
6339         rtl_tx(dev, tp, budget);
6340
6341         if (work_done < budget) {
6342                 napi_complete_done(napi, work_done);
6343                 rtl_irq_enable(tp);
6344         }
6345
6346         return work_done;
6347 }
6348
6349 static void rtl8169_rx_missed(struct net_device *dev)
6350 {
6351         struct rtl8169_private *tp = netdev_priv(dev);
6352
6353         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
6354                 return;
6355
6356         dev->stats.rx_missed_errors += RTL_R32(tp, RxMissed) & 0xffffff;
6357         RTL_W32(tp, RxMissed, 0);
6358 }
6359
6360 static void r8169_phylink_handler(struct net_device *ndev)
6361 {
6362         struct rtl8169_private *tp = netdev_priv(ndev);
6363
6364         if (netif_carrier_ok(ndev)) {
6365                 rtl_link_chg_patch(tp);
6366                 pm_request_resume(&tp->pci_dev->dev);
6367         } else {
6368                 pm_runtime_idle(&tp->pci_dev->dev);
6369         }
6370
6371         if (net_ratelimit())
6372                 phy_print_status(tp->phydev);
6373 }
6374
6375 static int r8169_phy_connect(struct rtl8169_private *tp)
6376 {
6377         struct phy_device *phydev = tp->phydev;
6378         phy_interface_t phy_mode;
6379         int ret;
6380
6381         phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
6382                    PHY_INTERFACE_MODE_MII;
6383
6384         ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
6385                                  phy_mode);
6386         if (ret)
6387                 return ret;
6388
6389         if (!tp->supports_gmii)
6390                 phy_set_max_speed(phydev, SPEED_100);
6391
6392         phy_support_asym_pause(phydev);
6393
6394         phy_attached_info(phydev);
6395
6396         return 0;
6397 }
6398
6399 static void rtl8169_down(struct net_device *dev)
6400 {
6401         struct rtl8169_private *tp = netdev_priv(dev);
6402
6403         phy_stop(tp->phydev);
6404
6405         napi_disable(&tp->napi);
6406         netif_stop_queue(dev);
6407
6408         rtl8169_hw_reset(tp);
6409         /*
6410          * At this point device interrupts can not be enabled in any function,
6411          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6412          * and napi is disabled (rtl8169_poll).
6413          */
6414         rtl8169_rx_missed(dev);
6415
6416         /* Give a racing hard_start_xmit a few cycles to complete. */
6417         synchronize_rcu();
6418
6419         rtl8169_tx_clear(tp);
6420
6421         rtl8169_rx_clear(tp);
6422
6423         rtl_pll_power_down(tp);
6424 }
6425
6426 static int rtl8169_close(struct net_device *dev)
6427 {
6428         struct rtl8169_private *tp = netdev_priv(dev);
6429         struct pci_dev *pdev = tp->pci_dev;
6430
6431         pm_runtime_get_sync(&pdev->dev);
6432
6433         /* Update counters before going down */
6434         rtl8169_update_counters(tp);
6435
6436         rtl_lock_work(tp);
6437         /* Clear all task flags */
6438         bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6439
6440         rtl8169_down(dev);
6441         rtl_unlock_work(tp);
6442
6443         cancel_work_sync(&tp->wk.work);
6444
6445         phy_disconnect(tp->phydev);
6446
6447         pci_free_irq(pdev, 0, tp);
6448
6449         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6450                           tp->RxPhyAddr);
6451         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6452                           tp->TxPhyAddr);
6453         tp->TxDescArray = NULL;
6454         tp->RxDescArray = NULL;
6455
6456         pm_runtime_put_sync(&pdev->dev);
6457
6458         return 0;
6459 }
6460
6461 #ifdef CONFIG_NET_POLL_CONTROLLER
6462 static void rtl8169_netpoll(struct net_device *dev)
6463 {
6464         struct rtl8169_private *tp = netdev_priv(dev);
6465
6466         rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp);
6467 }
6468 #endif
6469
6470 static int rtl_open(struct net_device *dev)
6471 {
6472         struct rtl8169_private *tp = netdev_priv(dev);
6473         struct pci_dev *pdev = tp->pci_dev;
6474         int retval = -ENOMEM;
6475
6476         pm_runtime_get_sync(&pdev->dev);
6477
6478         /*
6479          * Rx and Tx descriptors needs 256 bytes alignment.
6480          * dma_alloc_coherent provides more.
6481          */
6482         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6483                                              &tp->TxPhyAddr, GFP_KERNEL);
6484         if (!tp->TxDescArray)
6485                 goto err_pm_runtime_put;
6486
6487         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6488                                              &tp->RxPhyAddr, GFP_KERNEL);
6489         if (!tp->RxDescArray)
6490                 goto err_free_tx_0;
6491
6492         retval = rtl8169_init_ring(tp);
6493         if (retval < 0)
6494                 goto err_free_rx_1;
6495
6496         rtl_request_firmware(tp);
6497
6498         retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, tp,
6499                                  dev->name);
6500         if (retval < 0)
6501                 goto err_release_fw_2;
6502
6503         retval = r8169_phy_connect(tp);
6504         if (retval)
6505                 goto err_free_irq;
6506
6507         rtl_lock_work(tp);
6508
6509         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6510
6511         napi_enable(&tp->napi);
6512
6513         rtl8169_init_phy(dev, tp);
6514
6515         rtl_pll_power_up(tp);
6516
6517         rtl_hw_start(tp);
6518
6519         if (!rtl8169_init_counter_offsets(tp))
6520                 netif_warn(tp, hw, dev, "counter reset/update failed\n");
6521
6522         phy_start(tp->phydev);
6523         netif_start_queue(dev);
6524
6525         rtl_unlock_work(tp);
6526
6527         pm_runtime_put_sync(&pdev->dev);
6528 out:
6529         return retval;
6530
6531 err_free_irq:
6532         pci_free_irq(pdev, 0, tp);
6533 err_release_fw_2:
6534         rtl_release_firmware(tp);
6535         rtl8169_rx_clear(tp);
6536 err_free_rx_1:
6537         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6538                           tp->RxPhyAddr);
6539         tp->RxDescArray = NULL;
6540 err_free_tx_0:
6541         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6542                           tp->TxPhyAddr);
6543         tp->TxDescArray = NULL;
6544 err_pm_runtime_put:
6545         pm_runtime_put_noidle(&pdev->dev);
6546         goto out;
6547 }
6548
6549 static void
6550 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
6551 {
6552         struct rtl8169_private *tp = netdev_priv(dev);
6553         struct pci_dev *pdev = tp->pci_dev;
6554         struct rtl8169_counters *counters = tp->counters;
6555         unsigned int start;
6556
6557         pm_runtime_get_noresume(&pdev->dev);
6558
6559         if (netif_running(dev) && pm_runtime_active(&pdev->dev))
6560                 rtl8169_rx_missed(dev);
6561
6562         do {
6563                 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
6564                 stats->rx_packets = tp->rx_stats.packets;
6565                 stats->rx_bytes = tp->rx_stats.bytes;
6566         } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
6567
6568         do {
6569                 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
6570                 stats->tx_packets = tp->tx_stats.packets;
6571                 stats->tx_bytes = tp->tx_stats.bytes;
6572         } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
6573
6574         stats->rx_dropped       = dev->stats.rx_dropped;
6575         stats->tx_dropped       = dev->stats.tx_dropped;
6576         stats->rx_length_errors = dev->stats.rx_length_errors;
6577         stats->rx_errors        = dev->stats.rx_errors;
6578         stats->rx_crc_errors    = dev->stats.rx_crc_errors;
6579         stats->rx_fifo_errors   = dev->stats.rx_fifo_errors;
6580         stats->rx_missed_errors = dev->stats.rx_missed_errors;
6581         stats->multicast        = dev->stats.multicast;
6582
6583         /*
6584          * Fetch additonal counter values missing in stats collected by driver
6585          * from tally counters.
6586          */
6587         if (pm_runtime_active(&pdev->dev))
6588                 rtl8169_update_counters(tp);
6589
6590         /*
6591          * Subtract values fetched during initalization.
6592          * See rtl8169_init_counter_offsets for a description why we do that.
6593          */
6594         stats->tx_errors = le64_to_cpu(counters->tx_errors) -
6595                 le64_to_cpu(tp->tc_offset.tx_errors);
6596         stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
6597                 le32_to_cpu(tp->tc_offset.tx_multi_collision);
6598         stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
6599                 le16_to_cpu(tp->tc_offset.tx_aborted);
6600
6601         pm_runtime_put_noidle(&pdev->dev);
6602 }
6603
6604 static void rtl8169_net_suspend(struct net_device *dev)
6605 {
6606         struct rtl8169_private *tp = netdev_priv(dev);
6607
6608         if (!netif_running(dev))
6609                 return;
6610
6611         phy_stop(tp->phydev);
6612         netif_device_detach(dev);
6613
6614         rtl_lock_work(tp);
6615         napi_disable(&tp->napi);
6616         /* Clear all task flags */
6617         bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6618
6619         rtl_unlock_work(tp);
6620
6621         rtl_pll_power_down(tp);
6622 }
6623
6624 #ifdef CONFIG_PM
6625
6626 static int rtl8169_suspend(struct device *device)
6627 {
6628         struct net_device *dev = dev_get_drvdata(device);
6629         struct rtl8169_private *tp = netdev_priv(dev);
6630
6631         rtl8169_net_suspend(dev);
6632         clk_disable_unprepare(tp->clk);
6633
6634         return 0;
6635 }
6636
6637 static void __rtl8169_resume(struct net_device *dev)
6638 {
6639         struct rtl8169_private *tp = netdev_priv(dev);
6640
6641         netif_device_attach(dev);
6642
6643         rtl_pll_power_up(tp);
6644         rtl8169_init_phy(dev, tp);
6645
6646         phy_start(tp->phydev);
6647
6648         rtl_lock_work(tp);
6649         napi_enable(&tp->napi);
6650         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6651         rtl_reset_work(tp);
6652         rtl_unlock_work(tp);
6653 }
6654
6655 static int rtl8169_resume(struct device *device)
6656 {
6657         struct net_device *dev = dev_get_drvdata(device);
6658         struct rtl8169_private *tp = netdev_priv(dev);
6659
6660         clk_prepare_enable(tp->clk);
6661
6662         if (netif_running(dev))
6663                 __rtl8169_resume(dev);
6664
6665         return 0;
6666 }
6667
6668 static int rtl8169_runtime_suspend(struct device *device)
6669 {
6670         struct net_device *dev = dev_get_drvdata(device);
6671         struct rtl8169_private *tp = netdev_priv(dev);
6672
6673         if (!tp->TxDescArray)
6674                 return 0;
6675
6676         rtl_lock_work(tp);
6677         __rtl8169_set_wol(tp, WAKE_ANY);
6678         rtl_unlock_work(tp);
6679
6680         rtl8169_net_suspend(dev);
6681
6682         /* Update counters before going runtime suspend */
6683         rtl8169_rx_missed(dev);
6684         rtl8169_update_counters(tp);
6685
6686         return 0;
6687 }
6688
6689 static int rtl8169_runtime_resume(struct device *device)
6690 {
6691         struct net_device *dev = dev_get_drvdata(device);
6692         struct rtl8169_private *tp = netdev_priv(dev);
6693         rtl_rar_set(tp, dev->dev_addr);
6694
6695         if (!tp->TxDescArray)
6696                 return 0;
6697
6698         rtl_lock_work(tp);
6699         __rtl8169_set_wol(tp, tp->saved_wolopts);
6700         rtl_unlock_work(tp);
6701
6702         __rtl8169_resume(dev);
6703
6704         return 0;
6705 }
6706
6707 static int rtl8169_runtime_idle(struct device *device)
6708 {
6709         struct net_device *dev = dev_get_drvdata(device);
6710
6711         if (!netif_running(dev) || !netif_carrier_ok(dev))
6712                 pm_schedule_suspend(device, 10000);
6713
6714         return -EBUSY;
6715 }
6716
6717 static const struct dev_pm_ops rtl8169_pm_ops = {
6718         .suspend                = rtl8169_suspend,
6719         .resume                 = rtl8169_resume,
6720         .freeze                 = rtl8169_suspend,
6721         .thaw                   = rtl8169_resume,
6722         .poweroff               = rtl8169_suspend,
6723         .restore                = rtl8169_resume,
6724         .runtime_suspend        = rtl8169_runtime_suspend,
6725         .runtime_resume         = rtl8169_runtime_resume,
6726         .runtime_idle           = rtl8169_runtime_idle,
6727 };
6728
6729 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
6730
6731 #else /* !CONFIG_PM */
6732
6733 #define RTL8169_PM_OPS  NULL
6734
6735 #endif /* !CONFIG_PM */
6736
6737 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6738 {
6739         /* WoL fails with 8168b when the receiver is disabled. */
6740         switch (tp->mac_version) {
6741         case RTL_GIGA_MAC_VER_11:
6742         case RTL_GIGA_MAC_VER_12:
6743         case RTL_GIGA_MAC_VER_17:
6744                 pci_clear_master(tp->pci_dev);
6745
6746                 RTL_W8(tp, ChipCmd, CmdRxEnb);
6747                 /* PCI commit */
6748                 RTL_R8(tp, ChipCmd);
6749                 break;
6750         default:
6751                 break;
6752         }
6753 }
6754
6755 static void rtl_shutdown(struct pci_dev *pdev)
6756 {
6757         struct net_device *dev = pci_get_drvdata(pdev);
6758         struct rtl8169_private *tp = netdev_priv(dev);
6759
6760         rtl8169_net_suspend(dev);
6761
6762         /* Restore original MAC address */
6763         rtl_rar_set(tp, dev->perm_addr);
6764
6765         rtl8169_hw_reset(tp);
6766
6767         if (system_state == SYSTEM_POWER_OFF) {
6768                 if (tp->saved_wolopts) {
6769                         rtl_wol_suspend_quirk(tp);
6770                         rtl_wol_shutdown_quirk(tp);
6771                 }
6772
6773                 pci_wake_from_d3(pdev, true);
6774                 pci_set_power_state(pdev, PCI_D3hot);
6775         }
6776 }
6777
6778 static void rtl_remove_one(struct pci_dev *pdev)
6779 {
6780         struct net_device *dev = pci_get_drvdata(pdev);
6781         struct rtl8169_private *tp = netdev_priv(dev);
6782
6783         if (r8168_check_dash(tp))
6784                 rtl8168_driver_stop(tp);
6785
6786         netif_napi_del(&tp->napi);
6787
6788         unregister_netdev(dev);
6789         mdiobus_unregister(tp->phydev->mdio.bus);
6790
6791         rtl_release_firmware(tp);
6792
6793         if (pci_dev_run_wake(pdev))
6794                 pm_runtime_get_noresume(&pdev->dev);
6795
6796         /* restore original MAC address */
6797         rtl_rar_set(tp, dev->perm_addr);
6798 }
6799
6800 static const struct net_device_ops rtl_netdev_ops = {
6801         .ndo_open               = rtl_open,
6802         .ndo_stop               = rtl8169_close,
6803         .ndo_get_stats64        = rtl8169_get_stats64,
6804         .ndo_start_xmit         = rtl8169_start_xmit,
6805         .ndo_tx_timeout         = rtl8169_tx_timeout,
6806         .ndo_validate_addr      = eth_validate_addr,
6807         .ndo_change_mtu         = rtl8169_change_mtu,
6808         .ndo_fix_features       = rtl8169_fix_features,
6809         .ndo_set_features       = rtl8169_set_features,
6810         .ndo_set_mac_address    = rtl_set_mac_address,
6811         .ndo_do_ioctl           = rtl8169_ioctl,
6812         .ndo_set_rx_mode        = rtl_set_rx_mode,
6813 #ifdef CONFIG_NET_POLL_CONTROLLER
6814         .ndo_poll_controller    = rtl8169_netpoll,
6815 #endif
6816
6817 };
6818
6819 static const struct rtl_cfg_info {
6820         void (*hw_start)(struct rtl8169_private *tp);
6821         u16 irq_mask;
6822         unsigned int has_gmii:1;
6823         const struct rtl_coalesce_info *coalesce_info;
6824 } rtl_cfg_infos [] = {
6825         [RTL_CFG_0] = {
6826                 .hw_start       = rtl_hw_start_8169,
6827                 .irq_mask       = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
6828                 .has_gmii       = 1,
6829                 .coalesce_info  = rtl_coalesce_info_8169,
6830         },
6831         [RTL_CFG_1] = {
6832                 .hw_start       = rtl_hw_start_8168,
6833                 .irq_mask       = LinkChg | RxOverflow,
6834                 .has_gmii       = 1,
6835                 .coalesce_info  = rtl_coalesce_info_8168_8136,
6836         },
6837         [RTL_CFG_2] = {
6838                 .hw_start       = rtl_hw_start_8101,
6839                 .irq_mask       = LinkChg | RxOverflow | RxFIFOOver,
6840                 .coalesce_info  = rtl_coalesce_info_8168_8136,
6841         }
6842 };
6843
6844 static int rtl_alloc_irq(struct rtl8169_private *tp)
6845 {
6846         unsigned int flags;
6847
6848         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
6849                 rtl_unlock_config_regs(tp);
6850                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
6851                 rtl_lock_config_regs(tp);
6852                 flags = PCI_IRQ_LEGACY;
6853         } else {
6854                 flags = PCI_IRQ_ALL_TYPES;
6855         }
6856
6857         return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
6858 }
6859
6860 static void rtl_read_mac_address(struct rtl8169_private *tp,
6861                                  u8 mac_addr[ETH_ALEN])
6862 {
6863         u32 value;
6864
6865         /* Get MAC address */
6866         switch (tp->mac_version) {
6867         case RTL_GIGA_MAC_VER_35 ... RTL_GIGA_MAC_VER_38:
6868         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
6869                 value = rtl_eri_read(tp, 0xe0);
6870                 mac_addr[0] = (value >>  0) & 0xff;
6871                 mac_addr[1] = (value >>  8) & 0xff;
6872                 mac_addr[2] = (value >> 16) & 0xff;
6873                 mac_addr[3] = (value >> 24) & 0xff;
6874
6875                 value = rtl_eri_read(tp, 0xe4);
6876                 mac_addr[4] = (value >>  0) & 0xff;
6877                 mac_addr[5] = (value >>  8) & 0xff;
6878                 break;
6879         default:
6880                 break;
6881         }
6882 }
6883
6884 DECLARE_RTL_COND(rtl_link_list_ready_cond)
6885 {
6886         return RTL_R8(tp, MCU) & LINK_LIST_RDY;
6887 }
6888
6889 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
6890 {
6891         return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
6892 }
6893
6894 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
6895 {
6896         struct rtl8169_private *tp = mii_bus->priv;
6897
6898         if (phyaddr > 0)
6899                 return -ENODEV;
6900
6901         return rtl_readphy(tp, phyreg);
6902 }
6903
6904 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
6905                                 int phyreg, u16 val)
6906 {
6907         struct rtl8169_private *tp = mii_bus->priv;
6908
6909         if (phyaddr > 0)
6910                 return -ENODEV;
6911
6912         rtl_writephy(tp, phyreg, val);
6913
6914         return 0;
6915 }
6916
6917 static int r8169_mdio_register(struct rtl8169_private *tp)
6918 {
6919         struct pci_dev *pdev = tp->pci_dev;
6920         struct mii_bus *new_bus;
6921         int ret;
6922
6923         new_bus = devm_mdiobus_alloc(&pdev->dev);
6924         if (!new_bus)
6925                 return -ENOMEM;
6926
6927         new_bus->name = "r8169";
6928         new_bus->priv = tp;
6929         new_bus->parent = &pdev->dev;
6930         new_bus->irq[0] = PHY_IGNORE_INTERRUPT;
6931         snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x", pci_dev_id(pdev));
6932
6933         new_bus->read = r8169_mdio_read_reg;
6934         new_bus->write = r8169_mdio_write_reg;
6935
6936         ret = mdiobus_register(new_bus);
6937         if (ret)
6938                 return ret;
6939
6940         tp->phydev = mdiobus_get_phy(new_bus, 0);
6941         if (!tp->phydev) {
6942                 mdiobus_unregister(new_bus);
6943                 return -ENODEV;
6944         }
6945
6946         /* PHY will be woken up in rtl_open() */
6947         phy_suspend(tp->phydev);
6948
6949         return 0;
6950 }
6951
6952 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
6953 {
6954         u32 data;
6955
6956         tp->ocp_base = OCP_STD_PHY_BASE;
6957
6958         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
6959
6960         if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
6961                 return;
6962
6963         if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
6964                 return;
6965
6966         RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
6967         msleep(1);
6968         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
6969
6970         data = r8168_mac_ocp_read(tp, 0xe8de);
6971         data &= ~(1 << 14);
6972         r8168_mac_ocp_write(tp, 0xe8de, data);
6973
6974         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
6975                 return;
6976
6977         data = r8168_mac_ocp_read(tp, 0xe8de);
6978         data |= (1 << 15);
6979         r8168_mac_ocp_write(tp, 0xe8de, data);
6980
6981         rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42);
6982 }
6983
6984 static void rtl_hw_initialize(struct rtl8169_private *tp)
6985 {
6986         switch (tp->mac_version) {
6987         case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_51:
6988                 rtl8168ep_stop_cmac(tp);
6989                 /* fall through */
6990         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
6991                 rtl_hw_init_8168g(tp);
6992                 break;
6993         default:
6994                 break;
6995         }
6996 }
6997
6998 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */
6999 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
7000 {
7001         switch (tp->mac_version) {
7002         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
7003         case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
7004                 return false;
7005         default:
7006                 return true;
7007         }
7008 }
7009
7010 static int rtl_jumbo_max(struct rtl8169_private *tp)
7011 {
7012         /* Non-GBit versions don't support jumbo frames */
7013         if (!tp->supports_gmii)
7014                 return JUMBO_1K;
7015
7016         switch (tp->mac_version) {
7017         /* RTL8169 */
7018         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
7019                 return JUMBO_7K;
7020         /* RTL8168b */
7021         case RTL_GIGA_MAC_VER_11:
7022         case RTL_GIGA_MAC_VER_12:
7023         case RTL_GIGA_MAC_VER_17:
7024                 return JUMBO_4K;
7025         /* RTL8168c */
7026         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
7027                 return JUMBO_6K;
7028         default:
7029                 return JUMBO_9K;
7030         }
7031 }
7032
7033 static void rtl_disable_clk(void *data)
7034 {
7035         clk_disable_unprepare(data);
7036 }
7037
7038 static int rtl_get_ether_clk(struct rtl8169_private *tp)
7039 {
7040         struct device *d = tp_to_dev(tp);
7041         struct clk *clk;
7042         int rc;
7043
7044         clk = devm_clk_get(d, "ether_clk");
7045         if (IS_ERR(clk)) {
7046                 rc = PTR_ERR(clk);
7047                 if (rc == -ENOENT)
7048                         /* clk-core allows NULL (for suspend / resume) */
7049                         rc = 0;
7050                 else if (rc != -EPROBE_DEFER)
7051                         dev_err(d, "failed to get clk: %d\n", rc);
7052         } else {
7053                 tp->clk = clk;
7054                 rc = clk_prepare_enable(clk);
7055                 if (rc)
7056                         dev_err(d, "failed to enable clk: %d\n", rc);
7057                 else
7058                         rc = devm_add_action_or_reset(d, rtl_disable_clk, clk);
7059         }
7060
7061         return rc;
7062 }
7063
7064 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7065 {
7066         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
7067         /* align to u16 for is_valid_ether_addr() */
7068         u8 mac_addr[ETH_ALEN] __aligned(2) = {};
7069         struct rtl8169_private *tp;
7070         struct net_device *dev;
7071         int chipset, region, i;
7072         int jumbo_max, rc;
7073
7074         dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
7075         if (!dev)
7076                 return -ENOMEM;
7077
7078         SET_NETDEV_DEV(dev, &pdev->dev);
7079         dev->netdev_ops = &rtl_netdev_ops;
7080         tp = netdev_priv(dev);
7081         tp->dev = dev;
7082         tp->pci_dev = pdev;
7083         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
7084         tp->supports_gmii = cfg->has_gmii;
7085
7086         /* Get the *optional* external "ether_clk" used on some boards */
7087         rc = rtl_get_ether_clk(tp);
7088         if (rc)
7089                 return rc;
7090
7091         /* Disable ASPM completely as that cause random device stop working
7092          * problems as well as full system hangs for some PCIe devices users.
7093          */
7094         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);
7095
7096         /* enable device (incl. PCI PM wakeup and hotplug setup) */
7097         rc = pcim_enable_device(pdev);
7098         if (rc < 0) {
7099                 dev_err(&pdev->dev, "enable failure\n");
7100                 return rc;
7101         }
7102
7103         if (pcim_set_mwi(pdev) < 0)
7104                 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
7105
7106         /* use first MMIO region */
7107         region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
7108         if (region < 0) {
7109                 dev_err(&pdev->dev, "no MMIO resource found\n");
7110                 return -ENODEV;
7111         }
7112
7113         /* check for weird/broken PCI region reporting */
7114         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
7115                 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
7116                 return -ENODEV;
7117         }
7118
7119         rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME);
7120         if (rc < 0) {
7121                 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
7122                 return rc;
7123         }
7124
7125         tp->mmio_addr = pcim_iomap_table(pdev)[region];
7126
7127         /* Identify chip attached to board */
7128         rtl8169_get_mac_version(tp);
7129         if (tp->mac_version == RTL_GIGA_MAC_NONE)
7130                 return -ENODEV;
7131
7132         tp->cp_cmd = RTL_R16(tp, CPlusCmd);
7133
7134         if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 &&
7135             !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
7136                 dev->features |= NETIF_F_HIGHDMA;
7137         } else {
7138                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
7139                 if (rc < 0) {
7140                         dev_err(&pdev->dev, "DMA configuration failed\n");
7141                         return rc;
7142                 }
7143         }
7144
7145         rtl_init_rxcfg(tp);
7146
7147         rtl8169_irq_mask_and_ack(tp);
7148
7149         rtl_hw_initialize(tp);
7150
7151         rtl_hw_reset(tp);
7152
7153         pci_set_master(pdev);
7154
7155         rtl_init_mdio_ops(tp);
7156         rtl_init_jumbo_ops(tp);
7157
7158         chipset = tp->mac_version;
7159
7160         rc = rtl_alloc_irq(tp);
7161         if (rc < 0) {
7162                 dev_err(&pdev->dev, "Can't allocate interrupt\n");
7163                 return rc;
7164         }
7165
7166         mutex_init(&tp->wk.mutex);
7167         INIT_WORK(&tp->wk.work, rtl_task);
7168         u64_stats_init(&tp->rx_stats.syncp);
7169         u64_stats_init(&tp->tx_stats.syncp);
7170
7171         /* get MAC address */
7172         rc = eth_platform_get_mac_address(&pdev->dev, mac_addr);
7173         if (rc)
7174                 rtl_read_mac_address(tp, mac_addr);
7175
7176         if (is_valid_ether_addr(mac_addr))
7177                 rtl_rar_set(tp, mac_addr);
7178
7179         for (i = 0; i < ETH_ALEN; i++)
7180                 dev->dev_addr[i] = RTL_R8(tp, MAC0 + i);
7181
7182         dev->ethtool_ops = &rtl8169_ethtool_ops;
7183
7184         netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT);
7185
7186         /* don't enable SG, IP_CSUM and TSO by default - it might not work
7187          * properly for all devices */
7188         dev->features |= NETIF_F_RXCSUM |
7189                 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
7190
7191         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7192                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
7193                 NETIF_F_HW_VLAN_CTAG_RX;
7194         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7195                 NETIF_F_HIGHDMA;
7196         dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
7197
7198         tp->cp_cmd |= RxChkSum | RxVlan;
7199
7200         /*
7201          * Pretend we are using VLANs; This bypasses a nasty bug where
7202          * Interrupts stop flowing on high load on 8110SCd controllers.
7203          */
7204         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
7205                 /* Disallow toggling */
7206                 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
7207
7208         if (rtl_chip_supports_csum_v2(tp)) {
7209                 tp->tso_csum = rtl8169_tso_csum_v2;
7210                 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
7211         } else {
7212                 tp->tso_csum = rtl8169_tso_csum_v1;
7213         }
7214
7215         dev->hw_features |= NETIF_F_RXALL;
7216         dev->hw_features |= NETIF_F_RXFCS;
7217
7218         /* MTU range: 60 - hw-specific max */
7219         dev->min_mtu = ETH_ZLEN;
7220         jumbo_max = rtl_jumbo_max(tp);
7221         dev->max_mtu = jumbo_max;
7222
7223         tp->hw_start = cfg->hw_start;
7224         tp->irq_mask = RTL_EVENT_NAPI | cfg->irq_mask;
7225         tp->coalesce_info = cfg->coalesce_info;
7226
7227         tp->fw_name = rtl_chip_infos[chipset].fw_name;
7228
7229         tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
7230                                             &tp->counters_phys_addr,
7231                                             GFP_KERNEL);
7232         if (!tp->counters)
7233                 return -ENOMEM;
7234
7235         pci_set_drvdata(pdev, dev);
7236
7237         rc = r8169_mdio_register(tp);
7238         if (rc)
7239                 return rc;
7240
7241         /* chip gets powered up in rtl_open() */
7242         rtl_pll_power_down(tp);
7243
7244         rc = register_netdev(dev);
7245         if (rc)
7246                 goto err_mdio_unregister;
7247
7248         netif_info(tp, probe, dev, "%s, %pM, XID %03x, IRQ %d\n",
7249                    rtl_chip_infos[chipset].name, dev->dev_addr,
7250                    (RTL_R32(tp, TxConfig) >> 20) & 0xfcf,
7251                    pci_irq_vector(pdev, 0));
7252
7253         if (jumbo_max > JUMBO_1K)
7254                 netif_info(tp, probe, dev,
7255                            "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
7256                            jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?
7257                            "ok" : "ko");
7258
7259         if (r8168_check_dash(tp))
7260                 rtl8168_driver_start(tp);
7261
7262         if (pci_dev_run_wake(pdev))
7263                 pm_runtime_put_sync(&pdev->dev);
7264
7265         return 0;
7266
7267 err_mdio_unregister:
7268         mdiobus_unregister(tp->phydev->mdio.bus);
7269         return rc;
7270 }
7271
7272 static struct pci_driver rtl8169_pci_driver = {
7273         .name           = MODULENAME,
7274         .id_table       = rtl8169_pci_tbl,
7275         .probe          = rtl_init_one,
7276         .remove         = rtl_remove_one,
7277         .shutdown       = rtl_shutdown,
7278         .driver.pm      = RTL8169_PM_OPS,
7279 };
7280
7281 module_pci_driver(rtl8169_pci_driver);