2 * QLogic qlcnic NIC Driver
3 * Copyright (c) 2009-2013 QLogic Corporation
5 * See LICENSE.qlcnic for copyright and licensing details.
8 #include <linux/if_vlan.h>
9 #include <linux/ipv6.h>
10 #include <linux/ethtool.h>
11 #include <linux/interrupt.h>
12 #include <linux/aer.h>
15 #include "qlcnic_sriov.h"
17 static void __qlcnic_83xx_process_aen(struct qlcnic_adapter *);
18 static int qlcnic_83xx_clear_lb_mode(struct qlcnic_adapter *, u8);
19 static void qlcnic_83xx_configure_mac(struct qlcnic_adapter *, u8 *, u8,
20 struct qlcnic_cmd_args *);
21 static int qlcnic_83xx_get_port_config(struct qlcnic_adapter *);
22 static irqreturn_t qlcnic_83xx_handle_aen(int, void *);
23 static pci_ers_result_t qlcnic_83xx_io_error_detected(struct pci_dev *,
25 static int qlcnic_83xx_set_port_config(struct qlcnic_adapter *);
26 static pci_ers_result_t qlcnic_83xx_io_slot_reset(struct pci_dev *);
27 static void qlcnic_83xx_io_resume(struct pci_dev *);
28 static int qlcnic_83xx_set_lb_mode(struct qlcnic_adapter *, u8);
29 static void qlcnic_83xx_set_mac_filter_count(struct qlcnic_adapter *);
30 static int qlcnic_83xx_resume(struct qlcnic_adapter *);
31 static int qlcnic_83xx_shutdown(struct pci_dev *);
32 static void qlcnic_83xx_get_beacon_state(struct qlcnic_adapter *);
34 #define RSS_HASHTYPE_IP_TCP 0x3
35 #define QLC_83XX_FW_MBX_CMD 0
36 #define QLC_SKIP_INACTIVE_PCI_REGS 7
37 #define QLC_MAX_LEGACY_FUNC_SUPP 8
39 /* 83xx Module type */
40 #define QLC_83XX_MODULE_FIBRE_10GBASE_LRM 0x1 /* 10GBase-LRM */
41 #define QLC_83XX_MODULE_FIBRE_10GBASE_LR 0x2 /* 10GBase-LR */
42 #define QLC_83XX_MODULE_FIBRE_10GBASE_SR 0x3 /* 10GBase-SR */
43 #define QLC_83XX_MODULE_DA_10GE_PASSIVE_CP 0x4 /* 10GE passive
46 #define QLC_83XX_MODULE_DA_10GE_ACTIVE_CP 0x5 /* 10GE active limiting
49 #define QLC_83XX_MODULE_DA_10GE_LEGACY_CP 0x6 /* 10GE passive copper
50 * (legacy, best effort)
52 #define QLC_83XX_MODULE_FIBRE_1000BASE_SX 0x7 /* 1000Base-SX */
53 #define QLC_83XX_MODULE_FIBRE_1000BASE_LX 0x8 /* 1000Base-LX */
54 #define QLC_83XX_MODULE_FIBRE_1000BASE_CX 0x9 /* 1000Base-CX */
55 #define QLC_83XX_MODULE_TP_1000BASE_T 0xa /* 1000Base-T*/
56 #define QLC_83XX_MODULE_DA_1GE_PASSIVE_CP 0xb /* 1GE passive copper
57 * (legacy, best effort)
59 #define QLC_83XX_MODULE_UNKNOWN 0xf /* Unknown module type */
62 #define QLC_83XX_10_CAPABLE BIT_8
63 #define QLC_83XX_100_CAPABLE BIT_9
64 #define QLC_83XX_1G_CAPABLE BIT_10
65 #define QLC_83XX_10G_CAPABLE BIT_11
66 #define QLC_83XX_AUTONEG_ENABLE BIT_15
68 static const struct qlcnic_mailbox_metadata qlcnic_83xx_mbx_tbl[] = {
69 {QLCNIC_CMD_CONFIGURE_IP_ADDR, 6, 1},
70 {QLCNIC_CMD_CONFIG_INTRPT, 18, 34},
71 {QLCNIC_CMD_CREATE_RX_CTX, 136, 27},
72 {QLCNIC_CMD_DESTROY_RX_CTX, 2, 1},
73 {QLCNIC_CMD_CREATE_TX_CTX, 54, 18},
74 {QLCNIC_CMD_DESTROY_TX_CTX, 2, 1},
75 {QLCNIC_CMD_CONFIGURE_MAC_LEARNING, 2, 1},
76 {QLCNIC_CMD_INTRPT_TEST, 22, 12},
77 {QLCNIC_CMD_SET_MTU, 3, 1},
78 {QLCNIC_CMD_READ_PHY, 4, 2},
79 {QLCNIC_CMD_WRITE_PHY, 5, 1},
80 {QLCNIC_CMD_READ_HW_REG, 4, 1},
81 {QLCNIC_CMD_GET_FLOW_CTL, 4, 2},
82 {QLCNIC_CMD_SET_FLOW_CTL, 4, 1},
83 {QLCNIC_CMD_READ_MAX_MTU, 4, 2},
84 {QLCNIC_CMD_READ_MAX_LRO, 4, 2},
85 {QLCNIC_CMD_MAC_ADDRESS, 4, 3},
86 {QLCNIC_CMD_GET_PCI_INFO, 1, 129},
87 {QLCNIC_CMD_GET_NIC_INFO, 2, 19},
88 {QLCNIC_CMD_SET_NIC_INFO, 32, 1},
89 {QLCNIC_CMD_GET_ESWITCH_CAPABILITY, 4, 3},
90 {QLCNIC_CMD_TOGGLE_ESWITCH, 4, 1},
91 {QLCNIC_CMD_GET_ESWITCH_STATUS, 4, 3},
92 {QLCNIC_CMD_SET_PORTMIRRORING, 4, 1},
93 {QLCNIC_CMD_CONFIGURE_ESWITCH, 4, 1},
94 {QLCNIC_CMD_GET_ESWITCH_PORT_CONFIG, 4, 3},
95 {QLCNIC_CMD_GET_ESWITCH_STATS, 5, 1},
96 {QLCNIC_CMD_CONFIG_PORT, 4, 1},
97 {QLCNIC_CMD_TEMP_SIZE, 1, 4},
98 {QLCNIC_CMD_GET_TEMP_HDR, 5, 5},
99 {QLCNIC_CMD_GET_LINK_EVENT, 2, 1},
100 {QLCNIC_CMD_CONFIG_MAC_VLAN, 4, 3},
101 {QLCNIC_CMD_CONFIG_INTR_COAL, 6, 1},
102 {QLCNIC_CMD_CONFIGURE_RSS, 14, 1},
103 {QLCNIC_CMD_CONFIGURE_LED, 2, 1},
104 {QLCNIC_CMD_CONFIGURE_MAC_RX_MODE, 2, 1},
105 {QLCNIC_CMD_CONFIGURE_HW_LRO, 2, 1},
106 {QLCNIC_CMD_GET_STATISTICS, 2, 80},
107 {QLCNIC_CMD_SET_PORT_CONFIG, 2, 1},
108 {QLCNIC_CMD_GET_PORT_CONFIG, 2, 2},
109 {QLCNIC_CMD_GET_LINK_STATUS, 2, 4},
110 {QLCNIC_CMD_IDC_ACK, 5, 1},
111 {QLCNIC_CMD_INIT_NIC_FUNC, 3, 1},
112 {QLCNIC_CMD_STOP_NIC_FUNC, 2, 1},
113 {QLCNIC_CMD_SET_LED_CONFIG, 5, 1},
114 {QLCNIC_CMD_GET_LED_CONFIG, 1, 5},
115 {QLCNIC_CMD_83XX_SET_DRV_VER, 4, 1},
116 {QLCNIC_CMD_ADD_RCV_RINGS, 130, 26},
117 {QLCNIC_CMD_CONFIG_VPORT, 4, 4},
118 {QLCNIC_CMD_BC_EVENT_SETUP, 2, 1},
119 {QLCNIC_CMD_DCB_QUERY_CAP, 1, 2},
120 {QLCNIC_CMD_DCB_QUERY_PARAM, 1, 50},
121 {QLCNIC_CMD_SET_INGRESS_ENCAP, 2, 1},
122 {QLCNIC_CMD_83XX_EXTEND_ISCSI_DUMP_CAP, 4, 1},
125 const u32 qlcnic_83xx_ext_reg_tbl[] = {
126 0x38CC, /* Global Reset */
127 0x38F0, /* Wildcard */
128 0x38FC, /* Informant */
129 0x3038, /* Host MBX ctrl */
130 0x303C, /* FW MBX ctrl */
131 0x355C, /* BOOT LOADER ADDRESS REG */
132 0x3560, /* BOOT LOADER SIZE REG */
133 0x3564, /* FW IMAGE ADDR REG */
134 0x1000, /* MBX intr enable */
135 0x1200, /* Default Intr mask */
136 0x1204, /* Default Interrupt ID */
137 0x3780, /* QLC_83XX_IDC_MAJ_VERSION */
138 0x3784, /* QLC_83XX_IDC_DEV_STATE */
139 0x3788, /* QLC_83XX_IDC_DRV_PRESENCE */
140 0x378C, /* QLC_83XX_IDC_DRV_ACK */
141 0x3790, /* QLC_83XX_IDC_CTRL */
142 0x3794, /* QLC_83XX_IDC_DRV_AUDIT */
143 0x3798, /* QLC_83XX_IDC_MIN_VERSION */
144 0x379C, /* QLC_83XX_RECOVER_DRV_LOCK */
145 0x37A0, /* QLC_83XX_IDC_PF_0 */
146 0x37A4, /* QLC_83XX_IDC_PF_1 */
147 0x37A8, /* QLC_83XX_IDC_PF_2 */
148 0x37AC, /* QLC_83XX_IDC_PF_3 */
149 0x37B0, /* QLC_83XX_IDC_PF_4 */
150 0x37B4, /* QLC_83XX_IDC_PF_5 */
151 0x37B8, /* QLC_83XX_IDC_PF_6 */
152 0x37BC, /* QLC_83XX_IDC_PF_7 */
153 0x37C0, /* QLC_83XX_IDC_PF_8 */
154 0x37C4, /* QLC_83XX_IDC_PF_9 */
155 0x37C8, /* QLC_83XX_IDC_PF_10 */
156 0x37CC, /* QLC_83XX_IDC_PF_11 */
157 0x37D0, /* QLC_83XX_IDC_PF_12 */
158 0x37D4, /* QLC_83XX_IDC_PF_13 */
159 0x37D8, /* QLC_83XX_IDC_PF_14 */
160 0x37DC, /* QLC_83XX_IDC_PF_15 */
161 0x37E0, /* QLC_83XX_IDC_DEV_PARTITION_INFO_1 */
162 0x37E4, /* QLC_83XX_IDC_DEV_PARTITION_INFO_2 */
163 0x37F0, /* QLC_83XX_DRV_OP_MODE */
164 0x37F4, /* QLC_83XX_VNIC_STATE */
165 0x3868, /* QLC_83XX_DRV_LOCK */
166 0x386C, /* QLC_83XX_DRV_UNLOCK */
167 0x3504, /* QLC_83XX_DRV_LOCK_ID */
168 0x34A4, /* QLC_83XX_ASIC_TEMP */
171 const u32 qlcnic_83xx_reg_tbl[] = {
172 0x34A8, /* PEG_HALT_STAT1 */
173 0x34AC, /* PEG_HALT_STAT2 */
174 0x34B0, /* FW_HEARTBEAT */
175 0x3500, /* FLASH LOCK_ID */
176 0x3528, /* FW_CAPABILITIES */
177 0x3538, /* Driver active, DRV_REG0 */
178 0x3540, /* Device state, DRV_REG1 */
179 0x3544, /* Driver state, DRV_REG2 */
180 0x3548, /* Driver scratch, DRV_REG3 */
181 0x354C, /* Device partiton info, DRV_REG4 */
182 0x3524, /* Driver IDC ver, DRV_REG5 */
183 0x3550, /* FW_VER_MAJOR */
184 0x3554, /* FW_VER_MINOR */
185 0x3558, /* FW_VER_SUB */
186 0x359C, /* NPAR STATE */
187 0x35FC, /* FW_IMG_VALID */
188 0x3650, /* CMD_PEG_STATE */
189 0x373C, /* RCV_PEG_STATE */
190 0x37B4, /* ASIC TEMP */
192 0x3570, /* DRV OP MODE */
193 0x3850, /* FLASH LOCK */
194 0x3854, /* FLASH UNLOCK */
197 static struct qlcnic_hardware_ops qlcnic_83xx_hw_ops = {
198 .read_crb = qlcnic_83xx_read_crb,
199 .write_crb = qlcnic_83xx_write_crb,
200 .read_reg = qlcnic_83xx_rd_reg_indirect,
201 .write_reg = qlcnic_83xx_wrt_reg_indirect,
202 .get_mac_address = qlcnic_83xx_get_mac_address,
203 .setup_intr = qlcnic_83xx_setup_intr,
204 .alloc_mbx_args = qlcnic_83xx_alloc_mbx_args,
205 .mbx_cmd = qlcnic_83xx_issue_cmd,
206 .get_func_no = qlcnic_83xx_get_func_no,
207 .api_lock = qlcnic_83xx_cam_lock,
208 .api_unlock = qlcnic_83xx_cam_unlock,
209 .add_sysfs = qlcnic_83xx_add_sysfs,
210 .remove_sysfs = qlcnic_83xx_remove_sysfs,
211 .process_lb_rcv_ring_diag = qlcnic_83xx_process_rcv_ring_diag,
212 .create_rx_ctx = qlcnic_83xx_create_rx_ctx,
213 .create_tx_ctx = qlcnic_83xx_create_tx_ctx,
214 .del_rx_ctx = qlcnic_83xx_del_rx_ctx,
215 .del_tx_ctx = qlcnic_83xx_del_tx_ctx,
216 .setup_link_event = qlcnic_83xx_setup_link_event,
217 .get_nic_info = qlcnic_83xx_get_nic_info,
218 .get_pci_info = qlcnic_83xx_get_pci_info,
219 .set_nic_info = qlcnic_83xx_set_nic_info,
220 .change_macvlan = qlcnic_83xx_sre_macaddr_change,
221 .napi_enable = qlcnic_83xx_napi_enable,
222 .napi_disable = qlcnic_83xx_napi_disable,
223 .config_intr_coal = qlcnic_83xx_config_intr_coal,
224 .config_rss = qlcnic_83xx_config_rss,
225 .config_hw_lro = qlcnic_83xx_config_hw_lro,
226 .config_promisc_mode = qlcnic_83xx_nic_set_promisc,
227 .change_l2_filter = qlcnic_83xx_change_l2_filter,
228 .get_board_info = qlcnic_83xx_get_port_info,
229 .set_mac_filter_count = qlcnic_83xx_set_mac_filter_count,
230 .free_mac_list = qlcnic_82xx_free_mac_list,
231 .io_error_detected = qlcnic_83xx_io_error_detected,
232 .io_slot_reset = qlcnic_83xx_io_slot_reset,
233 .io_resume = qlcnic_83xx_io_resume,
234 .get_beacon_state = qlcnic_83xx_get_beacon_state,
235 .enable_sds_intr = qlcnic_83xx_enable_sds_intr,
236 .disable_sds_intr = qlcnic_83xx_disable_sds_intr,
237 .enable_tx_intr = qlcnic_83xx_enable_tx_intr,
238 .disable_tx_intr = qlcnic_83xx_disable_tx_intr,
239 .get_saved_state = qlcnic_83xx_get_saved_state,
240 .set_saved_state = qlcnic_83xx_set_saved_state,
241 .cache_tmpl_hdr_values = qlcnic_83xx_cache_tmpl_hdr_values,
242 .get_cap_size = qlcnic_83xx_get_cap_size,
243 .set_sys_info = qlcnic_83xx_set_sys_info,
244 .store_cap_mask = qlcnic_83xx_store_cap_mask,
247 static struct qlcnic_nic_template qlcnic_83xx_ops = {
248 .config_bridged_mode = qlcnic_config_bridged_mode,
249 .config_led = qlcnic_config_led,
250 .request_reset = qlcnic_83xx_idc_request_reset,
251 .cancel_idc_work = qlcnic_83xx_idc_exit,
252 .napi_add = qlcnic_83xx_napi_add,
253 .napi_del = qlcnic_83xx_napi_del,
254 .config_ipaddr = qlcnic_83xx_config_ipaddr,
255 .clear_legacy_intr = qlcnic_83xx_clear_legacy_intr,
256 .shutdown = qlcnic_83xx_shutdown,
257 .resume = qlcnic_83xx_resume,
260 void qlcnic_83xx_register_map(struct qlcnic_hardware_context *ahw)
262 ahw->hw_ops = &qlcnic_83xx_hw_ops;
263 ahw->reg_tbl = (u32 *)qlcnic_83xx_reg_tbl;
264 ahw->ext_reg_tbl = (u32 *)qlcnic_83xx_ext_reg_tbl;
267 int qlcnic_83xx_get_fw_version(struct qlcnic_adapter *adapter)
269 u32 fw_major, fw_minor, fw_build;
270 struct pci_dev *pdev = adapter->pdev;
272 fw_major = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MAJOR);
273 fw_minor = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MINOR);
274 fw_build = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_SUB);
275 adapter->fw_version = QLCNIC_VERSION_CODE(fw_major, fw_minor, fw_build);
277 dev_info(&pdev->dev, "Driver v%s, firmware version %d.%d.%d\n",
278 QLCNIC_LINUX_VERSIONID, fw_major, fw_minor, fw_build);
280 return adapter->fw_version;
283 static int __qlcnic_set_win_base(struct qlcnic_adapter *adapter, u32 addr)
288 base = adapter->ahw->pci_base0 +
289 QLC_83XX_CRB_WIN_FUNC(adapter->ahw->pci_func);
298 int qlcnic_83xx_rd_reg_indirect(struct qlcnic_adapter *adapter, ulong addr,
301 struct qlcnic_hardware_context *ahw = adapter->ahw;
303 *err = __qlcnic_set_win_base(adapter, (u32) addr);
305 return QLCRDX(ahw, QLCNIC_WILDCARD);
307 dev_err(&adapter->pdev->dev,
308 "%s failed, addr = 0x%lx\n", __func__, addr);
313 int qlcnic_83xx_wrt_reg_indirect(struct qlcnic_adapter *adapter, ulong addr,
317 struct qlcnic_hardware_context *ahw = adapter->ahw;
319 err = __qlcnic_set_win_base(adapter, (u32) addr);
321 QLCWRX(ahw, QLCNIC_WILDCARD, data);
324 dev_err(&adapter->pdev->dev,
325 "%s failed, addr = 0x%x data = 0x%x\n",
326 __func__, (int)addr, data);
331 static void qlcnic_83xx_enable_legacy(struct qlcnic_adapter *adapter)
333 struct qlcnic_hardware_context *ahw = adapter->ahw;
335 /* MSI-X enablement failed, use legacy interrupt */
336 adapter->tgt_status_reg = ahw->pci_base0 + QLC_83XX_INTX_PTR;
337 adapter->tgt_mask_reg = ahw->pci_base0 + QLC_83XX_INTX_MASK;
338 adapter->isr_int_vec = ahw->pci_base0 + QLC_83XX_INTX_TRGR;
339 adapter->msix_entries[0].vector = adapter->pdev->irq;
340 dev_info(&adapter->pdev->dev, "using legacy interrupt\n");
343 static int qlcnic_83xx_calculate_msix_vector(struct qlcnic_adapter *adapter)
347 num_msix = adapter->drv_sds_rings;
349 /* account for AEN interrupt MSI-X based interrupts */
352 if (!(adapter->flags & QLCNIC_TX_INTR_SHARED))
353 num_msix += adapter->drv_tx_rings;
358 int qlcnic_83xx_setup_intr(struct qlcnic_adapter *adapter)
360 struct qlcnic_hardware_context *ahw = adapter->ahw;
361 int err, i, num_msix;
363 if (adapter->flags & QLCNIC_TSS_RSS) {
364 err = qlcnic_setup_tss_rss_intr(adapter);
367 num_msix = ahw->num_msix;
369 num_msix = qlcnic_83xx_calculate_msix_vector(adapter);
371 err = qlcnic_enable_msix(adapter, num_msix);
375 if (adapter->flags & QLCNIC_MSIX_ENABLED) {
376 num_msix = ahw->num_msix;
378 if (qlcnic_sriov_vf_check(adapter))
381 adapter->drv_sds_rings = QLCNIC_SINGLE_RING;
382 adapter->drv_tx_rings = QLCNIC_SINGLE_RING;
386 /* setup interrupt mapping table for fw */
387 ahw->intr_tbl = vzalloc(num_msix *
388 sizeof(struct qlcnic_intrpt_config));
392 if (!(adapter->flags & QLCNIC_MSIX_ENABLED)) {
393 if (adapter->ahw->pci_func >= QLC_MAX_LEGACY_FUNC_SUPP) {
394 dev_err(&adapter->pdev->dev, "PCI function number 8 and higher are not supported with legacy interrupt, func 0x%x\n",
399 qlcnic_83xx_enable_legacy(adapter);
402 for (i = 0; i < num_msix; i++) {
403 if (adapter->flags & QLCNIC_MSIX_ENABLED)
404 ahw->intr_tbl[i].type = QLCNIC_INTRPT_MSIX;
406 ahw->intr_tbl[i].type = QLCNIC_INTRPT_INTX;
407 ahw->intr_tbl[i].id = i;
408 ahw->intr_tbl[i].src = 0;
414 static inline void qlcnic_83xx_clear_legacy_intr_mask(struct qlcnic_adapter *adapter)
416 writel(0, adapter->tgt_mask_reg);
419 static inline void qlcnic_83xx_set_legacy_intr_mask(struct qlcnic_adapter *adapter)
421 if (adapter->tgt_mask_reg)
422 writel(1, adapter->tgt_mask_reg);
425 static inline void qlcnic_83xx_enable_legacy_msix_mbx_intr(struct qlcnic_adapter
430 /* Mailbox in MSI-x mode and Legacy Interrupt share the same
431 * source register. We could be here before contexts are created
432 * and sds_ring->crb_intr_mask has not been initialized, calculate
433 * BAR offset for Interrupt Source Register
435 mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
436 writel(0, adapter->ahw->pci_base0 + mask);
439 void qlcnic_83xx_disable_mbx_intr(struct qlcnic_adapter *adapter)
443 mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
444 writel(1, adapter->ahw->pci_base0 + mask);
445 QLCWRX(adapter->ahw, QLCNIC_MBX_INTR_ENBL, 0);
448 static inline void qlcnic_83xx_get_mbx_data(struct qlcnic_adapter *adapter,
449 struct qlcnic_cmd_args *cmd)
453 if (cmd->op_type == QLC_83XX_MBX_POST_BC_OP)
456 for (i = 0; i < cmd->rsp.num; i++)
457 cmd->rsp.arg[i] = readl(QLCNIC_MBX_FW(adapter->ahw, i));
460 irqreturn_t qlcnic_83xx_clear_legacy_intr(struct qlcnic_adapter *adapter)
463 struct qlcnic_hardware_context *ahw = adapter->ahw;
466 intr_val = readl(adapter->tgt_status_reg);
468 if (!QLC_83XX_VALID_INTX_BIT31(intr_val))
471 if (QLC_83XX_INTX_FUNC(intr_val) != adapter->ahw->pci_func) {
472 adapter->stats.spurious_intr++;
475 /* The barrier is required to ensure writes to the registers */
478 /* clear the interrupt trigger control register */
479 writel(0, adapter->isr_int_vec);
480 intr_val = readl(adapter->isr_int_vec);
482 intr_val = readl(adapter->tgt_status_reg);
483 if (QLC_83XX_INTX_FUNC(intr_val) != ahw->pci_func)
486 } while (QLC_83XX_VALID_INTX_BIT30(intr_val) &&
487 (retries < QLC_83XX_LEGACY_INTX_MAX_RETRY));
492 static inline void qlcnic_83xx_notify_mbx_response(struct qlcnic_mailbox *mbx)
494 atomic_set(&mbx->rsp_status, QLC_83XX_MBX_RESPONSE_ARRIVED);
495 complete(&mbx->completion);
498 static void qlcnic_83xx_poll_process_aen(struct qlcnic_adapter *adapter)
500 u32 resp, event, rsp_status = QLC_83XX_MBX_RESPONSE_ARRIVED;
501 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
504 spin_lock_irqsave(&mbx->aen_lock, flags);
505 resp = QLCRDX(adapter->ahw, QLCNIC_FW_MBX_CTRL);
506 if (!(resp & QLCNIC_SET_OWNER))
509 event = readl(QLCNIC_MBX_FW(adapter->ahw, 0));
510 if (event & QLCNIC_MBX_ASYNC_EVENT) {
511 __qlcnic_83xx_process_aen(adapter);
513 if (atomic_read(&mbx->rsp_status) != rsp_status)
514 qlcnic_83xx_notify_mbx_response(mbx);
517 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
518 spin_unlock_irqrestore(&mbx->aen_lock, flags);
521 irqreturn_t qlcnic_83xx_intr(int irq, void *data)
523 struct qlcnic_adapter *adapter = data;
524 struct qlcnic_host_sds_ring *sds_ring;
525 struct qlcnic_hardware_context *ahw = adapter->ahw;
527 if (qlcnic_83xx_clear_legacy_intr(adapter) == IRQ_NONE)
530 qlcnic_83xx_poll_process_aen(adapter);
532 if (ahw->diag_test) {
533 if (ahw->diag_test == QLCNIC_INTERRUPT_TEST)
535 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
539 if (!test_bit(__QLCNIC_DEV_UP, &adapter->state)) {
540 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
542 sds_ring = &adapter->recv_ctx->sds_rings[0];
543 napi_schedule(&sds_ring->napi);
549 irqreturn_t qlcnic_83xx_tmp_intr(int irq, void *data)
551 struct qlcnic_host_sds_ring *sds_ring = data;
552 struct qlcnic_adapter *adapter = sds_ring->adapter;
554 if (adapter->flags & QLCNIC_MSIX_ENABLED)
557 if (adapter->nic_ops->clear_legacy_intr(adapter) == IRQ_NONE)
561 adapter->ahw->diag_cnt++;
562 qlcnic_enable_sds_intr(adapter, sds_ring);
567 void qlcnic_83xx_free_mbx_intr(struct qlcnic_adapter *adapter)
571 if (!(adapter->flags & QLCNIC_MSIX_ENABLED))
572 qlcnic_83xx_set_legacy_intr_mask(adapter);
574 qlcnic_83xx_disable_mbx_intr(adapter);
576 if (adapter->flags & QLCNIC_MSIX_ENABLED)
577 num_msix = adapter->ahw->num_msix - 1;
583 if (adapter->msix_entries) {
584 synchronize_irq(adapter->msix_entries[num_msix].vector);
585 free_irq(adapter->msix_entries[num_msix].vector, adapter);
589 int qlcnic_83xx_setup_mbx_intr(struct qlcnic_adapter *adapter)
591 irq_handler_t handler;
594 unsigned long flags = 0;
596 if (!(adapter->flags & QLCNIC_MSI_ENABLED) &&
597 !(adapter->flags & QLCNIC_MSIX_ENABLED))
598 flags |= IRQF_SHARED;
600 if (adapter->flags & QLCNIC_MSIX_ENABLED) {
601 handler = qlcnic_83xx_handle_aen;
602 val = adapter->msix_entries[adapter->ahw->num_msix - 1].vector;
603 err = request_irq(val, handler, flags, "qlcnic-MB", adapter);
605 dev_err(&adapter->pdev->dev,
606 "failed to register MBX interrupt\n");
610 handler = qlcnic_83xx_intr;
611 val = adapter->msix_entries[0].vector;
612 err = request_irq(val, handler, flags, "qlcnic", adapter);
614 dev_err(&adapter->pdev->dev,
615 "failed to register INTx interrupt\n");
618 qlcnic_83xx_clear_legacy_intr_mask(adapter);
621 /* Enable mailbox interrupt */
622 qlcnic_83xx_enable_mbx_interrupt(adapter);
627 void qlcnic_83xx_get_func_no(struct qlcnic_adapter *adapter)
629 u32 val = QLCRDX(adapter->ahw, QLCNIC_INFORMANT);
630 adapter->ahw->pci_func = (val >> 24) & 0xff;
633 int qlcnic_83xx_cam_lock(struct qlcnic_adapter *adapter)
638 struct qlcnic_hardware_context *ahw = adapter->ahw;
640 addr = ahw->pci_base0 + QLC_83XX_SEM_LOCK_FUNC(ahw->pci_func);
644 /* write the function number to register */
645 QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER,
649 usleep_range(1000, 2000);
650 } while (++limit <= QLCNIC_PCIE_SEM_TIMEOUT);
655 void qlcnic_83xx_cam_unlock(struct qlcnic_adapter *adapter)
659 struct qlcnic_hardware_context *ahw = adapter->ahw;
661 addr = ahw->pci_base0 + QLC_83XX_SEM_UNLOCK_FUNC(ahw->pci_func);
665 void qlcnic_83xx_read_crb(struct qlcnic_adapter *adapter, char *buf,
666 loff_t offset, size_t size)
671 if (qlcnic_api_lock(adapter)) {
672 dev_err(&adapter->pdev->dev,
673 "%s: failed to acquire lock. addr offset 0x%x\n",
674 __func__, (u32)offset);
678 data = QLCRD32(adapter, (u32) offset, &ret);
679 qlcnic_api_unlock(adapter);
682 dev_err(&adapter->pdev->dev,
683 "%s: failed. addr offset 0x%x\n",
684 __func__, (u32)offset);
687 memcpy(buf, &data, size);
690 void qlcnic_83xx_write_crb(struct qlcnic_adapter *adapter, char *buf,
691 loff_t offset, size_t size)
695 memcpy(&data, buf, size);
696 qlcnic_83xx_wrt_reg_indirect(adapter, (u32) offset, data);
699 int qlcnic_83xx_get_port_info(struct qlcnic_adapter *adapter)
701 struct qlcnic_hardware_context *ahw = adapter->ahw;
704 status = qlcnic_83xx_get_port_config(adapter);
706 dev_err(&adapter->pdev->dev,
707 "Get Port Info failed\n");
710 if (ahw->port_config & QLC_83XX_10G_CAPABLE) {
711 ahw->port_type = QLCNIC_XGBE;
712 } else if (ahw->port_config & QLC_83XX_10_CAPABLE ||
713 ahw->port_config & QLC_83XX_100_CAPABLE ||
714 ahw->port_config & QLC_83XX_1G_CAPABLE) {
715 ahw->port_type = QLCNIC_GBE;
717 ahw->port_type = QLCNIC_XGBE;
720 if (QLC_83XX_AUTONEG(ahw->port_config))
721 ahw->link_autoneg = AUTONEG_ENABLE;
727 static void qlcnic_83xx_set_mac_filter_count(struct qlcnic_adapter *adapter)
729 struct qlcnic_hardware_context *ahw = adapter->ahw;
730 u16 act_pci_fn = ahw->total_nic_func;
733 ahw->max_mc_count = QLC_83XX_MAX_MC_COUNT;
735 count = (QLC_83XX_MAX_UC_COUNT - QLC_83XX_MAX_MC_COUNT) /
738 count = (QLC_83XX_LB_MAX_FILTERS - QLC_83XX_MAX_MC_COUNT) /
740 ahw->max_uc_count = count;
743 void qlcnic_83xx_enable_mbx_interrupt(struct qlcnic_adapter *adapter)
747 if (adapter->flags & QLCNIC_MSIX_ENABLED)
748 val = BIT_2 | ((adapter->ahw->num_msix - 1) << 8);
752 QLCWRX(adapter->ahw, QLCNIC_MBX_INTR_ENBL, val);
753 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
756 void qlcnic_83xx_check_vf(struct qlcnic_adapter *adapter,
757 const struct pci_device_id *ent)
759 u32 op_mode, priv_level;
760 struct qlcnic_hardware_context *ahw = adapter->ahw;
762 ahw->fw_hal_version = 2;
763 qlcnic_get_func_no(adapter);
765 if (qlcnic_sriov_vf_check(adapter)) {
766 qlcnic_sriov_vf_set_ops(adapter);
770 /* Determine function privilege level */
771 op_mode = QLCRDX(adapter->ahw, QLC_83XX_DRV_OP_MODE);
772 if (op_mode == QLC_83XX_DEFAULT_OPMODE)
773 priv_level = QLCNIC_MGMT_FUNC;
775 priv_level = QLC_83XX_GET_FUNC_PRIVILEGE(op_mode,
778 if (priv_level == QLCNIC_NON_PRIV_FUNC) {
779 ahw->op_mode = QLCNIC_NON_PRIV_FUNC;
780 dev_info(&adapter->pdev->dev,
781 "HAL Version: %d Non Privileged function\n",
782 ahw->fw_hal_version);
783 adapter->nic_ops = &qlcnic_vf_ops;
785 if (pci_find_ext_capability(adapter->pdev,
786 PCI_EXT_CAP_ID_SRIOV))
787 set_bit(__QLCNIC_SRIOV_CAPABLE, &adapter->state);
788 adapter->nic_ops = &qlcnic_83xx_ops;
792 static void qlcnic_83xx_handle_link_aen(struct qlcnic_adapter *adapter,
794 static void qlcnic_83xx_handle_idc_comp_aen(struct qlcnic_adapter *adapter,
797 void qlcnic_dump_mbx(struct qlcnic_adapter *adapter,
798 struct qlcnic_cmd_args *cmd)
802 if (cmd->op_type == QLC_83XX_MBX_POST_BC_OP)
805 dev_info(&adapter->pdev->dev,
806 "Host MBX regs(%d)\n", cmd->req.num);
807 for (i = 0; i < cmd->req.num; i++) {
810 pr_info("%08x ", cmd->req.arg[i]);
813 dev_info(&adapter->pdev->dev,
814 "FW MBX regs(%d)\n", cmd->rsp.num);
815 for (i = 0; i < cmd->rsp.num; i++) {
818 pr_info("%08x ", cmd->rsp.arg[i]);
823 static void qlcnic_83xx_poll_for_mbx_completion(struct qlcnic_adapter *adapter,
824 struct qlcnic_cmd_args *cmd)
826 struct qlcnic_hardware_context *ahw = adapter->ahw;
827 int opcode = LSW(cmd->req.arg[0]);
828 unsigned long max_loops;
830 max_loops = cmd->total_cmds * QLC_83XX_MBX_CMD_LOOP;
832 for (; max_loops; max_loops--) {
833 if (atomic_read(&cmd->rsp_status) ==
834 QLC_83XX_MBX_RESPONSE_ARRIVED)
840 dev_err(&adapter->pdev->dev,
841 "%s: Mailbox command timed out, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
842 __func__, opcode, cmd->type, ahw->pci_func, ahw->op_mode);
843 flush_workqueue(ahw->mailbox->work_q);
847 int qlcnic_83xx_issue_cmd(struct qlcnic_adapter *adapter,
848 struct qlcnic_cmd_args *cmd)
850 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
851 struct qlcnic_hardware_context *ahw = adapter->ahw;
852 int cmd_type, err, opcode;
853 unsigned long timeout;
858 opcode = LSW(cmd->req.arg[0]);
859 cmd_type = cmd->type;
860 err = mbx->ops->enqueue_cmd(adapter, cmd, &timeout);
862 dev_err(&adapter->pdev->dev,
863 "%s: Mailbox not available, cmd_op=0x%x, cmd_context=0x%x, pci_func=0x%x, op_mode=0x%x\n",
864 __func__, opcode, cmd->type, ahw->pci_func,
870 case QLC_83XX_MBX_CMD_WAIT:
871 if (!wait_for_completion_timeout(&cmd->completion, timeout)) {
872 dev_err(&adapter->pdev->dev,
873 "%s: Mailbox command timed out, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
874 __func__, opcode, cmd_type, ahw->pci_func,
876 flush_workqueue(mbx->work_q);
879 case QLC_83XX_MBX_CMD_NO_WAIT:
881 case QLC_83XX_MBX_CMD_BUSY_WAIT:
882 qlcnic_83xx_poll_for_mbx_completion(adapter, cmd);
885 dev_err(&adapter->pdev->dev,
886 "%s: Invalid mailbox command, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
887 __func__, opcode, cmd_type, ahw->pci_func,
889 qlcnic_83xx_detach_mailbox_work(adapter);
892 return cmd->rsp_opcode;
895 int qlcnic_83xx_alloc_mbx_args(struct qlcnic_cmd_args *mbx,
896 struct qlcnic_adapter *adapter, u32 type)
900 const struct qlcnic_mailbox_metadata *mbx_tbl;
902 memset(mbx, 0, sizeof(struct qlcnic_cmd_args));
903 mbx_tbl = qlcnic_83xx_mbx_tbl;
904 size = ARRAY_SIZE(qlcnic_83xx_mbx_tbl);
905 for (i = 0; i < size; i++) {
906 if (type == mbx_tbl[i].cmd) {
907 mbx->op_type = QLC_83XX_FW_MBX_CMD;
908 mbx->req.num = mbx_tbl[i].in_args;
909 mbx->rsp.num = mbx_tbl[i].out_args;
910 mbx->req.arg = kcalloc(mbx->req.num, sizeof(u32),
914 mbx->rsp.arg = kcalloc(mbx->rsp.num, sizeof(u32),
921 memset(mbx->req.arg, 0, sizeof(u32) * mbx->req.num);
922 memset(mbx->rsp.arg, 0, sizeof(u32) * mbx->rsp.num);
923 temp = adapter->ahw->fw_hal_version << 29;
924 mbx->req.arg[0] = (type | (mbx->req.num << 16) | temp);
930 dev_err(&adapter->pdev->dev, "%s: Invalid mailbox command opcode 0x%x\n",
935 void qlcnic_83xx_idc_aen_work(struct work_struct *work)
937 struct qlcnic_adapter *adapter;
938 struct qlcnic_cmd_args cmd;
941 adapter = container_of(work, struct qlcnic_adapter, idc_aen_work.work);
942 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_IDC_ACK);
946 for (i = 1; i < QLC_83XX_MBX_AEN_CNT; i++)
947 cmd.req.arg[i] = adapter->ahw->mbox_aen[i];
949 err = qlcnic_issue_cmd(adapter, &cmd);
951 dev_info(&adapter->pdev->dev,
952 "%s: Mailbox IDC ACK failed.\n", __func__);
953 qlcnic_free_mbx_args(&cmd);
956 static void qlcnic_83xx_handle_idc_comp_aen(struct qlcnic_adapter *adapter,
959 dev_dbg(&adapter->pdev->dev, "Completion AEN:0x%x.\n",
960 QLCNIC_MBX_RSP(data[0]));
961 clear_bit(QLC_83XX_IDC_COMP_AEN, &adapter->ahw->idc.status);
965 static void __qlcnic_83xx_process_aen(struct qlcnic_adapter *adapter)
967 struct qlcnic_hardware_context *ahw = adapter->ahw;
968 u32 event[QLC_83XX_MBX_AEN_CNT];
971 for (i = 0; i < QLC_83XX_MBX_AEN_CNT; i++)
972 event[i] = readl(QLCNIC_MBX_FW(ahw, i));
974 switch (QLCNIC_MBX_RSP(event[0])) {
976 case QLCNIC_MBX_LINK_EVENT:
977 qlcnic_83xx_handle_link_aen(adapter, event);
979 case QLCNIC_MBX_COMP_EVENT:
980 qlcnic_83xx_handle_idc_comp_aen(adapter, event);
982 case QLCNIC_MBX_REQUEST_EVENT:
983 for (i = 0; i < QLC_83XX_MBX_AEN_CNT; i++)
984 adapter->ahw->mbox_aen[i] = QLCNIC_MBX_RSP(event[i]);
985 queue_delayed_work(adapter->qlcnic_wq,
986 &adapter->idc_aen_work, 0);
988 case QLCNIC_MBX_TIME_EXTEND_EVENT:
989 ahw->extend_lb_time = event[1] >> 8 & 0xf;
991 case QLCNIC_MBX_BC_EVENT:
992 qlcnic_sriov_handle_bc_event(adapter, event[1]);
994 case QLCNIC_MBX_SFP_INSERT_EVENT:
995 dev_info(&adapter->pdev->dev, "SFP+ Insert AEN:0x%x.\n",
996 QLCNIC_MBX_RSP(event[0]));
998 case QLCNIC_MBX_SFP_REMOVE_EVENT:
999 dev_info(&adapter->pdev->dev, "SFP Removed AEN:0x%x.\n",
1000 QLCNIC_MBX_RSP(event[0]));
1002 case QLCNIC_MBX_DCBX_CONFIG_CHANGE_EVENT:
1003 qlcnic_dcb_aen_handler(adapter->dcb, (void *)&event[1]);
1006 dev_dbg(&adapter->pdev->dev, "Unsupported AEN:0x%x.\n",
1007 QLCNIC_MBX_RSP(event[0]));
1011 QLCWRX(ahw, QLCNIC_FW_MBX_CTRL, QLCNIC_CLR_OWNER);
1014 static void qlcnic_83xx_process_aen(struct qlcnic_adapter *adapter)
1016 u32 resp, event, rsp_status = QLC_83XX_MBX_RESPONSE_ARRIVED;
1017 struct qlcnic_hardware_context *ahw = adapter->ahw;
1018 struct qlcnic_mailbox *mbx = ahw->mailbox;
1019 unsigned long flags;
1021 spin_lock_irqsave(&mbx->aen_lock, flags);
1022 resp = QLCRDX(ahw, QLCNIC_FW_MBX_CTRL);
1023 if (resp & QLCNIC_SET_OWNER) {
1024 event = readl(QLCNIC_MBX_FW(ahw, 0));
1025 if (event & QLCNIC_MBX_ASYNC_EVENT) {
1026 __qlcnic_83xx_process_aen(adapter);
1028 if (atomic_read(&mbx->rsp_status) != rsp_status)
1029 qlcnic_83xx_notify_mbx_response(mbx);
1032 spin_unlock_irqrestore(&mbx->aen_lock, flags);
1035 static void qlcnic_83xx_mbx_poll_work(struct work_struct *work)
1037 struct qlcnic_adapter *adapter;
1039 adapter = container_of(work, struct qlcnic_adapter, mbx_poll_work.work);
1041 if (!test_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state))
1044 qlcnic_83xx_process_aen(adapter);
1045 queue_delayed_work(adapter->qlcnic_wq, &adapter->mbx_poll_work,
1049 void qlcnic_83xx_enable_mbx_poll(struct qlcnic_adapter *adapter)
1051 if (test_and_set_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state))
1054 INIT_DELAYED_WORK(&adapter->mbx_poll_work, qlcnic_83xx_mbx_poll_work);
1055 queue_delayed_work(adapter->qlcnic_wq, &adapter->mbx_poll_work, 0);
1058 void qlcnic_83xx_disable_mbx_poll(struct qlcnic_adapter *adapter)
1060 if (!test_and_clear_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state))
1062 cancel_delayed_work_sync(&adapter->mbx_poll_work);
1065 static int qlcnic_83xx_add_rings(struct qlcnic_adapter *adapter)
1067 int index, i, err, sds_mbx_size;
1068 u32 *buf, intrpt_id, intr_mask;
1071 struct qlcnic_cmd_args cmd;
1072 struct qlcnic_host_sds_ring *sds;
1073 struct qlcnic_sds_mbx sds_mbx;
1074 struct qlcnic_add_rings_mbx_out *mbx_out;
1075 struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
1076 struct qlcnic_hardware_context *ahw = adapter->ahw;
1078 sds_mbx_size = sizeof(struct qlcnic_sds_mbx);
1079 context_id = recv_ctx->context_id;
1080 num_sds = adapter->drv_sds_rings - QLCNIC_MAX_SDS_RINGS;
1081 ahw->hw_ops->alloc_mbx_args(&cmd, adapter,
1082 QLCNIC_CMD_ADD_RCV_RINGS);
1083 cmd.req.arg[1] = 0 | (num_sds << 8) | (context_id << 16);
1085 /* set up status rings, mbx 2-81 */
1087 for (i = 8; i < adapter->drv_sds_rings; i++) {
1088 memset(&sds_mbx, 0, sds_mbx_size);
1089 sds = &recv_ctx->sds_rings[i];
1091 memset(sds->desc_head, 0, STATUS_DESC_RINGSIZE(sds));
1092 sds_mbx.phy_addr_low = LSD(sds->phys_addr);
1093 sds_mbx.phy_addr_high = MSD(sds->phys_addr);
1094 sds_mbx.sds_ring_size = sds->num_desc;
1096 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1097 intrpt_id = ahw->intr_tbl[i].id;
1099 intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
1101 if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
1102 sds_mbx.intrpt_id = intrpt_id;
1104 sds_mbx.intrpt_id = 0xffff;
1105 sds_mbx.intrpt_val = 0;
1106 buf = &cmd.req.arg[index];
1107 memcpy(buf, &sds_mbx, sds_mbx_size);
1108 index += sds_mbx_size / sizeof(u32);
1111 /* send the mailbox command */
1112 err = ahw->hw_ops->mbx_cmd(adapter, &cmd);
1114 dev_err(&adapter->pdev->dev,
1115 "Failed to add rings %d\n", err);
1119 mbx_out = (struct qlcnic_add_rings_mbx_out *)&cmd.rsp.arg[1];
1121 /* status descriptor ring */
1122 for (i = 8; i < adapter->drv_sds_rings; i++) {
1123 sds = &recv_ctx->sds_rings[i];
1124 sds->crb_sts_consumer = ahw->pci_base0 +
1125 mbx_out->host_csmr[index];
1126 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1127 intr_mask = ahw->intr_tbl[i].src;
1129 intr_mask = QLCRDX(ahw, QLCNIC_DEF_INT_MASK);
1131 sds->crb_intr_mask = ahw->pci_base0 + intr_mask;
1135 qlcnic_free_mbx_args(&cmd);
1139 void qlcnic_83xx_del_rx_ctx(struct qlcnic_adapter *adapter)
1143 struct qlcnic_cmd_args cmd;
1144 struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
1146 if (qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DESTROY_RX_CTX))
1149 if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1150 cmd.req.arg[0] |= (0x3 << 29);
1152 if (qlcnic_sriov_pf_check(adapter))
1153 qlcnic_pf_set_interface_id_del_rx_ctx(adapter, &temp);
1155 cmd.req.arg[1] = recv_ctx->context_id | temp;
1156 err = qlcnic_issue_cmd(adapter, &cmd);
1158 dev_err(&adapter->pdev->dev,
1159 "Failed to destroy rx ctx in firmware\n");
1161 recv_ctx->state = QLCNIC_HOST_CTX_STATE_FREED;
1162 qlcnic_free_mbx_args(&cmd);
1165 int qlcnic_83xx_create_rx_ctx(struct qlcnic_adapter *adapter)
1167 int i, err, index, sds_mbx_size, rds_mbx_size;
1168 u8 num_sds, num_rds;
1169 u32 *buf, intrpt_id, intr_mask, cap = 0;
1170 struct qlcnic_host_sds_ring *sds;
1171 struct qlcnic_host_rds_ring *rds;
1172 struct qlcnic_sds_mbx sds_mbx;
1173 struct qlcnic_rds_mbx rds_mbx;
1174 struct qlcnic_cmd_args cmd;
1175 struct qlcnic_rcv_mbx_out *mbx_out;
1176 struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
1177 struct qlcnic_hardware_context *ahw = adapter->ahw;
1178 num_rds = adapter->max_rds_rings;
1180 if (adapter->drv_sds_rings <= QLCNIC_MAX_SDS_RINGS)
1181 num_sds = adapter->drv_sds_rings;
1183 num_sds = QLCNIC_MAX_SDS_RINGS;
1185 sds_mbx_size = sizeof(struct qlcnic_sds_mbx);
1186 rds_mbx_size = sizeof(struct qlcnic_rds_mbx);
1187 cap = QLCNIC_CAP0_LEGACY_CONTEXT;
1189 if (adapter->flags & QLCNIC_FW_LRO_MSS_CAP)
1190 cap |= QLC_83XX_FW_CAP_LRO_MSS;
1192 /* set mailbox hdr and capabilities */
1193 err = qlcnic_alloc_mbx_args(&cmd, adapter,
1194 QLCNIC_CMD_CREATE_RX_CTX);
1198 if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1199 cmd.req.arg[0] |= (0x3 << 29);
1201 cmd.req.arg[1] = cap;
1202 cmd.req.arg[5] = 1 | (num_rds << 5) | (num_sds << 8) |
1203 (QLC_83XX_HOST_RDS_MODE_UNIQUE << 16);
1205 if (qlcnic_sriov_pf_check(adapter))
1206 qlcnic_pf_set_interface_id_create_rx_ctx(adapter,
1208 /* set up status rings, mbx 8-57/87 */
1209 index = QLC_83XX_HOST_SDS_MBX_IDX;
1210 for (i = 0; i < num_sds; i++) {
1211 memset(&sds_mbx, 0, sds_mbx_size);
1212 sds = &recv_ctx->sds_rings[i];
1214 memset(sds->desc_head, 0, STATUS_DESC_RINGSIZE(sds));
1215 sds_mbx.phy_addr_low = LSD(sds->phys_addr);
1216 sds_mbx.phy_addr_high = MSD(sds->phys_addr);
1217 sds_mbx.sds_ring_size = sds->num_desc;
1218 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1219 intrpt_id = ahw->intr_tbl[i].id;
1221 intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
1222 if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
1223 sds_mbx.intrpt_id = intrpt_id;
1225 sds_mbx.intrpt_id = 0xffff;
1226 sds_mbx.intrpt_val = 0;
1227 buf = &cmd.req.arg[index];
1228 memcpy(buf, &sds_mbx, sds_mbx_size);
1229 index += sds_mbx_size / sizeof(u32);
1231 /* set up receive rings, mbx 88-111/135 */
1232 index = QLCNIC_HOST_RDS_MBX_IDX;
1233 rds = &recv_ctx->rds_rings[0];
1235 memset(&rds_mbx, 0, rds_mbx_size);
1236 rds_mbx.phy_addr_reg_low = LSD(rds->phys_addr);
1237 rds_mbx.phy_addr_reg_high = MSD(rds->phys_addr);
1238 rds_mbx.reg_ring_sz = rds->dma_size;
1239 rds_mbx.reg_ring_len = rds->num_desc;
1241 rds = &recv_ctx->rds_rings[1];
1243 rds_mbx.phy_addr_jmb_low = LSD(rds->phys_addr);
1244 rds_mbx.phy_addr_jmb_high = MSD(rds->phys_addr);
1245 rds_mbx.jmb_ring_sz = rds->dma_size;
1246 rds_mbx.jmb_ring_len = rds->num_desc;
1247 buf = &cmd.req.arg[index];
1248 memcpy(buf, &rds_mbx, rds_mbx_size);
1250 /* send the mailbox command */
1251 err = ahw->hw_ops->mbx_cmd(adapter, &cmd);
1253 dev_err(&adapter->pdev->dev,
1254 "Failed to create Rx ctx in firmware%d\n", err);
1257 mbx_out = (struct qlcnic_rcv_mbx_out *)&cmd.rsp.arg[1];
1258 recv_ctx->context_id = mbx_out->ctx_id;
1259 recv_ctx->state = mbx_out->state;
1260 recv_ctx->virt_port = mbx_out->vport_id;
1261 dev_info(&adapter->pdev->dev, "Rx Context[%d] Created, state:0x%x\n",
1262 recv_ctx->context_id, recv_ctx->state);
1263 /* Receive descriptor ring */
1265 rds = &recv_ctx->rds_rings[0];
1266 rds->crb_rcv_producer = ahw->pci_base0 +
1267 mbx_out->host_prod[0].reg_buf;
1269 rds = &recv_ctx->rds_rings[1];
1270 rds->crb_rcv_producer = ahw->pci_base0 +
1271 mbx_out->host_prod[0].jmb_buf;
1272 /* status descriptor ring */
1273 for (i = 0; i < num_sds; i++) {
1274 sds = &recv_ctx->sds_rings[i];
1275 sds->crb_sts_consumer = ahw->pci_base0 +
1276 mbx_out->host_csmr[i];
1277 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1278 intr_mask = ahw->intr_tbl[i].src;
1280 intr_mask = QLCRDX(ahw, QLCNIC_DEF_INT_MASK);
1281 sds->crb_intr_mask = ahw->pci_base0 + intr_mask;
1284 if (adapter->drv_sds_rings > QLCNIC_MAX_SDS_RINGS)
1285 err = qlcnic_83xx_add_rings(adapter);
1287 qlcnic_free_mbx_args(&cmd);
1291 void qlcnic_83xx_del_tx_ctx(struct qlcnic_adapter *adapter,
1292 struct qlcnic_host_tx_ring *tx_ring)
1294 struct qlcnic_cmd_args cmd;
1297 if (qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DESTROY_TX_CTX))
1300 if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1301 cmd.req.arg[0] |= (0x3 << 29);
1303 if (qlcnic_sriov_pf_check(adapter))
1304 qlcnic_pf_set_interface_id_del_tx_ctx(adapter, &temp);
1306 cmd.req.arg[1] = tx_ring->ctx_id | temp;
1307 if (qlcnic_issue_cmd(adapter, &cmd))
1308 dev_err(&adapter->pdev->dev,
1309 "Failed to destroy tx ctx in firmware\n");
1310 qlcnic_free_mbx_args(&cmd);
1313 int qlcnic_83xx_create_tx_ctx(struct qlcnic_adapter *adapter,
1314 struct qlcnic_host_tx_ring *tx, int ring)
1318 u32 *buf, intr_mask, temp = 0;
1319 struct qlcnic_cmd_args cmd;
1320 struct qlcnic_tx_mbx mbx;
1321 struct qlcnic_tx_mbx_out *mbx_out;
1322 struct qlcnic_hardware_context *ahw = adapter->ahw;
1325 /* Reset host resources */
1327 tx->sw_consumer = 0;
1328 *(tx->hw_consumer) = 0;
1330 memset(&mbx, 0, sizeof(struct qlcnic_tx_mbx));
1332 /* setup mailbox inbox registerss */
1333 mbx.phys_addr_low = LSD(tx->phys_addr);
1334 mbx.phys_addr_high = MSD(tx->phys_addr);
1335 mbx.cnsmr_index_low = LSD(tx->hw_cons_phys_addr);
1336 mbx.cnsmr_index_high = MSD(tx->hw_cons_phys_addr);
1337 mbx.size = tx->num_desc;
1338 if (adapter->flags & QLCNIC_MSIX_ENABLED) {
1339 if (!(adapter->flags & QLCNIC_TX_INTR_SHARED))
1340 msix_vector = adapter->drv_sds_rings + ring;
1342 msix_vector = adapter->drv_sds_rings - 1;
1343 msix_id = ahw->intr_tbl[msix_vector].id;
1345 msix_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
1348 if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
1349 mbx.intr_id = msix_id;
1351 mbx.intr_id = 0xffff;
1354 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CREATE_TX_CTX);
1358 if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1359 cmd.req.arg[0] |= (0x3 << 29);
1361 if (qlcnic_sriov_pf_check(adapter))
1362 qlcnic_pf_set_interface_id_create_tx_ctx(adapter, &temp);
1364 cmd.req.arg[1] = QLCNIC_CAP0_LEGACY_CONTEXT;
1365 cmd.req.arg[5] = QLCNIC_SINGLE_RING | temp;
1367 buf = &cmd.req.arg[6];
1368 memcpy(buf, &mbx, sizeof(struct qlcnic_tx_mbx));
1369 /* send the mailbox command*/
1370 err = qlcnic_issue_cmd(adapter, &cmd);
1372 netdev_err(adapter->netdev,
1373 "Failed to create Tx ctx in firmware 0x%x\n", err);
1376 mbx_out = (struct qlcnic_tx_mbx_out *)&cmd.rsp.arg[2];
1377 tx->crb_cmd_producer = ahw->pci_base0 + mbx_out->host_prod;
1378 tx->ctx_id = mbx_out->ctx_id;
1379 if ((adapter->flags & QLCNIC_MSIX_ENABLED) &&
1380 !(adapter->flags & QLCNIC_TX_INTR_SHARED)) {
1381 intr_mask = ahw->intr_tbl[adapter->drv_sds_rings + ring].src;
1382 tx->crb_intr_mask = ahw->pci_base0 + intr_mask;
1384 netdev_info(adapter->netdev,
1385 "Tx Context[0x%x] Created, state:0x%x\n",
1386 tx->ctx_id, mbx_out->state);
1388 qlcnic_free_mbx_args(&cmd);
1392 static int qlcnic_83xx_diag_alloc_res(struct net_device *netdev, int test,
1395 struct qlcnic_adapter *adapter = netdev_priv(netdev);
1396 struct qlcnic_host_sds_ring *sds_ring;
1397 struct qlcnic_host_rds_ring *rds_ring;
1398 u16 adapter_state = adapter->is_up;
1402 netif_device_detach(netdev);
1404 if (netif_running(netdev))
1405 __qlcnic_down(adapter, netdev);
1407 qlcnic_detach(adapter);
1409 adapter->drv_sds_rings = QLCNIC_SINGLE_RING;
1410 adapter->ahw->diag_test = test;
1411 adapter->ahw->linkup = 0;
1413 ret = qlcnic_attach(adapter);
1415 netif_device_attach(netdev);
1419 ret = qlcnic_fw_create_ctx(adapter);
1421 qlcnic_detach(adapter);
1422 if (adapter_state == QLCNIC_ADAPTER_UP_MAGIC) {
1423 adapter->drv_sds_rings = num_sds_ring;
1424 qlcnic_attach(adapter);
1426 netif_device_attach(netdev);
1430 for (ring = 0; ring < adapter->max_rds_rings; ring++) {
1431 rds_ring = &adapter->recv_ctx->rds_rings[ring];
1432 qlcnic_post_rx_buffers(adapter, rds_ring, ring);
1435 if (adapter->ahw->diag_test == QLCNIC_INTERRUPT_TEST) {
1436 for (ring = 0; ring < adapter->drv_sds_rings; ring++) {
1437 sds_ring = &adapter->recv_ctx->sds_rings[ring];
1438 qlcnic_enable_sds_intr(adapter, sds_ring);
1442 if (adapter->ahw->diag_test == QLCNIC_LOOPBACK_TEST) {
1443 adapter->ahw->loopback_state = 0;
1444 adapter->ahw->hw_ops->setup_link_event(adapter, 1);
1447 set_bit(__QLCNIC_DEV_UP, &adapter->state);
1451 static void qlcnic_83xx_diag_free_res(struct net_device *netdev,
1454 struct qlcnic_adapter *adapter = netdev_priv(netdev);
1455 struct qlcnic_host_sds_ring *sds_ring;
1458 clear_bit(__QLCNIC_DEV_UP, &adapter->state);
1459 if (adapter->ahw->diag_test == QLCNIC_INTERRUPT_TEST) {
1460 for (ring = 0; ring < adapter->drv_sds_rings; ring++) {
1461 sds_ring = &adapter->recv_ctx->sds_rings[ring];
1462 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1463 qlcnic_disable_sds_intr(adapter, sds_ring);
1467 qlcnic_fw_destroy_ctx(adapter);
1468 qlcnic_detach(adapter);
1470 adapter->ahw->diag_test = 0;
1471 adapter->drv_sds_rings = drv_sds_rings;
1473 if (qlcnic_attach(adapter))
1476 if (netif_running(netdev))
1477 __qlcnic_up(adapter, netdev);
1480 netif_device_attach(netdev);
1483 static void qlcnic_83xx_get_beacon_state(struct qlcnic_adapter *adapter)
1485 struct qlcnic_hardware_context *ahw = adapter->ahw;
1486 struct qlcnic_cmd_args cmd;
1490 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_LED_CONFIG);
1492 err = qlcnic_issue_cmd(adapter, &cmd);
1494 beacon_state = cmd.rsp.arg[4];
1495 if (beacon_state == QLCNIC_BEACON_DISABLE)
1496 ahw->beacon_state = QLC_83XX_BEACON_OFF;
1497 else if (beacon_state == QLC_83XX_ENABLE_BEACON)
1498 ahw->beacon_state = QLC_83XX_BEACON_ON;
1501 netdev_err(adapter->netdev, "Get beacon state failed, err=%d\n",
1505 qlcnic_free_mbx_args(&cmd);
1510 int qlcnic_83xx_config_led(struct qlcnic_adapter *adapter, u32 state,
1513 struct qlcnic_cmd_args cmd;
1518 /* Get LED configuration */
1519 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1520 QLCNIC_CMD_GET_LED_CONFIG);
1524 status = qlcnic_issue_cmd(adapter, &cmd);
1526 dev_err(&adapter->pdev->dev,
1527 "Get led config failed.\n");
1530 for (i = 0; i < 4; i++)
1531 adapter->ahw->mbox_reg[i] = cmd.rsp.arg[i+1];
1533 qlcnic_free_mbx_args(&cmd);
1534 /* Set LED Configuration */
1535 mbx_in = (LSW(QLC_83XX_LED_CONFIG) << 16) |
1536 LSW(QLC_83XX_LED_CONFIG);
1537 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1538 QLCNIC_CMD_SET_LED_CONFIG);
1542 cmd.req.arg[1] = mbx_in;
1543 cmd.req.arg[2] = mbx_in;
1544 cmd.req.arg[3] = mbx_in;
1546 cmd.req.arg[4] = QLC_83XX_ENABLE_BEACON;
1547 status = qlcnic_issue_cmd(adapter, &cmd);
1549 dev_err(&adapter->pdev->dev,
1550 "Set led config failed.\n");
1553 qlcnic_free_mbx_args(&cmd);
1557 /* Restoring default LED configuration */
1558 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1559 QLCNIC_CMD_SET_LED_CONFIG);
1563 cmd.req.arg[1] = adapter->ahw->mbox_reg[0];
1564 cmd.req.arg[2] = adapter->ahw->mbox_reg[1];
1565 cmd.req.arg[3] = adapter->ahw->mbox_reg[2];
1567 cmd.req.arg[4] = adapter->ahw->mbox_reg[3];
1568 status = qlcnic_issue_cmd(adapter, &cmd);
1570 dev_err(&adapter->pdev->dev,
1571 "Restoring led config failed.\n");
1572 qlcnic_free_mbx_args(&cmd);
1577 int qlcnic_83xx_set_led(struct net_device *netdev,
1578 enum ethtool_phys_id_state state)
1580 struct qlcnic_adapter *adapter = netdev_priv(netdev);
1581 int err = -EIO, active = 1;
1583 if (adapter->ahw->op_mode == QLCNIC_NON_PRIV_FUNC) {
1585 "LED test is not supported in non-privileged mode\n");
1590 case ETHTOOL_ID_ACTIVE:
1591 if (test_and_set_bit(__QLCNIC_LED_ENABLE, &adapter->state))
1594 if (test_bit(__QLCNIC_RESETTING, &adapter->state))
1597 err = qlcnic_83xx_config_led(adapter, active, 0);
1599 netdev_err(netdev, "Failed to set LED blink state\n");
1601 case ETHTOOL_ID_INACTIVE:
1604 if (test_bit(__QLCNIC_RESETTING, &adapter->state))
1607 err = qlcnic_83xx_config_led(adapter, active, 0);
1609 netdev_err(netdev, "Failed to reset LED blink state\n");
1617 clear_bit(__QLCNIC_LED_ENABLE, &adapter->state);
1622 void qlcnic_83xx_initialize_nic(struct qlcnic_adapter *adapter, int enable)
1624 struct qlcnic_cmd_args cmd;
1627 if (qlcnic_sriov_vf_check(adapter))
1631 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1632 QLCNIC_CMD_INIT_NIC_FUNC);
1634 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1635 QLCNIC_CMD_STOP_NIC_FUNC);
1640 cmd.req.arg[1] = QLC_REGISTER_LB_IDC | QLC_INIT_FW_RESOURCES;
1643 cmd.req.arg[1] |= QLC_REGISTER_DCB_AEN;
1645 status = qlcnic_issue_cmd(adapter, &cmd);
1647 dev_err(&adapter->pdev->dev,
1648 "Failed to %s in NIC IDC function event.\n",
1649 (enable ? "register" : "unregister"));
1651 qlcnic_free_mbx_args(&cmd);
1654 static int qlcnic_83xx_set_port_config(struct qlcnic_adapter *adapter)
1656 struct qlcnic_cmd_args cmd;
1659 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_PORT_CONFIG);
1663 cmd.req.arg[1] = adapter->ahw->port_config;
1664 err = qlcnic_issue_cmd(adapter, &cmd);
1666 dev_info(&adapter->pdev->dev, "Set Port Config failed.\n");
1667 qlcnic_free_mbx_args(&cmd);
1671 static int qlcnic_83xx_get_port_config(struct qlcnic_adapter *adapter)
1673 struct qlcnic_cmd_args cmd;
1676 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_PORT_CONFIG);
1680 err = qlcnic_issue_cmd(adapter, &cmd);
1682 dev_info(&adapter->pdev->dev, "Get Port config failed\n");
1684 adapter->ahw->port_config = cmd.rsp.arg[1];
1685 qlcnic_free_mbx_args(&cmd);
1689 int qlcnic_83xx_setup_link_event(struct qlcnic_adapter *adapter, int enable)
1693 struct qlcnic_cmd_args cmd;
1695 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_LINK_EVENT);
1699 temp = adapter->recv_ctx->context_id << 16;
1700 cmd.req.arg[1] = (enable ? 1 : 0) | BIT_8 | temp;
1701 err = qlcnic_issue_cmd(adapter, &cmd);
1703 dev_info(&adapter->pdev->dev,
1704 "Setup linkevent mailbox failed\n");
1705 qlcnic_free_mbx_args(&cmd);
1709 static void qlcnic_83xx_set_interface_id_promisc(struct qlcnic_adapter *adapter,
1712 if (qlcnic_sriov_pf_check(adapter)) {
1713 qlcnic_alloc_lb_filters_mem(adapter);
1714 qlcnic_pf_set_interface_id_promisc(adapter, interface_id);
1715 adapter->rx_mac_learn = true;
1717 if (!qlcnic_sriov_vf_check(adapter))
1718 *interface_id = adapter->recv_ctx->context_id << 16;
1722 int qlcnic_83xx_nic_set_promisc(struct qlcnic_adapter *adapter, u32 mode)
1724 struct qlcnic_cmd_args *cmd = NULL;
1728 if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
1731 cmd = kzalloc(sizeof(*cmd), GFP_ATOMIC);
1735 err = qlcnic_alloc_mbx_args(cmd, adapter,
1736 QLCNIC_CMD_CONFIGURE_MAC_RX_MODE);
1740 cmd->type = QLC_83XX_MBX_CMD_NO_WAIT;
1741 qlcnic_83xx_set_interface_id_promisc(adapter, &temp);
1743 if (qlcnic_84xx_check(adapter) && qlcnic_sriov_pf_check(adapter))
1744 mode = VPORT_MISS_MODE_ACCEPT_ALL;
1746 cmd->req.arg[1] = mode | temp;
1747 err = qlcnic_issue_cmd(adapter, cmd);
1751 qlcnic_free_mbx_args(cmd);
1758 int qlcnic_83xx_loopback_test(struct net_device *netdev, u8 mode)
1760 struct qlcnic_adapter *adapter = netdev_priv(netdev);
1761 struct qlcnic_hardware_context *ahw = adapter->ahw;
1762 u8 drv_sds_rings = adapter->drv_sds_rings;
1763 u8 drv_tx_rings = adapter->drv_tx_rings;
1764 int ret = 0, loop = 0;
1766 if (ahw->op_mode == QLCNIC_NON_PRIV_FUNC) {
1768 "Loopback test not supported in non privileged mode\n");
1772 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1773 netdev_info(netdev, "Device is resetting\n");
1777 if (qlcnic_get_diag_lock(adapter)) {
1778 netdev_info(netdev, "Device is in diagnostics mode\n");
1782 netdev_info(netdev, "%s loopback test in progress\n",
1783 mode == QLCNIC_ILB_MODE ? "internal" : "external");
1785 ret = qlcnic_83xx_diag_alloc_res(netdev, QLCNIC_LOOPBACK_TEST,
1788 goto fail_diag_alloc;
1790 ret = qlcnic_83xx_set_lb_mode(adapter, mode);
1794 /* Poll for link up event before running traffic */
1796 msleep(QLC_83XX_LB_MSLEEP_COUNT);
1798 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1800 "Device is resetting, free LB test resources\n");
1804 if (loop++ > QLC_83XX_LB_WAIT_COUNT) {
1806 "Firmware didn't sent link up event to loopback request\n");
1808 qlcnic_83xx_clear_lb_mode(adapter, mode);
1811 } while ((adapter->ahw->linkup && ahw->has_link_events) != 1);
1813 ret = qlcnic_do_lb_test(adapter, mode);
1815 qlcnic_83xx_clear_lb_mode(adapter, mode);
1818 qlcnic_83xx_diag_free_res(netdev, drv_sds_rings);
1821 adapter->drv_sds_rings = drv_sds_rings;
1822 adapter->drv_tx_rings = drv_tx_rings;
1823 qlcnic_release_diag_lock(adapter);
1827 static void qlcnic_extend_lb_idc_cmpltn_wait(struct qlcnic_adapter *adapter,
1828 u32 *max_wait_count)
1830 struct qlcnic_hardware_context *ahw = adapter->ahw;
1833 netdev_info(adapter->netdev, "Received loopback IDC time extend event for 0x%x seconds\n",
1834 ahw->extend_lb_time);
1835 temp = ahw->extend_lb_time * 1000;
1836 *max_wait_count += temp / QLC_83XX_LB_MSLEEP_COUNT;
1837 ahw->extend_lb_time = 0;
1840 static int qlcnic_83xx_set_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
1842 struct qlcnic_hardware_context *ahw = adapter->ahw;
1843 struct net_device *netdev = adapter->netdev;
1844 u32 config, max_wait_count;
1845 int status = 0, loop = 0;
1847 ahw->extend_lb_time = 0;
1848 max_wait_count = QLC_83XX_LB_WAIT_COUNT;
1849 status = qlcnic_83xx_get_port_config(adapter);
1853 config = ahw->port_config;
1855 /* Check if port is already in loopback mode */
1856 if ((config & QLC_83XX_CFG_LOOPBACK_HSS) ||
1857 (config & QLC_83XX_CFG_LOOPBACK_EXT)) {
1859 "Port already in Loopback mode.\n");
1860 return -EINPROGRESS;
1863 set_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1865 if (mode == QLCNIC_ILB_MODE)
1866 ahw->port_config |= QLC_83XX_CFG_LOOPBACK_HSS;
1867 if (mode == QLCNIC_ELB_MODE)
1868 ahw->port_config |= QLC_83XX_CFG_LOOPBACK_EXT;
1870 status = qlcnic_83xx_set_port_config(adapter);
1873 "Failed to Set Loopback Mode = 0x%x.\n",
1875 ahw->port_config = config;
1876 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1880 /* Wait for Link and IDC Completion AEN */
1882 msleep(QLC_83XX_LB_MSLEEP_COUNT);
1884 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1886 "Device is resetting, free LB test resources\n");
1887 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1891 if (ahw->extend_lb_time)
1892 qlcnic_extend_lb_idc_cmpltn_wait(adapter,
1895 if (loop++ > max_wait_count) {
1896 netdev_err(netdev, "%s: Did not receive loopback IDC completion AEN\n",
1898 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1899 qlcnic_83xx_clear_lb_mode(adapter, mode);
1902 } while (test_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status));
1904 qlcnic_sre_macaddr_change(adapter, adapter->mac_addr, 0,
1909 static int qlcnic_83xx_clear_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
1911 struct qlcnic_hardware_context *ahw = adapter->ahw;
1912 u32 config = ahw->port_config, max_wait_count;
1913 struct net_device *netdev = adapter->netdev;
1914 int status = 0, loop = 0;
1916 ahw->extend_lb_time = 0;
1917 max_wait_count = QLC_83XX_LB_WAIT_COUNT;
1918 set_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1919 if (mode == QLCNIC_ILB_MODE)
1920 ahw->port_config &= ~QLC_83XX_CFG_LOOPBACK_HSS;
1921 if (mode == QLCNIC_ELB_MODE)
1922 ahw->port_config &= ~QLC_83XX_CFG_LOOPBACK_EXT;
1924 status = qlcnic_83xx_set_port_config(adapter);
1927 "Failed to Clear Loopback Mode = 0x%x.\n",
1929 ahw->port_config = config;
1930 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1934 /* Wait for Link and IDC Completion AEN */
1936 msleep(QLC_83XX_LB_MSLEEP_COUNT);
1938 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1940 "Device is resetting, free LB test resources\n");
1941 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1945 if (ahw->extend_lb_time)
1946 qlcnic_extend_lb_idc_cmpltn_wait(adapter,
1949 if (loop++ > max_wait_count) {
1950 netdev_err(netdev, "%s: Did not receive loopback IDC completion AEN\n",
1952 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1955 } while (test_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status));
1957 qlcnic_sre_macaddr_change(adapter, adapter->mac_addr, 0,
1962 static void qlcnic_83xx_set_interface_id_ipaddr(struct qlcnic_adapter *adapter,
1965 if (qlcnic_sriov_pf_check(adapter)) {
1966 qlcnic_pf_set_interface_id_ipaddr(adapter, interface_id);
1968 if (!qlcnic_sriov_vf_check(adapter))
1969 *interface_id = adapter->recv_ctx->context_id << 16;
1973 void qlcnic_83xx_config_ipaddr(struct qlcnic_adapter *adapter, __be32 ip,
1977 u32 temp = 0, temp_ip;
1978 struct qlcnic_cmd_args cmd;
1980 err = qlcnic_alloc_mbx_args(&cmd, adapter,
1981 QLCNIC_CMD_CONFIGURE_IP_ADDR);
1985 qlcnic_83xx_set_interface_id_ipaddr(adapter, &temp);
1987 if (mode == QLCNIC_IP_UP)
1988 cmd.req.arg[1] = 1 | temp;
1990 cmd.req.arg[1] = 2 | temp;
1993 * Adapter needs IP address in network byte order.
1994 * But hardware mailbox registers go through writel(), hence IP address
1995 * gets swapped on big endian architecture.
1996 * To negate swapping of writel() on big endian architecture
1997 * use swab32(value).
2000 temp_ip = swab32(ntohl(ip));
2001 memcpy(&cmd.req.arg[2], &temp_ip, sizeof(u32));
2002 err = qlcnic_issue_cmd(adapter, &cmd);
2003 if (err != QLCNIC_RCODE_SUCCESS)
2004 dev_err(&adapter->netdev->dev,
2005 "could not notify %s IP 0x%x request\n",
2006 (mode == QLCNIC_IP_UP) ? "Add" : "Remove", ip);
2008 qlcnic_free_mbx_args(&cmd);
2011 int qlcnic_83xx_config_hw_lro(struct qlcnic_adapter *adapter, int mode)
2015 struct qlcnic_cmd_args cmd;
2018 lro_bit_mask = (mode ? (BIT_0 | BIT_1 | BIT_2 | BIT_3) : 0);
2020 if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
2023 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIGURE_HW_LRO);
2027 temp = adapter->recv_ctx->context_id << 16;
2028 arg1 = lro_bit_mask | temp;
2029 cmd.req.arg[1] = arg1;
2031 err = qlcnic_issue_cmd(adapter, &cmd);
2033 dev_info(&adapter->pdev->dev, "LRO config failed\n");
2034 qlcnic_free_mbx_args(&cmd);
2039 int qlcnic_83xx_config_rss(struct qlcnic_adapter *adapter, int enable)
2043 struct qlcnic_cmd_args cmd;
2044 const u64 key[] = { 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
2045 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
2046 0x255b0ec26d5a56daULL };
2048 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIGURE_RSS);
2054 * 5-4: hash_type_ipv4
2055 * 7-6: hash_type_ipv6
2057 * 9: use indirection table
2058 * 16-31: indirection table mask
2060 word = ((u32)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
2061 ((u32)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
2062 ((u32)(enable & 0x1) << 8) |
2064 cmd.req.arg[1] = (adapter->recv_ctx->context_id);
2065 cmd.req.arg[2] = word;
2066 memcpy(&cmd.req.arg[4], key, sizeof(key));
2068 err = qlcnic_issue_cmd(adapter, &cmd);
2071 dev_info(&adapter->pdev->dev, "RSS config failed\n");
2072 qlcnic_free_mbx_args(&cmd);
2078 static void qlcnic_83xx_set_interface_id_macaddr(struct qlcnic_adapter *adapter,
2081 if (qlcnic_sriov_pf_check(adapter)) {
2082 qlcnic_pf_set_interface_id_macaddr(adapter, interface_id);
2084 if (!qlcnic_sriov_vf_check(adapter))
2085 *interface_id = adapter->recv_ctx->context_id << 16;
2089 int qlcnic_83xx_sre_macaddr_change(struct qlcnic_adapter *adapter, u8 *addr,
2092 struct qlcnic_cmd_args *cmd = NULL;
2093 struct qlcnic_macvlan_mbx mv;
2097 if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
2100 cmd = kzalloc(sizeof(*cmd), GFP_ATOMIC);
2104 err = qlcnic_alloc_mbx_args(cmd, adapter, QLCNIC_CMD_CONFIG_MAC_VLAN);
2108 cmd->type = QLC_83XX_MBX_CMD_NO_WAIT;
2111 op = (op == QLCNIC_MAC_ADD || op == QLCNIC_MAC_VLAN_ADD) ?
2112 QLCNIC_MAC_VLAN_ADD : QLCNIC_MAC_VLAN_DEL;
2114 cmd->req.arg[1] = op | (1 << 8);
2115 qlcnic_83xx_set_interface_id_macaddr(adapter, &temp);
2116 cmd->req.arg[1] |= temp;
2118 mv.mac_addr0 = addr[0];
2119 mv.mac_addr1 = addr[1];
2120 mv.mac_addr2 = addr[2];
2121 mv.mac_addr3 = addr[3];
2122 mv.mac_addr4 = addr[4];
2123 mv.mac_addr5 = addr[5];
2124 buf = &cmd->req.arg[2];
2125 memcpy(buf, &mv, sizeof(struct qlcnic_macvlan_mbx));
2126 err = qlcnic_issue_cmd(adapter, cmd);
2130 qlcnic_free_mbx_args(cmd);
2136 void qlcnic_83xx_change_l2_filter(struct qlcnic_adapter *adapter, u64 *addr,
2140 memcpy(&mac, addr, ETH_ALEN);
2141 qlcnic_83xx_sre_macaddr_change(adapter, mac, vlan_id, QLCNIC_MAC_ADD);
2144 static void qlcnic_83xx_configure_mac(struct qlcnic_adapter *adapter, u8 *mac,
2145 u8 type, struct qlcnic_cmd_args *cmd)
2148 case QLCNIC_SET_STATION_MAC:
2149 case QLCNIC_SET_FAC_DEF_MAC:
2150 memcpy(&cmd->req.arg[2], mac, sizeof(u32));
2151 memcpy(&cmd->req.arg[3], &mac[4], sizeof(u16));
2154 cmd->req.arg[1] = type;
2157 int qlcnic_83xx_get_mac_address(struct qlcnic_adapter *adapter, u8 *mac,
2161 struct qlcnic_cmd_args cmd;
2162 u32 mac_low, mac_high;
2165 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_MAC_ADDRESS);
2169 qlcnic_83xx_configure_mac(adapter, mac, QLCNIC_GET_CURRENT_MAC, &cmd);
2170 err = qlcnic_issue_cmd(adapter, &cmd);
2172 if (err == QLCNIC_RCODE_SUCCESS) {
2173 mac_low = cmd.rsp.arg[1];
2174 mac_high = cmd.rsp.arg[2];
2176 for (i = 0; i < 2; i++)
2177 mac[i] = (u8) (mac_high >> ((1 - i) * 8));
2178 for (i = 2; i < 6; i++)
2179 mac[i] = (u8) (mac_low >> ((5 - i) * 8));
2181 dev_err(&adapter->pdev->dev, "Failed to get mac address%d\n",
2185 qlcnic_free_mbx_args(&cmd);
2189 static int qlcnic_83xx_set_rx_intr_coal(struct qlcnic_adapter *adapter)
2191 struct qlcnic_nic_intr_coalesce *coal = &adapter->ahw->coal;
2192 struct qlcnic_cmd_args cmd;
2196 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_INTR_COAL);
2200 temp = adapter->recv_ctx->context_id;
2201 cmd.req.arg[1] = QLCNIC_INTR_COAL_TYPE_RX | temp << 16;
2202 temp = coal->rx_time_us;
2203 cmd.req.arg[2] = coal->rx_packets | temp << 16;
2204 cmd.req.arg[3] = coal->flag;
2206 err = qlcnic_issue_cmd(adapter, &cmd);
2207 if (err != QLCNIC_RCODE_SUCCESS)
2208 netdev_err(adapter->netdev,
2209 "failed to set interrupt coalescing parameters\n");
2211 qlcnic_free_mbx_args(&cmd);
2216 static int qlcnic_83xx_set_tx_intr_coal(struct qlcnic_adapter *adapter)
2218 struct qlcnic_nic_intr_coalesce *coal = &adapter->ahw->coal;
2219 struct qlcnic_cmd_args cmd;
2223 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_INTR_COAL);
2227 temp = adapter->tx_ring->ctx_id;
2228 cmd.req.arg[1] = QLCNIC_INTR_COAL_TYPE_TX | temp << 16;
2229 temp = coal->tx_time_us;
2230 cmd.req.arg[2] = coal->tx_packets | temp << 16;
2231 cmd.req.arg[3] = coal->flag;
2233 err = qlcnic_issue_cmd(adapter, &cmd);
2234 if (err != QLCNIC_RCODE_SUCCESS)
2235 netdev_err(adapter->netdev,
2236 "failed to set interrupt coalescing parameters\n");
2238 qlcnic_free_mbx_args(&cmd);
2243 int qlcnic_83xx_set_rx_tx_intr_coal(struct qlcnic_adapter *adapter)
2247 err = qlcnic_83xx_set_rx_intr_coal(adapter);
2249 netdev_err(adapter->netdev,
2250 "failed to set Rx coalescing parameters\n");
2252 err = qlcnic_83xx_set_tx_intr_coal(adapter);
2254 netdev_err(adapter->netdev,
2255 "failed to set Tx coalescing parameters\n");
2260 int qlcnic_83xx_config_intr_coal(struct qlcnic_adapter *adapter,
2261 struct ethtool_coalesce *ethcoal)
2263 struct qlcnic_nic_intr_coalesce *coal = &adapter->ahw->coal;
2264 u32 rx_coalesce_usecs, rx_max_frames;
2265 u32 tx_coalesce_usecs, tx_max_frames;
2268 if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
2271 tx_coalesce_usecs = ethcoal->tx_coalesce_usecs;
2272 tx_max_frames = ethcoal->tx_max_coalesced_frames;
2273 rx_coalesce_usecs = ethcoal->rx_coalesce_usecs;
2274 rx_max_frames = ethcoal->rx_max_coalesced_frames;
2275 coal->flag = QLCNIC_INTR_DEFAULT;
2277 if ((coal->rx_time_us == rx_coalesce_usecs) &&
2278 (coal->rx_packets == rx_max_frames)) {
2279 coal->type = QLCNIC_INTR_COAL_TYPE_TX;
2280 coal->tx_time_us = tx_coalesce_usecs;
2281 coal->tx_packets = tx_max_frames;
2282 } else if ((coal->tx_time_us == tx_coalesce_usecs) &&
2283 (coal->tx_packets == tx_max_frames)) {
2284 coal->type = QLCNIC_INTR_COAL_TYPE_RX;
2285 coal->rx_time_us = rx_coalesce_usecs;
2286 coal->rx_packets = rx_max_frames;
2288 coal->type = QLCNIC_INTR_COAL_TYPE_RX_TX;
2289 coal->rx_time_us = rx_coalesce_usecs;
2290 coal->rx_packets = rx_max_frames;
2291 coal->tx_time_us = tx_coalesce_usecs;
2292 coal->tx_packets = tx_max_frames;
2295 switch (coal->type) {
2296 case QLCNIC_INTR_COAL_TYPE_RX:
2297 err = qlcnic_83xx_set_rx_intr_coal(adapter);
2299 case QLCNIC_INTR_COAL_TYPE_TX:
2300 err = qlcnic_83xx_set_tx_intr_coal(adapter);
2302 case QLCNIC_INTR_COAL_TYPE_RX_TX:
2303 err = qlcnic_83xx_set_rx_tx_intr_coal(adapter);
2307 netdev_err(adapter->netdev,
2308 "Invalid Interrupt coalescing type\n");
2315 static void qlcnic_83xx_handle_link_aen(struct qlcnic_adapter *adapter,
2318 struct qlcnic_hardware_context *ahw = adapter->ahw;
2319 u8 link_status, duplex;
2321 link_status = LSB(data[3]) & 1;
2323 ahw->link_speed = MSW(data[2]);
2324 duplex = LSB(MSW(data[3]));
2326 ahw->link_duplex = DUPLEX_FULL;
2328 ahw->link_duplex = DUPLEX_HALF;
2330 ahw->link_speed = SPEED_UNKNOWN;
2331 ahw->link_duplex = DUPLEX_UNKNOWN;
2334 ahw->link_autoneg = MSB(MSW(data[3]));
2335 ahw->module_type = MSB(LSW(data[3]));
2336 ahw->has_link_events = 1;
2337 ahw->lb_mode = data[4] & QLCNIC_LB_MODE_MASK;
2338 qlcnic_advert_link_change(adapter, link_status);
2341 static irqreturn_t qlcnic_83xx_handle_aen(int irq, void *data)
2343 struct qlcnic_adapter *adapter = data;
2344 struct qlcnic_mailbox *mbx;
2345 u32 mask, resp, event;
2346 unsigned long flags;
2348 mbx = adapter->ahw->mailbox;
2349 spin_lock_irqsave(&mbx->aen_lock, flags);
2350 resp = QLCRDX(adapter->ahw, QLCNIC_FW_MBX_CTRL);
2351 if (!(resp & QLCNIC_SET_OWNER))
2354 event = readl(QLCNIC_MBX_FW(adapter->ahw, 0));
2355 if (event & QLCNIC_MBX_ASYNC_EVENT)
2356 __qlcnic_83xx_process_aen(adapter);
2358 qlcnic_83xx_notify_mbx_response(mbx);
2361 mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
2362 writel(0, adapter->ahw->pci_base0 + mask);
2363 spin_unlock_irqrestore(&mbx->aen_lock, flags);
2367 int qlcnic_83xx_set_nic_info(struct qlcnic_adapter *adapter,
2368 struct qlcnic_info *nic)
2371 struct qlcnic_cmd_args cmd;
2373 if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC) {
2374 dev_err(&adapter->pdev->dev,
2375 "%s: Error, invoked by non management func\n",
2380 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_NIC_INFO);
2384 cmd.req.arg[1] = (nic->pci_func << 16);
2385 cmd.req.arg[2] = 0x1 << 16;
2386 cmd.req.arg[3] = nic->phys_port | (nic->switch_mode << 16);
2387 cmd.req.arg[4] = nic->capabilities;
2388 cmd.req.arg[5] = (nic->max_mac_filters & 0xFF) | ((nic->max_mtu) << 16);
2389 cmd.req.arg[6] = (nic->max_tx_ques) | ((nic->max_rx_ques) << 16);
2390 cmd.req.arg[7] = (nic->min_tx_bw) | ((nic->max_tx_bw) << 16);
2391 for (i = 8; i < 32; i++)
2394 err = qlcnic_issue_cmd(adapter, &cmd);
2396 if (err != QLCNIC_RCODE_SUCCESS) {
2397 dev_err(&adapter->pdev->dev, "Failed to set nic info%d\n",
2402 qlcnic_free_mbx_args(&cmd);
2407 int qlcnic_83xx_get_nic_info(struct qlcnic_adapter *adapter,
2408 struct qlcnic_info *npar_info, u8 func_id)
2413 struct qlcnic_cmd_args cmd;
2414 struct qlcnic_hardware_context *ahw = adapter->ahw;
2416 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_NIC_INFO);
2420 if (func_id != ahw->pci_func) {
2421 temp = func_id << 16;
2422 cmd.req.arg[1] = op | BIT_31 | temp;
2424 cmd.req.arg[1] = ahw->pci_func << 16;
2426 err = qlcnic_issue_cmd(adapter, &cmd);
2428 dev_info(&adapter->pdev->dev,
2429 "Failed to get nic info %d\n", err);
2433 npar_info->op_type = cmd.rsp.arg[1];
2434 npar_info->pci_func = cmd.rsp.arg[2] & 0xFFFF;
2435 npar_info->op_mode = (cmd.rsp.arg[2] & 0xFFFF0000) >> 16;
2436 npar_info->phys_port = cmd.rsp.arg[3] & 0xFFFF;
2437 npar_info->switch_mode = (cmd.rsp.arg[3] & 0xFFFF0000) >> 16;
2438 npar_info->capabilities = cmd.rsp.arg[4];
2439 npar_info->max_mac_filters = cmd.rsp.arg[5] & 0xFF;
2440 npar_info->max_mtu = (cmd.rsp.arg[5] & 0xFFFF0000) >> 16;
2441 npar_info->max_tx_ques = cmd.rsp.arg[6] & 0xFFFF;
2442 npar_info->max_rx_ques = (cmd.rsp.arg[6] & 0xFFFF0000) >> 16;
2443 npar_info->min_tx_bw = cmd.rsp.arg[7] & 0xFFFF;
2444 npar_info->max_tx_bw = (cmd.rsp.arg[7] & 0xFFFF0000) >> 16;
2445 if (cmd.rsp.arg[8] & 0x1)
2446 npar_info->max_bw_reg_offset = (cmd.rsp.arg[8] & 0x7FFE) >> 1;
2447 if (cmd.rsp.arg[8] & 0x10000) {
2448 temp = (cmd.rsp.arg[8] & 0x7FFE0000) >> 17;
2449 npar_info->max_linkspeed_reg_offset = temp;
2452 memcpy(ahw->extra_capability, &cmd.rsp.arg[16],
2453 sizeof(ahw->extra_capability));
2456 qlcnic_free_mbx_args(&cmd);
2460 int qlcnic_get_pci_func_type(struct qlcnic_adapter *adapter, u16 type,
2461 u16 *nic, u16 *fcoe, u16 *iscsi)
2463 struct device *dev = &adapter->pdev->dev;
2467 case QLCNIC_TYPE_NIC:
2470 case QLCNIC_TYPE_FCOE:
2473 case QLCNIC_TYPE_ISCSI:
2477 dev_err(dev, "%s: Unknown PCI type[%x]\n",
2485 int qlcnic_83xx_get_pci_info(struct qlcnic_adapter *adapter,
2486 struct qlcnic_pci_info *pci_info)
2488 struct qlcnic_hardware_context *ahw = adapter->ahw;
2489 struct device *dev = &adapter->pdev->dev;
2490 u16 nic = 0, fcoe = 0, iscsi = 0;
2491 struct qlcnic_cmd_args cmd;
2492 int i, err = 0, j = 0;
2495 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_PCI_INFO);
2499 err = qlcnic_issue_cmd(adapter, &cmd);
2501 ahw->total_nic_func = 0;
2502 if (err == QLCNIC_RCODE_SUCCESS) {
2503 ahw->max_pci_func = cmd.rsp.arg[1] & 0xFF;
2504 for (i = 2, j = 0; j < ahw->max_vnic_func; j++, pci_info++) {
2505 pci_info->id = cmd.rsp.arg[i] & 0xFFFF;
2506 pci_info->active = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16;
2508 if (!pci_info->active) {
2509 i += QLC_SKIP_INACTIVE_PCI_REGS;
2512 pci_info->type = cmd.rsp.arg[i] & 0xFFFF;
2513 err = qlcnic_get_pci_func_type(adapter, pci_info->type,
2514 &nic, &fcoe, &iscsi);
2515 temp = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16;
2516 pci_info->default_port = temp;
2518 pci_info->tx_min_bw = cmd.rsp.arg[i] & 0xFFFF;
2519 temp = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16;
2520 pci_info->tx_max_bw = temp;
2522 memcpy(pci_info->mac, &cmd.rsp.arg[i], ETH_ALEN - 2);
2524 memcpy(pci_info->mac + sizeof(u32), &cmd.rsp.arg[i], 2);
2528 dev_err(dev, "Failed to get PCI Info, error = %d\n", err);
2532 ahw->total_nic_func = nic;
2533 ahw->total_pci_func = nic + fcoe + iscsi;
2534 if (ahw->total_nic_func == 0 || ahw->total_pci_func == 0) {
2535 dev_err(dev, "%s: Invalid function count: total nic func[%x], total pci func[%x]\n",
2536 __func__, ahw->total_nic_func, ahw->total_pci_func);
2539 qlcnic_free_mbx_args(&cmd);
2544 int qlcnic_83xx_config_intrpt(struct qlcnic_adapter *adapter, bool op_type)
2548 u32 val, temp, type;
2549 struct qlcnic_cmd_args cmd;
2551 max_ints = adapter->ahw->num_msix - 1;
2552 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_INTRPT);
2556 cmd.req.arg[1] = max_ints;
2558 if (qlcnic_sriov_vf_check(adapter))
2559 cmd.req.arg[1] |= (adapter->ahw->pci_func << 8) | BIT_16;
2561 for (i = 0, index = 2; i < max_ints; i++) {
2562 type = op_type ? QLCNIC_INTRPT_ADD : QLCNIC_INTRPT_DEL;
2563 val = type | (adapter->ahw->intr_tbl[i].type << 4);
2564 if (adapter->ahw->intr_tbl[i].type == QLCNIC_INTRPT_MSIX)
2565 val |= (adapter->ahw->intr_tbl[i].id << 16);
2566 cmd.req.arg[index++] = val;
2568 err = qlcnic_issue_cmd(adapter, &cmd);
2570 dev_err(&adapter->pdev->dev,
2571 "Failed to configure interrupts 0x%x\n", err);
2575 max_ints = cmd.rsp.arg[1];
2576 for (i = 0, index = 2; i < max_ints; i++, index += 2) {
2577 val = cmd.rsp.arg[index];
2579 dev_info(&adapter->pdev->dev,
2580 "Can't configure interrupt %d\n",
2581 adapter->ahw->intr_tbl[i].id);
2585 adapter->ahw->intr_tbl[i].id = MSW(val);
2586 adapter->ahw->intr_tbl[i].enabled = 1;
2587 temp = cmd.rsp.arg[index + 1];
2588 adapter->ahw->intr_tbl[i].src = temp;
2590 adapter->ahw->intr_tbl[i].id = i;
2591 adapter->ahw->intr_tbl[i].enabled = 0;
2592 adapter->ahw->intr_tbl[i].src = 0;
2596 qlcnic_free_mbx_args(&cmd);
2600 int qlcnic_83xx_lock_flash(struct qlcnic_adapter *adapter)
2602 int id, timeout = 0;
2605 while (status == 0) {
2606 status = QLC_SHARED_REG_RD32(adapter, QLCNIC_FLASH_LOCK);
2610 if (++timeout >= QLC_83XX_FLASH_LOCK_TIMEOUT) {
2611 id = QLC_SHARED_REG_RD32(adapter,
2612 QLCNIC_FLASH_LOCK_OWNER);
2613 dev_err(&adapter->pdev->dev,
2614 "%s: failed, lock held by %d\n", __func__, id);
2617 usleep_range(1000, 2000);
2620 QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER, adapter->portnum);
2624 void qlcnic_83xx_unlock_flash(struct qlcnic_adapter *adapter)
2626 QLC_SHARED_REG_RD32(adapter, QLCNIC_FLASH_UNLOCK);
2627 QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER, 0xFF);
2630 int qlcnic_83xx_lockless_flash_read32(struct qlcnic_adapter *adapter,
2631 u32 flash_addr, u8 *p_data,
2634 u32 word, range, flash_offset, addr = flash_addr, ret;
2635 ulong indirect_add, direct_window;
2638 flash_offset = addr & (QLCNIC_FLASH_SECTOR_SIZE - 1);
2640 dev_err(&adapter->pdev->dev, "Illegal addr = 0x%x\n", addr);
2644 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_DIRECT_WINDOW,
2645 (addr & 0xFFFF0000));
2647 range = flash_offset + (count * sizeof(u32));
2648 /* Check if data is spread across multiple sectors */
2649 if (range > (QLCNIC_FLASH_SECTOR_SIZE - 1)) {
2651 /* Multi sector read */
2652 for (i = 0; i < count; i++) {
2653 indirect_add = QLC_83XX_FLASH_DIRECT_DATA(addr);
2654 ret = QLCRD32(adapter, indirect_add, &err);
2659 *(u32 *)p_data = word;
2660 p_data = p_data + 4;
2662 flash_offset = flash_offset + 4;
2664 if (flash_offset > (QLCNIC_FLASH_SECTOR_SIZE - 1)) {
2665 direct_window = QLC_83XX_FLASH_DIRECT_WINDOW;
2666 /* This write is needed once for each sector */
2667 qlcnic_83xx_wrt_reg_indirect(adapter,
2674 /* Single sector read */
2675 for (i = 0; i < count; i++) {
2676 indirect_add = QLC_83XX_FLASH_DIRECT_DATA(addr);
2677 ret = QLCRD32(adapter, indirect_add, &err);
2682 *(u32 *)p_data = word;
2683 p_data = p_data + 4;
2691 static int qlcnic_83xx_poll_flash_status_reg(struct qlcnic_adapter *adapter)
2694 int retries = QLC_83XX_FLASH_READ_RETRY_COUNT;
2698 status = QLCRD32(adapter, QLC_83XX_FLASH_STATUS, &err);
2702 if ((status & QLC_83XX_FLASH_STATUS_READY) ==
2703 QLC_83XX_FLASH_STATUS_READY)
2706 usleep_range(1000, 1100);
2707 } while (--retries);
2715 int qlcnic_83xx_enable_flash_write(struct qlcnic_adapter *adapter)
2719 cmd = adapter->ahw->fdt.write_statusreg_cmd;
2720 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2721 (QLC_83XX_FLASH_FDT_WRITE_DEF_SIG | cmd));
2722 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2723 adapter->ahw->fdt.write_enable_bits);
2724 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2725 QLC_83XX_FLASH_SECOND_ERASE_MS_VAL);
2726 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2733 int qlcnic_83xx_disable_flash_write(struct qlcnic_adapter *adapter)
2737 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2738 (QLC_83XX_FLASH_FDT_WRITE_DEF_SIG |
2739 adapter->ahw->fdt.write_statusreg_cmd));
2740 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2741 adapter->ahw->fdt.write_disable_bits);
2742 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2743 QLC_83XX_FLASH_SECOND_ERASE_MS_VAL);
2744 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2751 int qlcnic_83xx_read_flash_mfg_id(struct qlcnic_adapter *adapter)
2756 if (qlcnic_83xx_lock_flash(adapter))
2759 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2760 QLC_83XX_FLASH_FDT_READ_MFG_ID_VAL);
2761 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2762 QLC_83XX_FLASH_READ_CTRL);
2763 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2765 qlcnic_83xx_unlock_flash(adapter);
2769 mfg_id = QLCRD32(adapter, QLC_83XX_FLASH_RDDATA, &err);
2771 qlcnic_83xx_unlock_flash(adapter);
2775 adapter->flash_mfg_id = (mfg_id & 0xFF);
2776 qlcnic_83xx_unlock_flash(adapter);
2781 int qlcnic_83xx_read_flash_descriptor_table(struct qlcnic_adapter *adapter)
2783 int count, fdt_size, ret = 0;
2785 fdt_size = sizeof(struct qlcnic_fdt);
2786 count = fdt_size / sizeof(u32);
2788 if (qlcnic_83xx_lock_flash(adapter))
2791 memset(&adapter->ahw->fdt, 0, fdt_size);
2792 ret = qlcnic_83xx_lockless_flash_read32(adapter, QLCNIC_FDT_LOCATION,
2793 (u8 *)&adapter->ahw->fdt,
2795 qlcnic_swap32_buffer((u32 *)&adapter->ahw->fdt, count);
2796 qlcnic_83xx_unlock_flash(adapter);
2800 int qlcnic_83xx_erase_flash_sector(struct qlcnic_adapter *adapter,
2801 u32 sector_start_addr)
2803 u32 reversed_addr, addr1, addr2, cmd;
2806 if (qlcnic_83xx_lock_flash(adapter) != 0)
2809 if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id) {
2810 ret = qlcnic_83xx_enable_flash_write(adapter);
2812 qlcnic_83xx_unlock_flash(adapter);
2813 dev_err(&adapter->pdev->dev,
2814 "%s failed at %d\n",
2815 __func__, __LINE__);
2820 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2822 qlcnic_83xx_unlock_flash(adapter);
2823 dev_err(&adapter->pdev->dev,
2824 "%s: failed at %d\n", __func__, __LINE__);
2828 addr1 = (sector_start_addr & 0xFF) << 16;
2829 addr2 = (sector_start_addr & 0xFF0000) >> 16;
2830 reversed_addr = addr1 | addr2 | (sector_start_addr & 0xFF00);
2832 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2834 cmd = QLC_83XX_FLASH_FDT_ERASE_DEF_SIG | adapter->ahw->fdt.erase_cmd;
2835 if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id)
2836 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, cmd);
2838 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2839 QLC_83XX_FLASH_OEM_ERASE_SIG);
2840 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2841 QLC_83XX_FLASH_LAST_ERASE_MS_VAL);
2843 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2845 qlcnic_83xx_unlock_flash(adapter);
2846 dev_err(&adapter->pdev->dev,
2847 "%s: failed at %d\n", __func__, __LINE__);
2851 if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id) {
2852 ret = qlcnic_83xx_disable_flash_write(adapter);
2854 qlcnic_83xx_unlock_flash(adapter);
2855 dev_err(&adapter->pdev->dev,
2856 "%s: failed at %d\n", __func__, __LINE__);
2861 qlcnic_83xx_unlock_flash(adapter);
2866 int qlcnic_83xx_flash_write32(struct qlcnic_adapter *adapter, u32 addr,
2870 u32 addr1 = 0x00800000 | (addr >> 2);
2872 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, addr1);
2873 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data);
2874 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2875 QLC_83XX_FLASH_LAST_ERASE_MS_VAL);
2876 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2878 dev_err(&adapter->pdev->dev,
2879 "%s: failed at %d\n", __func__, __LINE__);
2886 int qlcnic_83xx_flash_bulk_write(struct qlcnic_adapter *adapter, u32 addr,
2887 u32 *p_data, int count)
2890 int ret = -EIO, err = 0;
2892 if ((count < QLC_83XX_FLASH_WRITE_MIN) ||
2893 (count > QLC_83XX_FLASH_WRITE_MAX)) {
2894 dev_err(&adapter->pdev->dev,
2895 "%s: Invalid word count\n", __func__);
2899 temp = QLCRD32(adapter, QLC_83XX_FLASH_SPI_CONTROL, &err);
2903 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_SPI_CONTROL,
2904 (temp | QLC_83XX_FLASH_SPI_CTRL));
2905 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2906 QLC_83XX_FLASH_ADDR_TEMP_VAL);
2908 /* First DWORD write */
2909 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data++);
2910 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2911 QLC_83XX_FLASH_FIRST_MS_PATTERN);
2912 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2914 dev_err(&adapter->pdev->dev,
2915 "%s: failed at %d\n", __func__, __LINE__);
2920 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2921 QLC_83XX_FLASH_ADDR_SECOND_TEMP_VAL);
2922 /* Second to N-1 DWORD writes */
2923 while (count != 1) {
2924 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2926 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2927 QLC_83XX_FLASH_SECOND_MS_PATTERN);
2928 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2930 dev_err(&adapter->pdev->dev,
2931 "%s: failed at %d\n", __func__, __LINE__);
2937 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2938 QLC_83XX_FLASH_ADDR_TEMP_VAL |
2940 /* Last DWORD write */
2941 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data++);
2942 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2943 QLC_83XX_FLASH_LAST_MS_PATTERN);
2944 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2946 dev_err(&adapter->pdev->dev,
2947 "%s: failed at %d\n", __func__, __LINE__);
2951 ret = QLCRD32(adapter, QLC_83XX_FLASH_SPI_STATUS, &err);
2955 if ((ret & QLC_83XX_FLASH_SPI_CTRL) == QLC_83XX_FLASH_SPI_CTRL) {
2956 dev_err(&adapter->pdev->dev, "%s: failed at %d\n",
2957 __func__, __LINE__);
2958 /* Operation failed, clear error bit */
2959 temp = QLCRD32(adapter, QLC_83XX_FLASH_SPI_CONTROL, &err);
2963 qlcnic_83xx_wrt_reg_indirect(adapter,
2964 QLC_83XX_FLASH_SPI_CONTROL,
2965 (temp | QLC_83XX_FLASH_SPI_CTRL));
2971 static void qlcnic_83xx_recover_driver_lock(struct qlcnic_adapter *adapter)
2975 val = QLCRDX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK);
2977 /* Check if recovery need to be performed by the calling function */
2978 if ((val & QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK) == 0) {
2980 val = val | ((adapter->portnum << 2) |
2981 QLC_83XX_NEED_DRV_LOCK_RECOVERY);
2982 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val);
2983 dev_info(&adapter->pdev->dev,
2984 "%s: lock recovery initiated\n", __func__);
2985 msleep(QLC_83XX_DRV_LOCK_RECOVERY_DELAY);
2986 val = QLCRDX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK);
2987 id = ((val >> 2) & 0xF);
2988 if (id == adapter->portnum) {
2989 val = val & ~QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK;
2990 val = val | QLC_83XX_DRV_LOCK_RECOVERY_IN_PROGRESS;
2991 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val);
2992 /* Force release the lock */
2993 QLCRDX(adapter->ahw, QLC_83XX_DRV_UNLOCK);
2994 /* Clear recovery bits */
2996 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val);
2997 dev_info(&adapter->pdev->dev,
2998 "%s: lock recovery completed\n", __func__);
3000 dev_info(&adapter->pdev->dev,
3001 "%s: func %d to resume lock recovery process\n",
3005 dev_info(&adapter->pdev->dev,
3006 "%s: lock recovery initiated by other functions\n",
3011 int qlcnic_83xx_lock_driver(struct qlcnic_adapter *adapter)
3013 u32 lock_alive_counter, val, id, i = 0, status = 0, temp = 0;
3014 int max_attempt = 0;
3016 while (status == 0) {
3017 status = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK);
3021 msleep(QLC_83XX_DRV_LOCK_WAIT_DELAY);
3025 temp = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
3027 if (i == QLC_83XX_DRV_LOCK_WAIT_COUNTER) {
3028 val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
3031 dev_info(&adapter->pdev->dev,
3032 "%s: lock to be recovered from %d\n",
3034 qlcnic_83xx_recover_driver_lock(adapter);
3038 dev_err(&adapter->pdev->dev,
3039 "%s: failed to get lock\n", __func__);
3044 /* Force exit from while loop after few attempts */
3045 if (max_attempt == QLC_83XX_MAX_DRV_LOCK_RECOVERY_ATTEMPT) {
3046 dev_err(&adapter->pdev->dev,
3047 "%s: failed to get lock\n", __func__);
3052 val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
3053 lock_alive_counter = val >> 8;
3054 lock_alive_counter++;
3055 val = lock_alive_counter << 8 | adapter->portnum;
3056 QLCWRX(adapter->ahw, QLC_83XX_DRV_LOCK_ID, val);
3061 void qlcnic_83xx_unlock_driver(struct qlcnic_adapter *adapter)
3063 u32 val, lock_alive_counter, id;
3065 val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
3067 lock_alive_counter = val >> 8;
3069 if (id != adapter->portnum)
3070 dev_err(&adapter->pdev->dev,
3071 "%s:Warning func %d is unlocking lock owned by %d\n",
3072 __func__, adapter->portnum, id);
3074 val = (lock_alive_counter << 8) | 0xFF;
3075 QLCWRX(adapter->ahw, QLC_83XX_DRV_LOCK_ID, val);
3076 QLCRDX(adapter->ahw, QLC_83XX_DRV_UNLOCK);
3079 int qlcnic_ms_mem_write128(struct qlcnic_adapter *adapter, u64 addr,
3080 u32 *data, u32 count)
3085 /* Check alignment */
3089 mutex_lock(&adapter->ahw->mem_lock);
3090 qlcnic_ind_wr(adapter, QLCNIC_MS_ADDR_HI, 0);
3092 for (i = 0; i < count; i++, addr += 16) {
3093 if (!((ADDR_IN_RANGE(addr, QLCNIC_ADDR_QDR_NET,
3094 QLCNIC_ADDR_QDR_NET_MAX)) ||
3095 (ADDR_IN_RANGE(addr, QLCNIC_ADDR_DDR_NET,
3096 QLCNIC_ADDR_DDR_NET_MAX)))) {
3097 mutex_unlock(&adapter->ahw->mem_lock);
3101 qlcnic_ind_wr(adapter, QLCNIC_MS_ADDR_LO, addr);
3102 qlcnic_ind_wr(adapter, QLCNIC_MS_WRTDATA_LO, *data++);
3103 qlcnic_ind_wr(adapter, QLCNIC_MS_WRTDATA_HI, *data++);
3104 qlcnic_ind_wr(adapter, QLCNIC_MS_WRTDATA_ULO, *data++);
3105 qlcnic_ind_wr(adapter, QLCNIC_MS_WRTDATA_UHI, *data++);
3106 qlcnic_ind_wr(adapter, QLCNIC_MS_CTRL, QLCNIC_TA_WRITE_ENABLE);
3107 qlcnic_ind_wr(adapter, QLCNIC_MS_CTRL, QLCNIC_TA_WRITE_START);
3109 for (j = 0; j < MAX_CTL_CHECK; j++) {
3110 temp = qlcnic_ind_rd(adapter, QLCNIC_MS_CTRL);
3112 if ((temp & TA_CTL_BUSY) == 0)
3116 /* Status check failure */
3117 if (j >= MAX_CTL_CHECK) {
3118 printk_ratelimited(KERN_WARNING
3119 "MS memory write failed\n");
3120 mutex_unlock(&adapter->ahw->mem_lock);
3125 mutex_unlock(&adapter->ahw->mem_lock);
3130 int qlcnic_83xx_flash_read32(struct qlcnic_adapter *adapter, u32 flash_addr,
3131 u8 *p_data, int count)
3133 u32 word, addr = flash_addr, ret;
3134 ulong indirect_addr;
3137 if (qlcnic_83xx_lock_flash(adapter) != 0)
3141 dev_err(&adapter->pdev->dev, "Illegal addr = 0x%x\n", addr);
3142 qlcnic_83xx_unlock_flash(adapter);
3146 for (i = 0; i < count; i++) {
3147 if (qlcnic_83xx_wrt_reg_indirect(adapter,
3148 QLC_83XX_FLASH_DIRECT_WINDOW,
3150 qlcnic_83xx_unlock_flash(adapter);
3154 indirect_addr = QLC_83XX_FLASH_DIRECT_DATA(addr);
3155 ret = QLCRD32(adapter, indirect_addr, &err);
3160 *(u32 *)p_data = word;
3161 p_data = p_data + 4;
3165 qlcnic_83xx_unlock_flash(adapter);
3170 int qlcnic_83xx_test_link(struct qlcnic_adapter *adapter)
3174 u32 config = 0, state;
3175 struct qlcnic_cmd_args cmd;
3176 struct qlcnic_hardware_context *ahw = adapter->ahw;
3178 if (qlcnic_sriov_vf_check(adapter))
3179 pci_func = adapter->portnum;
3181 pci_func = ahw->pci_func;
3183 state = readl(ahw->pci_base0 + QLC_83XX_LINK_STATE(pci_func));
3184 if (!QLC_83xx_FUNC_VAL(state, pci_func)) {
3185 dev_info(&adapter->pdev->dev, "link state down\n");
3189 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_LINK_STATUS);
3193 err = qlcnic_issue_cmd(adapter, &cmd);
3195 dev_info(&adapter->pdev->dev,
3196 "Get Link Status Command failed: 0x%x\n", err);
3199 config = cmd.rsp.arg[1];
3200 switch (QLC_83XX_CURRENT_LINK_SPEED(config)) {
3201 case QLC_83XX_10M_LINK:
3202 ahw->link_speed = SPEED_10;
3204 case QLC_83XX_100M_LINK:
3205 ahw->link_speed = SPEED_100;
3207 case QLC_83XX_1G_LINK:
3208 ahw->link_speed = SPEED_1000;
3210 case QLC_83XX_10G_LINK:
3211 ahw->link_speed = SPEED_10000;
3214 ahw->link_speed = 0;
3217 config = cmd.rsp.arg[3];
3218 switch (QLC_83XX_SFP_MODULE_TYPE(config)) {
3219 case QLC_83XX_MODULE_FIBRE_10GBASE_LRM:
3220 case QLC_83XX_MODULE_FIBRE_10GBASE_LR:
3221 case QLC_83XX_MODULE_FIBRE_10GBASE_SR:
3222 ahw->supported_type = PORT_FIBRE;
3223 ahw->port_type = QLCNIC_XGBE;
3225 case QLC_83XX_MODULE_FIBRE_1000BASE_SX:
3226 case QLC_83XX_MODULE_FIBRE_1000BASE_LX:
3227 case QLC_83XX_MODULE_FIBRE_1000BASE_CX:
3228 ahw->supported_type = PORT_FIBRE;
3229 ahw->port_type = QLCNIC_GBE;
3231 case QLC_83XX_MODULE_TP_1000BASE_T:
3232 ahw->supported_type = PORT_TP;
3233 ahw->port_type = QLCNIC_GBE;
3235 case QLC_83XX_MODULE_DA_10GE_PASSIVE_CP:
3236 case QLC_83XX_MODULE_DA_10GE_ACTIVE_CP:
3237 case QLC_83XX_MODULE_DA_10GE_LEGACY_CP:
3238 case QLC_83XX_MODULE_DA_1GE_PASSIVE_CP:
3239 ahw->supported_type = PORT_DA;
3240 ahw->port_type = QLCNIC_XGBE;
3243 ahw->supported_type = PORT_OTHER;
3244 ahw->port_type = QLCNIC_XGBE;
3250 qlcnic_free_mbx_args(&cmd);
3254 int qlcnic_83xx_get_settings(struct qlcnic_adapter *adapter,
3255 struct ethtool_cmd *ecmd)
3257 struct qlcnic_hardware_context *ahw = adapter->ahw;
3261 if (!test_bit(__QLCNIC_MAINTENANCE_MODE, &adapter->state)) {
3262 /* Get port configuration info */
3263 status = qlcnic_83xx_get_port_info(adapter);
3264 /* Get Link Status related info */
3265 config = qlcnic_83xx_test_link(adapter);
3266 ahw->module_type = QLC_83XX_SFP_MODULE_TYPE(config);
3269 /* hard code until there is a way to get it from flash */
3270 ahw->board_type = QLCNIC_BRDTYPE_83XX_10G;
3272 if (netif_running(adapter->netdev) && ahw->has_link_events) {
3273 ethtool_cmd_speed_set(ecmd, ahw->link_speed);
3274 ecmd->duplex = ahw->link_duplex;
3275 ecmd->autoneg = ahw->link_autoneg;
3277 ethtool_cmd_speed_set(ecmd, SPEED_UNKNOWN);
3278 ecmd->duplex = DUPLEX_UNKNOWN;
3279 ecmd->autoneg = AUTONEG_DISABLE;
3282 ecmd->supported = (SUPPORTED_10baseT_Full |
3283 SUPPORTED_100baseT_Full |
3284 SUPPORTED_1000baseT_Full |
3285 SUPPORTED_10000baseT_Full |
3288 if (ecmd->autoneg == AUTONEG_ENABLE) {
3289 if (ahw->port_config & QLC_83XX_10_CAPABLE)
3290 ecmd->advertising |= SUPPORTED_10baseT_Full;
3291 if (ahw->port_config & QLC_83XX_100_CAPABLE)
3292 ecmd->advertising |= SUPPORTED_100baseT_Full;
3293 if (ahw->port_config & QLC_83XX_1G_CAPABLE)
3294 ecmd->advertising |= SUPPORTED_1000baseT_Full;
3295 if (ahw->port_config & QLC_83XX_10G_CAPABLE)
3296 ecmd->advertising |= SUPPORTED_10000baseT_Full;
3297 if (ahw->port_config & QLC_83XX_AUTONEG_ENABLE)
3298 ecmd->advertising |= ADVERTISED_Autoneg;
3300 switch (ahw->link_speed) {
3302 ecmd->advertising = SUPPORTED_10baseT_Full;
3305 ecmd->advertising = SUPPORTED_100baseT_Full;
3308 ecmd->advertising = SUPPORTED_1000baseT_Full;
3311 ecmd->advertising = SUPPORTED_10000baseT_Full;
3319 switch (ahw->supported_type) {
3321 ecmd->supported |= SUPPORTED_FIBRE;
3322 ecmd->advertising |= ADVERTISED_FIBRE;
3323 ecmd->port = PORT_FIBRE;
3324 ecmd->transceiver = XCVR_EXTERNAL;
3327 ecmd->supported |= SUPPORTED_TP;
3328 ecmd->advertising |= ADVERTISED_TP;
3329 ecmd->port = PORT_TP;
3330 ecmd->transceiver = XCVR_INTERNAL;
3333 ecmd->supported |= SUPPORTED_FIBRE;
3334 ecmd->advertising |= ADVERTISED_FIBRE;
3335 ecmd->port = PORT_DA;
3336 ecmd->transceiver = XCVR_EXTERNAL;
3339 ecmd->supported |= SUPPORTED_FIBRE;
3340 ecmd->advertising |= ADVERTISED_FIBRE;
3341 ecmd->port = PORT_OTHER;
3342 ecmd->transceiver = XCVR_EXTERNAL;
3345 ecmd->phy_address = ahw->physical_port;
3349 int qlcnic_83xx_set_settings(struct qlcnic_adapter *adapter,
3350 struct ethtool_cmd *ecmd)
3352 struct qlcnic_hardware_context *ahw = adapter->ahw;
3353 u32 config = adapter->ahw->port_config;
3356 /* 83xx devices do not support Half duplex */
3357 if (ecmd->duplex == DUPLEX_HALF) {
3358 netdev_info(adapter->netdev,
3359 "Half duplex mode not supported\n");
3363 if (ecmd->autoneg) {
3364 ahw->port_config |= QLC_83XX_AUTONEG_ENABLE;
3365 ahw->port_config |= (QLC_83XX_100_CAPABLE |
3366 QLC_83XX_1G_CAPABLE |
3367 QLC_83XX_10G_CAPABLE);
3368 } else { /* force speed */
3369 ahw->port_config &= ~QLC_83XX_AUTONEG_ENABLE;
3370 switch (ethtool_cmd_speed(ecmd)) {
3372 ahw->port_config &= ~(QLC_83XX_100_CAPABLE |
3373 QLC_83XX_1G_CAPABLE |
3374 QLC_83XX_10G_CAPABLE);
3375 ahw->port_config |= QLC_83XX_10_CAPABLE;
3378 ahw->port_config &= ~(QLC_83XX_10_CAPABLE |
3379 QLC_83XX_1G_CAPABLE |
3380 QLC_83XX_10G_CAPABLE);
3381 ahw->port_config |= QLC_83XX_100_CAPABLE;
3384 ahw->port_config &= ~(QLC_83XX_10_CAPABLE |
3385 QLC_83XX_100_CAPABLE |
3386 QLC_83XX_10G_CAPABLE);
3387 ahw->port_config |= QLC_83XX_1G_CAPABLE;
3390 ahw->port_config &= ~(QLC_83XX_10_CAPABLE |
3391 QLC_83XX_100_CAPABLE |
3392 QLC_83XX_1G_CAPABLE);
3393 ahw->port_config |= QLC_83XX_10G_CAPABLE;
3399 status = qlcnic_83xx_set_port_config(adapter);
3401 netdev_info(adapter->netdev,
3402 "Failed to Set Link Speed and autoneg.\n");
3403 ahw->port_config = config;
3409 static inline u64 *qlcnic_83xx_copy_stats(struct qlcnic_cmd_args *cmd,
3410 u64 *data, int index)
3415 low = cmd->rsp.arg[index];
3416 hi = cmd->rsp.arg[index + 1];
3417 val = (((u64) low) | (((u64) hi) << 32));
3422 static u64 *qlcnic_83xx_fill_stats(struct qlcnic_adapter *adapter,
3423 struct qlcnic_cmd_args *cmd, u64 *data,
3426 int err, k, total_regs;
3429 err = qlcnic_issue_cmd(adapter, cmd);
3430 if (err != QLCNIC_RCODE_SUCCESS) {
3431 dev_info(&adapter->pdev->dev,
3432 "Error in get statistics mailbox command\n");
3436 total_regs = cmd->rsp.num;
3438 case QLC_83XX_STAT_MAC:
3439 /* fill in MAC tx counters */
3440 for (k = 2; k < 28; k += 2)
3441 data = qlcnic_83xx_copy_stats(cmd, data, k);
3442 /* skip 24 bytes of reserved area */
3443 /* fill in MAC rx counters */
3444 for (k += 6; k < 60; k += 2)
3445 data = qlcnic_83xx_copy_stats(cmd, data, k);
3446 /* skip 24 bytes of reserved area */
3447 /* fill in MAC rx frame stats */
3448 for (k += 6; k < 80; k += 2)
3449 data = qlcnic_83xx_copy_stats(cmd, data, k);
3450 /* fill in eSwitch stats */
3451 for (; k < total_regs; k += 2)
3452 data = qlcnic_83xx_copy_stats(cmd, data, k);
3454 case QLC_83XX_STAT_RX:
3455 for (k = 2; k < 8; k += 2)
3456 data = qlcnic_83xx_copy_stats(cmd, data, k);
3457 /* skip 8 bytes of reserved data */
3458 for (k += 2; k < 24; k += 2)
3459 data = qlcnic_83xx_copy_stats(cmd, data, k);
3460 /* skip 8 bytes containing RE1FBQ error data */
3461 for (k += 2; k < total_regs; k += 2)
3462 data = qlcnic_83xx_copy_stats(cmd, data, k);
3464 case QLC_83XX_STAT_TX:
3465 for (k = 2; k < 10; k += 2)
3466 data = qlcnic_83xx_copy_stats(cmd, data, k);
3467 /* skip 8 bytes of reserved data */
3468 for (k += 2; k < total_regs; k += 2)
3469 data = qlcnic_83xx_copy_stats(cmd, data, k);
3472 dev_warn(&adapter->pdev->dev, "Unknown get statistics mode\n");
3478 void qlcnic_83xx_get_stats(struct qlcnic_adapter *adapter, u64 *data)
3480 struct qlcnic_cmd_args cmd;
3481 struct net_device *netdev = adapter->netdev;
3484 ret = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_STATISTICS);
3488 cmd.req.arg[1] = BIT_1 | (adapter->tx_ring->ctx_id << 16);
3489 cmd.rsp.num = QLC_83XX_TX_STAT_REGS;
3490 data = qlcnic_83xx_fill_stats(adapter, &cmd, data,
3491 QLC_83XX_STAT_TX, &ret);
3493 netdev_err(netdev, "Error getting Tx stats\n");
3497 cmd.req.arg[1] = BIT_2 | (adapter->portnum << 16);
3498 cmd.rsp.num = QLC_83XX_MAC_STAT_REGS;
3499 memset(cmd.rsp.arg, 0, sizeof(u32) * cmd.rsp.num);
3500 data = qlcnic_83xx_fill_stats(adapter, &cmd, data,
3501 QLC_83XX_STAT_MAC, &ret);
3503 netdev_err(netdev, "Error getting MAC stats\n");
3507 cmd.req.arg[1] = adapter->recv_ctx->context_id << 16;
3508 cmd.rsp.num = QLC_83XX_RX_STAT_REGS;
3509 memset(cmd.rsp.arg, 0, sizeof(u32) * cmd.rsp.num);
3510 data = qlcnic_83xx_fill_stats(adapter, &cmd, data,
3511 QLC_83XX_STAT_RX, &ret);
3513 netdev_err(netdev, "Error getting Rx stats\n");
3515 qlcnic_free_mbx_args(&cmd);
3518 #define QLCNIC_83XX_ADD_PORT0 BIT_0
3519 #define QLCNIC_83XX_ADD_PORT1 BIT_1
3520 #define QLCNIC_83XX_EXTENDED_MEM_SIZE 13 /* In MB */
3521 int qlcnic_83xx_extend_md_capab(struct qlcnic_adapter *adapter)
3523 struct qlcnic_cmd_args cmd;
3526 err = qlcnic_alloc_mbx_args(&cmd, adapter,
3527 QLCNIC_CMD_83XX_EXTEND_ISCSI_DUMP_CAP);
3531 cmd.req.arg[1] = (QLCNIC_83XX_ADD_PORT0 | QLCNIC_83XX_ADD_PORT1);
3532 cmd.req.arg[2] = QLCNIC_83XX_EXTENDED_MEM_SIZE;
3533 cmd.req.arg[3] = QLCNIC_83XX_EXTENDED_MEM_SIZE;
3535 err = qlcnic_issue_cmd(adapter, &cmd);
3537 dev_err(&adapter->pdev->dev,
3538 "failed to issue extend iSCSI minidump capability\n");
3543 int qlcnic_83xx_reg_test(struct qlcnic_adapter *adapter)
3545 u32 major, minor, sub;
3547 major = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MAJOR);
3548 minor = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MINOR);
3549 sub = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_SUB);
3551 if (adapter->fw_version != QLCNIC_VERSION_CODE(major, minor, sub)) {
3552 dev_info(&adapter->pdev->dev, "%s: Reg test failed\n",
3559 inline int qlcnic_83xx_get_regs_len(struct qlcnic_adapter *adapter)
3561 return (ARRAY_SIZE(qlcnic_83xx_ext_reg_tbl) *
3562 sizeof(*adapter->ahw->ext_reg_tbl)) +
3563 (ARRAY_SIZE(qlcnic_83xx_reg_tbl) *
3564 sizeof(*adapter->ahw->reg_tbl));
3567 int qlcnic_83xx_get_registers(struct qlcnic_adapter *adapter, u32 *regs_buff)
3571 for (i = QLCNIC_DEV_INFO_SIZE + 1;
3572 j < ARRAY_SIZE(qlcnic_83xx_reg_tbl); i++, j++)
3573 regs_buff[i] = QLC_SHARED_REG_RD32(adapter, j);
3575 for (j = 0; j < ARRAY_SIZE(qlcnic_83xx_ext_reg_tbl); j++)
3576 regs_buff[i++] = QLCRDX(adapter->ahw, j);
3580 int qlcnic_83xx_interrupt_test(struct net_device *netdev)
3582 struct qlcnic_adapter *adapter = netdev_priv(netdev);
3583 struct qlcnic_hardware_context *ahw = adapter->ahw;
3584 struct qlcnic_cmd_args cmd;
3585 u8 val, drv_sds_rings = adapter->drv_sds_rings;
3586 u8 drv_tx_rings = adapter->drv_tx_rings;
3591 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
3592 netdev_info(netdev, "Device is resetting\n");
3596 if (qlcnic_get_diag_lock(adapter)) {
3597 netdev_info(netdev, "Device in diagnostics mode\n");
3601 ret = qlcnic_83xx_diag_alloc_res(netdev, QLCNIC_INTERRUPT_TEST,
3607 ret = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_INTRPT_TEST);
3611 if (adapter->flags & QLCNIC_MSIX_ENABLED)
3612 intrpt_id = ahw->intr_tbl[0].id;
3614 intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
3617 cmd.req.arg[2] = intrpt_id;
3618 cmd.req.arg[3] = BIT_0;
3620 ret = qlcnic_issue_cmd(adapter, &cmd);
3621 data = cmd.rsp.arg[2];
3623 val = LSB(MSW(data));
3624 if (id != intrpt_id)
3625 dev_info(&adapter->pdev->dev,
3626 "Interrupt generated: 0x%x, requested:0x%x\n",
3629 dev_err(&adapter->pdev->dev,
3630 "Interrupt test error: 0x%x\n", val);
3635 ret = !ahw->diag_cnt;
3638 qlcnic_free_mbx_args(&cmd);
3639 qlcnic_83xx_diag_free_res(netdev, drv_sds_rings);
3642 adapter->drv_sds_rings = drv_sds_rings;
3643 adapter->drv_tx_rings = drv_tx_rings;
3644 qlcnic_release_diag_lock(adapter);
3648 void qlcnic_83xx_get_pauseparam(struct qlcnic_adapter *adapter,
3649 struct ethtool_pauseparam *pause)
3651 struct qlcnic_hardware_context *ahw = adapter->ahw;
3655 status = qlcnic_83xx_get_port_config(adapter);
3657 dev_err(&adapter->pdev->dev,
3658 "%s: Get Pause Config failed\n", __func__);
3661 config = ahw->port_config;
3662 if (config & QLC_83XX_CFG_STD_PAUSE) {
3663 switch (MSW(config)) {
3664 case QLC_83XX_TX_PAUSE:
3665 pause->tx_pause = 1;
3667 case QLC_83XX_RX_PAUSE:
3668 pause->rx_pause = 1;
3670 case QLC_83XX_TX_RX_PAUSE:
3672 /* Backward compatibility for existing
3675 pause->tx_pause = 1;
3676 pause->rx_pause = 1;
3680 if (QLC_83XX_AUTONEG(config))
3684 int qlcnic_83xx_set_pauseparam(struct qlcnic_adapter *adapter,
3685 struct ethtool_pauseparam *pause)
3687 struct qlcnic_hardware_context *ahw = adapter->ahw;
3691 status = qlcnic_83xx_get_port_config(adapter);
3693 dev_err(&adapter->pdev->dev,
3694 "%s: Get Pause Config failed.\n", __func__);
3697 config = ahw->port_config;
3699 if (ahw->port_type == QLCNIC_GBE) {
3701 ahw->port_config |= QLC_83XX_ENABLE_AUTONEG;
3702 if (!pause->autoneg)
3703 ahw->port_config &= ~QLC_83XX_ENABLE_AUTONEG;
3704 } else if ((ahw->port_type == QLCNIC_XGBE) && (pause->autoneg)) {
3708 if (!(config & QLC_83XX_CFG_STD_PAUSE))
3709 ahw->port_config |= QLC_83XX_CFG_STD_PAUSE;
3711 if (pause->rx_pause && pause->tx_pause) {
3712 ahw->port_config |= QLC_83XX_CFG_STD_TX_RX_PAUSE;
3713 } else if (pause->rx_pause && !pause->tx_pause) {
3714 ahw->port_config &= ~QLC_83XX_CFG_STD_TX_PAUSE;
3715 ahw->port_config |= QLC_83XX_CFG_STD_RX_PAUSE;
3716 } else if (pause->tx_pause && !pause->rx_pause) {
3717 ahw->port_config &= ~QLC_83XX_CFG_STD_RX_PAUSE;
3718 ahw->port_config |= QLC_83XX_CFG_STD_TX_PAUSE;
3719 } else if (!pause->rx_pause && !pause->tx_pause) {
3720 ahw->port_config &= ~(QLC_83XX_CFG_STD_TX_RX_PAUSE |
3721 QLC_83XX_CFG_STD_PAUSE);
3723 status = qlcnic_83xx_set_port_config(adapter);
3725 dev_err(&adapter->pdev->dev,
3726 "%s: Set Pause Config failed.\n", __func__);
3727 ahw->port_config = config;
3732 static int qlcnic_83xx_read_flash_status_reg(struct qlcnic_adapter *adapter)
3737 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
3738 QLC_83XX_FLASH_OEM_READ_SIG);
3739 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
3740 QLC_83XX_FLASH_READ_CTRL);
3741 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
3745 temp = QLCRD32(adapter, QLC_83XX_FLASH_RDDATA, &err);
3752 int qlcnic_83xx_flash_test(struct qlcnic_adapter *adapter)
3756 status = qlcnic_83xx_read_flash_status_reg(adapter);
3757 if (status == -EIO) {
3758 dev_info(&adapter->pdev->dev, "%s: EEPROM test failed.\n",
3765 static int qlcnic_83xx_shutdown(struct pci_dev *pdev)
3767 struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
3768 struct net_device *netdev = adapter->netdev;
3771 netif_device_detach(netdev);
3772 qlcnic_cancel_idc_work(adapter);
3774 if (netif_running(netdev))
3775 qlcnic_down(adapter, netdev);
3777 qlcnic_83xx_disable_mbx_intr(adapter);
3778 cancel_delayed_work_sync(&adapter->idc_aen_work);
3780 retval = pci_save_state(pdev);
3787 static int qlcnic_83xx_resume(struct qlcnic_adapter *adapter)
3789 struct qlcnic_hardware_context *ahw = adapter->ahw;
3790 struct qlc_83xx_idc *idc = &ahw->idc;
3793 err = qlcnic_83xx_idc_init(adapter);
3797 if (ahw->nic_mode == QLCNIC_VNIC_MODE) {
3798 if (ahw->op_mode == QLCNIC_MGMT_FUNC) {
3799 qlcnic_83xx_set_vnic_opmode(adapter);
3801 err = qlcnic_83xx_check_vnic_state(adapter);
3807 err = qlcnic_83xx_idc_reattach_driver(adapter);
3811 qlcnic_schedule_work(adapter, qlcnic_83xx_idc_poll_dev_state,
3816 void qlcnic_83xx_reinit_mbx_work(struct qlcnic_mailbox *mbx)
3818 reinit_completion(&mbx->completion);
3819 set_bit(QLC_83XX_MBX_READY, &mbx->status);
3822 void qlcnic_83xx_free_mailbox(struct qlcnic_mailbox *mbx)
3827 destroy_workqueue(mbx->work_q);
3832 qlcnic_83xx_notify_cmd_completion(struct qlcnic_adapter *adapter,
3833 struct qlcnic_cmd_args *cmd)
3835 atomic_set(&cmd->rsp_status, QLC_83XX_MBX_RESPONSE_ARRIVED);
3837 if (cmd->type == QLC_83XX_MBX_CMD_NO_WAIT) {
3838 qlcnic_free_mbx_args(cmd);
3842 complete(&cmd->completion);
3845 static void qlcnic_83xx_flush_mbx_queue(struct qlcnic_adapter *adapter)
3847 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3848 struct list_head *head = &mbx->cmd_q;
3849 struct qlcnic_cmd_args *cmd = NULL;
3851 spin_lock(&mbx->queue_lock);
3853 while (!list_empty(head)) {
3854 cmd = list_entry(head->next, struct qlcnic_cmd_args, list);
3855 dev_info(&adapter->pdev->dev, "%s: Mailbox command 0x%x\n",
3856 __func__, cmd->cmd_op);
3857 list_del(&cmd->list);
3859 qlcnic_83xx_notify_cmd_completion(adapter, cmd);
3862 spin_unlock(&mbx->queue_lock);
3865 static int qlcnic_83xx_check_mbx_status(struct qlcnic_adapter *adapter)
3867 struct qlcnic_hardware_context *ahw = adapter->ahw;
3868 struct qlcnic_mailbox *mbx = ahw->mailbox;
3871 if (!test_bit(QLC_83XX_MBX_READY, &mbx->status))
3874 host_mbx_ctrl = QLCRDX(ahw, QLCNIC_HOST_MBX_CTRL);
3875 if (host_mbx_ctrl) {
3876 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
3877 ahw->idc.collect_dump = 1;
3884 static inline void qlcnic_83xx_signal_mbx_cmd(struct qlcnic_adapter *adapter,
3888 QLCWRX(adapter->ahw, QLCNIC_HOST_MBX_CTRL, QLCNIC_SET_OWNER);
3890 QLCWRX(adapter->ahw, QLCNIC_FW_MBX_CTRL, QLCNIC_CLR_OWNER);
3893 static void qlcnic_83xx_dequeue_mbx_cmd(struct qlcnic_adapter *adapter,
3894 struct qlcnic_cmd_args *cmd)
3896 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3898 spin_lock(&mbx->queue_lock);
3900 list_del(&cmd->list);
3903 spin_unlock(&mbx->queue_lock);
3905 qlcnic_83xx_notify_cmd_completion(adapter, cmd);
3908 static void qlcnic_83xx_encode_mbx_cmd(struct qlcnic_adapter *adapter,
3909 struct qlcnic_cmd_args *cmd)
3911 u32 mbx_cmd, fw_hal_version, hdr_size, total_size, tmp;
3912 struct qlcnic_hardware_context *ahw = adapter->ahw;
3915 if (cmd->op_type != QLC_83XX_MBX_POST_BC_OP) {
3916 mbx_cmd = cmd->req.arg[0];
3917 writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 0));
3918 for (i = 1; i < cmd->req.num; i++)
3919 writel(cmd->req.arg[i], QLCNIC_MBX_HOST(ahw, i));
3921 fw_hal_version = ahw->fw_hal_version;
3922 hdr_size = sizeof(struct qlcnic_bc_hdr) / sizeof(u32);
3923 total_size = cmd->pay_size + hdr_size;
3924 tmp = QLCNIC_CMD_BC_EVENT_SETUP | total_size << 16;
3925 mbx_cmd = tmp | fw_hal_version << 29;
3926 writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 0));
3928 /* Back channel specific operations bits */
3929 mbx_cmd = 0x1 | 1 << 4;
3931 if (qlcnic_sriov_pf_check(adapter))
3932 mbx_cmd |= cmd->func_num << 5;
3934 writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 1));
3936 for (i = 2, j = 0; j < hdr_size; i++, j++)
3937 writel(*(cmd->hdr++), QLCNIC_MBX_HOST(ahw, i));
3938 for (j = 0; j < cmd->pay_size; j++, i++)
3939 writel(*(cmd->pay++), QLCNIC_MBX_HOST(ahw, i));
3943 void qlcnic_83xx_detach_mailbox_work(struct qlcnic_adapter *adapter)
3945 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3950 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
3951 complete(&mbx->completion);
3952 cancel_work_sync(&mbx->work);
3953 flush_workqueue(mbx->work_q);
3954 qlcnic_83xx_flush_mbx_queue(adapter);
3957 static int qlcnic_83xx_enqueue_mbx_cmd(struct qlcnic_adapter *adapter,
3958 struct qlcnic_cmd_args *cmd,
3959 unsigned long *timeout)
3961 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3963 if (test_bit(QLC_83XX_MBX_READY, &mbx->status)) {
3964 atomic_set(&cmd->rsp_status, QLC_83XX_MBX_RESPONSE_WAIT);
3965 init_completion(&cmd->completion);
3966 cmd->rsp_opcode = QLC_83XX_MBX_RESPONSE_UNKNOWN;
3968 spin_lock(&mbx->queue_lock);
3970 list_add_tail(&cmd->list, &mbx->cmd_q);
3972 cmd->total_cmds = mbx->num_cmds;
3973 *timeout = cmd->total_cmds * QLC_83XX_MBX_TIMEOUT;
3974 queue_work(mbx->work_q, &mbx->work);
3976 spin_unlock(&mbx->queue_lock);
3984 static int qlcnic_83xx_check_mac_rcode(struct qlcnic_adapter *adapter,
3985 struct qlcnic_cmd_args *cmd)
3990 if (cmd->cmd_op == QLCNIC_CMD_CONFIG_MAC_VLAN) {
3991 fw_data = readl(QLCNIC_MBX_FW(adapter->ahw, 2));
3992 mac_cmd_rcode = (u8)fw_data;
3993 if (mac_cmd_rcode == QLC_83XX_NO_NIC_RESOURCE ||
3994 mac_cmd_rcode == QLC_83XX_MAC_PRESENT ||
3995 mac_cmd_rcode == QLC_83XX_MAC_ABSENT) {
3996 cmd->rsp_opcode = QLCNIC_RCODE_SUCCESS;
3997 return QLCNIC_RCODE_SUCCESS;
4004 static void qlcnic_83xx_decode_mbx_rsp(struct qlcnic_adapter *adapter,
4005 struct qlcnic_cmd_args *cmd)
4007 struct qlcnic_hardware_context *ahw = adapter->ahw;
4008 struct device *dev = &adapter->pdev->dev;
4012 fw_data = readl(QLCNIC_MBX_FW(ahw, 0));
4013 mbx_err_code = QLCNIC_MBX_STATUS(fw_data);
4014 qlcnic_83xx_get_mbx_data(adapter, cmd);
4016 switch (mbx_err_code) {
4017 case QLCNIC_MBX_RSP_OK:
4018 case QLCNIC_MBX_PORT_RSP_OK:
4019 cmd->rsp_opcode = QLCNIC_RCODE_SUCCESS;
4022 if (!qlcnic_83xx_check_mac_rcode(adapter, cmd))
4025 dev_err(dev, "%s: Mailbox command failed, opcode=0x%x, cmd_type=0x%x, func=0x%x, op_mode=0x%x, error=0x%x\n",
4026 __func__, cmd->cmd_op, cmd->type, ahw->pci_func,
4027 ahw->op_mode, mbx_err_code);
4028 cmd->rsp_opcode = QLC_83XX_MBX_RESPONSE_FAILED;
4029 qlcnic_dump_mbx(adapter, cmd);
4035 static inline void qlcnic_dump_mailbox_registers(struct qlcnic_adapter *adapter)
4037 struct qlcnic_hardware_context *ahw = adapter->ahw;
4040 offset = QLCRDX(ahw, QLCNIC_DEF_INT_MASK);
4041 dev_info(&adapter->pdev->dev, "Mbx interrupt mask=0x%x, Mbx interrupt enable=0x%x, Host mbx control=0x%x, Fw mbx control=0x%x",
4042 readl(ahw->pci_base0 + offset),
4043 QLCRDX(ahw, QLCNIC_MBX_INTR_ENBL),
4044 QLCRDX(ahw, QLCNIC_HOST_MBX_CTRL),
4045 QLCRDX(ahw, QLCNIC_FW_MBX_CTRL));
4048 static void qlcnic_83xx_mailbox_worker(struct work_struct *work)
4050 struct qlcnic_mailbox *mbx = container_of(work, struct qlcnic_mailbox,
4052 struct qlcnic_adapter *adapter = mbx->adapter;
4053 struct qlcnic_mbx_ops *mbx_ops = mbx->ops;
4054 struct device *dev = &adapter->pdev->dev;
4055 atomic_t *rsp_status = &mbx->rsp_status;
4056 struct list_head *head = &mbx->cmd_q;
4057 struct qlcnic_hardware_context *ahw;
4058 struct qlcnic_cmd_args *cmd = NULL;
4063 if (qlcnic_83xx_check_mbx_status(adapter)) {
4064 qlcnic_83xx_flush_mbx_queue(adapter);
4068 atomic_set(rsp_status, QLC_83XX_MBX_RESPONSE_WAIT);
4070 spin_lock(&mbx->queue_lock);
4072 if (list_empty(head)) {
4073 spin_unlock(&mbx->queue_lock);
4076 cmd = list_entry(head->next, struct qlcnic_cmd_args, list);
4078 spin_unlock(&mbx->queue_lock);
4080 mbx_ops->encode_cmd(adapter, cmd);
4081 mbx_ops->nofity_fw(adapter, QLC_83XX_MBX_REQUEST);
4083 if (wait_for_completion_timeout(&mbx->completion,
4084 QLC_83XX_MBX_TIMEOUT)) {
4085 mbx_ops->decode_resp(adapter, cmd);
4086 mbx_ops->nofity_fw(adapter, QLC_83XX_MBX_COMPLETION);
4088 dev_err(dev, "%s: Mailbox command timeout, opcode=0x%x, cmd_type=0x%x, func=0x%x, op_mode=0x%x\n",
4089 __func__, cmd->cmd_op, cmd->type, ahw->pci_func,
4091 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
4092 qlcnic_dump_mailbox_registers(adapter);
4093 qlcnic_83xx_get_mbx_data(adapter, cmd);
4094 qlcnic_dump_mbx(adapter, cmd);
4095 qlcnic_83xx_idc_request_reset(adapter,
4096 QLCNIC_FORCE_FW_DUMP_KEY);
4097 cmd->rsp_opcode = QLCNIC_RCODE_TIMEOUT;
4099 mbx_ops->dequeue_cmd(adapter, cmd);
4103 static struct qlcnic_mbx_ops qlcnic_83xx_mbx_ops = {
4104 .enqueue_cmd = qlcnic_83xx_enqueue_mbx_cmd,
4105 .dequeue_cmd = qlcnic_83xx_dequeue_mbx_cmd,
4106 .decode_resp = qlcnic_83xx_decode_mbx_rsp,
4107 .encode_cmd = qlcnic_83xx_encode_mbx_cmd,
4108 .nofity_fw = qlcnic_83xx_signal_mbx_cmd,
4111 int qlcnic_83xx_init_mailbox_work(struct qlcnic_adapter *adapter)
4113 struct qlcnic_hardware_context *ahw = adapter->ahw;
4114 struct qlcnic_mailbox *mbx;
4116 ahw->mailbox = kzalloc(sizeof(*mbx), GFP_KERNEL);
4121 mbx->ops = &qlcnic_83xx_mbx_ops;
4122 mbx->adapter = adapter;
4124 spin_lock_init(&mbx->queue_lock);
4125 spin_lock_init(&mbx->aen_lock);
4126 INIT_LIST_HEAD(&mbx->cmd_q);
4127 init_completion(&mbx->completion);
4129 mbx->work_q = create_singlethread_workqueue("qlcnic_mailbox");
4130 if (mbx->work_q == NULL) {
4135 INIT_WORK(&mbx->work, qlcnic_83xx_mailbox_worker);
4136 set_bit(QLC_83XX_MBX_READY, &mbx->status);
4140 static pci_ers_result_t qlcnic_83xx_io_error_detected(struct pci_dev *pdev,
4141 pci_channel_state_t state)
4143 struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
4145 if (state == pci_channel_io_perm_failure)
4146 return PCI_ERS_RESULT_DISCONNECT;
4148 if (state == pci_channel_io_normal)
4149 return PCI_ERS_RESULT_RECOVERED;
4151 set_bit(__QLCNIC_AER, &adapter->state);
4152 set_bit(__QLCNIC_RESETTING, &adapter->state);
4154 qlcnic_83xx_aer_stop_poll_work(adapter);
4156 pci_save_state(pdev);
4157 pci_disable_device(pdev);
4159 return PCI_ERS_RESULT_NEED_RESET;
4162 static pci_ers_result_t qlcnic_83xx_io_slot_reset(struct pci_dev *pdev)
4164 struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
4167 pdev->error_state = pci_channel_io_normal;
4168 err = pci_enable_device(pdev);
4172 pci_set_power_state(pdev, PCI_D0);
4173 pci_set_master(pdev);
4174 pci_restore_state(pdev);
4176 err = qlcnic_83xx_aer_reset(adapter);
4178 return PCI_ERS_RESULT_RECOVERED;
4180 clear_bit(__QLCNIC_AER, &adapter->state);
4181 clear_bit(__QLCNIC_RESETTING, &adapter->state);
4182 return PCI_ERS_RESULT_DISCONNECT;
4185 static void qlcnic_83xx_io_resume(struct pci_dev *pdev)
4187 struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
4189 pci_cleanup_aer_uncorrect_error_status(pdev);
4190 if (test_and_clear_bit(__QLCNIC_AER, &adapter->state))
4191 qlcnic_83xx_aer_start_poll_work(adapter);