drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c

   1 /*
   2  * QLogic qlcnic NIC Driver
   3  * Copyright (c) 2009-2013 QLogic Corporation
   4  *
   5  * See LICENSE.qlcnic for copyright and licensing details.
   6  */
   7
   8 #include <linux/if_vlan.h>
   9 #include <linux/ipv6.h>
  10 #include <linux/ethtool.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/aer.h>
  13
  14 #include "qlcnic.h"
  15 #include "qlcnic_sriov.h"
  16
  17 static void __qlcnic_83xx_process_aen(struct qlcnic_adapter *);
  18 static int qlcnic_83xx_clear_lb_mode(struct qlcnic_adapter *, u8);
  19 static void qlcnic_83xx_configure_mac(struct qlcnic_adapter *, u8 *, u8,
  20                                       struct qlcnic_cmd_args *);
  21 static int qlcnic_83xx_get_port_config(struct qlcnic_adapter *);
  22 static irqreturn_t qlcnic_83xx_handle_aen(int, void *);
  23 static pci_ers_result_t qlcnic_83xx_io_error_detected(struct pci_dev *,
  24                                                       pci_channel_state_t);
  25 static int qlcnic_83xx_set_port_config(struct qlcnic_adapter *);
  26 static pci_ers_result_t qlcnic_83xx_io_slot_reset(struct pci_dev *);
  27 static void qlcnic_83xx_io_resume(struct pci_dev *);
  28 static int qlcnic_83xx_set_lb_mode(struct qlcnic_adapter *, u8);
  29 static void qlcnic_83xx_set_mac_filter_count(struct qlcnic_adapter *);
  30 static int qlcnic_83xx_resume(struct qlcnic_adapter *);
  31 static int qlcnic_83xx_shutdown(struct pci_dev *);
  32 static void qlcnic_83xx_get_beacon_state(struct qlcnic_adapter *);
  33
  34 #define RSS_HASHTYPE_IP_TCP             0x3
  35 #define QLC_83XX_FW_MBX_CMD             0
  36 #define QLC_SKIP_INACTIVE_PCI_REGS      7
  37 #define QLC_MAX_LEGACY_FUNC_SUPP        8
  38
  39 /* 83xx Module type */
  40 #define QLC_83XX_MODULE_FIBRE_10GBASE_LRM       0x1 /* 10GBase-LRM */
  41 #define QLC_83XX_MODULE_FIBRE_10GBASE_LR        0x2 /* 10GBase-LR */
  42 #define QLC_83XX_MODULE_FIBRE_10GBASE_SR        0x3 /* 10GBase-SR */
  43 #define QLC_83XX_MODULE_DA_10GE_PASSIVE_CP      0x4 /* 10GE passive
  44                                                      * copper(compliant)
  45                                                      */
  46 #define QLC_83XX_MODULE_DA_10GE_ACTIVE_CP       0x5 /* 10GE active limiting
  47                                                      * copper(compliant)
  48                                                      */
  49 #define QLC_83XX_MODULE_DA_10GE_LEGACY_CP       0x6 /* 10GE passive copper
  50                                                      * (legacy, best effort)
  51                                                      */
  52 #define QLC_83XX_MODULE_FIBRE_1000BASE_SX       0x7 /* 1000Base-SX */
  53 #define QLC_83XX_MODULE_FIBRE_1000BASE_LX       0x8 /* 1000Base-LX */
  54 #define QLC_83XX_MODULE_FIBRE_1000BASE_CX       0x9 /* 1000Base-CX */
  55 #define QLC_83XX_MODULE_TP_1000BASE_T           0xa /* 1000Base-T*/
  56 #define QLC_83XX_MODULE_DA_1GE_PASSIVE_CP       0xb /* 1GE passive copper
  57                                                      * (legacy, best effort)
  58                                                      */
  59 #define QLC_83XX_MODULE_UNKNOWN                 0xf /* Unknown module type */
  60
  61 /* Port types */
  62 #define QLC_83XX_10_CAPABLE      BIT_8
  63 #define QLC_83XX_100_CAPABLE     BIT_9
  64 #define QLC_83XX_1G_CAPABLE      BIT_10
  65 #define QLC_83XX_10G_CAPABLE     BIT_11
  66 #define QLC_83XX_AUTONEG_ENABLE  BIT_15
  67
  68 static const struct qlcnic_mailbox_metadata qlcnic_83xx_mbx_tbl[] = {
  69         {QLCNIC_CMD_CONFIGURE_IP_ADDR, 6, 1},
  70         {QLCNIC_CMD_CONFIG_INTRPT, 18, 34},
  71         {QLCNIC_CMD_CREATE_RX_CTX, 136, 27},
  72         {QLCNIC_CMD_DESTROY_RX_CTX, 2, 1},
  73         {QLCNIC_CMD_CREATE_TX_CTX, 54, 18},
  74         {QLCNIC_CMD_DESTROY_TX_CTX, 2, 1},
  75         {QLCNIC_CMD_CONFIGURE_MAC_LEARNING, 2, 1},
  76         {QLCNIC_CMD_INTRPT_TEST, 22, 12},
  77         {QLCNIC_CMD_SET_MTU, 3, 1},
  78         {QLCNIC_CMD_READ_PHY, 4, 2},
  79         {QLCNIC_CMD_WRITE_PHY, 5, 1},
  80         {QLCNIC_CMD_READ_HW_REG, 4, 1},
  81         {QLCNIC_CMD_GET_FLOW_CTL, 4, 2},
  82         {QLCNIC_CMD_SET_FLOW_CTL, 4, 1},
  83         {QLCNIC_CMD_READ_MAX_MTU, 4, 2},
  84         {QLCNIC_CMD_READ_MAX_LRO, 4, 2},
  85         {QLCNIC_CMD_MAC_ADDRESS, 4, 3},
  86         {QLCNIC_CMD_GET_PCI_INFO, 1, 129},
  87         {QLCNIC_CMD_GET_NIC_INFO, 2, 19},
  88         {QLCNIC_CMD_SET_NIC_INFO, 32, 1},
  89         {QLCNIC_CMD_GET_ESWITCH_CAPABILITY, 4, 3},
  90         {QLCNIC_CMD_TOGGLE_ESWITCH, 4, 1},
  91         {QLCNIC_CMD_GET_ESWITCH_STATUS, 4, 3},
  92         {QLCNIC_CMD_SET_PORTMIRRORING, 4, 1},
  93         {QLCNIC_CMD_CONFIGURE_ESWITCH, 4, 1},
  94         {QLCNIC_CMD_GET_ESWITCH_PORT_CONFIG, 4, 3},
  95         {QLCNIC_CMD_GET_ESWITCH_STATS, 5, 1},
  96         {QLCNIC_CMD_CONFIG_PORT, 4, 1},
  97         {QLCNIC_CMD_TEMP_SIZE, 1, 4},
  98         {QLCNIC_CMD_GET_TEMP_HDR, 5, 5},
  99         {QLCNIC_CMD_GET_LINK_EVENT, 2, 1},
 100         {QLCNIC_CMD_CONFIG_MAC_VLAN, 4, 3},
 101         {QLCNIC_CMD_CONFIG_INTR_COAL, 6, 1},
 102         {QLCNIC_CMD_CONFIGURE_RSS, 14, 1},
 103         {QLCNIC_CMD_CONFIGURE_LED, 2, 1},
 104         {QLCNIC_CMD_CONFIGURE_MAC_RX_MODE, 2, 1},
 105         {QLCNIC_CMD_CONFIGURE_HW_LRO, 2, 1},
 106         {QLCNIC_CMD_GET_STATISTICS, 2, 80},
 107         {QLCNIC_CMD_SET_PORT_CONFIG, 2, 1},
 108         {QLCNIC_CMD_GET_PORT_CONFIG, 2, 2},
 109         {QLCNIC_CMD_GET_LINK_STATUS, 2, 4},
 110         {QLCNIC_CMD_IDC_ACK, 5, 1},
 111         {QLCNIC_CMD_INIT_NIC_FUNC, 3, 1},
 112         {QLCNIC_CMD_STOP_NIC_FUNC, 2, 1},
 113         {QLCNIC_CMD_SET_LED_CONFIG, 5, 1},
 114         {QLCNIC_CMD_GET_LED_CONFIG, 1, 5},
 115         {QLCNIC_CMD_83XX_SET_DRV_VER, 4, 1},
 116         {QLCNIC_CMD_ADD_RCV_RINGS, 130, 26},
 117         {QLCNIC_CMD_CONFIG_VPORT, 4, 4},
 118         {QLCNIC_CMD_BC_EVENT_SETUP, 2, 1},
 119         {QLCNIC_CMD_DCB_QUERY_CAP, 1, 2},
 120         {QLCNIC_CMD_DCB_QUERY_PARAM, 1, 50},
 121         {QLCNIC_CMD_SET_INGRESS_ENCAP, 2, 1},
 122         {QLCNIC_CMD_83XX_EXTEND_ISCSI_DUMP_CAP, 4, 1},
 123 };
 124
 125 const u32 qlcnic_83xx_ext_reg_tbl[] = {
 126         0x38CC,         /* Global Reset */
 127         0x38F0,         /* Wildcard */
 128         0x38FC,         /* Informant */
 129         0x3038,         /* Host MBX ctrl */
 130         0x303C,         /* FW MBX ctrl */
 131         0x355C,         /* BOOT LOADER ADDRESS REG */
 132         0x3560,         /* BOOT LOADER SIZE REG */
 133         0x3564,         /* FW IMAGE ADDR REG */
 134         0x1000,         /* MBX intr enable */
 135         0x1200,         /* Default Intr mask */
 136         0x1204,         /* Default Interrupt ID */
 137         0x3780,         /* QLC_83XX_IDC_MAJ_VERSION */
 138         0x3784,         /* QLC_83XX_IDC_DEV_STATE */
 139         0x3788,         /* QLC_83XX_IDC_DRV_PRESENCE */
 140         0x378C,         /* QLC_83XX_IDC_DRV_ACK */
 141         0x3790,         /* QLC_83XX_IDC_CTRL */
 142         0x3794,         /* QLC_83XX_IDC_DRV_AUDIT */
 143         0x3798,         /* QLC_83XX_IDC_MIN_VERSION */
 144         0x379C,         /* QLC_83XX_RECOVER_DRV_LOCK */
 145         0x37A0,         /* QLC_83XX_IDC_PF_0 */
 146         0x37A4,         /* QLC_83XX_IDC_PF_1 */
 147         0x37A8,         /* QLC_83XX_IDC_PF_2 */
 148         0x37AC,         /* QLC_83XX_IDC_PF_3 */
 149         0x37B0,         /* QLC_83XX_IDC_PF_4 */
 150         0x37B4,         /* QLC_83XX_IDC_PF_5 */
 151         0x37B8,         /* QLC_83XX_IDC_PF_6 */
 152         0x37BC,         /* QLC_83XX_IDC_PF_7 */
 153         0x37C0,         /* QLC_83XX_IDC_PF_8 */
 154         0x37C4,         /* QLC_83XX_IDC_PF_9 */
 155         0x37C8,         /* QLC_83XX_IDC_PF_10 */
 156         0x37CC,         /* QLC_83XX_IDC_PF_11 */
 157         0x37D0,         /* QLC_83XX_IDC_PF_12 */
 158         0x37D4,         /* QLC_83XX_IDC_PF_13 */
 159         0x37D8,         /* QLC_83XX_IDC_PF_14 */
 160         0x37DC,         /* QLC_83XX_IDC_PF_15 */
 161         0x37E0,         /* QLC_83XX_IDC_DEV_PARTITION_INFO_1 */
 162         0x37E4,         /* QLC_83XX_IDC_DEV_PARTITION_INFO_2 */
 163         0x37F0,         /* QLC_83XX_DRV_OP_MODE */
 164         0x37F4,         /* QLC_83XX_VNIC_STATE */
 165         0x3868,         /* QLC_83XX_DRV_LOCK */
 166         0x386C,         /* QLC_83XX_DRV_UNLOCK */
 167         0x3504,         /* QLC_83XX_DRV_LOCK_ID */
 168         0x34A4,         /* QLC_83XX_ASIC_TEMP */
 169 };
 170
 171 const u32 qlcnic_83xx_reg_tbl[] = {
 172         0x34A8,         /* PEG_HALT_STAT1 */
 173         0x34AC,         /* PEG_HALT_STAT2 */
 174         0x34B0,         /* FW_HEARTBEAT */
 175         0x3500,         /* FLASH LOCK_ID */
 176         0x3528,         /* FW_CAPABILITIES */
 177         0x3538,         /* Driver active, DRV_REG0 */
 178         0x3540,         /* Device state, DRV_REG1 */
 179         0x3544,         /* Driver state, DRV_REG2 */
 180         0x3548,         /* Driver scratch, DRV_REG3 */
 181         0x354C,         /* Device partiton info, DRV_REG4 */
 182         0x3524,         /* Driver IDC ver, DRV_REG5 */
 183         0x3550,         /* FW_VER_MAJOR */
 184         0x3554,         /* FW_VER_MINOR */
 185         0x3558,         /* FW_VER_SUB */
 186         0x359C,         /* NPAR STATE */
 187         0x35FC,         /* FW_IMG_VALID */
 188         0x3650,         /* CMD_PEG_STATE */
 189         0x373C,         /* RCV_PEG_STATE */
 190         0x37B4,         /* ASIC TEMP */
 191         0x356C,         /* FW API */
 192         0x3570,         /* DRV OP MODE */
 193         0x3850,         /* FLASH LOCK */
 194         0x3854,         /* FLASH UNLOCK */
 195 };
 196
 197 static struct qlcnic_hardware_ops qlcnic_83xx_hw_ops = {
 198         .read_crb                       = qlcnic_83xx_read_crb,
 199         .write_crb                      = qlcnic_83xx_write_crb,
 200         .read_reg                       = qlcnic_83xx_rd_reg_indirect,
 201         .write_reg                      = qlcnic_83xx_wrt_reg_indirect,
 202         .get_mac_address                = qlcnic_83xx_get_mac_address,
 203         .setup_intr                     = qlcnic_83xx_setup_intr,
 204         .alloc_mbx_args                 = qlcnic_83xx_alloc_mbx_args,
 205         .mbx_cmd                        = qlcnic_83xx_issue_cmd,
 206         .get_func_no                    = qlcnic_83xx_get_func_no,
 207         .api_lock                       = qlcnic_83xx_cam_lock,
 208         .api_unlock                     = qlcnic_83xx_cam_unlock,
 209         .add_sysfs                      = qlcnic_83xx_add_sysfs,
 210         .remove_sysfs                   = qlcnic_83xx_remove_sysfs,
 211         .process_lb_rcv_ring_diag       = qlcnic_83xx_process_rcv_ring_diag,
 212         .create_rx_ctx                  = qlcnic_83xx_create_rx_ctx,
 213         .create_tx_ctx                  = qlcnic_83xx_create_tx_ctx,
 214         .del_rx_ctx                     = qlcnic_83xx_del_rx_ctx,
 215         .del_tx_ctx                     = qlcnic_83xx_del_tx_ctx,
 216         .setup_link_event               = qlcnic_83xx_setup_link_event,
 217         .get_nic_info                   = qlcnic_83xx_get_nic_info,
 218         .get_pci_info                   = qlcnic_83xx_get_pci_info,
 219         .set_nic_info                   = qlcnic_83xx_set_nic_info,
 220         .change_macvlan                 = qlcnic_83xx_sre_macaddr_change,
 221         .napi_enable                    = qlcnic_83xx_napi_enable,
 222         .napi_disable                   = qlcnic_83xx_napi_disable,
 223         .config_intr_coal               = qlcnic_83xx_config_intr_coal,
 224         .config_rss                     = qlcnic_83xx_config_rss,
 225         .config_hw_lro                  = qlcnic_83xx_config_hw_lro,
 226         .config_promisc_mode            = qlcnic_83xx_nic_set_promisc,
 227         .change_l2_filter               = qlcnic_83xx_change_l2_filter,
 228         .get_board_info                 = qlcnic_83xx_get_port_info,
 229         .set_mac_filter_count           = qlcnic_83xx_set_mac_filter_count,
 230         .free_mac_list                  = qlcnic_82xx_free_mac_list,
 231         .io_error_detected              = qlcnic_83xx_io_error_detected,
 232         .io_slot_reset                  = qlcnic_83xx_io_slot_reset,
 233         .io_resume                      = qlcnic_83xx_io_resume,
 234         .get_beacon_state               = qlcnic_83xx_get_beacon_state,
 235         .enable_sds_intr                = qlcnic_83xx_enable_sds_intr,
 236         .disable_sds_intr               = qlcnic_83xx_disable_sds_intr,
 237         .enable_tx_intr                 = qlcnic_83xx_enable_tx_intr,
 238         .disable_tx_intr                = qlcnic_83xx_disable_tx_intr,
 239         .get_saved_state                = qlcnic_83xx_get_saved_state,
 240         .set_saved_state                = qlcnic_83xx_set_saved_state,
 241         .cache_tmpl_hdr_values          = qlcnic_83xx_cache_tmpl_hdr_values,
 242         .get_cap_size                   = qlcnic_83xx_get_cap_size,
 243         .set_sys_info                   = qlcnic_83xx_set_sys_info,
 244         .store_cap_mask                 = qlcnic_83xx_store_cap_mask,
 245 };
 246
 247 static struct qlcnic_nic_template qlcnic_83xx_ops = {
 248         .config_bridged_mode    = qlcnic_config_bridged_mode,
 249         .config_led             = qlcnic_config_led,
 250         .request_reset          = qlcnic_83xx_idc_request_reset,
 251         .cancel_idc_work        = qlcnic_83xx_idc_exit,
 252         .napi_add               = qlcnic_83xx_napi_add,
 253         .napi_del               = qlcnic_83xx_napi_del,
 254         .config_ipaddr          = qlcnic_83xx_config_ipaddr,
 255         .clear_legacy_intr      = qlcnic_83xx_clear_legacy_intr,
 256         .shutdown               = qlcnic_83xx_shutdown,
 257         .resume                 = qlcnic_83xx_resume,
 258 };
 259
 260 void qlcnic_83xx_register_map(struct qlcnic_hardware_context *ahw)
 261 {
 262         ahw->hw_ops             = &qlcnic_83xx_hw_ops;
 263         ahw->reg_tbl            = (u32 *)qlcnic_83xx_reg_tbl;
 264         ahw->ext_reg_tbl        = (u32 *)qlcnic_83xx_ext_reg_tbl;
 265 }
 266
 267 int qlcnic_83xx_get_fw_version(struct qlcnic_adapter *adapter)
 268 {
 269         u32 fw_major, fw_minor, fw_build;
 270         struct pci_dev *pdev = adapter->pdev;
 271
 272         fw_major = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MAJOR);
 273         fw_minor = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MINOR);
 274         fw_build = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_SUB);
 275         adapter->fw_version = QLCNIC_VERSION_CODE(fw_major, fw_minor, fw_build);
 276
 277         dev_info(&pdev->dev, "Driver v%s, firmware version %d.%d.%d\n",
 278                  QLCNIC_LINUX_VERSIONID, fw_major, fw_minor, fw_build);
 279
 280         return adapter->fw_version;
 281 }
 282
 283 static int __qlcnic_set_win_base(struct qlcnic_adapter *adapter, u32 addr)
 284 {
 285         void __iomem *base;
 286         u32 val;
 287
 288         base = adapter->ahw->pci_base0 +
 289                QLC_83XX_CRB_WIN_FUNC(adapter->ahw->pci_func);
 290         writel(addr, base);
 291         val = readl(base);
 292         if (val != addr)
 293                 return -EIO;
 294
 295         return 0;
 296 }
 297
 298 int qlcnic_83xx_rd_reg_indirect(struct qlcnic_adapter *adapter, ulong addr,
 299                                 int *err)
 300 {
 301         struct qlcnic_hardware_context *ahw = adapter->ahw;
 302
 303         *err = __qlcnic_set_win_base(adapter, (u32) addr);
 304         if (!*err) {
 305                 return QLCRDX(ahw, QLCNIC_WILDCARD);
 306         } else {
 307                 dev_err(&adapter->pdev->dev,
 308                         "%s failed, addr = 0x%lx\n", __func__, addr);
 309                 return -EIO;
 310         }
 311 }
 312
 313 int qlcnic_83xx_wrt_reg_indirect(struct qlcnic_adapter *adapter, ulong addr,
 314                                  u32 data)
 315 {
 316         int err;
 317         struct qlcnic_hardware_context *ahw = adapter->ahw;
 318
 319         err = __qlcnic_set_win_base(adapter, (u32) addr);
 320         if (!err) {
 321                 QLCWRX(ahw, QLCNIC_WILDCARD, data);
 322                 return 0;
 323         } else {
 324                 dev_err(&adapter->pdev->dev,
 325                         "%s failed, addr = 0x%x data = 0x%x\n",
 326                         __func__, (int)addr, data);
 327                 return err;
 328         }
 329 }
 330
 331 static void qlcnic_83xx_enable_legacy(struct qlcnic_adapter *adapter)
 332 {
 333         struct qlcnic_hardware_context *ahw = adapter->ahw;
 334
 335         /* MSI-X enablement failed, use legacy interrupt */
 336         adapter->tgt_status_reg = ahw->pci_base0 + QLC_83XX_INTX_PTR;
 337         adapter->tgt_mask_reg = ahw->pci_base0 + QLC_83XX_INTX_MASK;
 338         adapter->isr_int_vec = ahw->pci_base0 + QLC_83XX_INTX_TRGR;
 339         adapter->msix_entries[0].vector = adapter->pdev->irq;
 340         dev_info(&adapter->pdev->dev, "using legacy interrupt\n");
 341 }
 342
 343 static int qlcnic_83xx_calculate_msix_vector(struct qlcnic_adapter *adapter)
 344 {
 345         int num_msix;
 346
 347         num_msix = adapter->drv_sds_rings;
 348
 349         /* account for AEN interrupt MSI-X based interrupts */
 350         num_msix += 1;
 351
 352         if (!(adapter->flags & QLCNIC_TX_INTR_SHARED))
 353                 num_msix += adapter->drv_tx_rings;
 354
 355         return num_msix;
 356 }
 357
 358 int qlcnic_83xx_setup_intr(struct qlcnic_adapter *adapter)
 359 {
 360         struct qlcnic_hardware_context *ahw = adapter->ahw;
 361         int err, i, num_msix;
 362
 363         if (adapter->flags & QLCNIC_TSS_RSS) {
 364                 err = qlcnic_setup_tss_rss_intr(adapter);
 365                 if (err < 0)
 366                         return err;
 367                 num_msix = ahw->num_msix;
 368         } else {
 369                 num_msix = qlcnic_83xx_calculate_msix_vector(adapter);
 370
 371                 err = qlcnic_enable_msix(adapter, num_msix);
 372                 if (err == -ENOMEM)
 373                         return err;
 374
 375                 if (adapter->flags & QLCNIC_MSIX_ENABLED) {
 376                         num_msix = ahw->num_msix;
 377                 } else {
 378                         if (qlcnic_sriov_vf_check(adapter))
 379                                 return -EINVAL;
 380                         num_msix = 1;
 381                         adapter->drv_sds_rings = QLCNIC_SINGLE_RING;
 382                         adapter->drv_tx_rings = QLCNIC_SINGLE_RING;
 383                 }
 384         }
 385
 386         /* setup interrupt mapping table for fw */
 387         ahw->intr_tbl = vzalloc(num_msix *
 388                                 sizeof(struct qlcnic_intrpt_config));
 389         if (!ahw->intr_tbl)
 390                 return -ENOMEM;
 391
 392         if (!(adapter->flags & QLCNIC_MSIX_ENABLED)) {
 393                 if (adapter->ahw->pci_func >= QLC_MAX_LEGACY_FUNC_SUPP) {
 394                         dev_err(&adapter->pdev->dev, "PCI function number 8 and higher are not supported with legacy interrupt, func 0x%x\n",
 395                                 ahw->pci_func);
 396                         return -EOPNOTSUPP;
 397                 }
 398
 399                 qlcnic_83xx_enable_legacy(adapter);
 400         }
 401
 402         for (i = 0; i < num_msix; i++) {
 403                 if (adapter->flags & QLCNIC_MSIX_ENABLED)
 404                         ahw->intr_tbl[i].type = QLCNIC_INTRPT_MSIX;
 405                 else
 406                         ahw->intr_tbl[i].type = QLCNIC_INTRPT_INTX;
 407                 ahw->intr_tbl[i].id = i;
 408                 ahw->intr_tbl[i].src = 0;
 409         }
 410
 411         return 0;
 412 }
 413
 414 static inline void qlcnic_83xx_clear_legacy_intr_mask(struct qlcnic_adapter *adapter)
 415 {
 416         writel(0, adapter->tgt_mask_reg);
 417 }
 418
 419 static inline void qlcnic_83xx_set_legacy_intr_mask(struct qlcnic_adapter *adapter)
 420 {
 421         if (adapter->tgt_mask_reg)
 422                 writel(1, adapter->tgt_mask_reg);
 423 }
 424
 425 static inline void qlcnic_83xx_enable_legacy_msix_mbx_intr(struct qlcnic_adapter
 426                                                     *adapter)
 427 {
 428         u32 mask;
 429
 430         /* Mailbox in MSI-x mode and Legacy Interrupt share the same
 431          * source register. We could be here before contexts are created
 432          * and sds_ring->crb_intr_mask has not been initialized, calculate
 433          * BAR offset for Interrupt Source Register
 434          */
 435         mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
 436         writel(0, adapter->ahw->pci_base0 + mask);
 437 }
 438
 439 void qlcnic_83xx_disable_mbx_intr(struct qlcnic_adapter *adapter)
 440 {
 441         u32 mask;
 442
 443         mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
 444         writel(1, adapter->ahw->pci_base0 + mask);
 445         QLCWRX(adapter->ahw, QLCNIC_MBX_INTR_ENBL, 0);
 446 }
 447
 448 static inline void qlcnic_83xx_get_mbx_data(struct qlcnic_adapter *adapter,
 449                                      struct qlcnic_cmd_args *cmd)
 450 {
 451         int i;
 452
 453         if (cmd->op_type == QLC_83XX_MBX_POST_BC_OP)
 454                 return;
 455
 456         for (i = 0; i < cmd->rsp.num; i++)
 457                 cmd->rsp.arg[i] = readl(QLCNIC_MBX_FW(adapter->ahw, i));
 458 }
 459
 460 irqreturn_t qlcnic_83xx_clear_legacy_intr(struct qlcnic_adapter *adapter)
 461 {
 462         u32 intr_val;
 463         struct qlcnic_hardware_context *ahw = adapter->ahw;
 464         int retries = 0;
 465
 466         intr_val = readl(adapter->tgt_status_reg);
 467
 468         if (!QLC_83XX_VALID_INTX_BIT31(intr_val))
 469                 return IRQ_NONE;
 470
 471         if (QLC_83XX_INTX_FUNC(intr_val) != adapter->ahw->pci_func) {
 472                 adapter->stats.spurious_intr++;
 473                 return IRQ_NONE;
 474         }
 475         /* The barrier is required to ensure writes to the registers */
 476         wmb();
 477
 478         /* clear the interrupt trigger control register */
 479         writel(0, adapter->isr_int_vec);
 480         intr_val = readl(adapter->isr_int_vec);
 481         do {
 482                 intr_val = readl(adapter->tgt_status_reg);
 483                 if (QLC_83XX_INTX_FUNC(intr_val) != ahw->pci_func)
 484                         break;
 485                 retries++;
 486         } while (QLC_83XX_VALID_INTX_BIT30(intr_val) &&
 487                  (retries < QLC_83XX_LEGACY_INTX_MAX_RETRY));
 488
 489         return IRQ_HANDLED;
 490 }
 491
 492 static inline void qlcnic_83xx_notify_mbx_response(struct qlcnic_mailbox *mbx)
 493 {
 494         atomic_set(&mbx->rsp_status, QLC_83XX_MBX_RESPONSE_ARRIVED);
 495         complete(&mbx->completion);
 496 }
 497
 498 static void qlcnic_83xx_poll_process_aen(struct qlcnic_adapter *adapter)
 499 {
 500         u32 resp, event, rsp_status = QLC_83XX_MBX_RESPONSE_ARRIVED;
 501         struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
 502         unsigned long flags;
 503
 504         spin_lock_irqsave(&mbx->aen_lock, flags);
 505         resp = QLCRDX(adapter->ahw, QLCNIC_FW_MBX_CTRL);
 506         if (!(resp & QLCNIC_SET_OWNER))
 507                 goto out;
 508
 509         event = readl(QLCNIC_MBX_FW(adapter->ahw, 0));
 510         if (event &  QLCNIC_MBX_ASYNC_EVENT) {
 511                 __qlcnic_83xx_process_aen(adapter);
 512         } else {
 513                 if (atomic_read(&mbx->rsp_status) != rsp_status)
 514                         qlcnic_83xx_notify_mbx_response(mbx);
 515         }
 516 out:
 517         qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
 518         spin_unlock_irqrestore(&mbx->aen_lock, flags);
 519 }
 520
 521 irqreturn_t qlcnic_83xx_intr(int irq, void *data)
 522 {
 523         struct qlcnic_adapter *adapter = data;
 524         struct qlcnic_host_sds_ring *sds_ring;
 525         struct qlcnic_hardware_context *ahw = adapter->ahw;
 526
 527         if (qlcnic_83xx_clear_legacy_intr(adapter) == IRQ_NONE)
 528                 return IRQ_NONE;
 529
 530         qlcnic_83xx_poll_process_aen(adapter);
 531
 532         if (ahw->diag_test) {
 533                 if (ahw->diag_test == QLCNIC_INTERRUPT_TEST)
 534                         ahw->diag_cnt++;
 535                 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
 536                 return IRQ_HANDLED;
 537         }
 538
 539         if (!test_bit(__QLCNIC_DEV_UP, &adapter->state)) {
 540                 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
 541         } else {
 542                 sds_ring = &adapter->recv_ctx->sds_rings[0];
 543                 napi_schedule(&sds_ring->napi);
 544         }
 545
 546         return IRQ_HANDLED;
 547 }
 548
 549 irqreturn_t qlcnic_83xx_tmp_intr(int irq, void *data)
 550 {
 551         struct qlcnic_host_sds_ring *sds_ring = data;
 552         struct qlcnic_adapter *adapter = sds_ring->adapter;
 553
 554         if (adapter->flags & QLCNIC_MSIX_ENABLED)
 555                 goto done;
 556
 557         if (adapter->nic_ops->clear_legacy_intr(adapter) == IRQ_NONE)
 558                 return IRQ_NONE;
 559
 560 done:
 561         adapter->ahw->diag_cnt++;
 562         qlcnic_enable_sds_intr(adapter, sds_ring);
 563
 564         return IRQ_HANDLED;
 565 }
 566
 567 void qlcnic_83xx_free_mbx_intr(struct qlcnic_adapter *adapter)
 568 {
 569         u32 num_msix;
 570
 571         if (!(adapter->flags & QLCNIC_MSIX_ENABLED))
 572                 qlcnic_83xx_set_legacy_intr_mask(adapter);
 573
 574         qlcnic_83xx_disable_mbx_intr(adapter);
 575
 576         if (adapter->flags & QLCNIC_MSIX_ENABLED)
 577                 num_msix = adapter->ahw->num_msix - 1;
 578         else
 579                 num_msix = 0;
 580
 581         msleep(20);
 582
 583         if (adapter->msix_entries) {
 584                 synchronize_irq(adapter->msix_entries[num_msix].vector);
 585                 free_irq(adapter->msix_entries[num_msix].vector, adapter);
 586         }
 587 }
 588
 589 int qlcnic_83xx_setup_mbx_intr(struct qlcnic_adapter *adapter)
 590 {
 591         irq_handler_t handler;
 592         u32 val;
 593         int err = 0;
 594         unsigned long flags = 0;
 595
 596         if (!(adapter->flags & QLCNIC_MSI_ENABLED) &&
 597             !(adapter->flags & QLCNIC_MSIX_ENABLED))
 598                 flags |= IRQF_SHARED;
 599
 600         if (adapter->flags & QLCNIC_MSIX_ENABLED) {
 601                 handler = qlcnic_83xx_handle_aen;
 602                 val = adapter->msix_entries[adapter->ahw->num_msix - 1].vector;
 603                 err = request_irq(val, handler, flags, "qlcnic-MB", adapter);
 604                 if (err) {
 605                         dev_err(&adapter->pdev->dev,
 606                                 "failed to register MBX interrupt\n");
 607                         return err;
 608                 }
 609         } else {
 610                 handler = qlcnic_83xx_intr;
 611                 val = adapter->msix_entries[0].vector;
 612                 err = request_irq(val, handler, flags, "qlcnic", adapter);
 613                 if (err) {
 614                         dev_err(&adapter->pdev->dev,
 615                                 "failed to register INTx interrupt\n");
 616                         return err;
 617                 }
 618                 qlcnic_83xx_clear_legacy_intr_mask(adapter);
 619         }
 620
 621         /* Enable mailbox interrupt */
 622         qlcnic_83xx_enable_mbx_interrupt(adapter);
 623
 624         return err;
 625 }
 626
 627 void qlcnic_83xx_get_func_no(struct qlcnic_adapter *adapter)
 628 {
 629         u32 val = QLCRDX(adapter->ahw, QLCNIC_INFORMANT);
 630         adapter->ahw->pci_func = (val >> 24) & 0xff;
 631 }
 632
 633 int qlcnic_83xx_cam_lock(struct qlcnic_adapter *adapter)
 634 {
 635         void __iomem *addr;
 636         u32 val, limit = 0;
 637
 638         struct qlcnic_hardware_context *ahw = adapter->ahw;
 639
 640         addr = ahw->pci_base0 + QLC_83XX_SEM_LOCK_FUNC(ahw->pci_func);
 641         do {
 642                 val = readl(addr);
 643                 if (val) {
 644                         /* write the function number to register */
 645                         QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER,
 646                                             ahw->pci_func);
 647                         return 0;
 648                 }
 649                 usleep_range(1000, 2000);
 650         } while (++limit <= QLCNIC_PCIE_SEM_TIMEOUT);
 651
 652         return -EIO;
 653 }
 654
 655 void qlcnic_83xx_cam_unlock(struct qlcnic_adapter *adapter)
 656 {
 657         void __iomem *addr;
 658         u32 val;
 659         struct qlcnic_hardware_context *ahw = adapter->ahw;
 660
 661         addr = ahw->pci_base0 + QLC_83XX_SEM_UNLOCK_FUNC(ahw->pci_func);
 662         val = readl(addr);
 663 }
 664
 665 void qlcnic_83xx_read_crb(struct qlcnic_adapter *adapter, char *buf,
 666                           loff_t offset, size_t size)
 667 {
 668         int ret = 0;
 669         u32 data;
 670
 671         if (qlcnic_api_lock(adapter)) {
 672                 dev_err(&adapter->pdev->dev,
 673                         "%s: failed to acquire lock. addr offset 0x%x\n",
 674                         __func__, (u32)offset);
 675                 return;
 676         }
 677
 678         data = QLCRD32(adapter, (u32) offset, &ret);
 679         qlcnic_api_unlock(adapter);
 680
 681         if (ret == -EIO) {
 682                 dev_err(&adapter->pdev->dev,
 683                         "%s: failed. addr offset 0x%x\n",
 684                         __func__, (u32)offset);
 685                 return;
 686         }
 687         memcpy(buf, &data, size);
 688 }
 689
 690 void qlcnic_83xx_write_crb(struct qlcnic_adapter *adapter, char *buf,
 691                            loff_t offset, size_t size)
 692 {
 693         u32 data;
 694
 695         memcpy(&data, buf, size);
 696         qlcnic_83xx_wrt_reg_indirect(adapter, (u32) offset, data);
 697 }
 698
 699 int qlcnic_83xx_get_port_info(struct qlcnic_adapter *adapter)
 700 {
 701         struct qlcnic_hardware_context *ahw = adapter->ahw;
 702         int status;
 703
 704         status = qlcnic_83xx_get_port_config(adapter);
 705         if (status) {
 706                 dev_err(&adapter->pdev->dev,
 707                         "Get Port Info failed\n");
 708         } else {
 709
 710                 if (ahw->port_config & QLC_83XX_10G_CAPABLE) {
 711                         ahw->port_type = QLCNIC_XGBE;
 712                 } else if (ahw->port_config & QLC_83XX_10_CAPABLE ||
 713                            ahw->port_config & QLC_83XX_100_CAPABLE ||
 714                            ahw->port_config & QLC_83XX_1G_CAPABLE) {
 715                         ahw->port_type = QLCNIC_GBE;
 716                 } else {
 717                         ahw->port_type = QLCNIC_XGBE;
 718                 }
 719
 720                 if (QLC_83XX_AUTONEG(ahw->port_config))
 721                         ahw->link_autoneg = AUTONEG_ENABLE;
 722
 723         }
 724         return status;
 725 }
 726
 727 static void qlcnic_83xx_set_mac_filter_count(struct qlcnic_adapter *adapter)
 728 {
 729         struct qlcnic_hardware_context *ahw = adapter->ahw;
 730         u16 act_pci_fn = ahw->total_nic_func;
 731         u16 count;
 732
 733         ahw->max_mc_count = QLC_83XX_MAX_MC_COUNT;
 734         if (act_pci_fn <= 2)
 735                 count = (QLC_83XX_MAX_UC_COUNT - QLC_83XX_MAX_MC_COUNT) /
 736                          act_pci_fn;
 737         else
 738                 count = (QLC_83XX_LB_MAX_FILTERS - QLC_83XX_MAX_MC_COUNT) /
 739                          act_pci_fn;
 740         ahw->max_uc_count = count;
 741 }
 742
 743 void qlcnic_83xx_enable_mbx_interrupt(struct qlcnic_adapter *adapter)
 744 {
 745         u32 val;
 746
 747         if (adapter->flags & QLCNIC_MSIX_ENABLED)
 748                 val = BIT_2 | ((adapter->ahw->num_msix - 1) << 8);
 749         else
 750                 val = BIT_2;
 751
 752         QLCWRX(adapter->ahw, QLCNIC_MBX_INTR_ENBL, val);
 753         qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
 754 }
 755
 756 void qlcnic_83xx_check_vf(struct qlcnic_adapter *adapter,
 757                           const struct pci_device_id *ent)
 758 {
 759         u32 op_mode, priv_level;
 760         struct qlcnic_hardware_context *ahw = adapter->ahw;
 761
 762         ahw->fw_hal_version = 2;
 763         qlcnic_get_func_no(adapter);
 764
 765         if (qlcnic_sriov_vf_check(adapter)) {
 766                 qlcnic_sriov_vf_set_ops(adapter);
 767                 return;
 768         }
 769
 770         /* Determine function privilege level */
 771         op_mode = QLCRDX(adapter->ahw, QLC_83XX_DRV_OP_MODE);
 772         if (op_mode == QLC_83XX_DEFAULT_OPMODE)
 773                 priv_level = QLCNIC_MGMT_FUNC;
 774         else
 775                 priv_level = QLC_83XX_GET_FUNC_PRIVILEGE(op_mode,
 776                                                          ahw->pci_func);
 777
 778         if (priv_level == QLCNIC_NON_PRIV_FUNC) {
 779                 ahw->op_mode = QLCNIC_NON_PRIV_FUNC;
 780                 dev_info(&adapter->pdev->dev,
 781                          "HAL Version: %d Non Privileged function\n",
 782                          ahw->fw_hal_version);
 783                 adapter->nic_ops = &qlcnic_vf_ops;
 784         } else {
 785                 if (pci_find_ext_capability(adapter->pdev,
 786                                             PCI_EXT_CAP_ID_SRIOV))
 787                         set_bit(__QLCNIC_SRIOV_CAPABLE, &adapter->state);
 788                 adapter->nic_ops = &qlcnic_83xx_ops;
 789         }
 790 }
 791
 792 static void qlcnic_83xx_handle_link_aen(struct qlcnic_adapter *adapter,
 793                                         u32 data[]);
 794 static void qlcnic_83xx_handle_idc_comp_aen(struct qlcnic_adapter *adapter,
 795                                             u32 data[]);
 796
 797 void qlcnic_dump_mbx(struct qlcnic_adapter *adapter,
 798                      struct qlcnic_cmd_args *cmd)
 799 {
 800         int i;
 801
 802         if (cmd->op_type == QLC_83XX_MBX_POST_BC_OP)
 803                 return;
 804
 805         dev_info(&adapter->pdev->dev,
 806                  "Host MBX regs(%d)\n", cmd->req.num);
 807         for (i = 0; i < cmd->req.num; i++) {
 808                 if (i && !(i % 8))
 809                         pr_info("\n");
 810                 pr_info("%08x ", cmd->req.arg[i]);
 811         }
 812         pr_info("\n");
 813         dev_info(&adapter->pdev->dev,
 814                  "FW MBX regs(%d)\n", cmd->rsp.num);
 815         for (i = 0; i < cmd->rsp.num; i++) {
 816                 if (i && !(i % 8))
 817                         pr_info("\n");
 818                 pr_info("%08x ", cmd->rsp.arg[i]);
 819         }
 820         pr_info("\n");
 821 }
 822
 823 static void qlcnic_83xx_poll_for_mbx_completion(struct qlcnic_adapter *adapter,
 824                                                 struct qlcnic_cmd_args *cmd)
 825 {
 826         struct qlcnic_hardware_context *ahw = adapter->ahw;
 827         int opcode = LSW(cmd->req.arg[0]);
 828         unsigned long max_loops;
 829
 830         max_loops = cmd->total_cmds * QLC_83XX_MBX_CMD_LOOP;
 831
 832         for (; max_loops; max_loops--) {
 833                 if (atomic_read(&cmd->rsp_status) ==
 834                     QLC_83XX_MBX_RESPONSE_ARRIVED)
 835                         return;
 836
 837                 udelay(1);
 838         }
 839
 840         dev_err(&adapter->pdev->dev,
 841                 "%s: Mailbox command timed out, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
 842                 __func__, opcode, cmd->type, ahw->pci_func, ahw->op_mode);
 843         flush_workqueue(ahw->mailbox->work_q);
 844         return;
 845 }
 846
 847 int qlcnic_83xx_issue_cmd(struct qlcnic_adapter *adapter,
 848                           struct qlcnic_cmd_args *cmd)
 849 {
 850         struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
 851         struct qlcnic_hardware_context *ahw = adapter->ahw;
 852         int cmd_type, err, opcode;
 853         unsigned long timeout;
 854
 855         if (!mbx)
 856                 return -EIO;
 857
 858         opcode = LSW(cmd->req.arg[0]);
 859         cmd_type = cmd->type;
 860         err = mbx->ops->enqueue_cmd(adapter, cmd, &timeout);
 861         if (err) {
 862                 dev_err(&adapter->pdev->dev,
 863                         "%s: Mailbox not available, cmd_op=0x%x, cmd_context=0x%x, pci_func=0x%x, op_mode=0x%x\n",
 864                         __func__, opcode, cmd->type, ahw->pci_func,
 865                         ahw->op_mode);
 866                 return err;
 867         }
 868
 869         switch (cmd_type) {
 870         case QLC_83XX_MBX_CMD_WAIT:
 871                 if (!wait_for_completion_timeout(&cmd->completion, timeout)) {
 872                         dev_err(&adapter->pdev->dev,
 873                                 "%s: Mailbox command timed out, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
 874                                 __func__, opcode, cmd_type, ahw->pci_func,
 875                                 ahw->op_mode);
 876                         flush_workqueue(mbx->work_q);
 877                 }
 878                 break;
 879         case QLC_83XX_MBX_CMD_NO_WAIT:
 880                 return 0;
 881         case QLC_83XX_MBX_CMD_BUSY_WAIT:
 882                 qlcnic_83xx_poll_for_mbx_completion(adapter, cmd);
 883                 break;
 884         default:
 885                 dev_err(&adapter->pdev->dev,
 886                         "%s: Invalid mailbox command, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
 887                         __func__, opcode, cmd_type, ahw->pci_func,
 888                         ahw->op_mode);
 889                 qlcnic_83xx_detach_mailbox_work(adapter);
 890         }
 891
 892         return cmd->rsp_opcode;
 893 }
 894
 895 int qlcnic_83xx_alloc_mbx_args(struct qlcnic_cmd_args *mbx,
 896                                struct qlcnic_adapter *adapter, u32 type)
 897 {
 898         int i, size;
 899         u32 temp;
 900         const struct qlcnic_mailbox_metadata *mbx_tbl;
 901
 902         memset(mbx, 0, sizeof(struct qlcnic_cmd_args));
 903         mbx_tbl = qlcnic_83xx_mbx_tbl;
 904         size = ARRAY_SIZE(qlcnic_83xx_mbx_tbl);
 905         for (i = 0; i < size; i++) {
 906                 if (type == mbx_tbl[i].cmd) {
 907                         mbx->op_type = QLC_83XX_FW_MBX_CMD;
 908                         mbx->req.num = mbx_tbl[i].in_args;
 909                         mbx->rsp.num = mbx_tbl[i].out_args;
 910                         mbx->req.arg = kcalloc(mbx->req.num, sizeof(u32),
 911                                                GFP_ATOMIC);
 912                         if (!mbx->req.arg)
 913                                 return -ENOMEM;
 914                         mbx->rsp.arg = kcalloc(mbx->rsp.num, sizeof(u32),
 915                                                GFP_ATOMIC);
 916                         if (!mbx->rsp.arg) {
 917                                 kfree(mbx->req.arg);
 918                                 mbx->req.arg = NULL;
 919                                 return -ENOMEM;
 920                         }
 921                         memset(mbx->req.arg, 0, sizeof(u32) * mbx->req.num);
 922                         memset(mbx->rsp.arg, 0, sizeof(u32) * mbx->rsp.num);
 923                         temp = adapter->ahw->fw_hal_version << 29;
 924                         mbx->req.arg[0] = (type | (mbx->req.num << 16) | temp);
 925                         mbx->cmd_op = type;
 926                         return 0;
 927                 }
 928         }
 929
 930         dev_err(&adapter->pdev->dev, "%s: Invalid mailbox command opcode 0x%x\n",
 931                 __func__, type);
 932         return -EINVAL;
 933 }
 934
 935 void qlcnic_83xx_idc_aen_work(struct work_struct *work)
 936 {
 937         struct qlcnic_adapter *adapter;
 938         struct qlcnic_cmd_args cmd;
 939         int i, err = 0;
 940
 941         adapter = container_of(work, struct qlcnic_adapter, idc_aen_work.work);
 942         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_IDC_ACK);
 943         if (err)
 944                 return;
 945
 946         for (i = 1; i < QLC_83XX_MBX_AEN_CNT; i++)
 947                 cmd.req.arg[i] = adapter->ahw->mbox_aen[i];
 948
 949         err = qlcnic_issue_cmd(adapter, &cmd);
 950         if (err)
 951                 dev_info(&adapter->pdev->dev,
 952                          "%s: Mailbox IDC ACK failed.\n", __func__);
 953         qlcnic_free_mbx_args(&cmd);
 954 }
 955
 956 static void qlcnic_83xx_handle_idc_comp_aen(struct qlcnic_adapter *adapter,
 957                                             u32 data[])
 958 {
 959         dev_dbg(&adapter->pdev->dev, "Completion AEN:0x%x.\n",
 960                 QLCNIC_MBX_RSP(data[0]));
 961         clear_bit(QLC_83XX_IDC_COMP_AEN, &adapter->ahw->idc.status);
 962         return;
 963 }
 964
 965 static void __qlcnic_83xx_process_aen(struct qlcnic_adapter *adapter)
 966 {
 967         struct qlcnic_hardware_context *ahw = adapter->ahw;
 968         u32 event[QLC_83XX_MBX_AEN_CNT];
 969         int i;
 970
 971         for (i = 0; i < QLC_83XX_MBX_AEN_CNT; i++)
 972                 event[i] = readl(QLCNIC_MBX_FW(ahw, i));
 973
 974         switch (QLCNIC_MBX_RSP(event[0])) {
 975
 976         case QLCNIC_MBX_LINK_EVENT:
 977                 qlcnic_83xx_handle_link_aen(adapter, event);
 978                 break;
 979         case QLCNIC_MBX_COMP_EVENT:
 980                 qlcnic_83xx_handle_idc_comp_aen(adapter, event);
 981                 break;
 982         case QLCNIC_MBX_REQUEST_EVENT:
 983                 for (i = 0; i < QLC_83XX_MBX_AEN_CNT; i++)
 984                         adapter->ahw->mbox_aen[i] = QLCNIC_MBX_RSP(event[i]);
 985                 queue_delayed_work(adapter->qlcnic_wq,
 986                                    &adapter->idc_aen_work, 0);
 987                 break;
 988         case QLCNIC_MBX_TIME_EXTEND_EVENT:
 989                 ahw->extend_lb_time = event[1] >> 8 & 0xf;
 990                 break;
 991         case QLCNIC_MBX_BC_EVENT:
 992                 qlcnic_sriov_handle_bc_event(adapter, event[1]);
 993                 break;
 994         case QLCNIC_MBX_SFP_INSERT_EVENT:
 995                 dev_info(&adapter->pdev->dev, "SFP+ Insert AEN:0x%x.\n",
 996                          QLCNIC_MBX_RSP(event[0]));
 997                 break;
 998         case QLCNIC_MBX_SFP_REMOVE_EVENT:
 999                 dev_info(&adapter->pdev->dev, "SFP Removed AEN:0x%x.\n",
1000                          QLCNIC_MBX_RSP(event[0]));
1001                 break;
1002         case QLCNIC_MBX_DCBX_CONFIG_CHANGE_EVENT:
1003                 qlcnic_dcb_aen_handler(adapter->dcb, (void *)&event[1]);
1004                 break;
1005         default:
1006                 dev_dbg(&adapter->pdev->dev, "Unsupported AEN:0x%x.\n",
1007                         QLCNIC_MBX_RSP(event[0]));
1008                 break;
1009         }
1010
1011         QLCWRX(ahw, QLCNIC_FW_MBX_CTRL, QLCNIC_CLR_OWNER);
1012 }
1013
1014 static void qlcnic_83xx_process_aen(struct qlcnic_adapter *adapter)
1015 {
1016         u32 resp, event, rsp_status = QLC_83XX_MBX_RESPONSE_ARRIVED;
1017         struct qlcnic_hardware_context *ahw = adapter->ahw;
1018         struct qlcnic_mailbox *mbx = ahw->mailbox;
1019         unsigned long flags;
1020
1021         spin_lock_irqsave(&mbx->aen_lock, flags);
1022         resp = QLCRDX(ahw, QLCNIC_FW_MBX_CTRL);
1023         if (resp & QLCNIC_SET_OWNER) {
1024                 event = readl(QLCNIC_MBX_FW(ahw, 0));
1025                 if (event &  QLCNIC_MBX_ASYNC_EVENT) {
1026                         __qlcnic_83xx_process_aen(adapter);
1027                 } else {
1028                         if (atomic_read(&mbx->rsp_status) != rsp_status)
1029                                 qlcnic_83xx_notify_mbx_response(mbx);
1030                 }
1031         }
1032         spin_unlock_irqrestore(&mbx->aen_lock, flags);
1033 }
1034
1035 static void qlcnic_83xx_mbx_poll_work(struct work_struct *work)
1036 {
1037         struct qlcnic_adapter *adapter;
1038
1039         adapter = container_of(work, struct qlcnic_adapter, mbx_poll_work.work);
1040
1041         if (!test_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state))
1042                 return;
1043
1044         qlcnic_83xx_process_aen(adapter);
1045         queue_delayed_work(adapter->qlcnic_wq, &adapter->mbx_poll_work,
1046                            (HZ / 10));
1047 }
1048
1049 void qlcnic_83xx_enable_mbx_poll(struct qlcnic_adapter *adapter)
1050 {
1051         if (test_and_set_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state))
1052                 return;
1053
1054         INIT_DELAYED_WORK(&adapter->mbx_poll_work, qlcnic_83xx_mbx_poll_work);
1055         queue_delayed_work(adapter->qlcnic_wq, &adapter->mbx_poll_work, 0);
1056 }
1057
1058 void qlcnic_83xx_disable_mbx_poll(struct qlcnic_adapter *adapter)
1059 {
1060         if (!test_and_clear_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state))
1061                 return;
1062         cancel_delayed_work_sync(&adapter->mbx_poll_work);
1063 }
1064
1065 static int qlcnic_83xx_add_rings(struct qlcnic_adapter *adapter)
1066 {
1067         int index, i, err, sds_mbx_size;
1068         u32 *buf, intrpt_id, intr_mask;
1069         u16 context_id;
1070         u8 num_sds;
1071         struct qlcnic_cmd_args cmd;
1072         struct qlcnic_host_sds_ring *sds;
1073         struct qlcnic_sds_mbx sds_mbx;
1074         struct qlcnic_add_rings_mbx_out *mbx_out;
1075         struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
1076         struct qlcnic_hardware_context *ahw = adapter->ahw;
1077
1078         sds_mbx_size = sizeof(struct qlcnic_sds_mbx);
1079         context_id = recv_ctx->context_id;
1080         num_sds = adapter->drv_sds_rings - QLCNIC_MAX_SDS_RINGS;
1081         ahw->hw_ops->alloc_mbx_args(&cmd, adapter,
1082                                     QLCNIC_CMD_ADD_RCV_RINGS);
1083         cmd.req.arg[1] = 0 | (num_sds << 8) | (context_id << 16);
1084
1085         /* set up status rings, mbx 2-81 */
1086         index = 2;
1087         for (i = 8; i < adapter->drv_sds_rings; i++) {
1088                 memset(&sds_mbx, 0, sds_mbx_size);
1089                 sds = &recv_ctx->sds_rings[i];
1090                 sds->consumer = 0;
1091                 memset(sds->desc_head, 0, STATUS_DESC_RINGSIZE(sds));
1092                 sds_mbx.phy_addr_low = LSD(sds->phys_addr);
1093                 sds_mbx.phy_addr_high = MSD(sds->phys_addr);
1094                 sds_mbx.sds_ring_size = sds->num_desc;
1095
1096                 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1097                         intrpt_id = ahw->intr_tbl[i].id;
1098                 else
1099                         intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
1100
1101                 if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
1102                         sds_mbx.intrpt_id = intrpt_id;
1103                 else
1104                         sds_mbx.intrpt_id = 0xffff;
1105                 sds_mbx.intrpt_val = 0;
1106                 buf = &cmd.req.arg[index];
1107                 memcpy(buf, &sds_mbx, sds_mbx_size);
1108                 index += sds_mbx_size / sizeof(u32);
1109         }
1110
1111         /* send the mailbox command */
1112         err = ahw->hw_ops->mbx_cmd(adapter, &cmd);
1113         if (err) {
1114                 dev_err(&adapter->pdev->dev,
1115                         "Failed to add rings %d\n", err);
1116                 goto out;
1117         }
1118
1119         mbx_out = (struct qlcnic_add_rings_mbx_out *)&cmd.rsp.arg[1];
1120         index = 0;
1121         /* status descriptor ring */
1122         for (i = 8; i < adapter->drv_sds_rings; i++) {
1123                 sds = &recv_ctx->sds_rings[i];
1124                 sds->crb_sts_consumer = ahw->pci_base0 +
1125                                         mbx_out->host_csmr[index];
1126                 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1127                         intr_mask = ahw->intr_tbl[i].src;
1128                 else
1129                         intr_mask = QLCRDX(ahw, QLCNIC_DEF_INT_MASK);
1130
1131                 sds->crb_intr_mask = ahw->pci_base0 + intr_mask;
1132                 index++;
1133         }
1134 out:
1135         qlcnic_free_mbx_args(&cmd);
1136         return err;
1137 }
1138
1139 void qlcnic_83xx_del_rx_ctx(struct qlcnic_adapter *adapter)
1140 {
1141         int err;
1142         u32 temp = 0;
1143         struct qlcnic_cmd_args cmd;
1144         struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
1145
1146         if (qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DESTROY_RX_CTX))
1147                 return;
1148
1149         if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1150                 cmd.req.arg[0] |= (0x3 << 29);
1151
1152         if (qlcnic_sriov_pf_check(adapter))
1153                 qlcnic_pf_set_interface_id_del_rx_ctx(adapter, &temp);
1154
1155         cmd.req.arg[1] = recv_ctx->context_id | temp;
1156         err = qlcnic_issue_cmd(adapter, &cmd);
1157         if (err)
1158                 dev_err(&adapter->pdev->dev,
1159                         "Failed to destroy rx ctx in firmware\n");
1160
1161         recv_ctx->state = QLCNIC_HOST_CTX_STATE_FREED;
1162         qlcnic_free_mbx_args(&cmd);
1163 }
1164
1165 int qlcnic_83xx_create_rx_ctx(struct qlcnic_adapter *adapter)
1166 {
1167         int i, err, index, sds_mbx_size, rds_mbx_size;
1168         u8 num_sds, num_rds;
1169         u32 *buf, intrpt_id, intr_mask, cap = 0;
1170         struct qlcnic_host_sds_ring *sds;
1171         struct qlcnic_host_rds_ring *rds;
1172         struct qlcnic_sds_mbx sds_mbx;
1173         struct qlcnic_rds_mbx rds_mbx;
1174         struct qlcnic_cmd_args cmd;
1175         struct qlcnic_rcv_mbx_out *mbx_out;
1176         struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
1177         struct qlcnic_hardware_context *ahw = adapter->ahw;
1178         num_rds = adapter->max_rds_rings;
1179
1180         if (adapter->drv_sds_rings <= QLCNIC_MAX_SDS_RINGS)
1181                 num_sds = adapter->drv_sds_rings;
1182         else
1183                 num_sds = QLCNIC_MAX_SDS_RINGS;
1184
1185         sds_mbx_size = sizeof(struct qlcnic_sds_mbx);
1186         rds_mbx_size = sizeof(struct qlcnic_rds_mbx);
1187         cap = QLCNIC_CAP0_LEGACY_CONTEXT;
1188
1189         if (adapter->flags & QLCNIC_FW_LRO_MSS_CAP)
1190                 cap |= QLC_83XX_FW_CAP_LRO_MSS;
1191
1192         /* set mailbox hdr and capabilities */
1193         err = qlcnic_alloc_mbx_args(&cmd, adapter,
1194                                     QLCNIC_CMD_CREATE_RX_CTX);
1195         if (err)
1196                 return err;
1197
1198         if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1199                 cmd.req.arg[0] |= (0x3 << 29);
1200
1201         cmd.req.arg[1] = cap;
1202         cmd.req.arg[5] = 1 | (num_rds << 5) | (num_sds << 8) |
1203                          (QLC_83XX_HOST_RDS_MODE_UNIQUE << 16);
1204
1205         if (qlcnic_sriov_pf_check(adapter))
1206                 qlcnic_pf_set_interface_id_create_rx_ctx(adapter,
1207                                                          &cmd.req.arg[6]);
1208         /* set up status rings, mbx 8-57/87 */
1209         index = QLC_83XX_HOST_SDS_MBX_IDX;
1210         for (i = 0; i < num_sds; i++) {
1211                 memset(&sds_mbx, 0, sds_mbx_size);
1212                 sds = &recv_ctx->sds_rings[i];
1213                 sds->consumer = 0;
1214                 memset(sds->desc_head, 0, STATUS_DESC_RINGSIZE(sds));
1215                 sds_mbx.phy_addr_low = LSD(sds->phys_addr);
1216                 sds_mbx.phy_addr_high = MSD(sds->phys_addr);
1217                 sds_mbx.sds_ring_size = sds->num_desc;
1218                 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1219                         intrpt_id = ahw->intr_tbl[i].id;
1220                 else
1221                         intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
1222                 if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
1223                         sds_mbx.intrpt_id = intrpt_id;
1224                 else
1225                         sds_mbx.intrpt_id = 0xffff;
1226                 sds_mbx.intrpt_val = 0;
1227                 buf = &cmd.req.arg[index];
1228                 memcpy(buf, &sds_mbx, sds_mbx_size);
1229                 index += sds_mbx_size / sizeof(u32);
1230         }
1231         /* set up receive rings, mbx 88-111/135 */
1232         index = QLCNIC_HOST_RDS_MBX_IDX;
1233         rds = &recv_ctx->rds_rings[0];
1234         rds->producer = 0;
1235         memset(&rds_mbx, 0, rds_mbx_size);
1236         rds_mbx.phy_addr_reg_low = LSD(rds->phys_addr);
1237         rds_mbx.phy_addr_reg_high = MSD(rds->phys_addr);
1238         rds_mbx.reg_ring_sz = rds->dma_size;
1239         rds_mbx.reg_ring_len = rds->num_desc;
1240         /* Jumbo ring */
1241         rds = &recv_ctx->rds_rings[1];
1242         rds->producer = 0;
1243         rds_mbx.phy_addr_jmb_low = LSD(rds->phys_addr);
1244         rds_mbx.phy_addr_jmb_high = MSD(rds->phys_addr);
1245         rds_mbx.jmb_ring_sz = rds->dma_size;
1246         rds_mbx.jmb_ring_len = rds->num_desc;
1247         buf = &cmd.req.arg[index];
1248         memcpy(buf, &rds_mbx, rds_mbx_size);
1249
1250         /* send the mailbox command */
1251         err = ahw->hw_ops->mbx_cmd(adapter, &cmd);
1252         if (err) {
1253                 dev_err(&adapter->pdev->dev,
1254                         "Failed to create Rx ctx in firmware%d\n", err);
1255                 goto out;
1256         }
1257         mbx_out = (struct qlcnic_rcv_mbx_out *)&cmd.rsp.arg[1];
1258         recv_ctx->context_id = mbx_out->ctx_id;
1259         recv_ctx->state = mbx_out->state;
1260         recv_ctx->virt_port = mbx_out->vport_id;
1261         dev_info(&adapter->pdev->dev, "Rx Context[%d] Created, state:0x%x\n",
1262                  recv_ctx->context_id, recv_ctx->state);
1263         /* Receive descriptor ring */
1264         /* Standard ring */
1265         rds = &recv_ctx->rds_rings[0];
1266         rds->crb_rcv_producer = ahw->pci_base0 +
1267                                 mbx_out->host_prod[0].reg_buf;
1268         /* Jumbo ring */
1269         rds = &recv_ctx->rds_rings[1];
1270         rds->crb_rcv_producer = ahw->pci_base0 +
1271                                 mbx_out->host_prod[0].jmb_buf;
1272         /* status descriptor ring */
1273         for (i = 0; i < num_sds; i++) {
1274                 sds = &recv_ctx->sds_rings[i];
1275                 sds->crb_sts_consumer = ahw->pci_base0 +
1276                                         mbx_out->host_csmr[i];
1277                 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1278                         intr_mask = ahw->intr_tbl[i].src;
1279                 else
1280                         intr_mask = QLCRDX(ahw, QLCNIC_DEF_INT_MASK);
1281                 sds->crb_intr_mask = ahw->pci_base0 + intr_mask;
1282         }
1283
1284         if (adapter->drv_sds_rings > QLCNIC_MAX_SDS_RINGS)
1285                 err = qlcnic_83xx_add_rings(adapter);
1286 out:
1287         qlcnic_free_mbx_args(&cmd);
1288         return err;
1289 }
1290
1291 void qlcnic_83xx_del_tx_ctx(struct qlcnic_adapter *adapter,
1292                             struct qlcnic_host_tx_ring *tx_ring)
1293 {
1294         struct qlcnic_cmd_args cmd;
1295         u32 temp = 0;
1296
1297         if (qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DESTROY_TX_CTX))
1298                 return;
1299
1300         if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1301                 cmd.req.arg[0] |= (0x3 << 29);
1302
1303         if (qlcnic_sriov_pf_check(adapter))
1304                 qlcnic_pf_set_interface_id_del_tx_ctx(adapter, &temp);
1305
1306         cmd.req.arg[1] = tx_ring->ctx_id | temp;
1307         if (qlcnic_issue_cmd(adapter, &cmd))
1308                 dev_err(&adapter->pdev->dev,
1309                         "Failed to destroy tx ctx in firmware\n");
1310         qlcnic_free_mbx_args(&cmd);
1311 }
1312
1313 int qlcnic_83xx_create_tx_ctx(struct qlcnic_adapter *adapter,
1314                               struct qlcnic_host_tx_ring *tx, int ring)
1315 {
1316         int err;
1317         u16 msix_id;
1318         u32 *buf, intr_mask, temp = 0;
1319         struct qlcnic_cmd_args cmd;
1320         struct qlcnic_tx_mbx mbx;
1321         struct qlcnic_tx_mbx_out *mbx_out;
1322         struct qlcnic_hardware_context *ahw = adapter->ahw;
1323         u32 msix_vector;
1324
1325         /* Reset host resources */
1326         tx->producer = 0;
1327         tx->sw_consumer = 0;
1328         *(tx->hw_consumer) = 0;
1329
1330         memset(&mbx, 0, sizeof(struct qlcnic_tx_mbx));
1331
1332         /* setup mailbox inbox registerss */
1333         mbx.phys_addr_low = LSD(tx->phys_addr);
1334         mbx.phys_addr_high = MSD(tx->phys_addr);
1335         mbx.cnsmr_index_low = LSD(tx->hw_cons_phys_addr);
1336         mbx.cnsmr_index_high = MSD(tx->hw_cons_phys_addr);
1337         mbx.size = tx->num_desc;
1338         if (adapter->flags & QLCNIC_MSIX_ENABLED) {
1339                 if (!(adapter->flags & QLCNIC_TX_INTR_SHARED))
1340                         msix_vector = adapter->drv_sds_rings + ring;
1341                 else
1342                         msix_vector = adapter->drv_sds_rings - 1;
1343                 msix_id = ahw->intr_tbl[msix_vector].id;
1344         } else {
1345                 msix_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
1346         }
1347
1348         if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
1349                 mbx.intr_id = msix_id;
1350         else
1351                 mbx.intr_id = 0xffff;
1352         mbx.src = 0;
1353
1354         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CREATE_TX_CTX);
1355         if (err)
1356                 return err;
1357
1358         if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1359                 cmd.req.arg[0] |= (0x3 << 29);
1360
1361         if (qlcnic_sriov_pf_check(adapter))
1362                 qlcnic_pf_set_interface_id_create_tx_ctx(adapter, &temp);
1363
1364         cmd.req.arg[1] = QLCNIC_CAP0_LEGACY_CONTEXT;
1365         cmd.req.arg[5] = QLCNIC_SINGLE_RING | temp;
1366
1367         buf = &cmd.req.arg[6];
1368         memcpy(buf, &mbx, sizeof(struct qlcnic_tx_mbx));
1369         /* send the mailbox command*/
1370         err = qlcnic_issue_cmd(adapter, &cmd);
1371         if (err) {
1372                 netdev_err(adapter->netdev,
1373                            "Failed to create Tx ctx in firmware 0x%x\n", err);
1374                 goto out;
1375         }
1376         mbx_out = (struct qlcnic_tx_mbx_out *)&cmd.rsp.arg[2];
1377         tx->crb_cmd_producer = ahw->pci_base0 + mbx_out->host_prod;
1378         tx->ctx_id = mbx_out->ctx_id;
1379         if ((adapter->flags & QLCNIC_MSIX_ENABLED) &&
1380             !(adapter->flags & QLCNIC_TX_INTR_SHARED)) {
1381                 intr_mask = ahw->intr_tbl[adapter->drv_sds_rings + ring].src;
1382                 tx->crb_intr_mask = ahw->pci_base0 + intr_mask;
1383         }
1384         netdev_info(adapter->netdev,
1385                     "Tx Context[0x%x] Created, state:0x%x\n",
1386                     tx->ctx_id, mbx_out->state);
1387 out:
1388         qlcnic_free_mbx_args(&cmd);
1389         return err;
1390 }
1391
1392 static int qlcnic_83xx_diag_alloc_res(struct net_device *netdev, int test,
1393                                       u8 num_sds_ring)
1394 {
1395         struct qlcnic_adapter *adapter = netdev_priv(netdev);
1396         struct qlcnic_host_sds_ring *sds_ring;
1397         struct qlcnic_host_rds_ring *rds_ring;
1398         u16 adapter_state = adapter->is_up;
1399         u8 ring;
1400         int ret;
1401
1402         netif_device_detach(netdev);
1403
1404         if (netif_running(netdev))
1405                 __qlcnic_down(adapter, netdev);
1406
1407         qlcnic_detach(adapter);
1408
1409         adapter->drv_sds_rings = QLCNIC_SINGLE_RING;
1410         adapter->ahw->diag_test = test;
1411         adapter->ahw->linkup = 0;
1412
1413         ret = qlcnic_attach(adapter);
1414         if (ret) {
1415                 netif_device_attach(netdev);
1416                 return ret;
1417         }
1418
1419         ret = qlcnic_fw_create_ctx(adapter);
1420         if (ret) {
1421                 qlcnic_detach(adapter);
1422                 if (adapter_state == QLCNIC_ADAPTER_UP_MAGIC) {
1423                         adapter->drv_sds_rings = num_sds_ring;
1424                         qlcnic_attach(adapter);
1425                 }
1426                 netif_device_attach(netdev);
1427                 return ret;
1428         }
1429
1430         for (ring = 0; ring < adapter->max_rds_rings; ring++) {
1431                 rds_ring = &adapter->recv_ctx->rds_rings[ring];
1432                 qlcnic_post_rx_buffers(adapter, rds_ring, ring);
1433         }
1434
1435         if (adapter->ahw->diag_test == QLCNIC_INTERRUPT_TEST) {
1436                 for (ring = 0; ring < adapter->drv_sds_rings; ring++) {
1437                         sds_ring = &adapter->recv_ctx->sds_rings[ring];
1438                         qlcnic_enable_sds_intr(adapter, sds_ring);
1439                 }
1440         }
1441
1442         if (adapter->ahw->diag_test == QLCNIC_LOOPBACK_TEST) {
1443                 adapter->ahw->loopback_state = 0;
1444                 adapter->ahw->hw_ops->setup_link_event(adapter, 1);
1445         }
1446
1447         set_bit(__QLCNIC_DEV_UP, &adapter->state);
1448         return 0;
1449 }
1450
1451 static void qlcnic_83xx_diag_free_res(struct net_device *netdev,
1452                                       u8 drv_sds_rings)
1453 {
1454         struct qlcnic_adapter *adapter = netdev_priv(netdev);
1455         struct qlcnic_host_sds_ring *sds_ring;
1456         int ring;
1457
1458         clear_bit(__QLCNIC_DEV_UP, &adapter->state);
1459         if (adapter->ahw->diag_test == QLCNIC_INTERRUPT_TEST) {
1460                 for (ring = 0; ring < adapter->drv_sds_rings; ring++) {
1461                         sds_ring = &adapter->recv_ctx->sds_rings[ring];
1462                         if (adapter->flags & QLCNIC_MSIX_ENABLED)
1463                                 qlcnic_disable_sds_intr(adapter, sds_ring);
1464                 }
1465         }
1466
1467         qlcnic_fw_destroy_ctx(adapter);
1468         qlcnic_detach(adapter);
1469
1470         adapter->ahw->diag_test = 0;
1471         adapter->drv_sds_rings = drv_sds_rings;
1472
1473         if (qlcnic_attach(adapter))
1474                 goto out;
1475
1476         if (netif_running(netdev))
1477                 __qlcnic_up(adapter, netdev);
1478
1479 out:
1480         netif_device_attach(netdev);
1481 }
1482
1483 static void qlcnic_83xx_get_beacon_state(struct qlcnic_adapter *adapter)
1484 {
1485         struct qlcnic_hardware_context *ahw = adapter->ahw;
1486         struct qlcnic_cmd_args cmd;
1487         u8 beacon_state;
1488         int err = 0;
1489
1490         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_LED_CONFIG);
1491         if (!err) {
1492                 err = qlcnic_issue_cmd(adapter, &cmd);
1493                 if (!err) {
1494                         beacon_state = cmd.rsp.arg[4];
1495                         if (beacon_state == QLCNIC_BEACON_DISABLE)
1496                                 ahw->beacon_state = QLC_83XX_BEACON_OFF;
1497                         else if (beacon_state == QLC_83XX_ENABLE_BEACON)
1498                                 ahw->beacon_state = QLC_83XX_BEACON_ON;
1499                 }
1500         } else {
1501                 netdev_err(adapter->netdev, "Get beacon state failed, err=%d\n",
1502                            err);
1503         }
1504
1505         qlcnic_free_mbx_args(&cmd);
1506
1507         return;
1508 }
1509
1510 int qlcnic_83xx_config_led(struct qlcnic_adapter *adapter, u32 state,
1511                            u32 beacon)
1512 {
1513         struct qlcnic_cmd_args cmd;
1514         u32 mbx_in;
1515         int i, status = 0;
1516
1517         if (state) {
1518                 /* Get LED configuration */
1519                 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1520                                                QLCNIC_CMD_GET_LED_CONFIG);
1521                 if (status)
1522                         return status;
1523
1524                 status = qlcnic_issue_cmd(adapter, &cmd);
1525                 if (status) {
1526                         dev_err(&adapter->pdev->dev,
1527                                 "Get led config failed.\n");
1528                         goto mbx_err;
1529                 } else {
1530                         for (i = 0; i < 4; i++)
1531                                 adapter->ahw->mbox_reg[i] = cmd.rsp.arg[i+1];
1532                 }
1533                 qlcnic_free_mbx_args(&cmd);
1534                 /* Set LED Configuration */
1535                 mbx_in = (LSW(QLC_83XX_LED_CONFIG) << 16) |
1536                           LSW(QLC_83XX_LED_CONFIG);
1537                 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1538                                                QLCNIC_CMD_SET_LED_CONFIG);
1539                 if (status)
1540                         return status;
1541
1542                 cmd.req.arg[1] = mbx_in;
1543                 cmd.req.arg[2] = mbx_in;
1544                 cmd.req.arg[3] = mbx_in;
1545                 if (beacon)
1546                         cmd.req.arg[4] = QLC_83XX_ENABLE_BEACON;
1547                 status = qlcnic_issue_cmd(adapter, &cmd);
1548                 if (status) {
1549                         dev_err(&adapter->pdev->dev,
1550                                 "Set led config failed.\n");
1551                 }
1552 mbx_err:
1553                 qlcnic_free_mbx_args(&cmd);
1554                 return status;
1555
1556         } else {
1557                 /* Restoring default LED configuration */
1558                 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1559                                                QLCNIC_CMD_SET_LED_CONFIG);
1560                 if (status)
1561                         return status;
1562
1563                 cmd.req.arg[1] = adapter->ahw->mbox_reg[0];
1564                 cmd.req.arg[2] = adapter->ahw->mbox_reg[1];
1565                 cmd.req.arg[3] = adapter->ahw->mbox_reg[2];
1566                 if (beacon)
1567                         cmd.req.arg[4] = adapter->ahw->mbox_reg[3];
1568                 status = qlcnic_issue_cmd(adapter, &cmd);
1569                 if (status)
1570                         dev_err(&adapter->pdev->dev,
1571                                 "Restoring led config failed.\n");
1572                 qlcnic_free_mbx_args(&cmd);
1573                 return status;
1574         }
1575 }
1576
1577 int  qlcnic_83xx_set_led(struct net_device *netdev,
1578                          enum ethtool_phys_id_state state)
1579 {
1580         struct qlcnic_adapter *adapter = netdev_priv(netdev);
1581         int err = -EIO, active = 1;
1582
1583         if (adapter->ahw->op_mode == QLCNIC_NON_PRIV_FUNC) {
1584                 netdev_warn(netdev,
1585                             "LED test is not supported in non-privileged mode\n");
1586                 return -EOPNOTSUPP;
1587         }
1588
1589         switch (state) {
1590         case ETHTOOL_ID_ACTIVE:
1591                 if (test_and_set_bit(__QLCNIC_LED_ENABLE, &adapter->state))
1592                         return -EBUSY;
1593
1594                 if (test_bit(__QLCNIC_RESETTING, &adapter->state))
1595                         break;
1596
1597                 err = qlcnic_83xx_config_led(adapter, active, 0);
1598                 if (err)
1599                         netdev_err(netdev, "Failed to set LED blink state\n");
1600                 break;
1601         case ETHTOOL_ID_INACTIVE:
1602                 active = 0;
1603
1604                 if (test_bit(__QLCNIC_RESETTING, &adapter->state))
1605                         break;
1606
1607                 err = qlcnic_83xx_config_led(adapter, active, 0);
1608                 if (err)
1609                         netdev_err(netdev, "Failed to reset LED blink state\n");
1610                 break;
1611
1612         default:
1613                 return -EINVAL;
1614         }
1615
1616         if (!active || err)
1617                 clear_bit(__QLCNIC_LED_ENABLE, &adapter->state);
1618
1619         return err;
1620 }
1621
1622 void qlcnic_83xx_initialize_nic(struct qlcnic_adapter *adapter, int enable)
1623 {
1624         struct qlcnic_cmd_args cmd;
1625         int status;
1626
1627         if (qlcnic_sriov_vf_check(adapter))
1628                 return;
1629
1630         if (enable)
1631                 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1632                                                QLCNIC_CMD_INIT_NIC_FUNC);
1633         else
1634                 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1635                                                QLCNIC_CMD_STOP_NIC_FUNC);
1636
1637         if (status)
1638                 return;
1639
1640         cmd.req.arg[1] = QLC_REGISTER_LB_IDC | QLC_INIT_FW_RESOURCES;
1641
1642         if (adapter->dcb)
1643                 cmd.req.arg[1] |= QLC_REGISTER_DCB_AEN;
1644
1645         status = qlcnic_issue_cmd(adapter, &cmd);
1646         if (status)
1647                 dev_err(&adapter->pdev->dev,
1648                         "Failed to %s in NIC IDC function event.\n",
1649                         (enable ? "register" : "unregister"));
1650
1651         qlcnic_free_mbx_args(&cmd);
1652 }
1653
1654 static int qlcnic_83xx_set_port_config(struct qlcnic_adapter *adapter)
1655 {
1656         struct qlcnic_cmd_args cmd;
1657         int err;
1658
1659         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_PORT_CONFIG);
1660         if (err)
1661                 return err;
1662
1663         cmd.req.arg[1] = adapter->ahw->port_config;
1664         err = qlcnic_issue_cmd(adapter, &cmd);
1665         if (err)
1666                 dev_info(&adapter->pdev->dev, "Set Port Config failed.\n");
1667         qlcnic_free_mbx_args(&cmd);
1668         return err;
1669 }
1670
1671 static int qlcnic_83xx_get_port_config(struct qlcnic_adapter *adapter)
1672 {
1673         struct qlcnic_cmd_args cmd;
1674         int err;
1675
1676         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_PORT_CONFIG);
1677         if (err)
1678                 return err;
1679
1680         err = qlcnic_issue_cmd(adapter, &cmd);
1681         if (err)
1682                 dev_info(&adapter->pdev->dev, "Get Port config failed\n");
1683         else
1684                 adapter->ahw->port_config = cmd.rsp.arg[1];
1685         qlcnic_free_mbx_args(&cmd);
1686         return err;
1687 }
1688
1689 int qlcnic_83xx_setup_link_event(struct qlcnic_adapter *adapter, int enable)
1690 {
1691         int err;
1692         u32 temp;
1693         struct qlcnic_cmd_args cmd;
1694
1695         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_LINK_EVENT);
1696         if (err)
1697                 return err;
1698
1699         temp = adapter->recv_ctx->context_id << 16;
1700         cmd.req.arg[1] = (enable ? 1 : 0) | BIT_8 | temp;
1701         err = qlcnic_issue_cmd(adapter, &cmd);
1702         if (err)
1703                 dev_info(&adapter->pdev->dev,
1704                          "Setup linkevent mailbox failed\n");
1705         qlcnic_free_mbx_args(&cmd);
1706         return err;
1707 }
1708
1709 static void qlcnic_83xx_set_interface_id_promisc(struct qlcnic_adapter *adapter,
1710                                                  u32 *interface_id)
1711 {
1712         if (qlcnic_sriov_pf_check(adapter)) {
1713                 qlcnic_alloc_lb_filters_mem(adapter);
1714                 qlcnic_pf_set_interface_id_promisc(adapter, interface_id);
1715                 adapter->rx_mac_learn = true;
1716         } else {
1717                 if (!qlcnic_sriov_vf_check(adapter))
1718                         *interface_id = adapter->recv_ctx->context_id << 16;
1719         }
1720 }
1721
1722 int qlcnic_83xx_nic_set_promisc(struct qlcnic_adapter *adapter, u32 mode)
1723 {
1724         struct qlcnic_cmd_args *cmd = NULL;
1725         u32 temp = 0;
1726         int err;
1727
1728         if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
1729                 return -EIO;
1730
1731         cmd = kzalloc(sizeof(*cmd), GFP_ATOMIC);
1732         if (!cmd)
1733                 return -ENOMEM;
1734
1735         err = qlcnic_alloc_mbx_args(cmd, adapter,
1736                                     QLCNIC_CMD_CONFIGURE_MAC_RX_MODE);
1737         if (err)
1738                 goto out;
1739
1740         cmd->type = QLC_83XX_MBX_CMD_NO_WAIT;
1741         qlcnic_83xx_set_interface_id_promisc(adapter, &temp);
1742
1743         if (qlcnic_84xx_check(adapter) && qlcnic_sriov_pf_check(adapter))
1744                 mode = VPORT_MISS_MODE_ACCEPT_ALL;
1745
1746         cmd->req.arg[1] = mode | temp;
1747         err = qlcnic_issue_cmd(adapter, cmd);
1748         if (!err)
1749                 return err;
1750
1751         qlcnic_free_mbx_args(cmd);
1752
1753 out:
1754         kfree(cmd);
1755         return err;
1756 }
1757
1758 int qlcnic_83xx_loopback_test(struct net_device *netdev, u8 mode)
1759 {
1760         struct qlcnic_adapter *adapter = netdev_priv(netdev);
1761         struct qlcnic_hardware_context *ahw = adapter->ahw;
1762         u8 drv_sds_rings = adapter->drv_sds_rings;
1763         u8 drv_tx_rings = adapter->drv_tx_rings;
1764         int ret = 0, loop = 0;
1765
1766         if (ahw->op_mode == QLCNIC_NON_PRIV_FUNC) {
1767                 netdev_warn(netdev,
1768                             "Loopback test not supported in non privileged mode\n");
1769                 return -ENOTSUPP;
1770         }
1771
1772         if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1773                 netdev_info(netdev, "Device is resetting\n");
1774                 return -EBUSY;
1775         }
1776
1777         if (qlcnic_get_diag_lock(adapter)) {
1778                 netdev_info(netdev, "Device is in diagnostics mode\n");
1779                 return -EBUSY;
1780         }
1781
1782         netdev_info(netdev, "%s loopback test in progress\n",
1783                     mode == QLCNIC_ILB_MODE ? "internal" : "external");
1784
1785         ret = qlcnic_83xx_diag_alloc_res(netdev, QLCNIC_LOOPBACK_TEST,
1786                                          drv_sds_rings);
1787         if (ret)
1788                 goto fail_diag_alloc;
1789
1790         ret = qlcnic_83xx_set_lb_mode(adapter, mode);
1791         if (ret)
1792                 goto free_diag_res;
1793
1794         /* Poll for link up event before running traffic */
1795         do {
1796                 msleep(QLC_83XX_LB_MSLEEP_COUNT);
1797
1798                 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1799                         netdev_info(netdev,
1800                                     "Device is resetting, free LB test resources\n");
1801                         ret = -EBUSY;
1802                         goto free_diag_res;
1803                 }
1804                 if (loop++ > QLC_83XX_LB_WAIT_COUNT) {
1805                         netdev_info(netdev,
1806                                     "Firmware didn't sent link up event to loopback request\n");
1807                         ret = -ETIMEDOUT;
1808                         qlcnic_83xx_clear_lb_mode(adapter, mode);
1809                         goto free_diag_res;
1810                 }
1811         } while ((adapter->ahw->linkup && ahw->has_link_events) != 1);
1812
1813         ret = qlcnic_do_lb_test(adapter, mode);
1814
1815         qlcnic_83xx_clear_lb_mode(adapter, mode);
1816
1817 free_diag_res:
1818         qlcnic_83xx_diag_free_res(netdev, drv_sds_rings);
1819
1820 fail_diag_alloc:
1821         adapter->drv_sds_rings = drv_sds_rings;
1822         adapter->drv_tx_rings = drv_tx_rings;
1823         qlcnic_release_diag_lock(adapter);
1824         return ret;
1825 }
1826
1827 static void qlcnic_extend_lb_idc_cmpltn_wait(struct qlcnic_adapter *adapter,
1828                                              u32 *max_wait_count)
1829 {
1830         struct qlcnic_hardware_context *ahw = adapter->ahw;
1831         int temp;
1832
1833         netdev_info(adapter->netdev, "Received loopback IDC time extend event for 0x%x seconds\n",
1834                     ahw->extend_lb_time);
1835         temp = ahw->extend_lb_time * 1000;
1836         *max_wait_count += temp / QLC_83XX_LB_MSLEEP_COUNT;
1837         ahw->extend_lb_time = 0;
1838 }
1839
1840 static int qlcnic_83xx_set_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
1841 {
1842         struct qlcnic_hardware_context *ahw = adapter->ahw;
1843         struct net_device *netdev = adapter->netdev;
1844         u32 config, max_wait_count;
1845         int status = 0, loop = 0;
1846
1847         ahw->extend_lb_time = 0;
1848         max_wait_count = QLC_83XX_LB_WAIT_COUNT;
1849         status = qlcnic_83xx_get_port_config(adapter);
1850         if (status)
1851                 return status;
1852
1853         config = ahw->port_config;
1854
1855         /* Check if port is already in loopback mode */
1856         if ((config & QLC_83XX_CFG_LOOPBACK_HSS) ||
1857             (config & QLC_83XX_CFG_LOOPBACK_EXT)) {
1858                 netdev_err(netdev,
1859                            "Port already in Loopback mode.\n");
1860                 return -EINPROGRESS;
1861         }
1862
1863         set_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1864
1865         if (mode == QLCNIC_ILB_MODE)
1866                 ahw->port_config |= QLC_83XX_CFG_LOOPBACK_HSS;
1867         if (mode == QLCNIC_ELB_MODE)
1868                 ahw->port_config |= QLC_83XX_CFG_LOOPBACK_EXT;
1869
1870         status = qlcnic_83xx_set_port_config(adapter);
1871         if (status) {
1872                 netdev_err(netdev,
1873                            "Failed to Set Loopback Mode = 0x%x.\n",
1874                            ahw->port_config);
1875                 ahw->port_config = config;
1876                 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1877                 return status;
1878         }
1879
1880         /* Wait for Link and IDC Completion AEN */
1881         do {
1882                 msleep(QLC_83XX_LB_MSLEEP_COUNT);
1883
1884                 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1885                         netdev_info(netdev,
1886                                     "Device is resetting, free LB test resources\n");
1887                         clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1888                         return -EBUSY;
1889                 }
1890
1891                 if (ahw->extend_lb_time)
1892                         qlcnic_extend_lb_idc_cmpltn_wait(adapter,
1893                                                          &max_wait_count);
1894
1895                 if (loop++ > max_wait_count) {
1896                         netdev_err(netdev, "%s: Did not receive loopback IDC completion AEN\n",
1897                                    __func__);
1898                         clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1899                         qlcnic_83xx_clear_lb_mode(adapter, mode);
1900                         return -ETIMEDOUT;
1901                 }
1902         } while (test_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status));
1903
1904         qlcnic_sre_macaddr_change(adapter, adapter->mac_addr, 0,
1905                                   QLCNIC_MAC_ADD);
1906         return status;
1907 }
1908
1909 static int qlcnic_83xx_clear_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
1910 {
1911         struct qlcnic_hardware_context *ahw = adapter->ahw;
1912         u32 config = ahw->port_config, max_wait_count;
1913         struct net_device *netdev = adapter->netdev;
1914         int status = 0, loop = 0;
1915
1916         ahw->extend_lb_time = 0;
1917         max_wait_count = QLC_83XX_LB_WAIT_COUNT;
1918         set_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1919         if (mode == QLCNIC_ILB_MODE)
1920                 ahw->port_config &= ~QLC_83XX_CFG_LOOPBACK_HSS;
1921         if (mode == QLCNIC_ELB_MODE)
1922                 ahw->port_config &= ~QLC_83XX_CFG_LOOPBACK_EXT;
1923
1924         status = qlcnic_83xx_set_port_config(adapter);
1925         if (status) {
1926                 netdev_err(netdev,
1927                            "Failed to Clear Loopback Mode = 0x%x.\n",
1928                            ahw->port_config);
1929                 ahw->port_config = config;
1930                 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1931                 return status;
1932         }
1933
1934         /* Wait for Link and IDC Completion AEN */
1935         do {
1936                 msleep(QLC_83XX_LB_MSLEEP_COUNT);
1937
1938                 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1939                         netdev_info(netdev,
1940                                     "Device is resetting, free LB test resources\n");
1941                         clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1942                         return -EBUSY;
1943                 }
1944
1945                 if (ahw->extend_lb_time)
1946                         qlcnic_extend_lb_idc_cmpltn_wait(adapter,
1947                                                          &max_wait_count);
1948
1949                 if (loop++ > max_wait_count) {
1950                         netdev_err(netdev, "%s: Did not receive loopback IDC completion AEN\n",
1951                                    __func__);
1952                         clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1953                         return -ETIMEDOUT;
1954                 }
1955         } while (test_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status));
1956
1957         qlcnic_sre_macaddr_change(adapter, adapter->mac_addr, 0,
1958                                   QLCNIC_MAC_DEL);
1959         return status;
1960 }
1961
1962 static void qlcnic_83xx_set_interface_id_ipaddr(struct qlcnic_adapter *adapter,
1963                                                 u32 *interface_id)
1964 {
1965         if (qlcnic_sriov_pf_check(adapter)) {
1966                 qlcnic_pf_set_interface_id_ipaddr(adapter, interface_id);
1967         } else {
1968                 if (!qlcnic_sriov_vf_check(adapter))
1969                         *interface_id = adapter->recv_ctx->context_id << 16;
1970         }
1971 }
1972
1973 void qlcnic_83xx_config_ipaddr(struct qlcnic_adapter *adapter, __be32 ip,
1974                                int mode)
1975 {
1976         int err;
1977         u32 temp = 0, temp_ip;
1978         struct qlcnic_cmd_args cmd;
1979
1980         err = qlcnic_alloc_mbx_args(&cmd, adapter,
1981                                     QLCNIC_CMD_CONFIGURE_IP_ADDR);
1982         if (err)
1983                 return;
1984
1985         qlcnic_83xx_set_interface_id_ipaddr(adapter, &temp);
1986
1987         if (mode == QLCNIC_IP_UP)
1988                 cmd.req.arg[1] = 1 | temp;
1989         else
1990                 cmd.req.arg[1] = 2 | temp;
1991
1992         /*
1993          * Adapter needs IP address in network byte order.
1994          * But hardware mailbox registers go through writel(), hence IP address
1995          * gets swapped on big endian architecture.
1996          * To negate swapping of writel() on big endian architecture
1997          * use swab32(value).
1998          */
1999
2000         temp_ip = swab32(ntohl(ip));
2001         memcpy(&cmd.req.arg[2], &temp_ip, sizeof(u32));
2002         err = qlcnic_issue_cmd(adapter, &cmd);
2003         if (err != QLCNIC_RCODE_SUCCESS)
2004                 dev_err(&adapter->netdev->dev,
2005                         "could not notify %s IP 0x%x request\n",
2006                         (mode == QLCNIC_IP_UP) ? "Add" : "Remove", ip);
2007
2008         qlcnic_free_mbx_args(&cmd);
2009 }
2010
2011 int qlcnic_83xx_config_hw_lro(struct qlcnic_adapter *adapter, int mode)
2012 {
2013         int err;
2014         u32 temp, arg1;
2015         struct qlcnic_cmd_args cmd;
2016         int lro_bit_mask;
2017
2018         lro_bit_mask = (mode ? (BIT_0 | BIT_1 | BIT_2 | BIT_3) : 0);
2019
2020         if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
2021                 return 0;
2022
2023         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIGURE_HW_LRO);
2024         if (err)
2025                 return err;
2026
2027         temp = adapter->recv_ctx->context_id << 16;
2028         arg1 = lro_bit_mask | temp;
2029         cmd.req.arg[1] = arg1;
2030
2031         err = qlcnic_issue_cmd(adapter, &cmd);
2032         if (err)
2033                 dev_info(&adapter->pdev->dev, "LRO config failed\n");
2034         qlcnic_free_mbx_args(&cmd);
2035
2036         return err;
2037 }
2038
2039 int qlcnic_83xx_config_rss(struct qlcnic_adapter *adapter, int enable)
2040 {
2041         int err;
2042         u32 word;
2043         struct qlcnic_cmd_args cmd;
2044         const u64 key[] = { 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
2045                             0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
2046                             0x255b0ec26d5a56daULL };
2047
2048         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIGURE_RSS);
2049         if (err)
2050                 return err;
2051         /*
2052          * RSS request:
2053          * bits 3-0: Rsvd
2054          *      5-4: hash_type_ipv4
2055          *      7-6: hash_type_ipv6
2056          *        8: enable
2057          *        9: use indirection table
2058          *    16-31: indirection table mask
2059          */
2060         word =  ((u32)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
2061                 ((u32)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
2062                 ((u32)(enable & 0x1) << 8) |
2063                 ((0x7ULL) << 16);
2064         cmd.req.arg[1] = (adapter->recv_ctx->context_id);
2065         cmd.req.arg[2] = word;
2066         memcpy(&cmd.req.arg[4], key, sizeof(key));
2067
2068         err = qlcnic_issue_cmd(adapter, &cmd);
2069
2070         if (err)
2071                 dev_info(&adapter->pdev->dev, "RSS config failed\n");
2072         qlcnic_free_mbx_args(&cmd);
2073
2074         return err;
2075
2076 }
2077
2078 static void qlcnic_83xx_set_interface_id_macaddr(struct qlcnic_adapter *adapter,
2079                                                  u32 *interface_id)
2080 {
2081         if (qlcnic_sriov_pf_check(adapter)) {
2082                 qlcnic_pf_set_interface_id_macaddr(adapter, interface_id);
2083         } else {
2084                 if (!qlcnic_sriov_vf_check(adapter))
2085                         *interface_id = adapter->recv_ctx->context_id << 16;
2086         }
2087 }
2088
2089 int qlcnic_83xx_sre_macaddr_change(struct qlcnic_adapter *adapter, u8 *addr,
2090                                    u16 vlan_id, u8 op)
2091 {
2092         struct qlcnic_cmd_args *cmd = NULL;
2093         struct qlcnic_macvlan_mbx mv;
2094         u32 *buf, temp = 0;
2095         int err;
2096
2097         if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
2098                 return -EIO;
2099
2100         cmd = kzalloc(sizeof(*cmd), GFP_ATOMIC);
2101         if (!cmd)
2102                 return -ENOMEM;
2103
2104         err = qlcnic_alloc_mbx_args(cmd, adapter, QLCNIC_CMD_CONFIG_MAC_VLAN);
2105         if (err)
2106                 goto out;
2107
2108         cmd->type = QLC_83XX_MBX_CMD_NO_WAIT;
2109
2110         if (vlan_id)
2111                 op = (op == QLCNIC_MAC_ADD || op == QLCNIC_MAC_VLAN_ADD) ?
2112                      QLCNIC_MAC_VLAN_ADD : QLCNIC_MAC_VLAN_DEL;
2113
2114         cmd->req.arg[1] = op | (1 << 8);
2115         qlcnic_83xx_set_interface_id_macaddr(adapter, &temp);
2116         cmd->req.arg[1] |= temp;
2117         mv.vlan = vlan_id;
2118         mv.mac_addr0 = addr[0];
2119         mv.mac_addr1 = addr[1];
2120         mv.mac_addr2 = addr[2];
2121         mv.mac_addr3 = addr[3];
2122         mv.mac_addr4 = addr[4];
2123         mv.mac_addr5 = addr[5];
2124         buf = &cmd->req.arg[2];
2125         memcpy(buf, &mv, sizeof(struct qlcnic_macvlan_mbx));
2126         err = qlcnic_issue_cmd(adapter, cmd);
2127         if (!err)
2128                 return err;
2129
2130         qlcnic_free_mbx_args(cmd);
2131 out:
2132         kfree(cmd);
2133         return err;
2134 }
2135
2136 void qlcnic_83xx_change_l2_filter(struct qlcnic_adapter *adapter, u64 *addr,
2137                                   u16 vlan_id)
2138 {
2139         u8 mac[ETH_ALEN];
2140         memcpy(&mac, addr, ETH_ALEN);
2141         qlcnic_83xx_sre_macaddr_change(adapter, mac, vlan_id, QLCNIC_MAC_ADD);
2142 }
2143
2144 static void qlcnic_83xx_configure_mac(struct qlcnic_adapter *adapter, u8 *mac,
2145                                       u8 type, struct qlcnic_cmd_args *cmd)
2146 {
2147         switch (type) {
2148         case QLCNIC_SET_STATION_MAC:
2149         case QLCNIC_SET_FAC_DEF_MAC:
2150                 memcpy(&cmd->req.arg[2], mac, sizeof(u32));
2151                 memcpy(&cmd->req.arg[3], &mac[4], sizeof(u16));
2152                 break;
2153         }
2154         cmd->req.arg[1] = type;
2155 }
2156
2157 int qlcnic_83xx_get_mac_address(struct qlcnic_adapter *adapter, u8 *mac,
2158                                 u8 function)
2159 {
2160         int err, i;
2161         struct qlcnic_cmd_args cmd;
2162         u32 mac_low, mac_high;
2163
2164         function = 0;
2165         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_MAC_ADDRESS);
2166         if (err)
2167                 return err;
2168
2169         qlcnic_83xx_configure_mac(adapter, mac, QLCNIC_GET_CURRENT_MAC, &cmd);
2170         err = qlcnic_issue_cmd(adapter, &cmd);
2171
2172         if (err == QLCNIC_RCODE_SUCCESS) {
2173                 mac_low = cmd.rsp.arg[1];
2174                 mac_high = cmd.rsp.arg[2];
2175
2176                 for (i = 0; i < 2; i++)
2177                         mac[i] = (u8) (mac_high >> ((1 - i) * 8));
2178                 for (i = 2; i < 6; i++)
2179                         mac[i] = (u8) (mac_low >> ((5 - i) * 8));
2180         } else {
2181                 dev_err(&adapter->pdev->dev, "Failed to get mac address%d\n",
2182                         err);
2183                 err = -EIO;
2184         }
2185         qlcnic_free_mbx_args(&cmd);
2186         return err;
2187 }
2188
2189 static int qlcnic_83xx_set_rx_intr_coal(struct qlcnic_adapter *adapter)
2190 {
2191         struct qlcnic_nic_intr_coalesce *coal = &adapter->ahw->coal;
2192         struct qlcnic_cmd_args cmd;
2193         u16 temp;
2194         int err;
2195
2196         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_INTR_COAL);
2197         if (err)
2198                 return err;
2199
2200         temp = adapter->recv_ctx->context_id;
2201         cmd.req.arg[1] = QLCNIC_INTR_COAL_TYPE_RX | temp << 16;
2202         temp = coal->rx_time_us;
2203         cmd.req.arg[2] = coal->rx_packets | temp << 16;
2204         cmd.req.arg[3] = coal->flag;
2205
2206         err = qlcnic_issue_cmd(adapter, &cmd);
2207         if (err != QLCNIC_RCODE_SUCCESS)
2208                 netdev_err(adapter->netdev,
2209                            "failed to set interrupt coalescing parameters\n");
2210
2211         qlcnic_free_mbx_args(&cmd);
2212
2213         return err;
2214 }
2215
2216 static int qlcnic_83xx_set_tx_intr_coal(struct qlcnic_adapter *adapter)
2217 {
2218         struct qlcnic_nic_intr_coalesce *coal = &adapter->ahw->coal;
2219         struct qlcnic_cmd_args cmd;
2220         u16 temp;
2221         int err;
2222
2223         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_INTR_COAL);
2224         if (err)
2225                 return err;
2226
2227         temp = adapter->tx_ring->ctx_id;
2228         cmd.req.arg[1] = QLCNIC_INTR_COAL_TYPE_TX | temp << 16;
2229         temp = coal->tx_time_us;
2230         cmd.req.arg[2] = coal->tx_packets | temp << 16;
2231         cmd.req.arg[3] = coal->flag;
2232
2233         err = qlcnic_issue_cmd(adapter, &cmd);
2234         if (err != QLCNIC_RCODE_SUCCESS)
2235                 netdev_err(adapter->netdev,
2236                            "failed to set interrupt coalescing  parameters\n");
2237
2238         qlcnic_free_mbx_args(&cmd);
2239
2240         return err;
2241 }
2242
2243 int qlcnic_83xx_set_rx_tx_intr_coal(struct qlcnic_adapter *adapter)
2244 {
2245         int err = 0;
2246
2247         err = qlcnic_83xx_set_rx_intr_coal(adapter);
2248         if (err)
2249                 netdev_err(adapter->netdev,
2250                            "failed to set Rx coalescing parameters\n");
2251
2252         err = qlcnic_83xx_set_tx_intr_coal(adapter);
2253         if (err)
2254                 netdev_err(adapter->netdev,
2255                            "failed to set Tx coalescing parameters\n");
2256
2257         return err;
2258 }
2259
2260 int qlcnic_83xx_config_intr_coal(struct qlcnic_adapter *adapter,
2261                                  struct ethtool_coalesce *ethcoal)
2262 {
2263         struct qlcnic_nic_intr_coalesce *coal = &adapter->ahw->coal;
2264         u32 rx_coalesce_usecs, rx_max_frames;
2265         u32 tx_coalesce_usecs, tx_max_frames;
2266         int err;
2267
2268         if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
2269                 return -EIO;
2270
2271         tx_coalesce_usecs = ethcoal->tx_coalesce_usecs;
2272         tx_max_frames = ethcoal->tx_max_coalesced_frames;
2273         rx_coalesce_usecs = ethcoal->rx_coalesce_usecs;
2274         rx_max_frames = ethcoal->rx_max_coalesced_frames;
2275         coal->flag = QLCNIC_INTR_DEFAULT;
2276
2277         if ((coal->rx_time_us == rx_coalesce_usecs) &&
2278             (coal->rx_packets == rx_max_frames)) {
2279                 coal->type = QLCNIC_INTR_COAL_TYPE_TX;
2280                 coal->tx_time_us = tx_coalesce_usecs;
2281                 coal->tx_packets = tx_max_frames;
2282         } else if ((coal->tx_time_us == tx_coalesce_usecs) &&
2283                    (coal->tx_packets == tx_max_frames)) {
2284                 coal->type = QLCNIC_INTR_COAL_TYPE_RX;
2285                 coal->rx_time_us = rx_coalesce_usecs;
2286                 coal->rx_packets = rx_max_frames;
2287         } else {
2288                 coal->type = QLCNIC_INTR_COAL_TYPE_RX_TX;
2289                 coal->rx_time_us = rx_coalesce_usecs;
2290                 coal->rx_packets = rx_max_frames;
2291                 coal->tx_time_us = tx_coalesce_usecs;
2292                 coal->tx_packets = tx_max_frames;
2293         }
2294
2295         switch (coal->type) {
2296         case QLCNIC_INTR_COAL_TYPE_RX:
2297                 err = qlcnic_83xx_set_rx_intr_coal(adapter);
2298                 break;
2299         case QLCNIC_INTR_COAL_TYPE_TX:
2300                 err = qlcnic_83xx_set_tx_intr_coal(adapter);
2301                 break;
2302         case QLCNIC_INTR_COAL_TYPE_RX_TX:
2303                 err = qlcnic_83xx_set_rx_tx_intr_coal(adapter);
2304                 break;
2305         default:
2306                 err = -EINVAL;
2307                 netdev_err(adapter->netdev,
2308                            "Invalid Interrupt coalescing type\n");
2309                 break;
2310         }
2311
2312         return err;
2313 }
2314
2315 static void qlcnic_83xx_handle_link_aen(struct qlcnic_adapter *adapter,
2316                                         u32 data[])
2317 {
2318         struct qlcnic_hardware_context *ahw = adapter->ahw;
2319         u8 link_status, duplex;
2320         /* link speed */
2321         link_status = LSB(data[3]) & 1;
2322         if (link_status) {
2323                 ahw->link_speed = MSW(data[2]);
2324                 duplex = LSB(MSW(data[3]));
2325                 if (duplex)
2326                         ahw->link_duplex = DUPLEX_FULL;
2327                 else
2328                         ahw->link_duplex = DUPLEX_HALF;
2329         } else {
2330                 ahw->link_speed = SPEED_UNKNOWN;
2331                 ahw->link_duplex = DUPLEX_UNKNOWN;
2332         }
2333
2334         ahw->link_autoneg = MSB(MSW(data[3]));
2335         ahw->module_type = MSB(LSW(data[3]));
2336         ahw->has_link_events = 1;
2337         ahw->lb_mode = data[4] & QLCNIC_LB_MODE_MASK;
2338         qlcnic_advert_link_change(adapter, link_status);
2339 }
2340
2341 static irqreturn_t qlcnic_83xx_handle_aen(int irq, void *data)
2342 {
2343         struct qlcnic_adapter *adapter = data;
2344         struct qlcnic_mailbox *mbx;
2345         u32 mask, resp, event;
2346         unsigned long flags;
2347
2348         mbx = adapter->ahw->mailbox;
2349         spin_lock_irqsave(&mbx->aen_lock, flags);
2350         resp = QLCRDX(adapter->ahw, QLCNIC_FW_MBX_CTRL);
2351         if (!(resp & QLCNIC_SET_OWNER))
2352                 goto out;
2353
2354         event = readl(QLCNIC_MBX_FW(adapter->ahw, 0));
2355         if (event &  QLCNIC_MBX_ASYNC_EVENT)
2356                 __qlcnic_83xx_process_aen(adapter);
2357         else
2358                 qlcnic_83xx_notify_mbx_response(mbx);
2359
2360 out:
2361         mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
2362         writel(0, adapter->ahw->pci_base0 + mask);
2363         spin_unlock_irqrestore(&mbx->aen_lock, flags);
2364         return IRQ_HANDLED;
2365 }
2366
2367 int qlcnic_83xx_set_nic_info(struct qlcnic_adapter *adapter,
2368                              struct qlcnic_info *nic)
2369 {
2370         int i, err = -EIO;
2371         struct qlcnic_cmd_args cmd;
2372
2373         if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC) {
2374                 dev_err(&adapter->pdev->dev,
2375                         "%s: Error, invoked by non management func\n",
2376                         __func__);
2377                 return err;
2378         }
2379
2380         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_NIC_INFO);
2381         if (err)
2382                 return err;
2383
2384         cmd.req.arg[1] = (nic->pci_func << 16);
2385         cmd.req.arg[2] = 0x1 << 16;
2386         cmd.req.arg[3] = nic->phys_port | (nic->switch_mode << 16);
2387         cmd.req.arg[4] = nic->capabilities;
2388         cmd.req.arg[5] = (nic->max_mac_filters & 0xFF) | ((nic->max_mtu) << 16);
2389         cmd.req.arg[6] = (nic->max_tx_ques) | ((nic->max_rx_ques) << 16);
2390         cmd.req.arg[7] = (nic->min_tx_bw) | ((nic->max_tx_bw) << 16);
2391         for (i = 8; i < 32; i++)
2392                 cmd.req.arg[i] = 0;
2393
2394         err = qlcnic_issue_cmd(adapter, &cmd);
2395
2396         if (err != QLCNIC_RCODE_SUCCESS) {
2397                 dev_err(&adapter->pdev->dev, "Failed to set nic info%d\n",
2398                         err);
2399                 err = -EIO;
2400         }
2401
2402         qlcnic_free_mbx_args(&cmd);
2403
2404         return err;
2405 }
2406
2407 int qlcnic_83xx_get_nic_info(struct qlcnic_adapter *adapter,
2408                              struct qlcnic_info *npar_info, u8 func_id)
2409 {
2410         int err;
2411         u32 temp;
2412         u8 op = 0;
2413         struct qlcnic_cmd_args cmd;
2414         struct qlcnic_hardware_context *ahw = adapter->ahw;
2415
2416         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_NIC_INFO);
2417         if (err)
2418                 return err;
2419
2420         if (func_id != ahw->pci_func) {
2421                 temp = func_id << 16;
2422                 cmd.req.arg[1] = op | BIT_31 | temp;
2423         } else {
2424                 cmd.req.arg[1] = ahw->pci_func << 16;
2425         }
2426         err = qlcnic_issue_cmd(adapter, &cmd);
2427         if (err) {
2428                 dev_info(&adapter->pdev->dev,
2429                          "Failed to get nic info %d\n", err);
2430                 goto out;
2431         }
2432
2433         npar_info->op_type = cmd.rsp.arg[1];
2434         npar_info->pci_func = cmd.rsp.arg[2] & 0xFFFF;
2435         npar_info->op_mode = (cmd.rsp.arg[2] & 0xFFFF0000) >> 16;
2436         npar_info->phys_port = cmd.rsp.arg[3] & 0xFFFF;
2437         npar_info->switch_mode = (cmd.rsp.arg[3] & 0xFFFF0000) >> 16;
2438         npar_info->capabilities = cmd.rsp.arg[4];
2439         npar_info->max_mac_filters = cmd.rsp.arg[5] & 0xFF;
2440         npar_info->max_mtu = (cmd.rsp.arg[5] & 0xFFFF0000) >> 16;
2441         npar_info->max_tx_ques = cmd.rsp.arg[6] & 0xFFFF;
2442         npar_info->max_rx_ques = (cmd.rsp.arg[6] & 0xFFFF0000) >> 16;
2443         npar_info->min_tx_bw = cmd.rsp.arg[7] & 0xFFFF;
2444         npar_info->max_tx_bw = (cmd.rsp.arg[7] & 0xFFFF0000) >> 16;
2445         if (cmd.rsp.arg[8] & 0x1)
2446                 npar_info->max_bw_reg_offset = (cmd.rsp.arg[8] & 0x7FFE) >> 1;
2447         if (cmd.rsp.arg[8] & 0x10000) {
2448                 temp = (cmd.rsp.arg[8] & 0x7FFE0000) >> 17;
2449                 npar_info->max_linkspeed_reg_offset = temp;
2450         }
2451
2452         memcpy(ahw->extra_capability, &cmd.rsp.arg[16],
2453                sizeof(ahw->extra_capability));
2454
2455 out:
2456         qlcnic_free_mbx_args(&cmd);
2457         return err;
2458 }
2459
2460 int qlcnic_get_pci_func_type(struct qlcnic_adapter *adapter, u16 type,
2461                              u16 *nic, u16 *fcoe, u16 *iscsi)
2462 {
2463         struct device *dev = &adapter->pdev->dev;
2464         int err = 0;
2465
2466         switch (type) {
2467         case QLCNIC_TYPE_NIC:
2468                 (*nic)++;
2469                 break;
2470         case QLCNIC_TYPE_FCOE:
2471                 (*fcoe)++;
2472                 break;
2473         case QLCNIC_TYPE_ISCSI:
2474                 (*iscsi)++;
2475                 break;
2476         default:
2477                 dev_err(dev, "%s: Unknown PCI type[%x]\n",
2478                         __func__, type);
2479                 err = -EIO;
2480         }
2481
2482         return err;
2483 }
2484
2485 int qlcnic_83xx_get_pci_info(struct qlcnic_adapter *adapter,
2486                              struct qlcnic_pci_info *pci_info)
2487 {
2488         struct qlcnic_hardware_context *ahw = adapter->ahw;
2489         struct device *dev = &adapter->pdev->dev;
2490         u16 nic = 0, fcoe = 0, iscsi = 0;
2491         struct qlcnic_cmd_args cmd;
2492         int i, err = 0, j = 0;
2493         u32 temp;
2494
2495         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_PCI_INFO);
2496         if (err)
2497                 return err;
2498
2499         err = qlcnic_issue_cmd(adapter, &cmd);
2500
2501         ahw->total_nic_func = 0;
2502         if (err == QLCNIC_RCODE_SUCCESS) {
2503                 ahw->max_pci_func = cmd.rsp.arg[1] & 0xFF;
2504                 for (i = 2, j = 0; j < ahw->max_vnic_func; j++, pci_info++) {
2505                         pci_info->id = cmd.rsp.arg[i] & 0xFFFF;
2506                         pci_info->active = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16;
2507                         i++;
2508                         if (!pci_info->active) {
2509                                 i += QLC_SKIP_INACTIVE_PCI_REGS;
2510                                 continue;
2511                         }
2512                         pci_info->type = cmd.rsp.arg[i] & 0xFFFF;
2513                         err = qlcnic_get_pci_func_type(adapter, pci_info->type,
2514                                                        &nic, &fcoe, &iscsi);
2515                         temp = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16;
2516                         pci_info->default_port = temp;
2517                         i++;
2518                         pci_info->tx_min_bw = cmd.rsp.arg[i] & 0xFFFF;
2519                         temp = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16;
2520                         pci_info->tx_max_bw = temp;
2521                         i = i + 2;
2522                         memcpy(pci_info->mac, &cmd.rsp.arg[i], ETH_ALEN - 2);
2523                         i++;
2524                         memcpy(pci_info->mac + sizeof(u32), &cmd.rsp.arg[i], 2);
2525                         i = i + 3;
2526                 }
2527         } else {
2528                 dev_err(dev, "Failed to get PCI Info, error = %d\n", err);
2529                 err = -EIO;
2530         }
2531
2532         ahw->total_nic_func = nic;
2533         ahw->total_pci_func = nic + fcoe + iscsi;
2534         if (ahw->total_nic_func == 0 || ahw->total_pci_func == 0) {
2535                 dev_err(dev, "%s: Invalid function count: total nic func[%x], total pci func[%x]\n",
2536                         __func__, ahw->total_nic_func, ahw->total_pci_func);
2537                 err = -EIO;
2538         }
2539         qlcnic_free_mbx_args(&cmd);
2540
2541         return err;
2542 }
2543
2544 int qlcnic_83xx_config_intrpt(struct qlcnic_adapter *adapter, bool op_type)
2545 {
2546         int i, index, err;
2547         u8 max_ints;
2548         u32 val, temp, type;
2549         struct qlcnic_cmd_args cmd;
2550
2551         max_ints = adapter->ahw->num_msix - 1;
2552         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_INTRPT);
2553         if (err)
2554                 return err;
2555
2556         cmd.req.arg[1] = max_ints;
2557
2558         if (qlcnic_sriov_vf_check(adapter))
2559                 cmd.req.arg[1] |= (adapter->ahw->pci_func << 8) | BIT_16;
2560
2561         for (i = 0, index = 2; i < max_ints; i++) {
2562                 type = op_type ? QLCNIC_INTRPT_ADD : QLCNIC_INTRPT_DEL;
2563                 val = type | (adapter->ahw->intr_tbl[i].type << 4);
2564                 if (adapter->ahw->intr_tbl[i].type == QLCNIC_INTRPT_MSIX)
2565                         val |= (adapter->ahw->intr_tbl[i].id << 16);
2566                 cmd.req.arg[index++] = val;
2567         }
2568         err = qlcnic_issue_cmd(adapter, &cmd);
2569         if (err) {
2570                 dev_err(&adapter->pdev->dev,
2571                         "Failed to configure interrupts 0x%x\n", err);
2572                 goto out;
2573         }
2574
2575         max_ints = cmd.rsp.arg[1];
2576         for (i = 0, index = 2; i < max_ints; i++, index += 2) {
2577                 val = cmd.rsp.arg[index];
2578                 if (LSB(val)) {
2579                         dev_info(&adapter->pdev->dev,
2580                                  "Can't configure interrupt %d\n",
2581                                  adapter->ahw->intr_tbl[i].id);
2582                         continue;
2583                 }
2584                 if (op_type) {
2585                         adapter->ahw->intr_tbl[i].id = MSW(val);
2586                         adapter->ahw->intr_tbl[i].enabled = 1;
2587                         temp = cmd.rsp.arg[index + 1];
2588                         adapter->ahw->intr_tbl[i].src = temp;
2589                 } else {
2590                         adapter->ahw->intr_tbl[i].id = i;
2591                         adapter->ahw->intr_tbl[i].enabled = 0;
2592                         adapter->ahw->intr_tbl[i].src = 0;
2593                 }
2594         }
2595 out:
2596         qlcnic_free_mbx_args(&cmd);
2597         return err;
2598 }
2599
2600 int qlcnic_83xx_lock_flash(struct qlcnic_adapter *adapter)
2601 {
2602         int id, timeout = 0;
2603         u32 status = 0;
2604
2605         while (status == 0) {
2606                 status = QLC_SHARED_REG_RD32(adapter, QLCNIC_FLASH_LOCK);
2607                 if (status)
2608                         break;
2609
2610                 if (++timeout >= QLC_83XX_FLASH_LOCK_TIMEOUT) {
2611                         id = QLC_SHARED_REG_RD32(adapter,
2612                                                  QLCNIC_FLASH_LOCK_OWNER);
2613                         dev_err(&adapter->pdev->dev,
2614                                 "%s: failed, lock held by %d\n", __func__, id);
2615                         return -EIO;
2616                 }
2617                 usleep_range(1000, 2000);
2618         }
2619
2620         QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER, adapter->portnum);
2621         return 0;
2622 }
2623
2624 void qlcnic_83xx_unlock_flash(struct qlcnic_adapter *adapter)
2625 {
2626         QLC_SHARED_REG_RD32(adapter, QLCNIC_FLASH_UNLOCK);
2627         QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER, 0xFF);
2628 }
2629
2630 int qlcnic_83xx_lockless_flash_read32(struct qlcnic_adapter *adapter,
2631                                       u32 flash_addr, u8 *p_data,
2632                                       int count)
2633 {
2634         u32 word, range, flash_offset, addr = flash_addr, ret;
2635         ulong indirect_add, direct_window;
2636         int i, err = 0;
2637
2638         flash_offset = addr & (QLCNIC_FLASH_SECTOR_SIZE - 1);
2639         if (addr & 0x3) {
2640                 dev_err(&adapter->pdev->dev, "Illegal addr = 0x%x\n", addr);
2641                 return -EIO;
2642         }
2643
2644         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_DIRECT_WINDOW,
2645                                      (addr & 0xFFFF0000));
2646
2647         range = flash_offset + (count * sizeof(u32));
2648         /* Check if data is spread across multiple sectors */
2649         if (range > (QLCNIC_FLASH_SECTOR_SIZE - 1)) {
2650
2651                 /* Multi sector read */
2652                 for (i = 0; i < count; i++) {
2653                         indirect_add = QLC_83XX_FLASH_DIRECT_DATA(addr);
2654                         ret = QLCRD32(adapter, indirect_add, &err);
2655                         if (err == -EIO)
2656                                 return err;
2657
2658                         word = ret;
2659                         *(u32 *)p_data  = word;
2660                         p_data = p_data + 4;
2661                         addr = addr + 4;
2662                         flash_offset = flash_offset + 4;
2663
2664                         if (flash_offset > (QLCNIC_FLASH_SECTOR_SIZE - 1)) {
2665                                 direct_window = QLC_83XX_FLASH_DIRECT_WINDOW;
2666                                 /* This write is needed once for each sector */
2667                                 qlcnic_83xx_wrt_reg_indirect(adapter,
2668                                                              direct_window,
2669                                                              (addr));
2670                                 flash_offset = 0;
2671                         }
2672                 }
2673         } else {
2674                 /* Single sector read */
2675                 for (i = 0; i < count; i++) {
2676                         indirect_add = QLC_83XX_FLASH_DIRECT_DATA(addr);
2677                         ret = QLCRD32(adapter, indirect_add, &err);
2678                         if (err == -EIO)
2679                                 return err;
2680
2681                         word = ret;
2682                         *(u32 *)p_data  = word;
2683                         p_data = p_data + 4;
2684                         addr = addr + 4;
2685                 }
2686         }
2687
2688         return 0;
2689 }
2690
2691 static int qlcnic_83xx_poll_flash_status_reg(struct qlcnic_adapter *adapter)
2692 {
2693         u32 status;
2694         int retries = QLC_83XX_FLASH_READ_RETRY_COUNT;
2695         int err = 0;
2696
2697         do {
2698                 status = QLCRD32(adapter, QLC_83XX_FLASH_STATUS, &err);
2699                 if (err == -EIO)
2700                         return err;
2701
2702                 if ((status & QLC_83XX_FLASH_STATUS_READY) ==
2703                     QLC_83XX_FLASH_STATUS_READY)
2704                         break;
2705
2706                 usleep_range(1000, 1100);
2707         } while (--retries);
2708
2709         if (!retries)
2710                 return -EIO;
2711
2712         return 0;
2713 }
2714
2715 int qlcnic_83xx_enable_flash_write(struct qlcnic_adapter *adapter)
2716 {
2717         int ret;
2718         u32 cmd;
2719         cmd = adapter->ahw->fdt.write_statusreg_cmd;
2720         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2721                                      (QLC_83XX_FLASH_FDT_WRITE_DEF_SIG | cmd));
2722         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2723                                      adapter->ahw->fdt.write_enable_bits);
2724         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2725                                      QLC_83XX_FLASH_SECOND_ERASE_MS_VAL);
2726         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2727         if (ret)
2728                 return -EIO;
2729
2730         return 0;
2731 }
2732
2733 int qlcnic_83xx_disable_flash_write(struct qlcnic_adapter *adapter)
2734 {
2735         int ret;
2736
2737         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2738                                      (QLC_83XX_FLASH_FDT_WRITE_DEF_SIG |
2739                                      adapter->ahw->fdt.write_statusreg_cmd));
2740         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2741                                      adapter->ahw->fdt.write_disable_bits);
2742         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2743                                      QLC_83XX_FLASH_SECOND_ERASE_MS_VAL);
2744         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2745         if (ret)
2746                 return -EIO;
2747
2748         return 0;
2749 }
2750
2751 int qlcnic_83xx_read_flash_mfg_id(struct qlcnic_adapter *adapter)
2752 {
2753         int ret, err = 0;
2754         u32 mfg_id;
2755
2756         if (qlcnic_83xx_lock_flash(adapter))
2757                 return -EIO;
2758
2759         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2760                                      QLC_83XX_FLASH_FDT_READ_MFG_ID_VAL);
2761         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2762                                      QLC_83XX_FLASH_READ_CTRL);
2763         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2764         if (ret) {
2765                 qlcnic_83xx_unlock_flash(adapter);
2766                 return -EIO;
2767         }
2768
2769         mfg_id = QLCRD32(adapter, QLC_83XX_FLASH_RDDATA, &err);
2770         if (err == -EIO) {
2771                 qlcnic_83xx_unlock_flash(adapter);
2772                 return err;
2773         }
2774
2775         adapter->flash_mfg_id = (mfg_id & 0xFF);
2776         qlcnic_83xx_unlock_flash(adapter);
2777
2778         return 0;
2779 }
2780
2781 int qlcnic_83xx_read_flash_descriptor_table(struct qlcnic_adapter *adapter)
2782 {
2783         int count, fdt_size, ret = 0;
2784
2785         fdt_size = sizeof(struct qlcnic_fdt);
2786         count = fdt_size / sizeof(u32);
2787
2788         if (qlcnic_83xx_lock_flash(adapter))
2789                 return -EIO;
2790
2791         memset(&adapter->ahw->fdt, 0, fdt_size);
2792         ret = qlcnic_83xx_lockless_flash_read32(adapter, QLCNIC_FDT_LOCATION,
2793                                                 (u8 *)&adapter->ahw->fdt,
2794                                                 count);
2795         qlcnic_swap32_buffer((u32 *)&adapter->ahw->fdt, count);
2796         qlcnic_83xx_unlock_flash(adapter);
2797         return ret;
2798 }
2799
2800 int qlcnic_83xx_erase_flash_sector(struct qlcnic_adapter *adapter,
2801                                    u32 sector_start_addr)
2802 {
2803         u32 reversed_addr, addr1, addr2, cmd;
2804         int ret = -EIO;
2805
2806         if (qlcnic_83xx_lock_flash(adapter) != 0)
2807                 return -EIO;
2808
2809         if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id) {
2810                 ret = qlcnic_83xx_enable_flash_write(adapter);
2811                 if (ret) {
2812                         qlcnic_83xx_unlock_flash(adapter);
2813                         dev_err(&adapter->pdev->dev,
2814                                 "%s failed at %d\n",
2815                                 __func__, __LINE__);
2816                         return ret;
2817                 }
2818         }
2819
2820         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2821         if (ret) {
2822                 qlcnic_83xx_unlock_flash(adapter);
2823                 dev_err(&adapter->pdev->dev,
2824                         "%s: failed at %d\n", __func__, __LINE__);
2825                 return -EIO;
2826         }
2827
2828         addr1 = (sector_start_addr & 0xFF) << 16;
2829         addr2 = (sector_start_addr & 0xFF0000) >> 16;
2830         reversed_addr = addr1 | addr2 | (sector_start_addr & 0xFF00);
2831
2832         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2833                                      reversed_addr);
2834         cmd = QLC_83XX_FLASH_FDT_ERASE_DEF_SIG | adapter->ahw->fdt.erase_cmd;
2835         if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id)
2836                 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, cmd);
2837         else
2838                 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2839                                              QLC_83XX_FLASH_OEM_ERASE_SIG);
2840         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2841                                      QLC_83XX_FLASH_LAST_ERASE_MS_VAL);
2842
2843         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2844         if (ret) {
2845                 qlcnic_83xx_unlock_flash(adapter);
2846                 dev_err(&adapter->pdev->dev,
2847                         "%s: failed at %d\n", __func__, __LINE__);
2848                 return -EIO;
2849         }
2850
2851         if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id) {
2852                 ret = qlcnic_83xx_disable_flash_write(adapter);
2853                 if (ret) {
2854                         qlcnic_83xx_unlock_flash(adapter);
2855                         dev_err(&adapter->pdev->dev,
2856                                 "%s: failed at %d\n", __func__, __LINE__);
2857                         return ret;
2858                 }
2859         }
2860
2861         qlcnic_83xx_unlock_flash(adapter);
2862
2863         return 0;
2864 }
2865
2866 int qlcnic_83xx_flash_write32(struct qlcnic_adapter *adapter, u32 addr,
2867                               u32 *p_data)
2868 {
2869         int ret = -EIO;
2870         u32 addr1 = 0x00800000 | (addr >> 2);
2871
2872         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, addr1);
2873         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data);
2874         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2875                                      QLC_83XX_FLASH_LAST_ERASE_MS_VAL);
2876         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2877         if (ret) {
2878                 dev_err(&adapter->pdev->dev,
2879                         "%s: failed at %d\n", __func__, __LINE__);
2880                 return -EIO;
2881         }
2882
2883         return 0;
2884 }
2885
2886 int qlcnic_83xx_flash_bulk_write(struct qlcnic_adapter *adapter, u32 addr,
2887                                  u32 *p_data, int count)
2888 {
2889         u32 temp;
2890         int ret = -EIO, err = 0;
2891
2892         if ((count < QLC_83XX_FLASH_WRITE_MIN) ||
2893             (count > QLC_83XX_FLASH_WRITE_MAX)) {
2894                 dev_err(&adapter->pdev->dev,
2895                         "%s: Invalid word count\n", __func__);
2896                 return -EIO;
2897         }
2898
2899         temp = QLCRD32(adapter, QLC_83XX_FLASH_SPI_CONTROL, &err);
2900         if (err == -EIO)
2901                 return err;
2902
2903         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_SPI_CONTROL,
2904                                      (temp | QLC_83XX_FLASH_SPI_CTRL));
2905         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2906                                      QLC_83XX_FLASH_ADDR_TEMP_VAL);
2907
2908         /* First DWORD write */
2909         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data++);
2910         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2911                                      QLC_83XX_FLASH_FIRST_MS_PATTERN);
2912         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2913         if (ret) {
2914                 dev_err(&adapter->pdev->dev,
2915                         "%s: failed at %d\n", __func__, __LINE__);
2916                 return -EIO;
2917         }
2918
2919         count--;
2920         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2921                                      QLC_83XX_FLASH_ADDR_SECOND_TEMP_VAL);
2922         /* Second to N-1 DWORD writes */
2923         while (count != 1) {
2924                 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2925                                              *p_data++);
2926                 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2927                                              QLC_83XX_FLASH_SECOND_MS_PATTERN);
2928                 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2929                 if (ret) {
2930                         dev_err(&adapter->pdev->dev,
2931                                 "%s: failed at %d\n", __func__, __LINE__);
2932                         return -EIO;
2933                 }
2934                 count--;
2935         }
2936
2937         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2938                                      QLC_83XX_FLASH_ADDR_TEMP_VAL |
2939                                      (addr >> 2));
2940         /* Last DWORD write */
2941         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data++);
2942         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2943                                      QLC_83XX_FLASH_LAST_MS_PATTERN);
2944         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2945         if (ret) {
2946                 dev_err(&adapter->pdev->dev,
2947                         "%s: failed at %d\n", __func__, __LINE__);
2948                 return -EIO;
2949         }
2950
2951         ret = QLCRD32(adapter, QLC_83XX_FLASH_SPI_STATUS, &err);
2952         if (err == -EIO)
2953                 return err;
2954
2955         if ((ret & QLC_83XX_FLASH_SPI_CTRL) == QLC_83XX_FLASH_SPI_CTRL) {
2956                 dev_err(&adapter->pdev->dev, "%s: failed at %d\n",
2957                         __func__, __LINE__);
2958                 /* Operation failed, clear error bit */
2959                 temp = QLCRD32(adapter, QLC_83XX_FLASH_SPI_CONTROL, &err);
2960                 if (err == -EIO)
2961                         return err;
2962
2963                 qlcnic_83xx_wrt_reg_indirect(adapter,
2964                                              QLC_83XX_FLASH_SPI_CONTROL,
2965                                              (temp | QLC_83XX_FLASH_SPI_CTRL));
2966         }
2967
2968         return 0;
2969 }
2970
2971 static void qlcnic_83xx_recover_driver_lock(struct qlcnic_adapter *adapter)
2972 {
2973         u32 val, id;
2974
2975         val = QLCRDX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK);
2976
2977         /* Check if recovery need to be performed by the calling function */
2978         if ((val & QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK) == 0) {
2979                 val = val & ~0x3F;
2980                 val = val | ((adapter->portnum << 2) |
2981                              QLC_83XX_NEED_DRV_LOCK_RECOVERY);
2982                 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val);
2983                 dev_info(&adapter->pdev->dev,
2984                          "%s: lock recovery initiated\n", __func__);
2985                 msleep(QLC_83XX_DRV_LOCK_RECOVERY_DELAY);
2986                 val = QLCRDX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK);
2987                 id = ((val >> 2) & 0xF);
2988                 if (id == adapter->portnum) {
2989                         val = val & ~QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK;
2990                         val = val | QLC_83XX_DRV_LOCK_RECOVERY_IN_PROGRESS;
2991                         QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val);
2992                         /* Force release the lock */
2993                         QLCRDX(adapter->ahw, QLC_83XX_DRV_UNLOCK);
2994                         /* Clear recovery bits */
2995                         val = val & ~0x3F;
2996                         QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val);
2997                         dev_info(&adapter->pdev->dev,
2998                                  "%s: lock recovery completed\n", __func__);
2999                 } else {
3000                         dev_info(&adapter->pdev->dev,
3001                                  "%s: func %d to resume lock recovery process\n",
3002                                  __func__, id);
3003                 }
3004         } else {
3005                 dev_info(&adapter->pdev->dev,
3006                          "%s: lock recovery initiated by other functions\n",
3007                          __func__);
3008         }
3009 }
3010
3011 int qlcnic_83xx_lock_driver(struct qlcnic_adapter *adapter)
3012 {
3013         u32 lock_alive_counter, val, id, i = 0, status = 0, temp = 0;
3014         int max_attempt = 0;
3015
3016         while (status == 0) {
3017                 status = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK);
3018                 if (status)
3019                         break;
3020
3021                 msleep(QLC_83XX_DRV_LOCK_WAIT_DELAY);
3022                 i++;
3023
3024                 if (i == 1)
3025                         temp = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
3026
3027                 if (i == QLC_83XX_DRV_LOCK_WAIT_COUNTER) {
3028                         val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
3029                         if (val == temp) {
3030                                 id = val & 0xFF;
3031                                 dev_info(&adapter->pdev->dev,
3032                                          "%s: lock to be recovered from %d\n",
3033                                          __func__, id);
3034                                 qlcnic_83xx_recover_driver_lock(adapter);
3035                                 i = 0;
3036                                 max_attempt++;
3037                         } else {
3038                                 dev_err(&adapter->pdev->dev,
3039                                         "%s: failed to get lock\n", __func__);
3040                                 return -EIO;
3041                         }
3042                 }
3043
3044                 /* Force exit from while loop after few attempts */
3045                 if (max_attempt == QLC_83XX_MAX_DRV_LOCK_RECOVERY_ATTEMPT) {
3046                         dev_err(&adapter->pdev->dev,
3047                                 "%s: failed to get lock\n", __func__);
3048                         return -EIO;
3049                 }
3050         }
3051
3052         val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
3053         lock_alive_counter = val >> 8;
3054         lock_alive_counter++;
3055         val = lock_alive_counter << 8 | adapter->portnum;
3056         QLCWRX(adapter->ahw, QLC_83XX_DRV_LOCK_ID, val);
3057
3058         return 0;
3059 }
3060
3061 void qlcnic_83xx_unlock_driver(struct qlcnic_adapter *adapter)
3062 {
3063         u32 val, lock_alive_counter, id;
3064
3065         val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
3066         id = val & 0xFF;
3067         lock_alive_counter = val >> 8;
3068
3069         if (id != adapter->portnum)
3070                 dev_err(&adapter->pdev->dev,
3071                         "%s:Warning func %d is unlocking lock owned by %d\n",
3072                         __func__, adapter->portnum, id);
3073
3074         val = (lock_alive_counter << 8) | 0xFF;
3075         QLCWRX(adapter->ahw, QLC_83XX_DRV_LOCK_ID, val);
3076         QLCRDX(adapter->ahw, QLC_83XX_DRV_UNLOCK);
3077 }
3078
3079 int qlcnic_ms_mem_write128(struct qlcnic_adapter *adapter, u64 addr,
3080                                 u32 *data, u32 count)
3081 {
3082         int i, j, ret = 0;
3083         u32 temp;
3084
3085         /* Check alignment */
3086         if (addr & 0xF)
3087                 return -EIO;
3088
3089         mutex_lock(&adapter->ahw->mem_lock);
3090         qlcnic_ind_wr(adapter, QLCNIC_MS_ADDR_HI, 0);
3091
3092         for (i = 0; i < count; i++, addr += 16) {
3093                 if (!((ADDR_IN_RANGE(addr, QLCNIC_ADDR_QDR_NET,
3094                                      QLCNIC_ADDR_QDR_NET_MAX)) ||
3095                       (ADDR_IN_RANGE(addr, QLCNIC_ADDR_DDR_NET,
3096                                      QLCNIC_ADDR_DDR_NET_MAX)))) {
3097                         mutex_unlock(&adapter->ahw->mem_lock);
3098                         return -EIO;
3099                 }
3100
3101                 qlcnic_ind_wr(adapter, QLCNIC_MS_ADDR_LO, addr);
3102                 qlcnic_ind_wr(adapter, QLCNIC_MS_WRTDATA_LO, *data++);
3103                 qlcnic_ind_wr(adapter, QLCNIC_MS_WRTDATA_HI, *data++);
3104                 qlcnic_ind_wr(adapter, QLCNIC_MS_WRTDATA_ULO, *data++);
3105                 qlcnic_ind_wr(adapter, QLCNIC_MS_WRTDATA_UHI, *data++);
3106                 qlcnic_ind_wr(adapter, QLCNIC_MS_CTRL, QLCNIC_TA_WRITE_ENABLE);
3107                 qlcnic_ind_wr(adapter, QLCNIC_MS_CTRL, QLCNIC_TA_WRITE_START);
3108
3109                 for (j = 0; j < MAX_CTL_CHECK; j++) {
3110                         temp = qlcnic_ind_rd(adapter, QLCNIC_MS_CTRL);
3111
3112                         if ((temp & TA_CTL_BUSY) == 0)
3113                                 break;
3114                 }
3115
3116                 /* Status check failure */
3117                 if (j >= MAX_CTL_CHECK) {
3118                         printk_ratelimited(KERN_WARNING
3119                                            "MS memory write failed\n");
3120                         mutex_unlock(&adapter->ahw->mem_lock);
3121                         return -EIO;
3122                 }
3123         }
3124
3125         mutex_unlock(&adapter->ahw->mem_lock);
3126
3127         return ret;
3128 }
3129
3130 int qlcnic_83xx_flash_read32(struct qlcnic_adapter *adapter, u32 flash_addr,
3131                              u8 *p_data, int count)
3132 {
3133         u32 word, addr = flash_addr, ret;
3134         ulong  indirect_addr;
3135         int i, err = 0;
3136
3137         if (qlcnic_83xx_lock_flash(adapter) != 0)
3138                 return -EIO;
3139
3140         if (addr & 0x3) {
3141                 dev_err(&adapter->pdev->dev, "Illegal addr = 0x%x\n", addr);
3142                 qlcnic_83xx_unlock_flash(adapter);
3143                 return -EIO;
3144         }
3145
3146         for (i = 0; i < count; i++) {
3147                 if (qlcnic_83xx_wrt_reg_indirect(adapter,
3148                                                  QLC_83XX_FLASH_DIRECT_WINDOW,
3149                                                  (addr))) {
3150                         qlcnic_83xx_unlock_flash(adapter);
3151                         return -EIO;
3152                 }
3153
3154                 indirect_addr = QLC_83XX_FLASH_DIRECT_DATA(addr);
3155                 ret = QLCRD32(adapter, indirect_addr, &err);
3156                 if (err == -EIO)
3157                         return err;
3158
3159                 word = ret;
3160                 *(u32 *)p_data  = word;
3161                 p_data = p_data + 4;
3162                 addr = addr + 4;
3163         }
3164
3165         qlcnic_83xx_unlock_flash(adapter);
3166
3167         return 0;
3168 }
3169
3170 int qlcnic_83xx_test_link(struct qlcnic_adapter *adapter)
3171 {
3172         u8 pci_func;
3173         int err;
3174         u32 config = 0, state;
3175         struct qlcnic_cmd_args cmd;
3176         struct qlcnic_hardware_context *ahw = adapter->ahw;
3177
3178         if (qlcnic_sriov_vf_check(adapter))
3179                 pci_func = adapter->portnum;
3180         else
3181                 pci_func = ahw->pci_func;
3182
3183         state = readl(ahw->pci_base0 + QLC_83XX_LINK_STATE(pci_func));
3184         if (!QLC_83xx_FUNC_VAL(state, pci_func)) {
3185                 dev_info(&adapter->pdev->dev, "link state down\n");
3186                 return config;
3187         }
3188
3189         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_LINK_STATUS);
3190         if (err)
3191                 return err;
3192
3193         err = qlcnic_issue_cmd(adapter, &cmd);
3194         if (err) {
3195                 dev_info(&adapter->pdev->dev,
3196                          "Get Link Status Command failed: 0x%x\n", err);
3197                 goto out;
3198         } else {
3199                 config = cmd.rsp.arg[1];
3200                 switch (QLC_83XX_CURRENT_LINK_SPEED(config)) {
3201                 case QLC_83XX_10M_LINK:
3202                         ahw->link_speed = SPEED_10;
3203                         break;
3204                 case QLC_83XX_100M_LINK:
3205                         ahw->link_speed = SPEED_100;
3206                         break;
3207                 case QLC_83XX_1G_LINK:
3208                         ahw->link_speed = SPEED_1000;
3209                         break;
3210                 case QLC_83XX_10G_LINK:
3211                         ahw->link_speed = SPEED_10000;
3212                         break;
3213                 default:
3214                         ahw->link_speed = 0;
3215                         break;
3216                 }
3217                 config = cmd.rsp.arg[3];
3218                 switch (QLC_83XX_SFP_MODULE_TYPE(config)) {
3219                 case QLC_83XX_MODULE_FIBRE_10GBASE_LRM:
3220                 case QLC_83XX_MODULE_FIBRE_10GBASE_LR:
3221                 case QLC_83XX_MODULE_FIBRE_10GBASE_SR:
3222                         ahw->supported_type = PORT_FIBRE;
3223                         ahw->port_type = QLCNIC_XGBE;
3224                         break;
3225                 case QLC_83XX_MODULE_FIBRE_1000BASE_SX:
3226                 case QLC_83XX_MODULE_FIBRE_1000BASE_LX:
3227                 case QLC_83XX_MODULE_FIBRE_1000BASE_CX:
3228                         ahw->supported_type = PORT_FIBRE;
3229                         ahw->port_type = QLCNIC_GBE;
3230                         break;
3231                 case QLC_83XX_MODULE_TP_1000BASE_T:
3232                         ahw->supported_type = PORT_TP;
3233                         ahw->port_type = QLCNIC_GBE;
3234                         break;
3235                 case QLC_83XX_MODULE_DA_10GE_PASSIVE_CP:
3236                 case QLC_83XX_MODULE_DA_10GE_ACTIVE_CP:
3237                 case QLC_83XX_MODULE_DA_10GE_LEGACY_CP:
3238                 case QLC_83XX_MODULE_DA_1GE_PASSIVE_CP:
3239                         ahw->supported_type = PORT_DA;
3240                         ahw->port_type = QLCNIC_XGBE;
3241                         break;
3242                 default:
3243                         ahw->supported_type = PORT_OTHER;
3244                         ahw->port_type = QLCNIC_XGBE;
3245                 }
3246                 if (config & 1)
3247                         err = 1;
3248         }
3249 out:
3250         qlcnic_free_mbx_args(&cmd);
3251         return config;
3252 }
3253
3254 int qlcnic_83xx_get_settings(struct qlcnic_adapter *adapter,
3255                              struct ethtool_cmd *ecmd)
3256 {
3257         struct qlcnic_hardware_context *ahw = adapter->ahw;
3258         u32 config = 0;
3259         int status = 0;
3260
3261         if (!test_bit(__QLCNIC_MAINTENANCE_MODE, &adapter->state)) {
3262                 /* Get port configuration info */
3263                 status = qlcnic_83xx_get_port_info(adapter);
3264                 /* Get Link Status related info */
3265                 config = qlcnic_83xx_test_link(adapter);
3266                 ahw->module_type = QLC_83XX_SFP_MODULE_TYPE(config);
3267         }
3268
3269         /* hard code until there is a way to get it from flash */
3270         ahw->board_type = QLCNIC_BRDTYPE_83XX_10G;
3271
3272         if (netif_running(adapter->netdev) && ahw->has_link_events) {
3273                 ethtool_cmd_speed_set(ecmd, ahw->link_speed);
3274                 ecmd->duplex = ahw->link_duplex;
3275                 ecmd->autoneg = ahw->link_autoneg;
3276         } else {
3277                 ethtool_cmd_speed_set(ecmd, SPEED_UNKNOWN);
3278                 ecmd->duplex = DUPLEX_UNKNOWN;
3279                 ecmd->autoneg = AUTONEG_DISABLE;
3280         }
3281
3282         ecmd->supported = (SUPPORTED_10baseT_Full |
3283                            SUPPORTED_100baseT_Full |
3284                            SUPPORTED_1000baseT_Full |
3285                            SUPPORTED_10000baseT_Full |
3286                            SUPPORTED_Autoneg);
3287
3288         if (ecmd->autoneg == AUTONEG_ENABLE) {
3289                 if (ahw->port_config & QLC_83XX_10_CAPABLE)
3290                         ecmd->advertising |= SUPPORTED_10baseT_Full;
3291                 if (ahw->port_config & QLC_83XX_100_CAPABLE)
3292                         ecmd->advertising |= SUPPORTED_100baseT_Full;
3293                 if (ahw->port_config & QLC_83XX_1G_CAPABLE)
3294                         ecmd->advertising |= SUPPORTED_1000baseT_Full;
3295                 if (ahw->port_config & QLC_83XX_10G_CAPABLE)
3296                         ecmd->advertising |= SUPPORTED_10000baseT_Full;
3297                 if (ahw->port_config & QLC_83XX_AUTONEG_ENABLE)
3298                         ecmd->advertising |= ADVERTISED_Autoneg;
3299         } else {
3300                 switch (ahw->link_speed) {
3301                 case SPEED_10:
3302                         ecmd->advertising = SUPPORTED_10baseT_Full;
3303                         break;
3304                 case SPEED_100:
3305                         ecmd->advertising = SUPPORTED_100baseT_Full;
3306                         break;
3307                 case SPEED_1000:
3308                         ecmd->advertising = SUPPORTED_1000baseT_Full;
3309                         break;
3310                 case SPEED_10000:
3311                         ecmd->advertising = SUPPORTED_10000baseT_Full;
3312                         break;
3313                 default:
3314                         break;
3315                 }
3316
3317         }
3318
3319         switch (ahw->supported_type) {
3320         case PORT_FIBRE:
3321                 ecmd->supported |= SUPPORTED_FIBRE;
3322                 ecmd->advertising |= ADVERTISED_FIBRE;
3323                 ecmd->port = PORT_FIBRE;
3324                 ecmd->transceiver = XCVR_EXTERNAL;
3325                 break;
3326         case PORT_TP:
3327                 ecmd->supported |= SUPPORTED_TP;
3328                 ecmd->advertising |= ADVERTISED_TP;
3329                 ecmd->port = PORT_TP;
3330                 ecmd->transceiver = XCVR_INTERNAL;
3331                 break;
3332         case PORT_DA:
3333                 ecmd->supported |= SUPPORTED_FIBRE;
3334                 ecmd->advertising |= ADVERTISED_FIBRE;
3335                 ecmd->port = PORT_DA;
3336                 ecmd->transceiver = XCVR_EXTERNAL;
3337                 break;
3338         default:
3339                 ecmd->supported |= SUPPORTED_FIBRE;
3340                 ecmd->advertising |= ADVERTISED_FIBRE;
3341                 ecmd->port = PORT_OTHER;
3342                 ecmd->transceiver = XCVR_EXTERNAL;
3343                 break;
3344         }
3345         ecmd->phy_address = ahw->physical_port;
3346         return status;
3347 }
3348
3349 int qlcnic_83xx_set_settings(struct qlcnic_adapter *adapter,
3350                              struct ethtool_cmd *ecmd)
3351 {
3352         struct qlcnic_hardware_context *ahw = adapter->ahw;
3353         u32 config = adapter->ahw->port_config;
3354         int status = 0;
3355
3356         /* 83xx devices do not support Half duplex */
3357         if (ecmd->duplex == DUPLEX_HALF) {
3358                         netdev_info(adapter->netdev,
3359                                     "Half duplex mode not supported\n");
3360                         return -EINVAL;
3361         }
3362
3363         if (ecmd->autoneg) {
3364                 ahw->port_config |= QLC_83XX_AUTONEG_ENABLE;
3365                 ahw->port_config |= (QLC_83XX_100_CAPABLE |
3366                                      QLC_83XX_1G_CAPABLE |
3367                                      QLC_83XX_10G_CAPABLE);
3368         } else { /* force speed */
3369                 ahw->port_config &= ~QLC_83XX_AUTONEG_ENABLE;
3370                 switch (ethtool_cmd_speed(ecmd)) {
3371                 case SPEED_10:
3372                         ahw->port_config &= ~(QLC_83XX_100_CAPABLE |
3373                                               QLC_83XX_1G_CAPABLE |
3374                                               QLC_83XX_10G_CAPABLE);
3375                         ahw->port_config |= QLC_83XX_10_CAPABLE;
3376                         break;
3377                 case SPEED_100:
3378                         ahw->port_config &= ~(QLC_83XX_10_CAPABLE |
3379                                               QLC_83XX_1G_CAPABLE |
3380                                               QLC_83XX_10G_CAPABLE);
3381                         ahw->port_config |= QLC_83XX_100_CAPABLE;
3382                         break;
3383                 case SPEED_1000:
3384                         ahw->port_config &= ~(QLC_83XX_10_CAPABLE |
3385                                               QLC_83XX_100_CAPABLE |
3386                                               QLC_83XX_10G_CAPABLE);
3387                         ahw->port_config |= QLC_83XX_1G_CAPABLE;
3388                         break;
3389                 case SPEED_10000:
3390                         ahw->port_config &= ~(QLC_83XX_10_CAPABLE |
3391                                               QLC_83XX_100_CAPABLE |
3392                                               QLC_83XX_1G_CAPABLE);
3393                         ahw->port_config |= QLC_83XX_10G_CAPABLE;
3394                         break;
3395                 default:
3396                         return -EINVAL;
3397                 }
3398         }
3399         status = qlcnic_83xx_set_port_config(adapter);
3400         if (status) {
3401                 netdev_info(adapter->netdev,
3402                             "Failed to Set Link Speed and autoneg.\n");
3403                 ahw->port_config = config;
3404         }
3405
3406         return status;
3407 }
3408
3409 static inline u64 *qlcnic_83xx_copy_stats(struct qlcnic_cmd_args *cmd,
3410                                           u64 *data, int index)
3411 {
3412         u32 low, hi;
3413         u64 val;
3414
3415         low = cmd->rsp.arg[index];
3416         hi = cmd->rsp.arg[index + 1];
3417         val = (((u64) low) | (((u64) hi) << 32));
3418         *data++ = val;
3419         return data;
3420 }
3421
3422 static u64 *qlcnic_83xx_fill_stats(struct qlcnic_adapter *adapter,
3423                                    struct qlcnic_cmd_args *cmd, u64 *data,
3424                                    int type, int *ret)
3425 {
3426         int err, k, total_regs;
3427
3428         *ret = 0;
3429         err = qlcnic_issue_cmd(adapter, cmd);
3430         if (err != QLCNIC_RCODE_SUCCESS) {
3431                 dev_info(&adapter->pdev->dev,
3432                          "Error in get statistics mailbox command\n");
3433                 *ret = -EIO;
3434                 return data;
3435         }
3436         total_regs = cmd->rsp.num;
3437         switch (type) {
3438         case QLC_83XX_STAT_MAC:
3439                 /* fill in MAC tx counters */
3440                 for (k = 2; k < 28; k += 2)
3441                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3442                 /* skip 24 bytes of reserved area */
3443                 /* fill in MAC rx counters */
3444                 for (k += 6; k < 60; k += 2)
3445                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3446                 /* skip 24 bytes of reserved area */
3447                 /* fill in MAC rx frame stats */
3448                 for (k += 6; k < 80; k += 2)
3449                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3450                 /* fill in eSwitch stats */
3451                 for (; k < total_regs; k += 2)
3452                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3453                 break;
3454         case QLC_83XX_STAT_RX:
3455                 for (k = 2; k < 8; k += 2)
3456                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3457                 /* skip 8 bytes of reserved data */
3458                 for (k += 2; k < 24; k += 2)
3459                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3460                 /* skip 8 bytes containing RE1FBQ error data */
3461                 for (k += 2; k < total_regs; k += 2)
3462                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3463                 break;
3464         case QLC_83XX_STAT_TX:
3465                 for (k = 2; k < 10; k += 2)
3466                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3467                 /* skip 8 bytes of reserved data */
3468                 for (k += 2; k < total_regs; k += 2)
3469                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3470                 break;
3471         default:
3472                 dev_warn(&adapter->pdev->dev, "Unknown get statistics mode\n");
3473                 *ret = -EIO;
3474         }
3475         return data;
3476 }
3477
3478 void qlcnic_83xx_get_stats(struct qlcnic_adapter *adapter, u64 *data)
3479 {
3480         struct qlcnic_cmd_args cmd;
3481         struct net_device *netdev = adapter->netdev;
3482         int ret = 0;
3483
3484         ret = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_STATISTICS);
3485         if (ret)
3486                 return;
3487         /* Get Tx stats */
3488         cmd.req.arg[1] = BIT_1 | (adapter->tx_ring->ctx_id << 16);
3489         cmd.rsp.num = QLC_83XX_TX_STAT_REGS;
3490         data = qlcnic_83xx_fill_stats(adapter, &cmd, data,
3491                                       QLC_83XX_STAT_TX, &ret);
3492         if (ret) {
3493                 netdev_err(netdev, "Error getting Tx stats\n");
3494                 goto out;
3495         }
3496         /* Get MAC stats */
3497         cmd.req.arg[1] = BIT_2 | (adapter->portnum << 16);
3498         cmd.rsp.num = QLC_83XX_MAC_STAT_REGS;
3499         memset(cmd.rsp.arg, 0, sizeof(u32) * cmd.rsp.num);
3500         data = qlcnic_83xx_fill_stats(adapter, &cmd, data,
3501                                       QLC_83XX_STAT_MAC, &ret);
3502         if (ret) {
3503                 netdev_err(netdev, "Error getting MAC stats\n");
3504                 goto out;
3505         }
3506         /* Get Rx stats */
3507         cmd.req.arg[1] = adapter->recv_ctx->context_id << 16;
3508         cmd.rsp.num = QLC_83XX_RX_STAT_REGS;
3509         memset(cmd.rsp.arg, 0, sizeof(u32) * cmd.rsp.num);
3510         data = qlcnic_83xx_fill_stats(adapter, &cmd, data,
3511                                       QLC_83XX_STAT_RX, &ret);
3512         if (ret)
3513                 netdev_err(netdev, "Error getting Rx stats\n");
3514 out:
3515         qlcnic_free_mbx_args(&cmd);
3516 }
3517
3518 #define QLCNIC_83XX_ADD_PORT0           BIT_0
3519 #define QLCNIC_83XX_ADD_PORT1           BIT_1
3520 #define QLCNIC_83XX_EXTENDED_MEM_SIZE   13 /* In MB */
3521 int qlcnic_83xx_extend_md_capab(struct qlcnic_adapter *adapter)
3522 {
3523         struct qlcnic_cmd_args cmd;
3524         int err;
3525
3526         err = qlcnic_alloc_mbx_args(&cmd, adapter,
3527                                     QLCNIC_CMD_83XX_EXTEND_ISCSI_DUMP_CAP);
3528         if (err)
3529                 return err;
3530
3531         cmd.req.arg[1] = (QLCNIC_83XX_ADD_PORT0 | QLCNIC_83XX_ADD_PORT1);
3532         cmd.req.arg[2] = QLCNIC_83XX_EXTENDED_MEM_SIZE;
3533         cmd.req.arg[3] = QLCNIC_83XX_EXTENDED_MEM_SIZE;
3534
3535         err = qlcnic_issue_cmd(adapter, &cmd);
3536         if (err)
3537                 dev_err(&adapter->pdev->dev,
3538                         "failed to issue extend iSCSI minidump capability\n");
3539
3540         return err;
3541 }
3542
3543 int qlcnic_83xx_reg_test(struct qlcnic_adapter *adapter)
3544 {
3545         u32 major, minor, sub;
3546
3547         major = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MAJOR);
3548         minor = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MINOR);
3549         sub = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_SUB);
3550
3551         if (adapter->fw_version != QLCNIC_VERSION_CODE(major, minor, sub)) {
3552                 dev_info(&adapter->pdev->dev, "%s: Reg test failed\n",
3553                          __func__);
3554                 return 1;
3555         }
3556         return 0;
3557 }
3558
3559 inline int qlcnic_83xx_get_regs_len(struct qlcnic_adapter *adapter)
3560 {
3561         return (ARRAY_SIZE(qlcnic_83xx_ext_reg_tbl) *
3562                 sizeof(*adapter->ahw->ext_reg_tbl)) +
3563                 (ARRAY_SIZE(qlcnic_83xx_reg_tbl) *
3564                 sizeof(*adapter->ahw->reg_tbl));
3565 }
3566
3567 int qlcnic_83xx_get_registers(struct qlcnic_adapter *adapter, u32 *regs_buff)
3568 {
3569         int i, j = 0;
3570
3571         for (i = QLCNIC_DEV_INFO_SIZE + 1;
3572              j < ARRAY_SIZE(qlcnic_83xx_reg_tbl); i++, j++)
3573                 regs_buff[i] = QLC_SHARED_REG_RD32(adapter, j);
3574
3575         for (j = 0; j < ARRAY_SIZE(qlcnic_83xx_ext_reg_tbl); j++)
3576                 regs_buff[i++] = QLCRDX(adapter->ahw, j);
3577         return i;
3578 }
3579
3580 int qlcnic_83xx_interrupt_test(struct net_device *netdev)
3581 {
3582         struct qlcnic_adapter *adapter = netdev_priv(netdev);
3583         struct qlcnic_hardware_context *ahw = adapter->ahw;
3584         struct qlcnic_cmd_args cmd;
3585         u8 val, drv_sds_rings = adapter->drv_sds_rings;
3586         u8 drv_tx_rings = adapter->drv_tx_rings;
3587         u32 data;
3588         u16 intrpt_id, id;
3589         int ret;
3590
3591         if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
3592                 netdev_info(netdev, "Device is resetting\n");
3593                 return -EBUSY;
3594         }
3595
3596         if (qlcnic_get_diag_lock(adapter)) {
3597                 netdev_info(netdev, "Device in diagnostics mode\n");
3598                 return -EBUSY;
3599         }
3600
3601         ret = qlcnic_83xx_diag_alloc_res(netdev, QLCNIC_INTERRUPT_TEST,
3602                                          drv_sds_rings);
3603         if (ret)
3604                 goto fail_diag_irq;
3605
3606         ahw->diag_cnt = 0;
3607         ret = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_INTRPT_TEST);
3608         if (ret)
3609                 goto fail_diag_irq;
3610
3611         if (adapter->flags & QLCNIC_MSIX_ENABLED)
3612                 intrpt_id = ahw->intr_tbl[0].id;
3613         else
3614                 intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
3615
3616         cmd.req.arg[1] = 1;
3617         cmd.req.arg[2] = intrpt_id;
3618         cmd.req.arg[3] = BIT_0;
3619
3620         ret = qlcnic_issue_cmd(adapter, &cmd);
3621         data = cmd.rsp.arg[2];
3622         id = LSW(data);
3623         val = LSB(MSW(data));
3624         if (id != intrpt_id)
3625                 dev_info(&adapter->pdev->dev,
3626                          "Interrupt generated: 0x%x, requested:0x%x\n",
3627                          id, intrpt_id);
3628         if (val)
3629                 dev_err(&adapter->pdev->dev,
3630                          "Interrupt test error: 0x%x\n", val);
3631         if (ret)
3632                 goto done;
3633
3634         msleep(20);
3635         ret = !ahw->diag_cnt;
3636
3637 done:
3638         qlcnic_free_mbx_args(&cmd);
3639         qlcnic_83xx_diag_free_res(netdev, drv_sds_rings);
3640
3641 fail_diag_irq:
3642         adapter->drv_sds_rings = drv_sds_rings;
3643         adapter->drv_tx_rings = drv_tx_rings;
3644         qlcnic_release_diag_lock(adapter);
3645         return ret;
3646 }
3647
3648 void qlcnic_83xx_get_pauseparam(struct qlcnic_adapter *adapter,
3649                                 struct ethtool_pauseparam *pause)
3650 {
3651         struct qlcnic_hardware_context *ahw = adapter->ahw;
3652         int status = 0;
3653         u32 config;
3654
3655         status = qlcnic_83xx_get_port_config(adapter);
3656         if (status) {
3657                 dev_err(&adapter->pdev->dev,
3658                         "%s: Get Pause Config failed\n", __func__);
3659                 return;
3660         }
3661         config = ahw->port_config;
3662         if (config & QLC_83XX_CFG_STD_PAUSE) {
3663                 switch (MSW(config)) {
3664                 case QLC_83XX_TX_PAUSE:
3665                         pause->tx_pause = 1;
3666                         break;
3667                 case QLC_83XX_RX_PAUSE:
3668                         pause->rx_pause = 1;
3669                         break;
3670                 case QLC_83XX_TX_RX_PAUSE:
3671                 default:
3672                         /* Backward compatibility for existing
3673                          * flash definitions
3674                          */
3675                         pause->tx_pause = 1;
3676                         pause->rx_pause = 1;
3677                 }
3678         }
3679
3680         if (QLC_83XX_AUTONEG(config))
3681                 pause->autoneg = 1;
3682 }
3683
3684 int qlcnic_83xx_set_pauseparam(struct qlcnic_adapter *adapter,
3685                                struct ethtool_pauseparam *pause)
3686 {
3687         struct qlcnic_hardware_context *ahw = adapter->ahw;
3688         int status = 0;
3689         u32 config;
3690
3691         status = qlcnic_83xx_get_port_config(adapter);
3692         if (status) {
3693                 dev_err(&adapter->pdev->dev,
3694                         "%s: Get Pause Config failed.\n", __func__);
3695                 return status;
3696         }
3697         config = ahw->port_config;
3698
3699         if (ahw->port_type == QLCNIC_GBE) {
3700                 if (pause->autoneg)
3701                         ahw->port_config |= QLC_83XX_ENABLE_AUTONEG;
3702                 if (!pause->autoneg)
3703                         ahw->port_config &= ~QLC_83XX_ENABLE_AUTONEG;
3704         } else if ((ahw->port_type == QLCNIC_XGBE) && (pause->autoneg)) {
3705                 return -EOPNOTSUPP;
3706         }
3707
3708         if (!(config & QLC_83XX_CFG_STD_PAUSE))
3709                 ahw->port_config |= QLC_83XX_CFG_STD_PAUSE;
3710
3711         if (pause->rx_pause && pause->tx_pause) {
3712                 ahw->port_config |= QLC_83XX_CFG_STD_TX_RX_PAUSE;
3713         } else if (pause->rx_pause && !pause->tx_pause) {
3714                 ahw->port_config &= ~QLC_83XX_CFG_STD_TX_PAUSE;
3715                 ahw->port_config |= QLC_83XX_CFG_STD_RX_PAUSE;
3716         } else if (pause->tx_pause && !pause->rx_pause) {
3717                 ahw->port_config &= ~QLC_83XX_CFG_STD_RX_PAUSE;
3718                 ahw->port_config |= QLC_83XX_CFG_STD_TX_PAUSE;
3719         } else if (!pause->rx_pause && !pause->tx_pause) {
3720                 ahw->port_config &= ~(QLC_83XX_CFG_STD_TX_RX_PAUSE |
3721                                       QLC_83XX_CFG_STD_PAUSE);
3722         }
3723         status = qlcnic_83xx_set_port_config(adapter);
3724         if (status) {
3725                 dev_err(&adapter->pdev->dev,
3726                         "%s: Set Pause Config failed.\n", __func__);
3727                 ahw->port_config = config;
3728         }
3729         return status;
3730 }
3731
3732 static int qlcnic_83xx_read_flash_status_reg(struct qlcnic_adapter *adapter)
3733 {
3734         int ret, err = 0;
3735         u32 temp;
3736
3737         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
3738                                      QLC_83XX_FLASH_OEM_READ_SIG);
3739         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
3740                                      QLC_83XX_FLASH_READ_CTRL);
3741         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
3742         if (ret)
3743                 return -EIO;
3744
3745         temp = QLCRD32(adapter, QLC_83XX_FLASH_RDDATA, &err);
3746         if (err == -EIO)
3747                 return err;
3748
3749         return temp & 0xFF;
3750 }
3751
3752 int qlcnic_83xx_flash_test(struct qlcnic_adapter *adapter)
3753 {
3754         int status;
3755
3756         status = qlcnic_83xx_read_flash_status_reg(adapter);
3757         if (status == -EIO) {
3758                 dev_info(&adapter->pdev->dev, "%s: EEPROM test failed.\n",
3759                          __func__);
3760                 return 1;
3761         }
3762         return 0;
3763 }
3764
3765 static int qlcnic_83xx_shutdown(struct pci_dev *pdev)
3766 {
3767         struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
3768         struct net_device *netdev = adapter->netdev;
3769         int retval;
3770
3771         netif_device_detach(netdev);
3772         qlcnic_cancel_idc_work(adapter);
3773
3774         if (netif_running(netdev))
3775                 qlcnic_down(adapter, netdev);
3776
3777         qlcnic_83xx_disable_mbx_intr(adapter);
3778         cancel_delayed_work_sync(&adapter->idc_aen_work);
3779
3780         retval = pci_save_state(pdev);
3781         if (retval)
3782                 return retval;
3783
3784         return 0;
3785 }
3786
3787 static int qlcnic_83xx_resume(struct qlcnic_adapter *adapter)
3788 {
3789         struct qlcnic_hardware_context *ahw = adapter->ahw;
3790         struct qlc_83xx_idc *idc = &ahw->idc;
3791         int err = 0;
3792
3793         err = qlcnic_83xx_idc_init(adapter);
3794         if (err)
3795                 return err;
3796
3797         if (ahw->nic_mode == QLCNIC_VNIC_MODE) {
3798                 if (ahw->op_mode == QLCNIC_MGMT_FUNC) {
3799                         qlcnic_83xx_set_vnic_opmode(adapter);
3800                 } else {
3801                         err = qlcnic_83xx_check_vnic_state(adapter);
3802                         if (err)
3803                                 return err;
3804                 }
3805         }
3806
3807         err = qlcnic_83xx_idc_reattach_driver(adapter);
3808         if (err)
3809                 return err;
3810
3811         qlcnic_schedule_work(adapter, qlcnic_83xx_idc_poll_dev_state,
3812                              idc->delay);
3813         return err;
3814 }
3815
3816 void qlcnic_83xx_reinit_mbx_work(struct qlcnic_mailbox *mbx)
3817 {
3818         reinit_completion(&mbx->completion);
3819         set_bit(QLC_83XX_MBX_READY, &mbx->status);
3820 }
3821
3822 void qlcnic_83xx_free_mailbox(struct qlcnic_mailbox *mbx)
3823 {
3824         if (!mbx)
3825                 return;
3826
3827         destroy_workqueue(mbx->work_q);
3828         kfree(mbx);
3829 }
3830
3831 static inline void
3832 qlcnic_83xx_notify_cmd_completion(struct qlcnic_adapter *adapter,
3833                                   struct qlcnic_cmd_args *cmd)
3834 {
3835         atomic_set(&cmd->rsp_status, QLC_83XX_MBX_RESPONSE_ARRIVED);
3836
3837         if (cmd->type == QLC_83XX_MBX_CMD_NO_WAIT) {
3838                 qlcnic_free_mbx_args(cmd);
3839                 kfree(cmd);
3840                 return;
3841         }
3842         complete(&cmd->completion);
3843 }
3844
3845 static void qlcnic_83xx_flush_mbx_queue(struct qlcnic_adapter *adapter)
3846 {
3847         struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3848         struct list_head *head = &mbx->cmd_q;
3849         struct qlcnic_cmd_args *cmd = NULL;
3850
3851         spin_lock(&mbx->queue_lock);
3852
3853         while (!list_empty(head)) {
3854                 cmd = list_entry(head->next, struct qlcnic_cmd_args, list);
3855                 dev_info(&adapter->pdev->dev, "%s: Mailbox command 0x%x\n",
3856                          __func__, cmd->cmd_op);
3857                 list_del(&cmd->list);
3858                 mbx->num_cmds--;
3859                 qlcnic_83xx_notify_cmd_completion(adapter, cmd);
3860         }
3861
3862         spin_unlock(&mbx->queue_lock);
3863 }
3864
3865 static int qlcnic_83xx_check_mbx_status(struct qlcnic_adapter *adapter)
3866 {
3867         struct qlcnic_hardware_context *ahw = adapter->ahw;
3868         struct qlcnic_mailbox *mbx = ahw->mailbox;
3869         u32 host_mbx_ctrl;
3870
3871         if (!test_bit(QLC_83XX_MBX_READY, &mbx->status))
3872                 return -EBUSY;
3873
3874         host_mbx_ctrl = QLCRDX(ahw, QLCNIC_HOST_MBX_CTRL);
3875         if (host_mbx_ctrl) {
3876                 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
3877                 ahw->idc.collect_dump = 1;
3878                 return -EIO;
3879         }
3880
3881         return 0;
3882 }
3883
3884 static inline void qlcnic_83xx_signal_mbx_cmd(struct qlcnic_adapter *adapter,
3885                                               u8 issue_cmd)
3886 {
3887         if (issue_cmd)
3888                 QLCWRX(adapter->ahw, QLCNIC_HOST_MBX_CTRL, QLCNIC_SET_OWNER);
3889         else
3890                 QLCWRX(adapter->ahw, QLCNIC_FW_MBX_CTRL, QLCNIC_CLR_OWNER);
3891 }
3892
3893 static void qlcnic_83xx_dequeue_mbx_cmd(struct qlcnic_adapter *adapter,
3894                                         struct qlcnic_cmd_args *cmd)
3895 {
3896         struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3897
3898         spin_lock(&mbx->queue_lock);
3899
3900         list_del(&cmd->list);
3901         mbx->num_cmds--;
3902
3903         spin_unlock(&mbx->queue_lock);
3904
3905         qlcnic_83xx_notify_cmd_completion(adapter, cmd);
3906 }
3907
3908 static void qlcnic_83xx_encode_mbx_cmd(struct qlcnic_adapter *adapter,
3909                                        struct qlcnic_cmd_args *cmd)
3910 {
3911         u32 mbx_cmd, fw_hal_version, hdr_size, total_size, tmp;
3912         struct qlcnic_hardware_context *ahw = adapter->ahw;
3913         int i, j;
3914
3915         if (cmd->op_type != QLC_83XX_MBX_POST_BC_OP) {
3916                 mbx_cmd = cmd->req.arg[0];
3917                 writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 0));
3918                 for (i = 1; i < cmd->req.num; i++)
3919                         writel(cmd->req.arg[i], QLCNIC_MBX_HOST(ahw, i));
3920         } else {
3921                 fw_hal_version = ahw->fw_hal_version;
3922                 hdr_size = sizeof(struct qlcnic_bc_hdr) / sizeof(u32);
3923                 total_size = cmd->pay_size + hdr_size;
3924                 tmp = QLCNIC_CMD_BC_EVENT_SETUP | total_size << 16;
3925                 mbx_cmd = tmp | fw_hal_version << 29;
3926                 writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 0));
3927
3928                 /* Back channel specific operations bits */
3929                 mbx_cmd = 0x1 | 1 << 4;
3930
3931                 if (qlcnic_sriov_pf_check(adapter))
3932                         mbx_cmd |= cmd->func_num << 5;
3933
3934                 writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 1));
3935
3936                 for (i = 2, j = 0; j < hdr_size; i++, j++)
3937                         writel(*(cmd->hdr++), QLCNIC_MBX_HOST(ahw, i));
3938                 for (j = 0; j < cmd->pay_size; j++, i++)
3939                         writel(*(cmd->pay++), QLCNIC_MBX_HOST(ahw, i));
3940         }
3941 }
3942
3943 void qlcnic_83xx_detach_mailbox_work(struct qlcnic_adapter *adapter)
3944 {
3945         struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3946
3947         if (!mbx)
3948                 return;
3949
3950         clear_bit(QLC_83XX_MBX_READY, &mbx->status);
3951         complete(&mbx->completion);
3952         cancel_work_sync(&mbx->work);
3953         flush_workqueue(mbx->work_q);
3954         qlcnic_83xx_flush_mbx_queue(adapter);
3955 }
3956
3957 static int qlcnic_83xx_enqueue_mbx_cmd(struct qlcnic_adapter *adapter,
3958                                        struct qlcnic_cmd_args *cmd,
3959                                        unsigned long *timeout)
3960 {
3961         struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3962
3963         if (test_bit(QLC_83XX_MBX_READY, &mbx->status)) {
3964                 atomic_set(&cmd->rsp_status, QLC_83XX_MBX_RESPONSE_WAIT);
3965                 init_completion(&cmd->completion);
3966                 cmd->rsp_opcode = QLC_83XX_MBX_RESPONSE_UNKNOWN;
3967
3968                 spin_lock(&mbx->queue_lock);
3969
3970                 list_add_tail(&cmd->list, &mbx->cmd_q);
3971                 mbx->num_cmds++;
3972                 cmd->total_cmds = mbx->num_cmds;
3973                 *timeout = cmd->total_cmds * QLC_83XX_MBX_TIMEOUT;
3974                 queue_work(mbx->work_q, &mbx->work);
3975
3976                 spin_unlock(&mbx->queue_lock);
3977
3978                 return 0;
3979         }
3980
3981         return -EBUSY;
3982 }
3983
3984 static int qlcnic_83xx_check_mac_rcode(struct qlcnic_adapter *adapter,
3985                                        struct qlcnic_cmd_args *cmd)
3986 {
3987         u8 mac_cmd_rcode;
3988         u32 fw_data;
3989
3990         if (cmd->cmd_op == QLCNIC_CMD_CONFIG_MAC_VLAN) {
3991                 fw_data = readl(QLCNIC_MBX_FW(adapter->ahw, 2));
3992                 mac_cmd_rcode = (u8)fw_data;
3993                 if (mac_cmd_rcode == QLC_83XX_NO_NIC_RESOURCE ||
3994                     mac_cmd_rcode == QLC_83XX_MAC_PRESENT ||
3995                     mac_cmd_rcode == QLC_83XX_MAC_ABSENT) {
3996                         cmd->rsp_opcode = QLCNIC_RCODE_SUCCESS;
3997                         return QLCNIC_RCODE_SUCCESS;
3998                 }
3999         }
4000
4001         return -EINVAL;
4002 }
4003
4004 static void qlcnic_83xx_decode_mbx_rsp(struct qlcnic_adapter *adapter,
4005                                        struct qlcnic_cmd_args *cmd)
4006 {
4007         struct qlcnic_hardware_context *ahw = adapter->ahw;
4008         struct device *dev = &adapter->pdev->dev;
4009         u8 mbx_err_code;
4010         u32 fw_data;
4011
4012         fw_data = readl(QLCNIC_MBX_FW(ahw, 0));
4013         mbx_err_code = QLCNIC_MBX_STATUS(fw_data);
4014         qlcnic_83xx_get_mbx_data(adapter, cmd);
4015
4016         switch (mbx_err_code) {
4017         case QLCNIC_MBX_RSP_OK:
4018         case QLCNIC_MBX_PORT_RSP_OK:
4019                 cmd->rsp_opcode = QLCNIC_RCODE_SUCCESS;
4020                 break;
4021         default:
4022                 if (!qlcnic_83xx_check_mac_rcode(adapter, cmd))
4023                         break;
4024
4025                 dev_err(dev, "%s: Mailbox command failed, opcode=0x%x, cmd_type=0x%x, func=0x%x, op_mode=0x%x, error=0x%x\n",
4026                         __func__, cmd->cmd_op, cmd->type, ahw->pci_func,
4027                         ahw->op_mode, mbx_err_code);
4028                 cmd->rsp_opcode = QLC_83XX_MBX_RESPONSE_FAILED;
4029                 qlcnic_dump_mbx(adapter, cmd);
4030         }
4031
4032         return;
4033 }
4034
4035 static inline void qlcnic_dump_mailbox_registers(struct qlcnic_adapter *adapter)
4036 {
4037         struct qlcnic_hardware_context *ahw = adapter->ahw;
4038         u32 offset;
4039
4040         offset = QLCRDX(ahw, QLCNIC_DEF_INT_MASK);
4041         dev_info(&adapter->pdev->dev, "Mbx interrupt mask=0x%x, Mbx interrupt enable=0x%x, Host mbx control=0x%x, Fw mbx control=0x%x",
4042                  readl(ahw->pci_base0 + offset),
4043                  QLCRDX(ahw, QLCNIC_MBX_INTR_ENBL),
4044                  QLCRDX(ahw, QLCNIC_HOST_MBX_CTRL),
4045                  QLCRDX(ahw, QLCNIC_FW_MBX_CTRL));
4046 }
4047
4048 static void qlcnic_83xx_mailbox_worker(struct work_struct *work)
4049 {
4050         struct qlcnic_mailbox *mbx = container_of(work, struct qlcnic_mailbox,
4051                                                   work);
4052         struct qlcnic_adapter *adapter = mbx->adapter;
4053         struct qlcnic_mbx_ops *mbx_ops = mbx->ops;
4054         struct device *dev = &adapter->pdev->dev;
4055         atomic_t *rsp_status = &mbx->rsp_status;
4056         struct list_head *head = &mbx->cmd_q;
4057         struct qlcnic_hardware_context *ahw;
4058         struct qlcnic_cmd_args *cmd = NULL;
4059
4060         ahw = adapter->ahw;
4061
4062         while (true) {
4063                 if (qlcnic_83xx_check_mbx_status(adapter)) {
4064                         qlcnic_83xx_flush_mbx_queue(adapter);
4065                         return;
4066                 }
4067
4068                 atomic_set(rsp_status, QLC_83XX_MBX_RESPONSE_WAIT);
4069
4070                 spin_lock(&mbx->queue_lock);
4071
4072                 if (list_empty(head)) {
4073                         spin_unlock(&mbx->queue_lock);
4074                         return;
4075                 }
4076                 cmd = list_entry(head->next, struct qlcnic_cmd_args, list);
4077
4078                 spin_unlock(&mbx->queue_lock);
4079
4080                 mbx_ops->encode_cmd(adapter, cmd);
4081                 mbx_ops->nofity_fw(adapter, QLC_83XX_MBX_REQUEST);
4082
4083                 if (wait_for_completion_timeout(&mbx->completion,
4084                                                 QLC_83XX_MBX_TIMEOUT)) {
4085                         mbx_ops->decode_resp(adapter, cmd);
4086                         mbx_ops->nofity_fw(adapter, QLC_83XX_MBX_COMPLETION);
4087                 } else {
4088                         dev_err(dev, "%s: Mailbox command timeout, opcode=0x%x, cmd_type=0x%x, func=0x%x, op_mode=0x%x\n",
4089                                 __func__, cmd->cmd_op, cmd->type, ahw->pci_func,
4090                                 ahw->op_mode);
4091                         clear_bit(QLC_83XX_MBX_READY, &mbx->status);
4092                         qlcnic_dump_mailbox_registers(adapter);
4093                         qlcnic_83xx_get_mbx_data(adapter, cmd);
4094                         qlcnic_dump_mbx(adapter, cmd);
4095                         qlcnic_83xx_idc_request_reset(adapter,
4096                                                       QLCNIC_FORCE_FW_DUMP_KEY);
4097                         cmd->rsp_opcode = QLCNIC_RCODE_TIMEOUT;
4098                 }
4099                 mbx_ops->dequeue_cmd(adapter, cmd);
4100         }
4101 }
4102
4103 static struct qlcnic_mbx_ops qlcnic_83xx_mbx_ops = {
4104         .enqueue_cmd    = qlcnic_83xx_enqueue_mbx_cmd,
4105         .dequeue_cmd    = qlcnic_83xx_dequeue_mbx_cmd,
4106         .decode_resp    = qlcnic_83xx_decode_mbx_rsp,
4107         .encode_cmd     = qlcnic_83xx_encode_mbx_cmd,
4108         .nofity_fw      = qlcnic_83xx_signal_mbx_cmd,
4109 };
4110
4111 int qlcnic_83xx_init_mailbox_work(struct qlcnic_adapter *adapter)
4112 {
4113         struct qlcnic_hardware_context *ahw = adapter->ahw;
4114         struct qlcnic_mailbox *mbx;
4115
4116         ahw->mailbox = kzalloc(sizeof(*mbx), GFP_KERNEL);
4117         if (!ahw->mailbox)
4118                 return -ENOMEM;
4119
4120         mbx = ahw->mailbox;
4121         mbx->ops = &qlcnic_83xx_mbx_ops;
4122         mbx->adapter = adapter;
4123
4124         spin_lock_init(&mbx->queue_lock);
4125         spin_lock_init(&mbx->aen_lock);
4126         INIT_LIST_HEAD(&mbx->cmd_q);
4127         init_completion(&mbx->completion);
4128
4129         mbx->work_q = create_singlethread_workqueue("qlcnic_mailbox");
4130         if (mbx->work_q == NULL) {
4131                 kfree(mbx);
4132                 return -ENOMEM;
4133         }
4134
4135         INIT_WORK(&mbx->work, qlcnic_83xx_mailbox_worker);
4136         set_bit(QLC_83XX_MBX_READY, &mbx->status);
4137         return 0;
4138 }
4139
4140 static pci_ers_result_t qlcnic_83xx_io_error_detected(struct pci_dev *pdev,
4141                                                       pci_channel_state_t state)
4142 {
4143         struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
4144
4145         if (state == pci_channel_io_perm_failure)
4146                 return PCI_ERS_RESULT_DISCONNECT;
4147
4148         if (state == pci_channel_io_normal)
4149                 return PCI_ERS_RESULT_RECOVERED;
4150
4151         set_bit(__QLCNIC_AER, &adapter->state);
4152         set_bit(__QLCNIC_RESETTING, &adapter->state);
4153
4154         qlcnic_83xx_aer_stop_poll_work(adapter);
4155
4156         pci_save_state(pdev);
4157         pci_disable_device(pdev);
4158
4159         return PCI_ERS_RESULT_NEED_RESET;
4160 }
4161
4162 static pci_ers_result_t qlcnic_83xx_io_slot_reset(struct pci_dev *pdev)
4163 {
4164         struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
4165         int err = 0;
4166
4167         pdev->error_state = pci_channel_io_normal;
4168         err = pci_enable_device(pdev);
4169         if (err)
4170                 goto disconnect;
4171
4172         pci_set_power_state(pdev, PCI_D0);
4173         pci_set_master(pdev);
4174         pci_restore_state(pdev);
4175
4176         err = qlcnic_83xx_aer_reset(adapter);
4177         if (err == 0)
4178                 return PCI_ERS_RESULT_RECOVERED;
4179 disconnect:
4180         clear_bit(__QLCNIC_AER, &adapter->state);
4181         clear_bit(__QLCNIC_RESETTING, &adapter->state);
4182         return PCI_ERS_RESULT_DISCONNECT;
4183 }
4184
4185 static void qlcnic_83xx_io_resume(struct pci_dev *pdev)
4186 {
4187         struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
4188
4189         pci_cleanup_aer_uncorrect_error_status(pdev);
4190         if (test_and_clear_bit(__QLCNIC_AER, &adapter->state))
4191                 qlcnic_83xx_aer_start_poll_work(adapter);
4192 }