drivers/net/ethernet/qlogic/qed/qed_mcp.c

   1 /* QLogic qed NIC Driver
   2  * Copyright (c) 2015 QLogic Corporation
   3  *
   4  * This software is available under the terms of the GNU General Public License
   5  * (GPL) Version 2, available from the file COPYING in the main directory of
   6  * this source tree.
   7  */
   8
   9 #include <linux/types.h>
  10 #include <asm/byteorder.h>
  11 #include <linux/delay.h>
  12 #include <linux/errno.h>
  13 #include <linux/kernel.h>
  14 #include <linux/slab.h>
  15 #include <linux/spinlock.h>
  16 #include <linux/string.h>
  17 #include "qed.h"
  18 #include "qed_hsi.h"
  19 #include "qed_hw.h"
  20 #include "qed_mcp.h"
  21 #include "qed_reg_addr.h"
  22 #include "qed_sriov.h"
  23
  24 #define CHIP_MCP_RESP_ITER_US 10
  25
  26 #define QED_DRV_MB_MAX_RETRIES  (500 * 1000)    /* Account for 5 sec */
  27 #define QED_MCP_RESET_RETRIES   (50 * 1000)     /* Account for 500 msec */
  28
  29 #define DRV_INNER_WR(_p_hwfn, _p_ptt, _ptr, _offset, _val)           \
  30         qed_wr(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset), \
  31                _val)
  32
  33 #define DRV_INNER_RD(_p_hwfn, _p_ptt, _ptr, _offset) \
  34         qed_rd(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset))
  35
  36 #define DRV_MB_WR(_p_hwfn, _p_ptt, _field, _val)  \
  37         DRV_INNER_WR(p_hwfn, _p_ptt, drv_mb_addr, \
  38                      offsetof(struct public_drv_mb, _field), _val)
  39
  40 #define DRV_MB_RD(_p_hwfn, _p_ptt, _field)         \
  41         DRV_INNER_RD(_p_hwfn, _p_ptt, drv_mb_addr, \
  42                      offsetof(struct public_drv_mb, _field))
  43
  44 #define PDA_COMP (((FW_MAJOR_VERSION) + (FW_MINOR_VERSION << 8)) << \
  45                   DRV_ID_PDA_COMP_VER_SHIFT)
  46
  47 #define MCP_BYTES_PER_MBIT_SHIFT 17
  48
  49 bool qed_mcp_is_init(struct qed_hwfn *p_hwfn)
  50 {
  51         if (!p_hwfn->mcp_info || !p_hwfn->mcp_info->public_base)
  52                 return false;
  53         return true;
  54 }
  55
  56 void qed_mcp_cmd_port_init(struct qed_hwfn *p_hwfn,
  57                            struct qed_ptt *p_ptt)
  58 {
  59         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
  60                                         PUBLIC_PORT);
  61         u32 mfw_mb_offsize = qed_rd(p_hwfn, p_ptt, addr);
  62
  63         p_hwfn->mcp_info->port_addr = SECTION_ADDR(mfw_mb_offsize,
  64                                                    MFW_PORT(p_hwfn));
  65         DP_VERBOSE(p_hwfn, QED_MSG_SP,
  66                    "port_addr = 0x%x, port_id 0x%02x\n",
  67                    p_hwfn->mcp_info->port_addr, MFW_PORT(p_hwfn));
  68 }
  69
  70 void qed_mcp_read_mb(struct qed_hwfn *p_hwfn,
  71                      struct qed_ptt *p_ptt)
  72 {
  73         u32 length = MFW_DRV_MSG_MAX_DWORDS(p_hwfn->mcp_info->mfw_mb_length);
  74         u32 tmp, i;
  75
  76         if (!p_hwfn->mcp_info->public_base)
  77                 return;
  78
  79         for (i = 0; i < length; i++) {
  80                 tmp = qed_rd(p_hwfn, p_ptt,
  81                              p_hwfn->mcp_info->mfw_mb_addr +
  82                              (i << 2) + sizeof(u32));
  83
  84                 /* The MB data is actually BE; Need to force it to cpu */
  85                 ((u32 *)p_hwfn->mcp_info->mfw_mb_cur)[i] =
  86                         be32_to_cpu((__force __be32)tmp);
  87         }
  88 }
  89
  90 int qed_mcp_free(struct qed_hwfn *p_hwfn)
  91 {
  92         if (p_hwfn->mcp_info) {
  93                 kfree(p_hwfn->mcp_info->mfw_mb_cur);
  94                 kfree(p_hwfn->mcp_info->mfw_mb_shadow);
  95         }
  96         kfree(p_hwfn->mcp_info);
  97
  98         return 0;
  99 }
 100
 101 static int qed_load_mcp_offsets(struct qed_hwfn *p_hwfn,
 102                                 struct qed_ptt *p_ptt)
 103 {
 104         struct qed_mcp_info *p_info = p_hwfn->mcp_info;
 105         u32 drv_mb_offsize, mfw_mb_offsize;
 106         u32 mcp_pf_id = MCP_PF_ID(p_hwfn);
 107
 108         p_info->public_base = qed_rd(p_hwfn, p_ptt, MISC_REG_SHARED_MEM_ADDR);
 109         if (!p_info->public_base)
 110                 return 0;
 111
 112         p_info->public_base |= GRCBASE_MCP;
 113
 114         /* Calculate the driver and MFW mailbox address */
 115         drv_mb_offsize = qed_rd(p_hwfn, p_ptt,
 116                                 SECTION_OFFSIZE_ADDR(p_info->public_base,
 117                                                      PUBLIC_DRV_MB));
 118         p_info->drv_mb_addr = SECTION_ADDR(drv_mb_offsize, mcp_pf_id);
 119         DP_VERBOSE(p_hwfn, QED_MSG_SP,
 120                    "drv_mb_offsiz = 0x%x, drv_mb_addr = 0x%x mcp_pf_id = 0x%x\n",
 121                    drv_mb_offsize, p_info->drv_mb_addr, mcp_pf_id);
 122
 123         /* Set the MFW MB address */
 124         mfw_mb_offsize = qed_rd(p_hwfn, p_ptt,
 125                                 SECTION_OFFSIZE_ADDR(p_info->public_base,
 126                                                      PUBLIC_MFW_MB));
 127         p_info->mfw_mb_addr = SECTION_ADDR(mfw_mb_offsize, mcp_pf_id);
 128         p_info->mfw_mb_length = (u16)qed_rd(p_hwfn, p_ptt, p_info->mfw_mb_addr);
 129
 130         /* Get the current driver mailbox sequence before sending
 131          * the first command
 132          */
 133         p_info->drv_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) &
 134                              DRV_MSG_SEQ_NUMBER_MASK;
 135
 136         /* Get current FW pulse sequence */
 137         p_info->drv_pulse_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_pulse_mb) &
 138                                 DRV_PULSE_SEQ_MASK;
 139
 140         p_info->mcp_hist = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
 141
 142         return 0;
 143 }
 144
 145 int qed_mcp_cmd_init(struct qed_hwfn *p_hwfn,
 146                      struct qed_ptt *p_ptt)
 147 {
 148         struct qed_mcp_info *p_info;
 149         u32 size;
 150
 151         /* Allocate mcp_info structure */
 152         p_hwfn->mcp_info = kzalloc(sizeof(*p_hwfn->mcp_info), GFP_KERNEL);
 153         if (!p_hwfn->mcp_info)
 154                 goto err;
 155         p_info = p_hwfn->mcp_info;
 156
 157         if (qed_load_mcp_offsets(p_hwfn, p_ptt) != 0) {
 158                 DP_NOTICE(p_hwfn, "MCP is not initialized\n");
 159                 /* Do not free mcp_info here, since public_base indicate that
 160                  * the MCP is not initialized
 161                  */
 162                 return 0;
 163         }
 164
 165         size = MFW_DRV_MSG_MAX_DWORDS(p_info->mfw_mb_length) * sizeof(u32);
 166         p_info->mfw_mb_cur = kzalloc(size, GFP_KERNEL);
 167         p_info->mfw_mb_shadow =
 168                 kzalloc(sizeof(u32) * MFW_DRV_MSG_MAX_DWORDS(
 169                                 p_info->mfw_mb_length), GFP_KERNEL);
 170         if (!p_info->mfw_mb_shadow || !p_info->mfw_mb_addr)
 171                 goto err;
 172
 173         /* Initialize the MFW spinlock */
 174         spin_lock_init(&p_info->lock);
 175
 176         return 0;
 177
 178 err:
 179         DP_NOTICE(p_hwfn, "Failed to allocate mcp memory\n");
 180         qed_mcp_free(p_hwfn);
 181         return -ENOMEM;
 182 }
 183
 184 /* Locks the MFW mailbox of a PF to ensure a single access.
 185  * The lock is achieved in most cases by holding a spinlock, causing other
 186  * threads to wait till a previous access is done.
 187  * In some cases (currently when a [UN]LOAD_REQ commands are sent), the single
 188  * access is achieved by setting a blocking flag, which will fail other
 189  * competing contexts to send their mailboxes.
 190  */
 191 static int qed_mcp_mb_lock(struct qed_hwfn *p_hwfn,
 192                            u32 cmd)
 193 {
 194         spin_lock_bh(&p_hwfn->mcp_info->lock);
 195
 196         /* The spinlock shouldn't be acquired when the mailbox command is
 197          * [UN]LOAD_REQ, since the engine is locked by the MFW, and a parallel
 198          * pending [UN]LOAD_REQ command of another PF together with a spinlock
 199          * (i.e. interrupts are disabled) - can lead to a deadlock.
 200          * It is assumed that for a single PF, no other mailbox commands can be
 201          * sent from another context while sending LOAD_REQ, and that any
 202          * parallel commands to UNLOAD_REQ can be cancelled.
 203          */
 204         if (cmd == DRV_MSG_CODE_LOAD_DONE || cmd == DRV_MSG_CODE_UNLOAD_DONE)
 205                 p_hwfn->mcp_info->block_mb_sending = false;
 206
 207         if (p_hwfn->mcp_info->block_mb_sending) {
 208                 DP_NOTICE(p_hwfn,
 209                           "Trying to send a MFW mailbox command [0x%x] in parallel to [UN]LOAD_REQ. Aborting.\n",
 210                           cmd);
 211                 spin_unlock_bh(&p_hwfn->mcp_info->lock);
 212                 return -EBUSY;
 213         }
 214
 215         if (cmd == DRV_MSG_CODE_LOAD_REQ || cmd == DRV_MSG_CODE_UNLOAD_REQ) {
 216                 p_hwfn->mcp_info->block_mb_sending = true;
 217                 spin_unlock_bh(&p_hwfn->mcp_info->lock);
 218         }
 219
 220         return 0;
 221 }
 222
 223 static void qed_mcp_mb_unlock(struct qed_hwfn   *p_hwfn,
 224                               u32               cmd)
 225 {
 226         if (cmd != DRV_MSG_CODE_LOAD_REQ && cmd != DRV_MSG_CODE_UNLOAD_REQ)
 227                 spin_unlock_bh(&p_hwfn->mcp_info->lock);
 228 }
 229
 230 int qed_mcp_reset(struct qed_hwfn *p_hwfn,
 231                   struct qed_ptt *p_ptt)
 232 {
 233         u32 seq = ++p_hwfn->mcp_info->drv_mb_seq;
 234         u8 delay = CHIP_MCP_RESP_ITER_US;
 235         u32 org_mcp_reset_seq, cnt = 0;
 236         int rc = 0;
 237
 238         /* Ensure that only a single thread is accessing the mailbox at a
 239          * certain time.
 240          */
 241         rc = qed_mcp_mb_lock(p_hwfn, DRV_MSG_CODE_MCP_RESET);
 242         if (rc != 0)
 243                 return rc;
 244
 245         /* Set drv command along with the updated sequence */
 246         org_mcp_reset_seq = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
 247         DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header,
 248                   (DRV_MSG_CODE_MCP_RESET | seq));
 249
 250         do {
 251                 /* Wait for MFW response */
 252                 udelay(delay);
 253                 /* Give the FW up to 500 second (50*1000*10usec) */
 254         } while ((org_mcp_reset_seq == qed_rd(p_hwfn, p_ptt,
 255                                               MISCS_REG_GENERIC_POR_0)) &&
 256                  (cnt++ < QED_MCP_RESET_RETRIES));
 257
 258         if (org_mcp_reset_seq !=
 259             qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) {
 260                 DP_VERBOSE(p_hwfn, QED_MSG_SP,
 261                            "MCP was reset after %d usec\n", cnt * delay);
 262         } else {
 263                 DP_ERR(p_hwfn, "Failed to reset MCP\n");
 264                 rc = -EAGAIN;
 265         }
 266
 267         qed_mcp_mb_unlock(p_hwfn, DRV_MSG_CODE_MCP_RESET);
 268
 269         return rc;
 270 }
 271
 272 static int qed_do_mcp_cmd(struct qed_hwfn *p_hwfn,
 273                           struct qed_ptt *p_ptt,
 274                           u32 cmd,
 275                           u32 param,
 276                           u32 *o_mcp_resp,
 277                           u32 *o_mcp_param)
 278 {
 279         u8 delay = CHIP_MCP_RESP_ITER_US;
 280         u32 seq, cnt = 1, actual_mb_seq;
 281         int rc = 0;
 282
 283         /* Get actual driver mailbox sequence */
 284         actual_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) &
 285                         DRV_MSG_SEQ_NUMBER_MASK;
 286
 287         /* Use MCP history register to check if MCP reset occurred between
 288          * init time and now.
 289          */
 290         if (p_hwfn->mcp_info->mcp_hist !=
 291             qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) {
 292                 DP_VERBOSE(p_hwfn, QED_MSG_SP, "Rereading MCP offsets\n");
 293                 qed_load_mcp_offsets(p_hwfn, p_ptt);
 294                 qed_mcp_cmd_port_init(p_hwfn, p_ptt);
 295         }
 296         seq = ++p_hwfn->mcp_info->drv_mb_seq;
 297
 298         /* Set drv param */
 299         DRV_MB_WR(p_hwfn, p_ptt, drv_mb_param, param);
 300
 301         /* Set drv command along with the updated sequence */
 302         DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (cmd | seq));
 303
 304         DP_VERBOSE(p_hwfn, QED_MSG_SP,
 305                    "wrote command (%x) to MFW MB param 0x%08x\n",
 306                    (cmd | seq), param);
 307
 308         do {
 309                 /* Wait for MFW response */
 310                 udelay(delay);
 311                 *o_mcp_resp = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_header);
 312
 313                 /* Give the FW up to 5 second (500*10ms) */
 314         } while ((seq != (*o_mcp_resp & FW_MSG_SEQ_NUMBER_MASK)) &&
 315                  (cnt++ < QED_DRV_MB_MAX_RETRIES));
 316
 317         DP_VERBOSE(p_hwfn, QED_MSG_SP,
 318                    "[after %d ms] read (%x) seq is (%x) from FW MB\n",
 319                    cnt * delay, *o_mcp_resp, seq);
 320
 321         /* Is this a reply to our command? */
 322         if (seq == (*o_mcp_resp & FW_MSG_SEQ_NUMBER_MASK)) {
 323                 *o_mcp_resp &= FW_MSG_CODE_MASK;
 324                 /* Get the MCP param */
 325                 *o_mcp_param = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_param);
 326         } else {
 327                 /* FW BUG! */
 328                 DP_ERR(p_hwfn, "MFW failed to respond!\n");
 329                 *o_mcp_resp = 0;
 330                 rc = -EAGAIN;
 331         }
 332         return rc;
 333 }
 334
 335 static int qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn,
 336                                  struct qed_ptt *p_ptt,
 337                                  struct qed_mcp_mb_params *p_mb_params)
 338 {
 339         u32 union_data_addr;
 340         int rc;
 341
 342         /* MCP not initialized */
 343         if (!qed_mcp_is_init(p_hwfn)) {
 344                 DP_NOTICE(p_hwfn, "MFW is not initialized !\n");
 345                 return -EBUSY;
 346         }
 347
 348         union_data_addr = p_hwfn->mcp_info->drv_mb_addr +
 349                           offsetof(struct public_drv_mb, union_data);
 350
 351         /* Ensure that only a single thread is accessing the mailbox at a
 352          * certain time.
 353          */
 354         rc = qed_mcp_mb_lock(p_hwfn, p_mb_params->cmd);
 355         if (rc)
 356                 return rc;
 357
 358         if (p_mb_params->p_data_src != NULL)
 359                 qed_memcpy_to(p_hwfn, p_ptt, union_data_addr,
 360                               p_mb_params->p_data_src,
 361                               sizeof(*p_mb_params->p_data_src));
 362
 363         rc = qed_do_mcp_cmd(p_hwfn, p_ptt, p_mb_params->cmd,
 364                             p_mb_params->param, &p_mb_params->mcp_resp,
 365                             &p_mb_params->mcp_param);
 366
 367         if (p_mb_params->p_data_dst != NULL)
 368                 qed_memcpy_from(p_hwfn, p_ptt, p_mb_params->p_data_dst,
 369                                 union_data_addr,
 370                                 sizeof(*p_mb_params->p_data_dst));
 371
 372         qed_mcp_mb_unlock(p_hwfn, p_mb_params->cmd);
 373
 374         return rc;
 375 }
 376
 377 int qed_mcp_cmd(struct qed_hwfn *p_hwfn,
 378                 struct qed_ptt *p_ptt,
 379                 u32 cmd,
 380                 u32 param,
 381                 u32 *o_mcp_resp,
 382                 u32 *o_mcp_param)
 383 {
 384         struct qed_mcp_mb_params mb_params;
 385         int rc;
 386
 387         memset(&mb_params, 0, sizeof(mb_params));
 388         mb_params.cmd = cmd;
 389         mb_params.param = param;
 390         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 391         if (rc)
 392                 return rc;
 393
 394         *o_mcp_resp = mb_params.mcp_resp;
 395         *o_mcp_param = mb_params.mcp_param;
 396
 397         return 0;
 398 }
 399
 400 int qed_mcp_load_req(struct qed_hwfn *p_hwfn,
 401                      struct qed_ptt *p_ptt,
 402                      u32 *p_load_code)
 403 {
 404         struct qed_dev *cdev = p_hwfn->cdev;
 405         struct qed_mcp_mb_params mb_params;
 406         union drv_union_data union_data;
 407         int rc;
 408
 409         memset(&mb_params, 0, sizeof(mb_params));
 410         /* Load Request */
 411         mb_params.cmd = DRV_MSG_CODE_LOAD_REQ;
 412         mb_params.param = PDA_COMP | DRV_ID_MCP_HSI_VER_CURRENT |
 413                           cdev->drv_type;
 414         memcpy(&union_data.ver_str, cdev->ver_str, MCP_DRV_VER_STR_SIZE);
 415         mb_params.p_data_src = &union_data;
 416         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 417
 418         /* if mcp fails to respond we must abort */
 419         if (rc) {
 420                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
 421                 return rc;
 422         }
 423
 424         *p_load_code = mb_params.mcp_resp;
 425
 426         /* If MFW refused (e.g. other port is in diagnostic mode) we
 427          * must abort. This can happen in the following cases:
 428          * - Other port is in diagnostic mode
 429          * - Previously loaded function on the engine is not compliant with
 430          *   the requester.
 431          * - MFW cannot cope with the requester's DRV_MFW_HSI_VERSION.
 432          *      -
 433          */
 434         if (!(*p_load_code) ||
 435             ((*p_load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED_HSI) ||
 436             ((*p_load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED_PDA) ||
 437             ((*p_load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED_DIAG)) {
 438                 DP_ERR(p_hwfn, "MCP refused load request, aborting\n");
 439                 return -EBUSY;
 440         }
 441
 442         return 0;
 443 }
 444
 445 static void qed_mcp_handle_transceiver_change(struct qed_hwfn *p_hwfn,
 446                                               struct qed_ptt *p_ptt)
 447 {
 448         u32 transceiver_state;
 449
 450         transceiver_state = qed_rd(p_hwfn, p_ptt,
 451                                    p_hwfn->mcp_info->port_addr +
 452                                    offsetof(struct public_port,
 453                                             transceiver_data));
 454
 455         DP_VERBOSE(p_hwfn,
 456                    (NETIF_MSG_HW | QED_MSG_SP),
 457                    "Received transceiver state update [0x%08x] from mfw [Addr 0x%x]\n",
 458                    transceiver_state,
 459                    (u32)(p_hwfn->mcp_info->port_addr +
 460                          offsetof(struct public_port,
 461                                   transceiver_data)));
 462
 463         transceiver_state = GET_FIELD(transceiver_state,
 464                                       PMM_TRANSCEIVER_STATE);
 465
 466         if (transceiver_state == PMM_TRANSCEIVER_STATE_PRESENT)
 467                 DP_NOTICE(p_hwfn, "Transceiver is present.\n");
 468         else
 469                 DP_NOTICE(p_hwfn, "Transceiver is unplugged.\n");
 470 }
 471
 472 static void qed_mcp_handle_link_change(struct qed_hwfn *p_hwfn,
 473                                        struct qed_ptt *p_ptt,
 474                                        bool b_reset)
 475 {
 476         struct qed_mcp_link_state *p_link;
 477         u8 max_bw, min_bw;
 478         u32 status = 0;
 479
 480         p_link = &p_hwfn->mcp_info->link_output;
 481         memset(p_link, 0, sizeof(*p_link));
 482         if (!b_reset) {
 483                 status = qed_rd(p_hwfn, p_ptt,
 484                                 p_hwfn->mcp_info->port_addr +
 485                                 offsetof(struct public_port, link_status));
 486                 DP_VERBOSE(p_hwfn, (NETIF_MSG_LINK | QED_MSG_SP),
 487                            "Received link update [0x%08x] from mfw [Addr 0x%x]\n",
 488                            status,
 489                            (u32)(p_hwfn->mcp_info->port_addr +
 490                                  offsetof(struct public_port,
 491                                           link_status)));
 492         } else {
 493                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
 494                            "Resetting link indications\n");
 495                 return;
 496         }
 497
 498         if (p_hwfn->b_drv_link_init)
 499                 p_link->link_up = !!(status & LINK_STATUS_LINK_UP);
 500         else
 501                 p_link->link_up = false;
 502
 503         p_link->full_duplex = true;
 504         switch ((status & LINK_STATUS_SPEED_AND_DUPLEX_MASK)) {
 505         case LINK_STATUS_SPEED_AND_DUPLEX_100G:
 506                 p_link->speed = 100000;
 507                 break;
 508         case LINK_STATUS_SPEED_AND_DUPLEX_50G:
 509                 p_link->speed = 50000;
 510                 break;
 511         case LINK_STATUS_SPEED_AND_DUPLEX_40G:
 512                 p_link->speed = 40000;
 513                 break;
 514         case LINK_STATUS_SPEED_AND_DUPLEX_25G:
 515                 p_link->speed = 25000;
 516                 break;
 517         case LINK_STATUS_SPEED_AND_DUPLEX_20G:
 518                 p_link->speed = 20000;
 519                 break;
 520         case LINK_STATUS_SPEED_AND_DUPLEX_10G:
 521                 p_link->speed = 10000;
 522                 break;
 523         case LINK_STATUS_SPEED_AND_DUPLEX_1000THD:
 524                 p_link->full_duplex = false;
 525         /* Fall-through */
 526         case LINK_STATUS_SPEED_AND_DUPLEX_1000TFD:
 527                 p_link->speed = 1000;
 528                 break;
 529         default:
 530                 p_link->speed = 0;
 531         }
 532
 533         if (p_link->link_up && p_link->speed)
 534                 p_link->line_speed = p_link->speed;
 535         else
 536                 p_link->line_speed = 0;
 537
 538         max_bw = p_hwfn->mcp_info->func_info.bandwidth_max;
 539         min_bw = p_hwfn->mcp_info->func_info.bandwidth_min;
 540
 541         /* Max bandwidth configuration */
 542         __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt, p_link, max_bw);
 543
 544         /* Min bandwidth configuration */
 545         __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt, p_link, min_bw);
 546         qed_configure_vp_wfq_on_link_change(p_hwfn->cdev, p_link->min_pf_rate);
 547
 548         p_link->an = !!(status & LINK_STATUS_AUTO_NEGOTIATE_ENABLED);
 549         p_link->an_complete = !!(status &
 550                                  LINK_STATUS_AUTO_NEGOTIATE_COMPLETE);
 551         p_link->parallel_detection = !!(status &
 552                                         LINK_STATUS_PARALLEL_DETECTION_USED);
 553         p_link->pfc_enabled = !!(status & LINK_STATUS_PFC_ENABLED);
 554
 555         p_link->partner_adv_speed |=
 556                 (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) ?
 557                 QED_LINK_PARTNER_SPEED_1G_FD : 0;
 558         p_link->partner_adv_speed |=
 559                 (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE) ?
 560                 QED_LINK_PARTNER_SPEED_1G_HD : 0;
 561         p_link->partner_adv_speed |=
 562                 (status & LINK_STATUS_LINK_PARTNER_10G_CAPABLE) ?
 563                 QED_LINK_PARTNER_SPEED_10G : 0;
 564         p_link->partner_adv_speed |=
 565                 (status & LINK_STATUS_LINK_PARTNER_20G_CAPABLE) ?
 566                 QED_LINK_PARTNER_SPEED_20G : 0;
 567         p_link->partner_adv_speed |=
 568                 (status & LINK_STATUS_LINK_PARTNER_40G_CAPABLE) ?
 569                 QED_LINK_PARTNER_SPEED_40G : 0;
 570         p_link->partner_adv_speed |=
 571                 (status & LINK_STATUS_LINK_PARTNER_50G_CAPABLE) ?
 572                 QED_LINK_PARTNER_SPEED_50G : 0;
 573         p_link->partner_adv_speed |=
 574                 (status & LINK_STATUS_LINK_PARTNER_100G_CAPABLE) ?
 575                 QED_LINK_PARTNER_SPEED_100G : 0;
 576
 577         p_link->partner_tx_flow_ctrl_en =
 578                 !!(status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED);
 579         p_link->partner_rx_flow_ctrl_en =
 580                 !!(status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED);
 581
 582         switch (status & LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK) {
 583         case LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE:
 584                 p_link->partner_adv_pause = QED_LINK_PARTNER_SYMMETRIC_PAUSE;
 585                 break;
 586         case LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE:
 587                 p_link->partner_adv_pause = QED_LINK_PARTNER_ASYMMETRIC_PAUSE;
 588                 break;
 589         case LINK_STATUS_LINK_PARTNER_BOTH_PAUSE:
 590                 p_link->partner_adv_pause = QED_LINK_PARTNER_BOTH_PAUSE;
 591                 break;
 592         default:
 593                 p_link->partner_adv_pause = 0;
 594         }
 595
 596         p_link->sfp_tx_fault = !!(status & LINK_STATUS_SFP_TX_FAULT);
 597
 598         qed_link_update(p_hwfn);
 599 }
 600
 601 int qed_mcp_set_link(struct qed_hwfn *p_hwfn,
 602                      struct qed_ptt *p_ptt,
 603                      bool b_up)
 604 {
 605         struct qed_mcp_link_params *params = &p_hwfn->mcp_info->link_input;
 606         struct qed_mcp_mb_params mb_params;
 607         union drv_union_data union_data;
 608         struct pmm_phy_cfg *phy_cfg;
 609         int rc = 0;
 610         u32 cmd;
 611
 612         /* Set the shmem configuration according to params */
 613         phy_cfg = &union_data.drv_phy_cfg;
 614         memset(phy_cfg, 0, sizeof(*phy_cfg));
 615         cmd = b_up ? DRV_MSG_CODE_INIT_PHY : DRV_MSG_CODE_LINK_RESET;
 616         if (!params->speed.autoneg)
 617                 phy_cfg->speed = params->speed.forced_speed;
 618         phy_cfg->pause |= (params->pause.autoneg) ? PMM_PAUSE_AUTONEG : 0;
 619         phy_cfg->pause |= (params->pause.forced_rx) ? PMM_PAUSE_RX : 0;
 620         phy_cfg->pause |= (params->pause.forced_tx) ? PMM_PAUSE_TX : 0;
 621         phy_cfg->adv_speed = params->speed.advertised_speeds;
 622         phy_cfg->loopback_mode = params->loopback_mode;
 623
 624         p_hwfn->b_drv_link_init = b_up;
 625
 626         if (b_up) {
 627                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
 628                            "Configuring Link: Speed 0x%08x, Pause 0x%08x, adv_speed 0x%08x, loopback 0x%08x, features 0x%08x\n",
 629                            phy_cfg->speed,
 630                            phy_cfg->pause,
 631                            phy_cfg->adv_speed,
 632                            phy_cfg->loopback_mode,
 633                            phy_cfg->feature_config_flags);
 634         } else {
 635                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
 636                            "Resetting link\n");
 637         }
 638
 639         memset(&mb_params, 0, sizeof(mb_params));
 640         mb_params.cmd = cmd;
 641         mb_params.p_data_src = &union_data;
 642         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 643
 644         /* if mcp fails to respond we must abort */
 645         if (rc) {
 646                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
 647                 return rc;
 648         }
 649
 650         /* Reset the link status if needed */
 651         if (!b_up)
 652                 qed_mcp_handle_link_change(p_hwfn, p_ptt, true);
 653
 654         return 0;
 655 }
 656
 657 static void qed_read_pf_bandwidth(struct qed_hwfn *p_hwfn,
 658                                   struct public_func *p_shmem_info)
 659 {
 660         struct qed_mcp_function_info *p_info;
 661
 662         p_info = &p_hwfn->mcp_info->func_info;
 663
 664         p_info->bandwidth_min = (p_shmem_info->config &
 665                                  FUNC_MF_CFG_MIN_BW_MASK) >>
 666                                         FUNC_MF_CFG_MIN_BW_SHIFT;
 667         if (p_info->bandwidth_min < 1 || p_info->bandwidth_min > 100) {
 668                 DP_INFO(p_hwfn,
 669                         "bandwidth minimum out of bounds [%02x]. Set to 1\n",
 670                         p_info->bandwidth_min);
 671                 p_info->bandwidth_min = 1;
 672         }
 673
 674         p_info->bandwidth_max = (p_shmem_info->config &
 675                                  FUNC_MF_CFG_MAX_BW_MASK) >>
 676                                         FUNC_MF_CFG_MAX_BW_SHIFT;
 677         if (p_info->bandwidth_max < 1 || p_info->bandwidth_max > 100) {
 678                 DP_INFO(p_hwfn,
 679                         "bandwidth maximum out of bounds [%02x]. Set to 100\n",
 680                         p_info->bandwidth_max);
 681                 p_info->bandwidth_max = 100;
 682         }
 683 }
 684
 685 static u32 qed_mcp_get_shmem_func(struct qed_hwfn *p_hwfn,
 686                                   struct qed_ptt *p_ptt,
 687                                   struct public_func *p_data,
 688                                   int pfid)
 689 {
 690         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
 691                                         PUBLIC_FUNC);
 692         u32 mfw_path_offsize = qed_rd(p_hwfn, p_ptt, addr);
 693         u32 func_addr = SECTION_ADDR(mfw_path_offsize, pfid);
 694         u32 i, size;
 695
 696         memset(p_data, 0, sizeof(*p_data));
 697
 698         size = min_t(u32, sizeof(*p_data),
 699                      QED_SECTION_SIZE(mfw_path_offsize));
 700         for (i = 0; i < size / sizeof(u32); i++)
 701                 ((u32 *)p_data)[i] = qed_rd(p_hwfn, p_ptt,
 702                                             func_addr + (i << 2));
 703         return size;
 704 }
 705
 706 static void qed_mcp_update_bw(struct qed_hwfn *p_hwfn,
 707                               struct qed_ptt *p_ptt)
 708 {
 709         struct qed_mcp_function_info *p_info;
 710         struct public_func shmem_info;
 711         u32 resp = 0, param = 0;
 712
 713         qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info,
 714                                MCP_PF_ID(p_hwfn));
 715
 716         qed_read_pf_bandwidth(p_hwfn, &shmem_info);
 717
 718         p_info = &p_hwfn->mcp_info->func_info;
 719
 720         qed_configure_pf_min_bandwidth(p_hwfn->cdev, p_info->bandwidth_min);
 721         qed_configure_pf_max_bandwidth(p_hwfn->cdev, p_info->bandwidth_max);
 722
 723         /* Acknowledge the MFW */
 724         qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BW_UPDATE_ACK, 0, &resp,
 725                     &param);
 726 }
 727
 728 int qed_mcp_handle_events(struct qed_hwfn *p_hwfn,
 729                           struct qed_ptt *p_ptt)
 730 {
 731         struct qed_mcp_info *info = p_hwfn->mcp_info;
 732         int rc = 0;
 733         bool found = false;
 734         u16 i;
 735
 736         DP_VERBOSE(p_hwfn, QED_MSG_SP, "Received message from MFW\n");
 737
 738         /* Read Messages from MFW */
 739         qed_mcp_read_mb(p_hwfn, p_ptt);
 740
 741         /* Compare current messages to old ones */
 742         for (i = 0; i < info->mfw_mb_length; i++) {
 743                 if (info->mfw_mb_cur[i] == info->mfw_mb_shadow[i])
 744                         continue;
 745
 746                 found = true;
 747
 748                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
 749                            "Msg [%d] - old CMD 0x%02x, new CMD 0x%02x\n",
 750                            i, info->mfw_mb_shadow[i], info->mfw_mb_cur[i]);
 751
 752                 switch (i) {
 753                 case MFW_DRV_MSG_LINK_CHANGE:
 754                         qed_mcp_handle_link_change(p_hwfn, p_ptt, false);
 755                         break;
 756                 case MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE:
 757                         qed_mcp_handle_transceiver_change(p_hwfn, p_ptt);
 758                         break;
 759                 case MFW_DRV_MSG_BW_UPDATE:
 760                         qed_mcp_update_bw(p_hwfn, p_ptt);
 761                         break;
 762                 default:
 763                         DP_NOTICE(p_hwfn, "Unimplemented MFW message %d\n", i);
 764                         rc = -EINVAL;
 765                 }
 766         }
 767
 768         /* ACK everything */
 769         for (i = 0; i < MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length); i++) {
 770                 __be32 val = cpu_to_be32(((u32 *)info->mfw_mb_cur)[i]);
 771
 772                 /* MFW expect answer in BE, so we force write in that format */
 773                 qed_wr(p_hwfn, p_ptt,
 774                        info->mfw_mb_addr + sizeof(u32) +
 775                        MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length) *
 776                        sizeof(u32) + i * sizeof(u32),
 777                        (__force u32)val);
 778         }
 779
 780         if (!found) {
 781                 DP_NOTICE(p_hwfn,
 782                           "Received an MFW message indication but no new message!\n");
 783                 rc = -EINVAL;
 784         }
 785
 786         /* Copy the new mfw messages into the shadow */
 787         memcpy(info->mfw_mb_shadow, info->mfw_mb_cur, info->mfw_mb_length);
 788
 789         return rc;
 790 }
 791
 792 int qed_mcp_get_mfw_ver(struct qed_hwfn *p_hwfn,
 793                         struct qed_ptt *p_ptt,
 794                         u32 *p_mfw_ver, u32 *p_running_bundle_id)
 795 {
 796         u32 global_offsize;
 797
 798         if (IS_VF(p_hwfn->cdev)) {
 799                 if (p_hwfn->vf_iov_info) {
 800                         struct pfvf_acquire_resp_tlv *p_resp;
 801
 802                         p_resp = &p_hwfn->vf_iov_info->acquire_resp;
 803                         *p_mfw_ver = p_resp->pfdev_info.mfw_ver;
 804                         return 0;
 805                 } else {
 806                         DP_VERBOSE(p_hwfn,
 807                                    QED_MSG_IOV,
 808                                    "VF requested MFW version prior to ACQUIRE\n");
 809                         return -EINVAL;
 810                 }
 811         }
 812
 813         global_offsize = qed_rd(p_hwfn, p_ptt,
 814                                 SECTION_OFFSIZE_ADDR(p_hwfn->
 815                                                      mcp_info->public_base,
 816                                                      PUBLIC_GLOBAL));
 817         *p_mfw_ver =
 818             qed_rd(p_hwfn, p_ptt,
 819                    SECTION_ADDR(global_offsize,
 820                                 0) + offsetof(struct public_global, mfw_ver));
 821
 822         if (p_running_bundle_id != NULL) {
 823                 *p_running_bundle_id = qed_rd(p_hwfn, p_ptt,
 824                                               SECTION_ADDR(global_offsize, 0) +
 825                                               offsetof(struct public_global,
 826                                                        running_bundle_id));
 827         }
 828
 829         return 0;
 830 }
 831
 832 int qed_mcp_get_media_type(struct qed_dev *cdev,
 833                            u32 *p_media_type)
 834 {
 835         struct qed_hwfn *p_hwfn = &cdev->hwfns[0];
 836         struct qed_ptt  *p_ptt;
 837
 838         if (IS_VF(cdev))
 839                 return -EINVAL;
 840
 841         if (!qed_mcp_is_init(p_hwfn)) {
 842                 DP_NOTICE(p_hwfn, "MFW is not initialized !\n");
 843                 return -EBUSY;
 844         }
 845
 846         *p_media_type = MEDIA_UNSPECIFIED;
 847
 848         p_ptt = qed_ptt_acquire(p_hwfn);
 849         if (!p_ptt)
 850                 return -EBUSY;
 851
 852         *p_media_type = qed_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
 853                                offsetof(struct public_port, media_type));
 854
 855         qed_ptt_release(p_hwfn, p_ptt);
 856
 857         return 0;
 858 }
 859
 860 static int
 861 qed_mcp_get_shmem_proto(struct qed_hwfn *p_hwfn,
 862                         struct public_func *p_info,
 863                         enum qed_pci_personality *p_proto)
 864 {
 865         int rc = 0;
 866
 867         switch (p_info->config & FUNC_MF_CFG_PROTOCOL_MASK) {
 868         case FUNC_MF_CFG_PROTOCOL_ETHERNET:
 869                 *p_proto = QED_PCI_ETH;
 870                 break;
 871         default:
 872                 rc = -EINVAL;
 873         }
 874
 875         return rc;
 876 }
 877
 878 int qed_mcp_fill_shmem_func_info(struct qed_hwfn *p_hwfn,
 879                                  struct qed_ptt *p_ptt)
 880 {
 881         struct qed_mcp_function_info *info;
 882         struct public_func shmem_info;
 883
 884         qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info,
 885                                MCP_PF_ID(p_hwfn));
 886         info = &p_hwfn->mcp_info->func_info;
 887
 888         info->pause_on_host = (shmem_info.config &
 889                                FUNC_MF_CFG_PAUSE_ON_HOST_RING) ? 1 : 0;
 890
 891         if (qed_mcp_get_shmem_proto(p_hwfn, &shmem_info,
 892                                     &info->protocol)) {
 893                 DP_ERR(p_hwfn, "Unknown personality %08x\n",
 894                        (u32)(shmem_info.config & FUNC_MF_CFG_PROTOCOL_MASK));
 895                 return -EINVAL;
 896         }
 897
 898         qed_read_pf_bandwidth(p_hwfn, &shmem_info);
 899
 900         if (shmem_info.mac_upper || shmem_info.mac_lower) {
 901                 info->mac[0] = (u8)(shmem_info.mac_upper >> 8);
 902                 info->mac[1] = (u8)(shmem_info.mac_upper);
 903                 info->mac[2] = (u8)(shmem_info.mac_lower >> 24);
 904                 info->mac[3] = (u8)(shmem_info.mac_lower >> 16);
 905                 info->mac[4] = (u8)(shmem_info.mac_lower >> 8);
 906                 info->mac[5] = (u8)(shmem_info.mac_lower);
 907         } else {
 908                 DP_NOTICE(p_hwfn, "MAC is 0 in shmem\n");
 909         }
 910
 911         info->wwn_port = (u64)shmem_info.fcoe_wwn_port_name_upper |
 912                          (((u64)shmem_info.fcoe_wwn_port_name_lower) << 32);
 913         info->wwn_node = (u64)shmem_info.fcoe_wwn_node_name_upper |
 914                          (((u64)shmem_info.fcoe_wwn_node_name_lower) << 32);
 915
 916         info->ovlan = (u16)(shmem_info.ovlan_stag & FUNC_MF_CFG_OV_STAG_MASK);
 917
 918         DP_VERBOSE(p_hwfn, (QED_MSG_SP | NETIF_MSG_IFUP),
 919                    "Read configuration from shmem: pause_on_host %02x protocol %02x BW [%02x - %02x] MAC %02x:%02x:%02x:%02x:%02x:%02x wwn port %llx node %llx ovlan %04x\n",
 920                 info->pause_on_host, info->protocol,
 921                 info->bandwidth_min, info->bandwidth_max,
 922                 info->mac[0], info->mac[1], info->mac[2],
 923                 info->mac[3], info->mac[4], info->mac[5],
 924                 info->wwn_port, info->wwn_node, info->ovlan);
 925
 926         return 0;
 927 }
 928
 929 struct qed_mcp_link_params
 930 *qed_mcp_get_link_params(struct qed_hwfn *p_hwfn)
 931 {
 932         if (!p_hwfn || !p_hwfn->mcp_info)
 933                 return NULL;
 934         return &p_hwfn->mcp_info->link_input;
 935 }
 936
 937 struct qed_mcp_link_state
 938 *qed_mcp_get_link_state(struct qed_hwfn *p_hwfn)
 939 {
 940         if (!p_hwfn || !p_hwfn->mcp_info)
 941                 return NULL;
 942         return &p_hwfn->mcp_info->link_output;
 943 }
 944
 945 struct qed_mcp_link_capabilities
 946 *qed_mcp_get_link_capabilities(struct qed_hwfn *p_hwfn)
 947 {
 948         if (!p_hwfn || !p_hwfn->mcp_info)
 949                 return NULL;
 950         return &p_hwfn->mcp_info->link_capabilities;
 951 }
 952
 953 int qed_mcp_drain(struct qed_hwfn *p_hwfn,
 954                   struct qed_ptt *p_ptt)
 955 {
 956         u32 resp = 0, param = 0;
 957         int rc;
 958
 959         rc = qed_mcp_cmd(p_hwfn, p_ptt,
 960                          DRV_MSG_CODE_NIG_DRAIN, 1000,
 961                          &resp, &param);
 962
 963         /* Wait for the drain to complete before returning */
 964         msleep(1020);
 965
 966         return rc;
 967 }
 968
 969 int qed_mcp_get_flash_size(struct qed_hwfn *p_hwfn,
 970                            struct qed_ptt *p_ptt,
 971                            u32 *p_flash_size)
 972 {
 973         u32 flash_size;
 974
 975         if (IS_VF(p_hwfn->cdev))
 976                 return -EINVAL;
 977
 978         flash_size = qed_rd(p_hwfn, p_ptt, MCP_REG_NVM_CFG4);
 979         flash_size = (flash_size & MCP_REG_NVM_CFG4_FLASH_SIZE) >>
 980                       MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT;
 981         flash_size = (1 << (flash_size + MCP_BYTES_PER_MBIT_SHIFT));
 982
 983         *p_flash_size = flash_size;
 984
 985         return 0;
 986 }
 987
 988 int qed_mcp_config_vf_msix(struct qed_hwfn *p_hwfn,
 989                            struct qed_ptt *p_ptt, u8 vf_id, u8 num)
 990 {
 991         u32 resp = 0, param = 0, rc_param = 0;
 992         int rc;
 993
 994         /* Only Leader can configure MSIX, and need to take CMT into account */
 995         if (!IS_LEAD_HWFN(p_hwfn))
 996                 return 0;
 997         num *= p_hwfn->cdev->num_hwfns;
 998
 999         param |= (vf_id << DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT) &
1000                  DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK;
1001         param |= (num << DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT) &
1002                  DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK;
1003
1004         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_VF_MSIX, param,
1005                          &resp, &rc_param);
1006
1007         if (resp != FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE) {
1008                 DP_NOTICE(p_hwfn, "VF[%d]: MFW failed to set MSI-X\n", vf_id);
1009                 rc = -EINVAL;
1010         } else {
1011                 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
1012                            "Requested 0x%02x MSI-x interrupts from VF 0x%02x\n",
1013                            num, vf_id);
1014         }
1015
1016         return rc;
1017 }
1018
1019 int
1020 qed_mcp_send_drv_version(struct qed_hwfn *p_hwfn,
1021                          struct qed_ptt *p_ptt,
1022                          struct qed_mcp_drv_version *p_ver)
1023 {
1024         struct drv_version_stc *p_drv_version;
1025         struct qed_mcp_mb_params mb_params;
1026         union drv_union_data union_data;
1027         __be32 val;
1028         u32 i;
1029         int rc;
1030
1031         p_drv_version = &union_data.drv_version;
1032         p_drv_version->version = p_ver->version;
1033
1034         for (i = 0; i < MCP_DRV_VER_STR_SIZE - 1; i += 4) {
1035                 val = cpu_to_be32(p_ver->name[i]);
1036                 *(__be32 *)&p_drv_version->name[i * sizeof(u32)] = val;
1037         }
1038
1039         memset(&mb_params, 0, sizeof(mb_params));
1040         mb_params.cmd = DRV_MSG_CODE_SET_VERSION;
1041         mb_params.p_data_src = &union_data;
1042         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1043         if (rc)
1044                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
1045
1046         return rc;
1047 }
1048
1049 int qed_mcp_set_led(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
1050                     enum qed_led_mode mode)
1051 {
1052         u32 resp = 0, param = 0, drv_mb_param;
1053         int rc;
1054
1055         switch (mode) {
1056         case QED_LED_MODE_ON:
1057                 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_ON;
1058                 break;
1059         case QED_LED_MODE_OFF:
1060                 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OFF;
1061                 break;
1062         case QED_LED_MODE_RESTORE:
1063                 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OPER;
1064                 break;
1065         default:
1066                 DP_NOTICE(p_hwfn, "Invalid LED mode %d\n", mode);
1067                 return -EINVAL;
1068         }
1069
1070         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_LED_MODE,
1071                          drv_mb_param, &resp, &param);
1072
1073         return rc;
1074 }
1075
1076 int qed_mcp_bist_register_test(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1077 {
1078         u32 drv_mb_param = 0, rsp, param;
1079         int rc = 0;
1080
1081         drv_mb_param = (DRV_MB_PARAM_BIST_REGISTER_TEST <<
1082                         DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
1083
1084         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
1085                          drv_mb_param, &rsp, &param);
1086
1087         if (rc)
1088                 return rc;
1089
1090         if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
1091             (param != DRV_MB_PARAM_BIST_RC_PASSED))
1092                 rc = -EAGAIN;
1093
1094         return rc;
1095 }
1096
1097 int qed_mcp_bist_clock_test(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1098 {
1099         u32 drv_mb_param, rsp, param;
1100         int rc = 0;
1101
1102         drv_mb_param = (DRV_MB_PARAM_BIST_CLOCK_TEST <<
1103                         DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
1104
1105         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
1106                          drv_mb_param, &rsp, &param);
1107
1108         if (rc)
1109                 return rc;
1110
1111         if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
1112             (param != DRV_MB_PARAM_BIST_RC_PASSED))
1113                 rc = -EAGAIN;
1114
1115         return rc;
1116 }