1 /* QLogic qed NIC Driver
2 * Copyright (c) 2015-2017 QLogic Corporation
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and /or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/stddef.h>
34 #include <linux/pci.h>
35 #include <linux/kernel.h>
36 #include <linux/slab.h>
37 #include <linux/delay.h>
38 #include <asm/byteorder.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/string.h>
41 #include <linux/module.h>
42 #include <linux/interrupt.h>
43 #include <linux/workqueue.h>
44 #include <linux/ethtool.h>
45 #include <linux/etherdevice.h>
46 #include <linux/vmalloc.h>
47 #include <linux/crash_dump.h>
48 #include <linux/crc32.h>
49 #include <linux/qed/qed_if.h>
50 #include <linux/qed/qed_ll2_if.h>
53 #include "qed_sriov.h"
55 #include "qed_dev_api.h"
58 #include "qed_iscsi.h"
61 #include "qed_reg_addr.h"
63 #include "qed_selftest.h"
64 #include "qed_debug.h"
66 #define QED_ROCE_QPS (8192)
67 #define QED_ROCE_DPIS (8)
68 #define QED_RDMA_SRQS QED_ROCE_QPS
70 static char version[] =
71 "QLogic FastLinQ 4xxxx Core Module qed " DRV_MODULE_VERSION "\n";
73 MODULE_DESCRIPTION("QLogic FastLinQ 4xxxx Core Module");
74 MODULE_LICENSE("GPL");
75 MODULE_VERSION(DRV_MODULE_VERSION);
77 #define FW_FILE_VERSION \
78 __stringify(FW_MAJOR_VERSION) "." \
79 __stringify(FW_MINOR_VERSION) "." \
80 __stringify(FW_REVISION_VERSION) "." \
81 __stringify(FW_ENGINEERING_VERSION)
83 #define QED_FW_FILE_NAME \
84 "qed/qed_init_values_zipped-" FW_FILE_VERSION ".bin"
86 MODULE_FIRMWARE(QED_FW_FILE_NAME);
88 static int __init qed_init(void)
90 pr_info("%s", version);
95 static void __exit qed_cleanup(void)
97 pr_notice("qed_cleanup called\n");
100 module_init(qed_init);
101 module_exit(qed_cleanup);
103 /* Check if the DMA controller on the machine can properly handle the DMA
104 * addressing required by the device.
106 static int qed_set_coherency_mask(struct qed_dev *cdev)
108 struct device *dev = &cdev->pdev->dev;
110 if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) {
111 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) {
113 "Can't request 64-bit consistent allocations\n");
116 } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) {
117 DP_NOTICE(cdev, "Can't request 64b/32b DMA addresses\n");
124 static void qed_free_pci(struct qed_dev *cdev)
126 struct pci_dev *pdev = cdev->pdev;
128 if (cdev->doorbells && cdev->db_size)
129 iounmap(cdev->doorbells);
131 iounmap(cdev->regview);
132 if (atomic_read(&pdev->enable_cnt) == 1)
133 pci_release_regions(pdev);
135 pci_disable_device(pdev);
138 #define PCI_REVISION_ID_ERROR_VAL 0xff
140 /* Performs PCI initializations as well as initializing PCI-related parameters
141 * in the device structrue. Returns 0 in case of success.
143 static int qed_init_pci(struct qed_dev *cdev, struct pci_dev *pdev)
150 rc = pci_enable_device(pdev);
152 DP_NOTICE(cdev, "Cannot enable PCI device\n");
156 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
157 DP_NOTICE(cdev, "No memory region found in bar #0\n");
162 if (IS_PF(cdev) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
163 DP_NOTICE(cdev, "No memory region found in bar #2\n");
168 if (atomic_read(&pdev->enable_cnt) == 1) {
169 rc = pci_request_regions(pdev, "qed");
172 "Failed to request PCI memory resources\n");
175 pci_set_master(pdev);
176 pci_save_state(pdev);
179 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
180 if (rev_id == PCI_REVISION_ID_ERROR_VAL) {
182 "Detected PCI device error [rev_id 0x%x]. Probably due to prior indication. Aborting.\n",
187 if (!pci_is_pcie(pdev)) {
188 DP_NOTICE(cdev, "The bus is not PCI Express\n");
193 cdev->pci_params.pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
194 if (IS_PF(cdev) && !cdev->pci_params.pm_cap)
195 DP_NOTICE(cdev, "Cannot find power management capability\n");
197 rc = qed_set_coherency_mask(cdev);
201 cdev->pci_params.mem_start = pci_resource_start(pdev, 0);
202 cdev->pci_params.mem_end = pci_resource_end(pdev, 0);
203 cdev->pci_params.irq = pdev->irq;
205 cdev->regview = pci_ioremap_bar(pdev, 0);
206 if (!cdev->regview) {
207 DP_NOTICE(cdev, "Cannot map register space, aborting\n");
212 cdev->db_phys_addr = pci_resource_start(cdev->pdev, 2);
213 cdev->db_size = pci_resource_len(cdev->pdev, 2);
214 if (!cdev->db_size) {
216 DP_NOTICE(cdev, "No Doorbell bar available\n");
223 cdev->doorbells = ioremap_wc(cdev->db_phys_addr, cdev->db_size);
225 if (!cdev->doorbells) {
226 DP_NOTICE(cdev, "Cannot map doorbell space\n");
233 pci_release_regions(pdev);
235 pci_disable_device(pdev);
240 int qed_fill_dev_info(struct qed_dev *cdev,
241 struct qed_dev_info *dev_info)
243 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
244 struct qed_hw_info *hw_info = &p_hwfn->hw_info;
245 struct qed_tunnel_info *tun = &cdev->tunnel;
248 memset(dev_info, 0, sizeof(struct qed_dev_info));
250 if (tun->vxlan.tun_cls == QED_TUNN_CLSS_MAC_VLAN &&
251 tun->vxlan.b_mode_enabled)
252 dev_info->vxlan_enable = true;
254 if (tun->l2_gre.b_mode_enabled && tun->ip_gre.b_mode_enabled &&
255 tun->l2_gre.tun_cls == QED_TUNN_CLSS_MAC_VLAN &&
256 tun->ip_gre.tun_cls == QED_TUNN_CLSS_MAC_VLAN)
257 dev_info->gre_enable = true;
259 if (tun->l2_geneve.b_mode_enabled && tun->ip_geneve.b_mode_enabled &&
260 tun->l2_geneve.tun_cls == QED_TUNN_CLSS_MAC_VLAN &&
261 tun->ip_geneve.tun_cls == QED_TUNN_CLSS_MAC_VLAN)
262 dev_info->geneve_enable = true;
264 dev_info->num_hwfns = cdev->num_hwfns;
265 dev_info->pci_mem_start = cdev->pci_params.mem_start;
266 dev_info->pci_mem_end = cdev->pci_params.mem_end;
267 dev_info->pci_irq = cdev->pci_params.irq;
268 dev_info->rdma_supported = QED_IS_RDMA_PERSONALITY(p_hwfn);
269 dev_info->dev_type = cdev->type;
270 ether_addr_copy(dev_info->hw_mac, hw_info->hw_mac_addr);
273 dev_info->fw_major = FW_MAJOR_VERSION;
274 dev_info->fw_minor = FW_MINOR_VERSION;
275 dev_info->fw_rev = FW_REVISION_VERSION;
276 dev_info->fw_eng = FW_ENGINEERING_VERSION;
277 dev_info->b_inter_pf_switch = test_bit(QED_MF_INTER_PF_SWITCH,
279 dev_info->tx_switching = true;
281 if (hw_info->b_wol_support == QED_WOL_SUPPORT_PME)
282 dev_info->wol_support = true;
284 dev_info->smart_an = qed_mcp_is_smart_an_supported(p_hwfn);
286 dev_info->abs_pf_id = QED_LEADING_HWFN(cdev)->abs_pf_id;
288 qed_vf_get_fw_version(&cdev->hwfns[0], &dev_info->fw_major,
289 &dev_info->fw_minor, &dev_info->fw_rev,
294 ptt = qed_ptt_acquire(QED_LEADING_HWFN(cdev));
296 qed_mcp_get_mfw_ver(QED_LEADING_HWFN(cdev), ptt,
297 &dev_info->mfw_rev, NULL);
299 qed_mcp_get_mbi_ver(QED_LEADING_HWFN(cdev), ptt,
300 &dev_info->mbi_version);
302 qed_mcp_get_flash_size(QED_LEADING_HWFN(cdev), ptt,
303 &dev_info->flash_size);
305 qed_ptt_release(QED_LEADING_HWFN(cdev), ptt);
308 qed_mcp_get_mfw_ver(QED_LEADING_HWFN(cdev), NULL,
309 &dev_info->mfw_rev, NULL);
312 dev_info->mtu = hw_info->mtu;
317 static void qed_free_cdev(struct qed_dev *cdev)
322 static struct qed_dev *qed_alloc_cdev(struct pci_dev *pdev)
324 struct qed_dev *cdev;
326 cdev = kzalloc(sizeof(*cdev), GFP_KERNEL);
330 qed_init_struct(cdev);
335 /* Sets the requested power state */
336 static int qed_set_power_state(struct qed_dev *cdev, pci_power_t state)
341 DP_VERBOSE(cdev, NETIF_MSG_DRV, "Omitting Power state change\n");
346 static struct qed_dev *qed_probe(struct pci_dev *pdev,
347 struct qed_probe_params *params)
349 struct qed_dev *cdev;
352 cdev = qed_alloc_cdev(pdev);
356 cdev->drv_type = DRV_ID_DRV_TYPE_LINUX;
357 cdev->protocol = params->protocol;
360 cdev->b_is_vf = true;
362 qed_init_dp(cdev, params->dp_module, params->dp_level);
364 cdev->recov_in_prog = params->recov_in_prog;
366 rc = qed_init_pci(cdev, pdev);
368 DP_ERR(cdev, "init pci failed\n");
371 DP_INFO(cdev, "PCI init completed successfully\n");
373 rc = qed_hw_prepare(cdev, QED_PCI_DEFAULT);
375 DP_ERR(cdev, "hw prepare failed\n");
379 DP_INFO(cdev, "qed_probe completed successfully\n");
391 static void qed_remove(struct qed_dev *cdev)
400 qed_set_power_state(cdev, PCI_D3hot);
405 static void qed_disable_msix(struct qed_dev *cdev)
407 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) {
408 pci_disable_msix(cdev->pdev);
409 kfree(cdev->int_params.msix_table);
410 } else if (cdev->int_params.out.int_mode == QED_INT_MODE_MSI) {
411 pci_disable_msi(cdev->pdev);
414 memset(&cdev->int_params.out, 0, sizeof(struct qed_int_param));
417 static int qed_enable_msix(struct qed_dev *cdev,
418 struct qed_int_params *int_params)
422 cnt = int_params->in.num_vectors;
424 for (i = 0; i < cnt; i++)
425 int_params->msix_table[i].entry = i;
427 rc = pci_enable_msix_range(cdev->pdev, int_params->msix_table,
428 int_params->in.min_msix_cnt, cnt);
429 if (rc < cnt && rc >= int_params->in.min_msix_cnt &&
430 (rc % cdev->num_hwfns)) {
431 pci_disable_msix(cdev->pdev);
433 /* If fastpath is initialized, we need at least one interrupt
434 * per hwfn [and the slow path interrupts]. New requested number
435 * should be a multiple of the number of hwfns.
437 cnt = (rc / cdev->num_hwfns) * cdev->num_hwfns;
439 "Trying to enable MSI-X with less vectors (%d out of %d)\n",
440 cnt, int_params->in.num_vectors);
441 rc = pci_enable_msix_exact(cdev->pdev, int_params->msix_table,
448 /* MSI-x configuration was achieved */
449 int_params->out.int_mode = QED_INT_MODE_MSIX;
450 int_params->out.num_vectors = rc;
454 "Failed to enable MSI-X [Requested %d vectors][rc %d]\n",
461 /* This function outputs the int mode and the number of enabled msix vector */
462 static int qed_set_int_mode(struct qed_dev *cdev, bool force_mode)
464 struct qed_int_params *int_params = &cdev->int_params;
465 struct msix_entry *tbl;
468 switch (int_params->in.int_mode) {
469 case QED_INT_MODE_MSIX:
470 /* Allocate MSIX table */
471 cnt = int_params->in.num_vectors;
472 int_params->msix_table = kcalloc(cnt, sizeof(*tbl), GFP_KERNEL);
473 if (!int_params->msix_table) {
479 rc = qed_enable_msix(cdev, int_params);
483 DP_NOTICE(cdev, "Failed to enable MSI-X\n");
484 kfree(int_params->msix_table);
489 case QED_INT_MODE_MSI:
490 if (cdev->num_hwfns == 1) {
491 rc = pci_enable_msi(cdev->pdev);
493 int_params->out.int_mode = QED_INT_MODE_MSI;
497 DP_NOTICE(cdev, "Failed to enable MSI\n");
503 case QED_INT_MODE_INTA:
504 int_params->out.int_mode = QED_INT_MODE_INTA;
508 DP_NOTICE(cdev, "Unknown int_mode value %d\n",
509 int_params->in.int_mode);
515 DP_INFO(cdev, "Using %s interrupts\n",
516 int_params->out.int_mode == QED_INT_MODE_INTA ?
517 "INTa" : int_params->out.int_mode == QED_INT_MODE_MSI ?
519 cdev->int_coalescing_mode = QED_COAL_MODE_ENABLE;
524 static void qed_simd_handler_config(struct qed_dev *cdev, void *token,
525 int index, void(*handler)(void *))
527 struct qed_hwfn *hwfn = &cdev->hwfns[index % cdev->num_hwfns];
528 int relative_idx = index / cdev->num_hwfns;
530 hwfn->simd_proto_handler[relative_idx].func = handler;
531 hwfn->simd_proto_handler[relative_idx].token = token;
534 static void qed_simd_handler_clean(struct qed_dev *cdev, int index)
536 struct qed_hwfn *hwfn = &cdev->hwfns[index % cdev->num_hwfns];
537 int relative_idx = index / cdev->num_hwfns;
539 memset(&hwfn->simd_proto_handler[relative_idx], 0,
540 sizeof(struct qed_simd_fp_handler));
543 static irqreturn_t qed_msix_sp_int(int irq, void *tasklet)
545 tasklet_schedule((struct tasklet_struct *)tasklet);
549 static irqreturn_t qed_single_int(int irq, void *dev_instance)
551 struct qed_dev *cdev = (struct qed_dev *)dev_instance;
552 struct qed_hwfn *hwfn;
553 irqreturn_t rc = IRQ_NONE;
557 for (i = 0; i < cdev->num_hwfns; i++) {
558 status = qed_int_igu_read_sisr_reg(&cdev->hwfns[i]);
563 hwfn = &cdev->hwfns[i];
565 /* Slowpath interrupt */
566 if (unlikely(status & 0x1)) {
567 tasklet_schedule(hwfn->sp_dpc);
572 /* Fastpath interrupts */
573 for (j = 0; j < 64; j++) {
574 if ((0x2ULL << j) & status) {
575 struct qed_simd_fp_handler *p_handler =
576 &hwfn->simd_proto_handler[j];
579 p_handler->func(p_handler->token);
582 "Not calling fastpath handler as it is NULL [handler #%d, status 0x%llx]\n",
585 status &= ~(0x2ULL << j);
590 if (unlikely(status))
591 DP_VERBOSE(hwfn, NETIF_MSG_INTR,
592 "got an unknown interrupt status 0x%llx\n",
599 int qed_slowpath_irq_req(struct qed_hwfn *hwfn)
601 struct qed_dev *cdev = hwfn->cdev;
606 int_mode = cdev->int_params.out.int_mode;
607 if (int_mode == QED_INT_MODE_MSIX) {
609 snprintf(hwfn->name, NAME_SIZE, "sp-%d-%02x:%02x.%02x",
610 id, cdev->pdev->bus->number,
611 PCI_SLOT(cdev->pdev->devfn), hwfn->abs_pf_id);
612 rc = request_irq(cdev->int_params.msix_table[id].vector,
613 qed_msix_sp_int, 0, hwfn->name, hwfn->sp_dpc);
615 unsigned long flags = 0;
617 snprintf(cdev->name, NAME_SIZE, "%02x:%02x.%02x",
618 cdev->pdev->bus->number, PCI_SLOT(cdev->pdev->devfn),
619 PCI_FUNC(cdev->pdev->devfn));
621 if (cdev->int_params.out.int_mode == QED_INT_MODE_INTA)
622 flags |= IRQF_SHARED;
624 rc = request_irq(cdev->pdev->irq, qed_single_int,
625 flags, cdev->name, cdev);
629 DP_NOTICE(cdev, "request_irq failed, rc = %d\n", rc);
631 DP_VERBOSE(hwfn, (NETIF_MSG_INTR | QED_MSG_SP),
632 "Requested slowpath %s\n",
633 (int_mode == QED_INT_MODE_MSIX) ? "MSI-X" : "IRQ");
638 static void qed_slowpath_tasklet_flush(struct qed_hwfn *p_hwfn)
640 /* Calling the disable function will make sure that any
641 * currently-running function is completed. The following call to the
642 * enable function makes this sequence a flush-like operation.
644 if (p_hwfn->b_sp_dpc_enabled) {
645 tasklet_disable(p_hwfn->sp_dpc);
646 tasklet_enable(p_hwfn->sp_dpc);
650 void qed_slowpath_irq_sync(struct qed_hwfn *p_hwfn)
652 struct qed_dev *cdev = p_hwfn->cdev;
653 u8 id = p_hwfn->my_id;
656 int_mode = cdev->int_params.out.int_mode;
657 if (int_mode == QED_INT_MODE_MSIX)
658 synchronize_irq(cdev->int_params.msix_table[id].vector);
660 synchronize_irq(cdev->pdev->irq);
662 qed_slowpath_tasklet_flush(p_hwfn);
665 static void qed_slowpath_irq_free(struct qed_dev *cdev)
669 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) {
670 for_each_hwfn(cdev, i) {
671 if (!cdev->hwfns[i].b_int_requested)
673 synchronize_irq(cdev->int_params.msix_table[i].vector);
674 free_irq(cdev->int_params.msix_table[i].vector,
675 cdev->hwfns[i].sp_dpc);
678 if (QED_LEADING_HWFN(cdev)->b_int_requested)
679 free_irq(cdev->pdev->irq, cdev);
681 qed_int_disable_post_isr_release(cdev);
684 static int qed_nic_stop(struct qed_dev *cdev)
688 rc = qed_hw_stop(cdev);
690 for (i = 0; i < cdev->num_hwfns; i++) {
691 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
693 if (p_hwfn->b_sp_dpc_enabled) {
694 tasklet_disable(p_hwfn->sp_dpc);
695 p_hwfn->b_sp_dpc_enabled = false;
696 DP_VERBOSE(cdev, NETIF_MSG_IFDOWN,
697 "Disabled sp tasklet [hwfn %d] at %p\n",
702 qed_dbg_pf_exit(cdev);
707 static int qed_nic_setup(struct qed_dev *cdev)
711 /* Determine if interface is going to require LL2 */
712 if (QED_LEADING_HWFN(cdev)->hw_info.personality != QED_PCI_ETH) {
713 for (i = 0; i < cdev->num_hwfns; i++) {
714 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
716 p_hwfn->using_ll2 = true;
720 rc = qed_resc_alloc(cdev);
724 DP_INFO(cdev, "Allocated qed resources\n");
726 qed_resc_setup(cdev);
731 static int qed_set_int_fp(struct qed_dev *cdev, u16 cnt)
735 /* Mark the fastpath as free/used */
736 cdev->int_params.fp_initialized = cnt ? true : false;
738 if (cdev->int_params.out.int_mode != QED_INT_MODE_MSIX)
739 limit = cdev->num_hwfns * 63;
740 else if (cdev->int_params.fp_msix_cnt)
741 limit = cdev->int_params.fp_msix_cnt;
746 return min_t(int, cnt, limit);
749 static int qed_get_int_fp(struct qed_dev *cdev, struct qed_int_info *info)
751 memset(info, 0, sizeof(struct qed_int_info));
753 if (!cdev->int_params.fp_initialized) {
755 "Protocol driver requested interrupt information, but its support is not yet configured\n");
759 /* Need to expose only MSI-X information; Single IRQ is handled solely
762 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) {
763 int msix_base = cdev->int_params.fp_msix_base;
765 info->msix_cnt = cdev->int_params.fp_msix_cnt;
766 info->msix = &cdev->int_params.msix_table[msix_base];
772 static int qed_slowpath_setup_int(struct qed_dev *cdev,
773 enum qed_int_mode int_mode)
775 struct qed_sb_cnt_info sb_cnt_info;
776 int num_l2_queues = 0;
780 if ((int_mode == QED_INT_MODE_MSI) && (cdev->num_hwfns > 1)) {
781 DP_NOTICE(cdev, "MSI mode is not supported for CMT devices\n");
785 memset(&cdev->int_params, 0, sizeof(struct qed_int_params));
786 cdev->int_params.in.int_mode = int_mode;
787 for_each_hwfn(cdev, i) {
788 memset(&sb_cnt_info, 0, sizeof(sb_cnt_info));
789 qed_int_get_num_sbs(&cdev->hwfns[i], &sb_cnt_info);
790 cdev->int_params.in.num_vectors += sb_cnt_info.cnt;
791 cdev->int_params.in.num_vectors++; /* slowpath */
794 /* We want a minimum of one slowpath and one fastpath vector per hwfn */
795 cdev->int_params.in.min_msix_cnt = cdev->num_hwfns * 2;
797 if (is_kdump_kernel()) {
799 "Kdump kernel: Limit the max number of requested MSI-X vectors to %hd\n",
800 cdev->int_params.in.min_msix_cnt);
801 cdev->int_params.in.num_vectors =
802 cdev->int_params.in.min_msix_cnt;
805 rc = qed_set_int_mode(cdev, false);
807 DP_ERR(cdev, "qed_slowpath_setup_int ERR\n");
811 cdev->int_params.fp_msix_base = cdev->num_hwfns;
812 cdev->int_params.fp_msix_cnt = cdev->int_params.out.num_vectors -
815 if (!IS_ENABLED(CONFIG_QED_RDMA) ||
816 !QED_IS_RDMA_PERSONALITY(QED_LEADING_HWFN(cdev)))
819 for_each_hwfn(cdev, i)
820 num_l2_queues += FEAT_NUM(&cdev->hwfns[i], QED_PF_L2_QUE);
822 DP_VERBOSE(cdev, QED_MSG_RDMA,
823 "cdev->int_params.fp_msix_cnt=%d num_l2_queues=%d\n",
824 cdev->int_params.fp_msix_cnt, num_l2_queues);
826 if (cdev->int_params.fp_msix_cnt > num_l2_queues) {
827 cdev->int_params.rdma_msix_cnt =
828 (cdev->int_params.fp_msix_cnt - num_l2_queues)
830 cdev->int_params.rdma_msix_base =
831 cdev->int_params.fp_msix_base + num_l2_queues;
832 cdev->int_params.fp_msix_cnt = num_l2_queues;
834 cdev->int_params.rdma_msix_cnt = 0;
837 DP_VERBOSE(cdev, QED_MSG_RDMA, "roce_msix_cnt=%d roce_msix_base=%d\n",
838 cdev->int_params.rdma_msix_cnt,
839 cdev->int_params.rdma_msix_base);
844 static int qed_slowpath_vf_setup_int(struct qed_dev *cdev)
848 memset(&cdev->int_params, 0, sizeof(struct qed_int_params));
849 cdev->int_params.in.int_mode = QED_INT_MODE_MSIX;
851 qed_vf_get_num_rxqs(QED_LEADING_HWFN(cdev),
852 &cdev->int_params.in.num_vectors);
853 if (cdev->num_hwfns > 1) {
856 qed_vf_get_num_rxqs(&cdev->hwfns[1], &vectors);
857 cdev->int_params.in.num_vectors += vectors;
860 /* We want a minimum of one fastpath vector per vf hwfn */
861 cdev->int_params.in.min_msix_cnt = cdev->num_hwfns;
863 rc = qed_set_int_mode(cdev, true);
867 cdev->int_params.fp_msix_base = 0;
868 cdev->int_params.fp_msix_cnt = cdev->int_params.out.num_vectors;
873 u32 qed_unzip_data(struct qed_hwfn *p_hwfn, u32 input_len,
874 u8 *input_buf, u32 max_size, u8 *unzip_buf)
878 p_hwfn->stream->next_in = input_buf;
879 p_hwfn->stream->avail_in = input_len;
880 p_hwfn->stream->next_out = unzip_buf;
881 p_hwfn->stream->avail_out = max_size;
883 rc = zlib_inflateInit2(p_hwfn->stream, MAX_WBITS);
886 DP_VERBOSE(p_hwfn, NETIF_MSG_DRV, "zlib init failed, rc = %d\n",
891 rc = zlib_inflate(p_hwfn->stream, Z_FINISH);
892 zlib_inflateEnd(p_hwfn->stream);
894 if (rc != Z_OK && rc != Z_STREAM_END) {
895 DP_VERBOSE(p_hwfn, NETIF_MSG_DRV, "FW unzip error: %s, rc=%d\n",
896 p_hwfn->stream->msg, rc);
900 return p_hwfn->stream->total_out / 4;
903 static int qed_alloc_stream_mem(struct qed_dev *cdev)
908 for_each_hwfn(cdev, i) {
909 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
911 p_hwfn->stream = kzalloc(sizeof(*p_hwfn->stream), GFP_KERNEL);
915 workspace = vzalloc(zlib_inflate_workspacesize());
918 p_hwfn->stream->workspace = workspace;
924 static void qed_free_stream_mem(struct qed_dev *cdev)
928 for_each_hwfn(cdev, i) {
929 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
934 vfree(p_hwfn->stream->workspace);
935 kfree(p_hwfn->stream);
939 static void qed_update_pf_params(struct qed_dev *cdev,
940 struct qed_pf_params *params)
944 if (IS_ENABLED(CONFIG_QED_RDMA)) {
945 params->rdma_pf_params.num_qps = QED_ROCE_QPS;
946 params->rdma_pf_params.min_dpis = QED_ROCE_DPIS;
947 params->rdma_pf_params.num_srqs = QED_RDMA_SRQS;
948 /* divide by 3 the MRs to avoid MF ILT overflow */
949 params->rdma_pf_params.gl_pi = QED_ROCE_PROTOCOL_INDEX;
952 if (cdev->num_hwfns > 1 || IS_VF(cdev))
953 params->eth_pf_params.num_arfs_filters = 0;
955 /* In case we might support RDMA, don't allow qede to be greedy
956 * with the L2 contexts. Allow for 64 queues [rx, tx cos, xdp]
959 if (QED_IS_RDMA_PERSONALITY(QED_LEADING_HWFN(cdev))) {
962 num_cons = ¶ms->eth_pf_params.num_cons;
963 *num_cons = min_t(u16, *num_cons, QED_MAX_L2_CONS);
966 for (i = 0; i < cdev->num_hwfns; i++) {
967 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
969 p_hwfn->pf_params = *params;
973 #define QED_PERIODIC_DB_REC_COUNT 10
974 #define QED_PERIODIC_DB_REC_INTERVAL_MS 100
975 #define QED_PERIODIC_DB_REC_INTERVAL \
976 msecs_to_jiffies(QED_PERIODIC_DB_REC_INTERVAL_MS)
977 #define QED_PERIODIC_DB_REC_WAIT_COUNT 10
978 #define QED_PERIODIC_DB_REC_WAIT_INTERVAL \
979 (QED_PERIODIC_DB_REC_INTERVAL_MS / QED_PERIODIC_DB_REC_WAIT_COUNT)
981 static int qed_slowpath_delayed_work(struct qed_hwfn *hwfn,
982 enum qed_slowpath_wq_flag wq_flag,
985 if (!hwfn->slowpath_wq_active)
988 /* Memory barrier for setting atomic bit */
989 smp_mb__before_atomic();
990 set_bit(wq_flag, &hwfn->slowpath_task_flags);
991 smp_mb__after_atomic();
992 queue_delayed_work(hwfn->slowpath_wq, &hwfn->slowpath_task, delay);
997 void qed_periodic_db_rec_start(struct qed_hwfn *p_hwfn)
999 /* Reset periodic Doorbell Recovery counter */
1000 p_hwfn->periodic_db_rec_count = QED_PERIODIC_DB_REC_COUNT;
1002 /* Don't schedule periodic Doorbell Recovery if already scheduled */
1003 if (test_bit(QED_SLOWPATH_PERIODIC_DB_REC,
1004 &p_hwfn->slowpath_task_flags))
1007 qed_slowpath_delayed_work(p_hwfn, QED_SLOWPATH_PERIODIC_DB_REC,
1008 QED_PERIODIC_DB_REC_INTERVAL);
1011 static void qed_slowpath_wq_stop(struct qed_dev *cdev)
1013 int i, sleep_count = QED_PERIODIC_DB_REC_WAIT_COUNT;
1018 for_each_hwfn(cdev, i) {
1019 if (!cdev->hwfns[i].slowpath_wq)
1022 /* Stop queuing new delayed works */
1023 cdev->hwfns[i].slowpath_wq_active = false;
1025 /* Wait until the last periodic doorbell recovery is executed */
1026 while (test_bit(QED_SLOWPATH_PERIODIC_DB_REC,
1027 &cdev->hwfns[i].slowpath_task_flags) &&
1029 msleep(QED_PERIODIC_DB_REC_WAIT_INTERVAL);
1031 flush_workqueue(cdev->hwfns[i].slowpath_wq);
1032 destroy_workqueue(cdev->hwfns[i].slowpath_wq);
1036 static void qed_slowpath_task(struct work_struct *work)
1038 struct qed_hwfn *hwfn = container_of(work, struct qed_hwfn,
1039 slowpath_task.work);
1040 struct qed_ptt *ptt = qed_ptt_acquire(hwfn);
1043 if (hwfn->slowpath_wq_active)
1044 queue_delayed_work(hwfn->slowpath_wq,
1045 &hwfn->slowpath_task, 0);
1050 if (test_and_clear_bit(QED_SLOWPATH_MFW_TLV_REQ,
1051 &hwfn->slowpath_task_flags))
1052 qed_mfw_process_tlv_req(hwfn, ptt);
1054 if (test_and_clear_bit(QED_SLOWPATH_PERIODIC_DB_REC,
1055 &hwfn->slowpath_task_flags)) {
1056 qed_db_rec_handler(hwfn, ptt);
1057 if (hwfn->periodic_db_rec_count--)
1058 qed_slowpath_delayed_work(hwfn,
1059 QED_SLOWPATH_PERIODIC_DB_REC,
1060 QED_PERIODIC_DB_REC_INTERVAL);
1063 qed_ptt_release(hwfn, ptt);
1066 static int qed_slowpath_wq_start(struct qed_dev *cdev)
1068 struct qed_hwfn *hwfn;
1069 char name[NAME_SIZE];
1075 for_each_hwfn(cdev, i) {
1076 hwfn = &cdev->hwfns[i];
1078 snprintf(name, NAME_SIZE, "slowpath-%02x:%02x.%02x",
1079 cdev->pdev->bus->number,
1080 PCI_SLOT(cdev->pdev->devfn), hwfn->abs_pf_id);
1082 hwfn->slowpath_wq = alloc_workqueue(name, 0, 0);
1083 if (!hwfn->slowpath_wq) {
1084 DP_NOTICE(hwfn, "Cannot create slowpath workqueue\n");
1088 INIT_DELAYED_WORK(&hwfn->slowpath_task, qed_slowpath_task);
1089 hwfn->slowpath_wq_active = true;
1095 static int qed_slowpath_start(struct qed_dev *cdev,
1096 struct qed_slowpath_params *params)
1098 struct qed_drv_load_params drv_load_params;
1099 struct qed_hw_init_params hw_init_params;
1100 struct qed_mcp_drv_version drv_version;
1101 struct qed_tunnel_info tunn_info;
1102 const u8 *data = NULL;
1103 struct qed_hwfn *hwfn;
1104 struct qed_ptt *p_ptt;
1107 if (qed_iov_wq_start(cdev))
1110 if (qed_slowpath_wq_start(cdev))
1114 rc = request_firmware(&cdev->firmware, QED_FW_FILE_NAME,
1118 "Failed to find fw file - /lib/firmware/%s\n",
1123 if (cdev->num_hwfns == 1) {
1124 p_ptt = qed_ptt_acquire(QED_LEADING_HWFN(cdev));
1126 QED_LEADING_HWFN(cdev)->p_arfs_ptt = p_ptt;
1129 "Failed to acquire PTT for aRFS\n");
1135 cdev->rx_coalesce_usecs = QED_DEFAULT_RX_USECS;
1136 rc = qed_nic_setup(cdev);
1141 rc = qed_slowpath_setup_int(cdev, params->int_mode);
1143 rc = qed_slowpath_vf_setup_int(cdev);
1148 /* Allocate stream for unzipping */
1149 rc = qed_alloc_stream_mem(cdev);
1153 /* First Dword used to differentiate between various sources */
1154 data = cdev->firmware->data + sizeof(u32);
1156 qed_dbg_pf_init(cdev);
1159 /* Start the slowpath */
1160 memset(&hw_init_params, 0, sizeof(hw_init_params));
1161 memset(&tunn_info, 0, sizeof(tunn_info));
1162 tunn_info.vxlan.b_mode_enabled = true;
1163 tunn_info.l2_gre.b_mode_enabled = true;
1164 tunn_info.ip_gre.b_mode_enabled = true;
1165 tunn_info.l2_geneve.b_mode_enabled = true;
1166 tunn_info.ip_geneve.b_mode_enabled = true;
1167 tunn_info.vxlan.tun_cls = QED_TUNN_CLSS_MAC_VLAN;
1168 tunn_info.l2_gre.tun_cls = QED_TUNN_CLSS_MAC_VLAN;
1169 tunn_info.ip_gre.tun_cls = QED_TUNN_CLSS_MAC_VLAN;
1170 tunn_info.l2_geneve.tun_cls = QED_TUNN_CLSS_MAC_VLAN;
1171 tunn_info.ip_geneve.tun_cls = QED_TUNN_CLSS_MAC_VLAN;
1172 hw_init_params.p_tunn = &tunn_info;
1173 hw_init_params.b_hw_start = true;
1174 hw_init_params.int_mode = cdev->int_params.out.int_mode;
1175 hw_init_params.allow_npar_tx_switch = true;
1176 hw_init_params.bin_fw_data = data;
1178 memset(&drv_load_params, 0, sizeof(drv_load_params));
1179 drv_load_params.is_crash_kernel = is_kdump_kernel();
1180 drv_load_params.mfw_timeout_val = QED_LOAD_REQ_LOCK_TO_DEFAULT;
1181 drv_load_params.avoid_eng_reset = false;
1182 drv_load_params.override_force_load = QED_OVERRIDE_FORCE_LOAD_NONE;
1183 hw_init_params.p_drv_load_params = &drv_load_params;
1185 rc = qed_hw_init(cdev, &hw_init_params);
1190 "HW initialization and function start completed successfully\n");
1193 cdev->tunn_feature_mask = (BIT(QED_MODE_VXLAN_TUNN) |
1194 BIT(QED_MODE_L2GENEVE_TUNN) |
1195 BIT(QED_MODE_IPGENEVE_TUNN) |
1196 BIT(QED_MODE_L2GRE_TUNN) |
1197 BIT(QED_MODE_IPGRE_TUNN));
1200 /* Allocate LL2 interface if needed */
1201 if (QED_LEADING_HWFN(cdev)->using_ll2) {
1202 rc = qed_ll2_alloc_if(cdev);
1207 hwfn = QED_LEADING_HWFN(cdev);
1208 drv_version.version = (params->drv_major << 24) |
1209 (params->drv_minor << 16) |
1210 (params->drv_rev << 8) |
1212 strlcpy(drv_version.name, params->name,
1213 MCP_DRV_VER_STR_SIZE - 4);
1214 rc = qed_mcp_send_drv_version(hwfn, hwfn->p_main_ptt,
1217 DP_NOTICE(cdev, "Failed sending drv version command\n");
1222 qed_reset_vport_stats(cdev);
1229 qed_hw_timers_stop_all(cdev);
1231 qed_slowpath_irq_free(cdev);
1232 qed_free_stream_mem(cdev);
1233 qed_disable_msix(cdev);
1235 qed_resc_free(cdev);
1238 release_firmware(cdev->firmware);
1240 if (IS_PF(cdev) && (cdev->num_hwfns == 1) &&
1241 QED_LEADING_HWFN(cdev)->p_arfs_ptt)
1242 qed_ptt_release(QED_LEADING_HWFN(cdev),
1243 QED_LEADING_HWFN(cdev)->p_arfs_ptt);
1245 qed_iov_wq_stop(cdev, false);
1247 qed_slowpath_wq_stop(cdev);
1252 static int qed_slowpath_stop(struct qed_dev *cdev)
1257 qed_slowpath_wq_stop(cdev);
1259 qed_ll2_dealloc_if(cdev);
1262 if (cdev->num_hwfns == 1)
1263 qed_ptt_release(QED_LEADING_HWFN(cdev),
1264 QED_LEADING_HWFN(cdev)->p_arfs_ptt);
1265 qed_free_stream_mem(cdev);
1266 if (IS_QED_ETH_IF(cdev))
1267 qed_sriov_disable(cdev, true);
1273 qed_slowpath_irq_free(cdev);
1275 qed_disable_msix(cdev);
1277 qed_resc_free(cdev);
1279 qed_iov_wq_stop(cdev, true);
1282 release_firmware(cdev->firmware);
1287 static void qed_set_name(struct qed_dev *cdev, char name[NAME_SIZE])
1291 memcpy(cdev->name, name, NAME_SIZE);
1292 for_each_hwfn(cdev, i)
1293 snprintf(cdev->hwfns[i].name, NAME_SIZE, "%s-%d", name, i);
1296 static u32 qed_sb_init(struct qed_dev *cdev,
1297 struct qed_sb_info *sb_info,
1299 dma_addr_t sb_phy_addr, u16 sb_id,
1300 enum qed_sb_type type)
1302 struct qed_hwfn *p_hwfn;
1303 struct qed_ptt *p_ptt;
1309 /* RoCE uses single engine and CMT uses two engines. When using both
1310 * we force only a single engine. Storage uses only engine 0 too.
1312 if (type == QED_SB_TYPE_L2_QUEUE)
1313 n_hwfns = cdev->num_hwfns;
1317 hwfn_index = sb_id % n_hwfns;
1318 p_hwfn = &cdev->hwfns[hwfn_index];
1319 rel_sb_id = sb_id / n_hwfns;
1321 DP_VERBOSE(cdev, NETIF_MSG_INTR,
1322 "hwfn [%d] <--[init]-- SB %04x [0x%04x upper]\n",
1323 hwfn_index, rel_sb_id, sb_id);
1325 if (IS_PF(p_hwfn->cdev)) {
1326 p_ptt = qed_ptt_acquire(p_hwfn);
1330 rc = qed_int_sb_init(p_hwfn, p_ptt, sb_info, sb_virt_addr,
1331 sb_phy_addr, rel_sb_id);
1332 qed_ptt_release(p_hwfn, p_ptt);
1334 rc = qed_int_sb_init(p_hwfn, NULL, sb_info, sb_virt_addr,
1335 sb_phy_addr, rel_sb_id);
1341 static u32 qed_sb_release(struct qed_dev *cdev,
1342 struct qed_sb_info *sb_info, u16 sb_id)
1344 struct qed_hwfn *p_hwfn;
1349 hwfn_index = sb_id % cdev->num_hwfns;
1350 p_hwfn = &cdev->hwfns[hwfn_index];
1351 rel_sb_id = sb_id / cdev->num_hwfns;
1353 DP_VERBOSE(cdev, NETIF_MSG_INTR,
1354 "hwfn [%d] <--[init]-- SB %04x [0x%04x upper]\n",
1355 hwfn_index, rel_sb_id, sb_id);
1357 rc = qed_int_sb_release(p_hwfn, sb_info, rel_sb_id);
1362 static bool qed_can_link_change(struct qed_dev *cdev)
1367 static int qed_set_link(struct qed_dev *cdev, struct qed_link_params *params)
1369 struct qed_hwfn *hwfn;
1370 struct qed_mcp_link_params *link_params;
1371 struct qed_ptt *ptt;
1378 /* The link should be set only once per PF */
1379 hwfn = &cdev->hwfns[0];
1381 /* When VF wants to set link, force it to read the bulletin instead.
1382 * This mimics the PF behavior, where a noitification [both immediate
1383 * and possible later] would be generated when changing properties.
1386 qed_schedule_iov(hwfn, QED_IOV_WQ_VF_FORCE_LINK_QUERY_FLAG);
1390 ptt = qed_ptt_acquire(hwfn);
1394 link_params = qed_mcp_get_link_params(hwfn);
1395 if (params->override_flags & QED_LINK_OVERRIDE_SPEED_AUTONEG)
1396 link_params->speed.autoneg = params->autoneg;
1397 if (params->override_flags & QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS) {
1398 link_params->speed.advertised_speeds = 0;
1399 sup_caps = QED_LM_1000baseT_Full_BIT |
1400 QED_LM_1000baseKX_Full_BIT |
1401 QED_LM_1000baseX_Full_BIT;
1402 if (params->adv_speeds & sup_caps)
1403 link_params->speed.advertised_speeds |=
1404 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G;
1405 sup_caps = QED_LM_10000baseT_Full_BIT |
1406 QED_LM_10000baseKR_Full_BIT |
1407 QED_LM_10000baseKX4_Full_BIT |
1408 QED_LM_10000baseR_FEC_BIT |
1409 QED_LM_10000baseCR_Full_BIT |
1410 QED_LM_10000baseSR_Full_BIT |
1411 QED_LM_10000baseLR_Full_BIT |
1412 QED_LM_10000baseLRM_Full_BIT;
1413 if (params->adv_speeds & sup_caps)
1414 link_params->speed.advertised_speeds |=
1415 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G;
1416 if (params->adv_speeds & QED_LM_20000baseKR2_Full_BIT)
1417 link_params->speed.advertised_speeds |=
1418 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G;
1419 sup_caps = QED_LM_25000baseKR_Full_BIT |
1420 QED_LM_25000baseCR_Full_BIT |
1421 QED_LM_25000baseSR_Full_BIT;
1422 if (params->adv_speeds & sup_caps)
1423 link_params->speed.advertised_speeds |=
1424 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G;
1425 sup_caps = QED_LM_40000baseLR4_Full_BIT |
1426 QED_LM_40000baseKR4_Full_BIT |
1427 QED_LM_40000baseCR4_Full_BIT |
1428 QED_LM_40000baseSR4_Full_BIT;
1429 if (params->adv_speeds & sup_caps)
1430 link_params->speed.advertised_speeds |=
1431 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G;
1432 sup_caps = QED_LM_50000baseKR2_Full_BIT |
1433 QED_LM_50000baseCR2_Full_BIT |
1434 QED_LM_50000baseSR2_Full_BIT;
1435 if (params->adv_speeds & sup_caps)
1436 link_params->speed.advertised_speeds |=
1437 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G;
1438 sup_caps = QED_LM_100000baseKR4_Full_BIT |
1439 QED_LM_100000baseSR4_Full_BIT |
1440 QED_LM_100000baseCR4_Full_BIT |
1441 QED_LM_100000baseLR4_ER4_Full_BIT;
1442 if (params->adv_speeds & sup_caps)
1443 link_params->speed.advertised_speeds |=
1444 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G;
1446 if (params->override_flags & QED_LINK_OVERRIDE_SPEED_FORCED_SPEED)
1447 link_params->speed.forced_speed = params->forced_speed;
1448 if (params->override_flags & QED_LINK_OVERRIDE_PAUSE_CONFIG) {
1449 if (params->pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE)
1450 link_params->pause.autoneg = true;
1452 link_params->pause.autoneg = false;
1453 if (params->pause_config & QED_LINK_PAUSE_RX_ENABLE)
1454 link_params->pause.forced_rx = true;
1456 link_params->pause.forced_rx = false;
1457 if (params->pause_config & QED_LINK_PAUSE_TX_ENABLE)
1458 link_params->pause.forced_tx = true;
1460 link_params->pause.forced_tx = false;
1462 if (params->override_flags & QED_LINK_OVERRIDE_LOOPBACK_MODE) {
1463 switch (params->loopback_mode) {
1464 case QED_LINK_LOOPBACK_INT_PHY:
1465 link_params->loopback_mode = ETH_LOOPBACK_INT_PHY;
1467 case QED_LINK_LOOPBACK_EXT_PHY:
1468 link_params->loopback_mode = ETH_LOOPBACK_EXT_PHY;
1470 case QED_LINK_LOOPBACK_EXT:
1471 link_params->loopback_mode = ETH_LOOPBACK_EXT;
1473 case QED_LINK_LOOPBACK_MAC:
1474 link_params->loopback_mode = ETH_LOOPBACK_MAC;
1477 link_params->loopback_mode = ETH_LOOPBACK_NONE;
1482 if (params->override_flags & QED_LINK_OVERRIDE_EEE_CONFIG)
1483 memcpy(&link_params->eee, ¶ms->eee,
1484 sizeof(link_params->eee));
1486 rc = qed_mcp_set_link(hwfn, ptt, params->link_up);
1488 qed_ptt_release(hwfn, ptt);
1493 static int qed_get_port_type(u32 media_type)
1497 switch (media_type) {
1498 case MEDIA_SFPP_10G_FIBER:
1499 case MEDIA_SFP_1G_FIBER:
1500 case MEDIA_XFP_FIBER:
1501 case MEDIA_MODULE_FIBER:
1503 port_type = PORT_FIBRE;
1505 case MEDIA_DA_TWINAX:
1506 port_type = PORT_DA;
1509 port_type = PORT_TP;
1511 case MEDIA_NOT_PRESENT:
1512 port_type = PORT_NONE;
1514 case MEDIA_UNSPECIFIED:
1516 port_type = PORT_OTHER;
1522 static int qed_get_link_data(struct qed_hwfn *hwfn,
1523 struct qed_mcp_link_params *params,
1524 struct qed_mcp_link_state *link,
1525 struct qed_mcp_link_capabilities *link_caps)
1529 if (!IS_PF(hwfn->cdev)) {
1530 qed_vf_get_link_params(hwfn, params);
1531 qed_vf_get_link_state(hwfn, link);
1532 qed_vf_get_link_caps(hwfn, link_caps);
1537 p = qed_mcp_get_link_params(hwfn);
1540 memcpy(params, p, sizeof(*params));
1542 p = qed_mcp_get_link_state(hwfn);
1545 memcpy(link, p, sizeof(*link));
1547 p = qed_mcp_get_link_capabilities(hwfn);
1550 memcpy(link_caps, p, sizeof(*link_caps));
1555 static void qed_fill_link_capability(struct qed_hwfn *hwfn,
1556 struct qed_ptt *ptt, u32 capability,
1559 u32 media_type, tcvr_state, tcvr_type;
1560 u32 speed_mask, board_cfg;
1562 if (qed_mcp_get_media_type(hwfn, ptt, &media_type))
1563 media_type = MEDIA_UNSPECIFIED;
1565 if (qed_mcp_get_transceiver_data(hwfn, ptt, &tcvr_state, &tcvr_type))
1566 tcvr_type = ETH_TRANSCEIVER_STATE_UNPLUGGED;
1568 if (qed_mcp_trans_speed_mask(hwfn, ptt, &speed_mask))
1569 speed_mask = 0xFFFFFFFF;
1571 if (qed_mcp_get_board_config(hwfn, ptt, &board_cfg))
1572 board_cfg = NVM_CFG1_PORT_PORT_TYPE_UNDEFINED;
1574 DP_VERBOSE(hwfn->cdev, NETIF_MSG_DRV,
1575 "Media_type = 0x%x tcvr_state = 0x%x tcvr_type = 0x%x speed_mask = 0x%x board_cfg = 0x%x\n",
1576 media_type, tcvr_state, tcvr_type, speed_mask, board_cfg);
1578 switch (media_type) {
1579 case MEDIA_DA_TWINAX:
1580 if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G)
1581 *if_capability |= QED_LM_20000baseKR2_Full_BIT;
1582 /* For DAC media multiple speed capabilities are supported*/
1583 capability = capability & speed_mask;
1584 if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
1585 *if_capability |= QED_LM_1000baseKX_Full_BIT;
1586 if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
1587 *if_capability |= QED_LM_10000baseCR_Full_BIT;
1588 if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
1589 *if_capability |= QED_LM_40000baseCR4_Full_BIT;
1590 if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
1591 *if_capability |= QED_LM_25000baseCR_Full_BIT;
1592 if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
1593 *if_capability |= QED_LM_50000baseCR2_Full_BIT;
1595 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
1596 *if_capability |= QED_LM_100000baseCR4_Full_BIT;
1599 if (board_cfg & NVM_CFG1_PORT_PORT_TYPE_EXT_PHY) {
1601 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G) {
1602 *if_capability |= QED_LM_1000baseT_Full_BIT;
1605 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G) {
1606 *if_capability |= QED_LM_10000baseT_Full_BIT;
1609 if (board_cfg & NVM_CFG1_PORT_PORT_TYPE_MODULE) {
1610 if (tcvr_type == ETH_TRANSCEIVER_TYPE_1000BASET)
1611 *if_capability |= QED_LM_1000baseT_Full_BIT;
1612 if (tcvr_type == ETH_TRANSCEIVER_TYPE_10G_BASET)
1613 *if_capability |= QED_LM_10000baseT_Full_BIT;
1616 case MEDIA_SFP_1G_FIBER:
1617 case MEDIA_SFPP_10G_FIBER:
1618 case MEDIA_XFP_FIBER:
1619 case MEDIA_MODULE_FIBER:
1621 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G) {
1622 if ((tcvr_type == ETH_TRANSCEIVER_TYPE_1G_LX) ||
1623 (tcvr_type == ETH_TRANSCEIVER_TYPE_1G_SX))
1624 *if_capability |= QED_LM_1000baseKX_Full_BIT;
1627 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G) {
1628 if (tcvr_type == ETH_TRANSCEIVER_TYPE_10G_SR)
1629 *if_capability |= QED_LM_10000baseSR_Full_BIT;
1630 if (tcvr_type == ETH_TRANSCEIVER_TYPE_10G_LR)
1631 *if_capability |= QED_LM_10000baseLR_Full_BIT;
1632 if (tcvr_type == ETH_TRANSCEIVER_TYPE_10G_LRM)
1633 *if_capability |= QED_LM_10000baseLRM_Full_BIT;
1634 if (tcvr_type == ETH_TRANSCEIVER_TYPE_10G_ER)
1635 *if_capability |= QED_LM_10000baseR_FEC_BIT;
1637 if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G)
1638 *if_capability |= QED_LM_20000baseKR2_Full_BIT;
1640 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G) {
1641 if (tcvr_type == ETH_TRANSCEIVER_TYPE_25G_SR)
1642 *if_capability |= QED_LM_25000baseSR_Full_BIT;
1645 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G) {
1646 if (tcvr_type == ETH_TRANSCEIVER_TYPE_40G_LR4)
1647 *if_capability |= QED_LM_40000baseLR4_Full_BIT;
1648 if (tcvr_type == ETH_TRANSCEIVER_TYPE_40G_SR4)
1649 *if_capability |= QED_LM_40000baseSR4_Full_BIT;
1652 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
1653 *if_capability |= QED_LM_50000baseKR2_Full_BIT;
1655 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G) {
1656 if (tcvr_type == ETH_TRANSCEIVER_TYPE_100G_SR4)
1657 *if_capability |= QED_LM_100000baseSR4_Full_BIT;
1662 if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G)
1663 *if_capability |= QED_LM_20000baseKR2_Full_BIT;
1665 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
1666 *if_capability |= QED_LM_1000baseKX_Full_BIT;
1668 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
1669 *if_capability |= QED_LM_10000baseKR_Full_BIT;
1671 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
1672 *if_capability |= QED_LM_25000baseKR_Full_BIT;
1674 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
1675 *if_capability |= QED_LM_40000baseKR4_Full_BIT;
1677 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
1678 *if_capability |= QED_LM_50000baseKR2_Full_BIT;
1680 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
1681 *if_capability |= QED_LM_100000baseKR4_Full_BIT;
1683 case MEDIA_UNSPECIFIED:
1684 case MEDIA_NOT_PRESENT:
1685 DP_VERBOSE(hwfn->cdev, QED_MSG_DEBUG,
1686 "Unknown media and transceiver type;\n");
1691 static void qed_fill_link(struct qed_hwfn *hwfn,
1692 struct qed_ptt *ptt,
1693 struct qed_link_output *if_link)
1695 struct qed_mcp_link_capabilities link_caps;
1696 struct qed_mcp_link_params params;
1697 struct qed_mcp_link_state link;
1700 memset(if_link, 0, sizeof(*if_link));
1702 /* Prepare source inputs */
1703 if (qed_get_link_data(hwfn, ¶ms, &link, &link_caps)) {
1704 dev_warn(&hwfn->cdev->pdev->dev, "no link data available\n");
1708 /* Set the link parameters to pass to protocol driver */
1710 if_link->link_up = true;
1712 /* TODO - at the moment assume supported and advertised speed equal */
1713 if_link->supported_caps = QED_LM_FIBRE_BIT;
1714 if (link_caps.default_speed_autoneg)
1715 if_link->supported_caps |= QED_LM_Autoneg_BIT;
1716 if (params.pause.autoneg ||
1717 (params.pause.forced_rx && params.pause.forced_tx))
1718 if_link->supported_caps |= QED_LM_Asym_Pause_BIT;
1719 if (params.pause.autoneg || params.pause.forced_rx ||
1720 params.pause.forced_tx)
1721 if_link->supported_caps |= QED_LM_Pause_BIT;
1723 if_link->advertised_caps = if_link->supported_caps;
1724 if (params.speed.autoneg)
1725 if_link->advertised_caps |= QED_LM_Autoneg_BIT;
1727 if_link->advertised_caps &= ~QED_LM_Autoneg_BIT;
1729 /* Fill link advertised capability*/
1730 qed_fill_link_capability(hwfn, ptt, params.speed.advertised_speeds,
1731 &if_link->advertised_caps);
1732 /* Fill link supported capability*/
1733 qed_fill_link_capability(hwfn, ptt, link_caps.speed_capabilities,
1734 &if_link->supported_caps);
1737 if_link->speed = link.speed;
1739 /* TODO - fill duplex properly */
1740 if_link->duplex = DUPLEX_FULL;
1741 qed_mcp_get_media_type(hwfn, ptt, &media_type);
1742 if_link->port = qed_get_port_type(media_type);
1744 if_link->autoneg = params.speed.autoneg;
1746 if (params.pause.autoneg)
1747 if_link->pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE;
1748 if (params.pause.forced_rx)
1749 if_link->pause_config |= QED_LINK_PAUSE_RX_ENABLE;
1750 if (params.pause.forced_tx)
1751 if_link->pause_config |= QED_LINK_PAUSE_TX_ENABLE;
1753 /* Link partner capabilities */
1754 if (link.partner_adv_speed &
1755 QED_LINK_PARTNER_SPEED_1G_FD)
1756 if_link->lp_caps |= QED_LM_1000baseT_Full_BIT;
1757 if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_10G)
1758 if_link->lp_caps |= QED_LM_10000baseKR_Full_BIT;
1759 if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_20G)
1760 if_link->lp_caps |= QED_LM_20000baseKR2_Full_BIT;
1761 if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_25G)
1762 if_link->lp_caps |= QED_LM_25000baseKR_Full_BIT;
1763 if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_40G)
1764 if_link->lp_caps |= QED_LM_40000baseLR4_Full_BIT;
1765 if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_50G)
1766 if_link->lp_caps |= QED_LM_50000baseKR2_Full_BIT;
1767 if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_100G)
1768 if_link->lp_caps |= QED_LM_100000baseKR4_Full_BIT;
1770 if (link.an_complete)
1771 if_link->lp_caps |= QED_LM_Autoneg_BIT;
1773 if (link.partner_adv_pause)
1774 if_link->lp_caps |= QED_LM_Pause_BIT;
1775 if (link.partner_adv_pause == QED_LINK_PARTNER_ASYMMETRIC_PAUSE ||
1776 link.partner_adv_pause == QED_LINK_PARTNER_BOTH_PAUSE)
1777 if_link->lp_caps |= QED_LM_Asym_Pause_BIT;
1779 if (link_caps.default_eee == QED_MCP_EEE_UNSUPPORTED) {
1780 if_link->eee_supported = false;
1782 if_link->eee_supported = true;
1783 if_link->eee_active = link.eee_active;
1784 if_link->sup_caps = link_caps.eee_speed_caps;
1785 /* MFW clears adv_caps on eee disable; use configured value */
1786 if_link->eee.adv_caps = link.eee_adv_caps ? link.eee_adv_caps :
1787 params.eee.adv_caps;
1788 if_link->eee.lp_adv_caps = link.eee_lp_adv_caps;
1789 if_link->eee.enable = params.eee.enable;
1790 if_link->eee.tx_lpi_enable = params.eee.tx_lpi_enable;
1791 if_link->eee.tx_lpi_timer = params.eee.tx_lpi_timer;
1795 static void qed_get_current_link(struct qed_dev *cdev,
1796 struct qed_link_output *if_link)
1798 struct qed_hwfn *hwfn;
1799 struct qed_ptt *ptt;
1802 hwfn = &cdev->hwfns[0];
1804 ptt = qed_ptt_acquire(hwfn);
1806 qed_fill_link(hwfn, ptt, if_link);
1807 qed_ptt_release(hwfn, ptt);
1809 DP_NOTICE(hwfn, "Failed to fill link; No PTT\n");
1812 qed_fill_link(hwfn, NULL, if_link);
1815 for_each_hwfn(cdev, i)
1816 qed_inform_vf_link_state(&cdev->hwfns[i]);
1819 void qed_link_update(struct qed_hwfn *hwfn, struct qed_ptt *ptt)
1821 void *cookie = hwfn->cdev->ops_cookie;
1822 struct qed_common_cb_ops *op = hwfn->cdev->protocol_ops.common;
1823 struct qed_link_output if_link;
1825 qed_fill_link(hwfn, ptt, &if_link);
1826 qed_inform_vf_link_state(hwfn);
1828 if (IS_LEAD_HWFN(hwfn) && cookie)
1829 op->link_update(cookie, &if_link);
1832 static int qed_drain(struct qed_dev *cdev)
1834 struct qed_hwfn *hwfn;
1835 struct qed_ptt *ptt;
1841 for_each_hwfn(cdev, i) {
1842 hwfn = &cdev->hwfns[i];
1843 ptt = qed_ptt_acquire(hwfn);
1845 DP_NOTICE(hwfn, "Failed to drain NIG; No PTT\n");
1848 rc = qed_mcp_drain(hwfn, ptt);
1849 qed_ptt_release(hwfn, ptt);
1857 static u32 qed_nvm_flash_image_access_crc(struct qed_dev *cdev,
1858 struct qed_nvm_image_att *nvm_image,
1865 /* Allocate a buffer for holding the nvram image */
1866 buf = kzalloc(nvm_image->length, GFP_KERNEL);
1870 /* Read image into buffer */
1871 rc = qed_mcp_nvm_read(cdev, nvm_image->start_addr,
1872 buf, nvm_image->length);
1874 DP_ERR(cdev, "Failed reading image from nvm\n");
1878 /* Convert the buffer into big-endian format (excluding the
1879 * closing 4 bytes of CRC).
1881 for (j = 0; j < nvm_image->length - 4; j += 4) {
1882 val = cpu_to_be32(*(u32 *)&buf[j]);
1883 *(u32 *)&buf[j] = val;
1886 /* Calc CRC for the "actual" image buffer, i.e. not including
1887 * the last 4 CRC bytes.
1889 *crc = (~cpu_to_be32(crc32(0xffffffff, buf, nvm_image->length - 4)));
1897 /* Binary file format -
1898 * /----------------------------------------------------------------------\
1899 * 0B | 0x4 [command index] |
1900 * 4B | image_type | Options | Number of register settings |
1904 * \----------------------------------------------------------------------/
1905 * There can be several Value-Mask-Offset sets as specified by 'Number of...'.
1906 * Options - 0'b - Calculate & Update CRC for image
1908 static int qed_nvm_flash_image_access(struct qed_dev *cdev, const u8 **data,
1911 struct qed_nvm_image_att nvm_image;
1912 struct qed_hwfn *p_hwfn;
1913 bool is_crc = false;
1919 image_type = **data;
1920 p_hwfn = QED_LEADING_HWFN(cdev);
1921 for (i = 0; i < p_hwfn->nvm_info.num_images; i++)
1922 if (image_type == p_hwfn->nvm_info.image_att[i].image_type)
1924 if (i == p_hwfn->nvm_info.num_images) {
1925 DP_ERR(cdev, "Failed to find nvram image of type %08x\n",
1930 nvm_image.start_addr = p_hwfn->nvm_info.image_att[i].nvm_start_addr;
1931 nvm_image.length = p_hwfn->nvm_info.image_att[i].len;
1933 DP_VERBOSE(cdev, NETIF_MSG_DRV,
1934 "Read image %02x; type = %08x; NVM [%08x,...,%08x]\n",
1935 **data, image_type, nvm_image.start_addr,
1936 nvm_image.start_addr + nvm_image.length - 1);
1938 is_crc = !!(**data & BIT(0));
1940 len = *((u16 *)*data);
1945 rc = qed_nvm_flash_image_access_crc(cdev, &nvm_image, &crc);
1947 DP_ERR(cdev, "Failed calculating CRC, rc = %d\n", rc);
1951 rc = qed_mcp_nvm_write(cdev, QED_NVM_WRITE_NVRAM,
1952 (nvm_image.start_addr +
1953 nvm_image.length - 4), (u8 *)&crc, 4);
1955 DP_ERR(cdev, "Failed writing to %08x, rc = %d\n",
1956 nvm_image.start_addr + nvm_image.length - 4, rc);
1960 /* Iterate over the values for setting */
1962 u32 offset, mask, value, cur_value;
1965 value = *((u32 *)*data);
1967 mask = *((u32 *)*data);
1969 offset = *((u32 *)*data);
1972 rc = qed_mcp_nvm_read(cdev, nvm_image.start_addr + offset, buf,
1975 DP_ERR(cdev, "Failed reading from %08x\n",
1976 nvm_image.start_addr + offset);
1980 cur_value = le32_to_cpu(*((__le32 *)buf));
1981 DP_VERBOSE(cdev, NETIF_MSG_DRV,
1982 "NVM %08x: %08x -> %08x [Value %08x Mask %08x]\n",
1983 nvm_image.start_addr + offset, cur_value,
1984 (cur_value & ~mask) | (value & mask), value, mask);
1985 value = (value & mask) | (cur_value & ~mask);
1986 rc = qed_mcp_nvm_write(cdev, QED_NVM_WRITE_NVRAM,
1987 nvm_image.start_addr + offset,
1990 DP_ERR(cdev, "Failed writing to %08x\n",
1991 nvm_image.start_addr + offset);
2001 /* Binary file format -
2002 * /----------------------------------------------------------------------\
2003 * 0B | 0x3 [command index] |
2004 * 4B | b'0: check_response? | b'1-31 reserved |
2005 * 8B | File-type | reserved |
2006 * 12B | Image length in bytes |
2007 * \----------------------------------------------------------------------/
2008 * Start a new file of the provided type
2010 static int qed_nvm_flash_image_file_start(struct qed_dev *cdev,
2011 const u8 **data, bool *check_resp)
2013 u32 file_type, file_size = 0;
2017 *check_resp = !!(**data & BIT(0));
2021 DP_VERBOSE(cdev, NETIF_MSG_DRV,
2022 "About to start a new file of type %02x\n", file_type);
2023 if (file_type == DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_MBI) {
2025 file_size = *((u32 *)(*data));
2028 rc = qed_mcp_nvm_write(cdev, QED_PUT_FILE_BEGIN, file_type,
2029 (u8 *)(&file_size), 4);
2035 /* Binary file format -
2036 * /----------------------------------------------------------------------\
2037 * 0B | 0x2 [command index] |
2038 * 4B | Length in bytes |
2039 * 8B | b'0: check_response? | b'1-31 reserved |
2040 * 12B | Offset in bytes |
2042 * \----------------------------------------------------------------------/
2043 * Write data as part of a file that was previously started. Data should be
2044 * of length equal to that provided in the message
2046 static int qed_nvm_flash_image_file_data(struct qed_dev *cdev,
2047 const u8 **data, bool *check_resp)
2053 len = *((u32 *)(*data));
2055 *check_resp = !!(**data & BIT(0));
2057 offset = *((u32 *)(*data));
2060 DP_VERBOSE(cdev, NETIF_MSG_DRV,
2061 "About to write File-data: %08x bytes to offset %08x\n",
2064 rc = qed_mcp_nvm_write(cdev, QED_PUT_FILE_DATA, offset,
2065 (char *)(*data), len);
2071 /* Binary file format [General header] -
2072 * /----------------------------------------------------------------------\
2073 * 0B | QED_NVM_SIGNATURE |
2074 * 4B | Length in bytes |
2075 * 8B | Highest command in this batchfile | Reserved |
2076 * \----------------------------------------------------------------------/
2078 static int qed_nvm_flash_image_validate(struct qed_dev *cdev,
2079 const struct firmware *image,
2084 /* Check minimum size */
2085 if (image->size < 12) {
2086 DP_ERR(cdev, "Image is too short [%08x]\n", (u32)image->size);
2090 /* Check signature */
2091 signature = *((u32 *)(*data));
2092 if (signature != QED_NVM_SIGNATURE) {
2093 DP_ERR(cdev, "Wrong signature '%08x'\n", signature);
2098 /* Validate internal size equals the image-size */
2099 len = *((u32 *)(*data));
2100 if (len != image->size) {
2101 DP_ERR(cdev, "Size mismatch: internal = %08x image = %08x\n",
2102 len, (u32)image->size);
2107 /* Make sure driver familiar with all commands necessary for this */
2108 if (*((u16 *)(*data)) >= QED_NVM_FLASH_CMD_NVM_MAX) {
2109 DP_ERR(cdev, "File contains unsupported commands [Need %04x]\n",
2119 static int qed_nvm_flash(struct qed_dev *cdev, const char *name)
2121 const struct firmware *image;
2122 const u8 *data, *data_end;
2126 rc = request_firmware(&image, name, &cdev->pdev->dev);
2128 DP_ERR(cdev, "Failed to find '%s'\n", name);
2132 DP_VERBOSE(cdev, NETIF_MSG_DRV,
2133 "Flashing '%s' - firmware's data at %p, size is %08x\n",
2134 name, image->data, (u32)image->size);
2136 data_end = data + image->size;
2138 rc = qed_nvm_flash_image_validate(cdev, image, &data);
2142 while (data < data_end) {
2143 bool check_resp = false;
2145 /* Parse the actual command */
2146 cmd_type = *((u32 *)data);
2148 case QED_NVM_FLASH_CMD_FILE_DATA:
2149 rc = qed_nvm_flash_image_file_data(cdev, &data,
2152 case QED_NVM_FLASH_CMD_FILE_START:
2153 rc = qed_nvm_flash_image_file_start(cdev, &data,
2156 case QED_NVM_FLASH_CMD_NVM_CHANGE:
2157 rc = qed_nvm_flash_image_access(cdev, &data,
2161 DP_ERR(cdev, "Unknown command %08x\n", cmd_type);
2167 DP_ERR(cdev, "Command %08x failed\n", cmd_type);
2171 /* Check response if needed */
2173 u32 mcp_response = 0;
2175 if (qed_mcp_nvm_resp(cdev, (u8 *)&mcp_response)) {
2176 DP_ERR(cdev, "Failed getting MCP response\n");
2181 switch (mcp_response & FW_MSG_CODE_MASK) {
2182 case FW_MSG_CODE_OK:
2183 case FW_MSG_CODE_NVM_OK:
2184 case FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK:
2185 case FW_MSG_CODE_PHY_OK:
2188 DP_ERR(cdev, "MFW returns error: %08x\n",
2197 release_firmware(image);
2202 static int qed_nvm_get_image(struct qed_dev *cdev, enum qed_nvm_images type,
2205 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
2207 return qed_mcp_get_nvm_image(hwfn, type, buf, len);
2210 void qed_schedule_recovery_handler(struct qed_hwfn *p_hwfn)
2212 struct qed_common_cb_ops *ops = p_hwfn->cdev->protocol_ops.common;
2213 void *cookie = p_hwfn->cdev->ops_cookie;
2215 if (ops && ops->schedule_recovery_handler)
2216 ops->schedule_recovery_handler(cookie);
2219 static int qed_set_coalesce(struct qed_dev *cdev, u16 rx_coal, u16 tx_coal,
2222 return qed_set_queue_coalesce(rx_coal, tx_coal, handle);
2225 static int qed_set_led(struct qed_dev *cdev, enum qed_led_mode mode)
2227 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
2228 struct qed_ptt *ptt;
2231 ptt = qed_ptt_acquire(hwfn);
2235 status = qed_mcp_set_led(hwfn, ptt, mode);
2237 qed_ptt_release(hwfn, ptt);
2242 static int qed_recovery_process(struct qed_dev *cdev)
2244 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
2245 struct qed_ptt *p_ptt;
2248 p_ptt = qed_ptt_acquire(p_hwfn);
2252 rc = qed_start_recovery_process(p_hwfn, p_ptt);
2254 qed_ptt_release(p_hwfn, p_ptt);
2259 static int qed_update_wol(struct qed_dev *cdev, bool enabled)
2261 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
2262 struct qed_ptt *ptt;
2268 ptt = qed_ptt_acquire(hwfn);
2272 rc = qed_mcp_ov_update_wol(hwfn, ptt, enabled ? QED_OV_WOL_ENABLED
2273 : QED_OV_WOL_DISABLED);
2276 rc = qed_mcp_ov_update_current_config(hwfn, ptt, QED_OV_CLIENT_DRV);
2279 qed_ptt_release(hwfn, ptt);
2283 static int qed_update_drv_state(struct qed_dev *cdev, bool active)
2285 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
2286 struct qed_ptt *ptt;
2292 ptt = qed_ptt_acquire(hwfn);
2296 status = qed_mcp_ov_update_driver_state(hwfn, ptt, active ?
2297 QED_OV_DRIVER_STATE_ACTIVE :
2298 QED_OV_DRIVER_STATE_DISABLED);
2300 qed_ptt_release(hwfn, ptt);
2305 static int qed_update_mac(struct qed_dev *cdev, u8 *mac)
2307 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
2308 struct qed_ptt *ptt;
2314 ptt = qed_ptt_acquire(hwfn);
2318 status = qed_mcp_ov_update_mac(hwfn, ptt, mac);
2322 status = qed_mcp_ov_update_current_config(hwfn, ptt, QED_OV_CLIENT_DRV);
2325 qed_ptt_release(hwfn, ptt);
2329 static int qed_update_mtu(struct qed_dev *cdev, u16 mtu)
2331 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
2332 struct qed_ptt *ptt;
2338 ptt = qed_ptt_acquire(hwfn);
2342 status = qed_mcp_ov_update_mtu(hwfn, ptt, mtu);
2346 status = qed_mcp_ov_update_current_config(hwfn, ptt, QED_OV_CLIENT_DRV);
2349 qed_ptt_release(hwfn, ptt);
2353 static int qed_read_module_eeprom(struct qed_dev *cdev, char *buf,
2354 u8 dev_addr, u32 offset, u32 len)
2356 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
2357 struct qed_ptt *ptt;
2363 ptt = qed_ptt_acquire(hwfn);
2367 rc = qed_mcp_phy_sfp_read(hwfn, ptt, MFW_PORT(hwfn), dev_addr,
2370 qed_ptt_release(hwfn, ptt);
2375 static struct qed_selftest_ops qed_selftest_ops_pass = {
2376 .selftest_memory = &qed_selftest_memory,
2377 .selftest_interrupt = &qed_selftest_interrupt,
2378 .selftest_register = &qed_selftest_register,
2379 .selftest_clock = &qed_selftest_clock,
2380 .selftest_nvram = &qed_selftest_nvram,
2383 const struct qed_common_ops qed_common_ops_pass = {
2384 .selftest = &qed_selftest_ops_pass,
2385 .probe = &qed_probe,
2386 .remove = &qed_remove,
2387 .set_power_state = &qed_set_power_state,
2388 .set_name = &qed_set_name,
2389 .update_pf_params = &qed_update_pf_params,
2390 .slowpath_start = &qed_slowpath_start,
2391 .slowpath_stop = &qed_slowpath_stop,
2392 .set_fp_int = &qed_set_int_fp,
2393 .get_fp_int = &qed_get_int_fp,
2394 .sb_init = &qed_sb_init,
2395 .sb_release = &qed_sb_release,
2396 .simd_handler_config = &qed_simd_handler_config,
2397 .simd_handler_clean = &qed_simd_handler_clean,
2398 .dbg_grc = &qed_dbg_grc,
2399 .dbg_grc_size = &qed_dbg_grc_size,
2400 .can_link_change = &qed_can_link_change,
2401 .set_link = &qed_set_link,
2402 .get_link = &qed_get_current_link,
2403 .drain = &qed_drain,
2404 .update_msglvl = &qed_init_dp,
2405 .dbg_all_data = &qed_dbg_all_data,
2406 .dbg_all_data_size = &qed_dbg_all_data_size,
2407 .chain_alloc = &qed_chain_alloc,
2408 .chain_free = &qed_chain_free,
2409 .nvm_flash = &qed_nvm_flash,
2410 .nvm_get_image = &qed_nvm_get_image,
2411 .set_coalesce = &qed_set_coalesce,
2412 .set_led = &qed_set_led,
2413 .recovery_process = &qed_recovery_process,
2414 .recovery_prolog = &qed_recovery_prolog,
2415 .update_drv_state = &qed_update_drv_state,
2416 .update_mac = &qed_update_mac,
2417 .update_mtu = &qed_update_mtu,
2418 .update_wol = &qed_update_wol,
2419 .db_recovery_add = &qed_db_recovery_add,
2420 .db_recovery_del = &qed_db_recovery_del,
2421 .read_module_eeprom = &qed_read_module_eeprom,
2424 void qed_get_protocol_stats(struct qed_dev *cdev,
2425 enum qed_mcp_protocol_type type,
2426 union qed_mcp_protocol_stats *stats)
2428 struct qed_eth_stats eth_stats;
2430 memset(stats, 0, sizeof(*stats));
2433 case QED_MCP_LAN_STATS:
2434 qed_get_vport_stats(cdev, ð_stats);
2435 stats->lan_stats.ucast_rx_pkts =
2436 eth_stats.common.rx_ucast_pkts;
2437 stats->lan_stats.ucast_tx_pkts =
2438 eth_stats.common.tx_ucast_pkts;
2439 stats->lan_stats.fcs_err = -1;
2441 case QED_MCP_FCOE_STATS:
2442 qed_get_protocol_stats_fcoe(cdev, &stats->fcoe_stats);
2444 case QED_MCP_ISCSI_STATS:
2445 qed_get_protocol_stats_iscsi(cdev, &stats->iscsi_stats);
2448 DP_VERBOSE(cdev, QED_MSG_SP,
2449 "Invalid protocol type = %d\n", type);
2454 int qed_mfw_tlv_req(struct qed_hwfn *hwfn)
2456 DP_VERBOSE(hwfn->cdev, NETIF_MSG_DRV,
2457 "Scheduling slowpath task [Flag: %d]\n",
2458 QED_SLOWPATH_MFW_TLV_REQ);
2459 smp_mb__before_atomic();
2460 set_bit(QED_SLOWPATH_MFW_TLV_REQ, &hwfn->slowpath_task_flags);
2461 smp_mb__after_atomic();
2462 queue_delayed_work(hwfn->slowpath_wq, &hwfn->slowpath_task, 0);
2468 qed_fill_generic_tlv_data(struct qed_dev *cdev, struct qed_mfw_tlv_generic *tlv)
2470 struct qed_common_cb_ops *op = cdev->protocol_ops.common;
2471 struct qed_eth_stats_common *p_common;
2472 struct qed_generic_tlvs gen_tlvs;
2473 struct qed_eth_stats stats;
2476 memset(&gen_tlvs, 0, sizeof(gen_tlvs));
2477 op->get_generic_tlv_data(cdev->ops_cookie, &gen_tlvs);
2479 if (gen_tlvs.feat_flags & QED_TLV_IP_CSUM)
2480 tlv->flags.ipv4_csum_offload = true;
2481 if (gen_tlvs.feat_flags & QED_TLV_LSO)
2482 tlv->flags.lso_supported = true;
2483 tlv->flags.b_set = true;
2485 for (i = 0; i < QED_TLV_MAC_COUNT; i++) {
2486 if (is_valid_ether_addr(gen_tlvs.mac[i])) {
2487 ether_addr_copy(tlv->mac[i], gen_tlvs.mac[i]);
2488 tlv->mac_set[i] = true;
2492 qed_get_vport_stats(cdev, &stats);
2493 p_common = &stats.common;
2494 tlv->rx_frames = p_common->rx_ucast_pkts + p_common->rx_mcast_pkts +
2495 p_common->rx_bcast_pkts;
2496 tlv->rx_frames_set = true;
2497 tlv->rx_bytes = p_common->rx_ucast_bytes + p_common->rx_mcast_bytes +
2498 p_common->rx_bcast_bytes;
2499 tlv->rx_bytes_set = true;
2500 tlv->tx_frames = p_common->tx_ucast_pkts + p_common->tx_mcast_pkts +
2501 p_common->tx_bcast_pkts;
2502 tlv->tx_frames_set = true;
2503 tlv->tx_bytes = p_common->tx_ucast_bytes + p_common->tx_mcast_bytes +
2504 p_common->tx_bcast_bytes;
2505 tlv->rx_bytes_set = true;
2508 int qed_mfw_fill_tlv_data(struct qed_hwfn *hwfn, enum qed_mfw_tlv_type type,
2509 union qed_mfw_tlv_data *tlv_buf)
2511 struct qed_dev *cdev = hwfn->cdev;
2512 struct qed_common_cb_ops *ops;
2514 ops = cdev->protocol_ops.common;
2515 if (!ops || !ops->get_protocol_tlv_data || !ops->get_generic_tlv_data) {
2516 DP_NOTICE(hwfn, "Can't collect TLV management info\n");
2521 case QED_MFW_TLV_GENERIC:
2522 qed_fill_generic_tlv_data(hwfn->cdev, &tlv_buf->generic);
2524 case QED_MFW_TLV_ETH:
2525 ops->get_protocol_tlv_data(cdev->ops_cookie, &tlv_buf->eth);
2527 case QED_MFW_TLV_FCOE:
2528 ops->get_protocol_tlv_data(cdev->ops_cookie, &tlv_buf->fcoe);
2530 case QED_MFW_TLV_ISCSI:
2531 ops->get_protocol_tlv_data(cdev->ops_cookie, &tlv_buf->iscsi);