drivers/net/ethernet/qlogic/qed/qed_main.c

   1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
   2 /* QLogic qed NIC Driver
   3  * Copyright (c) 2015-2017  QLogic Corporation
   4  * Copyright (c) 2019-2020 Marvell International Ltd.
   5  */
   6
   7 #include <linux/stddef.h>
   8 #include <linux/pci.h>
   9 #include <linux/kernel.h>
  10 #include <linux/slab.h>
  11 #include <linux/delay.h>
  12 #include <asm/byteorder.h>
  13 #include <linux/dma-mapping.h>
  14 #include <linux/string.h>
  15 #include <linux/module.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/workqueue.h>
  18 #include <linux/ethtool.h>
  19 #include <linux/etherdevice.h>
  20 #include <linux/vmalloc.h>
  21 #include <linux/crash_dump.h>
  22 #include <linux/crc32.h>
  23 #include <linux/qed/qed_if.h>
  24 #include <linux/qed/qed_ll2_if.h>
  25 #include <net/devlink.h>
  26 #include <linux/aer.h>
  27 #include <linux/phylink.h>
  28
  29 #include "qed.h"
  30 #include "qed_sriov.h"
  31 #include "qed_sp.h"
  32 #include "qed_dev_api.h"
  33 #include "qed_ll2.h"
  34 #include "qed_fcoe.h"
  35 #include "qed_iscsi.h"
  36
  37 #include "qed_mcp.h"
  38 #include "qed_reg_addr.h"
  39 #include "qed_hw.h"
  40 #include "qed_selftest.h"
  41 #include "qed_debug.h"
  42
  43 #define QED_ROCE_QPS                    (8192)
  44 #define QED_ROCE_DPIS                   (8)
  45 #define QED_RDMA_SRQS                   QED_ROCE_QPS
  46 #define QED_NVM_CFG_GET_FLAGS           0xA
  47 #define QED_NVM_CFG_GET_PF_FLAGS        0x1A
  48 #define QED_NVM_CFG_MAX_ATTRS           50
  49
  50 static char version[] =
  51         "QLogic FastLinQ 4xxxx Core Module qed " DRV_MODULE_VERSION "\n";
  52
  53 MODULE_DESCRIPTION("QLogic FastLinQ 4xxxx Core Module");
  54 MODULE_LICENSE("GPL");
  55 MODULE_VERSION(DRV_MODULE_VERSION);
  56
  57 #define FW_FILE_VERSION                         \
  58         __stringify(FW_MAJOR_VERSION) "."       \
  59         __stringify(FW_MINOR_VERSION) "."       \
  60         __stringify(FW_REVISION_VERSION) "."    \
  61         __stringify(FW_ENGINEERING_VERSION)
  62
  63 #define QED_FW_FILE_NAME        \
  64         "qed/qed_init_values_zipped-" FW_FILE_VERSION ".bin"
  65
  66 MODULE_FIRMWARE(QED_FW_FILE_NAME);
  67
  68 static int __init qed_init(void)
  69 {
  70         pr_info("%s", version);
  71
  72         return 0;
  73 }
  74
  75 static void __exit qed_cleanup(void)
  76 {
  77         pr_notice("qed_cleanup called\n");
  78 }
  79
  80 module_init(qed_init);
  81 module_exit(qed_cleanup);
  82
  83 /* Check if the DMA controller on the machine can properly handle the DMA
  84  * addressing required by the device.
  85 */
  86 static int qed_set_coherency_mask(struct qed_dev *cdev)
  87 {
  88         struct device *dev = &cdev->pdev->dev;
  89
  90         if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) {
  91                 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) {
  92                         DP_NOTICE(cdev,
  93                                   "Can't request 64-bit consistent allocations\n");
  94                         return -EIO;
  95                 }
  96         } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) {
  97                 DP_NOTICE(cdev, "Can't request 64b/32b DMA addresses\n");
  98                 return -EIO;
  99         }
 100
 101         return 0;
 102 }
 103
 104 static void qed_free_pci(struct qed_dev *cdev)
 105 {
 106         struct pci_dev *pdev = cdev->pdev;
 107
 108         pci_disable_pcie_error_reporting(pdev);
 109
 110         if (cdev->doorbells && cdev->db_size)
 111                 iounmap(cdev->doorbells);
 112         if (cdev->regview)
 113                 iounmap(cdev->regview);
 114         if (atomic_read(&pdev->enable_cnt) == 1)
 115                 pci_release_regions(pdev);
 116
 117         pci_disable_device(pdev);
 118 }
 119
 120 #define PCI_REVISION_ID_ERROR_VAL       0xff
 121
 122 /* Performs PCI initializations as well as initializing PCI-related parameters
 123  * in the device structrue. Returns 0 in case of success.
 124  */
 125 static int qed_init_pci(struct qed_dev *cdev, struct pci_dev *pdev)
 126 {
 127         u8 rev_id;
 128         int rc;
 129
 130         cdev->pdev = pdev;
 131
 132         rc = pci_enable_device(pdev);
 133         if (rc) {
 134                 DP_NOTICE(cdev, "Cannot enable PCI device\n");
 135                 goto err0;
 136         }
 137
 138         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
 139                 DP_NOTICE(cdev, "No memory region found in bar #0\n");
 140                 rc = -EIO;
 141                 goto err1;
 142         }
 143
 144         if (IS_PF(cdev) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
 145                 DP_NOTICE(cdev, "No memory region found in bar #2\n");
 146                 rc = -EIO;
 147                 goto err1;
 148         }
 149
 150         if (atomic_read(&pdev->enable_cnt) == 1) {
 151                 rc = pci_request_regions(pdev, "qed");
 152                 if (rc) {
 153                         DP_NOTICE(cdev,
 154                                   "Failed to request PCI memory resources\n");
 155                         goto err1;
 156                 }
 157                 pci_set_master(pdev);
 158                 pci_save_state(pdev);
 159         }
 160
 161         pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
 162         if (rev_id == PCI_REVISION_ID_ERROR_VAL) {
 163                 DP_NOTICE(cdev,
 164                           "Detected PCI device error [rev_id 0x%x]. Probably due to prior indication. Aborting.\n",
 165                           rev_id);
 166                 rc = -ENODEV;
 167                 goto err2;
 168         }
 169         if (!pci_is_pcie(pdev)) {
 170                 DP_NOTICE(cdev, "The bus is not PCI Express\n");
 171                 rc = -EIO;
 172                 goto err2;
 173         }
 174
 175         cdev->pci_params.pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
 176         if (IS_PF(cdev) && !cdev->pci_params.pm_cap)
 177                 DP_NOTICE(cdev, "Cannot find power management capability\n");
 178
 179         rc = qed_set_coherency_mask(cdev);
 180         if (rc)
 181                 goto err2;
 182
 183         cdev->pci_params.mem_start = pci_resource_start(pdev, 0);
 184         cdev->pci_params.mem_end = pci_resource_end(pdev, 0);
 185         cdev->pci_params.irq = pdev->irq;
 186
 187         cdev->regview = pci_ioremap_bar(pdev, 0);
 188         if (!cdev->regview) {
 189                 DP_NOTICE(cdev, "Cannot map register space, aborting\n");
 190                 rc = -ENOMEM;
 191                 goto err2;
 192         }
 193
 194         cdev->db_phys_addr = pci_resource_start(cdev->pdev, 2);
 195         cdev->db_size = pci_resource_len(cdev->pdev, 2);
 196         if (!cdev->db_size) {
 197                 if (IS_PF(cdev)) {
 198                         DP_NOTICE(cdev, "No Doorbell bar available\n");
 199                         return -EINVAL;
 200                 } else {
 201                         return 0;
 202                 }
 203         }
 204
 205         cdev->doorbells = ioremap_wc(cdev->db_phys_addr, cdev->db_size);
 206
 207         if (!cdev->doorbells) {
 208                 DP_NOTICE(cdev, "Cannot map doorbell space\n");
 209                 return -ENOMEM;
 210         }
 211
 212         /* AER (Advanced Error reporting) configuration */
 213         rc = pci_enable_pcie_error_reporting(pdev);
 214         if (rc)
 215                 DP_VERBOSE(cdev, NETIF_MSG_DRV,
 216                            "Failed to configure PCIe AER [%d]\n", rc);
 217
 218         return 0;
 219
 220 err2:
 221         pci_release_regions(pdev);
 222 err1:
 223         pci_disable_device(pdev);
 224 err0:
 225         return rc;
 226 }
 227
 228 int qed_fill_dev_info(struct qed_dev *cdev,
 229                       struct qed_dev_info *dev_info)
 230 {
 231         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
 232         struct qed_hw_info *hw_info = &p_hwfn->hw_info;
 233         struct qed_tunnel_info *tun = &cdev->tunnel;
 234         struct qed_ptt  *ptt;
 235
 236         memset(dev_info, 0, sizeof(struct qed_dev_info));
 237
 238         if (tun->vxlan.tun_cls == QED_TUNN_CLSS_MAC_VLAN &&
 239             tun->vxlan.b_mode_enabled)
 240                 dev_info->vxlan_enable = true;
 241
 242         if (tun->l2_gre.b_mode_enabled && tun->ip_gre.b_mode_enabled &&
 243             tun->l2_gre.tun_cls == QED_TUNN_CLSS_MAC_VLAN &&
 244             tun->ip_gre.tun_cls == QED_TUNN_CLSS_MAC_VLAN)
 245                 dev_info->gre_enable = true;
 246
 247         if (tun->l2_geneve.b_mode_enabled && tun->ip_geneve.b_mode_enabled &&
 248             tun->l2_geneve.tun_cls == QED_TUNN_CLSS_MAC_VLAN &&
 249             tun->ip_geneve.tun_cls == QED_TUNN_CLSS_MAC_VLAN)
 250                 dev_info->geneve_enable = true;
 251
 252         dev_info->num_hwfns = cdev->num_hwfns;
 253         dev_info->pci_mem_start = cdev->pci_params.mem_start;
 254         dev_info->pci_mem_end = cdev->pci_params.mem_end;
 255         dev_info->pci_irq = cdev->pci_params.irq;
 256         dev_info->rdma_supported = QED_IS_RDMA_PERSONALITY(p_hwfn);
 257         dev_info->dev_type = cdev->type;
 258         ether_addr_copy(dev_info->hw_mac, hw_info->hw_mac_addr);
 259
 260         if (IS_PF(cdev)) {
 261                 dev_info->fw_major = FW_MAJOR_VERSION;
 262                 dev_info->fw_minor = FW_MINOR_VERSION;
 263                 dev_info->fw_rev = FW_REVISION_VERSION;
 264                 dev_info->fw_eng = FW_ENGINEERING_VERSION;
 265                 dev_info->b_inter_pf_switch = test_bit(QED_MF_INTER_PF_SWITCH,
 266                                                        &cdev->mf_bits);
 267                 dev_info->tx_switching = true;
 268
 269                 if (hw_info->b_wol_support == QED_WOL_SUPPORT_PME)
 270                         dev_info->wol_support = true;
 271
 272                 dev_info->smart_an = qed_mcp_is_smart_an_supported(p_hwfn);
 273
 274                 dev_info->abs_pf_id = QED_LEADING_HWFN(cdev)->abs_pf_id;
 275         } else {
 276                 qed_vf_get_fw_version(&cdev->hwfns[0], &dev_info->fw_major,
 277                                       &dev_info->fw_minor, &dev_info->fw_rev,
 278                                       &dev_info->fw_eng);
 279         }
 280
 281         if (IS_PF(cdev)) {
 282                 ptt = qed_ptt_acquire(QED_LEADING_HWFN(cdev));
 283                 if (ptt) {
 284                         qed_mcp_get_mfw_ver(QED_LEADING_HWFN(cdev), ptt,
 285                                             &dev_info->mfw_rev, NULL);
 286
 287                         qed_mcp_get_mbi_ver(QED_LEADING_HWFN(cdev), ptt,
 288                                             &dev_info->mbi_version);
 289
 290                         qed_mcp_get_flash_size(QED_LEADING_HWFN(cdev), ptt,
 291                                                &dev_info->flash_size);
 292
 293                         qed_ptt_release(QED_LEADING_HWFN(cdev), ptt);
 294                 }
 295         } else {
 296                 qed_mcp_get_mfw_ver(QED_LEADING_HWFN(cdev), NULL,
 297                                     &dev_info->mfw_rev, NULL);
 298         }
 299
 300         dev_info->mtu = hw_info->mtu;
 301
 302         return 0;
 303 }
 304
 305 static void qed_free_cdev(struct qed_dev *cdev)
 306 {
 307         kfree((void *)cdev);
 308 }
 309
 310 static struct qed_dev *qed_alloc_cdev(struct pci_dev *pdev)
 311 {
 312         struct qed_dev *cdev;
 313
 314         cdev = kzalloc(sizeof(*cdev), GFP_KERNEL);
 315         if (!cdev)
 316                 return cdev;
 317
 318         qed_init_struct(cdev);
 319
 320         return cdev;
 321 }
 322
 323 /* Sets the requested power state */
 324 static int qed_set_power_state(struct qed_dev *cdev, pci_power_t state)
 325 {
 326         if (!cdev)
 327                 return -ENODEV;
 328
 329         DP_VERBOSE(cdev, NETIF_MSG_DRV, "Omitting Power state change\n");
 330         return 0;
 331 }
 332
 333 struct qed_devlink {
 334         struct qed_dev *cdev;
 335 };
 336
 337 enum qed_devlink_param_id {
 338         QED_DEVLINK_PARAM_ID_BASE = DEVLINK_PARAM_GENERIC_ID_MAX,
 339         QED_DEVLINK_PARAM_ID_IWARP_CMT,
 340 };
 341
 342 static int qed_dl_param_get(struct devlink *dl, u32 id,
 343                             struct devlink_param_gset_ctx *ctx)
 344 {
 345         struct qed_devlink *qed_dl;
 346         struct qed_dev *cdev;
 347
 348         qed_dl = devlink_priv(dl);
 349         cdev = qed_dl->cdev;
 350         ctx->val.vbool = cdev->iwarp_cmt;
 351
 352         return 0;
 353 }
 354
 355 static int qed_dl_param_set(struct devlink *dl, u32 id,
 356                             struct devlink_param_gset_ctx *ctx)
 357 {
 358         struct qed_devlink *qed_dl;
 359         struct qed_dev *cdev;
 360
 361         qed_dl = devlink_priv(dl);
 362         cdev = qed_dl->cdev;
 363         cdev->iwarp_cmt = ctx->val.vbool;
 364
 365         return 0;
 366 }
 367
 368 static const struct devlink_param qed_devlink_params[] = {
 369         DEVLINK_PARAM_DRIVER(QED_DEVLINK_PARAM_ID_IWARP_CMT,
 370                              "iwarp_cmt", DEVLINK_PARAM_TYPE_BOOL,
 371                              BIT(DEVLINK_PARAM_CMODE_RUNTIME),
 372                              qed_dl_param_get, qed_dl_param_set, NULL),
 373 };
 374
 375 static const struct devlink_ops qed_dl_ops;
 376
 377 static int qed_devlink_register(struct qed_dev *cdev)
 378 {
 379         union devlink_param_value value;
 380         struct qed_devlink *qed_dl;
 381         struct devlink *dl;
 382         int rc;
 383
 384         dl = devlink_alloc(&qed_dl_ops, sizeof(*qed_dl));
 385         if (!dl)
 386                 return -ENOMEM;
 387
 388         qed_dl = devlink_priv(dl);
 389
 390         cdev->dl = dl;
 391         qed_dl->cdev = cdev;
 392
 393         rc = devlink_register(dl, &cdev->pdev->dev);
 394         if (rc)
 395                 goto err_free;
 396
 397         rc = devlink_params_register(dl, qed_devlink_params,
 398                                      ARRAY_SIZE(qed_devlink_params));
 399         if (rc)
 400                 goto err_unregister;
 401
 402         value.vbool = false;
 403         devlink_param_driverinit_value_set(dl,
 404                                            QED_DEVLINK_PARAM_ID_IWARP_CMT,
 405                                            value);
 406
 407         devlink_params_publish(dl);
 408         cdev->iwarp_cmt = false;
 409
 410         return 0;
 411
 412 err_unregister:
 413         devlink_unregister(dl);
 414
 415 err_free:
 416         cdev->dl = NULL;
 417         devlink_free(dl);
 418
 419         return rc;
 420 }
 421
 422 static void qed_devlink_unregister(struct qed_dev *cdev)
 423 {
 424         if (!cdev->dl)
 425                 return;
 426
 427         devlink_params_unregister(cdev->dl, qed_devlink_params,
 428                                   ARRAY_SIZE(qed_devlink_params));
 429
 430         devlink_unregister(cdev->dl);
 431         devlink_free(cdev->dl);
 432 }
 433
 434 /* probing */
 435 static struct qed_dev *qed_probe(struct pci_dev *pdev,
 436                                  struct qed_probe_params *params)
 437 {
 438         struct qed_dev *cdev;
 439         int rc;
 440
 441         cdev = qed_alloc_cdev(pdev);
 442         if (!cdev)
 443                 goto err0;
 444
 445         cdev->drv_type = DRV_ID_DRV_TYPE_LINUX;
 446         cdev->protocol = params->protocol;
 447
 448         if (params->is_vf)
 449                 cdev->b_is_vf = true;
 450
 451         qed_init_dp(cdev, params->dp_module, params->dp_level);
 452
 453         cdev->recov_in_prog = params->recov_in_prog;
 454
 455         rc = qed_init_pci(cdev, pdev);
 456         if (rc) {
 457                 DP_ERR(cdev, "init pci failed\n");
 458                 goto err1;
 459         }
 460         DP_INFO(cdev, "PCI init completed successfully\n");
 461
 462         rc = qed_devlink_register(cdev);
 463         if (rc) {
 464                 DP_INFO(cdev, "Failed to register devlink.\n");
 465                 goto err2;
 466         }
 467
 468         rc = qed_hw_prepare(cdev, QED_PCI_DEFAULT);
 469         if (rc) {
 470                 DP_ERR(cdev, "hw prepare failed\n");
 471                 goto err2;
 472         }
 473
 474         DP_INFO(cdev, "qed_probe completed successfully\n");
 475
 476         return cdev;
 477
 478 err2:
 479         qed_free_pci(cdev);
 480 err1:
 481         qed_free_cdev(cdev);
 482 err0:
 483         return NULL;
 484 }
 485
 486 static void qed_remove(struct qed_dev *cdev)
 487 {
 488         if (!cdev)
 489                 return;
 490
 491         qed_hw_remove(cdev);
 492
 493         qed_free_pci(cdev);
 494
 495         qed_set_power_state(cdev, PCI_D3hot);
 496
 497         qed_devlink_unregister(cdev);
 498
 499         qed_free_cdev(cdev);
 500 }
 501
 502 static void qed_disable_msix(struct qed_dev *cdev)
 503 {
 504         if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) {
 505                 pci_disable_msix(cdev->pdev);
 506                 kfree(cdev->int_params.msix_table);
 507         } else if (cdev->int_params.out.int_mode == QED_INT_MODE_MSI) {
 508                 pci_disable_msi(cdev->pdev);
 509         }
 510
 511         memset(&cdev->int_params.out, 0, sizeof(struct qed_int_param));
 512 }
 513
 514 static int qed_enable_msix(struct qed_dev *cdev,
 515                            struct qed_int_params *int_params)
 516 {
 517         int i, rc, cnt;
 518
 519         cnt = int_params->in.num_vectors;
 520
 521         for (i = 0; i < cnt; i++)
 522                 int_params->msix_table[i].entry = i;
 523
 524         rc = pci_enable_msix_range(cdev->pdev, int_params->msix_table,
 525                                    int_params->in.min_msix_cnt, cnt);
 526         if (rc < cnt && rc >= int_params->in.min_msix_cnt &&
 527             (rc % cdev->num_hwfns)) {
 528                 pci_disable_msix(cdev->pdev);
 529
 530                 /* If fastpath is initialized, we need at least one interrupt
 531                  * per hwfn [and the slow path interrupts]. New requested number
 532                  * should be a multiple of the number of hwfns.
 533                  */
 534                 cnt = (rc / cdev->num_hwfns) * cdev->num_hwfns;
 535                 DP_NOTICE(cdev,
 536                           "Trying to enable MSI-X with less vectors (%d out of %d)\n",
 537                           cnt, int_params->in.num_vectors);
 538                 rc = pci_enable_msix_exact(cdev->pdev, int_params->msix_table,
 539                                            cnt);
 540                 if (!rc)
 541                         rc = cnt;
 542         }
 543
 544         if (rc > 0) {
 545                 /* MSI-x configuration was achieved */
 546                 int_params->out.int_mode = QED_INT_MODE_MSIX;
 547                 int_params->out.num_vectors = rc;
 548                 rc = 0;
 549         } else {
 550                 DP_NOTICE(cdev,
 551                           "Failed to enable MSI-X [Requested %d vectors][rc %d]\n",
 552                           cnt, rc);
 553         }
 554
 555         return rc;
 556 }
 557
 558 /* This function outputs the int mode and the number of enabled msix vector */
 559 static int qed_set_int_mode(struct qed_dev *cdev, bool force_mode)
 560 {
 561         struct qed_int_params *int_params = &cdev->int_params;
 562         struct msix_entry *tbl;
 563         int rc = 0, cnt;
 564
 565         switch (int_params->in.int_mode) {
 566         case QED_INT_MODE_MSIX:
 567                 /* Allocate MSIX table */
 568                 cnt = int_params->in.num_vectors;
 569                 int_params->msix_table = kcalloc(cnt, sizeof(*tbl), GFP_KERNEL);
 570                 if (!int_params->msix_table) {
 571                         rc = -ENOMEM;
 572                         goto out;
 573                 }
 574
 575                 /* Enable MSIX */
 576                 rc = qed_enable_msix(cdev, int_params);
 577                 if (!rc)
 578                         goto out;
 579
 580                 DP_NOTICE(cdev, "Failed to enable MSI-X\n");
 581                 kfree(int_params->msix_table);
 582                 if (force_mode)
 583                         goto out;
 584                 /* Fallthrough */
 585
 586         case QED_INT_MODE_MSI:
 587                 if (cdev->num_hwfns == 1) {
 588                         rc = pci_enable_msi(cdev->pdev);
 589                         if (!rc) {
 590                                 int_params->out.int_mode = QED_INT_MODE_MSI;
 591                                 goto out;
 592                         }
 593
 594                         DP_NOTICE(cdev, "Failed to enable MSI\n");
 595                         if (force_mode)
 596                                 goto out;
 597                 }
 598                 /* Fallthrough */
 599
 600         case QED_INT_MODE_INTA:
 601                         int_params->out.int_mode = QED_INT_MODE_INTA;
 602                         rc = 0;
 603                         goto out;
 604         default:
 605                 DP_NOTICE(cdev, "Unknown int_mode value %d\n",
 606                           int_params->in.int_mode);
 607                 rc = -EINVAL;
 608         }
 609
 610 out:
 611         if (!rc)
 612                 DP_INFO(cdev, "Using %s interrupts\n",
 613                         int_params->out.int_mode == QED_INT_MODE_INTA ?
 614                         "INTa" : int_params->out.int_mode == QED_INT_MODE_MSI ?
 615                         "MSI" : "MSIX");
 616         cdev->int_coalescing_mode = QED_COAL_MODE_ENABLE;
 617
 618         return rc;
 619 }
 620
 621 static void qed_simd_handler_config(struct qed_dev *cdev, void *token,
 622                                     int index, void(*handler)(void *))
 623 {
 624         struct qed_hwfn *hwfn = &cdev->hwfns[index % cdev->num_hwfns];
 625         int relative_idx = index / cdev->num_hwfns;
 626
 627         hwfn->simd_proto_handler[relative_idx].func = handler;
 628         hwfn->simd_proto_handler[relative_idx].token = token;
 629 }
 630
 631 static void qed_simd_handler_clean(struct qed_dev *cdev, int index)
 632 {
 633         struct qed_hwfn *hwfn = &cdev->hwfns[index % cdev->num_hwfns];
 634         int relative_idx = index / cdev->num_hwfns;
 635
 636         memset(&hwfn->simd_proto_handler[relative_idx], 0,
 637                sizeof(struct qed_simd_fp_handler));
 638 }
 639
 640 static irqreturn_t qed_msix_sp_int(int irq, void *tasklet)
 641 {
 642         tasklet_schedule((struct tasklet_struct *)tasklet);
 643         return IRQ_HANDLED;
 644 }
 645
 646 static irqreturn_t qed_single_int(int irq, void *dev_instance)
 647 {
 648         struct qed_dev *cdev = (struct qed_dev *)dev_instance;
 649         struct qed_hwfn *hwfn;
 650         irqreturn_t rc = IRQ_NONE;
 651         u64 status;
 652         int i, j;
 653
 654         for (i = 0; i < cdev->num_hwfns; i++) {
 655                 status = qed_int_igu_read_sisr_reg(&cdev->hwfns[i]);
 656
 657                 if (!status)
 658                         continue;
 659
 660                 hwfn = &cdev->hwfns[i];
 661
 662                 /* Slowpath interrupt */
 663                 if (unlikely(status & 0x1)) {
 664                         tasklet_schedule(hwfn->sp_dpc);
 665                         status &= ~0x1;
 666                         rc = IRQ_HANDLED;
 667                 }
 668
 669                 /* Fastpath interrupts */
 670                 for (j = 0; j < 64; j++) {
 671                         if ((0x2ULL << j) & status) {
 672                                 struct qed_simd_fp_handler *p_handler =
 673                                         &hwfn->simd_proto_handler[j];
 674
 675                                 if (p_handler->func)
 676                                         p_handler->func(p_handler->token);
 677                                 else
 678                                         DP_NOTICE(hwfn,
 679                                                   "Not calling fastpath handler as it is NULL [handler #%d, status 0x%llx]\n",
 680                                                   j, status);
 681
 682                                 status &= ~(0x2ULL << j);
 683                                 rc = IRQ_HANDLED;
 684                         }
 685                 }
 686
 687                 if (unlikely(status))
 688                         DP_VERBOSE(hwfn, NETIF_MSG_INTR,
 689                                    "got an unknown interrupt status 0x%llx\n",
 690                                    status);
 691         }
 692
 693         return rc;
 694 }
 695
 696 int qed_slowpath_irq_req(struct qed_hwfn *hwfn)
 697 {
 698         struct qed_dev *cdev = hwfn->cdev;
 699         u32 int_mode;
 700         int rc = 0;
 701         u8 id;
 702
 703         int_mode = cdev->int_params.out.int_mode;
 704         if (int_mode == QED_INT_MODE_MSIX) {
 705                 id = hwfn->my_id;
 706                 snprintf(hwfn->name, NAME_SIZE, "sp-%d-%02x:%02x.%02x",
 707                          id, cdev->pdev->bus->number,
 708                          PCI_SLOT(cdev->pdev->devfn), hwfn->abs_pf_id);
 709                 rc = request_irq(cdev->int_params.msix_table[id].vector,
 710                                  qed_msix_sp_int, 0, hwfn->name, hwfn->sp_dpc);
 711         } else {
 712                 unsigned long flags = 0;
 713
 714                 snprintf(cdev->name, NAME_SIZE, "%02x:%02x.%02x",
 715                          cdev->pdev->bus->number, PCI_SLOT(cdev->pdev->devfn),
 716                          PCI_FUNC(cdev->pdev->devfn));
 717
 718                 if (cdev->int_params.out.int_mode == QED_INT_MODE_INTA)
 719                         flags |= IRQF_SHARED;
 720
 721                 rc = request_irq(cdev->pdev->irq, qed_single_int,
 722                                  flags, cdev->name, cdev);
 723         }
 724
 725         if (rc)
 726                 DP_NOTICE(cdev, "request_irq failed, rc = %d\n", rc);
 727         else
 728                 DP_VERBOSE(hwfn, (NETIF_MSG_INTR | QED_MSG_SP),
 729                            "Requested slowpath %s\n",
 730                            (int_mode == QED_INT_MODE_MSIX) ? "MSI-X" : "IRQ");
 731
 732         return rc;
 733 }
 734
 735 static void qed_slowpath_tasklet_flush(struct qed_hwfn *p_hwfn)
 736 {
 737         /* Calling the disable function will make sure that any
 738          * currently-running function is completed. The following call to the
 739          * enable function makes this sequence a flush-like operation.
 740          */
 741         if (p_hwfn->b_sp_dpc_enabled) {
 742                 tasklet_disable(p_hwfn->sp_dpc);
 743                 tasklet_enable(p_hwfn->sp_dpc);
 744         }
 745 }
 746
 747 void qed_slowpath_irq_sync(struct qed_hwfn *p_hwfn)
 748 {
 749         struct qed_dev *cdev = p_hwfn->cdev;
 750         u8 id = p_hwfn->my_id;
 751         u32 int_mode;
 752
 753         int_mode = cdev->int_params.out.int_mode;
 754         if (int_mode == QED_INT_MODE_MSIX)
 755                 synchronize_irq(cdev->int_params.msix_table[id].vector);
 756         else
 757                 synchronize_irq(cdev->pdev->irq);
 758
 759         qed_slowpath_tasklet_flush(p_hwfn);
 760 }
 761
 762 static void qed_slowpath_irq_free(struct qed_dev *cdev)
 763 {
 764         int i;
 765
 766         if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) {
 767                 for_each_hwfn(cdev, i) {
 768                         if (!cdev->hwfns[i].b_int_requested)
 769                                 break;
 770                         synchronize_irq(cdev->int_params.msix_table[i].vector);
 771                         free_irq(cdev->int_params.msix_table[i].vector,
 772                                  cdev->hwfns[i].sp_dpc);
 773                 }
 774         } else {
 775                 if (QED_LEADING_HWFN(cdev)->b_int_requested)
 776                         free_irq(cdev->pdev->irq, cdev);
 777         }
 778         qed_int_disable_post_isr_release(cdev);
 779 }
 780
 781 static int qed_nic_stop(struct qed_dev *cdev)
 782 {
 783         int i, rc;
 784
 785         rc = qed_hw_stop(cdev);
 786
 787         for (i = 0; i < cdev->num_hwfns; i++) {
 788                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 789
 790                 if (p_hwfn->b_sp_dpc_enabled) {
 791                         tasklet_disable(p_hwfn->sp_dpc);
 792                         p_hwfn->b_sp_dpc_enabled = false;
 793                         DP_VERBOSE(cdev, NETIF_MSG_IFDOWN,
 794                                    "Disabled sp tasklet [hwfn %d] at %p\n",
 795                                    i, p_hwfn->sp_dpc);
 796                 }
 797         }
 798
 799         qed_dbg_pf_exit(cdev);
 800
 801         return rc;
 802 }
 803
 804 static int qed_nic_setup(struct qed_dev *cdev)
 805 {
 806         int rc, i;
 807
 808         /* Determine if interface is going to require LL2 */
 809         if (QED_LEADING_HWFN(cdev)->hw_info.personality != QED_PCI_ETH) {
 810                 for (i = 0; i < cdev->num_hwfns; i++) {
 811                         struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 812
 813                         p_hwfn->using_ll2 = true;
 814                 }
 815         }
 816
 817         rc = qed_resc_alloc(cdev);
 818         if (rc)
 819                 return rc;
 820
 821         DP_INFO(cdev, "Allocated qed resources\n");
 822
 823         qed_resc_setup(cdev);
 824
 825         return rc;
 826 }
 827
 828 static int qed_set_int_fp(struct qed_dev *cdev, u16 cnt)
 829 {
 830         int limit = 0;
 831
 832         /* Mark the fastpath as free/used */
 833         cdev->int_params.fp_initialized = cnt ? true : false;
 834
 835         if (cdev->int_params.out.int_mode != QED_INT_MODE_MSIX)
 836                 limit = cdev->num_hwfns * 63;
 837         else if (cdev->int_params.fp_msix_cnt)
 838                 limit = cdev->int_params.fp_msix_cnt;
 839
 840         if (!limit)
 841                 return -ENOMEM;
 842
 843         return min_t(int, cnt, limit);
 844 }
 845
 846 static int qed_get_int_fp(struct qed_dev *cdev, struct qed_int_info *info)
 847 {
 848         memset(info, 0, sizeof(struct qed_int_info));
 849
 850         if (!cdev->int_params.fp_initialized) {
 851                 DP_INFO(cdev,
 852                         "Protocol driver requested interrupt information, but its support is not yet configured\n");
 853                 return -EINVAL;
 854         }
 855
 856         /* Need to expose only MSI-X information; Single IRQ is handled solely
 857          * by qed.
 858          */
 859         if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) {
 860                 int msix_base = cdev->int_params.fp_msix_base;
 861
 862                 info->msix_cnt = cdev->int_params.fp_msix_cnt;
 863                 info->msix = &cdev->int_params.msix_table[msix_base];
 864         }
 865
 866         return 0;
 867 }
 868
 869 static int qed_slowpath_setup_int(struct qed_dev *cdev,
 870                                   enum qed_int_mode int_mode)
 871 {
 872         struct qed_sb_cnt_info sb_cnt_info;
 873         int num_l2_queues = 0;
 874         int rc;
 875         int i;
 876
 877         if ((int_mode == QED_INT_MODE_MSI) && (cdev->num_hwfns > 1)) {
 878                 DP_NOTICE(cdev, "MSI mode is not supported for CMT devices\n");
 879                 return -EINVAL;
 880         }
 881
 882         memset(&cdev->int_params, 0, sizeof(struct qed_int_params));
 883         cdev->int_params.in.int_mode = int_mode;
 884         for_each_hwfn(cdev, i) {
 885                 memset(&sb_cnt_info, 0, sizeof(sb_cnt_info));
 886                 qed_int_get_num_sbs(&cdev->hwfns[i], &sb_cnt_info);
 887                 cdev->int_params.in.num_vectors += sb_cnt_info.cnt;
 888                 cdev->int_params.in.num_vectors++; /* slowpath */
 889         }
 890
 891         /* We want a minimum of one slowpath and one fastpath vector per hwfn */
 892         cdev->int_params.in.min_msix_cnt = cdev->num_hwfns * 2;
 893
 894         if (is_kdump_kernel()) {
 895                 DP_INFO(cdev,
 896                         "Kdump kernel: Limit the max number of requested MSI-X vectors to %hd\n",
 897                         cdev->int_params.in.min_msix_cnt);
 898                 cdev->int_params.in.num_vectors =
 899                         cdev->int_params.in.min_msix_cnt;
 900         }
 901
 902         rc = qed_set_int_mode(cdev, false);
 903         if (rc)  {
 904                 DP_ERR(cdev, "qed_slowpath_setup_int ERR\n");
 905                 return rc;
 906         }
 907
 908         cdev->int_params.fp_msix_base = cdev->num_hwfns;
 909         cdev->int_params.fp_msix_cnt = cdev->int_params.out.num_vectors -
 910                                        cdev->num_hwfns;
 911
 912         if (!IS_ENABLED(CONFIG_QED_RDMA) ||
 913             !QED_IS_RDMA_PERSONALITY(QED_LEADING_HWFN(cdev)))
 914                 return 0;
 915
 916         for_each_hwfn(cdev, i)
 917                 num_l2_queues += FEAT_NUM(&cdev->hwfns[i], QED_PF_L2_QUE);
 918
 919         DP_VERBOSE(cdev, QED_MSG_RDMA,
 920                    "cdev->int_params.fp_msix_cnt=%d num_l2_queues=%d\n",
 921                    cdev->int_params.fp_msix_cnt, num_l2_queues);
 922
 923         if (cdev->int_params.fp_msix_cnt > num_l2_queues) {
 924                 cdev->int_params.rdma_msix_cnt =
 925                         (cdev->int_params.fp_msix_cnt - num_l2_queues)
 926                         / cdev->num_hwfns;
 927                 cdev->int_params.rdma_msix_base =
 928                         cdev->int_params.fp_msix_base + num_l2_queues;
 929                 cdev->int_params.fp_msix_cnt = num_l2_queues;
 930         } else {
 931                 cdev->int_params.rdma_msix_cnt = 0;
 932         }
 933
 934         DP_VERBOSE(cdev, QED_MSG_RDMA, "roce_msix_cnt=%d roce_msix_base=%d\n",
 935                    cdev->int_params.rdma_msix_cnt,
 936                    cdev->int_params.rdma_msix_base);
 937
 938         return 0;
 939 }
 940
 941 static int qed_slowpath_vf_setup_int(struct qed_dev *cdev)
 942 {
 943         int rc;
 944
 945         memset(&cdev->int_params, 0, sizeof(struct qed_int_params));
 946         cdev->int_params.in.int_mode = QED_INT_MODE_MSIX;
 947
 948         qed_vf_get_num_rxqs(QED_LEADING_HWFN(cdev),
 949                             &cdev->int_params.in.num_vectors);
 950         if (cdev->num_hwfns > 1) {
 951                 u8 vectors = 0;
 952
 953                 qed_vf_get_num_rxqs(&cdev->hwfns[1], &vectors);
 954                 cdev->int_params.in.num_vectors += vectors;
 955         }
 956
 957         /* We want a minimum of one fastpath vector per vf hwfn */
 958         cdev->int_params.in.min_msix_cnt = cdev->num_hwfns;
 959
 960         rc = qed_set_int_mode(cdev, true);
 961         if (rc)
 962                 return rc;
 963
 964         cdev->int_params.fp_msix_base = 0;
 965         cdev->int_params.fp_msix_cnt = cdev->int_params.out.num_vectors;
 966
 967         return 0;
 968 }
 969
 970 u32 qed_unzip_data(struct qed_hwfn *p_hwfn, u32 input_len,
 971                    u8 *input_buf, u32 max_size, u8 *unzip_buf)
 972 {
 973         int rc;
 974
 975         p_hwfn->stream->next_in = input_buf;
 976         p_hwfn->stream->avail_in = input_len;
 977         p_hwfn->stream->next_out = unzip_buf;
 978         p_hwfn->stream->avail_out = max_size;
 979
 980         rc = zlib_inflateInit2(p_hwfn->stream, MAX_WBITS);
 981
 982         if (rc != Z_OK) {
 983                 DP_VERBOSE(p_hwfn, NETIF_MSG_DRV, "zlib init failed, rc = %d\n",
 984                            rc);
 985                 return 0;
 986         }
 987
 988         rc = zlib_inflate(p_hwfn->stream, Z_FINISH);
 989         zlib_inflateEnd(p_hwfn->stream);
 990
 991         if (rc != Z_OK && rc != Z_STREAM_END) {
 992                 DP_VERBOSE(p_hwfn, NETIF_MSG_DRV, "FW unzip error: %s, rc=%d\n",
 993                            p_hwfn->stream->msg, rc);
 994                 return 0;
 995         }
 996
 997         return p_hwfn->stream->total_out / 4;
 998 }
 999
1000 static int qed_alloc_stream_mem(struct qed_dev *cdev)
1001 {
1002         int i;
1003         void *workspace;
1004
1005         for_each_hwfn(cdev, i) {
1006                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1007
1008                 p_hwfn->stream = kzalloc(sizeof(*p_hwfn->stream), GFP_KERNEL);
1009                 if (!p_hwfn->stream)
1010                         return -ENOMEM;
1011
1012                 workspace = vzalloc(zlib_inflate_workspacesize());
1013                 if (!workspace)
1014                         return -ENOMEM;
1015                 p_hwfn->stream->workspace = workspace;
1016         }
1017
1018         return 0;
1019 }
1020
1021 static void qed_free_stream_mem(struct qed_dev *cdev)
1022 {
1023         int i;
1024
1025         for_each_hwfn(cdev, i) {
1026                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1027
1028                 if (!p_hwfn->stream)
1029                         return;
1030
1031                 vfree(p_hwfn->stream->workspace);
1032                 kfree(p_hwfn->stream);
1033         }
1034 }
1035
1036 static void qed_update_pf_params(struct qed_dev *cdev,
1037                                  struct qed_pf_params *params)
1038 {
1039         int i;
1040
1041         if (IS_ENABLED(CONFIG_QED_RDMA)) {
1042                 params->rdma_pf_params.num_qps = QED_ROCE_QPS;
1043                 params->rdma_pf_params.min_dpis = QED_ROCE_DPIS;
1044                 params->rdma_pf_params.num_srqs = QED_RDMA_SRQS;
1045                 /* divide by 3 the MRs to avoid MF ILT overflow */
1046                 params->rdma_pf_params.gl_pi = QED_ROCE_PROTOCOL_INDEX;
1047         }
1048
1049         if (cdev->num_hwfns > 1 || IS_VF(cdev))
1050                 params->eth_pf_params.num_arfs_filters = 0;
1051
1052         /* In case we might support RDMA, don't allow qede to be greedy
1053          * with the L2 contexts. Allow for 64 queues [rx, tx cos, xdp]
1054          * per hwfn.
1055          */
1056         if (QED_IS_RDMA_PERSONALITY(QED_LEADING_HWFN(cdev))) {
1057                 u16 *num_cons;
1058
1059                 num_cons = &params->eth_pf_params.num_cons;
1060                 *num_cons = min_t(u16, *num_cons, QED_MAX_L2_CONS);
1061         }
1062
1063         for (i = 0; i < cdev->num_hwfns; i++) {
1064                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1065
1066                 p_hwfn->pf_params = *params;
1067         }
1068 }
1069
1070 #define QED_PERIODIC_DB_REC_COUNT               10
1071 #define QED_PERIODIC_DB_REC_INTERVAL_MS         100
1072 #define QED_PERIODIC_DB_REC_INTERVAL \
1073         msecs_to_jiffies(QED_PERIODIC_DB_REC_INTERVAL_MS)
1074
1075 static int qed_slowpath_delayed_work(struct qed_hwfn *hwfn,
1076                                      enum qed_slowpath_wq_flag wq_flag,
1077                                      unsigned long delay)
1078 {
1079         if (!hwfn->slowpath_wq_active)
1080                 return -EINVAL;
1081
1082         /* Memory barrier for setting atomic bit */
1083         smp_mb__before_atomic();
1084         set_bit(wq_flag, &hwfn->slowpath_task_flags);
1085         smp_mb__after_atomic();
1086         queue_delayed_work(hwfn->slowpath_wq, &hwfn->slowpath_task, delay);
1087
1088         return 0;
1089 }
1090
1091 void qed_periodic_db_rec_start(struct qed_hwfn *p_hwfn)
1092 {
1093         /* Reset periodic Doorbell Recovery counter */
1094         p_hwfn->periodic_db_rec_count = QED_PERIODIC_DB_REC_COUNT;
1095
1096         /* Don't schedule periodic Doorbell Recovery if already scheduled */
1097         if (test_bit(QED_SLOWPATH_PERIODIC_DB_REC,
1098                      &p_hwfn->slowpath_task_flags))
1099                 return;
1100
1101         qed_slowpath_delayed_work(p_hwfn, QED_SLOWPATH_PERIODIC_DB_REC,
1102                                   QED_PERIODIC_DB_REC_INTERVAL);
1103 }
1104
1105 static void qed_slowpath_wq_stop(struct qed_dev *cdev)
1106 {
1107         int i;
1108
1109         if (IS_VF(cdev))
1110                 return;
1111
1112         for_each_hwfn(cdev, i) {
1113                 if (!cdev->hwfns[i].slowpath_wq)
1114                         continue;
1115
1116                 /* Stop queuing new delayed works */
1117                 cdev->hwfns[i].slowpath_wq_active = false;
1118
1119                 cancel_delayed_work(&cdev->hwfns[i].slowpath_task);
1120                 destroy_workqueue(cdev->hwfns[i].slowpath_wq);
1121         }
1122 }
1123
1124 static void qed_slowpath_task(struct work_struct *work)
1125 {
1126         struct qed_hwfn *hwfn = container_of(work, struct qed_hwfn,
1127                                              slowpath_task.work);
1128         struct qed_ptt *ptt = qed_ptt_acquire(hwfn);
1129
1130         if (!ptt) {
1131                 if (hwfn->slowpath_wq_active)
1132                         queue_delayed_work(hwfn->slowpath_wq,
1133                                            &hwfn->slowpath_task, 0);
1134
1135                 return;
1136         }
1137
1138         if (test_and_clear_bit(QED_SLOWPATH_MFW_TLV_REQ,
1139                                &hwfn->slowpath_task_flags))
1140                 qed_mfw_process_tlv_req(hwfn, ptt);
1141
1142         if (test_and_clear_bit(QED_SLOWPATH_PERIODIC_DB_REC,
1143                                &hwfn->slowpath_task_flags)) {
1144                 qed_db_rec_handler(hwfn, ptt);
1145                 if (hwfn->periodic_db_rec_count--)
1146                         qed_slowpath_delayed_work(hwfn,
1147                                                   QED_SLOWPATH_PERIODIC_DB_REC,
1148                                                   QED_PERIODIC_DB_REC_INTERVAL);
1149         }
1150
1151         qed_ptt_release(hwfn, ptt);
1152 }
1153
1154 static int qed_slowpath_wq_start(struct qed_dev *cdev)
1155 {
1156         struct qed_hwfn *hwfn;
1157         char name[NAME_SIZE];
1158         int i;
1159
1160         if (IS_VF(cdev))
1161                 return 0;
1162
1163         for_each_hwfn(cdev, i) {
1164                 hwfn = &cdev->hwfns[i];
1165
1166                 snprintf(name, NAME_SIZE, "slowpath-%02x:%02x.%02x",
1167                          cdev->pdev->bus->number,
1168                          PCI_SLOT(cdev->pdev->devfn), hwfn->abs_pf_id);
1169
1170                 hwfn->slowpath_wq = alloc_workqueue(name, 0, 0);
1171                 if (!hwfn->slowpath_wq) {
1172                         DP_NOTICE(hwfn, "Cannot create slowpath workqueue\n");
1173                         return -ENOMEM;
1174                 }
1175
1176                 INIT_DELAYED_WORK(&hwfn->slowpath_task, qed_slowpath_task);
1177                 hwfn->slowpath_wq_active = true;
1178         }
1179
1180         return 0;
1181 }
1182
1183 static int qed_slowpath_start(struct qed_dev *cdev,
1184                               struct qed_slowpath_params *params)
1185 {
1186         struct qed_drv_load_params drv_load_params;
1187         struct qed_hw_init_params hw_init_params;
1188         struct qed_mcp_drv_version drv_version;
1189         struct qed_tunnel_info tunn_info;
1190         const u8 *data = NULL;
1191         struct qed_hwfn *hwfn;
1192         struct qed_ptt *p_ptt;
1193         int rc = -EINVAL;
1194
1195         if (qed_iov_wq_start(cdev))
1196                 goto err;
1197
1198         if (qed_slowpath_wq_start(cdev))
1199                 goto err;
1200
1201         if (IS_PF(cdev)) {
1202                 rc = request_firmware(&cdev->firmware, QED_FW_FILE_NAME,
1203                                       &cdev->pdev->dev);
1204                 if (rc) {
1205                         DP_NOTICE(cdev,
1206                                   "Failed to find fw file - /lib/firmware/%s\n",
1207                                   QED_FW_FILE_NAME);
1208                         goto err;
1209                 }
1210
1211                 if (cdev->num_hwfns == 1) {
1212                         p_ptt = qed_ptt_acquire(QED_LEADING_HWFN(cdev));
1213                         if (p_ptt) {
1214                                 QED_LEADING_HWFN(cdev)->p_arfs_ptt = p_ptt;
1215                         } else {
1216                                 DP_NOTICE(cdev,
1217                                           "Failed to acquire PTT for aRFS\n");
1218                                 goto err;
1219                         }
1220                 }
1221         }
1222
1223         cdev->rx_coalesce_usecs = QED_DEFAULT_RX_USECS;
1224         rc = qed_nic_setup(cdev);
1225         if (rc)
1226                 goto err;
1227
1228         if (IS_PF(cdev))
1229                 rc = qed_slowpath_setup_int(cdev, params->int_mode);
1230         else
1231                 rc = qed_slowpath_vf_setup_int(cdev);
1232         if (rc)
1233                 goto err1;
1234
1235         if (IS_PF(cdev)) {
1236                 /* Allocate stream for unzipping */
1237                 rc = qed_alloc_stream_mem(cdev);
1238                 if (rc)
1239                         goto err2;
1240
1241                 /* First Dword used to differentiate between various sources */
1242                 data = cdev->firmware->data + sizeof(u32);
1243
1244                 qed_dbg_pf_init(cdev);
1245         }
1246
1247         /* Start the slowpath */
1248         memset(&hw_init_params, 0, sizeof(hw_init_params));
1249         memset(&tunn_info, 0, sizeof(tunn_info));
1250         tunn_info.vxlan.b_mode_enabled = true;
1251         tunn_info.l2_gre.b_mode_enabled = true;
1252         tunn_info.ip_gre.b_mode_enabled = true;
1253         tunn_info.l2_geneve.b_mode_enabled = true;
1254         tunn_info.ip_geneve.b_mode_enabled = true;
1255         tunn_info.vxlan.tun_cls = QED_TUNN_CLSS_MAC_VLAN;
1256         tunn_info.l2_gre.tun_cls = QED_TUNN_CLSS_MAC_VLAN;
1257         tunn_info.ip_gre.tun_cls = QED_TUNN_CLSS_MAC_VLAN;
1258         tunn_info.l2_geneve.tun_cls = QED_TUNN_CLSS_MAC_VLAN;
1259         tunn_info.ip_geneve.tun_cls = QED_TUNN_CLSS_MAC_VLAN;
1260         hw_init_params.p_tunn = &tunn_info;
1261         hw_init_params.b_hw_start = true;
1262         hw_init_params.int_mode = cdev->int_params.out.int_mode;
1263         hw_init_params.allow_npar_tx_switch = true;
1264         hw_init_params.bin_fw_data = data;
1265
1266         memset(&drv_load_params, 0, sizeof(drv_load_params));
1267         drv_load_params.is_crash_kernel = is_kdump_kernel();
1268         drv_load_params.mfw_timeout_val = QED_LOAD_REQ_LOCK_TO_DEFAULT;
1269         drv_load_params.avoid_eng_reset = false;
1270         drv_load_params.override_force_load = QED_OVERRIDE_FORCE_LOAD_NONE;
1271         hw_init_params.p_drv_load_params = &drv_load_params;
1272
1273         rc = qed_hw_init(cdev, &hw_init_params);
1274         if (rc)
1275                 goto err2;
1276
1277         DP_INFO(cdev,
1278                 "HW initialization and function start completed successfully\n");
1279
1280         if (IS_PF(cdev)) {
1281                 cdev->tunn_feature_mask = (BIT(QED_MODE_VXLAN_TUNN) |
1282                                            BIT(QED_MODE_L2GENEVE_TUNN) |
1283                                            BIT(QED_MODE_IPGENEVE_TUNN) |
1284                                            BIT(QED_MODE_L2GRE_TUNN) |
1285                                            BIT(QED_MODE_IPGRE_TUNN));
1286         }
1287
1288         /* Allocate LL2 interface if needed */
1289         if (QED_LEADING_HWFN(cdev)->using_ll2) {
1290                 rc = qed_ll2_alloc_if(cdev);
1291                 if (rc)
1292                         goto err3;
1293         }
1294         if (IS_PF(cdev)) {
1295                 hwfn = QED_LEADING_HWFN(cdev);
1296                 drv_version.version = (params->drv_major << 24) |
1297                                       (params->drv_minor << 16) |
1298                                       (params->drv_rev << 8) |
1299                                       (params->drv_eng);
1300                 strlcpy(drv_version.name, params->name,
1301                         MCP_DRV_VER_STR_SIZE - 4);
1302                 rc = qed_mcp_send_drv_version(hwfn, hwfn->p_main_ptt,
1303                                               &drv_version);
1304                 if (rc) {
1305                         DP_NOTICE(cdev, "Failed sending drv version command\n");
1306                         goto err4;
1307                 }
1308         }
1309
1310         qed_reset_vport_stats(cdev);
1311
1312         return 0;
1313
1314 err4:
1315         qed_ll2_dealloc_if(cdev);
1316 err3:
1317         qed_hw_stop(cdev);
1318 err2:
1319         qed_hw_timers_stop_all(cdev);
1320         if (IS_PF(cdev))
1321                 qed_slowpath_irq_free(cdev);
1322         qed_free_stream_mem(cdev);
1323         qed_disable_msix(cdev);
1324 err1:
1325         qed_resc_free(cdev);
1326 err:
1327         if (IS_PF(cdev))
1328                 release_firmware(cdev->firmware);
1329
1330         if (IS_PF(cdev) && (cdev->num_hwfns == 1) &&
1331             QED_LEADING_HWFN(cdev)->p_arfs_ptt)
1332                 qed_ptt_release(QED_LEADING_HWFN(cdev),
1333                                 QED_LEADING_HWFN(cdev)->p_arfs_ptt);
1334
1335         qed_iov_wq_stop(cdev, false);
1336
1337         qed_slowpath_wq_stop(cdev);
1338
1339         return rc;
1340 }
1341
1342 static int qed_slowpath_stop(struct qed_dev *cdev)
1343 {
1344         if (!cdev)
1345                 return -ENODEV;
1346
1347         qed_slowpath_wq_stop(cdev);
1348
1349         qed_ll2_dealloc_if(cdev);
1350
1351         if (IS_PF(cdev)) {
1352                 if (cdev->num_hwfns == 1)
1353                         qed_ptt_release(QED_LEADING_HWFN(cdev),
1354                                         QED_LEADING_HWFN(cdev)->p_arfs_ptt);
1355                 qed_free_stream_mem(cdev);
1356                 if (IS_QED_ETH_IF(cdev))
1357                         qed_sriov_disable(cdev, true);
1358         }
1359
1360         qed_nic_stop(cdev);
1361
1362         if (IS_PF(cdev))
1363                 qed_slowpath_irq_free(cdev);
1364
1365         qed_disable_msix(cdev);
1366
1367         qed_resc_free(cdev);
1368
1369         qed_iov_wq_stop(cdev, true);
1370
1371         if (IS_PF(cdev))
1372                 release_firmware(cdev->firmware);
1373
1374         return 0;
1375 }
1376
1377 static void qed_set_name(struct qed_dev *cdev, char name[NAME_SIZE])
1378 {
1379         int i;
1380
1381         memcpy(cdev->name, name, NAME_SIZE);
1382         for_each_hwfn(cdev, i)
1383                 snprintf(cdev->hwfns[i].name, NAME_SIZE, "%s-%d", name, i);
1384 }
1385
1386 static u32 qed_sb_init(struct qed_dev *cdev,
1387                        struct qed_sb_info *sb_info,
1388                        void *sb_virt_addr,
1389                        dma_addr_t sb_phy_addr, u16 sb_id,
1390                        enum qed_sb_type type)
1391 {
1392         struct qed_hwfn *p_hwfn;
1393         struct qed_ptt *p_ptt;
1394         u16 rel_sb_id;
1395         u32 rc;
1396
1397         /* RoCE/Storage use a single engine in CMT mode while L2 uses both */
1398         if (type == QED_SB_TYPE_L2_QUEUE) {
1399                 p_hwfn = &cdev->hwfns[sb_id % cdev->num_hwfns];
1400                 rel_sb_id = sb_id / cdev->num_hwfns;
1401         } else {
1402                 p_hwfn = QED_AFFIN_HWFN(cdev);
1403                 rel_sb_id = sb_id;
1404         }
1405
1406         DP_VERBOSE(cdev, NETIF_MSG_INTR,
1407                    "hwfn [%d] <--[init]-- SB %04x [0x%04x upper]\n",
1408                    IS_LEAD_HWFN(p_hwfn) ? 0 : 1, rel_sb_id, sb_id);
1409
1410         if (IS_PF(p_hwfn->cdev)) {
1411                 p_ptt = qed_ptt_acquire(p_hwfn);
1412                 if (!p_ptt)
1413                         return -EBUSY;
1414
1415                 rc = qed_int_sb_init(p_hwfn, p_ptt, sb_info, sb_virt_addr,
1416                                      sb_phy_addr, rel_sb_id);
1417                 qed_ptt_release(p_hwfn, p_ptt);
1418         } else {
1419                 rc = qed_int_sb_init(p_hwfn, NULL, sb_info, sb_virt_addr,
1420                                      sb_phy_addr, rel_sb_id);
1421         }
1422
1423         return rc;
1424 }
1425
1426 static u32 qed_sb_release(struct qed_dev *cdev,
1427                           struct qed_sb_info *sb_info,
1428                           u16 sb_id,
1429                           enum qed_sb_type type)
1430 {
1431         struct qed_hwfn *p_hwfn;
1432         u16 rel_sb_id;
1433         u32 rc;
1434
1435         /* RoCE/Storage use a single engine in CMT mode while L2 uses both */
1436         if (type == QED_SB_TYPE_L2_QUEUE) {
1437                 p_hwfn = &cdev->hwfns[sb_id % cdev->num_hwfns];
1438                 rel_sb_id = sb_id / cdev->num_hwfns;
1439         } else {
1440                 p_hwfn = QED_AFFIN_HWFN(cdev);
1441                 rel_sb_id = sb_id;
1442         }
1443
1444         DP_VERBOSE(cdev, NETIF_MSG_INTR,
1445                    "hwfn [%d] <--[init]-- SB %04x [0x%04x upper]\n",
1446                    IS_LEAD_HWFN(p_hwfn) ? 0 : 1, rel_sb_id, sb_id);
1447
1448         rc = qed_int_sb_release(p_hwfn, sb_info, rel_sb_id);
1449
1450         return rc;
1451 }
1452
1453 static bool qed_can_link_change(struct qed_dev *cdev)
1454 {
1455         return true;
1456 }
1457
1458 static int qed_set_link(struct qed_dev *cdev, struct qed_link_params *params)
1459 {
1460         __ETHTOOL_DECLARE_LINK_MODE_MASK(sup_caps);
1461         struct qed_mcp_link_params *link_params;
1462         struct qed_hwfn *hwfn;
1463         struct qed_ptt *ptt;
1464         u32 as;
1465         int rc;
1466
1467         if (!cdev)
1468                 return -ENODEV;
1469
1470         /* The link should be set only once per PF */
1471         hwfn = &cdev->hwfns[0];
1472
1473         /* When VF wants to set link, force it to read the bulletin instead.
1474          * This mimics the PF behavior, where a noitification [both immediate
1475          * and possible later] would be generated when changing properties.
1476          */
1477         if (IS_VF(cdev)) {
1478                 qed_schedule_iov(hwfn, QED_IOV_WQ_VF_FORCE_LINK_QUERY_FLAG);
1479                 return 0;
1480         }
1481
1482         ptt = qed_ptt_acquire(hwfn);
1483         if (!ptt)
1484                 return -EBUSY;
1485
1486         link_params = qed_mcp_get_link_params(hwfn);
1487         if (!link_params)
1488                 return -ENODATA;
1489
1490         if (params->override_flags & QED_LINK_OVERRIDE_SPEED_AUTONEG)
1491                 link_params->speed.autoneg = params->autoneg;
1492
1493         if (params->override_flags & QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS) {
1494                 as = 0;
1495
1496                 phylink_zero(sup_caps);
1497                 phylink_set(sup_caps, 1000baseT_Full);
1498                 phylink_set(sup_caps, 1000baseKX_Full);
1499                 phylink_set(sup_caps, 1000baseX_Full);
1500
1501                 if (linkmode_intersects(params->adv_speeds, sup_caps))
1502                         as |= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G;
1503
1504                 phylink_zero(sup_caps);
1505                 phylink_set(sup_caps, 10000baseT_Full);
1506                 phylink_set(sup_caps, 10000baseKR_Full);
1507                 phylink_set(sup_caps, 10000baseKX4_Full);
1508                 phylink_set(sup_caps, 10000baseR_FEC);
1509                 phylink_set(sup_caps, 10000baseCR_Full);
1510                 phylink_set(sup_caps, 10000baseSR_Full);
1511                 phylink_set(sup_caps, 10000baseLR_Full);
1512                 phylink_set(sup_caps, 10000baseLRM_Full);
1513
1514                 if (linkmode_intersects(params->adv_speeds, sup_caps))
1515                         as |= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G;
1516
1517                 phylink_zero(sup_caps);
1518                 phylink_set(sup_caps, 20000baseKR2_Full);
1519
1520                 if (linkmode_intersects(params->adv_speeds, sup_caps))
1521                         as |= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G;
1522
1523                 phylink_zero(sup_caps);
1524                 phylink_set(sup_caps, 25000baseKR_Full);
1525                 phylink_set(sup_caps, 25000baseCR_Full);
1526                 phylink_set(sup_caps, 25000baseSR_Full);
1527
1528                 if (linkmode_intersects(params->adv_speeds, sup_caps))
1529                         as |= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G;
1530
1531                 phylink_zero(sup_caps);
1532                 phylink_set(sup_caps, 40000baseLR4_Full);
1533                 phylink_set(sup_caps, 40000baseKR4_Full);
1534                 phylink_set(sup_caps, 40000baseCR4_Full);
1535                 phylink_set(sup_caps, 40000baseSR4_Full);
1536
1537                 if (linkmode_intersects(params->adv_speeds, sup_caps))
1538                         as |= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G;
1539
1540                 phylink_zero(sup_caps);
1541                 phylink_set(sup_caps, 50000baseKR2_Full);
1542                 phylink_set(sup_caps, 50000baseCR2_Full);
1543                 phylink_set(sup_caps, 50000baseSR2_Full);
1544
1545                 if (linkmode_intersects(params->adv_speeds, sup_caps))
1546                         as |= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G;
1547
1548                 phylink_zero(sup_caps);
1549                 phylink_set(sup_caps, 100000baseKR4_Full);
1550                 phylink_set(sup_caps, 100000baseSR4_Full);
1551                 phylink_set(sup_caps, 100000baseCR4_Full);
1552                 phylink_set(sup_caps, 100000baseLR4_ER4_Full);
1553
1554                 if (linkmode_intersects(params->adv_speeds, sup_caps))
1555                         as |= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G;
1556
1557                 link_params->speed.advertised_speeds = as;
1558         }
1559
1560         if (params->override_flags & QED_LINK_OVERRIDE_SPEED_FORCED_SPEED)
1561                 link_params->speed.forced_speed = params->forced_speed;
1562         if (params->override_flags & QED_LINK_OVERRIDE_PAUSE_CONFIG) {
1563                 if (params->pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE)
1564                         link_params->pause.autoneg = true;
1565                 else
1566                         link_params->pause.autoneg = false;
1567                 if (params->pause_config & QED_LINK_PAUSE_RX_ENABLE)
1568                         link_params->pause.forced_rx = true;
1569                 else
1570                         link_params->pause.forced_rx = false;
1571                 if (params->pause_config & QED_LINK_PAUSE_TX_ENABLE)
1572                         link_params->pause.forced_tx = true;
1573                 else
1574                         link_params->pause.forced_tx = false;
1575         }
1576         if (params->override_flags & QED_LINK_OVERRIDE_LOOPBACK_MODE) {
1577                 switch (params->loopback_mode) {
1578                 case QED_LINK_LOOPBACK_INT_PHY:
1579                         link_params->loopback_mode = ETH_LOOPBACK_INT_PHY;
1580                         break;
1581                 case QED_LINK_LOOPBACK_EXT_PHY:
1582                         link_params->loopback_mode = ETH_LOOPBACK_EXT_PHY;
1583                         break;
1584                 case QED_LINK_LOOPBACK_EXT:
1585                         link_params->loopback_mode = ETH_LOOPBACK_EXT;
1586                         break;
1587                 case QED_LINK_LOOPBACK_MAC:
1588                         link_params->loopback_mode = ETH_LOOPBACK_MAC;
1589                         break;
1590                 default:
1591                         link_params->loopback_mode = ETH_LOOPBACK_NONE;
1592                         break;
1593                 }
1594         }
1595
1596         if (params->override_flags & QED_LINK_OVERRIDE_EEE_CONFIG)
1597                 memcpy(&link_params->eee, &params->eee,
1598                        sizeof(link_params->eee));
1599
1600         rc = qed_mcp_set_link(hwfn, ptt, params->link_up);
1601
1602         qed_ptt_release(hwfn, ptt);
1603
1604         return rc;
1605 }
1606
1607 static int qed_get_port_type(u32 media_type)
1608 {
1609         int port_type;
1610
1611         switch (media_type) {
1612         case MEDIA_SFPP_10G_FIBER:
1613         case MEDIA_SFP_1G_FIBER:
1614         case MEDIA_XFP_FIBER:
1615         case MEDIA_MODULE_FIBER:
1616         case MEDIA_KR:
1617                 port_type = PORT_FIBRE;
1618                 break;
1619         case MEDIA_DA_TWINAX:
1620                 port_type = PORT_DA;
1621                 break;
1622         case MEDIA_BASE_T:
1623                 port_type = PORT_TP;
1624                 break;
1625         case MEDIA_NOT_PRESENT:
1626                 port_type = PORT_NONE;
1627                 break;
1628         case MEDIA_UNSPECIFIED:
1629         default:
1630                 port_type = PORT_OTHER;
1631                 break;
1632         }
1633         return port_type;
1634 }
1635
1636 static int qed_get_link_data(struct qed_hwfn *hwfn,
1637                              struct qed_mcp_link_params *params,
1638                              struct qed_mcp_link_state *link,
1639                              struct qed_mcp_link_capabilities *link_caps)
1640 {
1641         void *p;
1642
1643         if (!IS_PF(hwfn->cdev)) {
1644                 qed_vf_get_link_params(hwfn, params);
1645                 qed_vf_get_link_state(hwfn, link);
1646                 qed_vf_get_link_caps(hwfn, link_caps);
1647
1648                 return 0;
1649         }
1650
1651         p = qed_mcp_get_link_params(hwfn);
1652         if (!p)
1653                 return -ENXIO;
1654         memcpy(params, p, sizeof(*params));
1655
1656         p = qed_mcp_get_link_state(hwfn);
1657         if (!p)
1658                 return -ENXIO;
1659         memcpy(link, p, sizeof(*link));
1660
1661         p = qed_mcp_get_link_capabilities(hwfn);
1662         if (!p)
1663                 return -ENXIO;
1664         memcpy(link_caps, p, sizeof(*link_caps));
1665
1666         return 0;
1667 }
1668
1669 static void qed_fill_link_capability(struct qed_hwfn *hwfn,
1670                                      struct qed_ptt *ptt, u32 capability,
1671                                      unsigned long *if_caps)
1672 {
1673         u32 media_type, tcvr_state, tcvr_type;
1674         u32 speed_mask, board_cfg;
1675
1676         if (qed_mcp_get_media_type(hwfn, ptt, &media_type))
1677                 media_type = MEDIA_UNSPECIFIED;
1678
1679         if (qed_mcp_get_transceiver_data(hwfn, ptt, &tcvr_state, &tcvr_type))
1680                 tcvr_type = ETH_TRANSCEIVER_STATE_UNPLUGGED;
1681
1682         if (qed_mcp_trans_speed_mask(hwfn, ptt, &speed_mask))
1683                 speed_mask = 0xFFFFFFFF;
1684
1685         if (qed_mcp_get_board_config(hwfn, ptt, &board_cfg))
1686                 board_cfg = NVM_CFG1_PORT_PORT_TYPE_UNDEFINED;
1687
1688         DP_VERBOSE(hwfn->cdev, NETIF_MSG_DRV,
1689                    "Media_type = 0x%x tcvr_state = 0x%x tcvr_type = 0x%x speed_mask = 0x%x board_cfg = 0x%x\n",
1690                    media_type, tcvr_state, tcvr_type, speed_mask, board_cfg);
1691
1692         switch (media_type) {
1693         case MEDIA_DA_TWINAX:
1694                 phylink_set(if_caps, FIBRE);
1695
1696                 if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G)
1697                         phylink_set(if_caps, 20000baseKR2_Full);
1698
1699                 /* For DAC media multiple speed capabilities are supported */
1700                 capability |= speed_mask;
1701
1702                 if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
1703                         phylink_set(if_caps, 1000baseKX_Full);
1704                 if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
1705                         phylink_set(if_caps, 10000baseCR_Full);
1706
1707                 if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
1708                         switch (tcvr_type) {
1709                         case ETH_TRANSCEIVER_TYPE_40G_CR4:
1710                         case ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_CR:
1711                         case ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_CR:
1712                                 phylink_set(if_caps, 40000baseCR4_Full);
1713                                 break;
1714                         default:
1715                                 break;
1716                         }
1717
1718                 if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
1719                         phylink_set(if_caps, 25000baseCR_Full);
1720                 if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
1721                         phylink_set(if_caps, 50000baseCR2_Full);
1722
1723                 if (capability &
1724                     NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
1725                         switch (tcvr_type) {
1726                         case ETH_TRANSCEIVER_TYPE_100G_CR4:
1727                         case ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_CR:
1728                                 phylink_set(if_caps, 100000baseCR4_Full);
1729                                 break;
1730                         default:
1731                                 break;
1732                         }
1733
1734                 break;
1735         case MEDIA_BASE_T:
1736                 phylink_set(if_caps, TP);
1737
1738                 if (board_cfg & NVM_CFG1_PORT_PORT_TYPE_EXT_PHY) {
1739                         if (capability &
1740                             NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
1741                                 phylink_set(if_caps, 1000baseT_Full);
1742                         if (capability &
1743                             NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
1744                                 phylink_set(if_caps, 10000baseT_Full);
1745                 }
1746
1747                 if (board_cfg & NVM_CFG1_PORT_PORT_TYPE_MODULE) {
1748                         phylink_set(if_caps, FIBRE);
1749
1750                         switch (tcvr_type) {
1751                         case ETH_TRANSCEIVER_TYPE_1000BASET:
1752                                 phylink_set(if_caps, 1000baseT_Full);
1753                                 break;
1754                         case ETH_TRANSCEIVER_TYPE_10G_BASET:
1755                                 phylink_set(if_caps, 10000baseT_Full);
1756                                 break;
1757                         default:
1758                                 break;
1759                         }
1760                 }
1761
1762                 break;
1763         case MEDIA_SFP_1G_FIBER:
1764         case MEDIA_SFPP_10G_FIBER:
1765         case MEDIA_XFP_FIBER:
1766         case MEDIA_MODULE_FIBER:
1767                 phylink_set(if_caps, FIBRE);
1768                 capability |= speed_mask;
1769
1770                 if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
1771                         switch (tcvr_type) {
1772                         case ETH_TRANSCEIVER_TYPE_1G_LX:
1773                         case ETH_TRANSCEIVER_TYPE_1G_SX:
1774                         case ETH_TRANSCEIVER_TYPE_MULTI_RATE_1G_10G_SR:
1775                         case ETH_TRANSCEIVER_TYPE_MULTI_RATE_1G_10G_LR:
1776                                 phylink_set(if_caps, 1000baseKX_Full);
1777                                 break;
1778                         default:
1779                                 break;
1780                         }
1781
1782                 if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
1783                         switch (tcvr_type) {
1784                         case ETH_TRANSCEIVER_TYPE_10G_SR:
1785                         case ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_SR:
1786                         case ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_25G_SR:
1787                         case ETH_TRANSCEIVER_TYPE_MULTI_RATE_1G_10G_SR:
1788                                 phylink_set(if_caps, 10000baseSR_Full);
1789                                 break;
1790                         case ETH_TRANSCEIVER_TYPE_10G_LR:
1791                         case ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_LR:
1792                         case ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_25G_LR:
1793                         case ETH_TRANSCEIVER_TYPE_MULTI_RATE_1G_10G_LR:
1794                                 phylink_set(if_caps, 10000baseLR_Full);
1795                                 break;
1796                         case ETH_TRANSCEIVER_TYPE_10G_LRM:
1797                                 phylink_set(if_caps, 10000baseLRM_Full);
1798                                 break;
1799                         case ETH_TRANSCEIVER_TYPE_10G_ER:
1800                                 phylink_set(if_caps, 10000baseR_FEC);
1801                                 break;
1802                         default:
1803                                 break;
1804                         }
1805
1806                 if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G)
1807                         phylink_set(if_caps, 20000baseKR2_Full);
1808
1809                 if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
1810                         switch (tcvr_type) {
1811                         case ETH_TRANSCEIVER_TYPE_25G_SR:
1812                         case ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_25G_SR:
1813                                 phylink_set(if_caps, 25000baseSR_Full);
1814                                 break;
1815                         default:
1816                                 break;
1817                         }
1818
1819                 if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
1820                         switch (tcvr_type) {
1821                         case ETH_TRANSCEIVER_TYPE_40G_LR4:
1822                         case ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_LR:
1823                         case ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_LR:
1824                                 phylink_set(if_caps, 40000baseLR4_Full);
1825                                 break;
1826                         case ETH_TRANSCEIVER_TYPE_40G_SR4:
1827                         case ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_SR:
1828                         case ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_SR:
1829                                 phylink_set(if_caps, 40000baseSR4_Full);
1830                                 break;
1831                         default:
1832                                 break;
1833                         }
1834
1835                 if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
1836                         phylink_set(if_caps, 50000baseKR2_Full);
1837
1838                 if (capability &
1839                     NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
1840                         switch (tcvr_type) {
1841                         case ETH_TRANSCEIVER_TYPE_100G_SR4:
1842                         case ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_SR:
1843                                 phylink_set(if_caps, 100000baseSR4_Full);
1844                                 break;
1845                         case ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_LR:
1846                                 phylink_set(if_caps, 100000baseLR4_ER4_Full);
1847                                 break;
1848                         default:
1849                                 break;
1850                         }
1851
1852                 break;
1853         case MEDIA_KR:
1854                 phylink_set(if_caps, Backplane);
1855
1856                 if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G)
1857                         phylink_set(if_caps, 20000baseKR2_Full);
1858                 if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
1859                         phylink_set(if_caps, 1000baseKX_Full);
1860                 if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
1861                         phylink_set(if_caps, 10000baseKR_Full);
1862                 if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
1863                         phylink_set(if_caps, 25000baseKR_Full);
1864                 if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
1865                         phylink_set(if_caps, 40000baseKR4_Full);
1866                 if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
1867                         phylink_set(if_caps, 50000baseKR2_Full);
1868                 if (capability &
1869                     NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
1870                         phylink_set(if_caps, 100000baseKR4_Full);
1871
1872                 break;
1873         case MEDIA_UNSPECIFIED:
1874         case MEDIA_NOT_PRESENT:
1875         default:
1876                 DP_VERBOSE(hwfn->cdev, QED_MSG_DEBUG,
1877                            "Unknown media and transceiver type;\n");
1878                 break;
1879         }
1880 }
1881
1882 static void qed_fill_link(struct qed_hwfn *hwfn,
1883                           struct qed_ptt *ptt,
1884                           struct qed_link_output *if_link)
1885 {
1886         struct qed_mcp_link_capabilities link_caps;
1887         struct qed_mcp_link_params params;
1888         struct qed_mcp_link_state link;
1889         u32 media_type;
1890
1891         memset(if_link, 0, sizeof(*if_link));
1892
1893         /* Prepare source inputs */
1894         if (qed_get_link_data(hwfn, &params, &link, &link_caps)) {
1895                 dev_warn(&hwfn->cdev->pdev->dev, "no link data available\n");
1896                 return;
1897         }
1898
1899         /* Set the link parameters to pass to protocol driver */
1900         if (link.link_up)
1901                 if_link->link_up = true;
1902
1903         /* TODO - at the moment assume supported and advertised speed equal */
1904         if (link_caps.default_speed_autoneg)
1905                 phylink_set(if_link->supported_caps, Autoneg);
1906         if (params.pause.autoneg ||
1907             (params.pause.forced_rx && params.pause.forced_tx))
1908                 phylink_set(if_link->supported_caps, Asym_Pause);
1909         if (params.pause.autoneg || params.pause.forced_rx ||
1910             params.pause.forced_tx)
1911                 phylink_set(if_link->supported_caps, Pause);
1912
1913         linkmode_copy(if_link->advertised_caps, if_link->supported_caps);
1914
1915         if (params.speed.autoneg)
1916                 phylink_set(if_link->advertised_caps, Autoneg);
1917         else
1918                 phylink_clear(if_link->advertised_caps, Autoneg);
1919
1920         /* Fill link advertised capability*/
1921         qed_fill_link_capability(hwfn, ptt, params.speed.advertised_speeds,
1922                                  if_link->advertised_caps);
1923         /* Fill link supported capability*/
1924         qed_fill_link_capability(hwfn, ptt, link_caps.speed_capabilities,
1925                                  if_link->supported_caps);
1926
1927         if (link.link_up)
1928                 if_link->speed = link.speed;
1929
1930         /* TODO - fill duplex properly */
1931         if_link->duplex = DUPLEX_FULL;
1932         qed_mcp_get_media_type(hwfn, ptt, &media_type);
1933         if_link->port = qed_get_port_type(media_type);
1934
1935         if_link->autoneg = params.speed.autoneg;
1936
1937         if (params.pause.autoneg)
1938                 if_link->pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE;
1939         if (params.pause.forced_rx)
1940                 if_link->pause_config |= QED_LINK_PAUSE_RX_ENABLE;
1941         if (params.pause.forced_tx)
1942                 if_link->pause_config |= QED_LINK_PAUSE_TX_ENABLE;
1943
1944         /* Link partner capabilities */
1945
1946         if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_1G_FD)
1947                 phylink_set(if_link->lp_caps, 1000baseT_Full);
1948         if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_10G)
1949                 phylink_set(if_link->lp_caps, 10000baseKR_Full);
1950         if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_20G)
1951                 phylink_set(if_link->lp_caps, 20000baseKR2_Full);
1952         if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_25G)
1953                 phylink_set(if_link->lp_caps, 25000baseKR_Full);
1954         if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_40G)
1955                 phylink_set(if_link->lp_caps, 40000baseLR4_Full);
1956         if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_50G)
1957                 phylink_set(if_link->lp_caps, 50000baseKR2_Full);
1958         if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_100G)
1959                 phylink_set(if_link->lp_caps, 100000baseKR4_Full);
1960
1961         if (link.an_complete)
1962                 phylink_set(if_link->lp_caps, Autoneg);
1963         if (link.partner_adv_pause)
1964                 phylink_set(if_link->lp_caps, Pause);
1965         if (link.partner_adv_pause == QED_LINK_PARTNER_ASYMMETRIC_PAUSE ||
1966             link.partner_adv_pause == QED_LINK_PARTNER_BOTH_PAUSE)
1967                 phylink_set(if_link->lp_caps, Asym_Pause);
1968
1969         if (link_caps.default_eee == QED_MCP_EEE_UNSUPPORTED) {
1970                 if_link->eee_supported = false;
1971         } else {
1972                 if_link->eee_supported = true;
1973                 if_link->eee_active = link.eee_active;
1974                 if_link->sup_caps = link_caps.eee_speed_caps;
1975                 /* MFW clears adv_caps on eee disable; use configured value */
1976                 if_link->eee.adv_caps = link.eee_adv_caps ? link.eee_adv_caps :
1977                                         params.eee.adv_caps;
1978                 if_link->eee.lp_adv_caps = link.eee_lp_adv_caps;
1979                 if_link->eee.enable = params.eee.enable;
1980                 if_link->eee.tx_lpi_enable = params.eee.tx_lpi_enable;
1981                 if_link->eee.tx_lpi_timer = params.eee.tx_lpi_timer;
1982         }
1983 }
1984
1985 static void qed_get_current_link(struct qed_dev *cdev,
1986                                  struct qed_link_output *if_link)
1987 {
1988         struct qed_hwfn *hwfn;
1989         struct qed_ptt *ptt;
1990         int i;
1991
1992         hwfn = &cdev->hwfns[0];
1993         if (IS_PF(cdev)) {
1994                 ptt = qed_ptt_acquire(hwfn);
1995                 if (ptt) {
1996                         qed_fill_link(hwfn, ptt, if_link);
1997                         qed_ptt_release(hwfn, ptt);
1998                 } else {
1999                         DP_NOTICE(hwfn, "Failed to fill link; No PTT\n");
2000                 }
2001         } else {
2002                 qed_fill_link(hwfn, NULL, if_link);
2003         }
2004
2005         for_each_hwfn(cdev, i)
2006                 qed_inform_vf_link_state(&cdev->hwfns[i]);
2007 }
2008
2009 void qed_link_update(struct qed_hwfn *hwfn, struct qed_ptt *ptt)
2010 {
2011         void *cookie = hwfn->cdev->ops_cookie;
2012         struct qed_common_cb_ops *op = hwfn->cdev->protocol_ops.common;
2013         struct qed_link_output if_link;
2014
2015         qed_fill_link(hwfn, ptt, &if_link);
2016         qed_inform_vf_link_state(hwfn);
2017
2018         if (IS_LEAD_HWFN(hwfn) && cookie)
2019                 op->link_update(cookie, &if_link);
2020 }
2021
2022 void qed_bw_update(struct qed_hwfn *hwfn, struct qed_ptt *ptt)
2023 {
2024         void *cookie = hwfn->cdev->ops_cookie;
2025         struct qed_common_cb_ops *op = hwfn->cdev->protocol_ops.common;
2026
2027         if (IS_LEAD_HWFN(hwfn) && cookie && op && op->bw_update)
2028                 op->bw_update(cookie);
2029 }
2030
2031 static int qed_drain(struct qed_dev *cdev)
2032 {
2033         struct qed_hwfn *hwfn;
2034         struct qed_ptt *ptt;
2035         int i, rc;
2036
2037         if (IS_VF(cdev))
2038                 return 0;
2039
2040         for_each_hwfn(cdev, i) {
2041                 hwfn = &cdev->hwfns[i];
2042                 ptt = qed_ptt_acquire(hwfn);
2043                 if (!ptt) {
2044                         DP_NOTICE(hwfn, "Failed to drain NIG; No PTT\n");
2045                         return -EBUSY;
2046                 }
2047                 rc = qed_mcp_drain(hwfn, ptt);
2048                 qed_ptt_release(hwfn, ptt);
2049                 if (rc)
2050                         return rc;
2051         }
2052
2053         return 0;
2054 }
2055
2056 static u32 qed_nvm_flash_image_access_crc(struct qed_dev *cdev,
2057                                           struct qed_nvm_image_att *nvm_image,
2058                                           u32 *crc)
2059 {
2060         u8 *buf = NULL;
2061         int rc;
2062
2063         /* Allocate a buffer for holding the nvram image */
2064         buf = kzalloc(nvm_image->length, GFP_KERNEL);
2065         if (!buf)
2066                 return -ENOMEM;
2067
2068         /* Read image into buffer */
2069         rc = qed_mcp_nvm_read(cdev, nvm_image->start_addr,
2070                               buf, nvm_image->length);
2071         if (rc) {
2072                 DP_ERR(cdev, "Failed reading image from nvm\n");
2073                 goto out;
2074         }
2075
2076         /* Convert the buffer into big-endian format (excluding the
2077          * closing 4 bytes of CRC).
2078          */
2079         cpu_to_be32_array((__force __be32 *)buf, (const u32 *)buf,
2080                           DIV_ROUND_UP(nvm_image->length - 4, 4));
2081
2082         /* Calc CRC for the "actual" image buffer, i.e. not including
2083          * the last 4 CRC bytes.
2084          */
2085         *crc = ~crc32(~0U, buf, nvm_image->length - 4);
2086         *crc = (__force u32)cpu_to_be32p(crc);
2087
2088 out:
2089         kfree(buf);
2090
2091         return rc;
2092 }
2093
2094 /* Binary file format -
2095  *     /----------------------------------------------------------------------\
2096  * 0B  |                       0x4 [command index]                            |
2097  * 4B  | image_type     | Options        |  Number of register settings       |
2098  * 8B  |                       Value                                          |
2099  * 12B |                       Mask                                           |
2100  * 16B |                       Offset                                         |
2101  *     \----------------------------------------------------------------------/
2102  * There can be several Value-Mask-Offset sets as specified by 'Number of...'.
2103  * Options - 0'b - Calculate & Update CRC for image
2104  */
2105 static int qed_nvm_flash_image_access(struct qed_dev *cdev, const u8 **data,
2106                                       bool *check_resp)
2107 {
2108         struct qed_nvm_image_att nvm_image;
2109         struct qed_hwfn *p_hwfn;
2110         bool is_crc = false;
2111         u32 image_type;
2112         int rc = 0, i;
2113         u16 len;
2114
2115         *data += 4;
2116         image_type = **data;
2117         p_hwfn = QED_LEADING_HWFN(cdev);
2118         for (i = 0; i < p_hwfn->nvm_info.num_images; i++)
2119                 if (image_type == p_hwfn->nvm_info.image_att[i].image_type)
2120                         break;
2121         if (i == p_hwfn->nvm_info.num_images) {
2122                 DP_ERR(cdev, "Failed to find nvram image of type %08x\n",
2123                        image_type);
2124                 return -ENOENT;
2125         }
2126
2127         nvm_image.start_addr = p_hwfn->nvm_info.image_att[i].nvm_start_addr;
2128         nvm_image.length = p_hwfn->nvm_info.image_att[i].len;
2129
2130         DP_VERBOSE(cdev, NETIF_MSG_DRV,
2131                    "Read image %02x; type = %08x; NVM [%08x,...,%08x]\n",
2132                    **data, image_type, nvm_image.start_addr,
2133                    nvm_image.start_addr + nvm_image.length - 1);
2134         (*data)++;
2135         is_crc = !!(**data & BIT(0));
2136         (*data)++;
2137         len = *((u16 *)*data);
2138         *data += 2;
2139         if (is_crc) {
2140                 u32 crc = 0;
2141
2142                 rc = qed_nvm_flash_image_access_crc(cdev, &nvm_image, &crc);
2143                 if (rc) {
2144                         DP_ERR(cdev, "Failed calculating CRC, rc = %d\n", rc);
2145                         goto exit;
2146                 }
2147
2148                 rc = qed_mcp_nvm_write(cdev, QED_NVM_WRITE_NVRAM,
2149                                        (nvm_image.start_addr +
2150                                         nvm_image.length - 4), (u8 *)&crc, 4);
2151                 if (rc)
2152                         DP_ERR(cdev, "Failed writing to %08x, rc = %d\n",
2153                                nvm_image.start_addr + nvm_image.length - 4, rc);
2154                 goto exit;
2155         }
2156
2157         /* Iterate over the values for setting */
2158         while (len) {
2159                 u32 offset, mask, value, cur_value;
2160                 u8 buf[4];
2161
2162                 value = *((u32 *)*data);
2163                 *data += 4;
2164                 mask = *((u32 *)*data);
2165                 *data += 4;
2166                 offset = *((u32 *)*data);
2167                 *data += 4;
2168
2169                 rc = qed_mcp_nvm_read(cdev, nvm_image.start_addr + offset, buf,
2170                                       4);
2171                 if (rc) {
2172                         DP_ERR(cdev, "Failed reading from %08x\n",
2173                                nvm_image.start_addr + offset);
2174                         goto exit;
2175                 }
2176
2177                 cur_value = le32_to_cpu(*((__le32 *)buf));
2178                 DP_VERBOSE(cdev, NETIF_MSG_DRV,
2179                            "NVM %08x: %08x -> %08x [Value %08x Mask %08x]\n",
2180                            nvm_image.start_addr + offset, cur_value,
2181                            (cur_value & ~mask) | (value & mask), value, mask);
2182                 value = (value & mask) | (cur_value & ~mask);
2183                 rc = qed_mcp_nvm_write(cdev, QED_NVM_WRITE_NVRAM,
2184                                        nvm_image.start_addr + offset,
2185                                        (u8 *)&value, 4);
2186                 if (rc) {
2187                         DP_ERR(cdev, "Failed writing to %08x\n",
2188                                nvm_image.start_addr + offset);
2189                         goto exit;
2190                 }
2191
2192                 len--;
2193         }
2194 exit:
2195         return rc;
2196 }
2197
2198 /* Binary file format -
2199  *     /----------------------------------------------------------------------\
2200  * 0B  |                       0x3 [command index]                            |
2201  * 4B  | b'0: check_response?   | b'1-31  reserved                            |
2202  * 8B  | File-type |                   reserved                               |
2203  * 12B |                    Image length in bytes                             |
2204  *     \----------------------------------------------------------------------/
2205  *     Start a new file of the provided type
2206  */
2207 static int qed_nvm_flash_image_file_start(struct qed_dev *cdev,
2208                                           const u8 **data, bool *check_resp)
2209 {
2210         u32 file_type, file_size = 0;
2211         int rc;
2212
2213         *data += 4;
2214         *check_resp = !!(**data & BIT(0));
2215         *data += 4;
2216         file_type = **data;
2217
2218         DP_VERBOSE(cdev, NETIF_MSG_DRV,
2219                    "About to start a new file of type %02x\n", file_type);
2220         if (file_type == DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_MBI) {
2221                 *data += 4;
2222                 file_size = *((u32 *)(*data));
2223         }
2224
2225         rc = qed_mcp_nvm_write(cdev, QED_PUT_FILE_BEGIN, file_type,
2226                                (u8 *)(&file_size), 4);
2227         *data += 4;
2228
2229         return rc;
2230 }
2231
2232 /* Binary file format -
2233  *     /----------------------------------------------------------------------\
2234  * 0B  |                       0x2 [command index]                            |
2235  * 4B  |                       Length in bytes                                |
2236  * 8B  | b'0: check_response?   | b'1-31  reserved                            |
2237  * 12B |                       Offset in bytes                                |
2238  * 16B |                       Data ...                                       |
2239  *     \----------------------------------------------------------------------/
2240  *     Write data as part of a file that was previously started. Data should be
2241  *     of length equal to that provided in the message
2242  */
2243 static int qed_nvm_flash_image_file_data(struct qed_dev *cdev,
2244                                          const u8 **data, bool *check_resp)
2245 {
2246         u32 offset, len;
2247         int rc;
2248
2249         *data += 4;
2250         len = *((u32 *)(*data));
2251         *data += 4;
2252         *check_resp = !!(**data & BIT(0));
2253         *data += 4;
2254         offset = *((u32 *)(*data));
2255         *data += 4;
2256
2257         DP_VERBOSE(cdev, NETIF_MSG_DRV,
2258                    "About to write File-data: %08x bytes to offset %08x\n",
2259                    len, offset);
2260
2261         rc = qed_mcp_nvm_write(cdev, QED_PUT_FILE_DATA, offset,
2262                                (char *)(*data), len);
2263         *data += len;
2264
2265         return rc;
2266 }
2267
2268 /* Binary file format [General header] -
2269  *     /----------------------------------------------------------------------\
2270  * 0B  |                       QED_NVM_SIGNATURE                              |
2271  * 4B  |                       Length in bytes                                |
2272  * 8B  | Highest command in this batchfile |          Reserved                |
2273  *     \----------------------------------------------------------------------/
2274  */
2275 static int qed_nvm_flash_image_validate(struct qed_dev *cdev,
2276                                         const struct firmware *image,
2277                                         const u8 **data)
2278 {
2279         u32 signature, len;
2280
2281         /* Check minimum size */
2282         if (image->size < 12) {
2283                 DP_ERR(cdev, "Image is too short [%08x]\n", (u32)image->size);
2284                 return -EINVAL;
2285         }
2286
2287         /* Check signature */
2288         signature = *((u32 *)(*data));
2289         if (signature != QED_NVM_SIGNATURE) {
2290                 DP_ERR(cdev, "Wrong signature '%08x'\n", signature);
2291                 return -EINVAL;
2292         }
2293
2294         *data += 4;
2295         /* Validate internal size equals the image-size */
2296         len = *((u32 *)(*data));
2297         if (len != image->size) {
2298                 DP_ERR(cdev, "Size mismatch: internal = %08x image = %08x\n",
2299                        len, (u32)image->size);
2300                 return -EINVAL;
2301         }
2302
2303         *data += 4;
2304         /* Make sure driver familiar with all commands necessary for this */
2305         if (*((u16 *)(*data)) >= QED_NVM_FLASH_CMD_NVM_MAX) {
2306                 DP_ERR(cdev, "File contains unsupported commands [Need %04x]\n",
2307                        *((u16 *)(*data)));
2308                 return -EINVAL;
2309         }
2310
2311         *data += 4;
2312
2313         return 0;
2314 }
2315
2316 /* Binary file format -
2317  *     /----------------------------------------------------------------------\
2318  * 0B  |                       0x5 [command index]                            |
2319  * 4B  | Number of config attributes     |          Reserved                  |
2320  * 4B  | Config ID                       | Entity ID      | Length            |
2321  * 4B  | Value                                                                |
2322  *     |                                                                      |
2323  *     \----------------------------------------------------------------------/
2324  * There can be several cfg_id-entity_id-Length-Value sets as specified by
2325  * 'Number of config attributes'.
2326  *
2327  * The API parses config attributes from the user provided buffer and flashes
2328  * them to the respective NVM path using Management FW inerface.
2329  */
2330 static int qed_nvm_flash_cfg_write(struct qed_dev *cdev, const u8 **data)
2331 {
2332         struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
2333         u8 entity_id, len, buf[32];
2334         bool need_nvm_init = true;
2335         struct qed_ptt *ptt;
2336         u16 cfg_id, count;
2337         int rc = 0, i;
2338         u32 flags;
2339
2340         ptt = qed_ptt_acquire(hwfn);
2341         if (!ptt)
2342                 return -EAGAIN;
2343
2344         /* NVM CFG ID attribute header */
2345         *data += 4;
2346         count = *((u16 *)*data);
2347         *data += 4;
2348
2349         DP_VERBOSE(cdev, NETIF_MSG_DRV,
2350                    "Read config ids: num_attrs = %0d\n", count);
2351         /* NVM CFG ID attributes. Start loop index from 1 to avoid additional
2352          * arithmetic operations in the implementation.
2353          */
2354         for (i = 1; i <= count; i++) {
2355                 cfg_id = *((u16 *)*data);
2356                 *data += 2;
2357                 entity_id = **data;
2358                 (*data)++;
2359                 len = **data;
2360                 (*data)++;
2361                 memcpy(buf, *data, len);
2362                 *data += len;
2363
2364                 flags = 0;
2365                 if (need_nvm_init) {
2366                         flags |= QED_NVM_CFG_OPTION_INIT;
2367                         need_nvm_init = false;
2368                 }
2369
2370                 /* Commit to flash and free the resources */
2371                 if (!(i % QED_NVM_CFG_MAX_ATTRS) || i == count) {
2372                         flags |= QED_NVM_CFG_OPTION_COMMIT |
2373                                  QED_NVM_CFG_OPTION_FREE;
2374                         need_nvm_init = true;
2375                 }
2376
2377                 if (entity_id)
2378                         flags |= QED_NVM_CFG_OPTION_ENTITY_SEL;
2379
2380                 DP_VERBOSE(cdev, NETIF_MSG_DRV,
2381                            "cfg_id = %d entity = %d len = %d\n", cfg_id,
2382                            entity_id, len);
2383                 rc = qed_mcp_nvm_set_cfg(hwfn, ptt, cfg_id, entity_id, flags,
2384                                          buf, len);
2385                 if (rc) {
2386                         DP_ERR(cdev, "Error %d configuring %d\n", rc, cfg_id);
2387                         break;
2388                 }
2389         }
2390
2391         qed_ptt_release(hwfn, ptt);
2392
2393         return rc;
2394 }
2395
2396 #define QED_MAX_NVM_BUF_LEN     32
2397 static int qed_nvm_flash_cfg_len(struct qed_dev *cdev, u32 cmd)
2398 {
2399         struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
2400         u8 buf[QED_MAX_NVM_BUF_LEN];
2401         struct qed_ptt *ptt;
2402         u32 len;
2403         int rc;
2404
2405         ptt = qed_ptt_acquire(hwfn);
2406         if (!ptt)
2407                 return QED_MAX_NVM_BUF_LEN;
2408
2409         rc = qed_mcp_nvm_get_cfg(hwfn, ptt, cmd, 0, QED_NVM_CFG_GET_FLAGS, buf,
2410                                  &len);
2411         if (rc || !len) {
2412                 DP_ERR(cdev, "Error %d reading %d\n", rc, cmd);
2413                 len = QED_MAX_NVM_BUF_LEN;
2414         }
2415
2416         qed_ptt_release(hwfn, ptt);
2417
2418         return len;
2419 }
2420
2421 static int qed_nvm_flash_cfg_read(struct qed_dev *cdev, u8 **data,
2422                                   u32 cmd, u32 entity_id)
2423 {
2424         struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
2425         struct qed_ptt *ptt;
2426         u32 flags, len;
2427         int rc = 0;
2428
2429         ptt = qed_ptt_acquire(hwfn);
2430         if (!ptt)
2431                 return -EAGAIN;
2432
2433         DP_VERBOSE(cdev, NETIF_MSG_DRV,
2434                    "Read config cmd = %d entity id %d\n", cmd, entity_id);
2435         flags = entity_id ? QED_NVM_CFG_GET_PF_FLAGS : QED_NVM_CFG_GET_FLAGS;
2436         rc = qed_mcp_nvm_get_cfg(hwfn, ptt, cmd, entity_id, flags, *data, &len);
2437         if (rc)
2438                 DP_ERR(cdev, "Error %d reading %d\n", rc, cmd);
2439
2440         qed_ptt_release(hwfn, ptt);
2441
2442         return rc;
2443 }
2444
2445 static int qed_nvm_flash(struct qed_dev *cdev, const char *name)
2446 {
2447         const struct firmware *image;
2448         const u8 *data, *data_end;
2449         u32 cmd_type;
2450         int rc;
2451
2452         rc = request_firmware(&image, name, &cdev->pdev->dev);
2453         if (rc) {
2454                 DP_ERR(cdev, "Failed to find '%s'\n", name);
2455                 return rc;
2456         }
2457
2458         DP_VERBOSE(cdev, NETIF_MSG_DRV,
2459                    "Flashing '%s' - firmware's data at %p, size is %08x\n",
2460                    name, image->data, (u32)image->size);
2461         data = image->data;
2462         data_end = data + image->size;
2463
2464         rc = qed_nvm_flash_image_validate(cdev, image, &data);
2465         if (rc)
2466                 goto exit;
2467
2468         while (data < data_end) {
2469                 bool check_resp = false;
2470
2471                 /* Parse the actual command */
2472                 cmd_type = *((u32 *)data);
2473                 switch (cmd_type) {
2474                 case QED_NVM_FLASH_CMD_FILE_DATA:
2475                         rc = qed_nvm_flash_image_file_data(cdev, &data,
2476                                                            &check_resp);
2477                         break;
2478                 case QED_NVM_FLASH_CMD_FILE_START:
2479                         rc = qed_nvm_flash_image_file_start(cdev, &data,
2480                                                             &check_resp);
2481                         break;
2482                 case QED_NVM_FLASH_CMD_NVM_CHANGE:
2483                         rc = qed_nvm_flash_image_access(cdev, &data,
2484                                                         &check_resp);
2485                         break;
2486                 case QED_NVM_FLASH_CMD_NVM_CFG_ID:
2487                         rc = qed_nvm_flash_cfg_write(cdev, &data);
2488                         break;
2489                 default:
2490                         DP_ERR(cdev, "Unknown command %08x\n", cmd_type);
2491                         rc = -EINVAL;
2492                         goto exit;
2493                 }
2494
2495                 if (rc) {
2496                         DP_ERR(cdev, "Command %08x failed\n", cmd_type);
2497                         goto exit;
2498                 }
2499
2500                 /* Check response if needed */
2501                 if (check_resp) {
2502                         u32 mcp_response = 0;
2503
2504                         if (qed_mcp_nvm_resp(cdev, (u8 *)&mcp_response)) {
2505                                 DP_ERR(cdev, "Failed getting MCP response\n");
2506                                 rc = -EINVAL;
2507                                 goto exit;
2508                         }
2509
2510                         switch (mcp_response & FW_MSG_CODE_MASK) {
2511                         case FW_MSG_CODE_OK:
2512                         case FW_MSG_CODE_NVM_OK:
2513                         case FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK:
2514                         case FW_MSG_CODE_PHY_OK:
2515                                 break;
2516                         default:
2517                                 DP_ERR(cdev, "MFW returns error: %08x\n",
2518                                        mcp_response);
2519                                 rc = -EINVAL;
2520                                 goto exit;
2521                         }
2522                 }
2523         }
2524
2525 exit:
2526         release_firmware(image);
2527
2528         return rc;
2529 }
2530
2531 static int qed_nvm_get_image(struct qed_dev *cdev, enum qed_nvm_images type,
2532                              u8 *buf, u16 len)
2533 {
2534         struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
2535
2536         return qed_mcp_get_nvm_image(hwfn, type, buf, len);
2537 }
2538
2539 void qed_schedule_recovery_handler(struct qed_hwfn *p_hwfn)
2540 {
2541         struct qed_common_cb_ops *ops = p_hwfn->cdev->protocol_ops.common;
2542         void *cookie = p_hwfn->cdev->ops_cookie;
2543
2544         if (ops && ops->schedule_recovery_handler)
2545                 ops->schedule_recovery_handler(cookie);
2546 }
2547
2548 static const char * const qed_hw_err_type_descr[] = {
2549         [QED_HW_ERR_FAN_FAIL]           = "Fan Failure",
2550         [QED_HW_ERR_MFW_RESP_FAIL]      = "MFW Response Failure",
2551         [QED_HW_ERR_HW_ATTN]            = "HW Attention",
2552         [QED_HW_ERR_DMAE_FAIL]          = "DMAE Failure",
2553         [QED_HW_ERR_RAMROD_FAIL]        = "Ramrod Failure",
2554         [QED_HW_ERR_FW_ASSERT]          = "FW Assertion",
2555         [QED_HW_ERR_LAST]               = "Unknown",
2556 };
2557
2558 void qed_hw_error_occurred(struct qed_hwfn *p_hwfn,
2559                            enum qed_hw_err_type err_type)
2560 {
2561         struct qed_common_cb_ops *ops = p_hwfn->cdev->protocol_ops.common;
2562         void *cookie = p_hwfn->cdev->ops_cookie;
2563         const char *err_str;
2564
2565         if (err_type > QED_HW_ERR_LAST)
2566                 err_type = QED_HW_ERR_LAST;
2567         err_str = qed_hw_err_type_descr[err_type];
2568
2569         DP_NOTICE(p_hwfn, "HW error occurred [%s]\n", err_str);
2570
2571         /* Call the HW error handler of the protocol driver.
2572          * If it is not available - perform a minimal handling of preventing
2573          * HW attentions from being reasserted.
2574          */
2575         if (ops && ops->schedule_hw_err_handler)
2576                 ops->schedule_hw_err_handler(cookie, err_type);
2577         else
2578                 qed_int_attn_clr_enable(p_hwfn->cdev, true);
2579 }
2580
2581 static int qed_set_coalesce(struct qed_dev *cdev, u16 rx_coal, u16 tx_coal,
2582                             void *handle)
2583 {
2584                 return qed_set_queue_coalesce(rx_coal, tx_coal, handle);
2585 }
2586
2587 static int qed_set_led(struct qed_dev *cdev, enum qed_led_mode mode)
2588 {
2589         struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
2590         struct qed_ptt *ptt;
2591         int status = 0;
2592
2593         ptt = qed_ptt_acquire(hwfn);
2594         if (!ptt)
2595                 return -EAGAIN;
2596
2597         status = qed_mcp_set_led(hwfn, ptt, mode);
2598
2599         qed_ptt_release(hwfn, ptt);
2600
2601         return status;
2602 }
2603
2604 static int qed_recovery_process(struct qed_dev *cdev)
2605 {
2606         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
2607         struct qed_ptt *p_ptt;
2608         int rc = 0;
2609
2610         p_ptt = qed_ptt_acquire(p_hwfn);
2611         if (!p_ptt)
2612                 return -EAGAIN;
2613
2614         rc = qed_start_recovery_process(p_hwfn, p_ptt);
2615
2616         qed_ptt_release(p_hwfn, p_ptt);
2617
2618         return rc;
2619 }
2620
2621 static int qed_update_wol(struct qed_dev *cdev, bool enabled)
2622 {
2623         struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
2624         struct qed_ptt *ptt;
2625         int rc = 0;
2626
2627         if (IS_VF(cdev))
2628                 return 0;
2629
2630         ptt = qed_ptt_acquire(hwfn);
2631         if (!ptt)
2632                 return -EAGAIN;
2633
2634         rc = qed_mcp_ov_update_wol(hwfn, ptt, enabled ? QED_OV_WOL_ENABLED
2635                                    : QED_OV_WOL_DISABLED);
2636         if (rc)
2637                 goto out;
2638         rc = qed_mcp_ov_update_current_config(hwfn, ptt, QED_OV_CLIENT_DRV);
2639
2640 out:
2641         qed_ptt_release(hwfn, ptt);
2642         return rc;
2643 }
2644
2645 static int qed_update_drv_state(struct qed_dev *cdev, bool active)
2646 {
2647         struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
2648         struct qed_ptt *ptt;
2649         int status = 0;
2650
2651         if (IS_VF(cdev))
2652                 return 0;
2653
2654         ptt = qed_ptt_acquire(hwfn);
2655         if (!ptt)
2656                 return -EAGAIN;
2657
2658         status = qed_mcp_ov_update_driver_state(hwfn, ptt, active ?
2659                                                 QED_OV_DRIVER_STATE_ACTIVE :
2660                                                 QED_OV_DRIVER_STATE_DISABLED);
2661
2662         qed_ptt_release(hwfn, ptt);
2663
2664         return status;
2665 }
2666
2667 static int qed_update_mac(struct qed_dev *cdev, u8 *mac)
2668 {
2669         struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
2670         struct qed_ptt *ptt;
2671         int status = 0;
2672
2673         if (IS_VF(cdev))
2674                 return 0;
2675
2676         ptt = qed_ptt_acquire(hwfn);
2677         if (!ptt)
2678                 return -EAGAIN;
2679
2680         status = qed_mcp_ov_update_mac(hwfn, ptt, mac);
2681         if (status)
2682                 goto out;
2683
2684         status = qed_mcp_ov_update_current_config(hwfn, ptt, QED_OV_CLIENT_DRV);
2685
2686 out:
2687         qed_ptt_release(hwfn, ptt);
2688         return status;
2689 }
2690
2691 static int qed_update_mtu(struct qed_dev *cdev, u16 mtu)
2692 {
2693         struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
2694         struct qed_ptt *ptt;
2695         int status = 0;
2696
2697         if (IS_VF(cdev))
2698                 return 0;
2699
2700         ptt = qed_ptt_acquire(hwfn);
2701         if (!ptt)
2702                 return -EAGAIN;
2703
2704         status = qed_mcp_ov_update_mtu(hwfn, ptt, mtu);
2705         if (status)
2706                 goto out;
2707
2708         status = qed_mcp_ov_update_current_config(hwfn, ptt, QED_OV_CLIENT_DRV);
2709
2710 out:
2711         qed_ptt_release(hwfn, ptt);
2712         return status;
2713 }
2714
2715 static int qed_read_module_eeprom(struct qed_dev *cdev, char *buf,
2716                                   u8 dev_addr, u32 offset, u32 len)
2717 {
2718         struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
2719         struct qed_ptt *ptt;
2720         int rc = 0;
2721
2722         if (IS_VF(cdev))
2723                 return 0;
2724
2725         ptt = qed_ptt_acquire(hwfn);
2726         if (!ptt)
2727                 return -EAGAIN;
2728
2729         rc = qed_mcp_phy_sfp_read(hwfn, ptt, MFW_PORT(hwfn), dev_addr,
2730                                   offset, len, buf);
2731
2732         qed_ptt_release(hwfn, ptt);
2733
2734         return rc;
2735 }
2736
2737 static int qed_set_grc_config(struct qed_dev *cdev, u32 cfg_id, u32 val)
2738 {
2739         struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
2740         struct qed_ptt *ptt;
2741         int rc = 0;
2742
2743         if (IS_VF(cdev))
2744                 return 0;
2745
2746         ptt = qed_ptt_acquire(hwfn);
2747         if (!ptt)
2748                 return -EAGAIN;
2749
2750         rc = qed_dbg_grc_config(hwfn, cfg_id, val);
2751
2752         qed_ptt_release(hwfn, ptt);
2753
2754         return rc;
2755 }
2756
2757 static u8 qed_get_affin_hwfn_idx(struct qed_dev *cdev)
2758 {
2759         return QED_AFFIN_HWFN_IDX(cdev);
2760 }
2761
2762 static struct qed_selftest_ops qed_selftest_ops_pass = {
2763         .selftest_memory = &qed_selftest_memory,
2764         .selftest_interrupt = &qed_selftest_interrupt,
2765         .selftest_register = &qed_selftest_register,
2766         .selftest_clock = &qed_selftest_clock,
2767         .selftest_nvram = &qed_selftest_nvram,
2768 };
2769
2770 const struct qed_common_ops qed_common_ops_pass = {
2771         .selftest = &qed_selftest_ops_pass,
2772         .probe = &qed_probe,
2773         .remove = &qed_remove,
2774         .set_power_state = &qed_set_power_state,
2775         .set_name = &qed_set_name,
2776         .update_pf_params = &qed_update_pf_params,
2777         .slowpath_start = &qed_slowpath_start,
2778         .slowpath_stop = &qed_slowpath_stop,
2779         .set_fp_int = &qed_set_int_fp,
2780         .get_fp_int = &qed_get_int_fp,
2781         .sb_init = &qed_sb_init,
2782         .sb_release = &qed_sb_release,
2783         .simd_handler_config = &qed_simd_handler_config,
2784         .simd_handler_clean = &qed_simd_handler_clean,
2785         .dbg_grc = &qed_dbg_grc,
2786         .dbg_grc_size = &qed_dbg_grc_size,
2787         .can_link_change = &qed_can_link_change,
2788         .set_link = &qed_set_link,
2789         .get_link = &qed_get_current_link,
2790         .drain = &qed_drain,
2791         .update_msglvl = &qed_init_dp,
2792         .dbg_all_data = &qed_dbg_all_data,
2793         .dbg_all_data_size = &qed_dbg_all_data_size,
2794         .chain_alloc = &qed_chain_alloc,
2795         .chain_free = &qed_chain_free,
2796         .nvm_flash = &qed_nvm_flash,
2797         .nvm_get_image = &qed_nvm_get_image,
2798         .set_coalesce = &qed_set_coalesce,
2799         .set_led = &qed_set_led,
2800         .recovery_process = &qed_recovery_process,
2801         .recovery_prolog = &qed_recovery_prolog,
2802         .attn_clr_enable = &qed_int_attn_clr_enable,
2803         .update_drv_state = &qed_update_drv_state,
2804         .update_mac = &qed_update_mac,
2805         .update_mtu = &qed_update_mtu,
2806         .update_wol = &qed_update_wol,
2807         .db_recovery_add = &qed_db_recovery_add,
2808         .db_recovery_del = &qed_db_recovery_del,
2809         .read_module_eeprom = &qed_read_module_eeprom,
2810         .get_affin_hwfn_idx = &qed_get_affin_hwfn_idx,
2811         .read_nvm_cfg = &qed_nvm_flash_cfg_read,
2812         .read_nvm_cfg_len = &qed_nvm_flash_cfg_len,
2813         .set_grc_config = &qed_set_grc_config,
2814 };
2815
2816 void qed_get_protocol_stats(struct qed_dev *cdev,
2817                             enum qed_mcp_protocol_type type,
2818                             union qed_mcp_protocol_stats *stats)
2819 {
2820         struct qed_eth_stats eth_stats;
2821
2822         memset(stats, 0, sizeof(*stats));
2823
2824         switch (type) {
2825         case QED_MCP_LAN_STATS:
2826                 qed_get_vport_stats(cdev, &eth_stats);
2827                 stats->lan_stats.ucast_rx_pkts =
2828                                         eth_stats.common.rx_ucast_pkts;
2829                 stats->lan_stats.ucast_tx_pkts =
2830                                         eth_stats.common.tx_ucast_pkts;
2831                 stats->lan_stats.fcs_err = -1;
2832                 break;
2833         case QED_MCP_FCOE_STATS:
2834                 qed_get_protocol_stats_fcoe(cdev, &stats->fcoe_stats);
2835                 break;
2836         case QED_MCP_ISCSI_STATS:
2837                 qed_get_protocol_stats_iscsi(cdev, &stats->iscsi_stats);
2838                 break;
2839         default:
2840                 DP_VERBOSE(cdev, QED_MSG_SP,
2841                            "Invalid protocol type = %d\n", type);
2842                 return;
2843         }
2844 }
2845
2846 int qed_mfw_tlv_req(struct qed_hwfn *hwfn)
2847 {
2848         DP_VERBOSE(hwfn->cdev, NETIF_MSG_DRV,
2849                    "Scheduling slowpath task [Flag: %d]\n",
2850                    QED_SLOWPATH_MFW_TLV_REQ);
2851         smp_mb__before_atomic();
2852         set_bit(QED_SLOWPATH_MFW_TLV_REQ, &hwfn->slowpath_task_flags);
2853         smp_mb__after_atomic();
2854         queue_delayed_work(hwfn->slowpath_wq, &hwfn->slowpath_task, 0);
2855
2856         return 0;
2857 }
2858
2859 static void
2860 qed_fill_generic_tlv_data(struct qed_dev *cdev, struct qed_mfw_tlv_generic *tlv)
2861 {
2862         struct qed_common_cb_ops *op = cdev->protocol_ops.common;
2863         struct qed_eth_stats_common *p_common;
2864         struct qed_generic_tlvs gen_tlvs;
2865         struct qed_eth_stats stats;
2866         int i;
2867
2868         memset(&gen_tlvs, 0, sizeof(gen_tlvs));
2869         op->get_generic_tlv_data(cdev->ops_cookie, &gen_tlvs);
2870
2871         if (gen_tlvs.feat_flags & QED_TLV_IP_CSUM)
2872                 tlv->flags.ipv4_csum_offload = true;
2873         if (gen_tlvs.feat_flags & QED_TLV_LSO)
2874                 tlv->flags.lso_supported = true;
2875         tlv->flags.b_set = true;
2876
2877         for (i = 0; i < QED_TLV_MAC_COUNT; i++) {
2878                 if (is_valid_ether_addr(gen_tlvs.mac[i])) {
2879                         ether_addr_copy(tlv->mac[i], gen_tlvs.mac[i]);
2880                         tlv->mac_set[i] = true;
2881                 }
2882         }
2883
2884         qed_get_vport_stats(cdev, &stats);
2885         p_common = &stats.common;
2886         tlv->rx_frames = p_common->rx_ucast_pkts + p_common->rx_mcast_pkts +
2887                          p_common->rx_bcast_pkts;
2888         tlv->rx_frames_set = true;
2889         tlv->rx_bytes = p_common->rx_ucast_bytes + p_common->rx_mcast_bytes +
2890                         p_common->rx_bcast_bytes;
2891         tlv->rx_bytes_set = true;
2892         tlv->tx_frames = p_common->tx_ucast_pkts + p_common->tx_mcast_pkts +
2893                          p_common->tx_bcast_pkts;
2894         tlv->tx_frames_set = true;
2895         tlv->tx_bytes = p_common->tx_ucast_bytes + p_common->tx_mcast_bytes +
2896                         p_common->tx_bcast_bytes;
2897         tlv->rx_bytes_set = true;
2898 }
2899
2900 int qed_mfw_fill_tlv_data(struct qed_hwfn *hwfn, enum qed_mfw_tlv_type type,
2901                           union qed_mfw_tlv_data *tlv_buf)
2902 {
2903         struct qed_dev *cdev = hwfn->cdev;
2904         struct qed_common_cb_ops *ops;
2905
2906         ops = cdev->protocol_ops.common;
2907         if (!ops || !ops->get_protocol_tlv_data || !ops->get_generic_tlv_data) {
2908                 DP_NOTICE(hwfn, "Can't collect TLV management info\n");
2909                 return -EINVAL;
2910         }
2911
2912         switch (type) {
2913         case QED_MFW_TLV_GENERIC:
2914                 qed_fill_generic_tlv_data(hwfn->cdev, &tlv_buf->generic);
2915                 break;
2916         case QED_MFW_TLV_ETH:
2917                 ops->get_protocol_tlv_data(cdev->ops_cookie, &tlv_buf->eth);
2918                 break;
2919         case QED_MFW_TLV_FCOE:
2920                 ops->get_protocol_tlv_data(cdev->ops_cookie, &tlv_buf->fcoe);
2921                 break;
2922         case QED_MFW_TLV_ISCSI:
2923                 ops->get_protocol_tlv_data(cdev->ops_cookie, &tlv_buf->iscsi);
2924                 break;
2925         default:
2926                 break;
2927         }
2928
2929         return 0;
2930 }