1 /* QLogic qed NIC Driver
2 * Copyright (c) 2015-2017 QLogic Corporation
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and /or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/types.h>
34 #include <asm/byteorder.h>
36 #include <linux/bitops.h>
37 #include <linux/delay.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/errno.h>
40 #include <linux/interrupt.h>
41 #include <linux/kernel.h>
42 #include <linux/pci.h>
43 #include <linux/slab.h>
44 #include <linux/string.h>
48 #include "qed_init_ops.h"
51 #include "qed_reg_addr.h"
53 #include "qed_sriov.h"
57 qed_int_comp_cb_t comp_cb;
61 struct qed_sb_sp_info {
62 struct qed_sb_info sb_info;
64 /* per protocol index data */
65 struct qed_pi_info pi_info_arr[PIS_PER_SB_E4];
68 enum qed_attention_type {
73 #define SB_ATTN_ALIGNED_SIZE(p_hwfn) \
74 ALIGNED_TYPE_SIZE(struct atten_status_block, p_hwfn)
76 struct aeu_invert_reg_bit {
79 #define ATTENTION_PARITY (1 << 0)
81 #define ATTENTION_LENGTH_MASK (0x00000ff0)
82 #define ATTENTION_LENGTH_SHIFT (4)
83 #define ATTENTION_LENGTH(flags) (((flags) & ATTENTION_LENGTH_MASK) >> \
84 ATTENTION_LENGTH_SHIFT)
85 #define ATTENTION_SINGLE BIT(ATTENTION_LENGTH_SHIFT)
86 #define ATTENTION_PAR (ATTENTION_SINGLE | ATTENTION_PARITY)
87 #define ATTENTION_PAR_INT ((2 << ATTENTION_LENGTH_SHIFT) | \
90 /* Multiple bits start with this offset */
91 #define ATTENTION_OFFSET_MASK (0x000ff000)
92 #define ATTENTION_OFFSET_SHIFT (12)
94 #define ATTENTION_BB_MASK (0x00700000)
95 #define ATTENTION_BB_SHIFT (20)
96 #define ATTENTION_BB(value) (value << ATTENTION_BB_SHIFT)
97 #define ATTENTION_BB_DIFFERENT BIT(23)
101 /* Callback to call if attention will be triggered */
102 int (*cb)(struct qed_hwfn *p_hwfn);
104 enum block_id block_index;
107 struct aeu_invert_reg {
108 struct aeu_invert_reg_bit bits[32];
111 #define MAX_ATTN_GRPS (8)
112 #define NUM_ATTN_REGS (9)
114 /* Specific HW attention callbacks */
115 static int qed_mcp_attn_cb(struct qed_hwfn *p_hwfn)
117 u32 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, MCP_REG_CPU_STATE);
119 /* This might occur on certain instances; Log it once then mask it */
120 DP_INFO(p_hwfn->cdev, "MCP_REG_CPU_STATE: %08x - Masking...\n",
122 qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, MCP_REG_CPU_EVENT_MASK,
128 #define QED_PSWHST_ATTENTION_INCORRECT_ACCESS (0x1)
129 #define ATTENTION_INCORRECT_ACCESS_WR_MASK (0x1)
130 #define ATTENTION_INCORRECT_ACCESS_WR_SHIFT (0)
131 #define ATTENTION_INCORRECT_ACCESS_CLIENT_MASK (0xf)
132 #define ATTENTION_INCORRECT_ACCESS_CLIENT_SHIFT (1)
133 #define ATTENTION_INCORRECT_ACCESS_VF_VALID_MASK (0x1)
134 #define ATTENTION_INCORRECT_ACCESS_VF_VALID_SHIFT (5)
135 #define ATTENTION_INCORRECT_ACCESS_VF_ID_MASK (0xff)
136 #define ATTENTION_INCORRECT_ACCESS_VF_ID_SHIFT (6)
137 #define ATTENTION_INCORRECT_ACCESS_PF_ID_MASK (0xf)
138 #define ATTENTION_INCORRECT_ACCESS_PF_ID_SHIFT (14)
139 #define ATTENTION_INCORRECT_ACCESS_BYTE_EN_MASK (0xff)
140 #define ATTENTION_INCORRECT_ACCESS_BYTE_EN_SHIFT (18)
141 static int qed_pswhst_attn_cb(struct qed_hwfn *p_hwfn)
143 u32 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
144 PSWHST_REG_INCORRECT_ACCESS_VALID);
146 if (tmp & QED_PSWHST_ATTENTION_INCORRECT_ACCESS) {
147 u32 addr, data, length;
149 addr = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
150 PSWHST_REG_INCORRECT_ACCESS_ADDRESS);
151 data = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
152 PSWHST_REG_INCORRECT_ACCESS_DATA);
153 length = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
154 PSWHST_REG_INCORRECT_ACCESS_LENGTH);
156 DP_INFO(p_hwfn->cdev,
157 "Incorrect access to %08x of length %08x - PF [%02x] VF [%04x] [valid %02x] client [%02x] write [%02x] Byte-Enable [%04x] [%08x]\n",
159 (u8) GET_FIELD(data, ATTENTION_INCORRECT_ACCESS_PF_ID),
160 (u8) GET_FIELD(data, ATTENTION_INCORRECT_ACCESS_VF_ID),
162 ATTENTION_INCORRECT_ACCESS_VF_VALID),
164 ATTENTION_INCORRECT_ACCESS_CLIENT),
165 (u8) GET_FIELD(data, ATTENTION_INCORRECT_ACCESS_WR),
167 ATTENTION_INCORRECT_ACCESS_BYTE_EN),
174 #define QED_GRC_ATTENTION_VALID_BIT (1 << 0)
175 #define QED_GRC_ATTENTION_ADDRESS_MASK (0x7fffff)
176 #define QED_GRC_ATTENTION_ADDRESS_SHIFT (0)
177 #define QED_GRC_ATTENTION_RDWR_BIT (1 << 23)
178 #define QED_GRC_ATTENTION_MASTER_MASK (0xf)
179 #define QED_GRC_ATTENTION_MASTER_SHIFT (24)
180 #define QED_GRC_ATTENTION_PF_MASK (0xf)
181 #define QED_GRC_ATTENTION_PF_SHIFT (0)
182 #define QED_GRC_ATTENTION_VF_MASK (0xff)
183 #define QED_GRC_ATTENTION_VF_SHIFT (4)
184 #define QED_GRC_ATTENTION_PRIV_MASK (0x3)
185 #define QED_GRC_ATTENTION_PRIV_SHIFT (14)
186 #define QED_GRC_ATTENTION_PRIV_VF (0)
187 static const char *attn_master_to_str(u8 master)
190 case 1: return "PXP";
191 case 2: return "MCP";
192 case 3: return "MSDM";
193 case 4: return "PSDM";
194 case 5: return "YSDM";
195 case 6: return "USDM";
196 case 7: return "TSDM";
197 case 8: return "XSDM";
198 case 9: return "DBU";
199 case 10: return "DMAE";
205 static int qed_grc_attn_cb(struct qed_hwfn *p_hwfn)
209 /* We've already cleared the timeout interrupt register, so we learn
210 * of interrupts via the validity register
212 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
213 GRC_REG_TIMEOUT_ATTN_ACCESS_VALID);
214 if (!(tmp & QED_GRC_ATTENTION_VALID_BIT))
217 /* Read the GRC timeout information */
218 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
219 GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_0);
220 tmp2 = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
221 GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_1);
223 DP_INFO(p_hwfn->cdev,
224 "GRC timeout [%08x:%08x] - %s Address [%08x] [Master %s] [PF: %02x %s %02x]\n",
226 (tmp & QED_GRC_ATTENTION_RDWR_BIT) ? "Write to" : "Read from",
227 GET_FIELD(tmp, QED_GRC_ATTENTION_ADDRESS) << 2,
228 attn_master_to_str(GET_FIELD(tmp, QED_GRC_ATTENTION_MASTER)),
229 GET_FIELD(tmp2, QED_GRC_ATTENTION_PF),
230 (GET_FIELD(tmp2, QED_GRC_ATTENTION_PRIV) ==
231 QED_GRC_ATTENTION_PRIV_VF) ? "VF" : "(Irrelevant)",
232 GET_FIELD(tmp2, QED_GRC_ATTENTION_VF));
235 /* Regardles of anything else, clean the validity bit */
236 qed_wr(p_hwfn, p_hwfn->p_dpc_ptt,
237 GRC_REG_TIMEOUT_ATTN_ACCESS_VALID, 0);
241 #define PGLUE_ATTENTION_VALID (1 << 29)
242 #define PGLUE_ATTENTION_RD_VALID (1 << 26)
243 #define PGLUE_ATTENTION_DETAILS_PFID_MASK (0xf)
244 #define PGLUE_ATTENTION_DETAILS_PFID_SHIFT (20)
245 #define PGLUE_ATTENTION_DETAILS_VF_VALID_MASK (0x1)
246 #define PGLUE_ATTENTION_DETAILS_VF_VALID_SHIFT (19)
247 #define PGLUE_ATTENTION_DETAILS_VFID_MASK (0xff)
248 #define PGLUE_ATTENTION_DETAILS_VFID_SHIFT (24)
249 #define PGLUE_ATTENTION_DETAILS2_WAS_ERR_MASK (0x1)
250 #define PGLUE_ATTENTION_DETAILS2_WAS_ERR_SHIFT (21)
251 #define PGLUE_ATTENTION_DETAILS2_BME_MASK (0x1)
252 #define PGLUE_ATTENTION_DETAILS2_BME_SHIFT (22)
253 #define PGLUE_ATTENTION_DETAILS2_FID_EN_MASK (0x1)
254 #define PGLUE_ATTENTION_DETAILS2_FID_EN_SHIFT (23)
255 #define PGLUE_ATTENTION_ICPL_VALID (1 << 23)
256 #define PGLUE_ATTENTION_ZLR_VALID (1 << 25)
257 #define PGLUE_ATTENTION_ILT_VALID (1 << 23)
259 int qed_pglueb_rbc_attn_handler(struct qed_hwfn *p_hwfn,
260 struct qed_ptt *p_ptt)
264 tmp = qed_rd(p_hwfn, p_ptt, PGLUE_B_REG_TX_ERR_WR_DETAILS2);
265 if (tmp & PGLUE_ATTENTION_VALID) {
266 u32 addr_lo, addr_hi, details;
268 addr_lo = qed_rd(p_hwfn, p_ptt,
269 PGLUE_B_REG_TX_ERR_WR_ADD_31_0);
270 addr_hi = qed_rd(p_hwfn, p_ptt,
271 PGLUE_B_REG_TX_ERR_WR_ADD_63_32);
272 details = qed_rd(p_hwfn, p_ptt,
273 PGLUE_B_REG_TX_ERR_WR_DETAILS);
276 "Illegal write by chip to [%08x:%08x] blocked.\n"
277 "Details: %08x [PFID %02x, VFID %02x, VF_VALID %02x]\n"
278 "Details2 %08x [Was_error %02x BME deassert %02x FID_enable deassert %02x]\n",
279 addr_hi, addr_lo, details,
280 (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_PFID),
281 (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_VFID),
283 PGLUE_ATTENTION_DETAILS_VF_VALID) ? 1 : 0,
286 PGLUE_ATTENTION_DETAILS2_WAS_ERR) ? 1 : 0,
288 PGLUE_ATTENTION_DETAILS2_BME) ? 1 : 0,
290 PGLUE_ATTENTION_DETAILS2_FID_EN) ? 1 : 0);
293 tmp = qed_rd(p_hwfn, p_ptt, PGLUE_B_REG_TX_ERR_RD_DETAILS2);
294 if (tmp & PGLUE_ATTENTION_RD_VALID) {
295 u32 addr_lo, addr_hi, details;
297 addr_lo = qed_rd(p_hwfn, p_ptt,
298 PGLUE_B_REG_TX_ERR_RD_ADD_31_0);
299 addr_hi = qed_rd(p_hwfn, p_ptt,
300 PGLUE_B_REG_TX_ERR_RD_ADD_63_32);
301 details = qed_rd(p_hwfn, p_ptt,
302 PGLUE_B_REG_TX_ERR_RD_DETAILS);
305 "Illegal read by chip from [%08x:%08x] blocked.\n"
306 "Details: %08x [PFID %02x, VFID %02x, VF_VALID %02x]\n"
307 "Details2 %08x [Was_error %02x BME deassert %02x FID_enable deassert %02x]\n",
308 addr_hi, addr_lo, details,
309 (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_PFID),
310 (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_VFID),
312 PGLUE_ATTENTION_DETAILS_VF_VALID) ? 1 : 0,
315 PGLUE_ATTENTION_DETAILS2_WAS_ERR) ? 1 : 0,
317 PGLUE_ATTENTION_DETAILS2_BME) ? 1 : 0,
319 PGLUE_ATTENTION_DETAILS2_FID_EN) ? 1 : 0);
322 tmp = qed_rd(p_hwfn, p_ptt, PGLUE_B_REG_TX_ERR_WR_DETAILS_ICPL);
323 if (tmp & PGLUE_ATTENTION_ICPL_VALID)
324 DP_NOTICE(p_hwfn, "ICPL error - %08x\n", tmp);
326 tmp = qed_rd(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_ZLR_ERR_DETAILS);
327 if (tmp & PGLUE_ATTENTION_ZLR_VALID) {
328 u32 addr_hi, addr_lo;
330 addr_lo = qed_rd(p_hwfn, p_ptt,
331 PGLUE_B_REG_MASTER_ZLR_ERR_ADD_31_0);
332 addr_hi = qed_rd(p_hwfn, p_ptt,
333 PGLUE_B_REG_MASTER_ZLR_ERR_ADD_63_32);
335 DP_NOTICE(p_hwfn, "ZLR error - %08x [Address %08x:%08x]\n",
336 tmp, addr_hi, addr_lo);
339 tmp = qed_rd(p_hwfn, p_ptt, PGLUE_B_REG_VF_ILT_ERR_DETAILS2);
340 if (tmp & PGLUE_ATTENTION_ILT_VALID) {
341 u32 addr_hi, addr_lo, details;
343 addr_lo = qed_rd(p_hwfn, p_ptt,
344 PGLUE_B_REG_VF_ILT_ERR_ADD_31_0);
345 addr_hi = qed_rd(p_hwfn, p_ptt,
346 PGLUE_B_REG_VF_ILT_ERR_ADD_63_32);
347 details = qed_rd(p_hwfn, p_ptt,
348 PGLUE_B_REG_VF_ILT_ERR_DETAILS);
351 "ILT error - Details %08x Details2 %08x [Address %08x:%08x]\n",
352 details, tmp, addr_hi, addr_lo);
355 /* Clear the indications */
356 qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_LATCHED_ERRORS_CLR, BIT(2));
361 static int qed_pglueb_rbc_attn_cb(struct qed_hwfn *p_hwfn)
363 return qed_pglueb_rbc_attn_handler(p_hwfn, p_hwfn->p_dpc_ptt);
366 #define QED_DORQ_ATTENTION_REASON_MASK (0xfffff)
367 #define QED_DORQ_ATTENTION_OPAQUE_MASK (0xffff)
368 #define QED_DORQ_ATTENTION_OPAQUE_SHIFT (0x0)
369 #define QED_DORQ_ATTENTION_SIZE_MASK (0x7f)
370 #define QED_DORQ_ATTENTION_SIZE_SHIFT (16)
372 #define QED_DB_REC_COUNT 1000
373 #define QED_DB_REC_INTERVAL 100
375 static int qed_db_rec_flush_queue(struct qed_hwfn *p_hwfn,
376 struct qed_ptt *p_ptt)
378 u32 count = QED_DB_REC_COUNT;
381 /* Flush any pending (e)dpms as they may never arrive */
382 qed_wr(p_hwfn, p_ptt, DORQ_REG_DPM_FORCE_ABORT, 0x1);
384 /* wait for usage to zero or count to run out. This is necessary since
385 * EDPM doorbell transactions can take multiple 64b cycles, and as such
386 * can "split" over the pci. Possibly, the doorbell drop can happen with
387 * half an EDPM in the queue and other half dropped. Another EDPM
388 * doorbell to the same address (from doorbell recovery mechanism or
389 * from the doorbelling entity) could have first half dropped and second
390 * half interpreted as continuation of the first. To prevent such
391 * malformed doorbells from reaching the device, flush the queue before
392 * releasing the overflow sticky indication.
394 while (count-- && usage) {
395 usage = qed_rd(p_hwfn, p_ptt, DORQ_REG_PF_USAGE_CNT);
396 udelay(QED_DB_REC_INTERVAL);
399 /* should have been depleted by now */
401 DP_NOTICE(p_hwfn->cdev,
402 "DB recovery: doorbell usage failed to zero after %d usec. usage was %x\n",
403 QED_DB_REC_INTERVAL * QED_DB_REC_COUNT, usage);
410 int qed_db_rec_handler(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
412 u32 attn_ovfl, cur_ovfl;
415 attn_ovfl = test_and_clear_bit(QED_OVERFLOW_BIT,
416 &p_hwfn->db_recovery_info.overflow);
417 cur_ovfl = qed_rd(p_hwfn, p_ptt, DORQ_REG_PF_OVFL_STICKY);
418 if (!cur_ovfl && !attn_ovfl)
421 DP_NOTICE(p_hwfn, "PF Overflow sticky: attn %u current %u\n",
422 attn_ovfl, cur_ovfl);
424 if (cur_ovfl && !p_hwfn->db_bar_no_edpm) {
425 rc = qed_db_rec_flush_queue(p_hwfn, p_ptt);
430 /* Release overflow sticky indication (stop silently dropping everything) */
431 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_OVFL_STICKY, 0x0);
433 /* Repeat all last doorbells (doorbell drop recovery) */
434 qed_db_recovery_execute(p_hwfn);
439 static void qed_dorq_attn_overflow(struct qed_hwfn *p_hwfn)
441 struct qed_ptt *p_ptt = p_hwfn->p_dpc_ptt;
445 overflow = qed_rd(p_hwfn, p_ptt, DORQ_REG_PF_OVFL_STICKY);
449 /* Run PF doorbell recovery in next periodic handler */
450 set_bit(QED_OVERFLOW_BIT, &p_hwfn->db_recovery_info.overflow);
452 if (!p_hwfn->db_bar_no_edpm) {
453 rc = qed_db_rec_flush_queue(p_hwfn, p_ptt);
458 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_OVFL_STICKY, 0x0);
460 /* Schedule the handler even if overflow was not detected */
461 qed_periodic_db_rec_start(p_hwfn);
464 static int qed_dorq_attn_int_sts(struct qed_hwfn *p_hwfn)
466 u32 int_sts, first_drop_reason, details, address, all_drops_reason;
467 struct qed_ptt *p_ptt = p_hwfn->p_dpc_ptt;
469 /* int_sts may be zero since all PFs were interrupted for doorbell
470 * overflow but another one already handled it. Can abort here. If
471 * This PF also requires overflow recovery we will be interrupted again.
472 * The masked almost full indication may also be set. Ignoring.
474 int_sts = qed_rd(p_hwfn, p_ptt, DORQ_REG_INT_STS);
475 if (!(int_sts & ~DORQ_REG_INT_STS_DORQ_FIFO_AFULL))
478 DP_NOTICE(p_hwfn->cdev, "DORQ attention. int_sts was %x\n", int_sts);
480 /* check if db_drop or overflow happened */
481 if (int_sts & (DORQ_REG_INT_STS_DB_DROP |
482 DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR)) {
483 /* Obtain data about db drop/overflow */
484 first_drop_reason = qed_rd(p_hwfn, p_ptt,
485 DORQ_REG_DB_DROP_REASON) &
486 QED_DORQ_ATTENTION_REASON_MASK;
487 details = qed_rd(p_hwfn, p_ptt, DORQ_REG_DB_DROP_DETAILS);
488 address = qed_rd(p_hwfn, p_ptt,
489 DORQ_REG_DB_DROP_DETAILS_ADDRESS);
490 all_drops_reason = qed_rd(p_hwfn, p_ptt,
491 DORQ_REG_DB_DROP_DETAILS_REASON);
494 DP_NOTICE(p_hwfn->cdev,
495 "Doorbell drop occurred\n"
496 "Address\t\t0x%08x\t(second BAR address)\n"
497 "FID\t\t0x%04x\t\t(Opaque FID)\n"
498 "Size\t\t0x%04x\t\t(in bytes)\n"
499 "1st drop reason\t0x%08x\t(details on first drop since last handling)\n"
500 "Sticky reasons\t0x%08x\t(all drop reasons since last handling)\n",
502 GET_FIELD(details, QED_DORQ_ATTENTION_OPAQUE),
503 GET_FIELD(details, QED_DORQ_ATTENTION_SIZE) * 4,
504 first_drop_reason, all_drops_reason);
506 /* Clear the doorbell drop details and prepare for next drop */
507 qed_wr(p_hwfn, p_ptt, DORQ_REG_DB_DROP_DETAILS_REL, 0);
509 /* Mark interrupt as handled (note: even if drop was due to a different
510 * reason than overflow we mark as handled)
515 DORQ_REG_INT_STS_DB_DROP |
516 DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR);
518 /* If there are no indications other than drop indications, success */
519 if ((int_sts & ~(DORQ_REG_INT_STS_DB_DROP |
520 DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR |
521 DORQ_REG_INT_STS_DORQ_FIFO_AFULL)) == 0)
525 /* Some other indication was present - non recoverable */
526 DP_INFO(p_hwfn, "DORQ fatal attention\n");
531 static int qed_dorq_attn_cb(struct qed_hwfn *p_hwfn)
533 p_hwfn->db_recovery_info.dorq_attn = true;
534 qed_dorq_attn_overflow(p_hwfn);
536 return qed_dorq_attn_int_sts(p_hwfn);
539 static void qed_dorq_attn_handler(struct qed_hwfn *p_hwfn)
541 if (p_hwfn->db_recovery_info.dorq_attn)
544 /* Call DORQ callback if the attention was missed */
545 qed_dorq_attn_cb(p_hwfn);
547 p_hwfn->db_recovery_info.dorq_attn = false;
550 /* Instead of major changes to the data-structure, we have a some 'special'
551 * identifiers for sources that changed meaning between adapters.
553 enum aeu_invert_reg_special_type {
554 AEU_INVERT_REG_SPECIAL_CNIG_0,
555 AEU_INVERT_REG_SPECIAL_CNIG_1,
556 AEU_INVERT_REG_SPECIAL_CNIG_2,
557 AEU_INVERT_REG_SPECIAL_CNIG_3,
558 AEU_INVERT_REG_SPECIAL_MAX,
561 static struct aeu_invert_reg_bit
562 aeu_descs_special[AEU_INVERT_REG_SPECIAL_MAX] = {
563 {"CNIG port 0", ATTENTION_SINGLE, NULL, BLOCK_CNIG},
564 {"CNIG port 1", ATTENTION_SINGLE, NULL, BLOCK_CNIG},
565 {"CNIG port 2", ATTENTION_SINGLE, NULL, BLOCK_CNIG},
566 {"CNIG port 3", ATTENTION_SINGLE, NULL, BLOCK_CNIG},
569 /* Notice aeu_invert_reg must be defined in the same order of bits as HW; */
570 static struct aeu_invert_reg aeu_descs[NUM_ATTN_REGS] = {
572 { /* After Invert 1 */
574 (32 << ATTENTION_LENGTH_SHIFT), NULL, MAX_BLOCK_ID},
579 { /* After Invert 2 */
580 {"PGLUE config_space", ATTENTION_SINGLE,
582 {"PGLUE misc_flr", ATTENTION_SINGLE,
584 {"PGLUE B RBC", ATTENTION_PAR_INT,
585 qed_pglueb_rbc_attn_cb, BLOCK_PGLUE_B},
586 {"PGLUE misc_mctp", ATTENTION_SINGLE,
588 {"Flash event", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID},
589 {"SMB event", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID},
590 {"Main Power", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID},
591 {"SW timers #%d", (8 << ATTENTION_LENGTH_SHIFT) |
592 (1 << ATTENTION_OFFSET_SHIFT),
594 {"PCIE glue/PXP VPD %d",
595 (16 << ATTENTION_LENGTH_SHIFT), NULL, BLOCK_PGLCS},
600 { /* After Invert 3 */
601 {"General Attention %d",
602 (32 << ATTENTION_LENGTH_SHIFT), NULL, MAX_BLOCK_ID},
607 { /* After Invert 4 */
608 {"General Attention 32", ATTENTION_SINGLE,
610 {"General Attention %d",
611 (2 << ATTENTION_LENGTH_SHIFT) |
612 (33 << ATTENTION_OFFSET_SHIFT), NULL, MAX_BLOCK_ID},
613 {"General Attention 35", ATTENTION_SINGLE,
616 ATTENTION_PAR | ATTENTION_BB_DIFFERENT |
617 ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_0),
620 ATTENTION_SINGLE | ATTENTION_BB_DIFFERENT |
621 ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_1),
624 ATTENTION_PAR | ATTENTION_BB_DIFFERENT |
625 ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_2),
628 ATTENTION_SINGLE | ATTENTION_BB_DIFFERENT |
629 ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_3),
631 {"MCP CPU", ATTENTION_SINGLE,
632 qed_mcp_attn_cb, MAX_BLOCK_ID},
633 {"MCP Watchdog timer", ATTENTION_SINGLE,
635 {"MCP M2P", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID},
636 {"AVS stop status ready", ATTENTION_SINGLE,
638 {"MSTAT", ATTENTION_PAR_INT, NULL, MAX_BLOCK_ID},
639 {"MSTAT per-path", ATTENTION_PAR_INT,
641 {"Reserved %d", (6 << ATTENTION_LENGTH_SHIFT),
643 {"NIG", ATTENTION_PAR_INT, NULL, BLOCK_NIG},
644 {"BMB/OPTE/MCP", ATTENTION_PAR_INT, NULL, BLOCK_BMB},
645 {"BTB", ATTENTION_PAR_INT, NULL, BLOCK_BTB},
646 {"BRB", ATTENTION_PAR_INT, NULL, BLOCK_BRB},
647 {"PRS", ATTENTION_PAR_INT, NULL, BLOCK_PRS},
652 { /* After Invert 5 */
653 {"SRC", ATTENTION_PAR_INT, NULL, BLOCK_SRC},
654 {"PB Client1", ATTENTION_PAR_INT, NULL, BLOCK_PBF_PB1},
655 {"PB Client2", ATTENTION_PAR_INT, NULL, BLOCK_PBF_PB2},
656 {"RPB", ATTENTION_PAR_INT, NULL, BLOCK_RPB},
657 {"PBF", ATTENTION_PAR_INT, NULL, BLOCK_PBF},
658 {"QM", ATTENTION_PAR_INT, NULL, BLOCK_QM},
659 {"TM", ATTENTION_PAR_INT, NULL, BLOCK_TM},
660 {"MCM", ATTENTION_PAR_INT, NULL, BLOCK_MCM},
661 {"MSDM", ATTENTION_PAR_INT, NULL, BLOCK_MSDM},
662 {"MSEM", ATTENTION_PAR_INT, NULL, BLOCK_MSEM},
663 {"PCM", ATTENTION_PAR_INT, NULL, BLOCK_PCM},
664 {"PSDM", ATTENTION_PAR_INT, NULL, BLOCK_PSDM},
665 {"PSEM", ATTENTION_PAR_INT, NULL, BLOCK_PSEM},
666 {"TCM", ATTENTION_PAR_INT, NULL, BLOCK_TCM},
667 {"TSDM", ATTENTION_PAR_INT, NULL, BLOCK_TSDM},
668 {"TSEM", ATTENTION_PAR_INT, NULL, BLOCK_TSEM},
673 { /* After Invert 6 */
674 {"UCM", ATTENTION_PAR_INT, NULL, BLOCK_UCM},
675 {"USDM", ATTENTION_PAR_INT, NULL, BLOCK_USDM},
676 {"USEM", ATTENTION_PAR_INT, NULL, BLOCK_USEM},
677 {"XCM", ATTENTION_PAR_INT, NULL, BLOCK_XCM},
678 {"XSDM", ATTENTION_PAR_INT, NULL, BLOCK_XSDM},
679 {"XSEM", ATTENTION_PAR_INT, NULL, BLOCK_XSEM},
680 {"YCM", ATTENTION_PAR_INT, NULL, BLOCK_YCM},
681 {"YSDM", ATTENTION_PAR_INT, NULL, BLOCK_YSDM},
682 {"YSEM", ATTENTION_PAR_INT, NULL, BLOCK_YSEM},
683 {"XYLD", ATTENTION_PAR_INT, NULL, BLOCK_XYLD},
684 {"TMLD", ATTENTION_PAR_INT, NULL, BLOCK_TMLD},
685 {"MYLD", ATTENTION_PAR_INT, NULL, BLOCK_MULD},
686 {"YULD", ATTENTION_PAR_INT, NULL, BLOCK_YULD},
687 {"DORQ", ATTENTION_PAR_INT,
688 qed_dorq_attn_cb, BLOCK_DORQ},
689 {"DBG", ATTENTION_PAR_INT, NULL, BLOCK_DBG},
690 {"IPC", ATTENTION_PAR_INT, NULL, BLOCK_IPC},
695 { /* After Invert 7 */
696 {"CCFC", ATTENTION_PAR_INT, NULL, BLOCK_CCFC},
697 {"CDU", ATTENTION_PAR_INT, NULL, BLOCK_CDU},
698 {"DMAE", ATTENTION_PAR_INT, NULL, BLOCK_DMAE},
699 {"IGU", ATTENTION_PAR_INT, NULL, BLOCK_IGU},
700 {"ATC", ATTENTION_PAR_INT, NULL, MAX_BLOCK_ID},
701 {"CAU", ATTENTION_PAR_INT, NULL, BLOCK_CAU},
702 {"PTU", ATTENTION_PAR_INT, NULL, BLOCK_PTU},
703 {"PRM", ATTENTION_PAR_INT, NULL, BLOCK_PRM},
704 {"TCFC", ATTENTION_PAR_INT, NULL, BLOCK_TCFC},
705 {"RDIF", ATTENTION_PAR_INT, NULL, BLOCK_RDIF},
706 {"TDIF", ATTENTION_PAR_INT, NULL, BLOCK_TDIF},
707 {"RSS", ATTENTION_PAR_INT, NULL, BLOCK_RSS},
708 {"MISC", ATTENTION_PAR_INT, NULL, BLOCK_MISC},
709 {"MISCS", ATTENTION_PAR_INT, NULL, BLOCK_MISCS},
710 {"PCIE", ATTENTION_PAR, NULL, BLOCK_PCIE},
711 {"Vaux PCI core", ATTENTION_SINGLE, NULL, BLOCK_PGLCS},
712 {"PSWRQ", ATTENTION_PAR_INT, NULL, BLOCK_PSWRQ},
717 { /* After Invert 8 */
718 {"PSWRQ (pci_clk)", ATTENTION_PAR_INT,
720 {"PSWWR", ATTENTION_PAR_INT, NULL, BLOCK_PSWWR},
721 {"PSWWR (pci_clk)", ATTENTION_PAR_INT,
723 {"PSWRD", ATTENTION_PAR_INT, NULL, BLOCK_PSWRD},
724 {"PSWRD (pci_clk)", ATTENTION_PAR_INT,
726 {"PSWHST", ATTENTION_PAR_INT,
727 qed_pswhst_attn_cb, BLOCK_PSWHST},
728 {"PSWHST (pci_clk)", ATTENTION_PAR_INT,
729 NULL, BLOCK_PSWHST2},
730 {"GRC", ATTENTION_PAR_INT,
731 qed_grc_attn_cb, BLOCK_GRC},
732 {"CPMU", ATTENTION_PAR_INT, NULL, BLOCK_CPMU},
733 {"NCSI", ATTENTION_PAR_INT, NULL, BLOCK_NCSI},
734 {"MSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID},
735 {"PSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID},
736 {"TSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID},
737 {"USEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID},
738 {"XSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID},
739 {"YSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID},
740 {"pxp_misc_mps", ATTENTION_PAR, NULL, BLOCK_PGLCS},
741 {"PCIE glue/PXP Exp. ROM", ATTENTION_SINGLE,
743 {"PERST_B assertion", ATTENTION_SINGLE,
745 {"PERST_B deassertion", ATTENTION_SINGLE,
747 {"Reserved %d", (2 << ATTENTION_LENGTH_SHIFT),
753 { /* After Invert 9 */
754 {"MCP Latched memory", ATTENTION_PAR,
756 {"MCP Latched scratchpad cache", ATTENTION_SINGLE,
758 {"MCP Latched ump_tx", ATTENTION_PAR,
760 {"MCP Latched scratchpad", ATTENTION_PAR,
762 {"Reserved %d", (28 << ATTENTION_LENGTH_SHIFT),
768 static struct aeu_invert_reg_bit *
769 qed_int_aeu_translate(struct qed_hwfn *p_hwfn,
770 struct aeu_invert_reg_bit *p_bit)
772 if (!QED_IS_BB(p_hwfn->cdev))
775 if (!(p_bit->flags & ATTENTION_BB_DIFFERENT))
778 return &aeu_descs_special[(p_bit->flags & ATTENTION_BB_MASK) >>
782 static bool qed_int_is_parity_flag(struct qed_hwfn *p_hwfn,
783 struct aeu_invert_reg_bit *p_bit)
785 return !!(qed_int_aeu_translate(p_hwfn, p_bit)->flags &
789 #define ATTN_STATE_BITS (0xfff)
790 #define ATTN_BITS_MASKABLE (0x3ff)
791 struct qed_sb_attn_info {
792 /* Virtual & Physical address of the SB */
793 struct atten_status_block *sb_attn;
796 /* Last seen running index */
799 /* A mask of the AEU bits resulting in a parity error */
800 u32 parity_mask[NUM_ATTN_REGS];
802 /* A pointer to the attention description structure */
803 struct aeu_invert_reg *p_aeu_desc;
805 /* Previously asserted attentions, which are still unasserted */
808 /* Cleanup address for the link's general hw attention */
812 static inline u16 qed_attn_update_idx(struct qed_hwfn *p_hwfn,
813 struct qed_sb_attn_info *p_sb_desc)
817 /* Make certain HW write took affect */
820 index = le16_to_cpu(p_sb_desc->sb_attn->sb_index);
821 if (p_sb_desc->index != index) {
822 p_sb_desc->index = index;
826 /* Make certain we got a consistent view with HW */
833 * @brief qed_int_assertion - handles asserted attention bits
836 * @param asserted_bits newly asserted bits
839 static int qed_int_assertion(struct qed_hwfn *p_hwfn, u16 asserted_bits)
841 struct qed_sb_attn_info *sb_attn_sw = p_hwfn->p_sb_attn;
844 /* Mask the source of the attention in the IGU */
845 igu_mask = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE);
846 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "IGU mask: 0x%08x --> 0x%08x\n",
847 igu_mask, igu_mask & ~(asserted_bits & ATTN_BITS_MASKABLE));
848 igu_mask &= ~(asserted_bits & ATTN_BITS_MASKABLE);
849 qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE, igu_mask);
851 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
852 "inner known ATTN state: 0x%04x --> 0x%04x\n",
853 sb_attn_sw->known_attn,
854 sb_attn_sw->known_attn | asserted_bits);
855 sb_attn_sw->known_attn |= asserted_bits;
857 /* Handle MCP events */
858 if (asserted_bits & 0x100) {
859 qed_mcp_handle_events(p_hwfn, p_hwfn->p_dpc_ptt);
860 /* Clean the MCP attention */
861 qed_wr(p_hwfn, p_hwfn->p_dpc_ptt,
862 sb_attn_sw->mfw_attn_addr, 0);
865 DIRECT_REG_WR((u8 __iomem *)p_hwfn->regview +
866 GTT_BAR0_MAP_REG_IGU_CMD +
867 ((IGU_CMD_ATTN_BIT_SET_UPPER -
868 IGU_CMD_INT_ACK_BASE) << 3),
871 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "set cmd IGU: 0x%04x\n",
877 static void qed_int_attn_print(struct qed_hwfn *p_hwfn,
879 enum dbg_attn_type type, bool b_clear)
881 struct dbg_attn_block_result attn_results;
882 enum dbg_status status;
884 memset(&attn_results, 0, sizeof(attn_results));
886 status = qed_dbg_read_attn(p_hwfn, p_hwfn->p_dpc_ptt, id, type,
887 b_clear, &attn_results);
888 if (status != DBG_STATUS_OK)
890 "Failed to parse attention information [status: %s]\n",
891 qed_dbg_get_status_str(status));
893 qed_dbg_parse_attn(p_hwfn, &attn_results);
897 * @brief qed_int_deassertion_aeu_bit - handles the effects of a single
898 * cause of the attention
901 * @param p_aeu - descriptor of an AEU bit which caused the attention
902 * @param aeu_en_reg - register offset of the AEU enable reg. which configured
903 * this bit to this group.
904 * @param bit_index - index of this bit in the aeu_en_reg
909 qed_int_deassertion_aeu_bit(struct qed_hwfn *p_hwfn,
910 struct aeu_invert_reg_bit *p_aeu,
912 const char *p_bit_name, u32 bitmask)
914 bool b_fatal = false;
918 DP_INFO(p_hwfn, "Deasserted attention `%s'[%08x]\n",
919 p_bit_name, bitmask);
921 /* Call callback before clearing the interrupt status */
923 DP_INFO(p_hwfn, "`%s (attention)': Calling Callback function\n",
925 rc = p_aeu->cb(p_hwfn);
931 /* Print HW block interrupt registers */
932 if (p_aeu->block_index != MAX_BLOCK_ID)
933 qed_int_attn_print(p_hwfn, p_aeu->block_index,
934 ATTN_TYPE_INTERRUPT, !b_fatal);
937 /* If the attention is benign, no need to prevent it */
941 /* Prevent this Attention from being asserted in the future */
942 val = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg);
943 qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg, (val & ~bitmask));
944 DP_INFO(p_hwfn, "`%s' - Disabled future attentions\n",
952 * @brief qed_int_deassertion_parity - handle a single parity AEU source
955 * @param p_aeu - descriptor of an AEU bit which caused the parity
956 * @param aeu_en_reg - address of the AEU enable register
959 static void qed_int_deassertion_parity(struct qed_hwfn *p_hwfn,
960 struct aeu_invert_reg_bit *p_aeu,
961 u32 aeu_en_reg, u8 bit_index)
963 u32 block_id = p_aeu->block_index, mask, val;
965 DP_NOTICE(p_hwfn->cdev,
966 "%s parity attention is set [address 0x%08x, bit %d]\n",
967 p_aeu->bit_name, aeu_en_reg, bit_index);
969 if (block_id != MAX_BLOCK_ID) {
970 qed_int_attn_print(p_hwfn, block_id, ATTN_TYPE_PARITY, false);
972 /* In BB, there's a single parity bit for several blocks */
973 if (block_id == BLOCK_BTB) {
974 qed_int_attn_print(p_hwfn, BLOCK_OPTE,
975 ATTN_TYPE_PARITY, false);
976 qed_int_attn_print(p_hwfn, BLOCK_MCP,
977 ATTN_TYPE_PARITY, false);
981 /* Prevent this parity error from being re-asserted */
982 mask = ~BIT(bit_index);
983 val = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg);
984 qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg, val & mask);
985 DP_INFO(p_hwfn, "`%s' - Disabled future parity errors\n",
990 * @brief - handles deassertion of previously asserted attentions.
993 * @param deasserted_bits - newly deasserted bits
997 static int qed_int_deassertion(struct qed_hwfn *p_hwfn,
1000 struct qed_sb_attn_info *sb_attn_sw = p_hwfn->p_sb_attn;
1001 u32 aeu_inv_arr[NUM_ATTN_REGS], aeu_mask, aeu_en, en;
1002 u8 i, j, k, bit_idx;
1005 /* Read the attention registers in the AEU */
1006 for (i = 0; i < NUM_ATTN_REGS; i++) {
1007 aeu_inv_arr[i] = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
1008 MISC_REG_AEU_AFTER_INVERT_1_IGU +
1010 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
1011 "Deasserted bits [%d]: %08x\n",
1015 /* Find parity attentions first */
1016 for (i = 0; i < NUM_ATTN_REGS; i++) {
1017 struct aeu_invert_reg *p_aeu = &sb_attn_sw->p_aeu_desc[i];
1020 aeu_en = MISC_REG_AEU_ENABLE1_IGU_OUT_0 + i * sizeof(u32);
1021 en = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en);
1023 /* Skip register in which no parity bit is currently set */
1024 parities = sb_attn_sw->parity_mask[i] & aeu_inv_arr[i] & en;
1028 for (j = 0, bit_idx = 0; bit_idx < 32; j++) {
1029 struct aeu_invert_reg_bit *p_bit = &p_aeu->bits[j];
1031 if (qed_int_is_parity_flag(p_hwfn, p_bit) &&
1032 !!(parities & BIT(bit_idx)))
1033 qed_int_deassertion_parity(p_hwfn, p_bit,
1036 bit_idx += ATTENTION_LENGTH(p_bit->flags);
1040 /* Find non-parity cause for attention and act */
1041 for (k = 0; k < MAX_ATTN_GRPS; k++) {
1042 struct aeu_invert_reg_bit *p_aeu;
1044 /* Handle only groups whose attention is currently deasserted */
1045 if (!(deasserted_bits & (1 << k)))
1048 for (i = 0; i < NUM_ATTN_REGS; i++) {
1051 aeu_en = MISC_REG_AEU_ENABLE1_IGU_OUT_0 +
1053 k * sizeof(u32) * NUM_ATTN_REGS;
1055 en = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en);
1056 bits = aeu_inv_arr[i] & en;
1058 /* Skip if no bit from this group is currently set */
1062 /* Find all set bits from current register which belong
1063 * to current group, making them responsible for the
1064 * previous assertion.
1066 for (j = 0, bit_idx = 0; bit_idx < 32; j++) {
1067 long unsigned int bitmask;
1070 p_aeu = &sb_attn_sw->p_aeu_desc[i].bits[j];
1071 p_aeu = qed_int_aeu_translate(p_hwfn, p_aeu);
1074 bit_len = ATTENTION_LENGTH(p_aeu->flags);
1075 if (qed_int_is_parity_flag(p_hwfn, p_aeu)) {
1081 bitmask = bits & (((1 << bit_len) - 1) << bit);
1085 u32 flags = p_aeu->flags;
1089 num = (u8)find_first_bit(&bitmask,
1092 /* Some bits represent more than a
1093 * a single interrupt. Correctly print
1096 if (ATTENTION_LENGTH(flags) > 2 ||
1097 ((flags & ATTENTION_PAR_INT) &&
1098 ATTENTION_LENGTH(flags) > 1))
1099 snprintf(bit_name, 30,
1100 p_aeu->bit_name, num);
1103 p_aeu->bit_name, 30);
1105 /* We now need to pass bitmask in its
1110 /* Handle source of the attention */
1111 qed_int_deassertion_aeu_bit(p_hwfn,
1118 bit_idx += ATTENTION_LENGTH(p_aeu->flags);
1123 /* Handle missed DORQ attention */
1124 qed_dorq_attn_handler(p_hwfn);
1126 /* Clear IGU indication for the deasserted bits */
1127 DIRECT_REG_WR((u8 __iomem *)p_hwfn->regview +
1128 GTT_BAR0_MAP_REG_IGU_CMD +
1129 ((IGU_CMD_ATTN_BIT_CLR_UPPER -
1130 IGU_CMD_INT_ACK_BASE) << 3),
1131 ~((u32)deasserted_bits));
1133 /* Unmask deasserted attentions in IGU */
1134 aeu_mask = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE);
1135 aeu_mask |= (deasserted_bits & ATTN_BITS_MASKABLE);
1136 qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE, aeu_mask);
1138 /* Clear deassertion from inner state */
1139 sb_attn_sw->known_attn &= ~deasserted_bits;
1144 static int qed_int_attentions(struct qed_hwfn *p_hwfn)
1146 struct qed_sb_attn_info *p_sb_attn_sw = p_hwfn->p_sb_attn;
1147 struct atten_status_block *p_sb_attn = p_sb_attn_sw->sb_attn;
1148 u32 attn_bits = 0, attn_acks = 0;
1149 u16 asserted_bits, deasserted_bits;
1153 /* Read current attention bits/acks - safeguard against attentions
1154 * by guaranting work on a synchronized timeframe
1157 index = p_sb_attn->sb_index;
1158 /* finish reading index before the loop condition */
1160 attn_bits = le32_to_cpu(p_sb_attn->atten_bits);
1161 attn_acks = le32_to_cpu(p_sb_attn->atten_ack);
1162 } while (index != p_sb_attn->sb_index);
1163 p_sb_attn->sb_index = index;
1165 /* Attention / Deassertion are meaningful (and in correct state)
1166 * only when they differ and consistent with known state - deassertion
1167 * when previous attention & current ack, and assertion when current
1168 * attention with no previous attention
1170 asserted_bits = (attn_bits & ~attn_acks & ATTN_STATE_BITS) &
1171 ~p_sb_attn_sw->known_attn;
1172 deasserted_bits = (~attn_bits & attn_acks & ATTN_STATE_BITS) &
1173 p_sb_attn_sw->known_attn;
1175 if ((asserted_bits & ~0x100) || (deasserted_bits & ~0x100)) {
1177 "Attention: Index: 0x%04x, Bits: 0x%08x, Acks: 0x%08x, asserted: 0x%04x, De-asserted 0x%04x [Prev. known: 0x%04x]\n",
1178 index, attn_bits, attn_acks, asserted_bits,
1179 deasserted_bits, p_sb_attn_sw->known_attn);
1180 } else if (asserted_bits == 0x100) {
1181 DP_INFO(p_hwfn, "MFW indication via attention\n");
1183 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
1184 "MFW indication [deassertion]\n");
1187 if (asserted_bits) {
1188 rc = qed_int_assertion(p_hwfn, asserted_bits);
1193 if (deasserted_bits)
1194 rc = qed_int_deassertion(p_hwfn, deasserted_bits);
1199 static void qed_sb_ack_attn(struct qed_hwfn *p_hwfn,
1200 void __iomem *igu_addr, u32 ack_cons)
1202 struct igu_prod_cons_update igu_ack = { 0 };
1204 igu_ack.sb_id_and_flags =
1205 ((ack_cons << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) |
1206 (1 << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) |
1207 (IGU_INT_NOP << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) |
1208 (IGU_SEG_ACCESS_ATTN <<
1209 IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT));
1211 DIRECT_REG_WR(igu_addr, igu_ack.sb_id_and_flags);
1213 /* Both segments (interrupts & acks) are written to same place address;
1214 * Need to guarantee all commands will be received (in-order) by HW.
1220 void qed_int_sp_dpc(unsigned long hwfn_cookie)
1222 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)hwfn_cookie;
1223 struct qed_pi_info *pi_info = NULL;
1224 struct qed_sb_attn_info *sb_attn;
1225 struct qed_sb_info *sb_info;
1229 if (!p_hwfn->p_sp_sb) {
1230 DP_ERR(p_hwfn->cdev, "DPC called - no p_sp_sb\n");
1234 sb_info = &p_hwfn->p_sp_sb->sb_info;
1235 arr_size = ARRAY_SIZE(p_hwfn->p_sp_sb->pi_info_arr);
1237 DP_ERR(p_hwfn->cdev,
1238 "Status block is NULL - cannot ack interrupts\n");
1242 if (!p_hwfn->p_sb_attn) {
1243 DP_ERR(p_hwfn->cdev, "DPC called - no p_sb_attn");
1246 sb_attn = p_hwfn->p_sb_attn;
1248 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "DPC Called! (hwfn %p %d)\n",
1249 p_hwfn, p_hwfn->my_id);
1251 /* Disable ack for def status block. Required both for msix +
1252 * inta in non-mask mode, in inta does no harm.
1254 qed_sb_ack(sb_info, IGU_INT_DISABLE, 0);
1256 /* Gather Interrupts/Attentions information */
1257 if (!sb_info->sb_virt) {
1258 DP_ERR(p_hwfn->cdev,
1259 "Interrupt Status block is NULL - cannot check for new interrupts!\n");
1261 u32 tmp_index = sb_info->sb_ack;
1263 rc = qed_sb_update_sb_idx(sb_info);
1264 DP_VERBOSE(p_hwfn->cdev, NETIF_MSG_INTR,
1265 "Interrupt indices: 0x%08x --> 0x%08x\n",
1266 tmp_index, sb_info->sb_ack);
1269 if (!sb_attn || !sb_attn->sb_attn) {
1270 DP_ERR(p_hwfn->cdev,
1271 "Attentions Status block is NULL - cannot check for new attentions!\n");
1273 u16 tmp_index = sb_attn->index;
1275 rc |= qed_attn_update_idx(p_hwfn, sb_attn);
1276 DP_VERBOSE(p_hwfn->cdev, NETIF_MSG_INTR,
1277 "Attention indices: 0x%08x --> 0x%08x\n",
1278 tmp_index, sb_attn->index);
1281 /* Check if we expect interrupts at this time. if not just ack them */
1282 if (!(rc & QED_SB_EVENT_MASK)) {
1283 qed_sb_ack(sb_info, IGU_INT_ENABLE, 1);
1287 /* Check the validity of the DPC ptt. If not ack interrupts and fail */
1288 if (!p_hwfn->p_dpc_ptt) {
1289 DP_NOTICE(p_hwfn->cdev, "Failed to allocate PTT\n");
1290 qed_sb_ack(sb_info, IGU_INT_ENABLE, 1);
1294 if (rc & QED_SB_ATT_IDX)
1295 qed_int_attentions(p_hwfn);
1297 if (rc & QED_SB_IDX) {
1300 /* Look for a free index */
1301 for (pi = 0; pi < arr_size; pi++) {
1302 pi_info = &p_hwfn->p_sp_sb->pi_info_arr[pi];
1303 if (pi_info->comp_cb)
1304 pi_info->comp_cb(p_hwfn, pi_info->cookie);
1308 if (sb_attn && (rc & QED_SB_ATT_IDX))
1309 /* This should be done before the interrupts are enabled,
1310 * since otherwise a new attention will be generated.
1312 qed_sb_ack_attn(p_hwfn, sb_info->igu_addr, sb_attn->index);
1314 qed_sb_ack(sb_info, IGU_INT_ENABLE, 1);
1317 static void qed_int_sb_attn_free(struct qed_hwfn *p_hwfn)
1319 struct qed_sb_attn_info *p_sb = p_hwfn->p_sb_attn;
1325 dma_free_coherent(&p_hwfn->cdev->pdev->dev,
1326 SB_ATTN_ALIGNED_SIZE(p_hwfn),
1327 p_sb->sb_attn, p_sb->sb_phys);
1329 p_hwfn->p_sb_attn = NULL;
1332 static void qed_int_sb_attn_setup(struct qed_hwfn *p_hwfn,
1333 struct qed_ptt *p_ptt)
1335 struct qed_sb_attn_info *sb_info = p_hwfn->p_sb_attn;
1337 memset(sb_info->sb_attn, 0, sizeof(*sb_info->sb_attn));
1340 sb_info->known_attn = 0;
1342 /* Configure Attention Status Block in IGU */
1343 qed_wr(p_hwfn, p_ptt, IGU_REG_ATTN_MSG_ADDR_L,
1344 lower_32_bits(p_hwfn->p_sb_attn->sb_phys));
1345 qed_wr(p_hwfn, p_ptt, IGU_REG_ATTN_MSG_ADDR_H,
1346 upper_32_bits(p_hwfn->p_sb_attn->sb_phys));
1349 static void qed_int_sb_attn_init(struct qed_hwfn *p_hwfn,
1350 struct qed_ptt *p_ptt,
1351 void *sb_virt_addr, dma_addr_t sb_phy_addr)
1353 struct qed_sb_attn_info *sb_info = p_hwfn->p_sb_attn;
1356 sb_info->sb_attn = sb_virt_addr;
1357 sb_info->sb_phys = sb_phy_addr;
1359 /* Set the pointer to the AEU descriptors */
1360 sb_info->p_aeu_desc = aeu_descs;
1362 /* Calculate Parity Masks */
1363 memset(sb_info->parity_mask, 0, sizeof(u32) * NUM_ATTN_REGS);
1364 for (i = 0; i < NUM_ATTN_REGS; i++) {
1365 /* j is array index, k is bit index */
1366 for (j = 0, k = 0; k < 32; j++) {
1367 struct aeu_invert_reg_bit *p_aeu;
1369 p_aeu = &aeu_descs[i].bits[j];
1370 if (qed_int_is_parity_flag(p_hwfn, p_aeu))
1371 sb_info->parity_mask[i] |= 1 << k;
1373 k += ATTENTION_LENGTH(p_aeu->flags);
1375 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
1376 "Attn Mask [Reg %d]: 0x%08x\n",
1377 i, sb_info->parity_mask[i]);
1380 /* Set the address of cleanup for the mcp attention */
1381 sb_info->mfw_attn_addr = (p_hwfn->rel_pf_id << 3) +
1382 MISC_REG_AEU_GENERAL_ATTN_0;
1384 qed_int_sb_attn_setup(p_hwfn, p_ptt);
1387 static int qed_int_sb_attn_alloc(struct qed_hwfn *p_hwfn,
1388 struct qed_ptt *p_ptt)
1390 struct qed_dev *cdev = p_hwfn->cdev;
1391 struct qed_sb_attn_info *p_sb;
1392 dma_addr_t p_phys = 0;
1396 p_sb = kmalloc(sizeof(*p_sb), GFP_KERNEL);
1401 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
1402 SB_ATTN_ALIGNED_SIZE(p_hwfn),
1403 &p_phys, GFP_KERNEL);
1410 /* Attention setup */
1411 p_hwfn->p_sb_attn = p_sb;
1412 qed_int_sb_attn_init(p_hwfn, p_ptt, p_virt, p_phys);
1417 /* coalescing timeout = timeset << (timer_res + 1) */
1418 #define QED_CAU_DEF_RX_USECS 24
1419 #define QED_CAU_DEF_TX_USECS 48
1421 void qed_init_cau_sb_entry(struct qed_hwfn *p_hwfn,
1422 struct cau_sb_entry *p_sb_entry,
1423 u8 pf_id, u16 vf_number, u8 vf_valid)
1425 struct qed_dev *cdev = p_hwfn->cdev;
1429 memset(p_sb_entry, 0, sizeof(*p_sb_entry));
1431 SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_PF_NUMBER, pf_id);
1432 SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_VF_NUMBER, vf_number);
1433 SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_VF_VALID, vf_valid);
1434 SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_SB_TIMESET0, 0x7F);
1435 SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_SB_TIMESET1, 0x7F);
1437 cau_state = CAU_HC_DISABLE_STATE;
1439 if (cdev->int_coalescing_mode == QED_COAL_MODE_ENABLE) {
1440 cau_state = CAU_HC_ENABLE_STATE;
1441 if (!cdev->rx_coalesce_usecs)
1442 cdev->rx_coalesce_usecs = QED_CAU_DEF_RX_USECS;
1443 if (!cdev->tx_coalesce_usecs)
1444 cdev->tx_coalesce_usecs = QED_CAU_DEF_TX_USECS;
1447 /* Coalesce = (timeset << timer-res), timeset is 7bit wide */
1448 if (cdev->rx_coalesce_usecs <= 0x7F)
1450 else if (cdev->rx_coalesce_usecs <= 0xFF)
1454 SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_TIMER_RES0, timer_res);
1456 if (cdev->tx_coalesce_usecs <= 0x7F)
1458 else if (cdev->tx_coalesce_usecs <= 0xFF)
1462 SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_TIMER_RES1, timer_res);
1464 SET_FIELD(p_sb_entry->data, CAU_SB_ENTRY_STATE0, cau_state);
1465 SET_FIELD(p_sb_entry->data, CAU_SB_ENTRY_STATE1, cau_state);
1468 static void qed_int_cau_conf_pi(struct qed_hwfn *p_hwfn,
1469 struct qed_ptt *p_ptt,
1472 enum qed_coalescing_fsm coalescing_fsm,
1475 struct cau_pi_entry pi_entry;
1476 u32 sb_offset, pi_offset;
1478 if (IS_VF(p_hwfn->cdev))
1481 sb_offset = igu_sb_id * PIS_PER_SB_E4;
1482 memset(&pi_entry, 0, sizeof(struct cau_pi_entry));
1484 SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_PI_TIMESET, timeset);
1485 if (coalescing_fsm == QED_COAL_RX_STATE_MACHINE)
1486 SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_FSM_SEL, 0);
1488 SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_FSM_SEL, 1);
1490 pi_offset = sb_offset + pi_index;
1491 if (p_hwfn->hw_init_done) {
1492 qed_wr(p_hwfn, p_ptt,
1493 CAU_REG_PI_MEMORY + pi_offset * sizeof(u32),
1494 *((u32 *)&(pi_entry)));
1496 STORE_RT_REG(p_hwfn,
1497 CAU_REG_PI_MEMORY_RT_OFFSET + pi_offset,
1498 *((u32 *)&(pi_entry)));
1502 void qed_int_cau_conf_sb(struct qed_hwfn *p_hwfn,
1503 struct qed_ptt *p_ptt,
1505 u16 igu_sb_id, u16 vf_number, u8 vf_valid)
1507 struct cau_sb_entry sb_entry;
1509 qed_init_cau_sb_entry(p_hwfn, &sb_entry, p_hwfn->rel_pf_id,
1510 vf_number, vf_valid);
1512 if (p_hwfn->hw_init_done) {
1513 /* Wide-bus, initialize via DMAE */
1514 u64 phys_addr = (u64)sb_phys;
1516 qed_dmae_host2grc(p_hwfn, p_ptt, (u64)(uintptr_t)&phys_addr,
1517 CAU_REG_SB_ADDR_MEMORY +
1518 igu_sb_id * sizeof(u64), 2, 0);
1519 qed_dmae_host2grc(p_hwfn, p_ptt, (u64)(uintptr_t)&sb_entry,
1520 CAU_REG_SB_VAR_MEMORY +
1521 igu_sb_id * sizeof(u64), 2, 0);
1523 /* Initialize Status Block Address */
1524 STORE_RT_REG_AGG(p_hwfn,
1525 CAU_REG_SB_ADDR_MEMORY_RT_OFFSET +
1529 STORE_RT_REG_AGG(p_hwfn,
1530 CAU_REG_SB_VAR_MEMORY_RT_OFFSET +
1535 /* Configure pi coalescing if set */
1536 if (p_hwfn->cdev->int_coalescing_mode == QED_COAL_MODE_ENABLE) {
1537 u8 num_tc = p_hwfn->hw_info.num_hw_tc;
1538 u8 timeset, timer_res;
1541 /* timeset = (coalesce >> timer-res), timeset is 7bit wide */
1542 if (p_hwfn->cdev->rx_coalesce_usecs <= 0x7F)
1544 else if (p_hwfn->cdev->rx_coalesce_usecs <= 0xFF)
1548 timeset = (u8)(p_hwfn->cdev->rx_coalesce_usecs >> timer_res);
1549 qed_int_cau_conf_pi(p_hwfn, p_ptt, igu_sb_id, RX_PI,
1550 QED_COAL_RX_STATE_MACHINE, timeset);
1552 if (p_hwfn->cdev->tx_coalesce_usecs <= 0x7F)
1554 else if (p_hwfn->cdev->tx_coalesce_usecs <= 0xFF)
1558 timeset = (u8)(p_hwfn->cdev->tx_coalesce_usecs >> timer_res);
1559 for (i = 0; i < num_tc; i++) {
1560 qed_int_cau_conf_pi(p_hwfn, p_ptt,
1561 igu_sb_id, TX_PI(i),
1562 QED_COAL_TX_STATE_MACHINE,
1568 void qed_int_sb_setup(struct qed_hwfn *p_hwfn,
1569 struct qed_ptt *p_ptt, struct qed_sb_info *sb_info)
1571 /* zero status block and ack counter */
1572 sb_info->sb_ack = 0;
1573 memset(sb_info->sb_virt, 0, sizeof(*sb_info->sb_virt));
1575 if (IS_PF(p_hwfn->cdev))
1576 qed_int_cau_conf_sb(p_hwfn, p_ptt, sb_info->sb_phys,
1577 sb_info->igu_sb_id, 0, 0);
1580 struct qed_igu_block *qed_get_igu_free_sb(struct qed_hwfn *p_hwfn, bool b_is_pf)
1582 struct qed_igu_block *p_block;
1585 for (igu_id = 0; igu_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev);
1587 p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_id];
1589 if (!(p_block->status & QED_IGU_STATUS_VALID) ||
1590 !(p_block->status & QED_IGU_STATUS_FREE))
1593 if (!!(p_block->status & QED_IGU_STATUS_PF) == b_is_pf)
1600 static u16 qed_get_pf_igu_sb_id(struct qed_hwfn *p_hwfn, u16 vector_id)
1602 struct qed_igu_block *p_block;
1605 for (igu_id = 0; igu_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev);
1607 p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_id];
1609 if (!(p_block->status & QED_IGU_STATUS_VALID) ||
1611 p_block->vector_number != vector_id)
1617 return QED_SB_INVALID_IDX;
1620 u16 qed_get_igu_sb_id(struct qed_hwfn *p_hwfn, u16 sb_id)
1624 /* Assuming continuous set of IGU SBs dedicated for given PF */
1625 if (sb_id == QED_SP_SB_ID)
1626 igu_sb_id = p_hwfn->hw_info.p_igu_info->igu_dsb_id;
1627 else if (IS_PF(p_hwfn->cdev))
1628 igu_sb_id = qed_get_pf_igu_sb_id(p_hwfn, sb_id + 1);
1630 igu_sb_id = qed_vf_get_igu_sb_id(p_hwfn, sb_id);
1632 if (sb_id == QED_SP_SB_ID)
1633 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
1634 "Slowpath SB index in IGU is 0x%04x\n", igu_sb_id);
1636 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
1637 "SB [%04x] <--> IGU SB [%04x]\n", sb_id, igu_sb_id);
1642 int qed_int_sb_init(struct qed_hwfn *p_hwfn,
1643 struct qed_ptt *p_ptt,
1644 struct qed_sb_info *sb_info,
1645 void *sb_virt_addr, dma_addr_t sb_phy_addr, u16 sb_id)
1647 sb_info->sb_virt = sb_virt_addr;
1648 sb_info->sb_phys = sb_phy_addr;
1650 sb_info->igu_sb_id = qed_get_igu_sb_id(p_hwfn, sb_id);
1652 if (sb_id != QED_SP_SB_ID) {
1653 if (IS_PF(p_hwfn->cdev)) {
1654 struct qed_igu_info *p_info;
1655 struct qed_igu_block *p_block;
1657 p_info = p_hwfn->hw_info.p_igu_info;
1658 p_block = &p_info->entry[sb_info->igu_sb_id];
1660 p_block->sb_info = sb_info;
1661 p_block->status &= ~QED_IGU_STATUS_FREE;
1662 p_info->usage.free_cnt--;
1664 qed_vf_set_sb_info(p_hwfn, sb_id, sb_info);
1668 sb_info->cdev = p_hwfn->cdev;
1670 /* The igu address will hold the absolute address that needs to be
1671 * written to for a specific status block
1673 if (IS_PF(p_hwfn->cdev)) {
1674 sb_info->igu_addr = (u8 __iomem *)p_hwfn->regview +
1675 GTT_BAR0_MAP_REG_IGU_CMD +
1676 (sb_info->igu_sb_id << 3);
1678 sb_info->igu_addr = (u8 __iomem *)p_hwfn->regview +
1679 PXP_VF_BAR0_START_IGU +
1680 ((IGU_CMD_INT_ACK_BASE +
1681 sb_info->igu_sb_id) << 3);
1684 sb_info->flags |= QED_SB_INFO_INIT;
1686 qed_int_sb_setup(p_hwfn, p_ptt, sb_info);
1691 int qed_int_sb_release(struct qed_hwfn *p_hwfn,
1692 struct qed_sb_info *sb_info, u16 sb_id)
1694 struct qed_igu_block *p_block;
1695 struct qed_igu_info *p_info;
1700 /* zero status block and ack counter */
1701 sb_info->sb_ack = 0;
1702 memset(sb_info->sb_virt, 0, sizeof(*sb_info->sb_virt));
1704 if (IS_VF(p_hwfn->cdev)) {
1705 qed_vf_set_sb_info(p_hwfn, sb_id, NULL);
1709 p_info = p_hwfn->hw_info.p_igu_info;
1710 p_block = &p_info->entry[sb_info->igu_sb_id];
1712 /* Vector 0 is reserved to Default SB */
1713 if (!p_block->vector_number) {
1714 DP_ERR(p_hwfn, "Do Not free sp sb using this function");
1718 /* Lose reference to client's SB info, and fix counters */
1719 p_block->sb_info = NULL;
1720 p_block->status |= QED_IGU_STATUS_FREE;
1721 p_info->usage.free_cnt++;
1726 static void qed_int_sp_sb_free(struct qed_hwfn *p_hwfn)
1728 struct qed_sb_sp_info *p_sb = p_hwfn->p_sp_sb;
1733 if (p_sb->sb_info.sb_virt)
1734 dma_free_coherent(&p_hwfn->cdev->pdev->dev,
1735 SB_ALIGNED_SIZE(p_hwfn),
1736 p_sb->sb_info.sb_virt,
1737 p_sb->sb_info.sb_phys);
1739 p_hwfn->p_sp_sb = NULL;
1742 static int qed_int_sp_sb_alloc(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1744 struct qed_sb_sp_info *p_sb;
1745 dma_addr_t p_phys = 0;
1749 p_sb = kmalloc(sizeof(*p_sb), GFP_KERNEL);
1754 p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
1755 SB_ALIGNED_SIZE(p_hwfn),
1756 &p_phys, GFP_KERNEL);
1762 /* Status Block setup */
1763 p_hwfn->p_sp_sb = p_sb;
1764 qed_int_sb_init(p_hwfn, p_ptt, &p_sb->sb_info, p_virt,
1765 p_phys, QED_SP_SB_ID);
1767 memset(p_sb->pi_info_arr, 0, sizeof(p_sb->pi_info_arr));
1772 int qed_int_register_cb(struct qed_hwfn *p_hwfn,
1773 qed_int_comp_cb_t comp_cb,
1774 void *cookie, u8 *sb_idx, __le16 **p_fw_cons)
1776 struct qed_sb_sp_info *p_sp_sb = p_hwfn->p_sp_sb;
1780 /* Look for a free index */
1781 for (pi = 0; pi < ARRAY_SIZE(p_sp_sb->pi_info_arr); pi++) {
1782 if (p_sp_sb->pi_info_arr[pi].comp_cb)
1785 p_sp_sb->pi_info_arr[pi].comp_cb = comp_cb;
1786 p_sp_sb->pi_info_arr[pi].cookie = cookie;
1788 *p_fw_cons = &p_sp_sb->sb_info.sb_virt->pi_array[pi];
1796 int qed_int_unregister_cb(struct qed_hwfn *p_hwfn, u8 pi)
1798 struct qed_sb_sp_info *p_sp_sb = p_hwfn->p_sp_sb;
1800 if (p_sp_sb->pi_info_arr[pi].comp_cb == NULL)
1803 p_sp_sb->pi_info_arr[pi].comp_cb = NULL;
1804 p_sp_sb->pi_info_arr[pi].cookie = NULL;
1809 u16 qed_int_get_sp_sb_id(struct qed_hwfn *p_hwfn)
1811 return p_hwfn->p_sp_sb->sb_info.igu_sb_id;
1814 void qed_int_igu_enable_int(struct qed_hwfn *p_hwfn,
1815 struct qed_ptt *p_ptt, enum qed_int_mode int_mode)
1817 u32 igu_pf_conf = IGU_PF_CONF_FUNC_EN | IGU_PF_CONF_ATTN_BIT_EN;
1819 p_hwfn->cdev->int_mode = int_mode;
1820 switch (p_hwfn->cdev->int_mode) {
1821 case QED_INT_MODE_INTA:
1822 igu_pf_conf |= IGU_PF_CONF_INT_LINE_EN;
1823 igu_pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
1826 case QED_INT_MODE_MSI:
1827 igu_pf_conf |= IGU_PF_CONF_MSI_MSIX_EN;
1828 igu_pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
1831 case QED_INT_MODE_MSIX:
1832 igu_pf_conf |= IGU_PF_CONF_MSI_MSIX_EN;
1834 case QED_INT_MODE_POLL:
1838 qed_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, igu_pf_conf);
1841 static void qed_int_igu_enable_attn(struct qed_hwfn *p_hwfn,
1842 struct qed_ptt *p_ptt)
1845 /* Configure AEU signal change to produce attentions */
1846 qed_wr(p_hwfn, p_ptt, IGU_REG_ATTENTION_ENABLE, 0);
1847 qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0xfff);
1848 qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0xfff);
1849 qed_wr(p_hwfn, p_ptt, IGU_REG_ATTENTION_ENABLE, 0xfff);
1851 /* Flush the writes to IGU */
1854 /* Unmask AEU signals toward IGU */
1855 qed_wr(p_hwfn, p_ptt, MISC_REG_AEU_MASK_ATTN_IGU, 0xff);
1859 qed_int_igu_enable(struct qed_hwfn *p_hwfn,
1860 struct qed_ptt *p_ptt, enum qed_int_mode int_mode)
1864 qed_int_igu_enable_attn(p_hwfn, p_ptt);
1866 if ((int_mode != QED_INT_MODE_INTA) || IS_LEAD_HWFN(p_hwfn)) {
1867 rc = qed_slowpath_irq_req(p_hwfn);
1869 DP_NOTICE(p_hwfn, "Slowpath IRQ request failed\n");
1872 p_hwfn->b_int_requested = true;
1874 /* Enable interrupt Generation */
1875 qed_int_igu_enable_int(p_hwfn, p_ptt, int_mode);
1876 p_hwfn->b_int_enabled = 1;
1881 void qed_int_igu_disable_int(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1883 p_hwfn->b_int_enabled = 0;
1885 if (IS_VF(p_hwfn->cdev))
1888 qed_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, 0);
1891 #define IGU_CLEANUP_SLEEP_LENGTH (1000)
1892 static void qed_int_igu_cleanup_sb(struct qed_hwfn *p_hwfn,
1893 struct qed_ptt *p_ptt,
1895 bool cleanup_set, u16 opaque_fid)
1897 u32 cmd_ctrl = 0, val = 0, sb_bit = 0, sb_bit_addr = 0, data = 0;
1898 u32 pxp_addr = IGU_CMD_INT_ACK_BASE + igu_sb_id;
1899 u32 sleep_cnt = IGU_CLEANUP_SLEEP_LENGTH;
1901 /* Set the data field */
1902 SET_FIELD(data, IGU_CLEANUP_CLEANUP_SET, cleanup_set ? 1 : 0);
1903 SET_FIELD(data, IGU_CLEANUP_CLEANUP_TYPE, 0);
1904 SET_FIELD(data, IGU_CLEANUP_COMMAND_TYPE, IGU_COMMAND_TYPE_SET);
1906 /* Set the control register */
1907 SET_FIELD(cmd_ctrl, IGU_CTRL_REG_PXP_ADDR, pxp_addr);
1908 SET_FIELD(cmd_ctrl, IGU_CTRL_REG_FID, opaque_fid);
1909 SET_FIELD(cmd_ctrl, IGU_CTRL_REG_TYPE, IGU_CTRL_CMD_TYPE_WR);
1911 qed_wr(p_hwfn, p_ptt, IGU_REG_COMMAND_REG_32LSB_DATA, data);
1915 qed_wr(p_hwfn, p_ptt, IGU_REG_COMMAND_REG_CTRL, cmd_ctrl);
1917 /* Flush the write to IGU */
1920 /* calculate where to read the status bit from */
1921 sb_bit = 1 << (igu_sb_id % 32);
1922 sb_bit_addr = igu_sb_id / 32 * sizeof(u32);
1924 sb_bit_addr += IGU_REG_CLEANUP_STATUS_0;
1926 /* Now wait for the command to complete */
1928 val = qed_rd(p_hwfn, p_ptt, sb_bit_addr);
1930 if ((val & sb_bit) == (cleanup_set ? sb_bit : 0))
1933 usleep_range(5000, 10000);
1934 } while (--sleep_cnt);
1938 "Timeout waiting for clear status 0x%08x [for sb %d]\n",
1942 void qed_int_igu_init_pure_rt_single(struct qed_hwfn *p_hwfn,
1943 struct qed_ptt *p_ptt,
1944 u16 igu_sb_id, u16 opaque, bool b_set)
1946 struct qed_igu_block *p_block;
1949 p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_sb_id];
1950 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
1951 "Cleaning SB [%04x]: func_id= %d is_pf = %d vector_num = 0x%0x\n",
1953 p_block->function_id,
1954 p_block->is_pf, p_block->vector_number);
1958 qed_int_igu_cleanup_sb(p_hwfn, p_ptt, igu_sb_id, 1, opaque);
1961 qed_int_igu_cleanup_sb(p_hwfn, p_ptt, igu_sb_id, 0, opaque);
1963 /* Wait for the IGU SB to cleanup */
1964 for (i = 0; i < IGU_CLEANUP_SLEEP_LENGTH; i++) {
1967 val = qed_rd(p_hwfn, p_ptt,
1968 IGU_REG_WRITE_DONE_PENDING +
1969 ((igu_sb_id / 32) * 4));
1970 if (val & BIT((igu_sb_id % 32)))
1971 usleep_range(10, 20);
1975 if (i == IGU_CLEANUP_SLEEP_LENGTH)
1977 "Failed SB[0x%08x] still appearing in WRITE_DONE_PENDING\n",
1980 /* Clear the CAU for the SB */
1981 for (pi = 0; pi < 12; pi++)
1982 qed_wr(p_hwfn, p_ptt,
1983 CAU_REG_PI_MEMORY + (igu_sb_id * 12 + pi) * 4, 0);
1986 void qed_int_igu_init_pure_rt(struct qed_hwfn *p_hwfn,
1987 struct qed_ptt *p_ptt,
1988 bool b_set, bool b_slowpath)
1990 struct qed_igu_info *p_info = p_hwfn->hw_info.p_igu_info;
1991 struct qed_igu_block *p_block;
1995 val = qed_rd(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION);
1996 val |= IGU_REG_BLOCK_CONFIGURATION_VF_CLEANUP_EN;
1997 val &= ~IGU_REG_BLOCK_CONFIGURATION_PXP_TPH_INTERFACE_EN;
1998 qed_wr(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION, val);
2001 igu_sb_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev); igu_sb_id++) {
2002 p_block = &p_info->entry[igu_sb_id];
2004 if (!(p_block->status & QED_IGU_STATUS_VALID) ||
2006 (p_block->status & QED_IGU_STATUS_DSB))
2009 qed_int_igu_init_pure_rt_single(p_hwfn, p_ptt, igu_sb_id,
2010 p_hwfn->hw_info.opaque_fid,
2015 qed_int_igu_init_pure_rt_single(p_hwfn, p_ptt,
2017 p_hwfn->hw_info.opaque_fid,
2021 int qed_int_igu_reset_cam(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2023 struct qed_igu_info *p_info = p_hwfn->hw_info.p_igu_info;
2024 struct qed_igu_block *p_block;
2029 if (!RESC_NUM(p_hwfn, QED_SB)) {
2030 p_info->b_allow_pf_vf_change = false;
2032 /* Use the numbers the MFW have provided -
2033 * don't forget MFW accounts for the default SB as well.
2035 p_info->b_allow_pf_vf_change = true;
2037 if (p_info->usage.cnt != RESC_NUM(p_hwfn, QED_SB) - 1) {
2039 "MFW notifies of 0x%04x PF SBs; IGU indicates of only 0x%04x\n",
2040 RESC_NUM(p_hwfn, QED_SB) - 1,
2042 p_info->usage.cnt = RESC_NUM(p_hwfn, QED_SB) - 1;
2045 if (IS_PF_SRIOV(p_hwfn)) {
2046 u16 vfs = p_hwfn->cdev->p_iov_info->total_vfs;
2048 if (vfs != p_info->usage.iov_cnt)
2051 "0x%04x VF SBs in IGU CAM != PCI configuration 0x%04x\n",
2052 p_info->usage.iov_cnt, vfs);
2054 /* At this point we know how many SBs we have totally
2055 * in IGU + number of PF SBs. So we can validate that
2056 * we'd have sufficient for VF.
2058 if (vfs > p_info->usage.free_cnt +
2059 p_info->usage.free_cnt_iov - p_info->usage.cnt) {
2061 "Not enough SBs for VFs - 0x%04x SBs, from which %04x PFs and %04x are required\n",
2062 p_info->usage.free_cnt +
2063 p_info->usage.free_cnt_iov,
2064 p_info->usage.cnt, vfs);
2068 /* Currently cap the number of VFs SBs by the
2071 p_info->usage.iov_cnt = vfs;
2075 /* Mark all SBs as free, now in the right PF/VFs division */
2076 p_info->usage.free_cnt = p_info->usage.cnt;
2077 p_info->usage.free_cnt_iov = p_info->usage.iov_cnt;
2078 p_info->usage.orig = p_info->usage.cnt;
2079 p_info->usage.iov_orig = p_info->usage.iov_cnt;
2081 /* We now proceed to re-configure the IGU cam to reflect the initial
2082 * configuration. We can start with the Default SB.
2084 pf_sbs = p_info->usage.cnt;
2085 vf_sbs = p_info->usage.iov_cnt;
2087 for (igu_sb_id = p_info->igu_dsb_id;
2088 igu_sb_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev); igu_sb_id++) {
2089 p_block = &p_info->entry[igu_sb_id];
2092 if (!(p_block->status & QED_IGU_STATUS_VALID))
2095 if (p_block->status & QED_IGU_STATUS_DSB) {
2096 p_block->function_id = p_hwfn->rel_pf_id;
2098 p_block->vector_number = 0;
2099 p_block->status = QED_IGU_STATUS_VALID |
2102 } else if (pf_sbs) {
2104 p_block->function_id = p_hwfn->rel_pf_id;
2106 p_block->vector_number = p_info->usage.cnt - pf_sbs;
2107 p_block->status = QED_IGU_STATUS_VALID |
2109 QED_IGU_STATUS_FREE;
2110 } else if (vf_sbs) {
2111 p_block->function_id =
2112 p_hwfn->cdev->p_iov_info->first_vf_in_pf +
2113 p_info->usage.iov_cnt - vf_sbs;
2115 p_block->vector_number = 0;
2116 p_block->status = QED_IGU_STATUS_VALID |
2117 QED_IGU_STATUS_FREE;
2120 p_block->function_id = 0;
2122 p_block->vector_number = 0;
2125 SET_FIELD(val, IGU_MAPPING_LINE_FUNCTION_NUMBER,
2126 p_block->function_id);
2127 SET_FIELD(val, IGU_MAPPING_LINE_PF_VALID, p_block->is_pf);
2128 SET_FIELD(val, IGU_MAPPING_LINE_VECTOR_NUMBER,
2129 p_block->vector_number);
2131 /* VF entries would be enabled when VF is initializaed */
2132 SET_FIELD(val, IGU_MAPPING_LINE_VALID, p_block->is_pf);
2134 rval = qed_rd(p_hwfn, p_ptt,
2135 IGU_REG_MAPPING_MEMORY + sizeof(u32) * igu_sb_id);
2138 qed_wr(p_hwfn, p_ptt,
2139 IGU_REG_MAPPING_MEMORY +
2140 sizeof(u32) * igu_sb_id, val);
2144 "IGU reset: [SB 0x%04x] func_id = %d is_pf = %d vector_num = 0x%x [%08x -> %08x]\n",
2146 p_block->function_id,
2148 p_block->vector_number, rval, val);
2155 static void qed_int_igu_read_cam_block(struct qed_hwfn *p_hwfn,
2156 struct qed_ptt *p_ptt, u16 igu_sb_id)
2158 u32 val = qed_rd(p_hwfn, p_ptt,
2159 IGU_REG_MAPPING_MEMORY + sizeof(u32) * igu_sb_id);
2160 struct qed_igu_block *p_block;
2162 p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_sb_id];
2164 /* Fill the block information */
2165 p_block->function_id = GET_FIELD(val, IGU_MAPPING_LINE_FUNCTION_NUMBER);
2166 p_block->is_pf = GET_FIELD(val, IGU_MAPPING_LINE_PF_VALID);
2167 p_block->vector_number = GET_FIELD(val, IGU_MAPPING_LINE_VECTOR_NUMBER);
2168 p_block->igu_sb_id = igu_sb_id;
2171 int qed_int_igu_read_cam(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2173 struct qed_igu_info *p_igu_info;
2174 struct qed_igu_block *p_block;
2175 u32 min_vf = 0, max_vf = 0;
2178 p_hwfn->hw_info.p_igu_info = kzalloc(sizeof(*p_igu_info), GFP_KERNEL);
2179 if (!p_hwfn->hw_info.p_igu_info)
2182 p_igu_info = p_hwfn->hw_info.p_igu_info;
2184 /* Distinguish between existent and non-existent default SB */
2185 p_igu_info->igu_dsb_id = QED_SB_INVALID_IDX;
2187 /* Find the range of VF ids whose SB belong to this PF */
2188 if (p_hwfn->cdev->p_iov_info) {
2189 struct qed_hw_sriov_info *p_iov = p_hwfn->cdev->p_iov_info;
2191 min_vf = p_iov->first_vf_in_pf;
2192 max_vf = p_iov->first_vf_in_pf + p_iov->total_vfs;
2196 igu_sb_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev); igu_sb_id++) {
2197 /* Read current entry; Notice it might not belong to this PF */
2198 qed_int_igu_read_cam_block(p_hwfn, p_ptt, igu_sb_id);
2199 p_block = &p_igu_info->entry[igu_sb_id];
2201 if ((p_block->is_pf) &&
2202 (p_block->function_id == p_hwfn->rel_pf_id)) {
2203 p_block->status = QED_IGU_STATUS_PF |
2204 QED_IGU_STATUS_VALID |
2205 QED_IGU_STATUS_FREE;
2207 if (p_igu_info->igu_dsb_id != QED_SB_INVALID_IDX)
2208 p_igu_info->usage.cnt++;
2209 } else if (!(p_block->is_pf) &&
2210 (p_block->function_id >= min_vf) &&
2211 (p_block->function_id < max_vf)) {
2212 /* Available for VFs of this PF */
2213 p_block->status = QED_IGU_STATUS_VALID |
2214 QED_IGU_STATUS_FREE;
2216 if (p_igu_info->igu_dsb_id != QED_SB_INVALID_IDX)
2217 p_igu_info->usage.iov_cnt++;
2220 /* Mark the First entry belonging to the PF or its VFs
2221 * as the default SB [we'll reset IGU prior to first usage].
2223 if ((p_block->status & QED_IGU_STATUS_VALID) &&
2224 (p_igu_info->igu_dsb_id == QED_SB_INVALID_IDX)) {
2225 p_igu_info->igu_dsb_id = igu_sb_id;
2226 p_block->status |= QED_IGU_STATUS_DSB;
2229 /* limit number of prints by having each PF print only its
2230 * entries with the exception of PF0 which would print
2233 if ((p_block->status & QED_IGU_STATUS_VALID) ||
2234 (p_hwfn->abs_pf_id == 0)) {
2235 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
2236 "IGU_BLOCK: [SB 0x%04x] func_id = %d is_pf = %d vector_num = 0x%x\n",
2237 igu_sb_id, p_block->function_id,
2238 p_block->is_pf, p_block->vector_number);
2242 if (p_igu_info->igu_dsb_id == QED_SB_INVALID_IDX) {
2244 "IGU CAM returned invalid values igu_dsb_id=0x%x\n",
2245 p_igu_info->igu_dsb_id);
2249 /* All non default SB are considered free at this point */
2250 p_igu_info->usage.free_cnt = p_igu_info->usage.cnt;
2251 p_igu_info->usage.free_cnt_iov = p_igu_info->usage.iov_cnt;
2253 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
2254 "igu_dsb_id=0x%x, num Free SBs - PF: %04x VF: %04x [might change after resource allocation]\n",
2255 p_igu_info->igu_dsb_id,
2256 p_igu_info->usage.cnt, p_igu_info->usage.iov_cnt);
2262 * @brief Initialize igu runtime registers
2266 void qed_int_igu_init_rt(struct qed_hwfn *p_hwfn)
2268 u32 igu_pf_conf = IGU_PF_CONF_FUNC_EN;
2270 STORE_RT_REG(p_hwfn, IGU_REG_PF_CONFIGURATION_RT_OFFSET, igu_pf_conf);
2273 u64 qed_int_igu_read_sisr_reg(struct qed_hwfn *p_hwfn)
2275 u32 lsb_igu_cmd_addr = IGU_REG_SISR_MDPC_WMASK_LSB_UPPER -
2276 IGU_CMD_INT_ACK_BASE;
2277 u32 msb_igu_cmd_addr = IGU_REG_SISR_MDPC_WMASK_MSB_UPPER -
2278 IGU_CMD_INT_ACK_BASE;
2279 u32 intr_status_hi = 0, intr_status_lo = 0;
2280 u64 intr_status = 0;
2282 intr_status_lo = REG_RD(p_hwfn,
2283 GTT_BAR0_MAP_REG_IGU_CMD +
2284 lsb_igu_cmd_addr * 8);
2285 intr_status_hi = REG_RD(p_hwfn,
2286 GTT_BAR0_MAP_REG_IGU_CMD +
2287 msb_igu_cmd_addr * 8);
2288 intr_status = ((u64)intr_status_hi << 32) + (u64)intr_status_lo;
2293 static void qed_int_sp_dpc_setup(struct qed_hwfn *p_hwfn)
2295 tasklet_init(p_hwfn->sp_dpc,
2296 qed_int_sp_dpc, (unsigned long)p_hwfn);
2297 p_hwfn->b_sp_dpc_enabled = true;
2300 static int qed_int_sp_dpc_alloc(struct qed_hwfn *p_hwfn)
2302 p_hwfn->sp_dpc = kmalloc(sizeof(*p_hwfn->sp_dpc), GFP_KERNEL);
2303 if (!p_hwfn->sp_dpc)
2309 static void qed_int_sp_dpc_free(struct qed_hwfn *p_hwfn)
2311 kfree(p_hwfn->sp_dpc);
2312 p_hwfn->sp_dpc = NULL;
2315 int qed_int_alloc(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2319 rc = qed_int_sp_dpc_alloc(p_hwfn);
2323 rc = qed_int_sp_sb_alloc(p_hwfn, p_ptt);
2327 rc = qed_int_sb_attn_alloc(p_hwfn, p_ptt);
2332 void qed_int_free(struct qed_hwfn *p_hwfn)
2334 qed_int_sp_sb_free(p_hwfn);
2335 qed_int_sb_attn_free(p_hwfn);
2336 qed_int_sp_dpc_free(p_hwfn);
2339 void qed_int_setup(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2341 qed_int_sb_setup(p_hwfn, p_ptt, &p_hwfn->p_sp_sb->sb_info);
2342 qed_int_sb_attn_setup(p_hwfn, p_ptt);
2343 qed_int_sp_dpc_setup(p_hwfn);
2346 void qed_int_get_num_sbs(struct qed_hwfn *p_hwfn,
2347 struct qed_sb_cnt_info *p_sb_cnt_info)
2349 struct qed_igu_info *info = p_hwfn->hw_info.p_igu_info;
2351 if (!info || !p_sb_cnt_info)
2354 memcpy(p_sb_cnt_info, &info->usage, sizeof(*p_sb_cnt_info));
2357 void qed_int_disable_post_isr_release(struct qed_dev *cdev)
2361 for_each_hwfn(cdev, i)
2362 cdev->hwfns[i].b_int_requested = false;
2365 int qed_int_set_timer_res(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
2366 u8 timer_res, u16 sb_id, bool tx)
2368 struct cau_sb_entry sb_entry;
2371 if (!p_hwfn->hw_init_done) {
2372 DP_ERR(p_hwfn, "hardware not initialized yet\n");
2376 rc = qed_dmae_grc2host(p_hwfn, p_ptt, CAU_REG_SB_VAR_MEMORY +
2377 sb_id * sizeof(u64),
2378 (u64)(uintptr_t)&sb_entry, 2, 0);
2380 DP_ERR(p_hwfn, "dmae_grc2host failed %d\n", rc);
2385 SET_FIELD(sb_entry.params, CAU_SB_ENTRY_TIMER_RES1, timer_res);
2387 SET_FIELD(sb_entry.params, CAU_SB_ENTRY_TIMER_RES0, timer_res);
2389 rc = qed_dmae_host2grc(p_hwfn, p_ptt,
2390 (u64)(uintptr_t)&sb_entry,
2391 CAU_REG_SB_VAR_MEMORY +
2392 sb_id * sizeof(u64), 2, 0);
2394 DP_ERR(p_hwfn, "dmae_host2grc failed %d\n", rc);