1 /* QLogic qed NIC Driver
2 * Copyright (c) 2015 QLogic Corporation
4 * This software is available under the terms of the GNU General Public License
5 * (GPL) Version 2, available from the file COPYING in the main directory of
12 #include <linux/types.h>
14 #include <linux/bitops.h>
15 #include <linux/delay.h>
16 #include <linux/kernel.h>
17 #include <linux/list.h>
18 #include <linux/slab.h>
19 #include <linux/qed/common_hsi.h>
20 #include <linux/qed/eth_common.h>
24 /********************************/
25 /* Add include to common target */
26 /********************************/
28 /* opcodes for the event ring */
29 enum common_event_opcode {
30 COMMON_EVENT_PF_START,
32 COMMON_EVENT_VF_START,
33 COMMON_EVENT_RESERVED2,
34 COMMON_EVENT_VF_PF_CHANNEL,
35 COMMON_EVENT_RESERVED4,
36 COMMON_EVENT_RESERVED5,
37 COMMON_EVENT_RESERVED6,
39 MAX_COMMON_EVENT_OPCODE
42 /* Common Ramrod Command IDs */
43 enum common_ramrod_cmd_id {
45 COMMON_RAMROD_PF_START /* PF Function Start Ramrod */,
46 COMMON_RAMROD_PF_STOP /* PF Function Stop Ramrod */,
47 COMMON_RAMROD_VF_START,
48 COMMON_RAMROD_RESERVED2,
49 COMMON_RAMROD_PF_UPDATE,
51 MAX_COMMON_RAMROD_CMD_ID
54 /* The core storm context for the Ystorm */
55 struct ystorm_core_conn_st_ctx {
59 /* The core storm context for the Pstorm */
60 struct pstorm_core_conn_st_ctx {
64 /* Core Slowpath Connection storm context of Xstorm */
65 struct xstorm_core_conn_st_ctx {
66 __le32 spq_base_lo /* SPQ Ring Base Address low dword */;
67 __le32 spq_base_hi /* SPQ Ring Base Address high dword */;
68 struct regpair consolid_base_addr;
69 __le16 spq_cons /* SPQ Ring Consumer */;
70 __le16 consolid_cons /* Consolidation Ring Consumer */;
71 __le32 reserved0[55] /* Pad to 15 cycles */;
74 struct xstorm_core_conn_ag_ctx {
75 u8 reserved0 /* cdu_validation */;
76 u8 core_state /* state */;
78 #define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
79 #define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
80 #define XSTORM_CORE_CONN_AG_CTX_RESERVED1_MASK 0x1
81 #define XSTORM_CORE_CONN_AG_CTX_RESERVED1_SHIFT 1
82 #define XSTORM_CORE_CONN_AG_CTX_RESERVED2_MASK 0x1
83 #define XSTORM_CORE_CONN_AG_CTX_RESERVED2_SHIFT 2
84 #define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
85 #define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
86 #define XSTORM_CORE_CONN_AG_CTX_RESERVED3_MASK 0x1
87 #define XSTORM_CORE_CONN_AG_CTX_RESERVED3_SHIFT 4
88 #define XSTORM_CORE_CONN_AG_CTX_RESERVED4_MASK 0x1
89 #define XSTORM_CORE_CONN_AG_CTX_RESERVED4_SHIFT 5
90 #define XSTORM_CORE_CONN_AG_CTX_RESERVED5_MASK 0x1 /* bit6 */
91 #define XSTORM_CORE_CONN_AG_CTX_RESERVED5_SHIFT 6
92 #define XSTORM_CORE_CONN_AG_CTX_RESERVED6_MASK 0x1 /* bit7 */
93 #define XSTORM_CORE_CONN_AG_CTX_RESERVED6_SHIFT 7
95 #define XSTORM_CORE_CONN_AG_CTX_RESERVED7_MASK 0x1 /* bit8 */
96 #define XSTORM_CORE_CONN_AG_CTX_RESERVED7_SHIFT 0
97 #define XSTORM_CORE_CONN_AG_CTX_RESERVED8_MASK 0x1 /* bit9 */
98 #define XSTORM_CORE_CONN_AG_CTX_RESERVED8_SHIFT 1
99 #define XSTORM_CORE_CONN_AG_CTX_RESERVED9_MASK 0x1 /* bit10 */
100 #define XSTORM_CORE_CONN_AG_CTX_RESERVED9_SHIFT 2
101 #define XSTORM_CORE_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */
102 #define XSTORM_CORE_CONN_AG_CTX_BIT11_SHIFT 3
103 #define XSTORM_CORE_CONN_AG_CTX_BIT12_MASK 0x1 /* bit12 */
104 #define XSTORM_CORE_CONN_AG_CTX_BIT12_SHIFT 4
105 #define XSTORM_CORE_CONN_AG_CTX_BIT13_MASK 0x1 /* bit13 */
106 #define XSTORM_CORE_CONN_AG_CTX_BIT13_SHIFT 5
107 #define XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1 /* bit14 */
108 #define XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6
109 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1 /* bit15 */
110 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7
112 #define XSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */
113 #define XSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 0
114 #define XSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */
115 #define XSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 2
116 #define XSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */
117 #define XSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 4
118 #define XSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3
119 #define XSTORM_CORE_CONN_AG_CTX_CF3_SHIFT 6
121 #define XSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */
122 #define XSTORM_CORE_CONN_AG_CTX_CF4_SHIFT 0
123 #define XSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */
124 #define XSTORM_CORE_CONN_AG_CTX_CF5_SHIFT 2
125 #define XSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */
126 #define XSTORM_CORE_CONN_AG_CTX_CF6_SHIFT 4
127 #define XSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */
128 #define XSTORM_CORE_CONN_AG_CTX_CF7_SHIFT 6
130 #define XSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */
131 #define XSTORM_CORE_CONN_AG_CTX_CF8_SHIFT 0
132 #define XSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */
133 #define XSTORM_CORE_CONN_AG_CTX_CF9_SHIFT 2
134 #define XSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */
135 #define XSTORM_CORE_CONN_AG_CTX_CF10_SHIFT 4
136 #define XSTORM_CORE_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */
137 #define XSTORM_CORE_CONN_AG_CTX_CF11_SHIFT 6
139 #define XSTORM_CORE_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */
140 #define XSTORM_CORE_CONN_AG_CTX_CF12_SHIFT 0
141 #define XSTORM_CORE_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */
142 #define XSTORM_CORE_CONN_AG_CTX_CF13_SHIFT 2
143 #define XSTORM_CORE_CONN_AG_CTX_CF14_MASK 0x3 /* cf14 */
144 #define XSTORM_CORE_CONN_AG_CTX_CF14_SHIFT 4
145 #define XSTORM_CORE_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */
146 #define XSTORM_CORE_CONN_AG_CTX_CF15_SHIFT 6
148 #define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_MASK 0x3 /* cf16 */
149 #define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_SHIFT 0
150 #define XSTORM_CORE_CONN_AG_CTX_CF17_MASK 0x3
151 #define XSTORM_CORE_CONN_AG_CTX_CF17_SHIFT 2
152 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_MASK 0x3 /* cf18 */
153 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_SHIFT 4
154 #define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_MASK 0x3 /* cf19 */
155 #define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_SHIFT 6
157 #define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 /* cf20 */
158 #define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
159 #define XSTORM_CORE_CONN_AG_CTX_RESERVED10_MASK 0x3 /* cf21 */
160 #define XSTORM_CORE_CONN_AG_CTX_RESERVED10_SHIFT 2
161 #define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */
162 #define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_SHIFT 4
163 #define XSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
164 #define XSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 6
165 #define XSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
166 #define XSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 7
168 #define XSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
169 #define XSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 0
170 #define XSTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */
171 #define XSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 1
172 #define XSTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */
173 #define XSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 2
174 #define XSTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */
175 #define XSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 3
176 #define XSTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */
177 #define XSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 4
178 #define XSTORM_CORE_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */
179 #define XSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT 5
180 #define XSTORM_CORE_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */
181 #define XSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT 6
182 #define XSTORM_CORE_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */
183 #define XSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT 7
185 #define XSTORM_CORE_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */
186 #define XSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT 0
187 #define XSTORM_CORE_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */
188 #define XSTORM_CORE_CONN_AG_CTX_CF11EN_SHIFT 1
189 #define XSTORM_CORE_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */
190 #define XSTORM_CORE_CONN_AG_CTX_CF12EN_SHIFT 2
191 #define XSTORM_CORE_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */
192 #define XSTORM_CORE_CONN_AG_CTX_CF13EN_SHIFT 3
193 #define XSTORM_CORE_CONN_AG_CTX_CF14EN_MASK 0x1 /* cf14en */
194 #define XSTORM_CORE_CONN_AG_CTX_CF14EN_SHIFT 4
195 #define XSTORM_CORE_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */
196 #define XSTORM_CORE_CONN_AG_CTX_CF15EN_SHIFT 5
197 #define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_MASK 0x1 /* cf16en */
198 #define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_SHIFT 6
199 #define XSTORM_CORE_CONN_AG_CTX_CF17EN_MASK 0x1
200 #define XSTORM_CORE_CONN_AG_CTX_CF17EN_SHIFT 7
202 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_MASK 0x1 /* cf18en */
203 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_SHIFT 0
204 #define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1 /* cf19en */
205 #define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1
206 #define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 /* cf20en */
207 #define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
208 #define XSTORM_CORE_CONN_AG_CTX_RESERVED11_MASK 0x1 /* cf21en */
209 #define XSTORM_CORE_CONN_AG_CTX_RESERVED11_SHIFT 3
210 #define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */
211 #define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
212 #define XSTORM_CORE_CONN_AG_CTX_CF23EN_MASK 0x1 /* cf23en */
213 #define XSTORM_CORE_CONN_AG_CTX_CF23EN_SHIFT 5
214 #define XSTORM_CORE_CONN_AG_CTX_RESERVED12_MASK 0x1 /* rule0en */
215 #define XSTORM_CORE_CONN_AG_CTX_RESERVED12_SHIFT 6
216 #define XSTORM_CORE_CONN_AG_CTX_RESERVED13_MASK 0x1 /* rule1en */
217 #define XSTORM_CORE_CONN_AG_CTX_RESERVED13_SHIFT 7
219 #define XSTORM_CORE_CONN_AG_CTX_RESERVED14_MASK 0x1 /* rule2en */
220 #define XSTORM_CORE_CONN_AG_CTX_RESERVED14_SHIFT 0
221 #define XSTORM_CORE_CONN_AG_CTX_RESERVED15_MASK 0x1 /* rule3en */
222 #define XSTORM_CORE_CONN_AG_CTX_RESERVED15_SHIFT 1
223 #define XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1 /* rule4en */
224 #define XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2
225 #define XSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
226 #define XSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 3
227 #define XSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */
228 #define XSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 4
229 #define XSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */
230 #define XSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 5
231 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */
232 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
233 #define XSTORM_CORE_CONN_AG_CTX_RULE9EN_MASK 0x1 /* rule9en */
234 #define XSTORM_CORE_CONN_AG_CTX_RULE9EN_SHIFT 7
236 #define XSTORM_CORE_CONN_AG_CTX_RULE10EN_MASK 0x1 /* rule10en */
237 #define XSTORM_CORE_CONN_AG_CTX_RULE10EN_SHIFT 0
238 #define XSTORM_CORE_CONN_AG_CTX_RULE11EN_MASK 0x1 /* rule11en */
239 #define XSTORM_CORE_CONN_AG_CTX_RULE11EN_SHIFT 1
240 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */
241 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
242 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */
243 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
244 #define XSTORM_CORE_CONN_AG_CTX_RULE14EN_MASK 0x1 /* rule14en */
245 #define XSTORM_CORE_CONN_AG_CTX_RULE14EN_SHIFT 4
246 #define XSTORM_CORE_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */
247 #define XSTORM_CORE_CONN_AG_CTX_RULE15EN_SHIFT 5
248 #define XSTORM_CORE_CONN_AG_CTX_RULE16EN_MASK 0x1 /* rule16en */
249 #define XSTORM_CORE_CONN_AG_CTX_RULE16EN_SHIFT 6
250 #define XSTORM_CORE_CONN_AG_CTX_RULE17EN_MASK 0x1 /* rule17en */
251 #define XSTORM_CORE_CONN_AG_CTX_RULE17EN_SHIFT 7
253 #define XSTORM_CORE_CONN_AG_CTX_RULE18EN_MASK 0x1 /* rule18en */
254 #define XSTORM_CORE_CONN_AG_CTX_RULE18EN_SHIFT 0
255 #define XSTORM_CORE_CONN_AG_CTX_RULE19EN_MASK 0x1 /* rule19en */
256 #define XSTORM_CORE_CONN_AG_CTX_RULE19EN_SHIFT 1
257 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 /* rule20en */
258 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
259 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 /* rule21en */
260 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
261 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */
262 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
263 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 /* rule23en */
264 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
265 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */
266 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
267 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */
268 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
270 #define XSTORM_CORE_CONN_AG_CTX_BIT16_MASK 0x1 /* bit16 */
271 #define XSTORM_CORE_CONN_AG_CTX_BIT16_SHIFT 0
272 #define XSTORM_CORE_CONN_AG_CTX_BIT17_MASK 0x1 /* bit17 */
273 #define XSTORM_CORE_CONN_AG_CTX_BIT17_SHIFT 1
274 #define XSTORM_CORE_CONN_AG_CTX_BIT18_MASK 0x1 /* bit18 */
275 #define XSTORM_CORE_CONN_AG_CTX_BIT18_SHIFT 2
276 #define XSTORM_CORE_CONN_AG_CTX_BIT19_MASK 0x1 /* bit19 */
277 #define XSTORM_CORE_CONN_AG_CTX_BIT19_SHIFT 3
278 #define XSTORM_CORE_CONN_AG_CTX_BIT20_MASK 0x1 /* bit20 */
279 #define XSTORM_CORE_CONN_AG_CTX_BIT20_SHIFT 4
280 #define XSTORM_CORE_CONN_AG_CTX_BIT21_MASK 0x1 /* bit21 */
281 #define XSTORM_CORE_CONN_AG_CTX_BIT21_SHIFT 5
282 #define XSTORM_CORE_CONN_AG_CTX_CF23_MASK 0x3 /* cf23 */
283 #define XSTORM_CORE_CONN_AG_CTX_CF23_SHIFT 6
284 u8 byte2 /* byte2 */;
285 __le16 physical_q0 /* physical_q0 */;
286 __le16 consolid_prod /* physical_q1 */;
287 __le16 reserved16 /* physical_q2 */;
288 __le16 tx_bd_cons /* word3 */;
289 __le16 tx_bd_or_spq_prod /* word4 */;
290 __le16 word5 /* word5 */;
291 __le16 conn_dpi /* conn_dpi */;
292 u8 byte3 /* byte3 */;
293 u8 byte4 /* byte4 */;
294 u8 byte5 /* byte5 */;
295 u8 byte6 /* byte6 */;
296 __le32 reg0 /* reg0 */;
297 __le32 reg1 /* reg1 */;
298 __le32 reg2 /* reg2 */;
299 __le32 reg3 /* reg3 */;
300 __le32 reg4 /* reg4 */;
301 __le32 reg5 /* cf_array0 */;
302 __le32 reg6 /* cf_array1 */;
303 __le16 word7 /* word7 */;
304 __le16 word8 /* word8 */;
305 __le16 word9 /* word9 */;
306 __le16 word10 /* word10 */;
307 __le32 reg7 /* reg7 */;
308 __le32 reg8 /* reg8 */;
309 __le32 reg9 /* reg9 */;
310 u8 byte7 /* byte7 */;
311 u8 byte8 /* byte8 */;
312 u8 byte9 /* byte9 */;
313 u8 byte10 /* byte10 */;
314 u8 byte11 /* byte11 */;
315 u8 byte12 /* byte12 */;
316 u8 byte13 /* byte13 */;
317 u8 byte14 /* byte14 */;
318 u8 byte15 /* byte15 */;
319 u8 byte16 /* byte16 */;
320 __le16 word11 /* word11 */;
321 __le32 reg10 /* reg10 */;
322 __le32 reg11 /* reg11 */;
323 __le32 reg12 /* reg12 */;
324 __le32 reg13 /* reg13 */;
325 __le32 reg14 /* reg14 */;
326 __le32 reg15 /* reg15 */;
327 __le32 reg16 /* reg16 */;
328 __le32 reg17 /* reg17 */;
329 __le32 reg18 /* reg18 */;
330 __le32 reg19 /* reg19 */;
331 __le16 word12 /* word12 */;
332 __le16 word13 /* word13 */;
333 __le16 word14 /* word14 */;
334 __le16 word15 /* word15 */;
337 struct tstorm_core_conn_ag_ctx {
338 u8 byte0 /* cdu_validation */;
339 u8 byte1 /* state */;
341 #define TSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */
342 #define TSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
343 #define TSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
344 #define TSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1
345 #define TSTORM_CORE_CONN_AG_CTX_BIT2_MASK 0x1 /* bit2 */
346 #define TSTORM_CORE_CONN_AG_CTX_BIT2_SHIFT 2
347 #define TSTORM_CORE_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */
348 #define TSTORM_CORE_CONN_AG_CTX_BIT3_SHIFT 3
349 #define TSTORM_CORE_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */
350 #define TSTORM_CORE_CONN_AG_CTX_BIT4_SHIFT 4
351 #define TSTORM_CORE_CONN_AG_CTX_BIT5_MASK 0x1 /* bit5 */
352 #define TSTORM_CORE_CONN_AG_CTX_BIT5_SHIFT 5
353 #define TSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */
354 #define TSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 6
356 #define TSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */
357 #define TSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 0
358 #define TSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */
359 #define TSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 2
360 #define TSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */
361 #define TSTORM_CORE_CONN_AG_CTX_CF3_SHIFT 4
362 #define TSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */
363 #define TSTORM_CORE_CONN_AG_CTX_CF4_SHIFT 6
365 #define TSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */
366 #define TSTORM_CORE_CONN_AG_CTX_CF5_SHIFT 0
367 #define TSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */
368 #define TSTORM_CORE_CONN_AG_CTX_CF6_SHIFT 2
369 #define TSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */
370 #define TSTORM_CORE_CONN_AG_CTX_CF7_SHIFT 4
371 #define TSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */
372 #define TSTORM_CORE_CONN_AG_CTX_CF8_SHIFT 6
374 #define TSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */
375 #define TSTORM_CORE_CONN_AG_CTX_CF9_SHIFT 0
376 #define TSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */
377 #define TSTORM_CORE_CONN_AG_CTX_CF10_SHIFT 2
378 #define TSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
379 #define TSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 4
380 #define TSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
381 #define TSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 5
382 #define TSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
383 #define TSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 6
384 #define TSTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */
385 #define TSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 7
387 #define TSTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */
388 #define TSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 0
389 #define TSTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */
390 #define TSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 1
391 #define TSTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */
392 #define TSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 2
393 #define TSTORM_CORE_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */
394 #define TSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT 3
395 #define TSTORM_CORE_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */
396 #define TSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT 4
397 #define TSTORM_CORE_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */
398 #define TSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT 5
399 #define TSTORM_CORE_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */
400 #define TSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT 6
401 #define TSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
402 #define TSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 7
404 #define TSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
405 #define TSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0
406 #define TSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
407 #define TSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 1
408 #define TSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
409 #define TSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 2
410 #define TSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
411 #define TSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 3
412 #define TSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
413 #define TSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 4
414 #define TSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */
415 #define TSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 5
416 #define TSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */
417 #define TSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 6
418 #define TSTORM_CORE_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */
419 #define TSTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT 7
420 __le32 reg0 /* reg0 */;
421 __le32 reg1 /* reg1 */;
422 __le32 reg2 /* reg2 */;
423 __le32 reg3 /* reg3 */;
424 __le32 reg4 /* reg4 */;
425 __le32 reg5 /* reg5 */;
426 __le32 reg6 /* reg6 */;
427 __le32 reg7 /* reg7 */;
428 __le32 reg8 /* reg8 */;
429 u8 byte2 /* byte2 */;
430 u8 byte3 /* byte3 */;
431 __le16 word0 /* word0 */;
432 u8 byte4 /* byte4 */;
433 u8 byte5 /* byte5 */;
434 __le16 word1 /* word1 */;
435 __le16 word2 /* conn_dpi */;
436 __le16 word3 /* word3 */;
437 __le32 reg9 /* reg9 */;
438 __le32 reg10 /* reg10 */;
441 struct ustorm_core_conn_ag_ctx {
442 u8 reserved /* cdu_validation */;
443 u8 byte1 /* state */;
445 #define USTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */
446 #define USTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
447 #define USTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
448 #define USTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1
449 #define USTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */
450 #define USTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2
451 #define USTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */
452 #define USTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4
453 #define USTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */
454 #define USTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6
456 #define USTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */
457 #define USTORM_CORE_CONN_AG_CTX_CF3_SHIFT 0
458 #define USTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */
459 #define USTORM_CORE_CONN_AG_CTX_CF4_SHIFT 2
460 #define USTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */
461 #define USTORM_CORE_CONN_AG_CTX_CF5_SHIFT 4
462 #define USTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */
463 #define USTORM_CORE_CONN_AG_CTX_CF6_SHIFT 6
465 #define USTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
466 #define USTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0
467 #define USTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
468 #define USTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1
469 #define USTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
470 #define USTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2
471 #define USTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */
472 #define USTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 3
473 #define USTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */
474 #define USTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 4
475 #define USTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */
476 #define USTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 5
477 #define USTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */
478 #define USTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 6
479 #define USTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
480 #define USTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 7
482 #define USTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
483 #define USTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0
484 #define USTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
485 #define USTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 1
486 #define USTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
487 #define USTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 2
488 #define USTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
489 #define USTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 3
490 #define USTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
491 #define USTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 4
492 #define USTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */
493 #define USTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 5
494 #define USTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */
495 #define USTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 6
496 #define USTORM_CORE_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */
497 #define USTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT 7
498 u8 byte2 /* byte2 */;
499 u8 byte3 /* byte3 */;
500 __le16 word0 /* conn_dpi */;
501 __le16 word1 /* word1 */;
502 __le32 rx_producers /* reg0 */;
503 __le32 reg1 /* reg1 */;
504 __le32 reg2 /* reg2 */;
505 __le32 reg3 /* reg3 */;
506 __le16 word2 /* word2 */;
507 __le16 word3 /* word3 */;
510 /* The core storm context for the Mstorm */
511 struct mstorm_core_conn_st_ctx {
515 /* The core storm context for the Ustorm */
516 struct ustorm_core_conn_st_ctx {
520 /* core connection context */
521 struct core_conn_context {
522 struct ystorm_core_conn_st_ctx ystorm_st_context;
523 struct regpair ystorm_st_padding[2] /* padding */;
524 struct pstorm_core_conn_st_ctx pstorm_st_context;
525 struct regpair pstorm_st_padding[2];
526 struct xstorm_core_conn_st_ctx xstorm_st_context;
527 struct xstorm_core_conn_ag_ctx xstorm_ag_context;
528 struct tstorm_core_conn_ag_ctx tstorm_ag_context;
529 struct ustorm_core_conn_ag_ctx ustorm_ag_context;
530 struct mstorm_core_conn_st_ctx mstorm_st_context;
531 struct ustorm_core_conn_st_ctx ustorm_st_context;
532 struct regpair ustorm_st_padding[2] /* padding */;
535 struct eth_mstorm_per_queue_stat {
536 struct regpair ttl0_discard;
537 struct regpair packet_too_big_discard;
538 struct regpair no_buff_discard;
539 struct regpair not_active_discard;
540 struct regpair tpa_coalesced_pkts;
541 struct regpair tpa_coalesced_events;
542 struct regpair tpa_aborts_num;
543 struct regpair tpa_coalesced_bytes;
546 struct eth_pstorm_per_queue_stat {
547 struct regpair sent_ucast_bytes;
548 struct regpair sent_mcast_bytes;
549 struct regpair sent_bcast_bytes;
550 struct regpair sent_ucast_pkts;
551 struct regpair sent_mcast_pkts;
552 struct regpair sent_bcast_pkts;
553 struct regpair error_drop_pkts;
556 struct eth_ustorm_per_queue_stat {
557 struct regpair rcv_ucast_bytes;
558 struct regpair rcv_mcast_bytes;
559 struct regpair rcv_bcast_bytes;
560 struct regpair rcv_ucast_pkts;
561 struct regpair rcv_mcast_pkts;
562 struct regpair rcv_bcast_pkts;
565 /* Event Ring Next Page Address */
566 struct event_ring_next_addr {
567 struct regpair addr /* Next Page Address */;
568 __le32 reserved[2] /* Reserved */;
571 union event_ring_element {
572 struct event_ring_entry entry /* Event Ring Entry */;
573 struct event_ring_next_addr next_addr;
576 struct mstorm_non_trigger_vf_zone {
577 struct eth_mstorm_per_queue_stat eth_queue_stat;
580 struct mstorm_vf_zone {
581 struct mstorm_non_trigger_vf_zone non_trigger;
584 enum personality_type {
586 PERSONALITY_RESERVED,
587 PERSONALITY_RESERVED2,
588 PERSONALITY_RDMA_AND_ETH /* Roce or Iwarp */,
589 PERSONALITY_RESERVED3,
591 PERSONALITY_ETH /* Ethernet */,
592 PERSONALITY_RESERVED4,
596 struct pf_start_tunnel_config {
597 u8 set_vxlan_udp_port_flg;
598 u8 set_geneve_udp_port_flg;
599 u8 tx_enable_vxlan /* If set, enable VXLAN tunnel in TX path. */;
600 u8 tx_enable_l2geneve;
601 u8 tx_enable_ipgeneve;
602 u8 tx_enable_l2gre /* If set, enable l2 GRE tunnel in TX path. */;
603 u8 tx_enable_ipgre /* If set, enable IP GRE tunnel in TX path. */;
604 u8 tunnel_clss_vxlan /* Classification scheme for VXLAN tunnel. */;
605 u8 tunnel_clss_l2geneve;
606 u8 tunnel_clss_ipgeneve;
607 u8 tunnel_clss_l2gre;
608 u8 tunnel_clss_ipgre;
609 __le16 vxlan_udp_port /* VXLAN tunnel UDP destination port. */;
610 __le16 geneve_udp_port /* GENEVE tunnel UDP destination port. */;
613 /* Ramrod data for PF start ramrod */
614 struct pf_start_ramrod_data {
615 struct regpair event_ring_pbl_addr;
616 struct regpair consolid_q_pbl_addr;
617 struct pf_start_tunnel_config tunnel_config;
618 __le16 event_ring_sb_id;
621 u8 event_ring_num_pages;
622 u8 event_ring_sb_index;
627 __le16 log_type_mask;
628 u8 mf_mode /* Multi function mode */;
629 u8 integ_phase /* Integration phase */;
630 u8 allow_npar_tx_switching;
631 u8 inner_to_outer_pri_map[8];
637 /* tunnel configuration */
638 struct pf_update_tunnel_config {
639 u8 update_rx_pf_clss;
640 u8 update_tx_pf_clss;
641 u8 set_vxlan_udp_port_flg;
642 u8 set_geneve_udp_port_flg;
644 u8 tx_enable_l2geneve;
645 u8 tx_enable_ipgeneve;
648 u8 tunnel_clss_vxlan;
649 u8 tunnel_clss_l2geneve;
650 u8 tunnel_clss_ipgeneve;
651 u8 tunnel_clss_l2gre;
652 u8 tunnel_clss_ipgre;
653 __le16 vxlan_udp_port;
654 __le16 geneve_udp_port;
658 struct pf_update_ramrod_data {
661 struct pf_update_tunnel_config tunnel_config;
664 /* Tunnel classification scheme */
666 TUNNEL_CLSS_MAC_VLAN = 0,
668 TUNNEL_CLSS_INNER_MAC_VLAN,
669 TUNNEL_CLSS_INNER_MAC_VNI,
674 ENGX2_PORTX1 /* 2 engines x 1 port */,
675 ENGX2_PORTX2 /* 2 engines x 2 ports */,
676 ENGX1_PORTX1 /* 1 engine x 1 port */,
677 ENGX1_PORTX2 /* 1 engine x 2 ports */,
678 ENGX1_PORTX4 /* 1 engine x 4 ports */,
682 struct pstorm_non_trigger_vf_zone {
683 struct eth_pstorm_per_queue_stat eth_queue_stat;
684 struct regpair reserved[2];
687 struct pstorm_vf_zone {
688 struct pstorm_non_trigger_vf_zone non_trigger;
689 struct regpair reserved[7];
692 /* Ramrod Header of SPQE */
693 struct ramrod_header {
694 __le32 cid /* Slowpath Connection CID */;
695 u8 cmd_id /* Ramrod Cmd (Per Protocol Type) */;
696 u8 protocol_id /* Ramrod Protocol ID */;
697 __le16 echo /* Ramrod echo */;
700 /* Slowpath Element (SPQE) */
701 struct slow_path_element {
702 struct ramrod_header hdr /* Ramrod Header */;
703 struct regpair data_ptr;
706 struct tstorm_per_port_stat {
707 struct regpair trunc_error_discard;
708 struct regpair mac_error_discard;
709 struct regpair mftag_filter_discard;
710 struct regpair eth_mac_filter_discard;
711 struct regpair ll2_mac_filter_discard;
712 struct regpair ll2_conn_disabled_discard;
713 struct regpair iscsi_irregular_pkt;
714 struct regpair fcoe_irregular_pkt;
715 struct regpair roce_irregular_pkt;
716 struct regpair eth_irregular_pkt;
717 struct regpair toe_irregular_pkt;
718 struct regpair preroce_irregular_pkt;
721 struct ustorm_non_trigger_vf_zone {
722 struct eth_ustorm_per_queue_stat eth_queue_stat;
723 struct regpair vf_pf_msg_addr;
726 struct ustorm_trigger_vf_zone {
731 struct ustorm_vf_zone {
732 struct ustorm_non_trigger_vf_zone non_trigger;
733 struct ustorm_trigger_vf_zone trigger;
736 struct vf_start_ramrod_data {
744 struct atten_status_block {
748 __le16 sb_index /* status block running index */;
753 GRCBASE_GRC = 0x50000,
754 GRCBASE_MISCS = 0x9000,
755 GRCBASE_MISC = 0x8000,
756 GRCBASE_DBU = 0xa000,
757 GRCBASE_PGLUE_B = 0x2a8000,
758 GRCBASE_CNIG = 0x218000,
759 GRCBASE_CPMU = 0x30000,
760 GRCBASE_NCSI = 0x40000,
761 GRCBASE_OPTE = 0x53000,
762 GRCBASE_BMB = 0x540000,
763 GRCBASE_PCIE = 0x54000,
764 GRCBASE_MCP = 0xe00000,
765 GRCBASE_MCP2 = 0x52000,
766 GRCBASE_PSWHST = 0x2a0000,
767 GRCBASE_PSWHST2 = 0x29e000,
768 GRCBASE_PSWRD = 0x29c000,
769 GRCBASE_PSWRD2 = 0x29d000,
770 GRCBASE_PSWWR = 0x29a000,
771 GRCBASE_PSWWR2 = 0x29b000,
772 GRCBASE_PSWRQ = 0x280000,
773 GRCBASE_PSWRQ2 = 0x240000,
775 GRCBASE_PTU = 0x560000,
776 GRCBASE_DMAE = 0xc000,
777 GRCBASE_TCM = 0x1180000,
778 GRCBASE_MCM = 0x1200000,
779 GRCBASE_UCM = 0x1280000,
780 GRCBASE_XCM = 0x1000000,
781 GRCBASE_YCM = 0x1080000,
782 GRCBASE_PCM = 0x1100000,
783 GRCBASE_QM = 0x2f0000,
784 GRCBASE_TM = 0x2c0000,
785 GRCBASE_DORQ = 0x100000,
786 GRCBASE_BRB = 0x340000,
787 GRCBASE_SRC = 0x238000,
788 GRCBASE_PRS = 0x1f0000,
789 GRCBASE_TSDM = 0xfb0000,
790 GRCBASE_MSDM = 0xfc0000,
791 GRCBASE_USDM = 0xfd0000,
792 GRCBASE_XSDM = 0xf80000,
793 GRCBASE_YSDM = 0xf90000,
794 GRCBASE_PSDM = 0xfa0000,
795 GRCBASE_TSEM = 0x1700000,
796 GRCBASE_MSEM = 0x1800000,
797 GRCBASE_USEM = 0x1900000,
798 GRCBASE_XSEM = 0x1400000,
799 GRCBASE_YSEM = 0x1500000,
800 GRCBASE_PSEM = 0x1600000,
801 GRCBASE_RSS = 0x238800,
802 GRCBASE_TMLD = 0x4d0000,
803 GRCBASE_MULD = 0x4e0000,
804 GRCBASE_YULD = 0x4c8000,
805 GRCBASE_XYLD = 0x4c0000,
806 GRCBASE_PRM = 0x230000,
807 GRCBASE_PBF_PB1 = 0xda0000,
808 GRCBASE_PBF_PB2 = 0xda4000,
809 GRCBASE_RPB = 0x23c000,
810 GRCBASE_BTB = 0xdb0000,
811 GRCBASE_PBF = 0xd80000,
812 GRCBASE_RDIF = 0x300000,
813 GRCBASE_TDIF = 0x310000,
814 GRCBASE_CDU = 0x580000,
815 GRCBASE_CCFC = 0x2e0000,
816 GRCBASE_TCFC = 0x2d0000,
817 GRCBASE_IGU = 0x180000,
818 GRCBASE_CAU = 0x1c0000,
819 GRCBASE_UMAC = 0x51000,
820 GRCBASE_XMAC = 0x210000,
821 GRCBASE_DBG = 0x10000,
822 GRCBASE_NIG = 0x500000,
823 GRCBASE_WOL = 0x600000,
824 GRCBASE_BMBN = 0x610000,
825 GRCBASE_IPC = 0x20000,
826 GRCBASE_NWM = 0x800000,
827 GRCBASE_NWS = 0x700000,
828 GRCBASE_MS = 0x6a0000,
829 GRCBASE_PHY_PCIE = 0x620000,
830 GRCBASE_MISC_AEU = 0x8000,
831 GRCBASE_BAR0_MAP = 0x1c00000,
918 enum command_type_bit {
919 IGU_COMMAND_TYPE_NOP = 0,
920 IGU_COMMAND_TYPE_SET = 1,
926 #define DMAE_CMD_SRC_MASK 0x1
927 #define DMAE_CMD_SRC_SHIFT 0
928 #define DMAE_CMD_DST_MASK 0x3
929 #define DMAE_CMD_DST_SHIFT 1
930 #define DMAE_CMD_C_DST_MASK 0x1
931 #define DMAE_CMD_C_DST_SHIFT 3
932 #define DMAE_CMD_CRC_RESET_MASK 0x1
933 #define DMAE_CMD_CRC_RESET_SHIFT 4
934 #define DMAE_CMD_SRC_ADDR_RESET_MASK 0x1
935 #define DMAE_CMD_SRC_ADDR_RESET_SHIFT 5
936 #define DMAE_CMD_DST_ADDR_RESET_MASK 0x1
937 #define DMAE_CMD_DST_ADDR_RESET_SHIFT 6
938 #define DMAE_CMD_COMP_FUNC_MASK 0x1
939 #define DMAE_CMD_COMP_FUNC_SHIFT 7
940 #define DMAE_CMD_COMP_WORD_EN_MASK 0x1
941 #define DMAE_CMD_COMP_WORD_EN_SHIFT 8
942 #define DMAE_CMD_COMP_CRC_EN_MASK 0x1
943 #define DMAE_CMD_COMP_CRC_EN_SHIFT 9
944 #define DMAE_CMD_COMP_CRC_OFFSET_MASK 0x7
945 #define DMAE_CMD_COMP_CRC_OFFSET_SHIFT 10
946 #define DMAE_CMD_RESERVED1_MASK 0x1
947 #define DMAE_CMD_RESERVED1_SHIFT 13
948 #define DMAE_CMD_ENDIANITY_MODE_MASK 0x3
949 #define DMAE_CMD_ENDIANITY_MODE_SHIFT 14
950 #define DMAE_CMD_ERR_HANDLING_MASK 0x3
951 #define DMAE_CMD_ERR_HANDLING_SHIFT 16
952 #define DMAE_CMD_PORT_ID_MASK 0x3
953 #define DMAE_CMD_PORT_ID_SHIFT 18
954 #define DMAE_CMD_SRC_PF_ID_MASK 0xF
955 #define DMAE_CMD_SRC_PF_ID_SHIFT 20
956 #define DMAE_CMD_DST_PF_ID_MASK 0xF
957 #define DMAE_CMD_DST_PF_ID_SHIFT 24
958 #define DMAE_CMD_SRC_VF_ID_VALID_MASK 0x1
959 #define DMAE_CMD_SRC_VF_ID_VALID_SHIFT 28
960 #define DMAE_CMD_DST_VF_ID_VALID_MASK 0x1
961 #define DMAE_CMD_DST_VF_ID_VALID_SHIFT 29
962 #define DMAE_CMD_RESERVED2_MASK 0x3
963 #define DMAE_CMD_RESERVED2_SHIFT 30
968 __le16 length /* Length in DW */;
970 #define DMAE_CMD_SRC_VF_ID_MASK 0xFF /* Source VF id */
971 #define DMAE_CMD_SRC_VF_ID_SHIFT 0
972 #define DMAE_CMD_DST_VF_ID_MASK 0xFF /* Destination VF id */
973 #define DMAE_CMD_DST_VF_ID_SHIFT 8
974 __le32 comp_addr_lo /* PCIe completion address low or grc address */;
976 __le32 comp_val /* Value to write to copmletion address */;
977 __le32 crc32 /* crc16 result */;
978 __le32 crc_32_c /* crc32_c result */;
979 __le16 crc16 /* crc16 result */;
980 __le16 crc16_c /* crc16_c result */;
981 __le16 crc10 /* crc_t10 result */;
983 __le16 xsum16 /* checksum16 result */;
984 __le16 xsum8 /* checksum8 result */;
988 __le32 sb_id_and_flags;
989 #define IGU_CLEANUP_RESERVED0_MASK 0x7FFFFFF
990 #define IGU_CLEANUP_RESERVED0_SHIFT 0
991 #define IGU_CLEANUP_CLEANUP_SET_MASK 0x1 /* cleanup clear - 0, set - 1 */
992 #define IGU_CLEANUP_CLEANUP_SET_SHIFT 27
993 #define IGU_CLEANUP_CLEANUP_TYPE_MASK 0x7
994 #define IGU_CLEANUP_CLEANUP_TYPE_SHIFT 28
995 #define IGU_CLEANUP_COMMAND_TYPE_MASK 0x1
996 #define IGU_CLEANUP_COMMAND_TYPE_SHIFT 31
1001 struct igu_prod_cons_update prod_cons_update;
1002 struct igu_cleanup cleanup;
1005 struct igu_command_reg_ctrl {
1007 __le16 igu_command_reg_ctrl_fields;
1008 #define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_MASK 0xFFF
1009 #define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_SHIFT 0
1010 #define IGU_COMMAND_REG_CTRL_RESERVED_MASK 0x7
1011 #define IGU_COMMAND_REG_CTRL_RESERVED_SHIFT 12
1012 #define IGU_COMMAND_REG_CTRL_COMMAND_TYPE_MASK 0x1
1013 #define IGU_COMMAND_REG_CTRL_COMMAND_TYPE_SHIFT 15
1016 struct igu_mapping_line {
1017 __le32 igu_mapping_line_fields;
1018 #define IGU_MAPPING_LINE_VALID_MASK 0x1
1019 #define IGU_MAPPING_LINE_VALID_SHIFT 0
1020 #define IGU_MAPPING_LINE_VECTOR_NUMBER_MASK 0xFF
1021 #define IGU_MAPPING_LINE_VECTOR_NUMBER_SHIFT 1
1022 #define IGU_MAPPING_LINE_FUNCTION_NUMBER_MASK 0xFF
1023 #define IGU_MAPPING_LINE_FUNCTION_NUMBER_SHIFT 9
1024 #define IGU_MAPPING_LINE_PF_VALID_MASK 0x1 /* PF-1, VF-0 */
1025 #define IGU_MAPPING_LINE_PF_VALID_SHIFT 17
1026 #define IGU_MAPPING_LINE_IPS_GROUP_MASK 0x3F
1027 #define IGU_MAPPING_LINE_IPS_GROUP_SHIFT 18
1028 #define IGU_MAPPING_LINE_RESERVED_MASK 0xFF
1029 #define IGU_MAPPING_LINE_RESERVED_SHIFT 24
1032 struct igu_msix_vector {
1033 struct regpair address;
1035 __le32 msix_vector_fields;
1036 #define IGU_MSIX_VECTOR_MASK_BIT_MASK 0x1
1037 #define IGU_MSIX_VECTOR_MASK_BIT_SHIFT 0
1038 #define IGU_MSIX_VECTOR_RESERVED0_MASK 0x7FFF
1039 #define IGU_MSIX_VECTOR_RESERVED0_SHIFT 1
1040 #define IGU_MSIX_VECTOR_STEERING_TAG_MASK 0xFF
1041 #define IGU_MSIX_VECTOR_STEERING_TAG_SHIFT 16
1042 #define IGU_MSIX_VECTOR_RESERVED1_MASK 0xFF
1043 #define IGU_MSIX_VECTOR_RESERVED1_SHIFT 24
1058 MODE_PORTS_PER_ENG_1,
1059 MODE_PORTS_PER_ENG_2,
1060 MODE_PORTS_PER_ENG_4,
1062 MODE_EAGLE_ENG1_WORKAROUND,
1075 /* per encapsulation type enabling flags */
1076 struct prs_reg_encapsulation_type_en {
1078 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_MASK 0x1
1079 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_SHIFT 0
1080 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_MASK 0x1
1081 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_SHIFT 1
1082 #define PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_MASK 0x1
1083 #define PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_SHIFT 2
1084 #define PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_MASK 0x1
1085 #define PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_SHIFT 3
1086 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_MASK 0x1
1087 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_SHIFT 4
1088 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_MASK 0x1
1089 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_SHIFT 5
1090 #define PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_MASK 0x3
1091 #define PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_SHIFT 6
1094 enum pxp_tph_st_hint {
1095 TPH_ST_HINT_BIDIR /* Read/Write access by Host and Device */,
1096 TPH_ST_HINT_REQUESTER /* Read/Write access by Device */,
1098 TPH_ST_HINT_TARGET_PRIO,
1102 /* QM hardware structure of enable bypass credit mask */
1103 struct qm_rf_bypass_mask {
1105 #define QM_RF_BYPASS_MASK_LINEVOQ_MASK 0x1
1106 #define QM_RF_BYPASS_MASK_LINEVOQ_SHIFT 0
1107 #define QM_RF_BYPASS_MASK_RESERVED0_MASK 0x1
1108 #define QM_RF_BYPASS_MASK_RESERVED0_SHIFT 1
1109 #define QM_RF_BYPASS_MASK_PFWFQ_MASK 0x1
1110 #define QM_RF_BYPASS_MASK_PFWFQ_SHIFT 2
1111 #define QM_RF_BYPASS_MASK_VPWFQ_MASK 0x1
1112 #define QM_RF_BYPASS_MASK_VPWFQ_SHIFT 3
1113 #define QM_RF_BYPASS_MASK_PFRL_MASK 0x1
1114 #define QM_RF_BYPASS_MASK_PFRL_SHIFT 4
1115 #define QM_RF_BYPASS_MASK_VPQCNRL_MASK 0x1
1116 #define QM_RF_BYPASS_MASK_VPQCNRL_SHIFT 5
1117 #define QM_RF_BYPASS_MASK_FWPAUSE_MASK 0x1
1118 #define QM_RF_BYPASS_MASK_FWPAUSE_SHIFT 6
1119 #define QM_RF_BYPASS_MASK_RESERVED1_MASK 0x1
1120 #define QM_RF_BYPASS_MASK_RESERVED1_SHIFT 7
1123 /* QM hardware structure of opportunistic credit mask */
1124 struct qm_rf_opportunistic_mask {
1126 #define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_MASK 0x1
1127 #define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_SHIFT 0
1128 #define QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_MASK 0x1
1129 #define QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_SHIFT 1
1130 #define QM_RF_OPPORTUNISTIC_MASK_PFWFQ_MASK 0x1
1131 #define QM_RF_OPPORTUNISTIC_MASK_PFWFQ_SHIFT 2
1132 #define QM_RF_OPPORTUNISTIC_MASK_VPWFQ_MASK 0x1
1133 #define QM_RF_OPPORTUNISTIC_MASK_VPWFQ_SHIFT 3
1134 #define QM_RF_OPPORTUNISTIC_MASK_PFRL_MASK 0x1
1135 #define QM_RF_OPPORTUNISTIC_MASK_PFRL_SHIFT 4
1136 #define QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_MASK 0x1
1137 #define QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_SHIFT 5
1138 #define QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_MASK 0x1
1139 #define QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_SHIFT 6
1140 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED0_MASK 0x1
1141 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED0_SHIFT 7
1142 #define QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_MASK 0x1
1143 #define QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_SHIFT 8
1144 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED1_MASK 0x7F
1145 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED1_SHIFT 9
1148 /* QM hardware structure of QM map memory */
1149 struct qm_rf_pq_map {
1151 #define QM_RF_PQ_MAP_PQ_VALID_MASK 0x1 /* PQ active */
1152 #define QM_RF_PQ_MAP_PQ_VALID_SHIFT 0
1153 #define QM_RF_PQ_MAP_RL_ID_MASK 0xFF /* RL ID */
1154 #define QM_RF_PQ_MAP_RL_ID_SHIFT 1
1155 #define QM_RF_PQ_MAP_VP_PQ_ID_MASK 0x1FF
1156 #define QM_RF_PQ_MAP_VP_PQ_ID_SHIFT 9
1157 #define QM_RF_PQ_MAP_VOQ_MASK 0x1F /* VOQ */
1158 #define QM_RF_PQ_MAP_VOQ_SHIFT 18
1159 #define QM_RF_PQ_MAP_WRR_WEIGHT_GROUP_MASK 0x3 /* WRR weight */
1160 #define QM_RF_PQ_MAP_WRR_WEIGHT_GROUP_SHIFT 23
1161 #define QM_RF_PQ_MAP_RL_VALID_MASK 0x1 /* RL active */
1162 #define QM_RF_PQ_MAP_RL_VALID_SHIFT 25
1163 #define QM_RF_PQ_MAP_RESERVED_MASK 0x3F
1164 #define QM_RF_PQ_MAP_RESERVED_SHIFT 26
1167 /* Completion params for aggregated interrupt completion */
1168 struct sdm_agg_int_comp_params {
1170 #define SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_MASK 0x3F
1171 #define SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT 0
1172 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_MASK 0x1
1173 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT 6
1174 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_MASK 0x1FF
1175 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT 7
1178 /* SDM operation gen command (generate aggregative interrupt) */
1181 #define SDM_OP_GEN_COMP_PARAM_MASK 0xFFFF /* completion parameters 0-15 */
1182 #define SDM_OP_GEN_COMP_PARAM_SHIFT 0
1183 #define SDM_OP_GEN_COMP_TYPE_MASK 0xF /* completion type 16-19 */
1184 #define SDM_OP_GEN_COMP_TYPE_SHIFT 16
1185 #define SDM_OP_GEN_RESERVED_MASK 0xFFF /* reserved 20-31 */
1186 #define SDM_OP_GEN_RESERVED_SHIFT 20
1189 /*********************************** Init ************************************/
1191 /* Width of GRC address in bits (addresses are specified in dwords) */
1192 #define GRC_ADDR_BITS 23
1193 #define MAX_GRC_ADDR ((1 << GRC_ADDR_BITS) - 1)
1195 /* indicates an init that should be applied to any phase ID */
1196 #define ANY_PHASE_ID 0xffff
1198 /* init pattern size in bytes */
1199 #define INIT_PATTERN_SIZE_BITS 4
1200 #define MAX_INIT_PATTERN_SIZE BIT(INIT_PATTERN_SIZE_BITS)
1202 /* Max size in dwords of a zipped array */
1203 #define MAX_ZIPPED_SIZE 8192
1205 /* Global PXP window */
1206 #define NUM_OF_PXP_WIN 19
1207 #define PXP_WIN_DWORD_SIZE_BITS 10
1208 #define PXP_WIN_DWORD_SIZE BIT(PXP_WIN_DWORD_SIZE_BITS)
1209 #define PXP_WIN_BYTE_SIZE_BITS (PXP_WIN_DWORD_SIZE_BITS + 2)
1210 #define PXP_WIN_BYTE_SIZE (PXP_WIN_DWORD_SIZE * 4)
1212 /********************************* GRC Dump **********************************/
1214 /* width of GRC dump register sequence length in bits */
1215 #define DUMP_SEQ_LEN_BITS 8
1216 #define DUMP_SEQ_LEN_MAX_VAL ((1 << DUMP_SEQ_LEN_BITS) - 1)
1218 /* width of GRC dump memory length in bits */
1219 #define DUMP_MEM_LEN_BITS 18
1220 #define DUMP_MEM_LEN_MAX_VAL ((1 << DUMP_MEM_LEN_BITS) - 1)
1222 /* width of register type ID in bits */
1223 #define REG_TYPE_ID_BITS 6
1224 #define REG_TYPE_ID_MAX_VAL ((1 << REG_TYPE_ID_BITS) - 1)
1226 /* width of block ID in bits */
1227 #define BLOCK_ID_BITS 8
1228 #define BLOCK_ID_MAX_VAL ((1 << BLOCK_ID_BITS) - 1)
1230 /******************************** Idle Check *********************************/
1232 /* max number of idle check predicate immediates */
1233 #define MAX_IDLE_CHK_PRED_IMM 3
1235 /* max number of idle check argument registers */
1236 #define MAX_IDLE_CHK_READ_REGS 3
1238 /* max number of idle check loops */
1239 #define MAX_IDLE_CHK_LOOPS 0x10000
1241 /* max idle check address increment */
1242 #define MAX_IDLE_CHK_INCREMENT 0x10000
1244 /* inicates an undefined idle check line index */
1245 #define IDLE_CHK_UNDEFINED_LINE_IDX 0xffffff
1247 /* max number of register values following the idle check header */
1248 #define IDLE_CHK_MAX_DUMP_REGS 2
1250 /* arguments for IDLE_CHK_MACRO_TYPE_QM_RD_WR */
1251 #define IDLE_CHK_QM_RD_WR_PTR 0
1252 #define IDLE_CHK_QM_RD_WR_BANK 1
1254 /**************************************/
1255 /* HSI Functions constants and macros */
1256 /**************************************/
1258 /* Number of VLAN priorities */
1259 #define NUM_OF_VLAN_PRIORITIES 8
1261 /* the MCP Trace meta data signautre is duplicated in the perl script that
1262 * generats the NVRAM images.
1264 #define MCP_TRACE_META_IMAGE_SIGNATURE 0x669955aa
1266 /* Binary buffer header */
1267 struct bin_buffer_hdr {
1269 u32 length /* buffer length in bytes */;
1272 /* binary buffer types */
1273 enum bin_buffer_type {
1274 BIN_BUF_FW_VER_INFO /* fw_ver_info struct */,
1275 BIN_BUF_INIT_CMD /* init commands */,
1276 BIN_BUF_INIT_VAL /* init data */,
1277 BIN_BUF_INIT_MODE_TREE /* init modes tree */,
1278 BIN_BUF_IRO /* internal RAM offsets array */,
1284 CHIP_BB_A0 /* BB A0 chip ID */,
1285 CHIP_BB_B0 /* BB B0 chip ID */,
1286 CHIP_K2 /* AH chip ID */,
1290 struct init_array_raw_hdr {
1292 #define INIT_ARRAY_RAW_HDR_TYPE_MASK 0xF
1293 #define INIT_ARRAY_RAW_HDR_TYPE_SHIFT 0
1294 #define INIT_ARRAY_RAW_HDR_PARAMS_MASK 0xFFFFFFF /* init array params */
1295 #define INIT_ARRAY_RAW_HDR_PARAMS_SHIFT 4
1298 struct init_array_standard_hdr {
1300 #define INIT_ARRAY_STANDARD_HDR_TYPE_MASK 0xF
1301 #define INIT_ARRAY_STANDARD_HDR_TYPE_SHIFT 0
1302 #define INIT_ARRAY_STANDARD_HDR_SIZE_MASK 0xFFFFFFF
1303 #define INIT_ARRAY_STANDARD_HDR_SIZE_SHIFT 4
1306 struct init_array_zipped_hdr {
1308 #define INIT_ARRAY_ZIPPED_HDR_TYPE_MASK 0xF
1309 #define INIT_ARRAY_ZIPPED_HDR_TYPE_SHIFT 0
1310 #define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_MASK 0xFFFFFFF
1311 #define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_SHIFT 4
1314 struct init_array_pattern_hdr {
1316 #define INIT_ARRAY_PATTERN_HDR_TYPE_MASK 0xF
1317 #define INIT_ARRAY_PATTERN_HDR_TYPE_SHIFT 0
1318 #define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_MASK 0xF
1319 #define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_SHIFT 4
1320 #define INIT_ARRAY_PATTERN_HDR_REPETITIONS_MASK 0xFFFFFF
1321 #define INIT_ARRAY_PATTERN_HDR_REPETITIONS_SHIFT 8
1324 union init_array_hdr {
1325 struct init_array_raw_hdr raw /* raw init array header */;
1326 struct init_array_standard_hdr standard;
1327 struct init_array_zipped_hdr zipped /* zipped init array header */;
1328 struct init_array_pattern_hdr pattern /* pattern init array header */;
1331 enum init_array_types {
1332 INIT_ARR_STANDARD /* standard init array */,
1333 INIT_ARR_ZIPPED /* zipped init array */,
1334 INIT_ARR_PATTERN /* a repeated pattern */,
1335 MAX_INIT_ARRAY_TYPES
1338 /* init operation: callback */
1339 struct init_callback_op {
1341 #define INIT_CALLBACK_OP_OP_MASK 0xF
1342 #define INIT_CALLBACK_OP_OP_SHIFT 0
1343 #define INIT_CALLBACK_OP_RESERVED_MASK 0xFFFFFFF
1344 #define INIT_CALLBACK_OP_RESERVED_SHIFT 4
1345 __le16 callback_id /* Callback ID */;
1346 __le16 block_id /* Blocks ID */;
1349 /* init operation: delay */
1350 struct init_delay_op {
1352 #define INIT_DELAY_OP_OP_MASK 0xF
1353 #define INIT_DELAY_OP_OP_SHIFT 0
1354 #define INIT_DELAY_OP_RESERVED_MASK 0xFFFFFFF
1355 #define INIT_DELAY_OP_RESERVED_SHIFT 4
1356 __le32 delay /* delay in us */;
1359 /* init operation: if_mode */
1360 struct init_if_mode_op {
1362 #define INIT_IF_MODE_OP_OP_MASK 0xF
1363 #define INIT_IF_MODE_OP_OP_SHIFT 0
1364 #define INIT_IF_MODE_OP_RESERVED1_MASK 0xFFF
1365 #define INIT_IF_MODE_OP_RESERVED1_SHIFT 4
1366 #define INIT_IF_MODE_OP_CMD_OFFSET_MASK 0xFFFF
1367 #define INIT_IF_MODE_OP_CMD_OFFSET_SHIFT 16
1369 __le16 modes_buf_offset;
1372 /* init operation: if_phase */
1373 struct init_if_phase_op {
1375 #define INIT_IF_PHASE_OP_OP_MASK 0xF
1376 #define INIT_IF_PHASE_OP_OP_SHIFT 0
1377 #define INIT_IF_PHASE_OP_DMAE_ENABLE_MASK 0x1
1378 #define INIT_IF_PHASE_OP_DMAE_ENABLE_SHIFT 4
1379 #define INIT_IF_PHASE_OP_RESERVED1_MASK 0x7FF
1380 #define INIT_IF_PHASE_OP_RESERVED1_SHIFT 5
1381 #define INIT_IF_PHASE_OP_CMD_OFFSET_MASK 0xFFFF
1382 #define INIT_IF_PHASE_OP_CMD_OFFSET_SHIFT 16
1384 #define INIT_IF_PHASE_OP_PHASE_MASK 0xFF /* Init phase */
1385 #define INIT_IF_PHASE_OP_PHASE_SHIFT 0
1386 #define INIT_IF_PHASE_OP_RESERVED2_MASK 0xFF
1387 #define INIT_IF_PHASE_OP_RESERVED2_SHIFT 8
1388 #define INIT_IF_PHASE_OP_PHASE_ID_MASK 0xFFFF /* Init phase ID */
1389 #define INIT_IF_PHASE_OP_PHASE_ID_SHIFT 16
1392 /* init mode operators */
1393 enum init_mode_ops {
1394 INIT_MODE_OP_NOT /* init mode not operator */,
1395 INIT_MODE_OP_OR /* init mode or operator */,
1396 INIT_MODE_OP_AND /* init mode and operator */,
1400 /* init operation: raw */
1401 struct init_raw_op {
1403 #define INIT_RAW_OP_OP_MASK 0xF
1404 #define INIT_RAW_OP_OP_SHIFT 0
1405 #define INIT_RAW_OP_PARAM1_MASK 0xFFFFFFF /* init param 1 */
1406 #define INIT_RAW_OP_PARAM1_SHIFT 4
1407 __le32 param2 /* Init param 2 */;
1410 /* init array params */
1411 struct init_op_array_params {
1412 __le16 size /* array size in dwords */;
1413 __le16 offset /* array start offset in dwords */;
1416 /* Write init operation arguments */
1417 union init_write_args {
1420 __le32 array_offset;
1421 struct init_op_array_params runtime;
1424 /* init operation: write */
1425 struct init_write_op {
1427 #define INIT_WRITE_OP_OP_MASK 0xF
1428 #define INIT_WRITE_OP_OP_SHIFT 0
1429 #define INIT_WRITE_OP_SOURCE_MASK 0x7
1430 #define INIT_WRITE_OP_SOURCE_SHIFT 4
1431 #define INIT_WRITE_OP_RESERVED_MASK 0x1
1432 #define INIT_WRITE_OP_RESERVED_SHIFT 7
1433 #define INIT_WRITE_OP_WIDE_BUS_MASK 0x1
1434 #define INIT_WRITE_OP_WIDE_BUS_SHIFT 8
1435 #define INIT_WRITE_OP_ADDRESS_MASK 0x7FFFFF
1436 #define INIT_WRITE_OP_ADDRESS_SHIFT 9
1437 union init_write_args args /* Write init operation arguments */;
1440 /* init operation: read */
1441 struct init_read_op {
1443 #define INIT_READ_OP_OP_MASK 0xF
1444 #define INIT_READ_OP_OP_SHIFT 0
1445 #define INIT_READ_OP_POLL_TYPE_MASK 0xF
1446 #define INIT_READ_OP_POLL_TYPE_SHIFT 4
1447 #define INIT_READ_OP_RESERVED_MASK 0x1
1448 #define INIT_READ_OP_RESERVED_SHIFT 8
1449 #define INIT_READ_OP_ADDRESS_MASK 0x7FFFFF
1450 #define INIT_READ_OP_ADDRESS_SHIFT 9
1451 __le32 expected_val;
1454 /* Init operations union */
1456 struct init_raw_op raw /* raw init operation */;
1457 struct init_write_op write /* write init operation */;
1458 struct init_read_op read /* read init operation */;
1459 struct init_if_mode_op if_mode /* if_mode init operation */;
1460 struct init_if_phase_op if_phase /* if_phase init operation */;
1461 struct init_callback_op callback /* callback init operation */;
1462 struct init_delay_op delay /* delay init operation */;
1465 /* Init command operation types */
1466 enum init_op_types {
1467 INIT_OP_READ /* GRC read init command */,
1468 INIT_OP_WRITE /* GRC write init command */,
1471 INIT_OP_DELAY /* delay init command */,
1472 INIT_OP_CALLBACK /* callback init command */,
1476 enum init_poll_types {
1477 INIT_POLL_NONE /* No polling */,
1478 INIT_POLL_EQ /* init value is included in the init command */,
1479 INIT_POLL_OR /* init value is all zeros */,
1480 INIT_POLL_AND /* init value is an array of values */,
1484 /* init source types */
1485 enum init_source_types {
1486 INIT_SRC_INLINE /* init value is included in the init command */,
1487 INIT_SRC_ZEROS /* init value is all zeros */,
1488 INIT_SRC_ARRAY /* init value is an array of values */,
1489 INIT_SRC_RUNTIME /* init value is provided during runtime */,
1490 MAX_INIT_SOURCE_TYPES
1493 /* Internal RAM Offsets macro data */
1495 u32 base /* RAM field offset */;
1496 u16 m1 /* multiplier 1 */;
1497 u16 m2 /* multiplier 2 */;
1498 u16 m3 /* multiplier 3 */;
1499 u16 size /* RAM field size */;
1502 /* QM per-port init parameters */
1503 struct init_qm_port_params {
1504 u8 active /* Indicates if this port is active */;
1505 u8 num_active_phys_tcs;
1506 u16 num_pbf_cmd_lines;
1511 /* QM per-PQ init parameters */
1512 struct init_qm_pq_params {
1513 u8 vport_id /* VPORT ID */;
1514 u8 tc_id /* TC ID */;
1515 u8 wrr_group /* WRR group */;
1519 /* QM per-vport init parameters */
1520 struct init_qm_vport_params {
1523 u16 first_tx_pq_id[NUM_OF_TCS];
1527 #define GTT_BAR0_MAP_REG_IGU_CMD \
1530 #define GTT_BAR0_MAP_REG_TSDM_RAM \
1533 #define GTT_BAR0_MAP_REG_MSDM_RAM \
1536 #define GTT_BAR0_MAP_REG_MSDM_RAM_1024 \
1539 #define GTT_BAR0_MAP_REG_USDM_RAM \
1542 #define GTT_BAR0_MAP_REG_USDM_RAM_1024 \
1545 #define GTT_BAR0_MAP_REG_USDM_RAM_2048 \
1548 #define GTT_BAR0_MAP_REG_XSDM_RAM \
1551 #define GTT_BAR0_MAP_REG_YSDM_RAM \
1554 #define GTT_BAR0_MAP_REG_PSDM_RAM \
1558 * @brief qed_qm_pf_mem_size - prepare QM ILT sizes
1560 * Returns the required host memory size in 4KB units.
1561 * Must be called before all QM init HSI functions.
1563 * @param pf_id - physical function ID
1564 * @param num_pf_cids - number of connections used by this PF
1565 * @param num_vf_cids - number of connections used by VFs of this PF
1566 * @param num_tids - number of tasks used by this PF
1567 * @param num_pf_pqs - number of PQs used by this PF
1568 * @param num_vf_pqs - number of PQs used by VFs of this PF
1570 * @return The required host memory size in 4KB units.
1572 u32 qed_qm_pf_mem_size(u8 pf_id,
1579 struct qed_qm_common_rt_init_params {
1580 u8 max_ports_per_engine;
1581 u8 max_phys_tcs_per_port;
1586 struct init_qm_port_params *port_params;
1590 * @brief qed_qm_common_rt_init - Prepare QM runtime init values for the
1594 * @param max_ports_per_engine - max number of ports per engine in HW
1595 * @param max_phys_tcs_per_port - max number of physical TCs per port in HW
1596 * @param pf_rl_en - enable per-PF rate limiters
1597 * @param pf_wfq_en - enable per-PF WFQ
1598 * @param vport_rl_en - enable per-VPORT rate limiters
1599 * @param vport_wfq_en - enable per-VPORT WFQ
1600 * @param port_params - array of size MAX_NUM_PORTS with
1601 * arameters for each port
1603 * @return 0 on success, -1 on error.
1605 int qed_qm_common_rt_init(
1606 struct qed_hwfn *p_hwfn,
1607 struct qed_qm_common_rt_init_params *p_params);
1609 struct qed_qm_pf_rt_init_params {
1612 u8 max_phys_tcs_per_port;
1624 struct init_qm_pq_params *pq_params;
1625 struct init_qm_vport_params *vport_params;
1628 int qed_qm_pf_rt_init(struct qed_hwfn *p_hwfn,
1629 struct qed_ptt *p_ptt,
1630 struct qed_qm_pf_rt_init_params *p_params);
1633 * @brief qed_init_pf_rl Initializes the rate limit of the specified PF
1636 * @param p_ptt - ptt window used for writing the registers
1637 * @param pf_id - PF ID
1638 * @param pf_rl - rate limit in Mb/sec units
1640 * @return 0 on success, -1 on error.
1642 int qed_init_pf_rl(struct qed_hwfn *p_hwfn,
1643 struct qed_ptt *p_ptt,
1648 * @brief qed_init_vport_rl Initializes the rate limit of the specified VPORT
1651 * @param p_ptt - ptt window used for writing the registers
1652 * @param vport_id - VPORT ID
1653 * @param vport_rl - rate limit in Mb/sec units
1655 * @return 0 on success, -1 on error.
1658 int qed_init_vport_rl(struct qed_hwfn *p_hwfn,
1659 struct qed_ptt *p_ptt,
1663 * @brief qed_send_qm_stop_cmd Sends a stop command to the QM
1666 * @param p_ptt - ptt window used for writing the registers
1667 * @param is_release_cmd - true for release, false for stop.
1668 * @param is_tx_pq - true for Tx PQs, false for Other PQs.
1669 * @param start_pq - first PQ ID to stop
1670 * @param num_pqs - Number of PQs to stop, starting from start_pq.
1672 * @return bool, true if successful, false if timeout occurred while waiting
1673 * for QM command done.
1676 bool qed_send_qm_stop_cmd(struct qed_hwfn *p_hwfn,
1677 struct qed_ptt *p_ptt,
1678 bool is_release_cmd,
1683 void qed_set_vxlan_dest_port(struct qed_hwfn *p_hwfn,
1684 struct qed_ptt *p_ptt, u16 dest_port);
1685 void qed_set_vxlan_enable(struct qed_hwfn *p_hwfn,
1686 struct qed_ptt *p_ptt, bool vxlan_enable);
1687 void qed_set_gre_enable(struct qed_hwfn *p_hwfn,
1688 struct qed_ptt *p_ptt, bool eth_gre_enable,
1689 bool ip_gre_enable);
1690 void qed_set_geneve_dest_port(struct qed_hwfn *p_hwfn,
1691 struct qed_ptt *p_ptt, u16 dest_port);
1692 void qed_set_geneve_enable(struct qed_hwfn *p_hwfn,
1693 struct qed_ptt *p_ptt, bool eth_geneve_enable,
1694 bool ip_geneve_enable);
1696 /* Ystorm flow control mode. Use enum fw_flow_ctrl_mode */
1697 #define YSTORM_FLOW_CONTROL_MODE_OFFSET (IRO[0].base)
1698 #define YSTORM_FLOW_CONTROL_MODE_SIZE (IRO[0].size)
1699 /* Tstorm port statistics */
1700 #define TSTORM_PORT_STAT_OFFSET(port_id) (IRO[1].base + ((port_id) * IRO[1].m1))
1701 #define TSTORM_PORT_STAT_SIZE (IRO[1].size)
1702 /* Tstorm ll2 port statistics */
1703 #define TSTORM_LL2_PORT_STAT_OFFSET(port_id) \
1704 (IRO[2].base + ((port_id) * IRO[2].m1))
1705 #define TSTORM_LL2_PORT_STAT_SIZE (IRO[2].size)
1706 /* Ustorm VF-PF Channel ready flag */
1707 #define USTORM_VF_PF_CHANNEL_READY_OFFSET(vf_id) \
1708 (IRO[3].base + ((vf_id) * IRO[3].m1))
1709 #define USTORM_VF_PF_CHANNEL_READY_SIZE (IRO[3].size)
1710 /* Ustorm Final flr cleanup ack */
1711 #define USTORM_FLR_FINAL_ACK_OFFSET(pf_id) (IRO[4].base + ((pf_id) * IRO[4].m1))
1712 #define USTORM_FLR_FINAL_ACK_SIZE (IRO[4].size)
1713 /* Ustorm Event ring consumer */
1714 #define USTORM_EQE_CONS_OFFSET(pf_id) (IRO[5].base + ((pf_id) * IRO[5].m1))
1715 #define USTORM_EQE_CONS_SIZE (IRO[5].size)
1716 /* Ustorm Common Queue ring consumer */
1717 #define USTORM_COMMON_QUEUE_CONS_OFFSET(global_queue_id) \
1718 (IRO[6].base + ((global_queue_id) * IRO[6].m1))
1719 #define USTORM_COMMON_QUEUE_CONS_SIZE (IRO[6].size)
1720 /* Xstorm Integration Test Data */
1721 #define XSTORM_INTEG_TEST_DATA_OFFSET (IRO[7].base)
1722 #define XSTORM_INTEG_TEST_DATA_SIZE (IRO[7].size)
1723 /* Ystorm Integration Test Data */
1724 #define YSTORM_INTEG_TEST_DATA_OFFSET (IRO[8].base)
1725 #define YSTORM_INTEG_TEST_DATA_SIZE (IRO[8].size)
1726 /* Pstorm Integration Test Data */
1727 #define PSTORM_INTEG_TEST_DATA_OFFSET (IRO[9].base)
1728 #define PSTORM_INTEG_TEST_DATA_SIZE (IRO[9].size)
1729 /* Tstorm Integration Test Data */
1730 #define TSTORM_INTEG_TEST_DATA_OFFSET (IRO[10].base)
1731 #define TSTORM_INTEG_TEST_DATA_SIZE (IRO[10].size)
1732 /* Mstorm Integration Test Data */
1733 #define MSTORM_INTEG_TEST_DATA_OFFSET (IRO[11].base)
1734 #define MSTORM_INTEG_TEST_DATA_SIZE (IRO[11].size)
1735 /* Ustorm Integration Test Data */
1736 #define USTORM_INTEG_TEST_DATA_OFFSET (IRO[12].base)
1737 #define USTORM_INTEG_TEST_DATA_SIZE (IRO[12].size)
1738 /* Tstorm producers */
1739 #define TSTORM_LL2_RX_PRODS_OFFSET(core_rx_queue_id) \
1740 (IRO[13].base + ((core_rx_queue_id) * IRO[13].m1))
1741 #define TSTORM_LL2_RX_PRODS_SIZE (IRO[13].size)
1742 /* Tstorm LightL2 queue statistics */
1743 #define CORE_LL2_TSTORM_PER_QUEUE_STAT_OFFSET(core_rx_queue_id) \
1744 (IRO[14].base + ((core_rx_queue_id) * IRO[14].m1))
1745 #define CORE_LL2_TSTORM_PER_QUEUE_STAT_SIZE (IRO[14].size)
1746 /* Ustorm LiteL2 queue statistics */
1747 #define CORE_LL2_USTORM_PER_QUEUE_STAT_OFFSET(core_rx_queue_id) \
1748 (IRO[15].base + ((core_rx_queue_id) * IRO[15].m1))
1749 #define CORE_LL2_USTORM_PER_QUEUE_STAT_SIZE (IRO[15].size)
1750 /* Pstorm LiteL2 queue statistics */
1751 #define CORE_LL2_PSTORM_PER_QUEUE_STAT_OFFSET(core_tx_stats_id) \
1752 (IRO[16].base + ((core_tx_stats_id) * IRO[16].m1))
1753 #define CORE_LL2_PSTORM_PER_QUEUE_STAT_SIZE (IRO[16].size)
1754 /* Mstorm queue statistics */
1755 #define MSTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
1756 (IRO[17].base + ((stat_counter_id) * IRO[17].m1))
1757 #define MSTORM_QUEUE_STAT_SIZE (IRO[17].size)
1758 /* Mstorm producers */
1759 #define MSTORM_PRODS_OFFSET(queue_id) (IRO[18].base + ((queue_id) * IRO[18].m1))
1760 #define MSTORM_PRODS_SIZE (IRO[18].size)
1761 /* TPA agregation timeout in us resolution (on ASIC) */
1762 #define MSTORM_TPA_TIMEOUT_US_OFFSET (IRO[19].base)
1763 #define MSTORM_TPA_TIMEOUT_US_SIZE (IRO[19].size)
1764 /* Ustorm queue statistics */
1765 #define USTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
1766 (IRO[20].base + ((stat_counter_id) * IRO[20].m1))
1767 #define USTORM_QUEUE_STAT_SIZE (IRO[20].size)
1768 /* Ustorm queue zone */
1769 #define USTORM_ETH_QUEUE_ZONE_OFFSET(queue_id) \
1770 (IRO[21].base + ((queue_id) * IRO[21].m1))
1771 #define USTORM_ETH_QUEUE_ZONE_SIZE (IRO[21].size)
1772 /* Pstorm queue statistics */
1773 #define PSTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
1774 (IRO[22].base + ((stat_counter_id) * IRO[22].m1))
1775 #define PSTORM_QUEUE_STAT_SIZE (IRO[22].size)
1776 /* Tstorm last parser message */
1777 #define TSTORM_ETH_PRS_INPUT_OFFSET (IRO[23].base)
1778 #define TSTORM_ETH_PRS_INPUT_SIZE (IRO[23].size)
1779 /* Tstorm Eth limit Rx rate */
1780 #define ETH_RX_RATE_LIMIT_OFFSET(pf_id) (IRO[24].base + ((pf_id) * IRO[24].m1))
1781 #define ETH_RX_RATE_LIMIT_SIZE (IRO[24].size)
1782 /* Ystorm queue zone */
1783 #define YSTORM_ETH_QUEUE_ZONE_OFFSET(queue_id) \
1784 (IRO[25].base + ((queue_id) * IRO[25].m1))
1785 #define YSTORM_ETH_QUEUE_ZONE_SIZE (IRO[25].size)
1786 /* Ystorm cqe producer */
1787 #define YSTORM_TOE_CQ_PROD_OFFSET(rss_id) \
1788 (IRO[26].base + ((rss_id) * IRO[26].m1))
1789 #define YSTORM_TOE_CQ_PROD_SIZE (IRO[26].size)
1790 /* Ustorm cqe producer */
1791 #define USTORM_TOE_CQ_PROD_OFFSET(rss_id) \
1792 (IRO[27].base + ((rss_id) * IRO[27].m1))
1793 #define USTORM_TOE_CQ_PROD_SIZE (IRO[27].size)
1794 /* Ustorm grq producer */
1795 #define USTORM_TOE_GRQ_PROD_OFFSET(pf_id) \
1796 (IRO[28].base + ((pf_id) * IRO[28].m1))
1797 #define USTORM_TOE_GRQ_PROD_SIZE (IRO[28].size)
1798 /* Tstorm cmdq-cons of given command queue-id */
1799 #define TSTORM_SCSI_CMDQ_CONS_OFFSET(cmdq_queue_id) \
1800 (IRO[29].base + ((cmdq_queue_id) * IRO[29].m1))
1801 #define TSTORM_SCSI_CMDQ_CONS_SIZE (IRO[29].size)
1802 /* Mstorm rq-cons of given queue-id */
1803 #define MSTORM_SCSI_RQ_CONS_OFFSET(rq_queue_id) \
1804 (IRO[30].base + ((rq_queue_id) * IRO[30].m1))
1805 #define MSTORM_SCSI_RQ_CONS_SIZE (IRO[30].size)
1806 /* Mstorm bdq-external-producer of given BDQ function ID, BDqueue-id */
1807 #define MSTORM_SCSI_BDQ_EXT_PROD_OFFSET(func_id, bdq_id) \
1808 (IRO[31].base + ((func_id) * IRO[31].m1) + ((bdq_id) * IRO[31].m2))
1809 #define MSTORM_SCSI_BDQ_EXT_PROD_SIZE (IRO[31].size)
1810 /* Tstorm (reflects M-Storm) bdq-external-producer of given fn ID, BDqueue-id */
1811 #define TSTORM_SCSI_BDQ_EXT_PROD_OFFSET(func_id, bdq_id) \
1812 (IRO[32].base + ((func_id) * IRO[32].m1) + ((bdq_id) * IRO[32].m2))
1813 #define TSTORM_SCSI_BDQ_EXT_PROD_SIZE (IRO[32].size)
1814 /* Tstorm iSCSI RX stats */
1815 #define TSTORM_ISCSI_RX_STATS_OFFSET(pf_id) \
1816 (IRO[33].base + ((pf_id) * IRO[33].m1))
1817 #define TSTORM_ISCSI_RX_STATS_SIZE (IRO[33].size)
1818 /* Mstorm iSCSI RX stats */
1819 #define MSTORM_ISCSI_RX_STATS_OFFSET(pf_id) \
1820 (IRO[34].base + ((pf_id) * IRO[34].m1))
1821 #define MSTORM_ISCSI_RX_STATS_SIZE (IRO[34].size)
1822 /* Ustorm iSCSI RX stats */
1823 #define USTORM_ISCSI_RX_STATS_OFFSET(pf_id) \
1824 (IRO[35].base + ((pf_id) * IRO[35].m1))
1825 #define USTORM_ISCSI_RX_STATS_SIZE (IRO[35].size)
1826 /* Xstorm iSCSI TX stats */
1827 #define XSTORM_ISCSI_TX_STATS_OFFSET(pf_id) \
1828 (IRO[36].base + ((pf_id) * IRO[36].m1))
1829 #define XSTORM_ISCSI_TX_STATS_SIZE (IRO[36].size)
1830 /* Ystorm iSCSI TX stats */
1831 #define YSTORM_ISCSI_TX_STATS_OFFSET(pf_id) \
1832 (IRO[37].base + ((pf_id) * IRO[37].m1))
1833 #define YSTORM_ISCSI_TX_STATS_SIZE (IRO[37].size)
1834 /* Pstorm iSCSI TX stats */
1835 #define PSTORM_ISCSI_TX_STATS_OFFSET(pf_id) \
1836 (IRO[38].base + ((pf_id) * IRO[38].m1))
1837 #define PSTORM_ISCSI_TX_STATS_SIZE (IRO[38].size)
1838 /* Tstorm FCoE RX stats */
1839 #define TSTORM_FCOE_RX_STATS_OFFSET(pf_id) \
1840 (IRO[39].base + ((pf_id) * IRO[39].m1))
1841 #define TSTORM_FCOE_RX_STATS_SIZE (IRO[39].size)
1842 /* Mstorm FCoE RX stats */
1843 #define MSTORM_FCOE_RX_STATS_OFFSET(pf_id) \
1844 (IRO[40].base + ((pf_id) * IRO[40].m1))
1845 #define MSTORM_FCOE_RX_STATS_SIZE (IRO[40].size)
1846 /* Pstorm FCoE TX stats */
1847 #define PSTORM_FCOE_TX_STATS_OFFSET(pf_id) \
1848 (IRO[41].base + ((pf_id) * IRO[41].m1))
1849 #define PSTORM_FCOE_TX_STATS_SIZE (IRO[41].size)
1850 /* Pstorm RoCE statistics */
1851 #define PSTORM_ROCE_STAT_OFFSET(stat_counter_id) \
1852 (IRO[42].base + ((stat_counter_id) * IRO[42].m1))
1853 #define PSTORM_ROCE_STAT_SIZE (IRO[42].size)
1854 /* Tstorm RoCE statistics */
1855 #define TSTORM_ROCE_STAT_OFFSET(stat_counter_id) \
1856 (IRO[43].base + ((stat_counter_id) * IRO[43].m1))
1857 #define TSTORM_ROCE_STAT_SIZE (IRO[43].size)
1859 static const struct iro iro_arr[44] = {
1860 { 0x10, 0x0, 0x0, 0x0, 0x8 },
1861 { 0x47c8, 0x60, 0x0, 0x0, 0x60 },
1862 { 0x5e30, 0x20, 0x0, 0x0, 0x20 },
1863 { 0x510, 0x8, 0x0, 0x0, 0x4 },
1864 { 0x490, 0x8, 0x0, 0x0, 0x4 },
1865 { 0x10, 0x8, 0x0, 0x0, 0x2 },
1866 { 0x90, 0x8, 0x0, 0x0, 0x2 },
1867 { 0x4940, 0x0, 0x0, 0x0, 0x78 },
1868 { 0x3de0, 0x0, 0x0, 0x0, 0x78 },
1869 { 0x2998, 0x0, 0x0, 0x0, 0x78 },
1870 { 0x4750, 0x0, 0x0, 0x0, 0x78 },
1871 { 0x56d0, 0x0, 0x0, 0x0, 0x78 },
1872 { 0x7e50, 0x0, 0x0, 0x0, 0x78 },
1873 { 0x100, 0x8, 0x0, 0x0, 0x8 },
1874 { 0x5c10, 0x10, 0x0, 0x0, 0x10 },
1875 { 0xb508, 0x30, 0x0, 0x0, 0x30 },
1876 { 0x95c0, 0x30, 0x0, 0x0, 0x30 },
1877 { 0x58a0, 0x40, 0x0, 0x0, 0x40 },
1878 { 0x200, 0x10, 0x0, 0x0, 0x8 },
1879 { 0xa230, 0x0, 0x0, 0x0, 0x4 },
1880 { 0x8058, 0x40, 0x0, 0x0, 0x30 },
1881 { 0xd00, 0x8, 0x0, 0x0, 0x8 },
1882 { 0x2b30, 0x80, 0x0, 0x0, 0x38 },
1883 { 0xa808, 0x0, 0x0, 0x0, 0xf0 },
1884 { 0xa8f8, 0x8, 0x0, 0x0, 0x8 },
1885 { 0x80, 0x8, 0x0, 0x0, 0x8 },
1886 { 0xac0, 0x8, 0x0, 0x0, 0x8 },
1887 { 0x2580, 0x8, 0x0, 0x0, 0x8 },
1888 { 0x2500, 0x8, 0x0, 0x0, 0x8 },
1889 { 0x440, 0x8, 0x0, 0x0, 0x2 },
1890 { 0x1800, 0x8, 0x0, 0x0, 0x2 },
1891 { 0x1a00, 0x10, 0x8, 0x0, 0x2 },
1892 { 0x640, 0x10, 0x8, 0x0, 0x2 },
1893 { 0xd9b8, 0x38, 0x0, 0x0, 0x24 },
1894 { 0x11048, 0x10, 0x0, 0x0, 0x8 },
1895 { 0x11678, 0x38, 0x0, 0x0, 0x18 },
1896 { 0xaec0, 0x30, 0x0, 0x0, 0x10 },
1897 { 0x8700, 0x28, 0x0, 0x0, 0x18 },
1898 { 0xec00, 0x10, 0x0, 0x0, 0x10 },
1899 { 0xde38, 0x40, 0x0, 0x0, 0x30 },
1900 { 0x121a8, 0x38, 0x0, 0x0, 0x8 },
1901 { 0xf068, 0x20, 0x0, 0x0, 0x20 },
1902 { 0x2b68, 0x80, 0x0, 0x0, 0x10 },
1903 { 0x4ab8, 0x10, 0x0, 0x0, 0x10 },
1906 /* Runtime array offsets */
1907 #define DORQ_REG_PF_MAX_ICID_0_RT_OFFSET 0
1908 #define DORQ_REG_PF_MAX_ICID_1_RT_OFFSET 1
1909 #define DORQ_REG_PF_MAX_ICID_2_RT_OFFSET 2
1910 #define DORQ_REG_PF_MAX_ICID_3_RT_OFFSET 3
1911 #define DORQ_REG_PF_MAX_ICID_4_RT_OFFSET 4
1912 #define DORQ_REG_PF_MAX_ICID_5_RT_OFFSET 5
1913 #define DORQ_REG_PF_MAX_ICID_6_RT_OFFSET 6
1914 #define DORQ_REG_PF_MAX_ICID_7_RT_OFFSET 7
1915 #define DORQ_REG_VF_MAX_ICID_0_RT_OFFSET 8
1916 #define DORQ_REG_VF_MAX_ICID_1_RT_OFFSET 9
1917 #define DORQ_REG_VF_MAX_ICID_2_RT_OFFSET 10
1918 #define DORQ_REG_VF_MAX_ICID_3_RT_OFFSET 11
1919 #define DORQ_REG_VF_MAX_ICID_4_RT_OFFSET 12
1920 #define DORQ_REG_VF_MAX_ICID_5_RT_OFFSET 13
1921 #define DORQ_REG_VF_MAX_ICID_6_RT_OFFSET 14
1922 #define DORQ_REG_VF_MAX_ICID_7_RT_OFFSET 15
1923 #define DORQ_REG_PF_WAKE_ALL_RT_OFFSET 16
1924 #define DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET 17
1925 #define IGU_REG_PF_CONFIGURATION_RT_OFFSET 18
1926 #define IGU_REG_VF_CONFIGURATION_RT_OFFSET 19
1927 #define IGU_REG_ATTN_MSG_ADDR_L_RT_OFFSET 20
1928 #define IGU_REG_ATTN_MSG_ADDR_H_RT_OFFSET 21
1929 #define IGU_REG_LEADING_EDGE_LATCH_RT_OFFSET 22
1930 #define IGU_REG_TRAILING_EDGE_LATCH_RT_OFFSET 23
1931 #define CAU_REG_CQE_AGG_UNIT_SIZE_RT_OFFSET 24
1932 #define CAU_REG_SB_VAR_MEMORY_RT_OFFSET 761
1933 #define CAU_REG_SB_VAR_MEMORY_RT_SIZE 736
1934 #define CAU_REG_SB_VAR_MEMORY_RT_OFFSET 761
1935 #define CAU_REG_SB_VAR_MEMORY_RT_SIZE 736
1936 #define CAU_REG_SB_ADDR_MEMORY_RT_OFFSET 1497
1937 #define CAU_REG_SB_ADDR_MEMORY_RT_SIZE 736
1938 #define CAU_REG_PI_MEMORY_RT_OFFSET 2233
1939 #define CAU_REG_PI_MEMORY_RT_SIZE 4416
1940 #define PRS_REG_SEARCH_RESP_INITIATOR_TYPE_RT_OFFSET 6649
1941 #define PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET 6650
1942 #define PRS_REG_TASK_ID_MAX_INITIATOR_VF_RT_OFFSET 6651
1943 #define PRS_REG_TASK_ID_MAX_TARGET_PF_RT_OFFSET 6652
1944 #define PRS_REG_TASK_ID_MAX_TARGET_VF_RT_OFFSET 6653
1945 #define PRS_REG_SEARCH_TCP_RT_OFFSET 6654
1946 #define PRS_REG_SEARCH_FCOE_RT_OFFSET 6655
1947 #define PRS_REG_SEARCH_ROCE_RT_OFFSET 6656
1948 #define PRS_REG_ROCE_DEST_QP_MAX_VF_RT_OFFSET 6657
1949 #define PRS_REG_ROCE_DEST_QP_MAX_PF_RT_OFFSET 6658
1950 #define PRS_REG_SEARCH_OPENFLOW_RT_OFFSET 6659
1951 #define PRS_REG_SEARCH_NON_IP_AS_OPENFLOW_RT_OFFSET 6660
1952 #define PRS_REG_OPENFLOW_SUPPORT_ONLY_KNOWN_OVER_IP_RT_OFFSET 6661
1953 #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_RT_OFFSET 6662
1954 #define PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET 6663
1955 #define PRS_REG_LIGHT_L2_ETHERTYPE_EN_RT_OFFSET 6664
1956 #define SRC_REG_FIRSTFREE_RT_OFFSET 6665
1957 #define SRC_REG_FIRSTFREE_RT_SIZE 2
1958 #define SRC_REG_LASTFREE_RT_OFFSET 6667
1959 #define SRC_REG_LASTFREE_RT_SIZE 2
1960 #define SRC_REG_COUNTFREE_RT_OFFSET 6669
1961 #define SRC_REG_NUMBER_HASH_BITS_RT_OFFSET 6670
1962 #define PSWRQ2_REG_CDUT_P_SIZE_RT_OFFSET 6671
1963 #define PSWRQ2_REG_CDUC_P_SIZE_RT_OFFSET 6672
1964 #define PSWRQ2_REG_TM_P_SIZE_RT_OFFSET 6673
1965 #define PSWRQ2_REG_QM_P_SIZE_RT_OFFSET 6674
1966 #define PSWRQ2_REG_SRC_P_SIZE_RT_OFFSET 6675
1967 #define PSWRQ2_REG_TM_FIRST_ILT_RT_OFFSET 6676
1968 #define PSWRQ2_REG_TM_LAST_ILT_RT_OFFSET 6677
1969 #define PSWRQ2_REG_QM_FIRST_ILT_RT_OFFSET 6678
1970 #define PSWRQ2_REG_QM_LAST_ILT_RT_OFFSET 6679
1971 #define PSWRQ2_REG_SRC_FIRST_ILT_RT_OFFSET 6680
1972 #define PSWRQ2_REG_SRC_LAST_ILT_RT_OFFSET 6681
1973 #define PSWRQ2_REG_CDUC_FIRST_ILT_RT_OFFSET 6682
1974 #define PSWRQ2_REG_CDUC_LAST_ILT_RT_OFFSET 6683
1975 #define PSWRQ2_REG_CDUT_FIRST_ILT_RT_OFFSET 6684
1976 #define PSWRQ2_REG_CDUT_LAST_ILT_RT_OFFSET 6685
1977 #define PSWRQ2_REG_TSDM_FIRST_ILT_RT_OFFSET 6686
1978 #define PSWRQ2_REG_TSDM_LAST_ILT_RT_OFFSET 6687
1979 #define PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6688
1980 #define PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6689
1981 #define PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6690
1982 #define PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET 6691
1983 #define PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET 6692
1984 #define PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET 6693
1985 #define PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET 6694
1986 #define PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET 6695
1987 #define PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET 6696
1988 #define PSWRQ2_REG_VF_BASE_RT_OFFSET 6697
1989 #define PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET 6698
1990 #define PSWRQ2_REG_WR_MBS0_RT_OFFSET 6699
1991 #define PSWRQ2_REG_RD_MBS0_RT_OFFSET 6700
1992 #define PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET 6701
1993 #define PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET 6702
1994 #define PSWRQ2_REG_ILT_MEMORY_RT_OFFSET 6703
1995 #define PSWRQ2_REG_ILT_MEMORY_RT_SIZE 22000
1996 #define PGLUE_REG_B_VF_BASE_RT_OFFSET 28703
1997 #define PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET 28704
1998 #define PGLUE_REG_B_PF_BAR0_SIZE_RT_OFFSET 28705
1999 #define PGLUE_REG_B_PF_BAR1_SIZE_RT_OFFSET 28706
2000 #define PGLUE_REG_B_VF_BAR1_SIZE_RT_OFFSET 28707
2001 #define TM_REG_VF_ENABLE_CONN_RT_OFFSET 28708
2002 #define TM_REG_PF_ENABLE_CONN_RT_OFFSET 28709
2003 #define TM_REG_PF_ENABLE_TASK_RT_OFFSET 28710
2004 #define TM_REG_GROUP_SIZE_RESOLUTION_CONN_RT_OFFSET 28711
2005 #define TM_REG_GROUP_SIZE_RESOLUTION_TASK_RT_OFFSET 28712
2006 #define TM_REG_CONFIG_CONN_MEM_RT_OFFSET 28713
2007 #define TM_REG_CONFIG_CONN_MEM_RT_SIZE 416
2008 #define TM_REG_CONFIG_TASK_MEM_RT_OFFSET 29129
2009 #define TM_REG_CONFIG_TASK_MEM_RT_SIZE 512
2010 #define QM_REG_MAXPQSIZE_0_RT_OFFSET 29641
2011 #define QM_REG_MAXPQSIZE_1_RT_OFFSET 29642
2012 #define QM_REG_MAXPQSIZE_2_RT_OFFSET 29643
2013 #define QM_REG_MAXPQSIZETXSEL_0_RT_OFFSET 29644
2014 #define QM_REG_MAXPQSIZETXSEL_1_RT_OFFSET 29645
2015 #define QM_REG_MAXPQSIZETXSEL_2_RT_OFFSET 29646
2016 #define QM_REG_MAXPQSIZETXSEL_3_RT_OFFSET 29647
2017 #define QM_REG_MAXPQSIZETXSEL_4_RT_OFFSET 29648
2018 #define QM_REG_MAXPQSIZETXSEL_5_RT_OFFSET 29649
2019 #define QM_REG_MAXPQSIZETXSEL_6_RT_OFFSET 29650
2020 #define QM_REG_MAXPQSIZETXSEL_7_RT_OFFSET 29651
2021 #define QM_REG_MAXPQSIZETXSEL_8_RT_OFFSET 29652
2022 #define QM_REG_MAXPQSIZETXSEL_9_RT_OFFSET 29653
2023 #define QM_REG_MAXPQSIZETXSEL_10_RT_OFFSET 29654
2024 #define QM_REG_MAXPQSIZETXSEL_11_RT_OFFSET 29655
2025 #define QM_REG_MAXPQSIZETXSEL_12_RT_OFFSET 29656
2026 #define QM_REG_MAXPQSIZETXSEL_13_RT_OFFSET 29657
2027 #define QM_REG_MAXPQSIZETXSEL_14_RT_OFFSET 29658
2028 #define QM_REG_MAXPQSIZETXSEL_15_RT_OFFSET 29659
2029 #define QM_REG_MAXPQSIZETXSEL_16_RT_OFFSET 29660
2030 #define QM_REG_MAXPQSIZETXSEL_17_RT_OFFSET 29661
2031 #define QM_REG_MAXPQSIZETXSEL_18_RT_OFFSET 29662
2032 #define QM_REG_MAXPQSIZETXSEL_19_RT_OFFSET 29663
2033 #define QM_REG_MAXPQSIZETXSEL_20_RT_OFFSET 29664
2034 #define QM_REG_MAXPQSIZETXSEL_21_RT_OFFSET 29665
2035 #define QM_REG_MAXPQSIZETXSEL_22_RT_OFFSET 29666
2036 #define QM_REG_MAXPQSIZETXSEL_23_RT_OFFSET 29667
2037 #define QM_REG_MAXPQSIZETXSEL_24_RT_OFFSET 29668
2038 #define QM_REG_MAXPQSIZETXSEL_25_RT_OFFSET 29669
2039 #define QM_REG_MAXPQSIZETXSEL_26_RT_OFFSET 29670
2040 #define QM_REG_MAXPQSIZETXSEL_27_RT_OFFSET 29671
2041 #define QM_REG_MAXPQSIZETXSEL_28_RT_OFFSET 29672
2042 #define QM_REG_MAXPQSIZETXSEL_29_RT_OFFSET 29673
2043 #define QM_REG_MAXPQSIZETXSEL_30_RT_OFFSET 29674
2044 #define QM_REG_MAXPQSIZETXSEL_31_RT_OFFSET 29675
2045 #define QM_REG_MAXPQSIZETXSEL_32_RT_OFFSET 29676
2046 #define QM_REG_MAXPQSIZETXSEL_33_RT_OFFSET 29677
2047 #define QM_REG_MAXPQSIZETXSEL_34_RT_OFFSET 29678
2048 #define QM_REG_MAXPQSIZETXSEL_35_RT_OFFSET 29679
2049 #define QM_REG_MAXPQSIZETXSEL_36_RT_OFFSET 29680
2050 #define QM_REG_MAXPQSIZETXSEL_37_RT_OFFSET 29681
2051 #define QM_REG_MAXPQSIZETXSEL_38_RT_OFFSET 29682
2052 #define QM_REG_MAXPQSIZETXSEL_39_RT_OFFSET 29683
2053 #define QM_REG_MAXPQSIZETXSEL_40_RT_OFFSET 29684
2054 #define QM_REG_MAXPQSIZETXSEL_41_RT_OFFSET 29685
2055 #define QM_REG_MAXPQSIZETXSEL_42_RT_OFFSET 29686
2056 #define QM_REG_MAXPQSIZETXSEL_43_RT_OFFSET 29687
2057 #define QM_REG_MAXPQSIZETXSEL_44_RT_OFFSET 29688
2058 #define QM_REG_MAXPQSIZETXSEL_45_RT_OFFSET 29689
2059 #define QM_REG_MAXPQSIZETXSEL_46_RT_OFFSET 29690
2060 #define QM_REG_MAXPQSIZETXSEL_47_RT_OFFSET 29691
2061 #define QM_REG_MAXPQSIZETXSEL_48_RT_OFFSET 29692
2062 #define QM_REG_MAXPQSIZETXSEL_49_RT_OFFSET 29693
2063 #define QM_REG_MAXPQSIZETXSEL_50_RT_OFFSET 29694
2064 #define QM_REG_MAXPQSIZETXSEL_51_RT_OFFSET 29695
2065 #define QM_REG_MAXPQSIZETXSEL_52_RT_OFFSET 29696
2066 #define QM_REG_MAXPQSIZETXSEL_53_RT_OFFSET 29697
2067 #define QM_REG_MAXPQSIZETXSEL_54_RT_OFFSET 29698
2068 #define QM_REG_MAXPQSIZETXSEL_55_RT_OFFSET 29699
2069 #define QM_REG_MAXPQSIZETXSEL_56_RT_OFFSET 29700
2070 #define QM_REG_MAXPQSIZETXSEL_57_RT_OFFSET 29701
2071 #define QM_REG_MAXPQSIZETXSEL_58_RT_OFFSET 29702
2072 #define QM_REG_MAXPQSIZETXSEL_59_RT_OFFSET 29703
2073 #define QM_REG_MAXPQSIZETXSEL_60_RT_OFFSET 29704
2074 #define QM_REG_MAXPQSIZETXSEL_61_RT_OFFSET 29705
2075 #define QM_REG_MAXPQSIZETXSEL_62_RT_OFFSET 29706
2076 #define QM_REG_MAXPQSIZETXSEL_63_RT_OFFSET 29707
2077 #define QM_REG_BASEADDROTHERPQ_RT_OFFSET 29708
2078 #define QM_REG_BASEADDROTHERPQ_RT_SIZE 128
2079 #define QM_REG_VOQCRDLINE_RT_OFFSET 29836
2080 #define QM_REG_VOQCRDLINE_RT_SIZE 20
2081 #define QM_REG_VOQINITCRDLINE_RT_OFFSET 29856
2082 #define QM_REG_VOQINITCRDLINE_RT_SIZE 20
2083 #define QM_REG_AFULLQMBYPTHRPFWFQ_RT_OFFSET 29876
2084 #define QM_REG_AFULLQMBYPTHRVPWFQ_RT_OFFSET 29877
2085 #define QM_REG_AFULLQMBYPTHRPFRL_RT_OFFSET 29878
2086 #define QM_REG_AFULLQMBYPTHRGLBLRL_RT_OFFSET 29879
2087 #define QM_REG_AFULLOPRTNSTCCRDMASK_RT_OFFSET 29880
2088 #define QM_REG_WRROTHERPQGRP_0_RT_OFFSET 29881
2089 #define QM_REG_WRROTHERPQGRP_1_RT_OFFSET 29882
2090 #define QM_REG_WRROTHERPQGRP_2_RT_OFFSET 29883
2091 #define QM_REG_WRROTHERPQGRP_3_RT_OFFSET 29884
2092 #define QM_REG_WRROTHERPQGRP_4_RT_OFFSET 29885
2093 #define QM_REG_WRROTHERPQGRP_5_RT_OFFSET 29886
2094 #define QM_REG_WRROTHERPQGRP_6_RT_OFFSET 29887
2095 #define QM_REG_WRROTHERPQGRP_7_RT_OFFSET 29888
2096 #define QM_REG_WRROTHERPQGRP_8_RT_OFFSET 29889
2097 #define QM_REG_WRROTHERPQGRP_9_RT_OFFSET 29890
2098 #define QM_REG_WRROTHERPQGRP_10_RT_OFFSET 29891
2099 #define QM_REG_WRROTHERPQGRP_11_RT_OFFSET 29892
2100 #define QM_REG_WRROTHERPQGRP_12_RT_OFFSET 29893
2101 #define QM_REG_WRROTHERPQGRP_13_RT_OFFSET 29894
2102 #define QM_REG_WRROTHERPQGRP_14_RT_OFFSET 29895
2103 #define QM_REG_WRROTHERPQGRP_15_RT_OFFSET 29896
2104 #define QM_REG_WRROTHERGRPWEIGHT_0_RT_OFFSET 29897
2105 #define QM_REG_WRROTHERGRPWEIGHT_1_RT_OFFSET 29898
2106 #define QM_REG_WRROTHERGRPWEIGHT_2_RT_OFFSET 29899
2107 #define QM_REG_WRROTHERGRPWEIGHT_3_RT_OFFSET 29900
2108 #define QM_REG_WRRTXGRPWEIGHT_0_RT_OFFSET 29901
2109 #define QM_REG_WRRTXGRPWEIGHT_1_RT_OFFSET 29902
2110 #define QM_REG_PQTX2PF_0_RT_OFFSET 29903
2111 #define QM_REG_PQTX2PF_1_RT_OFFSET 29904
2112 #define QM_REG_PQTX2PF_2_RT_OFFSET 29905
2113 #define QM_REG_PQTX2PF_3_RT_OFFSET 29906
2114 #define QM_REG_PQTX2PF_4_RT_OFFSET 29907
2115 #define QM_REG_PQTX2PF_5_RT_OFFSET 29908
2116 #define QM_REG_PQTX2PF_6_RT_OFFSET 29909
2117 #define QM_REG_PQTX2PF_7_RT_OFFSET 29910
2118 #define QM_REG_PQTX2PF_8_RT_OFFSET 29911
2119 #define QM_REG_PQTX2PF_9_RT_OFFSET 29912
2120 #define QM_REG_PQTX2PF_10_RT_OFFSET 29913
2121 #define QM_REG_PQTX2PF_11_RT_OFFSET 29914
2122 #define QM_REG_PQTX2PF_12_RT_OFFSET 29915
2123 #define QM_REG_PQTX2PF_13_RT_OFFSET 29916
2124 #define QM_REG_PQTX2PF_14_RT_OFFSET 29917
2125 #define QM_REG_PQTX2PF_15_RT_OFFSET 29918
2126 #define QM_REG_PQTX2PF_16_RT_OFFSET 29919
2127 #define QM_REG_PQTX2PF_17_RT_OFFSET 29920
2128 #define QM_REG_PQTX2PF_18_RT_OFFSET 29921
2129 #define QM_REG_PQTX2PF_19_RT_OFFSET 29922
2130 #define QM_REG_PQTX2PF_20_RT_OFFSET 29923
2131 #define QM_REG_PQTX2PF_21_RT_OFFSET 29924
2132 #define QM_REG_PQTX2PF_22_RT_OFFSET 29925
2133 #define QM_REG_PQTX2PF_23_RT_OFFSET 29926
2134 #define QM_REG_PQTX2PF_24_RT_OFFSET 29927
2135 #define QM_REG_PQTX2PF_25_RT_OFFSET 29928
2136 #define QM_REG_PQTX2PF_26_RT_OFFSET 29929
2137 #define QM_REG_PQTX2PF_27_RT_OFFSET 29930
2138 #define QM_REG_PQTX2PF_28_RT_OFFSET 29931
2139 #define QM_REG_PQTX2PF_29_RT_OFFSET 29932
2140 #define QM_REG_PQTX2PF_30_RT_OFFSET 29933
2141 #define QM_REG_PQTX2PF_31_RT_OFFSET 29934
2142 #define QM_REG_PQTX2PF_32_RT_OFFSET 29935
2143 #define QM_REG_PQTX2PF_33_RT_OFFSET 29936
2144 #define QM_REG_PQTX2PF_34_RT_OFFSET 29937
2145 #define QM_REG_PQTX2PF_35_RT_OFFSET 29938
2146 #define QM_REG_PQTX2PF_36_RT_OFFSET 29939
2147 #define QM_REG_PQTX2PF_37_RT_OFFSET 29940
2148 #define QM_REG_PQTX2PF_38_RT_OFFSET 29941
2149 #define QM_REG_PQTX2PF_39_RT_OFFSET 29942
2150 #define QM_REG_PQTX2PF_40_RT_OFFSET 29943
2151 #define QM_REG_PQTX2PF_41_RT_OFFSET 29944
2152 #define QM_REG_PQTX2PF_42_RT_OFFSET 29945
2153 #define QM_REG_PQTX2PF_43_RT_OFFSET 29946
2154 #define QM_REG_PQTX2PF_44_RT_OFFSET 29947
2155 #define QM_REG_PQTX2PF_45_RT_OFFSET 29948
2156 #define QM_REG_PQTX2PF_46_RT_OFFSET 29949
2157 #define QM_REG_PQTX2PF_47_RT_OFFSET 29950
2158 #define QM_REG_PQTX2PF_48_RT_OFFSET 29951
2159 #define QM_REG_PQTX2PF_49_RT_OFFSET 29952
2160 #define QM_REG_PQTX2PF_50_RT_OFFSET 29953
2161 #define QM_REG_PQTX2PF_51_RT_OFFSET 29954
2162 #define QM_REG_PQTX2PF_52_RT_OFFSET 29955
2163 #define QM_REG_PQTX2PF_53_RT_OFFSET 29956
2164 #define QM_REG_PQTX2PF_54_RT_OFFSET 29957
2165 #define QM_REG_PQTX2PF_55_RT_OFFSET 29958
2166 #define QM_REG_PQTX2PF_56_RT_OFFSET 29959
2167 #define QM_REG_PQTX2PF_57_RT_OFFSET 29960
2168 #define QM_REG_PQTX2PF_58_RT_OFFSET 29961
2169 #define QM_REG_PQTX2PF_59_RT_OFFSET 29962
2170 #define QM_REG_PQTX2PF_60_RT_OFFSET 29963
2171 #define QM_REG_PQTX2PF_61_RT_OFFSET 29964
2172 #define QM_REG_PQTX2PF_62_RT_OFFSET 29965
2173 #define QM_REG_PQTX2PF_63_RT_OFFSET 29966
2174 #define QM_REG_PQOTHER2PF_0_RT_OFFSET 29967
2175 #define QM_REG_PQOTHER2PF_1_RT_OFFSET 29968
2176 #define QM_REG_PQOTHER2PF_2_RT_OFFSET 29969
2177 #define QM_REG_PQOTHER2PF_3_RT_OFFSET 29970
2178 #define QM_REG_PQOTHER2PF_4_RT_OFFSET 29971
2179 #define QM_REG_PQOTHER2PF_5_RT_OFFSET 29972
2180 #define QM_REG_PQOTHER2PF_6_RT_OFFSET 29973
2181 #define QM_REG_PQOTHER2PF_7_RT_OFFSET 29974
2182 #define QM_REG_PQOTHER2PF_8_RT_OFFSET 29975
2183 #define QM_REG_PQOTHER2PF_9_RT_OFFSET 29976
2184 #define QM_REG_PQOTHER2PF_10_RT_OFFSET 29977
2185 #define QM_REG_PQOTHER2PF_11_RT_OFFSET 29978
2186 #define QM_REG_PQOTHER2PF_12_RT_OFFSET 29979
2187 #define QM_REG_PQOTHER2PF_13_RT_OFFSET 29980
2188 #define QM_REG_PQOTHER2PF_14_RT_OFFSET 29981
2189 #define QM_REG_PQOTHER2PF_15_RT_OFFSET 29982
2190 #define QM_REG_RLGLBLPERIOD_0_RT_OFFSET 29983
2191 #define QM_REG_RLGLBLPERIOD_1_RT_OFFSET 29984
2192 #define QM_REG_RLGLBLPERIODTIMER_0_RT_OFFSET 29985
2193 #define QM_REG_RLGLBLPERIODTIMER_1_RT_OFFSET 29986
2194 #define QM_REG_RLGLBLPERIODSEL_0_RT_OFFSET 29987
2195 #define QM_REG_RLGLBLPERIODSEL_1_RT_OFFSET 29988
2196 #define QM_REG_RLGLBLPERIODSEL_2_RT_OFFSET 29989
2197 #define QM_REG_RLGLBLPERIODSEL_3_RT_OFFSET 29990
2198 #define QM_REG_RLGLBLPERIODSEL_4_RT_OFFSET 29991
2199 #define QM_REG_RLGLBLPERIODSEL_5_RT_OFFSET 29992
2200 #define QM_REG_RLGLBLPERIODSEL_6_RT_OFFSET 29993
2201 #define QM_REG_RLGLBLPERIODSEL_7_RT_OFFSET 29994
2202 #define QM_REG_RLGLBLINCVAL_RT_OFFSET 29995
2203 #define QM_REG_RLGLBLINCVAL_RT_SIZE 256
2204 #define QM_REG_RLGLBLUPPERBOUND_RT_OFFSET 30251
2205 #define QM_REG_RLGLBLUPPERBOUND_RT_SIZE 256
2206 #define QM_REG_RLGLBLCRD_RT_OFFSET 30507
2207 #define QM_REG_RLGLBLCRD_RT_SIZE 256
2208 #define QM_REG_RLGLBLENABLE_RT_OFFSET 30763
2209 #define QM_REG_RLPFPERIOD_RT_OFFSET 30764
2210 #define QM_REG_RLPFPERIODTIMER_RT_OFFSET 30765
2211 #define QM_REG_RLPFINCVAL_RT_OFFSET 30766
2212 #define QM_REG_RLPFINCVAL_RT_SIZE 16
2213 #define QM_REG_RLPFUPPERBOUND_RT_OFFSET 30782
2214 #define QM_REG_RLPFUPPERBOUND_RT_SIZE 16
2215 #define QM_REG_RLPFCRD_RT_OFFSET 30798
2216 #define QM_REG_RLPFCRD_RT_SIZE 16
2217 #define QM_REG_RLPFENABLE_RT_OFFSET 30814
2218 #define QM_REG_RLPFVOQENABLE_RT_OFFSET 30815
2219 #define QM_REG_WFQPFWEIGHT_RT_OFFSET 30816
2220 #define QM_REG_WFQPFWEIGHT_RT_SIZE 16
2221 #define QM_REG_WFQPFUPPERBOUND_RT_OFFSET 30832
2222 #define QM_REG_WFQPFUPPERBOUND_RT_SIZE 16
2223 #define QM_REG_WFQPFCRD_RT_OFFSET 30848
2224 #define QM_REG_WFQPFCRD_RT_SIZE 160
2225 #define QM_REG_WFQPFENABLE_RT_OFFSET 31008
2226 #define QM_REG_WFQVPENABLE_RT_OFFSET 31009
2227 #define QM_REG_BASEADDRTXPQ_RT_OFFSET 31010
2228 #define QM_REG_BASEADDRTXPQ_RT_SIZE 512
2229 #define QM_REG_TXPQMAP_RT_OFFSET 31522
2230 #define QM_REG_TXPQMAP_RT_SIZE 512
2231 #define QM_REG_WFQVPWEIGHT_RT_OFFSET 32034
2232 #define QM_REG_WFQVPWEIGHT_RT_SIZE 512
2233 #define QM_REG_WFQVPCRD_RT_OFFSET 32546
2234 #define QM_REG_WFQVPCRD_RT_SIZE 512
2235 #define QM_REG_WFQVPMAP_RT_OFFSET 33058
2236 #define QM_REG_WFQVPMAP_RT_SIZE 512
2237 #define QM_REG_WFQPFCRD_MSB_RT_OFFSET 33570
2238 #define QM_REG_WFQPFCRD_MSB_RT_SIZE 160
2239 #define NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET 33730
2240 #define NIG_REG_OUTER_TAG_VALUE_LIST0_RT_OFFSET 33731
2241 #define NIG_REG_OUTER_TAG_VALUE_LIST1_RT_OFFSET 33732
2242 #define NIG_REG_OUTER_TAG_VALUE_LIST2_RT_OFFSET 33733
2243 #define NIG_REG_OUTER_TAG_VALUE_LIST3_RT_OFFSET 33734
2244 #define NIG_REG_OUTER_TAG_VALUE_MASK_RT_OFFSET 33735
2245 #define NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET 33736
2246 #define NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET 33737
2247 #define NIG_REG_LLH_FUNC_TAG_EN_RT_SIZE 4
2248 #define NIG_REG_LLH_FUNC_TAG_HDR_SEL_RT_OFFSET 33741
2249 #define NIG_REG_LLH_FUNC_TAG_HDR_SEL_RT_SIZE 4
2250 #define NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET 33745
2251 #define NIG_REG_LLH_FUNC_TAG_VALUE_RT_SIZE 4
2252 #define NIG_REG_LLH_FUNC_NO_TAG_RT_OFFSET 33749
2253 #define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_OFFSET 33750
2254 #define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_SIZE 32
2255 #define NIG_REG_LLH_FUNC_FILTER_EN_RT_OFFSET 33782
2256 #define NIG_REG_LLH_FUNC_FILTER_EN_RT_SIZE 16
2257 #define NIG_REG_LLH_FUNC_FILTER_MODE_RT_OFFSET 33798
2258 #define NIG_REG_LLH_FUNC_FILTER_MODE_RT_SIZE 16
2259 #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_OFFSET 33814
2260 #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_SIZE 16
2261 #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET 33830
2262 #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_SIZE 16
2263 #define NIG_REG_TX_EDPM_CTRL_RT_OFFSET 33846
2264 #define CDU_REG_CID_ADDR_PARAMS_RT_OFFSET 33847
2265 #define CDU_REG_SEGMENT0_PARAMS_RT_OFFSET 33848
2266 #define CDU_REG_SEGMENT1_PARAMS_RT_OFFSET 33849
2267 #define CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET 33850
2268 #define CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET 33851
2269 #define CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET 33852
2270 #define CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET 33853
2271 #define CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET 33854
2272 #define CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET 33855
2273 #define CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET 33856
2274 #define CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET 33857
2275 #define CDU_REG_VF_SEG_TYPE_OFFSET_RT_OFFSET 33858
2276 #define CDU_REG_VF_FL_SEG_TYPE_OFFSET_RT_OFFSET 33859
2277 #define PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET 33860
2278 #define PBF_REG_BTB_SHARED_AREA_SIZE_RT_OFFSET 33861
2279 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET 33862
2280 #define PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET 33863
2281 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ0_RT_OFFSET 33864
2282 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ1_RT_OFFSET 33865
2283 #define PBF_REG_BTB_GUARANTEED_VOQ1_RT_OFFSET 33866
2284 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ1_RT_OFFSET 33867
2285 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ2_RT_OFFSET 33868
2286 #define PBF_REG_BTB_GUARANTEED_VOQ2_RT_OFFSET 33869
2287 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ2_RT_OFFSET 33870
2288 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ3_RT_OFFSET 33871
2289 #define PBF_REG_BTB_GUARANTEED_VOQ3_RT_OFFSET 33872
2290 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ3_RT_OFFSET 33873
2291 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ4_RT_OFFSET 33874
2292 #define PBF_REG_BTB_GUARANTEED_VOQ4_RT_OFFSET 33875
2293 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ4_RT_OFFSET 33876
2294 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ5_RT_OFFSET 33877
2295 #define PBF_REG_BTB_GUARANTEED_VOQ5_RT_OFFSET 33878
2296 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ5_RT_OFFSET 33879
2297 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ6_RT_OFFSET 33880
2298 #define PBF_REG_BTB_GUARANTEED_VOQ6_RT_OFFSET 33881
2299 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ6_RT_OFFSET 33882
2300 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ7_RT_OFFSET 33883
2301 #define PBF_REG_BTB_GUARANTEED_VOQ7_RT_OFFSET 33884
2302 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ7_RT_OFFSET 33885
2303 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ8_RT_OFFSET 33886
2304 #define PBF_REG_BTB_GUARANTEED_VOQ8_RT_OFFSET 33887
2305 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ8_RT_OFFSET 33888
2306 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ9_RT_OFFSET 33889
2307 #define PBF_REG_BTB_GUARANTEED_VOQ9_RT_OFFSET 33890
2308 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ9_RT_OFFSET 33891
2309 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ10_RT_OFFSET 33892
2310 #define PBF_REG_BTB_GUARANTEED_VOQ10_RT_OFFSET 33893
2311 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ10_RT_OFFSET 33894
2312 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ11_RT_OFFSET 33895
2313 #define PBF_REG_BTB_GUARANTEED_VOQ11_RT_OFFSET 33896
2314 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ11_RT_OFFSET 33897
2315 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ12_RT_OFFSET 33898
2316 #define PBF_REG_BTB_GUARANTEED_VOQ12_RT_OFFSET 33899
2317 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ12_RT_OFFSET 33900
2318 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ13_RT_OFFSET 33901
2319 #define PBF_REG_BTB_GUARANTEED_VOQ13_RT_OFFSET 33902
2320 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ13_RT_OFFSET 33903
2321 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ14_RT_OFFSET 33904
2322 #define PBF_REG_BTB_GUARANTEED_VOQ14_RT_OFFSET 33905
2323 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ14_RT_OFFSET 33906
2324 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ15_RT_OFFSET 33907
2325 #define PBF_REG_BTB_GUARANTEED_VOQ15_RT_OFFSET 33908
2326 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ15_RT_OFFSET 33909
2327 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ16_RT_OFFSET 33910
2328 #define PBF_REG_BTB_GUARANTEED_VOQ16_RT_OFFSET 33911
2329 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ16_RT_OFFSET 33912
2330 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ17_RT_OFFSET 33913
2331 #define PBF_REG_BTB_GUARANTEED_VOQ17_RT_OFFSET 33914
2332 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ17_RT_OFFSET 33915
2333 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ18_RT_OFFSET 33916
2334 #define PBF_REG_BTB_GUARANTEED_VOQ18_RT_OFFSET 33917
2335 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ18_RT_OFFSET 33918
2336 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ19_RT_OFFSET 33919
2337 #define PBF_REG_BTB_GUARANTEED_VOQ19_RT_OFFSET 33920
2338 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ19_RT_OFFSET 33921
2339 #define XCM_REG_CON_PHY_Q3_RT_OFFSET 33922
2341 #define RUNTIME_ARRAY_SIZE 33923
2343 /* The eth storm context for the Tstorm */
2344 struct tstorm_eth_conn_st_ctx {
2348 /* The eth storm context for the Pstorm */
2349 struct pstorm_eth_conn_st_ctx {
2353 /* The eth storm context for the Xstorm */
2354 struct xstorm_eth_conn_st_ctx {
2355 __le32 reserved[60];
2358 struct xstorm_eth_conn_ag_ctx {
2359 u8 reserved0 /* cdu_validation */;
2360 u8 eth_state /* state */;
2362 #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
2363 #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
2364 #define XSTORM_ETH_CONN_AG_CTX_RESERVED1_MASK 0x1
2365 #define XSTORM_ETH_CONN_AG_CTX_RESERVED1_SHIFT 1
2366 #define XSTORM_ETH_CONN_AG_CTX_RESERVED2_MASK 0x1
2367 #define XSTORM_ETH_CONN_AG_CTX_RESERVED2_SHIFT 2
2368 #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
2369 #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
2370 #define XSTORM_ETH_CONN_AG_CTX_RESERVED3_MASK 0x1 /* bit4 */
2371 #define XSTORM_ETH_CONN_AG_CTX_RESERVED3_SHIFT 4
2372 #define XSTORM_ETH_CONN_AG_CTX_RESERVED4_MASK 0x1
2373 #define XSTORM_ETH_CONN_AG_CTX_RESERVED4_SHIFT 5
2374 #define XSTORM_ETH_CONN_AG_CTX_RESERVED5_MASK 0x1 /* bit6 */
2375 #define XSTORM_ETH_CONN_AG_CTX_RESERVED5_SHIFT 6
2376 #define XSTORM_ETH_CONN_AG_CTX_RESERVED6_MASK 0x1 /* bit7 */
2377 #define XSTORM_ETH_CONN_AG_CTX_RESERVED6_SHIFT 7
2379 #define XSTORM_ETH_CONN_AG_CTX_RESERVED7_MASK 0x1 /* bit8 */
2380 #define XSTORM_ETH_CONN_AG_CTX_RESERVED7_SHIFT 0
2381 #define XSTORM_ETH_CONN_AG_CTX_RESERVED8_MASK 0x1 /* bit9 */
2382 #define XSTORM_ETH_CONN_AG_CTX_RESERVED8_SHIFT 1
2383 #define XSTORM_ETH_CONN_AG_CTX_RESERVED9_MASK 0x1 /* bit10 */
2384 #define XSTORM_ETH_CONN_AG_CTX_RESERVED9_SHIFT 2
2385 #define XSTORM_ETH_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */
2386 #define XSTORM_ETH_CONN_AG_CTX_BIT11_SHIFT 3
2387 #define XSTORM_ETH_CONN_AG_CTX_BIT12_MASK 0x1 /* bit12 */
2388 #define XSTORM_ETH_CONN_AG_CTX_BIT12_SHIFT 4
2389 #define XSTORM_ETH_CONN_AG_CTX_BIT13_MASK 0x1 /* bit13 */
2390 #define XSTORM_ETH_CONN_AG_CTX_BIT13_SHIFT 5
2391 #define XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1 /* bit14 */
2392 #define XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6
2393 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1 /* bit15 */
2394 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7
2396 #define XSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */
2397 #define XSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 0
2398 #define XSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */
2399 #define XSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 2
2400 #define XSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */
2401 #define XSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 4
2402 #define XSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3
2403 #define XSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 6
2405 #define XSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */
2406 #define XSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 0
2407 #define XSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */
2408 #define XSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 2
2409 #define XSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */
2410 #define XSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 4
2411 #define XSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */
2412 #define XSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 6
2414 #define XSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */
2415 #define XSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 0
2416 #define XSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */
2417 #define XSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 2
2418 #define XSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */
2419 #define XSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 4
2420 #define XSTORM_ETH_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */
2421 #define XSTORM_ETH_CONN_AG_CTX_CF11_SHIFT 6
2423 #define XSTORM_ETH_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */
2424 #define XSTORM_ETH_CONN_AG_CTX_CF12_SHIFT 0
2425 #define XSTORM_ETH_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */
2426 #define XSTORM_ETH_CONN_AG_CTX_CF13_SHIFT 2
2427 #define XSTORM_ETH_CONN_AG_CTX_CF14_MASK 0x3 /* cf14 */
2428 #define XSTORM_ETH_CONN_AG_CTX_CF14_SHIFT 4
2429 #define XSTORM_ETH_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */
2430 #define XSTORM_ETH_CONN_AG_CTX_CF15_SHIFT 6
2432 #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3 /* cf16 */
2433 #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0
2434 #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3
2435 #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT 2
2436 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_MASK 0x3 /* cf18 */
2437 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_SHIFT 4
2438 #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_MASK 0x3 /* cf19 */
2439 #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_SHIFT 6
2441 #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 /* cf20 */
2442 #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
2443 #define XSTORM_ETH_CONN_AG_CTX_RESERVED10_MASK 0x3 /* cf21 */
2444 #define XSTORM_ETH_CONN_AG_CTX_RESERVED10_SHIFT 2
2445 #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */
2446 #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_SHIFT 4
2447 #define XSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
2448 #define XSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 6
2449 #define XSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
2450 #define XSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 7
2452 #define XSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
2453 #define XSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 0
2454 #define XSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */
2455 #define XSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 1
2456 #define XSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */
2457 #define XSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 2
2458 #define XSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */
2459 #define XSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 3
2460 #define XSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */
2461 #define XSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 4
2462 #define XSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */
2463 #define XSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 5
2464 #define XSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */
2465 #define XSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 6
2466 #define XSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */
2467 #define XSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 7
2469 #define XSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */
2470 #define XSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 0
2471 #define XSTORM_ETH_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */
2472 #define XSTORM_ETH_CONN_AG_CTX_CF11EN_SHIFT 1
2473 #define XSTORM_ETH_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */
2474 #define XSTORM_ETH_CONN_AG_CTX_CF12EN_SHIFT 2
2475 #define XSTORM_ETH_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */
2476 #define XSTORM_ETH_CONN_AG_CTX_CF13EN_SHIFT 3
2477 #define XSTORM_ETH_CONN_AG_CTX_CF14EN_MASK 0x1 /* cf14en */
2478 #define XSTORM_ETH_CONN_AG_CTX_CF14EN_SHIFT 4
2479 #define XSTORM_ETH_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */
2480 #define XSTORM_ETH_CONN_AG_CTX_CF15EN_SHIFT 5
2481 #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1 /* cf16en */
2482 #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT 6
2483 #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1
2484 #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT 7
2486 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_MASK 0x1 /* cf18en */
2487 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_SHIFT 0
2488 #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1 /* cf19en */
2489 #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1
2490 #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 /* cf20en */
2491 #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
2492 #define XSTORM_ETH_CONN_AG_CTX_RESERVED11_MASK 0x1 /* cf21en */
2493 #define XSTORM_ETH_CONN_AG_CTX_RESERVED11_SHIFT 3
2494 #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */
2495 #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
2496 #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1 /* cf23en */
2497 #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5
2498 #define XSTORM_ETH_CONN_AG_CTX_RESERVED12_MASK 0x1 /* rule0en */
2499 #define XSTORM_ETH_CONN_AG_CTX_RESERVED12_SHIFT 6
2500 #define XSTORM_ETH_CONN_AG_CTX_RESERVED13_MASK 0x1 /* rule1en */
2501 #define XSTORM_ETH_CONN_AG_CTX_RESERVED13_SHIFT 7
2503 #define XSTORM_ETH_CONN_AG_CTX_RESERVED14_MASK 0x1 /* rule2en */
2504 #define XSTORM_ETH_CONN_AG_CTX_RESERVED14_SHIFT 0
2505 #define XSTORM_ETH_CONN_AG_CTX_RESERVED15_MASK 0x1 /* rule3en */
2506 #define XSTORM_ETH_CONN_AG_CTX_RESERVED15_SHIFT 1
2507 #define XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1 /* rule4en */
2508 #define XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2
2509 #define XSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
2510 #define XSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 3
2511 #define XSTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */
2512 #define XSTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 4
2513 #define XSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */
2514 #define XSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 5
2515 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */
2516 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
2517 #define XSTORM_ETH_CONN_AG_CTX_RULE9EN_MASK 0x1 /* rule9en */
2518 #define XSTORM_ETH_CONN_AG_CTX_RULE9EN_SHIFT 7
2520 #define XSTORM_ETH_CONN_AG_CTX_RULE10EN_MASK 0x1 /* rule10en */
2521 #define XSTORM_ETH_CONN_AG_CTX_RULE10EN_SHIFT 0
2522 #define XSTORM_ETH_CONN_AG_CTX_RULE11EN_MASK 0x1 /* rule11en */
2523 #define XSTORM_ETH_CONN_AG_CTX_RULE11EN_SHIFT 1
2524 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */
2525 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
2526 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */
2527 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
2528 #define XSTORM_ETH_CONN_AG_CTX_RULE14EN_MASK 0x1 /* rule14en */
2529 #define XSTORM_ETH_CONN_AG_CTX_RULE14EN_SHIFT 4
2530 #define XSTORM_ETH_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */
2531 #define XSTORM_ETH_CONN_AG_CTX_RULE15EN_SHIFT 5
2532 #define XSTORM_ETH_CONN_AG_CTX_RULE16EN_MASK 0x1 /* rule16en */
2533 #define XSTORM_ETH_CONN_AG_CTX_RULE16EN_SHIFT 6
2534 #define XSTORM_ETH_CONN_AG_CTX_RULE17EN_MASK 0x1 /* rule17en */
2535 #define XSTORM_ETH_CONN_AG_CTX_RULE17EN_SHIFT 7
2537 #define XSTORM_ETH_CONN_AG_CTX_RULE18EN_MASK 0x1 /* rule18en */
2538 #define XSTORM_ETH_CONN_AG_CTX_RULE18EN_SHIFT 0
2539 #define XSTORM_ETH_CONN_AG_CTX_RULE19EN_MASK 0x1 /* rule19en */
2540 #define XSTORM_ETH_CONN_AG_CTX_RULE19EN_SHIFT 1
2541 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 /* rule20en */
2542 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
2543 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 /* rule21en */
2544 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
2545 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */
2546 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
2547 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 /* rule23en */
2548 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
2549 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */
2550 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
2551 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */
2552 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
2554 #define XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1 /* bit16 */
2555 #define XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0
2556 #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1 /* bit17 */
2557 #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT 1
2558 #define XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1 /* bit18 */
2559 #define XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2
2560 #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1 /* bit19 */
2561 #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3
2562 #define XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1 /* bit20 */
2563 #define XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT 4
2564 #define XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1 /* bit21 */
2565 #define XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
2566 #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_MASK 0x3 /* cf23 */
2567 #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_SHIFT 6
2568 u8 edpm_event_id /* byte2 */;
2569 __le16 physical_q0 /* physical_q0 */;
2570 __le16 word1 /* physical_q1 */;
2571 __le16 edpm_num_bds /* physical_q2 */;
2572 __le16 tx_bd_cons /* word3 */;
2573 __le16 tx_bd_prod /* word4 */;
2574 __le16 go_to_bd_cons /* word5 */;
2575 __le16 conn_dpi /* conn_dpi */;
2576 u8 byte3 /* byte3 */;
2577 u8 byte4 /* byte4 */;
2578 u8 byte5 /* byte5 */;
2579 u8 byte6 /* byte6 */;
2580 __le32 reg0 /* reg0 */;
2581 __le32 reg1 /* reg1 */;
2582 __le32 reg2 /* reg2 */;
2583 __le32 reg3 /* reg3 */;
2584 __le32 reg4 /* reg4 */;
2585 __le32 reg5 /* cf_array0 */;
2586 __le32 reg6 /* cf_array1 */;
2587 __le16 word7 /* word7 */;
2588 __le16 word8 /* word8 */;
2589 __le16 word9 /* word9 */;
2590 __le16 word10 /* word10 */;
2591 __le32 reg7 /* reg7 */;
2592 __le32 reg8 /* reg8 */;
2593 __le32 reg9 /* reg9 */;
2594 u8 byte7 /* byte7 */;
2595 u8 byte8 /* byte8 */;
2596 u8 byte9 /* byte9 */;
2597 u8 byte10 /* byte10 */;
2598 u8 byte11 /* byte11 */;
2599 u8 byte12 /* byte12 */;
2600 u8 byte13 /* byte13 */;
2601 u8 byte14 /* byte14 */;
2602 u8 byte15 /* byte15 */;
2603 u8 byte16 /* byte16 */;
2604 __le16 word11 /* word11 */;
2605 __le32 reg10 /* reg10 */;
2606 __le32 reg11 /* reg11 */;
2607 __le32 reg12 /* reg12 */;
2608 __le32 reg13 /* reg13 */;
2609 __le32 reg14 /* reg14 */;
2610 __le32 reg15 /* reg15 */;
2611 __le32 reg16 /* reg16 */;
2612 __le32 reg17 /* reg17 */;
2613 __le32 reg18 /* reg18 */;
2614 __le32 reg19 /* reg19 */;
2615 __le16 word12 /* word12 */;
2616 __le16 word13 /* word13 */;
2617 __le16 word14 /* word14 */;
2618 __le16 word15 /* word15 */;
2621 /* The eth storm context for the Ystorm */
2622 struct ystorm_eth_conn_st_ctx {
2626 struct ystorm_eth_conn_ag_ctx {
2627 u8 byte0 /* cdu_validation */;
2628 u8 byte1 /* state */;
2630 #define YSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */
2631 #define YSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0
2632 #define YSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
2633 #define YSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
2634 #define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3 /* cf0 */
2635 #define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 2
2636 #define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_MASK 0x3 /* cf1 */
2637 #define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_SHIFT 4
2638 #define YSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */
2639 #define YSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6
2641 #define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1 /* cf0en */
2642 #define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 0
2643 #define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_MASK 0x1 /* cf1en */
2644 #define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_SHIFT 1
2645 #define YSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
2646 #define YSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2
2647 #define YSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
2648 #define YSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 3
2649 #define YSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
2650 #define YSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 4
2651 #define YSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
2652 #define YSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 5
2653 #define YSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
2654 #define YSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 6
2655 #define YSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
2656 #define YSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 7
2657 u8 byte2 /* byte2 */;
2658 u8 byte3 /* byte3 */;
2659 __le16 word0 /* word0 */;
2660 __le32 terminate_spqe /* reg0 */;
2661 __le32 reg1 /* reg1 */;
2662 __le16 tx_bd_cons_upd /* word1 */;
2663 __le16 word2 /* word2 */;
2664 __le16 word3 /* word3 */;
2665 __le16 word4 /* word4 */;
2666 __le32 reg2 /* reg2 */;
2667 __le32 reg3 /* reg3 */;
2670 struct tstorm_eth_conn_ag_ctx {
2671 u8 byte0 /* cdu_validation */;
2672 u8 byte1 /* state */;
2674 #define TSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */
2675 #define TSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0
2676 #define TSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
2677 #define TSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
2678 #define TSTORM_ETH_CONN_AG_CTX_BIT2_MASK 0x1 /* bit2 */
2679 #define TSTORM_ETH_CONN_AG_CTX_BIT2_SHIFT 2
2680 #define TSTORM_ETH_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */
2681 #define TSTORM_ETH_CONN_AG_CTX_BIT3_SHIFT 3
2682 #define TSTORM_ETH_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */
2683 #define TSTORM_ETH_CONN_AG_CTX_BIT4_SHIFT 4
2684 #define TSTORM_ETH_CONN_AG_CTX_BIT5_MASK 0x1 /* bit5 */
2685 #define TSTORM_ETH_CONN_AG_CTX_BIT5_SHIFT 5
2686 #define TSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */
2687 #define TSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 6
2689 #define TSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */
2690 #define TSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 0
2691 #define TSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */
2692 #define TSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 2
2693 #define TSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */
2694 #define TSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 4
2695 #define TSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */
2696 #define TSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 6
2698 #define TSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */
2699 #define TSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 0
2700 #define TSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */
2701 #define TSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 2
2702 #define TSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */
2703 #define TSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 4
2704 #define TSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */
2705 #define TSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 6
2707 #define TSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */
2708 #define TSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 0
2709 #define TSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */
2710 #define TSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 2
2711 #define TSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
2712 #define TSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 4
2713 #define TSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
2714 #define TSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 5
2715 #define TSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
2716 #define TSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 6
2717 #define TSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */
2718 #define TSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 7
2720 #define TSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */
2721 #define TSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 0
2722 #define TSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */
2723 #define TSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 1
2724 #define TSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */
2725 #define TSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 2
2726 #define TSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */
2727 #define TSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 3
2728 #define TSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */
2729 #define TSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 4
2730 #define TSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */
2731 #define TSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 5
2732 #define TSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */
2733 #define TSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 6
2734 #define TSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
2735 #define TSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7
2737 #define TSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
2738 #define TSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0
2739 #define TSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
2740 #define TSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1
2741 #define TSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
2742 #define TSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2
2743 #define TSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
2744 #define TSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3
2745 #define TSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
2746 #define TSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4
2747 #define TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_MASK 0x1 /* rule6en */
2748 #define TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_SHIFT 5
2749 #define TSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */
2750 #define TSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6
2751 #define TSTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */
2752 #define TSTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7
2753 __le32 reg0 /* reg0 */;
2754 __le32 reg1 /* reg1 */;
2755 __le32 reg2 /* reg2 */;
2756 __le32 reg3 /* reg3 */;
2757 __le32 reg4 /* reg4 */;
2758 __le32 reg5 /* reg5 */;
2759 __le32 reg6 /* reg6 */;
2760 __le32 reg7 /* reg7 */;
2761 __le32 reg8 /* reg8 */;
2762 u8 byte2 /* byte2 */;
2763 u8 byte3 /* byte3 */;
2764 __le16 rx_bd_cons /* word0 */;
2765 u8 byte4 /* byte4 */;
2766 u8 byte5 /* byte5 */;
2767 __le16 rx_bd_prod /* word1 */;
2768 __le16 word2 /* conn_dpi */;
2769 __le16 word3 /* word3 */;
2770 __le32 reg9 /* reg9 */;
2771 __le32 reg10 /* reg10 */;
2774 struct ustorm_eth_conn_ag_ctx {
2775 u8 byte0 /* cdu_validation */;
2776 u8 byte1 /* state */;
2778 #define USTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */
2779 #define USTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0
2780 #define USTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
2781 #define USTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
2782 #define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_MASK 0x3 /* timer0cf */
2783 #define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_SHIFT 2
2784 #define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_MASK 0x3 /* timer1cf */
2785 #define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_SHIFT 4
2786 #define USTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */
2787 #define USTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6
2789 #define USTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */
2790 #define USTORM_ETH_CONN_AG_CTX_CF3_SHIFT 0
2791 #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_MASK 0x3 /* cf4 */
2792 #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_SHIFT 2
2793 #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_MASK 0x3 /* cf5 */
2794 #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_SHIFT 4
2795 #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3 /* cf6 */
2796 #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 6
2798 #define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_MASK 0x1 /* cf0en */
2799 #define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_SHIFT 0
2800 #define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_MASK 0x1 /* cf1en */
2801 #define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_SHIFT 1
2802 #define USTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
2803 #define USTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2
2804 #define USTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */
2805 #define USTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 3
2806 #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_MASK 0x1 /* cf4en */
2807 #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_SHIFT 4
2808 #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_MASK 0x1 /* cf5en */
2809 #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_SHIFT 5
2810 #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1 /* cf6en */
2811 #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 6
2812 #define USTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
2813 #define USTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7
2815 #define USTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
2816 #define USTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0
2817 #define USTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
2818 #define USTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1
2819 #define USTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
2820 #define USTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2
2821 #define USTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
2822 #define USTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3
2823 #define USTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
2824 #define USTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4
2825 #define USTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */
2826 #define USTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 5
2827 #define USTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */
2828 #define USTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6
2829 #define USTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */
2830 #define USTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7
2831 u8 byte2 /* byte2 */;
2832 u8 byte3 /* byte3 */;
2833 __le16 word0 /* conn_dpi */;
2834 __le16 tx_bd_cons /* word1 */;
2835 __le32 reg0 /* reg0 */;
2836 __le32 reg1 /* reg1 */;
2837 __le32 reg2 /* reg2 */;
2838 __le32 tx_int_coallecing_timeset /* reg3 */;
2839 __le16 tx_drv_bd_cons /* word2 */;
2840 __le16 rx_drv_cqe_cons /* word3 */;
2843 /* The eth storm context for the Ustorm */
2844 struct ustorm_eth_conn_st_ctx {
2845 __le32 reserved[40];
2848 /* The eth storm context for the Mstorm */
2849 struct mstorm_eth_conn_st_ctx {
2853 /* eth connection context */
2854 struct eth_conn_context {
2855 struct tstorm_eth_conn_st_ctx tstorm_st_context;
2856 struct regpair tstorm_st_padding[2];
2857 struct pstorm_eth_conn_st_ctx pstorm_st_context;
2858 struct xstorm_eth_conn_st_ctx xstorm_st_context;
2859 struct xstorm_eth_conn_ag_ctx xstorm_ag_context;
2860 struct ystorm_eth_conn_st_ctx ystorm_st_context;
2861 struct ystorm_eth_conn_ag_ctx ystorm_ag_context;
2862 struct tstorm_eth_conn_ag_ctx tstorm_ag_context;
2863 struct ustorm_eth_conn_ag_ctx ustorm_ag_context;
2864 struct ustorm_eth_conn_st_ctx ustorm_st_context;
2865 struct mstorm_eth_conn_st_ctx mstorm_st_context;
2868 enum eth_filter_action {
2869 ETH_FILTER_ACTION_REMOVE,
2870 ETH_FILTER_ACTION_ADD,
2871 ETH_FILTER_ACTION_REMOVE_ALL,
2872 MAX_ETH_FILTER_ACTION
2875 struct eth_filter_cmd {
2876 u8 type /* Filter Type (MAC/VLAN/Pair/VNI) */;
2877 u8 vport_id /* the vport id */;
2878 u8 action /* filter command action: add/remove/replace */;
2887 struct eth_filter_cmd_header {
2895 enum eth_filter_type {
2896 ETH_FILTER_TYPE_MAC,
2897 ETH_FILTER_TYPE_VLAN,
2898 ETH_FILTER_TYPE_PAIR,
2899 ETH_FILTER_TYPE_INNER_MAC,
2900 ETH_FILTER_TYPE_INNER_VLAN,
2901 ETH_FILTER_TYPE_INNER_PAIR,
2902 ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR,
2903 ETH_FILTER_TYPE_MAC_VNI_PAIR,
2904 ETH_FILTER_TYPE_VNI,
2908 enum eth_ramrod_cmd_id {
2910 ETH_RAMROD_VPORT_START /* VPort Start Ramrod */,
2911 ETH_RAMROD_VPORT_UPDATE /* VPort Update Ramrod */,
2912 ETH_RAMROD_VPORT_STOP /* VPort Stop Ramrod */,
2913 ETH_RAMROD_RX_QUEUE_START /* RX Queue Start Ramrod */,
2914 ETH_RAMROD_RX_QUEUE_STOP /* RX Queue Stop Ramrod */,
2915 ETH_RAMROD_TX_QUEUE_START /* TX Queue Start Ramrod */,
2916 ETH_RAMROD_TX_QUEUE_STOP /* TX Queue Stop Ramrod */,
2917 ETH_RAMROD_FILTERS_UPDATE /* Add or Remove Mac/Vlan/Pair filters */,
2918 ETH_RAMROD_RX_QUEUE_UPDATE /* RX Queue Update Ramrod */,
2919 ETH_RAMROD_RESERVED,
2920 ETH_RAMROD_RESERVED2,
2921 ETH_RAMROD_RESERVED3,
2922 ETH_RAMROD_RESERVED4,
2923 ETH_RAMROD_RESERVED5,
2924 ETH_RAMROD_RESERVED6,
2925 ETH_RAMROD_RESERVED7,
2926 ETH_RAMROD_RESERVED8,
2927 MAX_ETH_RAMROD_CMD_ID
2931 ETH_TX_ERR_DROP /* Drop erronous packet. */,
2932 ETH_TX_ERR_ASSERT_MALICIOUS,
2936 struct eth_tx_err_vals {
2938 #define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_MASK 0x1
2939 #define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_SHIFT 0
2940 #define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_MASK 0x1
2941 #define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_SHIFT 1
2942 #define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_MASK 0x1
2943 #define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_SHIFT 2
2944 #define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_MASK 0x1
2945 #define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_SHIFT 3
2946 #define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_MASK 0x1
2947 #define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_SHIFT 4
2948 #define ETH_TX_ERR_VALS_MTU_VIOLATION_MASK 0x1
2949 #define ETH_TX_ERR_VALS_MTU_VIOLATION_SHIFT 5
2950 #define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_MASK 0x1
2951 #define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_SHIFT 6
2952 #define ETH_TX_ERR_VALS_RESERVED_MASK 0x1FF
2953 #define ETH_TX_ERR_VALS_RESERVED_SHIFT 7
2956 struct eth_vport_rss_config {
2957 __le16 capabilities;
2958 #define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_MASK 0x1
2959 #define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_SHIFT 0
2960 #define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_MASK 0x1
2961 #define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_SHIFT 1
2962 #define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_MASK 0x1
2963 #define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_SHIFT 2
2964 #define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_MASK 0x1
2965 #define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_SHIFT 3
2966 #define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_MASK 0x1
2967 #define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_SHIFT 4
2968 #define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_MASK 0x1
2969 #define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_SHIFT 5
2970 #define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_MASK 0x1
2971 #define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_SHIFT 6
2972 #define ETH_VPORT_RSS_CONFIG_RESERVED0_MASK 0x1FF
2973 #define ETH_VPORT_RSS_CONFIG_RESERVED0_SHIFT 7
2977 u8 update_rss_ind_table;
2978 u8 update_rss_capabilities;
2980 __le32 reserved2[2];
2981 __le16 indirection_table[ETH_RSS_IND_TABLE_ENTRIES_NUM];
2982 __le32 rss_key[ETH_RSS_KEY_SIZE_REGS];
2983 __le32 reserved3[2];
2986 enum eth_vport_rss_mode {
2987 ETH_VPORT_RSS_MODE_DISABLED,
2988 ETH_VPORT_RSS_MODE_REGULAR,
2989 MAX_ETH_VPORT_RSS_MODE
2992 struct eth_vport_rx_mode {
2994 #define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_MASK 0x1
2995 #define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_SHIFT 0
2996 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_MASK 0x1
2997 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_SHIFT 1
2998 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_MASK 0x1
2999 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_SHIFT 2
3000 #define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_MASK 0x1
3001 #define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_SHIFT 3
3002 #define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_MASK 0x1
3003 #define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_SHIFT 4
3004 #define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_MASK 0x1
3005 #define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_SHIFT 5
3006 #define ETH_VPORT_RX_MODE_RESERVED1_MASK 0x3FF
3007 #define ETH_VPORT_RX_MODE_RESERVED1_SHIFT 6
3008 __le16 reserved2[3];
3011 struct eth_vport_tpa_param {
3014 u8 tpa_ipv4_tunn_en_flg;
3015 u8 tpa_ipv6_tunn_en_flg;
3016 u8 tpa_pkt_split_flg;
3017 u8 tpa_hdr_data_split_flg;
3018 u8 tpa_gro_consistent_flg;
3019 u8 tpa_max_aggs_num;
3021 u16 tpa_min_size_to_start;
3022 u16 tpa_min_size_to_cont;
3027 struct eth_vport_tx_mode {
3029 #define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_MASK 0x1
3030 #define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_SHIFT 0
3031 #define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_MASK 0x1
3032 #define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_SHIFT 1
3033 #define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_MASK 0x1
3034 #define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_SHIFT 2
3035 #define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_MASK 0x1
3036 #define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_SHIFT 3
3037 #define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_MASK 0x1
3038 #define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_SHIFT 4
3039 #define ETH_VPORT_TX_MODE_RESERVED1_MASK 0x7FF
3040 #define ETH_VPORT_TX_MODE_RESERVED1_SHIFT 5
3041 __le16 reserved2[3];
3044 struct rx_queue_start_ramrod_data {
3046 __le16 num_of_pbl_pages;
3047 __le16 bd_max_bytes;
3051 u8 default_rss_queue_flg;
3052 u8 complete_cqe_flg;
3053 u8 complete_event_flg;
3054 u8 stats_counter_id;
3056 u8 pxp_tph_valid_bd;
3057 u8 pxp_tph_valid_pkt;
3059 __le16 pxp_st_index;
3065 struct regpair cqe_pbl_addr;
3066 struct regpair bd_base;
3067 struct regpair reserved2;
3070 struct rx_queue_stop_ramrod_data {
3072 u8 complete_cqe_flg;
3073 u8 complete_event_flg;
3078 struct rx_queue_update_ramrod_data {
3080 u8 complete_cqe_flg;
3081 u8 complete_event_flg;
3089 struct regpair reserved6;
3092 struct tx_queue_start_ramrod_data {
3097 u8 stats_counter_id;
3100 #define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_MASK 0x1
3101 #define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_SHIFT 0
3102 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_MASK 0x1
3103 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_SHIFT 1
3104 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_TX_DEST_MASK 0x1
3105 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_TX_DEST_SHIFT 2
3106 #define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_MASK 0x1
3107 #define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_SHIFT 3
3108 #define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_MASK 0x1
3109 #define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_SHIFT 4
3110 #define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_MASK 0x1
3111 #define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_SHIFT 5
3112 #define TX_QUEUE_START_RAMROD_DATA_RESERVED1_MASK 0x3
3113 #define TX_QUEUE_START_RAMROD_DATA_RESERVED1_SHIFT 6
3115 u8 pxp_tph_valid_bd;
3116 u8 pxp_tph_valid_pkt;
3117 __le16 pxp_st_index;
3118 __le16 comp_agg_size;
3119 __le16 queue_zone_id;
3120 __le16 test_dup_count;
3123 struct regpair pbl_base_addr;
3124 struct regpair bd_cons_address;
3127 struct tx_queue_stop_ramrod_data {
3131 struct vport_filter_update_ramrod_data {
3132 struct eth_filter_cmd_header filter_cmd_hdr;
3133 struct eth_filter_cmd filter_cmds[ETH_FILTER_RULES_COUNT];
3136 struct vport_start_ramrod_data {
3141 u8 inner_vlan_removal_en;
3142 struct eth_vport_rx_mode rx_mode;
3143 struct eth_vport_tx_mode tx_mode;
3144 struct eth_vport_tpa_param tpa_param;
3145 __le16 default_vlan;
3147 u8 anti_spoofing_en;
3150 u8 silent_vlan_removal_en;
3152 struct eth_tx_err_vals tx_err_behav;
3153 u8 zero_placement_offset;
3157 struct vport_stop_ramrod_data {
3162 struct vport_update_ramrod_data_cmn {
3164 u8 update_rx_active_flg;
3166 u8 update_tx_active_flg;
3168 u8 update_rx_mode_flg;
3169 u8 update_tx_mode_flg;
3170 u8 update_approx_mcast_flg;
3172 u8 update_inner_vlan_removal_en_flg;
3173 u8 inner_vlan_removal_en;
3174 u8 update_tpa_param_flg;
3175 u8 update_tpa_en_flg;
3176 u8 update_tx_switching_en_flg;
3178 u8 update_anti_spoofing_en_flg;
3179 u8 anti_spoofing_en;
3180 u8 update_handle_ptp_pkts;
3182 u8 update_default_vlan_en_flg;
3184 u8 update_default_vlan_flg;
3185 __le16 default_vlan;
3186 u8 update_accept_any_vlan_flg;
3188 u8 silent_vlan_removal_en;
3194 struct vport_update_ramrod_mcast {
3195 __le32 bins[ETH_MULTICAST_MAC_BINS_IN_REGS];
3198 struct vport_update_ramrod_data {
3199 struct vport_update_ramrod_data_cmn common;
3200 struct eth_vport_rx_mode rx_mode;
3201 struct eth_vport_tx_mode tx_mode;
3202 struct eth_vport_tpa_param tpa_param;
3203 struct vport_update_ramrod_mcast approx_mcast;
3204 struct eth_vport_rss_config rss_config;
3207 #define VF_MAX_STATIC 192 /* In case of K2 */
3209 #define MCP_GLOB_PATH_MAX 2
3210 #define MCP_PORT_MAX 2 /* Global */
3211 #define MCP_GLOB_PORT_MAX 4 /* Global */
3212 #define MCP_GLOB_FUNC_MAX 16 /* Global */
3214 typedef u32 offsize_t; /* In DWORDS !!! */
3215 /* Offset from the beginning of the MCP scratchpad */
3216 #define OFFSIZE_OFFSET_SHIFT 0
3217 #define OFFSIZE_OFFSET_MASK 0x0000ffff
3218 /* Size of specific element (not the whole array if any) */
3219 #define OFFSIZE_SIZE_SHIFT 16
3220 #define OFFSIZE_SIZE_MASK 0xffff0000
3222 /* SECTION_OFFSET is calculating the offset in bytes out of offsize */
3223 #define SECTION_OFFSET(_offsize) ((((_offsize & \
3224 OFFSIZE_OFFSET_MASK) >> \
3225 OFFSIZE_OFFSET_SHIFT) << 2))
3227 /* QED_SECTION_SIZE is calculating the size in bytes out of offsize */
3228 #define QED_SECTION_SIZE(_offsize) (((_offsize & \
3229 OFFSIZE_SIZE_MASK) >> \
3230 OFFSIZE_SIZE_SHIFT) << 2)
3232 /* SECTION_ADDR returns the GRC addr of a section, given offsize and index
3235 #define SECTION_ADDR(_offsize, idx) (MCP_REG_SCRATCH + \
3236 SECTION_OFFSET(_offsize) + \
3237 (QED_SECTION_SIZE(_offsize) * idx))
3239 /* SECTION_OFFSIZE_ADDR returns the GRC addr to the offsize address.
3240 * Use offsetof, since the OFFSETUP collide with the firmware definition
3242 #define SECTION_OFFSIZE_ADDR(_pub_base, _section) (_pub_base + \
3245 sections[_section]))
3246 /* PHY configuration */
3247 struct pmm_phy_cfg {
3249 #define PMM_SPEED_AUTONEG 0
3251 u32 pause; /* bitmask */
3252 #define PMM_PAUSE_NONE 0x0
3253 #define PMM_PAUSE_AUTONEG 0x1
3254 #define PMM_PAUSE_RX 0x2
3255 #define PMM_PAUSE_TX 0x4
3257 u32 adv_speed; /* Default should be the speed_cap_mask */
3259 #define PMM_LOOPBACK_NONE 0
3260 #define PMM_LOOPBACK_INT_PHY 1
3261 #define PMM_LOOPBACK_EXT_PHY 2
3262 #define PMM_LOOPBACK_EXT 3
3263 #define PMM_LOOPBACK_MAC 4
3266 u32 feature_config_flags;
3269 struct port_mf_cfg {
3270 u32 dynamic_cfg; /* device control channel */
3271 #define PORT_MF_CFG_OV_TAG_MASK 0x0000ffff
3272 #define PORT_MF_CFG_OV_TAG_SHIFT 0
3273 #define PORT_MF_CFG_OV_TAG_DEFAULT PORT_MF_CFG_OV_TAG_MASK
3278 /* DO NOT add new fields in the middle
3279 * MUST be synced with struct pmm_stats_map
3282 u64 r64; /* 0x00 (Offset 0x00 ) RX 64-byte frame counter*/
3283 u64 r127; /* 0x01 (Offset 0x08 ) RX 65 to 127 byte frame counter*/
3293 u64 rfcs; /* 0x0F (Offset 0x58 ) RX FCS error frame counter*/
3294 u64 rxcf; /* 0x10 (Offset 0x60 ) RX control frame counter*/
3295 u64 rxpf; /* 0x11 (Offset 0x68 ) RX pause frame counter*/
3296 u64 rxpp; /* 0x12 (Offset 0x70 ) RX PFC frame counter*/
3297 u64 raln; /* 0x16 (Offset 0x78 ) RX alignment error counter*/
3298 u64 rfcr; /* 0x19 (Offset 0x80 ) RX false carrier counter */
3299 u64 rovr; /* 0x1A (Offset 0x88 ) RX oversized frame counter*/
3300 u64 rjbr; /* 0x1B (Offset 0x90 ) RX jabber frame counter */
3301 u64 rund; /* 0x34 (Offset 0x98 ) RX undersized frame counter */
3302 u64 rfrg; /* 0x35 (Offset 0xa0 ) RX fragment counter */
3303 u64 t64; /* 0x40 (Offset 0xa8 ) TX 64-byte frame counter */
3313 u64 txpf; /* 0x50 (Offset 0xf8 ) TX pause frame counter */
3314 u64 txpp; /* 0x51 (Offset 0x100) TX PFC frame counter */
3317 u64 rbyte; /* 0x3d (Offset 0x118) RX byte counter */
3318 u64 rxuca; /* 0x0c (Offset 0x120) RX UC frame counter */
3319 u64 rxmca; /* 0x0d (Offset 0x128) RX MC frame counter */
3320 u64 rxbca; /* 0x0e (Offset 0x130) RX BC frame counter */
3322 u64 tbyte; /* 0x6f (Offset 0x140) TX byte counter */
3323 u64 txuca; /* 0x4d (Offset 0x148) TX UC frame counter */
3324 u64 txmca; /* 0x4e (Offset 0x150) TX MC frame counter */
3325 u64 txbca; /* 0x4f (Offset 0x158) TX BC frame counter */
3326 u64 txcf; /* 0x54 (Offset 0x160) TX control frame counter */
3330 u64 brb_truncate[8];
3335 struct brb_stats brb;
3336 struct pmm_stats pmm;
3341 #define CMT_TEAM_MAX 2
3343 struct couple_mode_teaming {
3344 u8 port_cmt[MCP_GLOB_PORT_MAX];
3345 #define PORT_CMT_IN_TEAM BIT(0)
3347 #define PORT_CMT_PORT_ROLE BIT(1)
3348 #define PORT_CMT_PORT_INACTIVE (0 << 1)
3349 #define PORT_CMT_PORT_ACTIVE BIT(1)
3351 #define PORT_CMT_TEAM_MASK BIT(2)
3352 #define PORT_CMT_TEAM0 (0 << 2)
3353 #define PORT_CMT_TEAM1 BIT(2)
3356 /**************************************
3357 * LLDP and DCBX HSI structures
3358 **************************************/
3359 #define LLDP_CHASSIS_ID_STAT_LEN 4
3360 #define LLDP_PORT_ID_STAT_LEN 4
3361 #define DCBX_MAX_APP_PROTOCOL 32
3362 #define MAX_SYSTEM_LLDP_TLV_DATA 32
3365 LLDP_NEAREST_BRIDGE = 0,
3366 LLDP_NEAREST_NON_TPMR_BRIDGE,
3367 LLDP_NEAREST_CUSTOMER_BRIDGE,
3368 LLDP_MAX_LLDP_AGENTS
3371 struct lldp_config_params_s {
3373 #define LLDP_CONFIG_TX_INTERVAL_MASK 0x000000ff
3374 #define LLDP_CONFIG_TX_INTERVAL_SHIFT 0
3375 #define LLDP_CONFIG_HOLD_MASK 0x00000f00
3376 #define LLDP_CONFIG_HOLD_SHIFT 8
3377 #define LLDP_CONFIG_MAX_CREDIT_MASK 0x0000f000
3378 #define LLDP_CONFIG_MAX_CREDIT_SHIFT 12
3379 #define LLDP_CONFIG_ENABLE_RX_MASK 0x40000000
3380 #define LLDP_CONFIG_ENABLE_RX_SHIFT 30
3381 #define LLDP_CONFIG_ENABLE_TX_MASK 0x80000000
3382 #define LLDP_CONFIG_ENABLE_TX_SHIFT 31
3383 u32 local_chassis_id[LLDP_CHASSIS_ID_STAT_LEN];
3384 u32 local_port_id[LLDP_PORT_ID_STAT_LEN];
3387 struct lldp_status_params_s {
3389 u32 status; /* TBD */
3391 /* Holds remote Chassis ID TLV header, subtype and 9B of payload. */
3392 u32 peer_chassis_id[LLDP_CHASSIS_ID_STAT_LEN];
3394 /* Holds remote Port ID TLV header, subtype and 9B of payload. */
3395 u32 peer_port_id[LLDP_PORT_ID_STAT_LEN];
3399 struct dcbx_ets_feature {
3401 #define DCBX_ETS_ENABLED_MASK 0x00000001
3402 #define DCBX_ETS_ENABLED_SHIFT 0
3403 #define DCBX_ETS_WILLING_MASK 0x00000002
3404 #define DCBX_ETS_WILLING_SHIFT 1
3405 #define DCBX_ETS_ERROR_MASK 0x00000004
3406 #define DCBX_ETS_ERROR_SHIFT 2
3407 #define DCBX_ETS_CBS_MASK 0x00000008
3408 #define DCBX_ETS_CBS_SHIFT 3
3409 #define DCBX_ETS_MAX_TCS_MASK 0x000000f0
3410 #define DCBX_ETS_MAX_TCS_SHIFT 4
3412 #define DCBX_ISCSI_OOO_TC 4
3413 #define NIG_ETS_ISCSI_OOO_CLIENT_OFFSET (DCBX_ISCSI_OOO_TC + 1)
3416 #define DCBX_ETS_TSA_STRICT 0
3417 #define DCBX_ETS_TSA_CBS 1
3418 #define DCBX_ETS_TSA_ETS 2
3421 struct dcbx_app_priority_entry {
3423 #define DCBX_APP_PRI_MAP_MASK 0x000000ff
3424 #define DCBX_APP_PRI_MAP_SHIFT 0
3425 #define DCBX_APP_PRI_0 0x01
3426 #define DCBX_APP_PRI_1 0x02
3427 #define DCBX_APP_PRI_2 0x04
3428 #define DCBX_APP_PRI_3 0x08
3429 #define DCBX_APP_PRI_4 0x10
3430 #define DCBX_APP_PRI_5 0x20
3431 #define DCBX_APP_PRI_6 0x40
3432 #define DCBX_APP_PRI_7 0x80
3433 #define DCBX_APP_SF_MASK 0x00000300
3434 #define DCBX_APP_SF_SHIFT 8
3435 #define DCBX_APP_SF_ETHTYPE 0
3436 #define DCBX_APP_SF_PORT 1
3437 #define DCBX_APP_PROTOCOL_ID_MASK 0xffff0000
3438 #define DCBX_APP_PROTOCOL_ID_SHIFT 16
3441 /* FW structure in BE */
3442 struct dcbx_app_priority_feature {
3444 #define DCBX_APP_ENABLED_MASK 0x00000001
3445 #define DCBX_APP_ENABLED_SHIFT 0
3446 #define DCBX_APP_WILLING_MASK 0x00000002
3447 #define DCBX_APP_WILLING_SHIFT 1
3448 #define DCBX_APP_ERROR_MASK 0x00000004
3449 #define DCBX_APP_ERROR_SHIFT 2
3451 * #define DCBX_APP_DEFAULT_PRI_MASK 0x00000f00
3452 * #define DCBX_APP_DEFAULT_PRI_SHIFT 8
3454 #define DCBX_APP_MAX_TCS_MASK 0x0000f000
3455 #define DCBX_APP_MAX_TCS_SHIFT 12
3456 #define DCBX_APP_NUM_ENTRIES_MASK 0x00ff0000
3457 #define DCBX_APP_NUM_ENTRIES_SHIFT 16
3458 struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL];
3461 /* FW structure in BE */
3462 struct dcbx_features {
3464 struct dcbx_ets_feature ets;
3468 #define DCBX_PFC_PRI_EN_BITMAP_MASK 0x000000ff
3469 #define DCBX_PFC_PRI_EN_BITMAP_SHIFT 0
3470 #define DCBX_PFC_PRI_EN_BITMAP_PRI_0 0x01
3471 #define DCBX_PFC_PRI_EN_BITMAP_PRI_1 0x02
3472 #define DCBX_PFC_PRI_EN_BITMAP_PRI_2 0x04
3473 #define DCBX_PFC_PRI_EN_BITMAP_PRI_3 0x08
3474 #define DCBX_PFC_PRI_EN_BITMAP_PRI_4 0x10
3475 #define DCBX_PFC_PRI_EN_BITMAP_PRI_5 0x20
3476 #define DCBX_PFC_PRI_EN_BITMAP_PRI_6 0x40
3477 #define DCBX_PFC_PRI_EN_BITMAP_PRI_7 0x80
3479 #define DCBX_PFC_FLAGS_MASK 0x0000ff00
3480 #define DCBX_PFC_FLAGS_SHIFT 8
3481 #define DCBX_PFC_CAPS_MASK 0x00000f00
3482 #define DCBX_PFC_CAPS_SHIFT 8
3483 #define DCBX_PFC_MBC_MASK 0x00004000
3484 #define DCBX_PFC_MBC_SHIFT 14
3485 #define DCBX_PFC_WILLING_MASK 0x00008000
3486 #define DCBX_PFC_WILLING_SHIFT 15
3487 #define DCBX_PFC_ENABLED_MASK 0x00010000
3488 #define DCBX_PFC_ENABLED_SHIFT 16
3489 #define DCBX_PFC_ERROR_MASK 0x00020000
3490 #define DCBX_PFC_ERROR_SHIFT 17
3493 struct dcbx_app_priority_feature app;
3496 struct dcbx_local_params {
3498 #define DCBX_CONFIG_VERSION_MASK 0x00000003
3499 #define DCBX_CONFIG_VERSION_SHIFT 0
3500 #define DCBX_CONFIG_VERSION_DISABLED 0
3501 #define DCBX_CONFIG_VERSION_IEEE 1
3502 #define DCBX_CONFIG_VERSION_CEE 2
3505 struct dcbx_features features;
3511 struct dcbx_features features;
3515 struct lldp_system_tlvs_buffer_s {
3518 u32 data[MAX_SYSTEM_LLDP_TLV_DATA];
3521 /**************************************/
3523 /* P U B L I C G L O B A L */
3525 /**************************************/
3526 struct public_global {
3528 #define MAX_PATH_BIG_BEAR 2
3529 #define MAX_PATH_K2 1
3535 u32 debug_mb_offset;
3536 u32 phymod_dbg_mb_offset;
3537 struct couple_mode_teaming cmt;
3538 s32 internal_temperature;
3540 u32 running_bundle_id;
3543 /**************************************/
3545 /* P U B L I C P A T H */
3547 /**************************************/
3549 /****************************************************************************
3550 * Shared Memory 2 Region *
3551 ****************************************************************************/
3552 /* The fw_flr_ack is actually built in the following way: */
3554 /* 128 bit: VF ack */
3555 /* 8 bit: ios_dis_ack */
3556 /* In order to maintain endianity in the mailbox hsi, we want to keep using */
3557 /* u32. The fw must have the VF right after the PF since this is how it */
3558 /* access arrays(it expects always the VF to reside after the PF, and that */
3559 /* makes the calculation much easier for it. ) */
3560 /* In order to answer both limitations, and keep the struct small, the code */
3561 /* will abuse the structure defined here to achieve the actual partition */
3563 /****************************************************************************/
3567 u32 accum_ack; /* 0..15:PF, 16..207:VF, 256..271:IOV_DIS */
3568 #define ACCUM_ACK_PF_BASE 0
3569 #define ACCUM_ACK_PF_SHIFT 0
3571 #define ACCUM_ACK_VF_BASE 8
3572 #define ACCUM_ACK_VF_SHIFT 3
3574 #define ACCUM_ACK_IOV_DIS_BASE 256
3575 #define ACCUM_ACK_IOV_DIS_SHIFT 8
3578 struct public_path {
3579 struct fw_flr_mb flr_mb;
3580 u32 mcp_vf_disabled[VF_MAX_STATIC / 32];
3583 #define PROCESS_KILL_COUNTER_MASK 0x0000ffff
3584 #define PROCESS_KILL_COUNTER_SHIFT 0
3585 #define PROCESS_KILL_GLOB_AEU_BIT_MASK 0xffff0000
3586 #define PROCESS_KILL_GLOB_AEU_BIT_SHIFT 16
3587 #define GLOBAL_AEU_BIT(aeu_reg_id, aeu_bit) (aeu_reg_id * 32 + aeu_bit)
3590 /**************************************/
3592 /* P U B L I C P O R T */
3594 /**************************************/
3596 /****************************************************************************
3597 * Driver <-> FW Mailbox *
3598 ****************************************************************************/
3600 struct public_port {
3601 u32 validity_map; /* 0x0 (4*2 = 0x8) */
3604 #define MCP_VALIDITY_PCI_CFG 0x00100000
3605 #define MCP_VALIDITY_MB 0x00200000
3606 #define MCP_VALIDITY_DEV_INFO 0x00400000
3607 #define MCP_VALIDITY_RESERVED 0x00000007
3609 /* One licensing bit should be set */
3610 #define MCP_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038
3611 #define MCP_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008
3612 #define MCP_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010
3613 #define MCP_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020
3616 #define MCP_VALIDITY_ACTIVE_MFW_UNKNOWN 0x00000000
3617 #define MCP_VALIDITY_ACTIVE_MFW_MASK 0x000001c0
3618 #define MCP_VALIDITY_ACTIVE_MFW_NCSI 0x00000040
3619 #define MCP_VALIDITY_ACTIVE_MFW_NONE 0x000001c0
3622 #define LINK_STATUS_LINK_UP \
3624 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001e
3625 #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD BIT(1)
3626 #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (2 << 1)
3627 #define LINK_STATUS_SPEED_AND_DUPLEX_10G (3 << 1)
3628 #define LINK_STATUS_SPEED_AND_DUPLEX_20G (4 << 1)
3629 #define LINK_STATUS_SPEED_AND_DUPLEX_40G (5 << 1)
3630 #define LINK_STATUS_SPEED_AND_DUPLEX_50G (6 << 1)
3631 #define LINK_STATUS_SPEED_AND_DUPLEX_100G (7 << 1)
3632 #define LINK_STATUS_SPEED_AND_DUPLEX_25G (8 << 1)
3634 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020
3636 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040
3637 #define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080
3639 #define LINK_STATUS_PFC_ENABLED \
3641 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200
3642 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400
3643 #define LINK_STATUS_LINK_PARTNER_10G_CAPABLE 0x00000800
3644 #define LINK_STATUS_LINK_PARTNER_20G_CAPABLE 0x00001000
3645 #define LINK_STATUS_LINK_PARTNER_40G_CAPABLE 0x00002000
3646 #define LINK_STATUS_LINK_PARTNER_50G_CAPABLE 0x00004000
3647 #define LINK_STATUS_LINK_PARTNER_100G_CAPABLE 0x00008000
3648 #define LINK_STATUS_LINK_PARTNER_25G_CAPABLE 0x00010000
3650 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000
3651 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0 << 18)
3652 #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE BIT(18)
3653 #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2 << 18)
3654 #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3 << 18)
3656 #define LINK_STATUS_SFP_TX_FAULT \
3658 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00200000
3659 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00400000
3662 u32 ext_phy_fw_version;
3663 u32 drv_phy_cfg_addr;
3669 struct port_mf_cfg port_mf_config;
3670 struct port_stats stats;
3673 #define MEDIA_UNSPECIFIED 0x0
3674 #define MEDIA_SFPP_10G_FIBER 0x1
3675 #define MEDIA_XFP_FIBER 0x2
3676 #define MEDIA_DA_TWINAX 0x3
3677 #define MEDIA_BASE_T 0x4
3678 #define MEDIA_SFP_1G_FIBER 0x5
3679 #define MEDIA_KR 0xf0
3680 #define MEDIA_NOT_PRESENT 0xff
3683 #define LFA_LINK_FLAP_REASON_OFFSET 0
3684 #define LFA_LINK_FLAP_REASON_MASK 0x000000ff
3685 #define LFA_NO_REASON (0 << 0)
3686 #define LFA_LINK_DOWN BIT(0)
3687 #define LFA_FORCE_INIT BIT(1)
3688 #define LFA_LOOPBACK_MISMATCH BIT(2)
3689 #define LFA_SPEED_MISMATCH BIT(3)
3690 #define LFA_FLOW_CTRL_MISMATCH BIT(4)
3691 #define LFA_ADV_SPEED_MISMATCH BIT(5)
3692 #define LINK_FLAP_AVOIDANCE_COUNT_OFFSET 8
3693 #define LINK_FLAP_AVOIDANCE_COUNT_MASK 0x0000ff00
3694 #define LINK_FLAP_COUNT_OFFSET 16
3695 #define LINK_FLAP_COUNT_MASK 0x00ff0000
3697 u32 link_change_count;
3700 struct lldp_config_params_s lldp_config_params[
3701 LLDP_MAX_LLDP_AGENTS];
3702 struct lldp_status_params_s lldp_status_params[
3703 LLDP_MAX_LLDP_AGENTS];
3704 struct lldp_system_tlvs_buffer_s system_lldp_tlvs_buf;
3706 /* DCBX related MIB */
3707 struct dcbx_local_params local_admin_dcbx_mib;
3708 struct dcbx_mib remote_dcbx_mib;
3709 struct dcbx_mib operational_dcbx_mib;
3711 u32 fc_npiv_nvram_tbl_addr;
3712 u32 fc_npiv_nvram_tbl_size;
3713 u32 transceiver_data;
3714 #define PMM_TRANSCEIVER_STATE_MASK 0x000000FF
3715 #define PMM_TRANSCEIVER_STATE_SHIFT 0x00000000
3716 #define PMM_TRANSCEIVER_STATE_PRESENT 0x00000001
3719 /**************************************/
3721 /* P U B L I C F U N C */
3723 /**************************************/
3725 struct public_func {
3726 u32 iscsi_boot_signature;
3727 u32 iscsi_boot_block_offset;
3730 u32 c2s_pcp_map_lower;
3731 u32 c2s_pcp_map_upper;
3732 u32 c2s_pcp_map_default;
3738 /* function 0 of each port cannot be hidden */
3739 #define FUNC_MF_CFG_FUNC_HIDE 0x00000001
3740 #define FUNC_MF_CFG_PAUSE_ON_HOST_RING 0x00000002
3741 #define FUNC_MF_CFG_PAUSE_ON_HOST_RING_SHIFT 0x00000001
3743 #define FUNC_MF_CFG_PROTOCOL_MASK 0x000000f0
3744 #define FUNC_MF_CFG_PROTOCOL_SHIFT 4
3745 #define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000000
3746 #define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000010
3747 #define FUNC_MF_CFG_PROTOCOL_FCOE 0x00000020
3748 #define FUNC_MF_CFG_PROTOCOL_ROCE 0x00000030
3749 #define FUNC_MF_CFG_PROTOCOL_MAX 0x00000030
3752 /* value range - 0..100, increments in 1 % */
3753 #define FUNC_MF_CFG_MIN_BW_MASK 0x0000ff00
3754 #define FUNC_MF_CFG_MIN_BW_SHIFT 8
3755 #define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000
3756 #define FUNC_MF_CFG_MAX_BW_MASK 0x00ff0000
3757 #define FUNC_MF_CFG_MAX_BW_SHIFT 16
3758 #define FUNC_MF_CFG_MAX_BW_DEFAULT 0x00640000
3761 #define FUNC_STATUS_VLINK_DOWN 0x00000001
3763 u32 mac_upper; /* MAC */
3764 #define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff
3765 #define FUNC_MF_CFG_UPPERMAC_SHIFT 0
3766 #define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK
3768 #define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff
3770 u32 fcoe_wwn_port_name_upper;
3771 u32 fcoe_wwn_port_name_lower;
3773 u32 fcoe_wwn_node_name_upper;
3774 u32 fcoe_wwn_node_name_lower;
3776 u32 ovlan_stag; /* tags */
3777 #define FUNC_MF_CFG_OV_STAG_MASK 0x0000ffff
3778 #define FUNC_MF_CFG_OV_STAG_SHIFT 0
3779 #define FUNC_MF_CFG_OV_STAG_DEFAULT FUNC_MF_CFG_OV_STAG_MASK
3781 u32 pf_allocation; /* vf per pf */
3783 u32 preserve_data; /* Will be used bt CCM */
3785 u32 driver_last_activity_ts;
3787 u32 drv_ack_vf_disabled[VF_MAX_STATIC / 32]; /* 0x0044 */
3790 #define DRV_ID_PDA_COMP_VER_MASK 0x0000ffff
3791 #define DRV_ID_PDA_COMP_VER_SHIFT 0
3793 #define DRV_ID_MCP_HSI_VER_MASK 0x00ff0000
3794 #define DRV_ID_MCP_HSI_VER_SHIFT 16
3795 #define DRV_ID_MCP_HSI_VER_CURRENT BIT(DRV_ID_MCP_HSI_VER_SHIFT)
3797 #define DRV_ID_DRV_TYPE_MASK 0x7f000000
3798 #define DRV_ID_DRV_TYPE_SHIFT 24
3799 #define DRV_ID_DRV_TYPE_UNKNOWN (0 << DRV_ID_DRV_TYPE_SHIFT)
3800 #define DRV_ID_DRV_TYPE_LINUX (1 << DRV_ID_DRV_TYPE_SHIFT)
3801 #define DRV_ID_DRV_TYPE_WINDOWS (2 << DRV_ID_DRV_TYPE_SHIFT)
3802 #define DRV_ID_DRV_TYPE_DIAG (3 << DRV_ID_DRV_TYPE_SHIFT)
3803 #define DRV_ID_DRV_TYPE_PREBOOT (4 << DRV_ID_DRV_TYPE_SHIFT)
3804 #define DRV_ID_DRV_TYPE_SOLARIS (5 << DRV_ID_DRV_TYPE_SHIFT)
3805 #define DRV_ID_DRV_TYPE_VMWARE (6 << DRV_ID_DRV_TYPE_SHIFT)
3806 #define DRV_ID_DRV_TYPE_FREEBSD (7 << DRV_ID_DRV_TYPE_SHIFT)
3807 #define DRV_ID_DRV_TYPE_AIX (8 << DRV_ID_DRV_TYPE_SHIFT)
3809 #define DRV_ID_DRV_INIT_HW_MASK 0x80000000
3810 #define DRV_ID_DRV_INIT_HW_SHIFT 31
3811 #define DRV_ID_DRV_INIT_HW_FLAG BIT(DRV_ID_DRV_INIT_HW_SHIFT)
3814 /**************************************/
3816 /* P U B L I C M B */
3818 /**************************************/
3819 /* This is the only section that the driver can write to, and each */
3820 /* Basically each driver request to set feature parameters,
3821 * will be done using a different command, which will be linked
3822 * to a specific data structure from the union below.
3823 * For huge strucuture, the common blank structure should be used.
3827 u32 mac_upper; /* Upper 16 bits are always zeroes */
3836 struct mcp_file_att {
3841 #define MCP_DRV_VER_STR_SIZE 16
3842 #define MCP_DRV_VER_STR_SIZE_DWORD (MCP_DRV_VER_STR_SIZE / sizeof(u32))
3843 #define MCP_DRV_NVM_BUF_LEN 32
3844 struct drv_version_stc {
3846 u8 name[MCP_DRV_VER_STR_SIZE - 4];
3849 union drv_union_data {
3850 u32 ver_str[MCP_DRV_VER_STR_SIZE_DWORD];
3851 struct mcp_mac wol_mac;
3853 struct pmm_phy_cfg drv_phy_cfg;
3855 struct mcp_val64 val64; /* For PHY / AVS commands */
3857 u8 raw_data[MCP_DRV_NVM_BUF_LEN];
3859 struct mcp_file_att file_att;
3861 u32 ack_vf_disabled[VF_MAX_STATIC / 32];
3863 struct drv_version_stc drv_version;
3866 struct public_drv_mb {
3868 #define DRV_MSG_CODE_MASK 0xffff0000
3869 #define DRV_MSG_CODE_LOAD_REQ 0x10000000
3870 #define DRV_MSG_CODE_LOAD_DONE 0x11000000
3871 #define DRV_MSG_CODE_INIT_HW 0x12000000
3872 #define DRV_MSG_CODE_UNLOAD_REQ 0x20000000
3873 #define DRV_MSG_CODE_UNLOAD_DONE 0x21000000
3874 #define DRV_MSG_CODE_INIT_PHY 0x22000000
3875 /* Params - FORCE - Reinitialize the link regardless of LFA */
3876 /* - DONT_CARE - Don't flap the link if up */
3877 #define DRV_MSG_CODE_LINK_RESET 0x23000000
3879 #define DRV_MSG_CODE_SET_LLDP 0x24000000
3880 #define DRV_MSG_CODE_SET_DCBX 0x25000000
3881 #define DRV_MSG_CODE_BW_UPDATE_ACK 0x32000000
3882 #define DRV_MSG_CODE_NIG_DRAIN 0x30000000
3884 #define DRV_MSG_CODE_INITIATE_FLR 0x02000000
3885 #define DRV_MSG_CODE_VF_DISABLED_DONE 0xc0000000
3886 #define DRV_MSG_CODE_CFG_VF_MSIX 0xc0010000
3887 #define DRV_MSG_CODE_NVM_PUT_FILE_BEGIN 0x00010000
3888 #define DRV_MSG_CODE_NVM_PUT_FILE_DATA 0x00020000
3889 #define DRV_MSG_CODE_NVM_GET_FILE_ATT 0x00030000
3890 #define DRV_MSG_CODE_NVM_READ_NVRAM 0x00050000
3891 #define DRV_MSG_CODE_NVM_WRITE_NVRAM 0x00060000
3892 #define DRV_MSG_CODE_NVM_DEL_FILE 0x00080000
3893 #define DRV_MSG_CODE_MCP_RESET 0x00090000
3894 #define DRV_MSG_CODE_SET_SECURE_MODE 0x000a0000
3895 #define DRV_MSG_CODE_PHY_RAW_READ 0x000b0000
3896 #define DRV_MSG_CODE_PHY_RAW_WRITE 0x000c0000
3897 #define DRV_MSG_CODE_PHY_CORE_READ 0x000d0000
3898 #define DRV_MSG_CODE_PHY_CORE_WRITE 0x000e0000
3899 #define DRV_MSG_CODE_SET_VERSION 0x000f0000
3901 #define DRV_MSG_CODE_BIST_TEST 0x001e0000
3902 #define DRV_MSG_CODE_SET_LED_MODE 0x00200000
3904 #define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff
3908 /* UNLOAD_REQ params */
3909 #define DRV_MB_PARAM_UNLOAD_WOL_UNKNOWN 0x00000000
3910 #define DRV_MB_PARAM_UNLOAD_WOL_MCP 0x00000001
3911 #define DRV_MB_PARAM_UNLOAD_WOL_DISABLED 0x00000002
3912 #define DRV_MB_PARAM_UNLOAD_WOL_ENABLED 0x00000003
3914 /* UNLOAD_DONE_params */
3915 #define DRV_MB_PARAM_UNLOAD_NON_D3_POWER 0x00000001
3917 /* INIT_PHY params */
3918 #define DRV_MB_PARAM_INIT_PHY_FORCE 0x00000001
3919 #define DRV_MB_PARAM_INIT_PHY_DONT_CARE 0x00000002
3921 /* LLDP / DCBX params*/
3922 #define DRV_MB_PARAM_LLDP_SEND_MASK 0x00000001
3923 #define DRV_MB_PARAM_LLDP_SEND_SHIFT 0
3924 #define DRV_MB_PARAM_LLDP_AGENT_MASK 0x00000006
3925 #define DRV_MB_PARAM_LLDP_AGENT_SHIFT 1
3926 #define DRV_MB_PARAM_DCBX_NOTIFY_MASK 0x00000008
3927 #define DRV_MB_PARAM_DCBX_NOTIFY_SHIFT 3
3929 #define DRV_MB_PARAM_NIG_DRAIN_PERIOD_MS_MASK 0x000000FF
3930 #define DRV_MB_PARAM_NIG_DRAIN_PERIOD_MS_SHIFT 0
3932 #define DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_MFW 0x1
3933 #define DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_IMAGE 0x2
3935 #define DRV_MB_PARAM_NVM_OFFSET_SHIFT 0
3936 #define DRV_MB_PARAM_NVM_OFFSET_MASK 0x00FFFFFF
3937 #define DRV_MB_PARAM_NVM_LEN_SHIFT 24
3938 #define DRV_MB_PARAM_NVM_LEN_MASK 0xFF000000
3940 #define DRV_MB_PARAM_PHY_ADDR_SHIFT 0
3941 #define DRV_MB_PARAM_PHY_ADDR_MASK 0x1FF0FFFF
3942 #define DRV_MB_PARAM_PHY_LANE_SHIFT 16
3943 #define DRV_MB_PARAM_PHY_LANE_MASK 0x000F0000
3944 #define DRV_MB_PARAM_PHY_SELECT_PORT_SHIFT 29
3945 #define DRV_MB_PARAM_PHY_SELECT_PORT_MASK 0x20000000
3946 #define DRV_MB_PARAM_PHY_PORT_SHIFT 30
3947 #define DRV_MB_PARAM_PHY_PORT_MASK 0xc0000000
3949 /* configure vf MSIX params*/
3950 #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT 0
3951 #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK 0x000000FF
3952 #define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT 8
3953 #define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK 0x0000FF00
3955 #define DRV_MB_PARAM_SET_LED_MODE_OPER 0x0
3956 #define DRV_MB_PARAM_SET_LED_MODE_ON 0x1
3957 #define DRV_MB_PARAM_SET_LED_MODE_OFF 0x2
3959 #define DRV_MB_PARAM_BIST_UNKNOWN_TEST 0
3960 #define DRV_MB_PARAM_BIST_REGISTER_TEST 1
3961 #define DRV_MB_PARAM_BIST_CLOCK_TEST 2
3963 #define DRV_MB_PARAM_BIST_RC_UNKNOWN 0
3964 #define DRV_MB_PARAM_BIST_RC_PASSED 1
3965 #define DRV_MB_PARAM_BIST_RC_FAILED 2
3966 #define DRV_MB_PARAM_BIST_RC_INVALID_PARAMETER 3
3968 #define DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT 0
3969 #define DRV_MB_PARAM_BIST_TEST_INDEX_MASK 0x000000FF
3972 #define FW_MSG_CODE_MASK 0xffff0000
3973 #define FW_MSG_CODE_DRV_LOAD_ENGINE 0x10100000
3974 #define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000
3975 #define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000
3976 #define FW_MSG_CODE_DRV_LOAD_REFUSED_PDA 0x10200000
3977 #define FW_MSG_CODE_DRV_LOAD_REFUSED_HSI 0x10210000
3978 #define FW_MSG_CODE_DRV_LOAD_REFUSED_DIAG 0x10220000
3979 #define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000
3980 #define FW_MSG_CODE_DRV_UNLOAD_ENGINE 0x20110000
3981 #define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20120000
3982 #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20130000
3983 #define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000
3984 #define FW_MSG_CODE_INIT_PHY_DONE 0x21200000
3985 #define FW_MSG_CODE_INIT_PHY_ERR_INVALID_ARGS 0x21300000
3986 #define FW_MSG_CODE_LINK_RESET_DONE 0x23000000
3987 #define FW_MSG_CODE_SET_LLDP_DONE 0x24000000
3988 #define FW_MSG_CODE_SET_LLDP_UNSUPPORTED_AGENT 0x24010000
3989 #define FW_MSG_CODE_SET_DCBX_DONE 0x25000000
3990 #define FW_MSG_CODE_NIG_DRAIN_DONE 0x30000000
3991 #define FW_MSG_CODE_VF_DISABLED_DONE 0xb0000000
3992 #define FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE 0xb0010000
3993 #define FW_MSG_CODE_FLR_ACK 0x02000000
3994 #define FW_MSG_CODE_FLR_NACK 0x02100000
3996 #define FW_MSG_CODE_NVM_OK 0x00010000
3997 #define FW_MSG_CODE_NVM_INVALID_MODE 0x00020000
3998 #define FW_MSG_CODE_NVM_PREV_CMD_WAS_NOT_FINISHED 0x00030000
3999 #define FW_MSG_CODE_NVM_FAILED_TO_ALLOCATE_PAGE 0x00040000
4000 #define FW_MSG_CODE_NVM_INVALID_DIR_FOUND 0x00050000
4001 #define FW_MSG_CODE_NVM_PAGE_NOT_FOUND 0x00060000
4002 #define FW_MSG_CODE_NVM_FAILED_PARSING_BNDLE_HEADER 0x00070000
4003 #define FW_MSG_CODE_NVM_FAILED_PARSING_IMAGE_HEADER 0x00080000
4004 #define FW_MSG_CODE_NVM_PARSING_OUT_OF_SYNC 0x00090000
4005 #define FW_MSG_CODE_NVM_FAILED_UPDATING_DIR 0x000a0000
4006 #define FW_MSG_CODE_NVM_FAILED_TO_FREE_PAGE 0x000b0000
4007 #define FW_MSG_CODE_NVM_FILE_NOT_FOUND 0x000c0000
4008 #define FW_MSG_CODE_NVM_OPERATION_FAILED 0x000d0000
4009 #define FW_MSG_CODE_NVM_FAILED_UNALIGNED 0x000e0000
4010 #define FW_MSG_CODE_NVM_BAD_OFFSET 0x000f0000
4011 #define FW_MSG_CODE_NVM_BAD_SIGNATURE 0x00100000
4012 #define FW_MSG_CODE_NVM_FILE_READ_ONLY 0x00200000
4013 #define FW_MSG_CODE_NVM_UNKNOWN_FILE 0x00300000
4014 #define FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK 0x00400000
4015 #define FW_MSG_CODE_MCP_RESET_REJECT 0x00600000
4016 #define FW_MSG_CODE_PHY_OK 0x00110000
4017 #define FW_MSG_CODE_PHY_ERROR 0x00120000
4018 #define FW_MSG_CODE_SET_SECURE_MODE_ERROR 0x00130000
4019 #define FW_MSG_CODE_SET_SECURE_MODE_OK 0x00140000
4020 #define FW_MSG_MODE_PHY_PRIVILEGE_ERROR 0x00150000
4021 #define FW_MSG_CODE_OK 0x00160000
4023 #define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff
4028 #define DRV_PULSE_SEQ_MASK 0x00007fff
4029 #define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000
4030 #define DRV_PULSE_ALWAYS_ALIVE 0x00008000
4032 #define MCP_PULSE_SEQ_MASK 0x00007fff
4033 #define MCP_PULSE_ALWAYS_ALIVE 0x00008000
4034 #define MCP_EVENT_MASK 0xffff0000
4035 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000
4037 union drv_union_data union_data;
4041 /**********************************************************************
4043 * Incremental Aggregative
4044 * 8-bit MFW counter per message
4045 * 8-bit ack-counter per message
4047 * Provides up to 256 aggregative message per type
4048 * Provides 4 message types in dword
4049 * Message type pointers to byte offset
4050 * Backward Compatibility by using sizeof for the counters.
4051 * No lock requires for 32bit messages
4053 * In case of messages greater than 32bit, a dedicated mechanism(e.g lock)
4054 * is required to prevent data corruption.
4055 **********************************************************************/
4056 enum MFW_DRV_MSG_TYPE {
4057 MFW_DRV_MSG_LINK_CHANGE,
4058 MFW_DRV_MSG_FLR_FW_ACK_FAILED,
4059 MFW_DRV_MSG_VF_DISABLED,
4060 MFW_DRV_MSG_LLDP_DATA_UPDATED,
4061 MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED,
4062 MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED,
4063 MFW_DRV_MSG_ERROR_RECOVERY,
4064 MFW_DRV_MSG_BW_UPDATE,
4065 MFW_DRV_MSG_S_TAG_UPDATE,
4066 MFW_DRV_MSG_GET_LAN_STATS,
4067 MFW_DRV_MSG_GET_FCOE_STATS,
4068 MFW_DRV_MSG_GET_ISCSI_STATS,
4069 MFW_DRV_MSG_GET_RDMA_STATS,
4070 MFW_DRV_MSG_FAILURE_DETECTED,
4071 MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE,
4075 #define MFW_DRV_MSG_MAX_DWORDS(msgs) (((msgs - 1) >> 2) + 1)
4076 #define MFW_DRV_MSG_DWORD(msg_id) (msg_id >> 2)
4077 #define MFW_DRV_MSG_OFFSET(msg_id) ((msg_id & 0x3) << 3)
4078 #define MFW_DRV_MSG_MASK(msg_id) (0xff << MFW_DRV_MSG_OFFSET(msg_id))
4080 struct public_mfw_mb {
4082 u32 msg[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)];
4083 u32 ack[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)];
4086 /**************************************/
4088 /* P U B L I C D A T A */
4090 /**************************************/
4091 enum public_sections {
4092 PUBLIC_DRV_MB, /* Points to the first drv_mb of path0 */
4093 PUBLIC_MFW_MB, /* Points to the first mfw_mb of path0 */
4101 struct drv_ver_info_stc {
4106 struct mcp_public_data {
4107 /* The sections fields is an array */
4109 offsize_t sections[PUBLIC_MAX_SECTIONS];
4110 struct public_drv_mb drv_mb[MCP_GLOB_FUNC_MAX];
4111 struct public_mfw_mb mfw_mb[MCP_GLOB_FUNC_MAX];
4112 struct public_global global;
4113 struct public_path path[MCP_GLOB_PATH_MAX];
4114 struct public_port port[MCP_GLOB_PORT_MAX];
4115 struct public_func func[MCP_GLOB_FUNC_MAX];
4116 struct drv_ver_info_stc drv_info;
4119 struct nvm_cfg_mac_address {
4121 #define NVM_CFG_MAC_ADDRESS_HI_MASK 0x0000FFFF
4122 #define NVM_CFG_MAC_ADDRESS_HI_OFFSET 0
4127 /******************************************
4129 ******************************************/
4131 struct nvm_cfg1_glob {
4132 u32 generic_cont0; /* 0x0 */
4133 #define NVM_CFG1_GLOB_BOARD_SWAP_MASK 0x0000000F
4134 #define NVM_CFG1_GLOB_BOARD_SWAP_OFFSET 0
4135 #define NVM_CFG1_GLOB_BOARD_SWAP_NONE 0x0
4136 #define NVM_CFG1_GLOB_BOARD_SWAP_PATH 0x1
4137 #define NVM_CFG1_GLOB_BOARD_SWAP_PORT 0x2
4138 #define NVM_CFG1_GLOB_BOARD_SWAP_BOTH 0x3
4139 #define NVM_CFG1_GLOB_MF_MODE_MASK 0x00000FF0
4140 #define NVM_CFG1_GLOB_MF_MODE_OFFSET 4
4141 #define NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED 0x0
4142 #define NVM_CFG1_GLOB_MF_MODE_DEFAULT 0x1
4143 #define NVM_CFG1_GLOB_MF_MODE_SPIO4 0x2
4144 #define NVM_CFG1_GLOB_MF_MODE_NPAR1_0 0x3
4145 #define NVM_CFG1_GLOB_MF_MODE_NPAR1_5 0x4
4146 #define NVM_CFG1_GLOB_MF_MODE_NPAR2_0 0x5
4147 #define NVM_CFG1_GLOB_MF_MODE_BD 0x6
4148 #define NVM_CFG1_GLOB_MF_MODE_UFP 0x7
4149 #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_MASK 0x00001000
4150 #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_OFFSET 12
4151 #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_DISABLED 0x0
4152 #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_ENABLED 0x1
4153 #define NVM_CFG1_GLOB_AVS_MARGIN_LOW_MASK 0x001FE000
4154 #define NVM_CFG1_GLOB_AVS_MARGIN_LOW_OFFSET 13
4155 #define NVM_CFG1_GLOB_AVS_MARGIN_HIGH_MASK 0x1FE00000
4156 #define NVM_CFG1_GLOB_AVS_MARGIN_HIGH_OFFSET 21
4157 #define NVM_CFG1_GLOB_ENABLE_SRIOV_MASK 0x20000000
4158 #define NVM_CFG1_GLOB_ENABLE_SRIOV_OFFSET 29
4159 #define NVM_CFG1_GLOB_ENABLE_SRIOV_DISABLED 0x0
4160 #define NVM_CFG1_GLOB_ENABLE_SRIOV_ENABLED 0x1
4161 #define NVM_CFG1_GLOB_ENABLE_ATC_MASK 0x40000000
4162 #define NVM_CFG1_GLOB_ENABLE_ATC_OFFSET 30
4163 #define NVM_CFG1_GLOB_ENABLE_ATC_DISABLED 0x0
4164 #define NVM_CFG1_GLOB_ENABLE_ATC_ENABLED 0x1
4165 #define NVM_CFG1_GLOB_CLOCK_SLOWDOWN_MASK 0x80000000
4166 #define NVM_CFG1_GLOB_CLOCK_SLOWDOWN_OFFSET 31
4167 #define NVM_CFG1_GLOB_CLOCK_SLOWDOWN_DISABLED 0x0
4168 #define NVM_CFG1_GLOB_CLOCK_SLOWDOWN_ENABLED 0x1
4170 u32 engineering_change[3]; /* 0x4 */
4172 u32 manufacturing_id; /* 0x10 */
4174 u32 serial_number[4]; /* 0x14 */
4176 u32 pcie_cfg; /* 0x24 */
4177 #define NVM_CFG1_GLOB_PCI_GEN_MASK 0x00000003
4178 #define NVM_CFG1_GLOB_PCI_GEN_OFFSET 0
4179 #define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN1 0x0
4180 #define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN2 0x1
4181 #define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN3 0x2
4182 #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_MASK 0x00000004
4183 #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_OFFSET 2
4184 #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_DISABLED 0x0
4185 #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_ENABLED 0x1
4186 #define NVM_CFG1_GLOB_ASPM_SUPPORT_MASK 0x00000018
4187 #define NVM_CFG1_GLOB_ASPM_SUPPORT_OFFSET 3
4188 #define NVM_CFG1_GLOB_ASPM_SUPPORT_L0S_L1_ENABLED 0x0
4189 #define NVM_CFG1_GLOB_ASPM_SUPPORT_L0S_DISABLED 0x1
4190 #define NVM_CFG1_GLOB_ASPM_SUPPORT_L1_DISABLED 0x2
4191 #define NVM_CFG1_GLOB_ASPM_SUPPORT_L0S_L1_DISABLED 0x3
4192 #define NVM_CFG1_GLOB_PREVENT_PCIE_L1_MENTRY_MASK 0x00000020
4193 #define NVM_CFG1_GLOB_PREVENT_PCIE_L1_MENTRY_OFFSET 5
4194 #define NVM_CFG1_GLOB_PREVENT_PCIE_L1_MENTRY_DISABLED 0x0
4195 #define NVM_CFG1_GLOB_PREVENT_PCIE_L1_MENTRY_ENABLED 0x1
4196 #define NVM_CFG1_GLOB_PCIE_G2_TX_AMPLITUDE_MASK 0x000003C0
4197 #define NVM_CFG1_GLOB_PCIE_G2_TX_AMPLITUDE_OFFSET 6
4198 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_MASK 0x00001C00
4199 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_OFFSET 10
4200 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_HW 0x0
4201 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_0DB 0x1
4202 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_3_5DB 0x2
4203 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_6_0DB 0x3
4204 #define NVM_CFG1_GLOB_WWN_NODE_PREFIX0_MASK 0x001FE000
4205 #define NVM_CFG1_GLOB_WWN_NODE_PREFIX0_OFFSET 13
4206 #define NVM_CFG1_GLOB_WWN_NODE_PREFIX1_MASK 0x1FE00000
4207 #define NVM_CFG1_GLOB_WWN_NODE_PREFIX1_OFFSET 21
4208 #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_MASK 0x60000000
4209 #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_OFFSET 29
4211 u32 mgmt_traffic; /* 0x28 */
4212 #define NVM_CFG1_GLOB_RESERVED60_MASK 0x00000001
4213 #define NVM_CFG1_GLOB_RESERVED60_OFFSET 0
4214 #define NVM_CFG1_GLOB_RESERVED60_100KHZ 0x0
4215 #define NVM_CFG1_GLOB_RESERVED60_400KHZ 0x1
4216 #define NVM_CFG1_GLOB_WWN_PORT_PREFIX0_MASK 0x000001FE
4217 #define NVM_CFG1_GLOB_WWN_PORT_PREFIX0_OFFSET 1
4218 #define NVM_CFG1_GLOB_WWN_PORT_PREFIX1_MASK 0x0001FE00
4219 #define NVM_CFG1_GLOB_WWN_PORT_PREFIX1_OFFSET 9
4220 #define NVM_CFG1_GLOB_SMBUS_ADDRESS_MASK 0x01FE0000
4221 #define NVM_CFG1_GLOB_SMBUS_ADDRESS_OFFSET 17
4222 #define NVM_CFG1_GLOB_SIDEBAND_MODE_MASK 0x06000000
4223 #define NVM_CFG1_GLOB_SIDEBAND_MODE_OFFSET 25
4224 #define NVM_CFG1_GLOB_SIDEBAND_MODE_DISABLED 0x0
4225 #define NVM_CFG1_GLOB_SIDEBAND_MODE_RMII 0x1
4226 #define NVM_CFG1_GLOB_SIDEBAND_MODE_SGMII 0x2
4228 u32 core_cfg; /* 0x2C */
4229 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK 0x000000FF
4230 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET 0
4231 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_2X40G 0x0
4232 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_2X50G 0x1
4233 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_1X100G 0x2
4234 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_4X10G_F 0x3
4235 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_4X10G_E 0x4
4236 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_4X20G 0x5
4237 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_1X40G 0xB
4238 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_2X25G 0xC
4239 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_1X25G 0xD
4240 #define NVM_CFG1_GLOB_EAGLE_ENFORCE_TX_FIR_CFG_MASK 0x00000100
4241 #define NVM_CFG1_GLOB_EAGLE_ENFORCE_TX_FIR_CFG_OFFSET 8
4242 #define NVM_CFG1_GLOB_EAGLE_ENFORCE_TX_FIR_CFG_DISABLED 0x0
4243 #define NVM_CFG1_GLOB_EAGLE_ENFORCE_TX_FIR_CFG_ENABLED 0x1
4244 #define NVM_CFG1_GLOB_FALCON_ENFORCE_TX_FIR_CFG_MASK 0x00000200
4245 #define NVM_CFG1_GLOB_FALCON_ENFORCE_TX_FIR_CFG_OFFSET 9
4246 #define NVM_CFG1_GLOB_FALCON_ENFORCE_TX_FIR_CFG_DISABLED 0x0
4247 #define NVM_CFG1_GLOB_FALCON_ENFORCE_TX_FIR_CFG_ENABLED 0x1
4248 #define NVM_CFG1_GLOB_EAGLE_CORE_ADDR_MASK 0x0003FC00
4249 #define NVM_CFG1_GLOB_EAGLE_CORE_ADDR_OFFSET 10
4250 #define NVM_CFG1_GLOB_FALCON_CORE_ADDR_MASK 0x03FC0000
4251 #define NVM_CFG1_GLOB_FALCON_CORE_ADDR_OFFSET 18
4252 #define NVM_CFG1_GLOB_AVS_MODE_MASK 0x1C000000
4253 #define NVM_CFG1_GLOB_AVS_MODE_OFFSET 26
4254 #define NVM_CFG1_GLOB_AVS_MODE_CLOSE_LOOP 0x0
4255 #define NVM_CFG1_GLOB_AVS_MODE_OPEN_LOOP 0x1
4256 #define NVM_CFG1_GLOB_AVS_MODE_DISABLED 0x3
4257 #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_MASK 0x60000000
4258 #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_OFFSET 29
4259 #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_DISABLED 0x0
4260 #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_ENABLED 0x1
4262 u32 e_lane_cfg1; /* 0x30 */
4263 #define NVM_CFG1_GLOB_RX_LANE0_SWAP_MASK 0x0000000F
4264 #define NVM_CFG1_GLOB_RX_LANE0_SWAP_OFFSET 0
4265 #define NVM_CFG1_GLOB_RX_LANE1_SWAP_MASK 0x000000F0
4266 #define NVM_CFG1_GLOB_RX_LANE1_SWAP_OFFSET 4
4267 #define NVM_CFG1_GLOB_RX_LANE2_SWAP_MASK 0x00000F00
4268 #define NVM_CFG1_GLOB_RX_LANE2_SWAP_OFFSET 8
4269 #define NVM_CFG1_GLOB_RX_LANE3_SWAP_MASK 0x0000F000
4270 #define NVM_CFG1_GLOB_RX_LANE3_SWAP_OFFSET 12
4271 #define NVM_CFG1_GLOB_TX_LANE0_SWAP_MASK 0x000F0000
4272 #define NVM_CFG1_GLOB_TX_LANE0_SWAP_OFFSET 16
4273 #define NVM_CFG1_GLOB_TX_LANE1_SWAP_MASK 0x00F00000
4274 #define NVM_CFG1_GLOB_TX_LANE1_SWAP_OFFSET 20
4275 #define NVM_CFG1_GLOB_TX_LANE2_SWAP_MASK 0x0F000000
4276 #define NVM_CFG1_GLOB_TX_LANE2_SWAP_OFFSET 24
4277 #define NVM_CFG1_GLOB_TX_LANE3_SWAP_MASK 0xF0000000
4278 #define NVM_CFG1_GLOB_TX_LANE3_SWAP_OFFSET 28
4280 u32 e_lane_cfg2; /* 0x34 */
4281 #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_MASK 0x00000001
4282 #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_OFFSET 0
4283 #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_MASK 0x00000002
4284 #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_OFFSET 1
4285 #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_MASK 0x00000004
4286 #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_OFFSET 2
4287 #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_MASK 0x00000008
4288 #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_OFFSET 3
4289 #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_MASK 0x00000010
4290 #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_OFFSET 4
4291 #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_MASK 0x00000020
4292 #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_OFFSET 5
4293 #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_MASK 0x00000040
4294 #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_OFFSET 6
4295 #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_MASK 0x00000080
4296 #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_OFFSET 7
4297 #define NVM_CFG1_GLOB_SMBUS_MODE_MASK 0x00000F00
4298 #define NVM_CFG1_GLOB_SMBUS_MODE_OFFSET 8
4299 #define NVM_CFG1_GLOB_SMBUS_MODE_DISABLED 0x0
4300 #define NVM_CFG1_GLOB_SMBUS_MODE_100KHZ 0x1
4301 #define NVM_CFG1_GLOB_SMBUS_MODE_400KHZ 0x2
4302 #define NVM_CFG1_GLOB_NCSI_MASK 0x0000F000
4303 #define NVM_CFG1_GLOB_NCSI_OFFSET 12
4304 #define NVM_CFG1_GLOB_NCSI_DISABLED 0x0
4305 #define NVM_CFG1_GLOB_NCSI_ENABLED 0x1
4307 u32 f_lane_cfg1; /* 0x38 */
4308 #define NVM_CFG1_GLOB_RX_LANE0_SWAP_MASK 0x0000000F
4309 #define NVM_CFG1_GLOB_RX_LANE0_SWAP_OFFSET 0
4310 #define NVM_CFG1_GLOB_RX_LANE1_SWAP_MASK 0x000000F0
4311 #define NVM_CFG1_GLOB_RX_LANE1_SWAP_OFFSET 4
4312 #define NVM_CFG1_GLOB_RX_LANE2_SWAP_MASK 0x00000F00
4313 #define NVM_CFG1_GLOB_RX_LANE2_SWAP_OFFSET 8
4314 #define NVM_CFG1_GLOB_RX_LANE3_SWAP_MASK 0x0000F000
4315 #define NVM_CFG1_GLOB_RX_LANE3_SWAP_OFFSET 12
4316 #define NVM_CFG1_GLOB_TX_LANE0_SWAP_MASK 0x000F0000
4317 #define NVM_CFG1_GLOB_TX_LANE0_SWAP_OFFSET 16
4318 #define NVM_CFG1_GLOB_TX_LANE1_SWAP_MASK 0x00F00000
4319 #define NVM_CFG1_GLOB_TX_LANE1_SWAP_OFFSET 20
4320 #define NVM_CFG1_GLOB_TX_LANE2_SWAP_MASK 0x0F000000
4321 #define NVM_CFG1_GLOB_TX_LANE2_SWAP_OFFSET 24
4322 #define NVM_CFG1_GLOB_TX_LANE3_SWAP_MASK 0xF0000000
4323 #define NVM_CFG1_GLOB_TX_LANE3_SWAP_OFFSET 28
4325 u32 f_lane_cfg2; /* 0x3C */
4326 #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_MASK 0x00000001
4327 #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_OFFSET 0
4328 #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_MASK 0x00000002
4329 #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_OFFSET 1
4330 #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_MASK 0x00000004
4331 #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_OFFSET 2
4332 #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_MASK 0x00000008
4333 #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_OFFSET 3
4334 #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_MASK 0x00000010
4335 #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_OFFSET 4
4336 #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_MASK 0x00000020
4337 #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_OFFSET 5
4338 #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_MASK 0x00000040
4339 #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_OFFSET 6
4340 #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_MASK 0x00000080
4341 #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_OFFSET 7
4343 u32 eagle_preemphasis; /* 0x40 */
4344 #define NVM_CFG1_GLOB_LANE0_PREEMP_MASK 0x000000FF
4345 #define NVM_CFG1_GLOB_LANE0_PREEMP_OFFSET 0
4346 #define NVM_CFG1_GLOB_LANE1_PREEMP_MASK 0x0000FF00
4347 #define NVM_CFG1_GLOB_LANE1_PREEMP_OFFSET 8
4348 #define NVM_CFG1_GLOB_LANE2_PREEMP_MASK 0x00FF0000
4349 #define NVM_CFG1_GLOB_LANE2_PREEMP_OFFSET 16
4350 #define NVM_CFG1_GLOB_LANE3_PREEMP_MASK 0xFF000000
4351 #define NVM_CFG1_GLOB_LANE3_PREEMP_OFFSET 24
4353 u32 eagle_driver_current; /* 0x44 */
4354 #define NVM_CFG1_GLOB_LANE0_AMP_MASK 0x000000FF
4355 #define NVM_CFG1_GLOB_LANE0_AMP_OFFSET 0
4356 #define NVM_CFG1_GLOB_LANE1_AMP_MASK 0x0000FF00
4357 #define NVM_CFG1_GLOB_LANE1_AMP_OFFSET 8
4358 #define NVM_CFG1_GLOB_LANE2_AMP_MASK 0x00FF0000
4359 #define NVM_CFG1_GLOB_LANE2_AMP_OFFSET 16
4360 #define NVM_CFG1_GLOB_LANE3_AMP_MASK 0xFF000000
4361 #define NVM_CFG1_GLOB_LANE3_AMP_OFFSET 24
4363 u32 falcon_preemphasis; /* 0x48 */
4364 #define NVM_CFG1_GLOB_LANE0_PREEMP_MASK 0x000000FF
4365 #define NVM_CFG1_GLOB_LANE0_PREEMP_OFFSET 0
4366 #define NVM_CFG1_GLOB_LANE1_PREEMP_MASK 0x0000FF00
4367 #define NVM_CFG1_GLOB_LANE1_PREEMP_OFFSET 8
4368 #define NVM_CFG1_GLOB_LANE2_PREEMP_MASK 0x00FF0000
4369 #define NVM_CFG1_GLOB_LANE2_PREEMP_OFFSET 16
4370 #define NVM_CFG1_GLOB_LANE3_PREEMP_MASK 0xFF000000
4371 #define NVM_CFG1_GLOB_LANE3_PREEMP_OFFSET 24
4373 u32 falcon_driver_current; /* 0x4C */
4374 #define NVM_CFG1_GLOB_LANE0_AMP_MASK 0x000000FF
4375 #define NVM_CFG1_GLOB_LANE0_AMP_OFFSET 0
4376 #define NVM_CFG1_GLOB_LANE1_AMP_MASK 0x0000FF00
4377 #define NVM_CFG1_GLOB_LANE1_AMP_OFFSET 8
4378 #define NVM_CFG1_GLOB_LANE2_AMP_MASK 0x00FF0000
4379 #define NVM_CFG1_GLOB_LANE2_AMP_OFFSET 16
4380 #define NVM_CFG1_GLOB_LANE3_AMP_MASK 0xFF000000
4381 #define NVM_CFG1_GLOB_LANE3_AMP_OFFSET 24
4383 u32 pci_id; /* 0x50 */
4384 #define NVM_CFG1_GLOB_VENDOR_ID_MASK 0x0000FFFF
4385 #define NVM_CFG1_GLOB_VENDOR_ID_OFFSET 0
4387 u32 pci_subsys_id; /* 0x54 */
4388 #define NVM_CFG1_GLOB_SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFF
4389 #define NVM_CFG1_GLOB_SUBSYSTEM_VENDOR_ID_OFFSET 0
4390 #define NVM_CFG1_GLOB_SUBSYSTEM_DEVICE_ID_MASK 0xFFFF0000
4391 #define NVM_CFG1_GLOB_SUBSYSTEM_DEVICE_ID_OFFSET 16
4394 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_MASK 0x0000000F
4395 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_OFFSET 0
4396 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_DISABLED 0x0
4397 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_2K 0x1
4398 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_4K 0x2
4399 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_8K 0x3
4400 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_16K 0x4
4401 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_32K 0x5
4402 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_64K 0x6
4403 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_128K 0x7
4404 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_256K 0x8
4405 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_512K 0x9
4406 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_1M 0xA
4407 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_2M 0xB
4408 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_4M 0xC
4409 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_8M 0xD
4410 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_16M 0xE
4411 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_32M 0xF
4412 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_MASK 0x000000F0
4413 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_OFFSET 4
4414 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_DISABLED 0x0
4415 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_4K 0x1
4416 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_8K 0x2
4417 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_16K 0x3
4418 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_32K 0x4
4419 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_64K 0x5
4420 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_128K 0x6
4421 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_256K 0x7
4422 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_512K 0x8
4423 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_1M 0x9
4424 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_2M 0xA
4425 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_4M 0xB
4426 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_8M 0xC
4427 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_16M 0xD
4428 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_32M 0xE
4429 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_64M 0xF
4430 #define NVM_CFG1_GLOB_BAR2_SIZE_MASK 0x00000F00
4431 #define NVM_CFG1_GLOB_BAR2_SIZE_OFFSET 8
4432 #define NVM_CFG1_GLOB_BAR2_SIZE_DISABLED 0x0
4433 #define NVM_CFG1_GLOB_BAR2_SIZE_64K 0x1
4434 #define NVM_CFG1_GLOB_BAR2_SIZE_128K 0x2
4435 #define NVM_CFG1_GLOB_BAR2_SIZE_256K 0x3
4436 #define NVM_CFG1_GLOB_BAR2_SIZE_512K 0x4
4437 #define NVM_CFG1_GLOB_BAR2_SIZE_1M 0x5
4438 #define NVM_CFG1_GLOB_BAR2_SIZE_2M 0x6
4439 #define NVM_CFG1_GLOB_BAR2_SIZE_4M 0x7
4440 #define NVM_CFG1_GLOB_BAR2_SIZE_8M 0x8
4441 #define NVM_CFG1_GLOB_BAR2_SIZE_16M 0x9
4442 #define NVM_CFG1_GLOB_BAR2_SIZE_32M 0xA
4443 #define NVM_CFG1_GLOB_BAR2_SIZE_64M 0xB
4444 #define NVM_CFG1_GLOB_BAR2_SIZE_128M 0xC
4445 #define NVM_CFG1_GLOB_BAR2_SIZE_256M 0xD
4446 #define NVM_CFG1_GLOB_BAR2_SIZE_512M 0xE
4447 #define NVM_CFG1_GLOB_BAR2_SIZE_1G 0xF
4449 u32 eagle_txfir_main; /* 0x5C */
4450 #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_MASK 0x000000FF
4451 #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_OFFSET 0
4452 #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_MASK 0x0000FF00
4453 #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_OFFSET 8
4454 #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_MASK 0x00FF0000
4455 #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_OFFSET 16
4456 #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_MASK 0xFF000000
4457 #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_OFFSET 24
4459 u32 eagle_txfir_post; /* 0x60 */
4460 #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_MASK 0x000000FF
4461 #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_OFFSET 0
4462 #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_MASK 0x0000FF00
4463 #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_OFFSET 8
4464 #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_MASK 0x00FF0000
4465 #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_OFFSET 16
4466 #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_MASK 0xFF000000
4467 #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_OFFSET 24
4469 u32 falcon_txfir_main; /* 0x64 */
4470 #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_MASK 0x000000FF
4471 #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_OFFSET 0
4472 #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_MASK 0x0000FF00
4473 #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_OFFSET 8
4474 #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_MASK 0x00FF0000
4475 #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_OFFSET 16
4476 #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_MASK 0xFF000000
4477 #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_OFFSET 24
4479 u32 falcon_txfir_post; /* 0x68 */
4480 #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_MASK 0x000000FF
4481 #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_OFFSET 0
4482 #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_MASK 0x0000FF00
4483 #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_OFFSET 8
4484 #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_MASK 0x00FF0000
4485 #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_OFFSET 16
4486 #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_MASK 0xFF000000
4487 #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_OFFSET 24
4489 u32 manufacture_ver; /* 0x6C */
4490 #define NVM_CFG1_GLOB_MANUF0_VER_MASK 0x0000003F
4491 #define NVM_CFG1_GLOB_MANUF0_VER_OFFSET 0
4492 #define NVM_CFG1_GLOB_MANUF1_VER_MASK 0x00000FC0
4493 #define NVM_CFG1_GLOB_MANUF1_VER_OFFSET 6
4494 #define NVM_CFG1_GLOB_MANUF2_VER_MASK 0x0003F000
4495 #define NVM_CFG1_GLOB_MANUF2_VER_OFFSET 12
4496 #define NVM_CFG1_GLOB_MANUF3_VER_MASK 0x00FC0000
4497 #define NVM_CFG1_GLOB_MANUF3_VER_OFFSET 18
4498 #define NVM_CFG1_GLOB_MANUF4_VER_MASK 0x3F000000
4499 #define NVM_CFG1_GLOB_MANUF4_VER_OFFSET 24
4501 u32 manufacture_time; /* 0x70 */
4502 #define NVM_CFG1_GLOB_MANUF0_TIME_MASK 0x0000003F
4503 #define NVM_CFG1_GLOB_MANUF0_TIME_OFFSET 0
4504 #define NVM_CFG1_GLOB_MANUF1_TIME_MASK 0x00000FC0
4505 #define NVM_CFG1_GLOB_MANUF1_TIME_OFFSET 6
4506 #define NVM_CFG1_GLOB_MANUF2_TIME_MASK 0x0003F000
4507 #define NVM_CFG1_GLOB_MANUF2_TIME_OFFSET 12
4509 u32 led_global_settings; /* 0x74 */
4510 #define NVM_CFG1_GLOB_LED_SWAP_0_MASK 0x0000000F
4511 #define NVM_CFG1_GLOB_LED_SWAP_0_OFFSET 0
4512 #define NVM_CFG1_GLOB_LED_SWAP_1_MASK 0x000000F0
4513 #define NVM_CFG1_GLOB_LED_SWAP_1_OFFSET 4
4514 #define NVM_CFG1_GLOB_LED_SWAP_2_MASK 0x00000F00
4515 #define NVM_CFG1_GLOB_LED_SWAP_2_OFFSET 8
4516 #define NVM_CFG1_GLOB_LED_SWAP_3_MASK 0x0000F000
4517 #define NVM_CFG1_GLOB_LED_SWAP_3_OFFSET 12
4519 u32 generic_cont1; /* 0x78 */
4520 #define NVM_CFG1_GLOB_AVS_DAC_CODE_MASK 0x000003FF
4521 #define NVM_CFG1_GLOB_AVS_DAC_CODE_OFFSET 0
4523 u32 mbi_version; /* 0x7C */
4524 #define NVM_CFG1_GLOB_MBI_VERSION_0_MASK 0x000000FF
4525 #define NVM_CFG1_GLOB_MBI_VERSION_0_OFFSET 0
4526 #define NVM_CFG1_GLOB_MBI_VERSION_1_MASK 0x0000FF00
4527 #define NVM_CFG1_GLOB_MBI_VERSION_1_OFFSET 8
4528 #define NVM_CFG1_GLOB_MBI_VERSION_2_MASK 0x00FF0000
4529 #define NVM_CFG1_GLOB_MBI_VERSION_2_OFFSET 16
4531 u32 mbi_date; /* 0x80 */
4533 u32 misc_sig; /* 0x84 */
4535 /* Define the GPIO mapping to switch i2c mux */
4536 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_0_MASK 0x000000FF
4537 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_0_OFFSET 0
4538 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_1_MASK 0x0000FF00
4539 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_1_OFFSET 8
4540 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__NA 0x0
4541 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO0 0x1
4542 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO1 0x2
4543 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO2 0x3
4544 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO3 0x4
4545 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO4 0x5
4546 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO5 0x6
4547 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO6 0x7
4548 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO7 0x8
4549 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO8 0x9
4550 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO9 0xA
4551 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO10 0xB
4552 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO11 0xC
4553 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO12 0xD
4554 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO13 0xE
4555 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO14 0xF
4556 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO15 0x10
4557 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO16 0x11
4558 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO17 0x12
4559 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO18 0x13
4560 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO19 0x14
4561 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO20 0x15
4562 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO21 0x16
4563 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO22 0x17
4564 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO23 0x18
4565 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO24 0x19
4566 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO25 0x1A
4567 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO26 0x1B
4568 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO27 0x1C
4569 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO28 0x1D
4570 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO29 0x1E
4571 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO30 0x1F
4572 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO31 0x20
4573 u32 device_capabilities; /* 0x88 */
4574 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET 0x1
4575 u32 power_dissipated; /* 0x8C */
4576 u32 power_consumed; /* 0x90 */
4577 u32 efi_version; /* 0x94 */
4578 u32 reserved[42]; /* 0x98 */
4581 struct nvm_cfg1_path {
4582 u32 reserved[30]; /* 0x0 */
4585 struct nvm_cfg1_port {
4586 u32 reserved__m_relocated_to_option_123; /* 0x0 */
4587 u32 reserved__m_relocated_to_option_124; /* 0x4 */
4588 u32 generic_cont0; /* 0x8 */
4589 #define NVM_CFG1_PORT_LED_MODE_MASK 0x000000FF
4590 #define NVM_CFG1_PORT_LED_MODE_OFFSET 0
4591 #define NVM_CFG1_PORT_LED_MODE_MAC1 0x0
4592 #define NVM_CFG1_PORT_LED_MODE_PHY1 0x1
4593 #define NVM_CFG1_PORT_LED_MODE_PHY2 0x2
4594 #define NVM_CFG1_PORT_LED_MODE_PHY3 0x3
4595 #define NVM_CFG1_PORT_LED_MODE_MAC2 0x4
4596 #define NVM_CFG1_PORT_LED_MODE_PHY4 0x5
4597 #define NVM_CFG1_PORT_LED_MODE_PHY5 0x6
4598 #define NVM_CFG1_PORT_LED_MODE_PHY6 0x7
4599 #define NVM_CFG1_PORT_LED_MODE_MAC3 0x8
4600 #define NVM_CFG1_PORT_LED_MODE_PHY7 0x9
4601 #define NVM_CFG1_PORT_LED_MODE_PHY8 0xA
4602 #define NVM_CFG1_PORT_LED_MODE_PHY9 0xB
4603 #define NVM_CFG1_PORT_LED_MODE_MAC4 0xC
4604 #define NVM_CFG1_PORT_LED_MODE_PHY10 0xD
4605 #define NVM_CFG1_PORT_LED_MODE_PHY11 0xE
4606 #define NVM_CFG1_PORT_LED_MODE_PHY12 0xF
4607 #define NVM_CFG1_PORT_ROCE_PRIORITY_MASK 0x0000FF00
4608 #define NVM_CFG1_PORT_ROCE_PRIORITY_OFFSET 8
4609 #define NVM_CFG1_PORT_DCBX_MODE_MASK 0x000F0000
4610 #define NVM_CFG1_PORT_DCBX_MODE_OFFSET 16
4611 #define NVM_CFG1_PORT_DCBX_MODE_DISABLED 0x0
4612 #define NVM_CFG1_PORT_DCBX_MODE_IEEE 0x1
4613 #define NVM_CFG1_PORT_DCBX_MODE_CEE 0x2
4614 #define NVM_CFG1_PORT_DCBX_MODE_DYNAMIC 0x3
4615 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_MASK 0x00F00000
4616 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_OFFSET 20
4617 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ETHERNET 0x1
4618 u32 pcie_cfg; /* 0xC */
4619 #define NVM_CFG1_PORT_RESERVED15_MASK 0x00000007
4620 #define NVM_CFG1_PORT_RESERVED15_OFFSET 0
4622 u32 features; /* 0x10 */
4623 #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_MASK 0x00000001
4624 #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_OFFSET 0
4625 #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_DISABLED 0x0
4626 #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_ENABLED 0x1
4627 #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_MASK 0x00000002
4628 #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_OFFSET 1
4629 #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_DISABLED 0x0
4630 #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_ENABLED 0x1
4632 u32 speed_cap_mask; /* 0x14 */
4633 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK 0x0000FFFF
4634 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_OFFSET 0
4635 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G 0x1
4636 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G 0x2
4637 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G 0x8
4638 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G 0x10
4639 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G 0x20
4640 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_100G 0x40
4641 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_MASK 0xFFFF0000
4642 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_OFFSET 16
4643 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_1G 0x1
4644 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_10G 0x2
4645 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_25G 0x8
4646 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_40G 0x10
4647 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_50G 0x20
4648 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_100G 0x40
4650 u32 link_settings; /* 0x18 */
4651 #define NVM_CFG1_PORT_DRV_LINK_SPEED_MASK 0x0000000F
4652 #define NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET 0
4653 #define NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG 0x0
4654 #define NVM_CFG1_PORT_DRV_LINK_SPEED_1G 0x1
4655 #define NVM_CFG1_PORT_DRV_LINK_SPEED_10G 0x2
4656 #define NVM_CFG1_PORT_DRV_LINK_SPEED_25G 0x4
4657 #define NVM_CFG1_PORT_DRV_LINK_SPEED_40G 0x5
4658 #define NVM_CFG1_PORT_DRV_LINK_SPEED_50G 0x6
4659 #define NVM_CFG1_PORT_DRV_LINK_SPEED_100G 0x7
4660 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK 0x00000070
4661 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET 4
4662 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG 0x1
4663 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX 0x2
4664 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX 0x4
4665 #define NVM_CFG1_PORT_MFW_LINK_SPEED_MASK 0x00000780
4666 #define NVM_CFG1_PORT_MFW_LINK_SPEED_OFFSET 7
4667 #define NVM_CFG1_PORT_MFW_LINK_SPEED_AUTONEG 0x0
4668 #define NVM_CFG1_PORT_MFW_LINK_SPEED_1G 0x1
4669 #define NVM_CFG1_PORT_MFW_LINK_SPEED_10G 0x2
4670 #define NVM_CFG1_PORT_MFW_LINK_SPEED_25G 0x4
4671 #define NVM_CFG1_PORT_MFW_LINK_SPEED_40G 0x5
4672 #define NVM_CFG1_PORT_MFW_LINK_SPEED_50G 0x6
4673 #define NVM_CFG1_PORT_MFW_LINK_SPEED_100G 0x7
4674 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_MASK 0x00003800
4675 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_OFFSET 11
4676 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_AUTONEG 0x1
4677 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_RX 0x2
4678 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_TX 0x4
4679 #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_MASK 0x00004000
4680 #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_OFFSET 14
4681 #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_DISABLED 0x0
4682 #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_ENABLED 0x1
4684 u32 phy_cfg; /* 0x1C */
4685 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_MASK 0x0000FFFF
4686 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_OFFSET 0
4687 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_HIGIG 0x1
4688 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_SCRAMBLER 0x2
4689 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_FIBER 0x4
4690 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_DISABLE_CL72_AN 0x8
4691 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_DISABLE_FEC_AN 0x10
4692 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_MASK 0x00FF0000
4693 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_OFFSET 16
4694 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_BYPASS 0x0
4695 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR 0x2
4696 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR2 0x3
4697 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR4 0x4
4698 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XFI 0x8
4699 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_SFI 0x9
4700 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_1000X 0xB
4701 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_SGMII 0xC
4702 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XLAUI 0x11
4703 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XLPPI 0x12
4704 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_CAUI 0x21
4705 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_CPPI 0x22
4706 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_25GAUI 0x31
4707 #define NVM_CFG1_PORT_AN_MODE_MASK 0xFF000000
4708 #define NVM_CFG1_PORT_AN_MODE_OFFSET 24
4709 #define NVM_CFG1_PORT_AN_MODE_NONE 0x0
4710 #define NVM_CFG1_PORT_AN_MODE_CL73 0x1
4711 #define NVM_CFG1_PORT_AN_MODE_CL37 0x2
4712 #define NVM_CFG1_PORT_AN_MODE_CL73_BAM 0x3
4713 #define NVM_CFG1_PORT_AN_MODE_CL37_BAM 0x4
4714 #define NVM_CFG1_PORT_AN_MODE_HPAM 0x5
4715 #define NVM_CFG1_PORT_AN_MODE_SGMII 0x6
4717 u32 mgmt_traffic; /* 0x20 */
4718 #define NVM_CFG1_PORT_RESERVED61_MASK 0x0000000F
4719 #define NVM_CFG1_PORT_RESERVED61_OFFSET 0
4721 u32 ext_phy; /* 0x24 */
4722 #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_MASK 0x000000FF
4723 #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_OFFSET 0
4724 #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_NONE 0x0
4725 #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_BCM84844 0x1
4726 #define NVM_CFG1_PORT_EXTERNAL_PHY_ADDRESS_MASK 0x0000FF00
4727 #define NVM_CFG1_PORT_EXTERNAL_PHY_ADDRESS_OFFSET 8
4729 u32 mba_cfg1; /* 0x28 */
4730 #define NVM_CFG1_PORT_PREBOOT_OPROM_MASK 0x00000001
4731 #define NVM_CFG1_PORT_PREBOOT_OPROM_OFFSET 0
4732 #define NVM_CFG1_PORT_PREBOOT_OPROM_DISABLED 0x0
4733 #define NVM_CFG1_PORT_PREBOOT_OPROM_ENABLED 0x1
4734 #define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_TYPE_MASK 0x00000006
4735 #define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_TYPE_OFFSET 1
4736 #define NVM_CFG1_PORT_MBA_DELAY_TIME_MASK 0x00000078
4737 #define NVM_CFG1_PORT_MBA_DELAY_TIME_OFFSET 3
4738 #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_MASK 0x00000080
4739 #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_OFFSET 7
4740 #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_CTRL_S 0x0
4741 #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_CTRL_B 0x1
4742 #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_MASK 0x00000100
4743 #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_OFFSET 8
4744 #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_DISABLED 0x0
4745 #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_ENABLED 0x1
4746 #define NVM_CFG1_PORT_RESERVED5_MASK 0x0001FE00
4747 #define NVM_CFG1_PORT_RESERVED5_OFFSET 9
4748 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_MASK 0x001E0000
4749 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_OFFSET 17
4750 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_AUTONEG 0x0
4751 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_1G 0x1
4752 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_10G 0x2
4753 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_25G 0x4
4754 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_40G 0x5
4755 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_50G 0x6
4756 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_100G 0x7
4757 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_SMARTLINQ 0x8
4758 #define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_RETRY_COUNT_MASK 0x00E00000
4759 #define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_RETRY_COUNT_OFFSET 21
4761 u32 mba_cfg2; /* 0x2C */
4762 #define NVM_CFG1_PORT_RESERVED65_MASK 0x0000FFFF
4763 #define NVM_CFG1_PORT_RESERVED65_OFFSET 0
4764 #define NVM_CFG1_PORT_RESERVED66_MASK 0x00010000
4765 #define NVM_CFG1_PORT_RESERVED66_OFFSET 16
4767 u32 vf_cfg; /* 0x30 */
4768 #define NVM_CFG1_PORT_RESERVED8_MASK 0x0000FFFF
4769 #define NVM_CFG1_PORT_RESERVED8_OFFSET 0
4770 #define NVM_CFG1_PORT_RESERVED6_MASK 0x000F0000
4771 #define NVM_CFG1_PORT_RESERVED6_OFFSET 16
4773 struct nvm_cfg_mac_address lldp_mac_address; /* 0x34 */
4775 u32 led_port_settings; /* 0x3C */
4776 #define NVM_CFG1_PORT_LANE_LED_SPD_0_SEL_MASK 0x000000FF
4777 #define NVM_CFG1_PORT_LANE_LED_SPD_0_SEL_OFFSET 0
4778 #define NVM_CFG1_PORT_LANE_LED_SPD_1_SEL_MASK 0x0000FF00
4779 #define NVM_CFG1_PORT_LANE_LED_SPD_1_SEL_OFFSET 8
4780 #define NVM_CFG1_PORT_LANE_LED_SPD_2_SEL_MASK 0x00FF0000
4781 #define NVM_CFG1_PORT_LANE_LED_SPD_2_SEL_OFFSET 16
4782 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_1G 0x1
4783 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_10G 0x2
4784 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_25G 0x8
4785 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_40G 0x10
4786 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_50G 0x20
4787 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_100G 0x40
4789 u32 transceiver_00; /* 0x40 */
4791 /* Define for mapping of transceiver signal module absent */
4792 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_MASK 0x000000FF
4793 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_OFFSET 0
4794 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_NA 0x0
4795 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO0 0x1
4796 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO1 0x2
4797 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO2 0x3
4798 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO3 0x4
4799 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO4 0x5
4800 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO5 0x6
4801 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO6 0x7
4802 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO7 0x8
4803 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO8 0x9
4804 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO9 0xA
4805 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO10 0xB
4806 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO11 0xC
4807 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO12 0xD
4808 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO13 0xE
4809 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO14 0xF
4810 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO15 0x10
4811 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO16 0x11
4812 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO17 0x12
4813 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO18 0x13
4814 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO19 0x14
4815 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO20 0x15
4816 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO21 0x16
4817 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO22 0x17
4818 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO23 0x18
4819 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO24 0x19
4820 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO25 0x1A
4821 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO26 0x1B
4822 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO27 0x1C
4823 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO28 0x1D
4824 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO29 0x1E
4825 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO30 0x1F
4826 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO31 0x20
4827 /* Define the GPIO mux settings to switch i2c mux to this port */
4828 #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_0_MASK 0x00000F00
4829 #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_0_OFFSET 8
4830 #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_1_MASK 0x0000F000
4831 #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_1_OFFSET 12
4833 u32 reserved[133]; /* 0x44 */
4836 struct nvm_cfg1_func {
4837 struct nvm_cfg_mac_address mac_address; /* 0x0 */
4839 u32 rsrv1; /* 0x8 */
4840 #define NVM_CFG1_FUNC_RESERVED1_MASK 0x0000FFFF
4841 #define NVM_CFG1_FUNC_RESERVED1_OFFSET 0
4842 #define NVM_CFG1_FUNC_RESERVED2_MASK 0xFFFF0000
4843 #define NVM_CFG1_FUNC_RESERVED2_OFFSET 16
4845 u32 rsrv2; /* 0xC */
4846 #define NVM_CFG1_FUNC_RESERVED3_MASK 0x0000FFFF
4847 #define NVM_CFG1_FUNC_RESERVED3_OFFSET 0
4848 #define NVM_CFG1_FUNC_RESERVED4_MASK 0xFFFF0000
4849 #define NVM_CFG1_FUNC_RESERVED4_OFFSET 16
4851 u32 device_id; /* 0x10 */
4852 #define NVM_CFG1_FUNC_MF_VENDOR_DEVICE_ID_MASK 0x0000FFFF
4853 #define NVM_CFG1_FUNC_MF_VENDOR_DEVICE_ID_OFFSET 0
4854 #define NVM_CFG1_FUNC_RESERVED77_MASK 0xFFFF0000
4855 #define NVM_CFG1_FUNC_RESERVED77_OFFSET 16
4857 u32 cmn_cfg; /* 0x14 */
4858 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_MASK 0x00000007
4859 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_OFFSET 0
4860 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_PXE 0x0
4861 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_ISCSI_BOOT 0x3
4862 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_FCOE_BOOT 0x4
4863 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_NONE 0x7
4864 #define NVM_CFG1_FUNC_VF_PCI_DEVICE_ID_MASK 0x0007FFF8
4865 #define NVM_CFG1_FUNC_VF_PCI_DEVICE_ID_OFFSET 3
4866 #define NVM_CFG1_FUNC_PERSONALITY_MASK 0x00780000
4867 #define NVM_CFG1_FUNC_PERSONALITY_OFFSET 19
4868 #define NVM_CFG1_FUNC_PERSONALITY_ETHERNET 0x0
4869 #define NVM_CFG1_FUNC_PERSONALITY_ISCSI 0x1
4870 #define NVM_CFG1_FUNC_PERSONALITY_FCOE 0x2
4871 #define NVM_CFG1_FUNC_PERSONALITY_ROCE 0x3
4872 #define NVM_CFG1_FUNC_BANDWIDTH_WEIGHT_MASK 0x7F800000
4873 #define NVM_CFG1_FUNC_BANDWIDTH_WEIGHT_OFFSET 23
4874 #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_MASK 0x80000000
4875 #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_OFFSET 31
4876 #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_DISABLED 0x0
4877 #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_ENABLED 0x1
4879 u32 pci_cfg; /* 0x18 */
4880 #define NVM_CFG1_FUNC_NUMBER_OF_VFS_PER_PF_MASK 0x0000007F
4881 #define NVM_CFG1_FUNC_NUMBER_OF_VFS_PER_PF_OFFSET 0
4882 #define NVM_CFG1_FUNC_RESERVESD12_MASK 0x00003F80
4883 #define NVM_CFG1_FUNC_RESERVESD12_OFFSET 7
4884 #define NVM_CFG1_FUNC_BAR1_SIZE_MASK 0x0003C000
4885 #define NVM_CFG1_FUNC_BAR1_SIZE_OFFSET 14
4886 #define NVM_CFG1_FUNC_BAR1_SIZE_DISABLED 0x0
4887 #define NVM_CFG1_FUNC_BAR1_SIZE_64K 0x1
4888 #define NVM_CFG1_FUNC_BAR1_SIZE_128K 0x2
4889 #define NVM_CFG1_FUNC_BAR1_SIZE_256K 0x3
4890 #define NVM_CFG1_FUNC_BAR1_SIZE_512K 0x4
4891 #define NVM_CFG1_FUNC_BAR1_SIZE_1M 0x5
4892 #define NVM_CFG1_FUNC_BAR1_SIZE_2M 0x6
4893 #define NVM_CFG1_FUNC_BAR1_SIZE_4M 0x7
4894 #define NVM_CFG1_FUNC_BAR1_SIZE_8M 0x8
4895 #define NVM_CFG1_FUNC_BAR1_SIZE_16M 0x9
4896 #define NVM_CFG1_FUNC_BAR1_SIZE_32M 0xA
4897 #define NVM_CFG1_FUNC_BAR1_SIZE_64M 0xB
4898 #define NVM_CFG1_FUNC_BAR1_SIZE_128M 0xC
4899 #define NVM_CFG1_FUNC_BAR1_SIZE_256M 0xD
4900 #define NVM_CFG1_FUNC_BAR1_SIZE_512M 0xE
4901 #define NVM_CFG1_FUNC_BAR1_SIZE_1G 0xF
4902 #define NVM_CFG1_FUNC_MAX_BANDWIDTH_MASK 0x03FC0000
4903 #define NVM_CFG1_FUNC_MAX_BANDWIDTH_OFFSET 18
4905 struct nvm_cfg_mac_address fcoe_node_wwn_mac_addr; /* 0x1C */
4907 struct nvm_cfg_mac_address fcoe_port_wwn_mac_addr; /* 0x24 */
4908 u32 preboot_generic_cfg; /* 0x2C */
4909 u32 reserved[8]; /* 0x30 */
4913 struct nvm_cfg1_glob glob; /* 0x0 */
4915 struct nvm_cfg1_path path[MCP_GLOB_PATH_MAX]; /* 0x140 */
4917 struct nvm_cfg1_port port[MCP_GLOB_PORT_MAX]; /* 0x230 */
4919 struct nvm_cfg1_func func[MCP_GLOB_FUNC_MAX]; /* 0xB90 */
4922 /******************************************
4924 ******************************************/
4926 enum nvm_cfg_sections {
4927 NVM_CFG_SECTION_NVM_CFG1,
4933 u32 sections_offset[NVM_CFG_SECTION_MAX];
4934 struct nvm_cfg1 cfg1;
4942 extern struct spad_layout g_spad;
4944 #define MCP_SPAD_SIZE 0x00028000 /* 160 KB */
4946 #define SPAD_OFFSET(addr) (((u32)addr - (u32)CPU_SPAD_BASE))
4948 #define TO_OFFSIZE(_offset, _size) \
4949 (u32)((((u32)(_offset) >> 2) << OFFSIZE_OFFSET_SHIFT) | \
4950 (((u32)(_size) >> 2) << OFFSIZE_SIZE_SHIFT))
4952 enum spad_sections {
4954 SPAD_SECTION_NVM_CFG,
4955 SPAD_SECTION_PUBLIC,
4956 SPAD_SECTION_PRIVATE,
4960 struct spad_layout {
4961 struct nvm_cfg nvm_cfg;
4962 struct mcp_public_data public_data;
4965 #define CRC_MAGIC_VALUE 0xDEBB20E3
4966 #define CRC32_POLYNOMIAL 0xEDB88320
4967 #define NVM_CRC_SIZE (sizeof(u32))
4969 enum nvm_sw_arbitrator {
4976 /****************************************************************************
4977 * Boot Strap Region *
4978 ****************************************************************************/
4979 struct legacy_bootstrap_region {
4981 #define NVM_MAGIC_VALUE 0x669955aa
4982 u32 sram_start_addr;
4983 u32 code_len; /* boot code length (in dwords) */
4984 u32 code_start_addr;
4985 u32 crc; /* 32-bit CRC */
4988 /****************************************************************************
4989 * Directories Region *
4990 ****************************************************************************/
4991 struct nvm_code_entry {
4992 u32 image_type; /* Image type */
4993 u32 nvm_start_addr; /* NVM address of the image */
4994 u32 len; /* Include CRC */
4995 u32 sram_start_addr;
4996 u32 sram_run_addr; /* Relevant in case of MIM only */
4999 enum nvm_image_type {
5000 NVM_TYPE_TIM1 = 0x01,
5001 NVM_TYPE_TIM2 = 0x02,
5002 NVM_TYPE_MIM1 = 0x03,
5003 NVM_TYPE_MIM2 = 0x04,
5004 NVM_TYPE_MBA = 0x05,
5005 NVM_TYPE_MODULES_PN = 0x06,
5006 NVM_TYPE_VPD = 0x07,
5007 NVM_TYPE_MFW_TRACE1 = 0x08,
5008 NVM_TYPE_MFW_TRACE2 = 0x09,
5009 NVM_TYPE_NVM_CFG1 = 0x0a,
5010 NVM_TYPE_L2B = 0x0b,
5011 NVM_TYPE_DIR1 = 0x0c,
5012 NVM_TYPE_EAGLE_FW1 = 0x0d,
5013 NVM_TYPE_FALCON_FW1 = 0x0e,
5014 NVM_TYPE_PCIE_FW1 = 0x0f,
5015 NVM_TYPE_HW_SET = 0x10,
5016 NVM_TYPE_LIM = 0x11,
5017 NVM_TYPE_AVS_FW1 = 0x12,
5018 NVM_TYPE_DIR2 = 0x13,
5019 NVM_TYPE_CCM = 0x14,
5020 NVM_TYPE_EAGLE_FW2 = 0x15,
5021 NVM_TYPE_FALCON_FW2 = 0x16,
5022 NVM_TYPE_PCIE_FW2 = 0x17,
5023 NVM_TYPE_AVS_FW2 = 0x18,
5028 #define MAX_NVM_DIR_ENTRIES 200
5032 #define NVM_DIR_NEXT_MFW_MASK 0x00000001
5033 #define NVM_DIR_SEQ_MASK 0xfffffffe
5034 #define NVM_DIR_NEXT_MFW(seq) ((seq) & NVM_DIR_NEXT_MFW_MASK)
5036 #define IS_DIR_SEQ_VALID(seq) ((seq & NVM_DIR_SEQ_MASK) != NVM_DIR_SEQ_MASK)
5040 struct nvm_code_entry code[1]; /* Up to MAX_NVM_DIR_ENTRIES */
5043 #define NVM_DIR_SIZE(_num_images) (sizeof(struct nvm_dir) + \
5045 1) * sizeof(struct nvm_code_entry) + \
5048 struct nvm_vpd_image {
5049 u32 format_revision;
5050 #define VPD_IMAGE_VERSION 1
5052 /* This array length depends on the number of VPD fields */
5056 /****************************************************************************
5058 ****************************************************************************/
5059 #define DIR_ID_1 (0)
5060 #define DIR_ID_2 (1)
5061 #define MAX_DIR_IDS (2)
5063 #define MFW_BUNDLE_1 (0)
5064 #define MFW_BUNDLE_2 (1)
5065 #define MAX_MFW_BUNDLES (2)
5067 #define FLASH_PAGE_SIZE 0x1000
5068 #define NVM_DIR_MAX_SIZE (FLASH_PAGE_SIZE) /* 4Kb */
5069 #define ASIC_MIM_MAX_SIZE (300 * FLASH_PAGE_SIZE) /* 1.2Mb */
5070 #define FPGA_MIM_MAX_SIZE (25 * FLASH_PAGE_SIZE) /* 60Kb */
5072 #define LIM_MAX_SIZE ((2 * \
5073 FLASH_PAGE_SIZE) - \
5074 sizeof(struct legacy_bootstrap_region) - \
5076 #define LIM_OFFSET (NVM_OFFSET(lim_image))
5077 #define NVM_RSV_SIZE (44)
5078 #define MIM_MAX_SIZE(is_asic) ((is_asic) ? ASIC_MIM_MAX_SIZE : \
5080 #define MIM_OFFSET(idx, is_asic) (NVM_OFFSET(dir[MAX_MFW_BUNDLES]) + \
5082 NVM_TYPE_MIM2) ? MIM_MAX_SIZE(is_asic) : 0))
5083 #define NVM_FIXED_AREA_SIZE(is_asic) (sizeof(struct nvm_image) + \
5084 MIM_MAX_SIZE(is_asic) * 2)
5086 union nvm_dir_union {
5088 u8 page[FLASH_PAGE_SIZE];
5092 * +-------------------+ 0x000000
5095 * | sram_start_addr |
5097 * | code_start_addr |
5099 * +-------------------+ 0x000014
5101 * +-------------------+ 0x000040
5103 * +-------------------+ 0x002000
5105 * +-------------------+ 0x003000
5107 * +-------------------+ 0x004000
5109 * +-------------------+ 0x130000
5111 * +-------------------+ 0x25C000
5115 * | Eagle/Falcon FW |
5121 * +-------------------+ 0x400000
5124 /*********** !!! FIXED SECTIONS !!! DO NOT MODIFY !!! **********************/
5125 /* NVM Offset (size) */
5126 struct legacy_bootstrap_region bootstrap;
5127 u8 rsrv[NVM_RSV_SIZE];
5128 u8 lim_image[LIM_MAX_SIZE];
5129 union nvm_dir_union dir[MAX_MFW_BUNDLES];
5131 /* MIM1_IMAGE 0x004000 (0x12c000) */
5132 /* MIM2_IMAGE 0x130000 (0x12c000) */
5133 /*********** !!! FIXED SECTIONS !!! DO NOT MODIFY !!! **********************/
5136 #define NVM_OFFSET(f) ((u32_t)((int_ptr_t)(&(((struct nvm_image *)0)->f))))
5138 struct hw_set_info {
5140 #define GRC_REG_TYPE 1
5141 #define PHY_REG_TYPE 2
5142 #define PCI_REG_TYPE 4
5149 #define RMW_SET_OP 3
5150 #define RMW_CLR_OP 4
5156 #define POR_RESET_TYPE BIT(0)
5157 #define HARD_RESET_TYPE BIT(1)
5158 #define CORE_RESET_TYPE BIT(2)
5159 #define MCP_RESET_TYPE BIT(3)
5160 #define PERSET_ASSERT BIT(4)
5161 #define PERSET_DEASSERT BIT(5)
5164 struct hw_set_image {
5166 #define HW_SET_IMAGE_VERSION 1
5169 /* This array length depends on the no_hw_sets */
5170 struct hw_set_info hw_sets[1];
5173 int qed_init_pf_wfq(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
5174 u8 pf_id, u16 pf_wfq);
5175 int qed_init_vport_wfq(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
5176 u16 first_tx_pq_id[NUM_OF_TCS], u16 vport_wfq);