drivers/net/ethernet/qlogic/qed/qed_dev.c

   1 /* QLogic qed NIC Driver
   2  * Copyright (c) 2015-2017  QLogic Corporation
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and /or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/types.h>
  34 #include <asm/byteorder.h>
  35 #include <linux/io.h>
  36 #include <linux/delay.h>
  37 #include <linux/dma-mapping.h>
  38 #include <linux/errno.h>
  39 #include <linux/kernel.h>
  40 #include <linux/mutex.h>
  41 #include <linux/pci.h>
  42 #include <linux/slab.h>
  43 #include <linux/string.h>
  44 #include <linux/vmalloc.h>
  45 #include <linux/etherdevice.h>
  46 #include <linux/qed/qed_chain.h>
  47 #include <linux/qed/qed_if.h>
  48 #include "qed.h"
  49 #include "qed_cxt.h"
  50 #include "qed_dcbx.h"
  51 #include "qed_dev_api.h"
  52 #include "qed_fcoe.h"
  53 #include "qed_hsi.h"
  54 #include "qed_hw.h"
  55 #include "qed_init_ops.h"
  56 #include "qed_int.h"
  57 #include "qed_iscsi.h"
  58 #include "qed_ll2.h"
  59 #include "qed_mcp.h"
  60 #include "qed_ooo.h"
  61 #include "qed_reg_addr.h"
  62 #include "qed_sp.h"
  63 #include "qed_sriov.h"
  64 #include "qed_vf.h"
  65 #include "qed_rdma.h"
  66
  67 static DEFINE_SPINLOCK(qm_lock);
  68
  69 /******************** Doorbell Recovery *******************/
  70 /* The doorbell recovery mechanism consists of a list of entries which represent
  71  * doorbelling entities (l2 queues, roce sq/rq/cqs, the slowpath spq, etc). Each
  72  * entity needs to register with the mechanism and provide the parameters
  73  * describing it's doorbell, including a location where last used doorbell data
  74  * can be found. The doorbell execute function will traverse the list and
  75  * doorbell all of the registered entries.
  76  */
  77 struct qed_db_recovery_entry {
  78         struct list_head list_entry;
  79         void __iomem *db_addr;
  80         void *db_data;
  81         enum qed_db_rec_width db_width;
  82         enum qed_db_rec_space db_space;
  83         u8 hwfn_idx;
  84 };
  85
  86 /* Display a single doorbell recovery entry */
  87 static void qed_db_recovery_dp_entry(struct qed_hwfn *p_hwfn,
  88                                      struct qed_db_recovery_entry *db_entry,
  89                                      char *action)
  90 {
  91         DP_VERBOSE(p_hwfn,
  92                    QED_MSG_SPQ,
  93                    "(%s: db_entry %p, addr %p, data %p, width %s, %s space, hwfn %d)\n",
  94                    action,
  95                    db_entry,
  96                    db_entry->db_addr,
  97                    db_entry->db_data,
  98                    db_entry->db_width == DB_REC_WIDTH_32B ? "32b" : "64b",
  99                    db_entry->db_space == DB_REC_USER ? "user" : "kernel",
 100                    db_entry->hwfn_idx);
 101 }
 102
 103 /* Doorbell address sanity (address within doorbell bar range) */
 104 static bool qed_db_rec_sanity(struct qed_dev *cdev,
 105                               void __iomem *db_addr, void *db_data)
 106 {
 107         /* Make sure doorbell address is within the doorbell bar */
 108         if (db_addr < cdev->doorbells ||
 109             (u8 __iomem *)db_addr >
 110             (u8 __iomem *)cdev->doorbells + cdev->db_size) {
 111                 WARN(true,
 112                      "Illegal doorbell address: %p. Legal range for doorbell addresses is [%p..%p]\n",
 113                      db_addr,
 114                      cdev->doorbells,
 115                      (u8 __iomem *)cdev->doorbells + cdev->db_size);
 116                 return false;
 117         }
 118
 119         /* ake sure doorbell data pointer is not null */
 120         if (!db_data) {
 121                 WARN(true, "Illegal doorbell data pointer: %p", db_data);
 122                 return false;
 123         }
 124
 125         return true;
 126 }
 127
 128 /* Find hwfn according to the doorbell address */
 129 static struct qed_hwfn *qed_db_rec_find_hwfn(struct qed_dev *cdev,
 130                                              void __iomem *db_addr)
 131 {
 132         struct qed_hwfn *p_hwfn;
 133
 134         /* In CMT doorbell bar is split down the middle between engine 0 and enigne 1 */
 135         if (cdev->num_hwfns > 1)
 136                 p_hwfn = db_addr < cdev->hwfns[1].doorbells ?
 137                     &cdev->hwfns[0] : &cdev->hwfns[1];
 138         else
 139                 p_hwfn = QED_LEADING_HWFN(cdev);
 140
 141         return p_hwfn;
 142 }
 143
 144 /* Add a new entry to the doorbell recovery mechanism */
 145 int qed_db_recovery_add(struct qed_dev *cdev,
 146                         void __iomem *db_addr,
 147                         void *db_data,
 148                         enum qed_db_rec_width db_width,
 149                         enum qed_db_rec_space db_space)
 150 {
 151         struct qed_db_recovery_entry *db_entry;
 152         struct qed_hwfn *p_hwfn;
 153
 154         /* Shortcircuit VFs, for now */
 155         if (IS_VF(cdev)) {
 156                 DP_VERBOSE(cdev,
 157                            QED_MSG_IOV, "db recovery - skipping VF doorbell\n");
 158                 return 0;
 159         }
 160
 161         /* Sanitize doorbell address */
 162         if (!qed_db_rec_sanity(cdev, db_addr, db_data))
 163                 return -EINVAL;
 164
 165         /* Obtain hwfn from doorbell address */
 166         p_hwfn = qed_db_rec_find_hwfn(cdev, db_addr);
 167
 168         /* Create entry */
 169         db_entry = kzalloc(sizeof(*db_entry), GFP_KERNEL);
 170         if (!db_entry) {
 171                 DP_NOTICE(cdev, "Failed to allocate a db recovery entry\n");
 172                 return -ENOMEM;
 173         }
 174
 175         /* Populate entry */
 176         db_entry->db_addr = db_addr;
 177         db_entry->db_data = db_data;
 178         db_entry->db_width = db_width;
 179         db_entry->db_space = db_space;
 180         db_entry->hwfn_idx = p_hwfn->my_id;
 181
 182         /* Display */
 183         qed_db_recovery_dp_entry(p_hwfn, db_entry, "Adding");
 184
 185         /* Protect the list */
 186         spin_lock_bh(&p_hwfn->db_recovery_info.lock);
 187         list_add_tail(&db_entry->list_entry, &p_hwfn->db_recovery_info.list);
 188         spin_unlock_bh(&p_hwfn->db_recovery_info.lock);
 189
 190         return 0;
 191 }
 192
 193 /* Remove an entry from the doorbell recovery mechanism */
 194 int qed_db_recovery_del(struct qed_dev *cdev,
 195                         void __iomem *db_addr, void *db_data)
 196 {
 197         struct qed_db_recovery_entry *db_entry = NULL;
 198         struct qed_hwfn *p_hwfn;
 199         int rc = -EINVAL;
 200
 201         /* Shortcircuit VFs, for now */
 202         if (IS_VF(cdev)) {
 203                 DP_VERBOSE(cdev,
 204                            QED_MSG_IOV, "db recovery - skipping VF doorbell\n");
 205                 return 0;
 206         }
 207
 208         /* Sanitize doorbell address */
 209         if (!qed_db_rec_sanity(cdev, db_addr, db_data))
 210                 return -EINVAL;
 211
 212         /* Obtain hwfn from doorbell address */
 213         p_hwfn = qed_db_rec_find_hwfn(cdev, db_addr);
 214
 215         /* Protect the list */
 216         spin_lock_bh(&p_hwfn->db_recovery_info.lock);
 217         list_for_each_entry(db_entry,
 218                             &p_hwfn->db_recovery_info.list, list_entry) {
 219                 /* search according to db_data addr since db_addr is not unique (roce) */
 220                 if (db_entry->db_data == db_data) {
 221                         qed_db_recovery_dp_entry(p_hwfn, db_entry, "Deleting");
 222                         list_del(&db_entry->list_entry);
 223                         rc = 0;
 224                         break;
 225                 }
 226         }
 227
 228         spin_unlock_bh(&p_hwfn->db_recovery_info.lock);
 229
 230         if (rc == -EINVAL)
 231
 232                 DP_NOTICE(p_hwfn,
 233                           "Failed to find element in list. Key (db_data addr) was %p. db_addr was %p\n",
 234                           db_data, db_addr);
 235         else
 236                 kfree(db_entry);
 237
 238         return rc;
 239 }
 240
 241 /* Initialize the doorbell recovery mechanism */
 242 static int qed_db_recovery_setup(struct qed_hwfn *p_hwfn)
 243 {
 244         DP_VERBOSE(p_hwfn, QED_MSG_SPQ, "Setting up db recovery\n");
 245
 246         /* Make sure db_size was set in cdev */
 247         if (!p_hwfn->cdev->db_size) {
 248                 DP_ERR(p_hwfn->cdev, "db_size not set\n");
 249                 return -EINVAL;
 250         }
 251
 252         INIT_LIST_HEAD(&p_hwfn->db_recovery_info.list);
 253         spin_lock_init(&p_hwfn->db_recovery_info.lock);
 254         p_hwfn->db_recovery_info.db_recovery_counter = 0;
 255
 256         return 0;
 257 }
 258
 259 /* Destroy the doorbell recovery mechanism */
 260 static void qed_db_recovery_teardown(struct qed_hwfn *p_hwfn)
 261 {
 262         struct qed_db_recovery_entry *db_entry = NULL;
 263
 264         DP_VERBOSE(p_hwfn, QED_MSG_SPQ, "Tearing down db recovery\n");
 265         if (!list_empty(&p_hwfn->db_recovery_info.list)) {
 266                 DP_VERBOSE(p_hwfn,
 267                            QED_MSG_SPQ,
 268                            "Doorbell Recovery teardown found the doorbell recovery list was not empty (Expected in disorderly driver unload (e.g. recovery) otherwise this probably means some flow forgot to db_recovery_del). Prepare to purge doorbell recovery list...\n");
 269                 while (!list_empty(&p_hwfn->db_recovery_info.list)) {
 270                         db_entry =
 271                             list_first_entry(&p_hwfn->db_recovery_info.list,
 272                                              struct qed_db_recovery_entry,
 273                                              list_entry);
 274                         qed_db_recovery_dp_entry(p_hwfn, db_entry, "Purging");
 275                         list_del(&db_entry->list_entry);
 276                         kfree(db_entry);
 277                 }
 278         }
 279         p_hwfn->db_recovery_info.db_recovery_counter = 0;
 280 }
 281
 282 /* Print the content of the doorbell recovery mechanism */
 283 void qed_db_recovery_dp(struct qed_hwfn *p_hwfn)
 284 {
 285         struct qed_db_recovery_entry *db_entry = NULL;
 286
 287         DP_NOTICE(p_hwfn,
 288                   "Displaying doorbell recovery database. Counter was %d\n",
 289                   p_hwfn->db_recovery_info.db_recovery_counter);
 290
 291         /* Protect the list */
 292         spin_lock_bh(&p_hwfn->db_recovery_info.lock);
 293         list_for_each_entry(db_entry,
 294                             &p_hwfn->db_recovery_info.list, list_entry) {
 295                 qed_db_recovery_dp_entry(p_hwfn, db_entry, "Printing");
 296         }
 297
 298         spin_unlock_bh(&p_hwfn->db_recovery_info.lock);
 299 }
 300
 301 /* Ring the doorbell of a single doorbell recovery entry */
 302 static void qed_db_recovery_ring(struct qed_hwfn *p_hwfn,
 303                                  struct qed_db_recovery_entry *db_entry,
 304                                  enum qed_db_rec_exec db_exec)
 305 {
 306         if (db_exec != DB_REC_ONCE) {
 307                 /* Print according to width */
 308                 if (db_entry->db_width == DB_REC_WIDTH_32B) {
 309                         DP_VERBOSE(p_hwfn, QED_MSG_SPQ,
 310                                    "%s doorbell address %p data %x\n",
 311                                    db_exec == DB_REC_DRY_RUN ?
 312                                    "would have rung" : "ringing",
 313                                    db_entry->db_addr,
 314                                    *(u32 *)db_entry->db_data);
 315                 } else {
 316                         DP_VERBOSE(p_hwfn, QED_MSG_SPQ,
 317                                    "%s doorbell address %p data %llx\n",
 318                                    db_exec == DB_REC_DRY_RUN ?
 319                                    "would have rung" : "ringing",
 320                                    db_entry->db_addr,
 321                                    *(u64 *)(db_entry->db_data));
 322                 }
 323         }
 324
 325         /* Sanity */
 326         if (!qed_db_rec_sanity(p_hwfn->cdev, db_entry->db_addr,
 327                                db_entry->db_data))
 328                 return;
 329
 330         /* Flush the write combined buffer. Since there are multiple doorbelling
 331          * entities using the same address, if we don't flush, a transaction
 332          * could be lost.
 333          */
 334         wmb();
 335
 336         /* Ring the doorbell */
 337         if (db_exec == DB_REC_REAL_DEAL || db_exec == DB_REC_ONCE) {
 338                 if (db_entry->db_width == DB_REC_WIDTH_32B)
 339                         DIRECT_REG_WR(db_entry->db_addr,
 340                                       *(u32 *)(db_entry->db_data));
 341                 else
 342                         DIRECT_REG_WR64(db_entry->db_addr,
 343                                         *(u64 *)(db_entry->db_data));
 344         }
 345
 346         /* Flush the write combined buffer. Next doorbell may come from a
 347          * different entity to the same address...
 348          */
 349         wmb();
 350 }
 351
 352 /* Traverse the doorbell recovery entry list and ring all the doorbells */
 353 void qed_db_recovery_execute(struct qed_hwfn *p_hwfn,
 354                              enum qed_db_rec_exec db_exec)
 355 {
 356         struct qed_db_recovery_entry *db_entry = NULL;
 357
 358         if (db_exec != DB_REC_ONCE) {
 359                 DP_NOTICE(p_hwfn,
 360                           "Executing doorbell recovery. Counter was %d\n",
 361                           p_hwfn->db_recovery_info.db_recovery_counter);
 362
 363                 /* Track amount of times recovery was executed */
 364                 p_hwfn->db_recovery_info.db_recovery_counter++;
 365         }
 366
 367         /* Protect the list */
 368         spin_lock_bh(&p_hwfn->db_recovery_info.lock);
 369         list_for_each_entry(db_entry,
 370                             &p_hwfn->db_recovery_info.list, list_entry) {
 371                 qed_db_recovery_ring(p_hwfn, db_entry, db_exec);
 372                 if (db_exec == DB_REC_ONCE)
 373                         break;
 374         }
 375
 376         spin_unlock_bh(&p_hwfn->db_recovery_info.lock);
 377 }
 378
 379 /******************** Doorbell Recovery end ****************/
 380
 381 #define QED_MIN_DPIS            (4)
 382 #define QED_MIN_PWM_REGION      (QED_WID_SIZE * QED_MIN_DPIS)
 383
 384 static u32 qed_hw_bar_size(struct qed_hwfn *p_hwfn,
 385                            struct qed_ptt *p_ptt, enum BAR_ID bar_id)
 386 {
 387         u32 bar_reg = (bar_id == BAR_ID_0 ?
 388                        PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
 389         u32 val;
 390
 391         if (IS_VF(p_hwfn->cdev))
 392                 return qed_vf_hw_bar_size(p_hwfn, bar_id);
 393
 394         val = qed_rd(p_hwfn, p_ptt, bar_reg);
 395         if (val)
 396                 return 1 << (val + 15);
 397
 398         /* Old MFW initialized above registered only conditionally */
 399         if (p_hwfn->cdev->num_hwfns > 1) {
 400                 DP_INFO(p_hwfn,
 401                         "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n");
 402                         return BAR_ID_0 ? 256 * 1024 : 512 * 1024;
 403         } else {
 404                 DP_INFO(p_hwfn,
 405                         "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n");
 406                         return 512 * 1024;
 407         }
 408 }
 409
 410 void qed_init_dp(struct qed_dev *cdev, u32 dp_module, u8 dp_level)
 411 {
 412         u32 i;
 413
 414         cdev->dp_level = dp_level;
 415         cdev->dp_module = dp_module;
 416         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
 417                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 418
 419                 p_hwfn->dp_level = dp_level;
 420                 p_hwfn->dp_module = dp_module;
 421         }
 422 }
 423
 424 void qed_init_struct(struct qed_dev *cdev)
 425 {
 426         u8 i;
 427
 428         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
 429                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 430
 431                 p_hwfn->cdev = cdev;
 432                 p_hwfn->my_id = i;
 433                 p_hwfn->b_active = false;
 434
 435                 mutex_init(&p_hwfn->dmae_info.mutex);
 436         }
 437
 438         /* hwfn 0 is always active */
 439         cdev->hwfns[0].b_active = true;
 440
 441         /* set the default cache alignment to 128 */
 442         cdev->cache_shift = 7;
 443 }
 444
 445 static void qed_qm_info_free(struct qed_hwfn *p_hwfn)
 446 {
 447         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 448
 449         kfree(qm_info->qm_pq_params);
 450         qm_info->qm_pq_params = NULL;
 451         kfree(qm_info->qm_vport_params);
 452         qm_info->qm_vport_params = NULL;
 453         kfree(qm_info->qm_port_params);
 454         qm_info->qm_port_params = NULL;
 455         kfree(qm_info->wfq_data);
 456         qm_info->wfq_data = NULL;
 457 }
 458
 459 static void qed_dbg_user_data_free(struct qed_hwfn *p_hwfn)
 460 {
 461         kfree(p_hwfn->dbg_user_info);
 462         p_hwfn->dbg_user_info = NULL;
 463 }
 464
 465 void qed_resc_free(struct qed_dev *cdev)
 466 {
 467         int i;
 468
 469         if (IS_VF(cdev)) {
 470                 for_each_hwfn(cdev, i)
 471                         qed_l2_free(&cdev->hwfns[i]);
 472                 return;
 473         }
 474
 475         kfree(cdev->fw_data);
 476         cdev->fw_data = NULL;
 477
 478         kfree(cdev->reset_stats);
 479         cdev->reset_stats = NULL;
 480
 481         for_each_hwfn(cdev, i) {
 482                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 483
 484                 qed_cxt_mngr_free(p_hwfn);
 485                 qed_qm_info_free(p_hwfn);
 486                 qed_spq_free(p_hwfn);
 487                 qed_eq_free(p_hwfn);
 488                 qed_consq_free(p_hwfn);
 489                 qed_int_free(p_hwfn);
 490 #ifdef CONFIG_QED_LL2
 491                 qed_ll2_free(p_hwfn);
 492 #endif
 493                 if (p_hwfn->hw_info.personality == QED_PCI_FCOE)
 494                         qed_fcoe_free(p_hwfn);
 495
 496                 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
 497                         qed_iscsi_free(p_hwfn);
 498                         qed_ooo_free(p_hwfn);
 499                 }
 500
 501                 if (QED_IS_RDMA_PERSONALITY(p_hwfn))
 502                         qed_rdma_info_free(p_hwfn);
 503
 504                 qed_iov_free(p_hwfn);
 505                 qed_l2_free(p_hwfn);
 506                 qed_dmae_info_free(p_hwfn);
 507                 qed_dcbx_info_free(p_hwfn);
 508                 qed_dbg_user_data_free(p_hwfn);
 509
 510                 /* Destroy doorbell recovery mechanism */
 511                 qed_db_recovery_teardown(p_hwfn);
 512         }
 513 }
 514
 515 /******************** QM initialization *******************/
 516 #define ACTIVE_TCS_BMAP 0x9f
 517 #define ACTIVE_TCS_BMAP_4PORT_K2 0xf
 518
 519 /* determines the physical queue flags for a given PF. */
 520 static u32 qed_get_pq_flags(struct qed_hwfn *p_hwfn)
 521 {
 522         u32 flags;
 523
 524         /* common flags */
 525         flags = PQ_FLAGS_LB;
 526
 527         /* feature flags */
 528         if (IS_QED_SRIOV(p_hwfn->cdev))
 529                 flags |= PQ_FLAGS_VFS;
 530
 531         /* protocol flags */
 532         switch (p_hwfn->hw_info.personality) {
 533         case QED_PCI_ETH:
 534                 flags |= PQ_FLAGS_MCOS;
 535                 break;
 536         case QED_PCI_FCOE:
 537                 flags |= PQ_FLAGS_OFLD;
 538                 break;
 539         case QED_PCI_ISCSI:
 540                 flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD;
 541                 break;
 542         case QED_PCI_ETH_ROCE:
 543                 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_OFLD | PQ_FLAGS_LLT;
 544                 if (IS_QED_MULTI_TC_ROCE(p_hwfn))
 545                         flags |= PQ_FLAGS_MTC;
 546                 break;
 547         case QED_PCI_ETH_IWARP:
 548                 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_ACK | PQ_FLAGS_OOO |
 549                     PQ_FLAGS_OFLD;
 550                 break;
 551         default:
 552                 DP_ERR(p_hwfn,
 553                        "unknown personality %d\n", p_hwfn->hw_info.personality);
 554                 return 0;
 555         }
 556
 557         return flags;
 558 }
 559
 560 /* Getters for resource amounts necessary for qm initialization */
 561 static u8 qed_init_qm_get_num_tcs(struct qed_hwfn *p_hwfn)
 562 {
 563         return p_hwfn->hw_info.num_hw_tc;
 564 }
 565
 566 static u16 qed_init_qm_get_num_vfs(struct qed_hwfn *p_hwfn)
 567 {
 568         return IS_QED_SRIOV(p_hwfn->cdev) ?
 569                p_hwfn->cdev->p_iov_info->total_vfs : 0;
 570 }
 571
 572 static u8 qed_init_qm_get_num_mtc_tcs(struct qed_hwfn *p_hwfn)
 573 {
 574         u32 pq_flags = qed_get_pq_flags(p_hwfn);
 575
 576         if (!(PQ_FLAGS_MTC & pq_flags))
 577                 return 1;
 578
 579         return qed_init_qm_get_num_tcs(p_hwfn);
 580 }
 581
 582 #define NUM_DEFAULT_RLS 1
 583
 584 static u16 qed_init_qm_get_num_pf_rls(struct qed_hwfn *p_hwfn)
 585 {
 586         u16 num_pf_rls, num_vfs = qed_init_qm_get_num_vfs(p_hwfn);
 587
 588         /* num RLs can't exceed resource amount of rls or vports */
 589         num_pf_rls = (u16) min_t(u32, RESC_NUM(p_hwfn, QED_RL),
 590                                  RESC_NUM(p_hwfn, QED_VPORT));
 591
 592         /* Make sure after we reserve there's something left */
 593         if (num_pf_rls < num_vfs + NUM_DEFAULT_RLS)
 594                 return 0;
 595
 596         /* subtract rls necessary for VFs and one default one for the PF */
 597         num_pf_rls -= num_vfs + NUM_DEFAULT_RLS;
 598
 599         return num_pf_rls;
 600 }
 601
 602 static u16 qed_init_qm_get_num_vports(struct qed_hwfn *p_hwfn)
 603 {
 604         u32 pq_flags = qed_get_pq_flags(p_hwfn);
 605
 606         /* all pqs share the same vport, except for vfs and pf_rl pqs */
 607         return (!!(PQ_FLAGS_RLS & pq_flags)) *
 608                qed_init_qm_get_num_pf_rls(p_hwfn) +
 609                (!!(PQ_FLAGS_VFS & pq_flags)) *
 610                qed_init_qm_get_num_vfs(p_hwfn) + 1;
 611 }
 612
 613 /* calc amount of PQs according to the requested flags */
 614 static u16 qed_init_qm_get_num_pqs(struct qed_hwfn *p_hwfn)
 615 {
 616         u32 pq_flags = qed_get_pq_flags(p_hwfn);
 617
 618         return (!!(PQ_FLAGS_RLS & pq_flags)) *
 619                qed_init_qm_get_num_pf_rls(p_hwfn) +
 620                (!!(PQ_FLAGS_MCOS & pq_flags)) *
 621                qed_init_qm_get_num_tcs(p_hwfn) +
 622                (!!(PQ_FLAGS_LB & pq_flags)) + (!!(PQ_FLAGS_OOO & pq_flags)) +
 623                (!!(PQ_FLAGS_ACK & pq_flags)) +
 624                (!!(PQ_FLAGS_OFLD & pq_flags)) *
 625                qed_init_qm_get_num_mtc_tcs(p_hwfn) +
 626                (!!(PQ_FLAGS_LLT & pq_flags)) *
 627                qed_init_qm_get_num_mtc_tcs(p_hwfn) +
 628                (!!(PQ_FLAGS_VFS & pq_flags)) * qed_init_qm_get_num_vfs(p_hwfn);
 629 }
 630
 631 /* initialize the top level QM params */
 632 static void qed_init_qm_params(struct qed_hwfn *p_hwfn)
 633 {
 634         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 635         bool four_port;
 636
 637         /* pq and vport bases for this PF */
 638         qm_info->start_pq = (u16) RESC_START(p_hwfn, QED_PQ);
 639         qm_info->start_vport = (u8) RESC_START(p_hwfn, QED_VPORT);
 640
 641         /* rate limiting and weighted fair queueing are always enabled */
 642         qm_info->vport_rl_en = true;
 643         qm_info->vport_wfq_en = true;
 644
 645         /* TC config is different for AH 4 port */
 646         four_port = p_hwfn->cdev->num_ports_in_engine == MAX_NUM_PORTS_K2;
 647
 648         /* in AH 4 port we have fewer TCs per port */
 649         qm_info->max_phys_tcs_per_port = four_port ? NUM_PHYS_TCS_4PORT_K2 :
 650                                                      NUM_OF_PHYS_TCS;
 651
 652         /* unless MFW indicated otherwise, ooo_tc == 3 for
 653          * AH 4-port and 4 otherwise.
 654          */
 655         if (!qm_info->ooo_tc)
 656                 qm_info->ooo_tc = four_port ? DCBX_TCP_OOO_K2_4PORT_TC :
 657                                               DCBX_TCP_OOO_TC;
 658 }
 659
 660 /* initialize qm vport params */
 661 static void qed_init_qm_vport_params(struct qed_hwfn *p_hwfn)
 662 {
 663         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 664         u8 i;
 665
 666         /* all vports participate in weighted fair queueing */
 667         for (i = 0; i < qed_init_qm_get_num_vports(p_hwfn); i++)
 668                 qm_info->qm_vport_params[i].vport_wfq = 1;
 669 }
 670
 671 /* initialize qm port params */
 672 static void qed_init_qm_port_params(struct qed_hwfn *p_hwfn)
 673 {
 674         /* Initialize qm port parameters */
 675         u8 i, active_phys_tcs, num_ports = p_hwfn->cdev->num_ports_in_engine;
 676
 677         /* indicate how ooo and high pri traffic is dealt with */
 678         active_phys_tcs = num_ports == MAX_NUM_PORTS_K2 ?
 679                           ACTIVE_TCS_BMAP_4PORT_K2 :
 680                           ACTIVE_TCS_BMAP;
 681
 682         for (i = 0; i < num_ports; i++) {
 683                 struct init_qm_port_params *p_qm_port =
 684                     &p_hwfn->qm_info.qm_port_params[i];
 685
 686                 p_qm_port->active = 1;
 687                 p_qm_port->active_phys_tcs = active_phys_tcs;
 688                 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports;
 689                 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
 690         }
 691 }
 692
 693 /* Reset the params which must be reset for qm init. QM init may be called as
 694  * a result of flows other than driver load (e.g. dcbx renegotiation). Other
 695  * params may be affected by the init but would simply recalculate to the same
 696  * values. The allocations made for QM init, ports, vports, pqs and vfqs are not
 697  * affected as these amounts stay the same.
 698  */
 699 static void qed_init_qm_reset_params(struct qed_hwfn *p_hwfn)
 700 {
 701         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 702
 703         qm_info->num_pqs = 0;
 704         qm_info->num_vports = 0;
 705         qm_info->num_pf_rls = 0;
 706         qm_info->num_vf_pqs = 0;
 707         qm_info->first_vf_pq = 0;
 708         qm_info->first_mcos_pq = 0;
 709         qm_info->first_rl_pq = 0;
 710 }
 711
 712 static void qed_init_qm_advance_vport(struct qed_hwfn *p_hwfn)
 713 {
 714         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 715
 716         qm_info->num_vports++;
 717
 718         if (qm_info->num_vports > qed_init_qm_get_num_vports(p_hwfn))
 719                 DP_ERR(p_hwfn,
 720                        "vport overflow! qm_info->num_vports %d, qm_init_get_num_vports() %d\n",
 721                        qm_info->num_vports, qed_init_qm_get_num_vports(p_hwfn));
 722 }
 723
 724 /* initialize a single pq and manage qm_info resources accounting.
 725  * The pq_init_flags param determines whether the PQ is rate limited
 726  * (for VF or PF) and whether a new vport is allocated to the pq or not
 727  * (i.e. vport will be shared).
 728  */
 729
 730 /* flags for pq init */
 731 #define PQ_INIT_SHARE_VPORT     (1 << 0)
 732 #define PQ_INIT_PF_RL           (1 << 1)
 733 #define PQ_INIT_VF_RL           (1 << 2)
 734
 735 /* defines for pq init */
 736 #define PQ_INIT_DEFAULT_WRR_GROUP       1
 737 #define PQ_INIT_DEFAULT_TC              0
 738
 739 void qed_hw_info_set_offload_tc(struct qed_hw_info *p_info, u8 tc)
 740 {
 741         p_info->offload_tc = tc;
 742         p_info->offload_tc_set = true;
 743 }
 744
 745 static bool qed_is_offload_tc_set(struct qed_hwfn *p_hwfn)
 746 {
 747         return p_hwfn->hw_info.offload_tc_set;
 748 }
 749
 750 static u32 qed_get_offload_tc(struct qed_hwfn *p_hwfn)
 751 {
 752         if (qed_is_offload_tc_set(p_hwfn))
 753                 return p_hwfn->hw_info.offload_tc;
 754
 755         return PQ_INIT_DEFAULT_TC;
 756 }
 757
 758 static void qed_init_qm_pq(struct qed_hwfn *p_hwfn,
 759                            struct qed_qm_info *qm_info,
 760                            u8 tc, u32 pq_init_flags)
 761 {
 762         u16 pq_idx = qm_info->num_pqs, max_pq = qed_init_qm_get_num_pqs(p_hwfn);
 763
 764         if (pq_idx > max_pq)
 765                 DP_ERR(p_hwfn,
 766                        "pq overflow! pq %d, max pq %d\n", pq_idx, max_pq);
 767
 768         /* init pq params */
 769         qm_info->qm_pq_params[pq_idx].port_id = p_hwfn->port_id;
 770         qm_info->qm_pq_params[pq_idx].vport_id = qm_info->start_vport +
 771             qm_info->num_vports;
 772         qm_info->qm_pq_params[pq_idx].tc_id = tc;
 773         qm_info->qm_pq_params[pq_idx].wrr_group = PQ_INIT_DEFAULT_WRR_GROUP;
 774         qm_info->qm_pq_params[pq_idx].rl_valid =
 775             (pq_init_flags & PQ_INIT_PF_RL || pq_init_flags & PQ_INIT_VF_RL);
 776
 777         /* qm params accounting */
 778         qm_info->num_pqs++;
 779         if (!(pq_init_flags & PQ_INIT_SHARE_VPORT))
 780                 qm_info->num_vports++;
 781
 782         if (pq_init_flags & PQ_INIT_PF_RL)
 783                 qm_info->num_pf_rls++;
 784
 785         if (qm_info->num_vports > qed_init_qm_get_num_vports(p_hwfn))
 786                 DP_ERR(p_hwfn,
 787                        "vport overflow! qm_info->num_vports %d, qm_init_get_num_vports() %d\n",
 788                        qm_info->num_vports, qed_init_qm_get_num_vports(p_hwfn));
 789
 790         if (qm_info->num_pf_rls > qed_init_qm_get_num_pf_rls(p_hwfn))
 791                 DP_ERR(p_hwfn,
 792                        "rl overflow! qm_info->num_pf_rls %d, qm_init_get_num_pf_rls() %d\n",
 793                        qm_info->num_pf_rls, qed_init_qm_get_num_pf_rls(p_hwfn));
 794 }
 795
 796 /* get pq index according to PQ_FLAGS */
 797 static u16 *qed_init_qm_get_idx_from_flags(struct qed_hwfn *p_hwfn,
 798                                            unsigned long pq_flags)
 799 {
 800         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 801
 802         /* Can't have multiple flags set here */
 803         if (bitmap_weight(&pq_flags,
 804                           sizeof(pq_flags) * BITS_PER_BYTE) > 1) {
 805                 DP_ERR(p_hwfn, "requested multiple pq flags 0x%lx\n", pq_flags);
 806                 goto err;
 807         }
 808
 809         if (!(qed_get_pq_flags(p_hwfn) & pq_flags)) {
 810                 DP_ERR(p_hwfn, "pq flag 0x%lx is not set\n", pq_flags);
 811                 goto err;
 812         }
 813
 814         switch (pq_flags) {
 815         case PQ_FLAGS_RLS:
 816                 return &qm_info->first_rl_pq;
 817         case PQ_FLAGS_MCOS:
 818                 return &qm_info->first_mcos_pq;
 819         case PQ_FLAGS_LB:
 820                 return &qm_info->pure_lb_pq;
 821         case PQ_FLAGS_OOO:
 822                 return &qm_info->ooo_pq;
 823         case PQ_FLAGS_ACK:
 824                 return &qm_info->pure_ack_pq;
 825         case PQ_FLAGS_OFLD:
 826                 return &qm_info->first_ofld_pq;
 827         case PQ_FLAGS_LLT:
 828                 return &qm_info->first_llt_pq;
 829         case PQ_FLAGS_VFS:
 830                 return &qm_info->first_vf_pq;
 831         default:
 832                 goto err;
 833         }
 834
 835 err:
 836         return &qm_info->start_pq;
 837 }
 838
 839 /* save pq index in qm info */
 840 static void qed_init_qm_set_idx(struct qed_hwfn *p_hwfn,
 841                                 u32 pq_flags, u16 pq_val)
 842 {
 843         u16 *base_pq_idx = qed_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
 844
 845         *base_pq_idx = p_hwfn->qm_info.start_pq + pq_val;
 846 }
 847
 848 /* get tx pq index, with the PQ TX base already set (ready for context init) */
 849 u16 qed_get_cm_pq_idx(struct qed_hwfn *p_hwfn, u32 pq_flags)
 850 {
 851         u16 *base_pq_idx = qed_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
 852
 853         return *base_pq_idx + CM_TX_PQ_BASE;
 854 }
 855
 856 u16 qed_get_cm_pq_idx_mcos(struct qed_hwfn *p_hwfn, u8 tc)
 857 {
 858         u8 max_tc = qed_init_qm_get_num_tcs(p_hwfn);
 859
 860         if (max_tc == 0) {
 861                 DP_ERR(p_hwfn, "pq with flag 0x%lx do not exist\n",
 862                        PQ_FLAGS_MCOS);
 863                 return p_hwfn->qm_info.start_pq;
 864         }
 865
 866         if (tc > max_tc)
 867                 DP_ERR(p_hwfn, "tc %d must be smaller than %d\n", tc, max_tc);
 868
 869         return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_MCOS) + (tc % max_tc);
 870 }
 871
 872 u16 qed_get_cm_pq_idx_vf(struct qed_hwfn *p_hwfn, u16 vf)
 873 {
 874         u16 max_vf = qed_init_qm_get_num_vfs(p_hwfn);
 875
 876         if (max_vf == 0) {
 877                 DP_ERR(p_hwfn, "pq with flag 0x%lx do not exist\n",
 878                        PQ_FLAGS_VFS);
 879                 return p_hwfn->qm_info.start_pq;
 880         }
 881
 882         if (vf > max_vf)
 883                 DP_ERR(p_hwfn, "vf %d must be smaller than %d\n", vf, max_vf);
 884
 885         return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_VFS) + (vf % max_vf);
 886 }
 887
 888 u16 qed_get_cm_pq_idx_ofld_mtc(struct qed_hwfn *p_hwfn, u8 tc)
 889 {
 890         u16 first_ofld_pq, pq_offset;
 891
 892         first_ofld_pq = qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_OFLD);
 893         pq_offset = (tc < qed_init_qm_get_num_mtc_tcs(p_hwfn)) ?
 894                     tc : PQ_INIT_DEFAULT_TC;
 895
 896         return first_ofld_pq + pq_offset;
 897 }
 898
 899 u16 qed_get_cm_pq_idx_llt_mtc(struct qed_hwfn *p_hwfn, u8 tc)
 900 {
 901         u16 first_llt_pq, pq_offset;
 902
 903         first_llt_pq = qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_LLT);
 904         pq_offset = (tc < qed_init_qm_get_num_mtc_tcs(p_hwfn)) ?
 905                     tc : PQ_INIT_DEFAULT_TC;
 906
 907         return first_llt_pq + pq_offset;
 908 }
 909
 910 /* Functions for creating specific types of pqs */
 911 static void qed_init_qm_lb_pq(struct qed_hwfn *p_hwfn)
 912 {
 913         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 914
 915         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_LB))
 916                 return;
 917
 918         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_LB, qm_info->num_pqs);
 919         qed_init_qm_pq(p_hwfn, qm_info, PURE_LB_TC, PQ_INIT_SHARE_VPORT);
 920 }
 921
 922 static void qed_init_qm_ooo_pq(struct qed_hwfn *p_hwfn)
 923 {
 924         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 925
 926         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_OOO))
 927                 return;
 928
 929         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_OOO, qm_info->num_pqs);
 930         qed_init_qm_pq(p_hwfn, qm_info, qm_info->ooo_tc, PQ_INIT_SHARE_VPORT);
 931 }
 932
 933 static void qed_init_qm_pure_ack_pq(struct qed_hwfn *p_hwfn)
 934 {
 935         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 936
 937         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_ACK))
 938                 return;
 939
 940         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_ACK, qm_info->num_pqs);
 941         qed_init_qm_pq(p_hwfn, qm_info, qed_get_offload_tc(p_hwfn),
 942                        PQ_INIT_SHARE_VPORT);
 943 }
 944
 945 static void qed_init_qm_mtc_pqs(struct qed_hwfn *p_hwfn)
 946 {
 947         u8 num_tcs = qed_init_qm_get_num_mtc_tcs(p_hwfn);
 948         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 949         u8 tc;
 950
 951         /* override pq's TC if offload TC is set */
 952         for (tc = 0; tc < num_tcs; tc++)
 953                 qed_init_qm_pq(p_hwfn, qm_info,
 954                                qed_is_offload_tc_set(p_hwfn) ?
 955                                p_hwfn->hw_info.offload_tc : tc,
 956                                PQ_INIT_SHARE_VPORT);
 957 }
 958
 959 static void qed_init_qm_offload_pq(struct qed_hwfn *p_hwfn)
 960 {
 961         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 962
 963         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_OFLD))
 964                 return;
 965
 966         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_OFLD, qm_info->num_pqs);
 967         qed_init_qm_mtc_pqs(p_hwfn);
 968 }
 969
 970 static void qed_init_qm_low_latency_pq(struct qed_hwfn *p_hwfn)
 971 {
 972         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 973
 974         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_LLT))
 975                 return;
 976
 977         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_LLT, qm_info->num_pqs);
 978         qed_init_qm_mtc_pqs(p_hwfn);
 979 }
 980
 981 static void qed_init_qm_mcos_pqs(struct qed_hwfn *p_hwfn)
 982 {
 983         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 984         u8 tc_idx;
 985
 986         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_MCOS))
 987                 return;
 988
 989         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_MCOS, qm_info->num_pqs);
 990         for (tc_idx = 0; tc_idx < qed_init_qm_get_num_tcs(p_hwfn); tc_idx++)
 991                 qed_init_qm_pq(p_hwfn, qm_info, tc_idx, PQ_INIT_SHARE_VPORT);
 992 }
 993
 994 static void qed_init_qm_vf_pqs(struct qed_hwfn *p_hwfn)
 995 {
 996         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 997         u16 vf_idx, num_vfs = qed_init_qm_get_num_vfs(p_hwfn);
 998
 999         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_VFS))
1000                 return;
1001
1002         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_VFS, qm_info->num_pqs);
1003         qm_info->num_vf_pqs = num_vfs;
1004         for (vf_idx = 0; vf_idx < num_vfs; vf_idx++)
1005                 qed_init_qm_pq(p_hwfn,
1006                                qm_info, PQ_INIT_DEFAULT_TC, PQ_INIT_VF_RL);
1007 }
1008
1009 static void qed_init_qm_rl_pqs(struct qed_hwfn *p_hwfn)
1010 {
1011         u16 pf_rls_idx, num_pf_rls = qed_init_qm_get_num_pf_rls(p_hwfn);
1012         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1013
1014         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_RLS))
1015                 return;
1016
1017         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_RLS, qm_info->num_pqs);
1018         for (pf_rls_idx = 0; pf_rls_idx < num_pf_rls; pf_rls_idx++)
1019                 qed_init_qm_pq(p_hwfn, qm_info, qed_get_offload_tc(p_hwfn),
1020                                PQ_INIT_PF_RL);
1021 }
1022
1023 static void qed_init_qm_pq_params(struct qed_hwfn *p_hwfn)
1024 {
1025         /* rate limited pqs, must come first (FW assumption) */
1026         qed_init_qm_rl_pqs(p_hwfn);
1027
1028         /* pqs for multi cos */
1029         qed_init_qm_mcos_pqs(p_hwfn);
1030
1031         /* pure loopback pq */
1032         qed_init_qm_lb_pq(p_hwfn);
1033
1034         /* out of order pq */
1035         qed_init_qm_ooo_pq(p_hwfn);
1036
1037         /* pure ack pq */
1038         qed_init_qm_pure_ack_pq(p_hwfn);
1039
1040         /* pq for offloaded protocol */
1041         qed_init_qm_offload_pq(p_hwfn);
1042
1043         /* low latency pq */
1044         qed_init_qm_low_latency_pq(p_hwfn);
1045
1046         /* done sharing vports */
1047         qed_init_qm_advance_vport(p_hwfn);
1048
1049         /* pqs for vfs */
1050         qed_init_qm_vf_pqs(p_hwfn);
1051 }
1052
1053 /* compare values of getters against resources amounts */
1054 static int qed_init_qm_sanity(struct qed_hwfn *p_hwfn)
1055 {
1056         if (qed_init_qm_get_num_vports(p_hwfn) > RESC_NUM(p_hwfn, QED_VPORT)) {
1057                 DP_ERR(p_hwfn, "requested amount of vports exceeds resource\n");
1058                 return -EINVAL;
1059         }
1060
1061         if (qed_init_qm_get_num_pqs(p_hwfn) <= RESC_NUM(p_hwfn, QED_PQ))
1062                 return 0;
1063
1064         if (QED_IS_ROCE_PERSONALITY(p_hwfn)) {
1065                 p_hwfn->hw_info.multi_tc_roce_en = 0;
1066                 DP_NOTICE(p_hwfn,
1067                           "multi-tc roce was disabled to reduce requested amount of pqs\n");
1068                 if (qed_init_qm_get_num_pqs(p_hwfn) <= RESC_NUM(p_hwfn, QED_PQ))
1069                         return 0;
1070         }
1071
1072         DP_ERR(p_hwfn, "requested amount of pqs exceeds resource\n");
1073         return -EINVAL;
1074 }
1075
1076 static void qed_dp_init_qm_params(struct qed_hwfn *p_hwfn)
1077 {
1078         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1079         struct init_qm_vport_params *vport;
1080         struct init_qm_port_params *port;
1081         struct init_qm_pq_params *pq;
1082         int i, tc;
1083
1084         /* top level params */
1085         DP_VERBOSE(p_hwfn,
1086                    NETIF_MSG_HW,
1087                    "qm init top level params: start_pq %d, start_vport %d, pure_lb_pq %d, offload_pq %d, llt_pq %d, pure_ack_pq %d\n",
1088                    qm_info->start_pq,
1089                    qm_info->start_vport,
1090                    qm_info->pure_lb_pq,
1091                    qm_info->first_ofld_pq,
1092                    qm_info->first_llt_pq,
1093                    qm_info->pure_ack_pq);
1094         DP_VERBOSE(p_hwfn,
1095                    NETIF_MSG_HW,
1096                    "ooo_pq %d, first_vf_pq %d, num_pqs %d, num_vf_pqs %d, num_vports %d, max_phys_tcs_per_port %d\n",
1097                    qm_info->ooo_pq,
1098                    qm_info->first_vf_pq,
1099                    qm_info->num_pqs,
1100                    qm_info->num_vf_pqs,
1101                    qm_info->num_vports, qm_info->max_phys_tcs_per_port);
1102         DP_VERBOSE(p_hwfn,
1103                    NETIF_MSG_HW,
1104                    "pf_rl_en %d, pf_wfq_en %d, vport_rl_en %d, vport_wfq_en %d, pf_wfq %d, pf_rl %d, num_pf_rls %d, pq_flags %x\n",
1105                    qm_info->pf_rl_en,
1106                    qm_info->pf_wfq_en,
1107                    qm_info->vport_rl_en,
1108                    qm_info->vport_wfq_en,
1109                    qm_info->pf_wfq,
1110                    qm_info->pf_rl,
1111                    qm_info->num_pf_rls, qed_get_pq_flags(p_hwfn));
1112
1113         /* port table */
1114         for (i = 0; i < p_hwfn->cdev->num_ports_in_engine; i++) {
1115                 port = &(qm_info->qm_port_params[i]);
1116                 DP_VERBOSE(p_hwfn,
1117                            NETIF_MSG_HW,
1118                            "port idx %d, active %d, active_phys_tcs %d, num_pbf_cmd_lines %d, num_btb_blocks %d, reserved %d\n",
1119                            i,
1120                            port->active,
1121                            port->active_phys_tcs,
1122                            port->num_pbf_cmd_lines,
1123                            port->num_btb_blocks, port->reserved);
1124         }
1125
1126         /* vport table */
1127         for (i = 0; i < qm_info->num_vports; i++) {
1128                 vport = &(qm_info->qm_vport_params[i]);
1129                 DP_VERBOSE(p_hwfn,
1130                            NETIF_MSG_HW,
1131                            "vport idx %d, vport_rl %d, wfq %d, first_tx_pq_id [ ",
1132                            qm_info->start_vport + i,
1133                            vport->vport_rl, vport->vport_wfq);
1134                 for (tc = 0; tc < NUM_OF_TCS; tc++)
1135                         DP_VERBOSE(p_hwfn,
1136                                    NETIF_MSG_HW,
1137                                    "%d ", vport->first_tx_pq_id[tc]);
1138                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "]\n");
1139         }
1140
1141         /* pq table */
1142         for (i = 0; i < qm_info->num_pqs; i++) {
1143                 pq = &(qm_info->qm_pq_params[i]);
1144                 DP_VERBOSE(p_hwfn,
1145                            NETIF_MSG_HW,
1146                            "pq idx %d, port %d, vport_id %d, tc %d, wrr_grp %d, rl_valid %d\n",
1147                            qm_info->start_pq + i,
1148                            pq->port_id,
1149                            pq->vport_id,
1150                            pq->tc_id, pq->wrr_group, pq->rl_valid);
1151         }
1152 }
1153
1154 static void qed_init_qm_info(struct qed_hwfn *p_hwfn)
1155 {
1156         /* reset params required for init run */
1157         qed_init_qm_reset_params(p_hwfn);
1158
1159         /* init QM top level params */
1160         qed_init_qm_params(p_hwfn);
1161
1162         /* init QM port params */
1163         qed_init_qm_port_params(p_hwfn);
1164
1165         /* init QM vport params */
1166         qed_init_qm_vport_params(p_hwfn);
1167
1168         /* init QM physical queue params */
1169         qed_init_qm_pq_params(p_hwfn);
1170
1171         /* display all that init */
1172         qed_dp_init_qm_params(p_hwfn);
1173 }
1174
1175 /* This function reconfigures the QM pf on the fly.
1176  * For this purpose we:
1177  * 1. reconfigure the QM database
1178  * 2. set new values to runtime array
1179  * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
1180  * 4. activate init tool in QM_PF stage
1181  * 5. send an sdm_qm_cmd through rbc interface to release the QM
1182  */
1183 int qed_qm_reconf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1184 {
1185         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1186         bool b_rc;
1187         int rc;
1188
1189         /* initialize qed's qm data structure */
1190         qed_init_qm_info(p_hwfn);
1191
1192         /* stop PF's qm queues */
1193         spin_lock_bh(&qm_lock);
1194         b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
1195                                     qm_info->start_pq, qm_info->num_pqs);
1196         spin_unlock_bh(&qm_lock);
1197         if (!b_rc)
1198                 return -EINVAL;
1199
1200         /* clear the QM_PF runtime phase leftovers from previous init */
1201         qed_init_clear_rt_data(p_hwfn);
1202
1203         /* prepare QM portion of runtime array */
1204         qed_qm_init_pf(p_hwfn, p_ptt, false);
1205
1206         /* activate init tool on runtime array */
1207         rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
1208                           p_hwfn->hw_info.hw_mode);
1209         if (rc)
1210                 return rc;
1211
1212         /* start PF's qm queues */
1213         spin_lock_bh(&qm_lock);
1214         b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
1215                                     qm_info->start_pq, qm_info->num_pqs);
1216         spin_unlock_bh(&qm_lock);
1217         if (!b_rc)
1218                 return -EINVAL;
1219
1220         return 0;
1221 }
1222
1223 static int qed_alloc_qm_data(struct qed_hwfn *p_hwfn)
1224 {
1225         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1226         int rc;
1227
1228         rc = qed_init_qm_sanity(p_hwfn);
1229         if (rc)
1230                 goto alloc_err;
1231
1232         qm_info->qm_pq_params = kcalloc(qed_init_qm_get_num_pqs(p_hwfn),
1233                                         sizeof(*qm_info->qm_pq_params),
1234                                         GFP_KERNEL);
1235         if (!qm_info->qm_pq_params)
1236                 goto alloc_err;
1237
1238         qm_info->qm_vport_params = kcalloc(qed_init_qm_get_num_vports(p_hwfn),
1239                                            sizeof(*qm_info->qm_vport_params),
1240                                            GFP_KERNEL);
1241         if (!qm_info->qm_vport_params)
1242                 goto alloc_err;
1243
1244         qm_info->qm_port_params = kcalloc(p_hwfn->cdev->num_ports_in_engine,
1245                                           sizeof(*qm_info->qm_port_params),
1246                                           GFP_KERNEL);
1247         if (!qm_info->qm_port_params)
1248                 goto alloc_err;
1249
1250         qm_info->wfq_data = kcalloc(qed_init_qm_get_num_vports(p_hwfn),
1251                                     sizeof(*qm_info->wfq_data),
1252                                     GFP_KERNEL);
1253         if (!qm_info->wfq_data)
1254                 goto alloc_err;
1255
1256         return 0;
1257
1258 alloc_err:
1259         DP_NOTICE(p_hwfn, "Failed to allocate memory for QM params\n");
1260         qed_qm_info_free(p_hwfn);
1261         return -ENOMEM;
1262 }
1263
1264 int qed_resc_alloc(struct qed_dev *cdev)
1265 {
1266         u32 rdma_tasks, excess_tasks;
1267         u32 line_count;
1268         int i, rc = 0;
1269
1270         if (IS_VF(cdev)) {
1271                 for_each_hwfn(cdev, i) {
1272                         rc = qed_l2_alloc(&cdev->hwfns[i]);
1273                         if (rc)
1274                                 return rc;
1275                 }
1276                 return rc;
1277         }
1278
1279         cdev->fw_data = kzalloc(sizeof(*cdev->fw_data), GFP_KERNEL);
1280         if (!cdev->fw_data)
1281                 return -ENOMEM;
1282
1283         for_each_hwfn(cdev, i) {
1284                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1285                 u32 n_eqes, num_cons;
1286
1287                 /* Initialize the doorbell recovery mechanism */
1288                 rc = qed_db_recovery_setup(p_hwfn);
1289                 if (rc)
1290                         goto alloc_err;
1291
1292                 /* First allocate the context manager structure */
1293                 rc = qed_cxt_mngr_alloc(p_hwfn);
1294                 if (rc)
1295                         goto alloc_err;
1296
1297                 /* Set the HW cid/tid numbers (in the contest manager)
1298                  * Must be done prior to any further computations.
1299                  */
1300                 rc = qed_cxt_set_pf_params(p_hwfn, RDMA_MAX_TIDS);
1301                 if (rc)
1302                         goto alloc_err;
1303
1304                 rc = qed_alloc_qm_data(p_hwfn);
1305                 if (rc)
1306                         goto alloc_err;
1307
1308                 /* init qm info */
1309                 qed_init_qm_info(p_hwfn);
1310
1311                 /* Compute the ILT client partition */
1312                 rc = qed_cxt_cfg_ilt_compute(p_hwfn, &line_count);
1313                 if (rc) {
1314                         DP_NOTICE(p_hwfn,
1315                                   "too many ILT lines; re-computing with less lines\n");
1316                         /* In case there are not enough ILT lines we reduce the
1317                          * number of RDMA tasks and re-compute.
1318                          */
1319                         excess_tasks =
1320                             qed_cxt_cfg_ilt_compute_excess(p_hwfn, line_count);
1321                         if (!excess_tasks)
1322                                 goto alloc_err;
1323
1324                         rdma_tasks = RDMA_MAX_TIDS - excess_tasks;
1325                         rc = qed_cxt_set_pf_params(p_hwfn, rdma_tasks);
1326                         if (rc)
1327                                 goto alloc_err;
1328
1329                         rc = qed_cxt_cfg_ilt_compute(p_hwfn, &line_count);
1330                         if (rc) {
1331                                 DP_ERR(p_hwfn,
1332                                        "failed ILT compute. Requested too many lines: %u\n",
1333                                        line_count);
1334
1335                                 goto alloc_err;
1336                         }
1337                 }
1338
1339                 /* CID map / ILT shadow table / T2
1340                  * The talbes sizes are determined by the computations above
1341                  */
1342                 rc = qed_cxt_tables_alloc(p_hwfn);
1343                 if (rc)
1344                         goto alloc_err;
1345
1346                 /* SPQ, must follow ILT because initializes SPQ context */
1347                 rc = qed_spq_alloc(p_hwfn);
1348                 if (rc)
1349                         goto alloc_err;
1350
1351                 /* SP status block allocation */
1352                 p_hwfn->p_dpc_ptt = qed_get_reserved_ptt(p_hwfn,
1353                                                          RESERVED_PTT_DPC);
1354
1355                 rc = qed_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
1356                 if (rc)
1357                         goto alloc_err;
1358
1359                 rc = qed_iov_alloc(p_hwfn);
1360                 if (rc)
1361                         goto alloc_err;
1362
1363                 /* EQ */
1364                 n_eqes = qed_chain_get_capacity(&p_hwfn->p_spq->chain);
1365                 if (QED_IS_RDMA_PERSONALITY(p_hwfn)) {
1366                         enum protocol_type rdma_proto;
1367
1368                         if (QED_IS_ROCE_PERSONALITY(p_hwfn))
1369                                 rdma_proto = PROTOCOLID_ROCE;
1370                         else
1371                                 rdma_proto = PROTOCOLID_IWARP;
1372
1373                         num_cons = qed_cxt_get_proto_cid_count(p_hwfn,
1374                                                                rdma_proto,
1375                                                                NULL) * 2;
1376                         n_eqes += num_cons + 2 * MAX_NUM_VFS_BB;
1377                 } else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
1378                         num_cons =
1379                             qed_cxt_get_proto_cid_count(p_hwfn,
1380                                                         PROTOCOLID_ISCSI,
1381                                                         NULL);
1382                         n_eqes += 2 * num_cons;
1383                 }
1384
1385                 if (n_eqes > 0xFFFF) {
1386                         DP_ERR(p_hwfn,
1387                                "Cannot allocate 0x%x EQ elements. The maximum of a u16 chain is 0x%x\n",
1388                                n_eqes, 0xFFFF);
1389                         goto alloc_no_mem;
1390                 }
1391
1392                 rc = qed_eq_alloc(p_hwfn, (u16) n_eqes);
1393                 if (rc)
1394                         goto alloc_err;
1395
1396                 rc = qed_consq_alloc(p_hwfn);
1397                 if (rc)
1398                         goto alloc_err;
1399
1400                 rc = qed_l2_alloc(p_hwfn);
1401                 if (rc)
1402                         goto alloc_err;
1403
1404 #ifdef CONFIG_QED_LL2
1405                 if (p_hwfn->using_ll2) {
1406                         rc = qed_ll2_alloc(p_hwfn);
1407                         if (rc)
1408                                 goto alloc_err;
1409                 }
1410 #endif
1411
1412                 if (p_hwfn->hw_info.personality == QED_PCI_FCOE) {
1413                         rc = qed_fcoe_alloc(p_hwfn);
1414                         if (rc)
1415                                 goto alloc_err;
1416                 }
1417
1418                 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
1419                         rc = qed_iscsi_alloc(p_hwfn);
1420                         if (rc)
1421                                 goto alloc_err;
1422                         rc = qed_ooo_alloc(p_hwfn);
1423                         if (rc)
1424                                 goto alloc_err;
1425                 }
1426
1427                 if (QED_IS_RDMA_PERSONALITY(p_hwfn)) {
1428                         rc = qed_rdma_info_alloc(p_hwfn);
1429                         if (rc)
1430                                 goto alloc_err;
1431                 }
1432
1433                 /* DMA info initialization */
1434                 rc = qed_dmae_info_alloc(p_hwfn);
1435                 if (rc)
1436                         goto alloc_err;
1437
1438                 /* DCBX initialization */
1439                 rc = qed_dcbx_info_alloc(p_hwfn);
1440                 if (rc)
1441                         goto alloc_err;
1442
1443                 rc = qed_dbg_alloc_user_data(p_hwfn);
1444                 if (rc)
1445                         goto alloc_err;
1446         }
1447
1448         cdev->reset_stats = kzalloc(sizeof(*cdev->reset_stats), GFP_KERNEL);
1449         if (!cdev->reset_stats)
1450                 goto alloc_no_mem;
1451
1452         return 0;
1453
1454 alloc_no_mem:
1455         rc = -ENOMEM;
1456 alloc_err:
1457         qed_resc_free(cdev);
1458         return rc;
1459 }
1460
1461 void qed_resc_setup(struct qed_dev *cdev)
1462 {
1463         int i;
1464
1465         if (IS_VF(cdev)) {
1466                 for_each_hwfn(cdev, i)
1467                         qed_l2_setup(&cdev->hwfns[i]);
1468                 return;
1469         }
1470
1471         for_each_hwfn(cdev, i) {
1472                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1473
1474                 qed_cxt_mngr_setup(p_hwfn);
1475                 qed_spq_setup(p_hwfn);
1476                 qed_eq_setup(p_hwfn);
1477                 qed_consq_setup(p_hwfn);
1478
1479                 /* Read shadow of current MFW mailbox */
1480                 qed_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
1481                 memcpy(p_hwfn->mcp_info->mfw_mb_shadow,
1482                        p_hwfn->mcp_info->mfw_mb_cur,
1483                        p_hwfn->mcp_info->mfw_mb_length);
1484
1485                 qed_int_setup(p_hwfn, p_hwfn->p_main_ptt);
1486
1487                 qed_l2_setup(p_hwfn);
1488                 qed_iov_setup(p_hwfn);
1489 #ifdef CONFIG_QED_LL2
1490                 if (p_hwfn->using_ll2)
1491                         qed_ll2_setup(p_hwfn);
1492 #endif
1493                 if (p_hwfn->hw_info.personality == QED_PCI_FCOE)
1494                         qed_fcoe_setup(p_hwfn);
1495
1496                 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
1497                         qed_iscsi_setup(p_hwfn);
1498                         qed_ooo_setup(p_hwfn);
1499                 }
1500         }
1501 }
1502
1503 #define FINAL_CLEANUP_POLL_CNT          (100)
1504 #define FINAL_CLEANUP_POLL_TIME         (10)
1505 int qed_final_cleanup(struct qed_hwfn *p_hwfn,
1506                       struct qed_ptt *p_ptt, u16 id, bool is_vf)
1507 {
1508         u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
1509         int rc = -EBUSY;
1510
1511         addr = GTT_BAR0_MAP_REG_USDM_RAM +
1512                 USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
1513
1514         if (is_vf)
1515                 id += 0x10;
1516
1517         command |= X_FINAL_CLEANUP_AGG_INT <<
1518                 SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
1519         command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
1520         command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
1521         command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
1522
1523         /* Make sure notification is not set before initiating final cleanup */
1524         if (REG_RD(p_hwfn, addr)) {
1525                 DP_NOTICE(p_hwfn,
1526                           "Unexpected; Found final cleanup notification before initiating final cleanup\n");
1527                 REG_WR(p_hwfn, addr, 0);
1528         }
1529
1530         DP_VERBOSE(p_hwfn, QED_MSG_IOV,
1531                    "Sending final cleanup for PFVF[%d] [Command %08x]\n",
1532                    id, command);
1533
1534         qed_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);
1535
1536         /* Poll until completion */
1537         while (!REG_RD(p_hwfn, addr) && count--)
1538                 msleep(FINAL_CLEANUP_POLL_TIME);
1539
1540         if (REG_RD(p_hwfn, addr))
1541                 rc = 0;
1542         else
1543                 DP_NOTICE(p_hwfn,
1544                           "Failed to receive FW final cleanup notification\n");
1545
1546         /* Cleanup afterwards */
1547         REG_WR(p_hwfn, addr, 0);
1548
1549         return rc;
1550 }
1551
1552 static int qed_calc_hw_mode(struct qed_hwfn *p_hwfn)
1553 {
1554         int hw_mode = 0;
1555
1556         if (QED_IS_BB_B0(p_hwfn->cdev)) {
1557                 hw_mode |= 1 << MODE_BB;
1558         } else if (QED_IS_AH(p_hwfn->cdev)) {
1559                 hw_mode |= 1 << MODE_K2;
1560         } else {
1561                 DP_NOTICE(p_hwfn, "Unknown chip type %#x\n",
1562                           p_hwfn->cdev->type);
1563                 return -EINVAL;
1564         }
1565
1566         switch (p_hwfn->cdev->num_ports_in_engine) {
1567         case 1:
1568                 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
1569                 break;
1570         case 2:
1571                 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
1572                 break;
1573         case 4:
1574                 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
1575                 break;
1576         default:
1577                 DP_NOTICE(p_hwfn, "num_ports_in_engine = %d not supported\n",
1578                           p_hwfn->cdev->num_ports_in_engine);
1579                 return -EINVAL;
1580         }
1581
1582         if (test_bit(QED_MF_OVLAN_CLSS, &p_hwfn->cdev->mf_bits))
1583                 hw_mode |= 1 << MODE_MF_SD;
1584         else
1585                 hw_mode |= 1 << MODE_MF_SI;
1586
1587         hw_mode |= 1 << MODE_ASIC;
1588
1589         if (p_hwfn->cdev->num_hwfns > 1)
1590                 hw_mode |= 1 << MODE_100G;
1591
1592         p_hwfn->hw_info.hw_mode = hw_mode;
1593
1594         DP_VERBOSE(p_hwfn, (NETIF_MSG_PROBE | NETIF_MSG_IFUP),
1595                    "Configuring function for hw_mode: 0x%08x\n",
1596                    p_hwfn->hw_info.hw_mode);
1597
1598         return 0;
1599 }
1600
1601 /* Init run time data for all PFs on an engine. */
1602 static void qed_init_cau_rt_data(struct qed_dev *cdev)
1603 {
1604         u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
1605         int i, igu_sb_id;
1606
1607         for_each_hwfn(cdev, i) {
1608                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1609                 struct qed_igu_info *p_igu_info;
1610                 struct qed_igu_block *p_block;
1611                 struct cau_sb_entry sb_entry;
1612
1613                 p_igu_info = p_hwfn->hw_info.p_igu_info;
1614
1615                 for (igu_sb_id = 0;
1616                      igu_sb_id < QED_MAPPING_MEMORY_SIZE(cdev); igu_sb_id++) {
1617                         p_block = &p_igu_info->entry[igu_sb_id];
1618
1619                         if (!p_block->is_pf)
1620                                 continue;
1621
1622                         qed_init_cau_sb_entry(p_hwfn, &sb_entry,
1623                                               p_block->function_id, 0, 0);
1624                         STORE_RT_REG_AGG(p_hwfn, offset + igu_sb_id * 2,
1625                                          sb_entry);
1626                 }
1627         }
1628 }
1629
1630 static void qed_init_cache_line_size(struct qed_hwfn *p_hwfn,
1631                                      struct qed_ptt *p_ptt)
1632 {
1633         u32 val, wr_mbs, cache_line_size;
1634
1635         val = qed_rd(p_hwfn, p_ptt, PSWRQ2_REG_WR_MBS0);
1636         switch (val) {
1637         case 0:
1638                 wr_mbs = 128;
1639                 break;
1640         case 1:
1641                 wr_mbs = 256;
1642                 break;
1643         case 2:
1644                 wr_mbs = 512;
1645                 break;
1646         default:
1647                 DP_INFO(p_hwfn,
1648                         "Unexpected value of PSWRQ2_REG_WR_MBS0 [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
1649                         val);
1650                 return;
1651         }
1652
1653         cache_line_size = min_t(u32, L1_CACHE_BYTES, wr_mbs);
1654         switch (cache_line_size) {
1655         case 32:
1656                 val = 0;
1657                 break;
1658         case 64:
1659                 val = 1;
1660                 break;
1661         case 128:
1662                 val = 2;
1663                 break;
1664         case 256:
1665                 val = 3;
1666                 break;
1667         default:
1668                 DP_INFO(p_hwfn,
1669                         "Unexpected value of cache line size [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
1670                         cache_line_size);
1671         }
1672
1673         if (L1_CACHE_BYTES > wr_mbs)
1674                 DP_INFO(p_hwfn,
1675                         "The cache line size for padding is suboptimal for performance [OS cache line size 0x%x, wr mbs 0x%x]\n",
1676                         L1_CACHE_BYTES, wr_mbs);
1677
1678         STORE_RT_REG(p_hwfn, PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET, val);
1679         if (val > 0) {
1680                 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET, val);
1681                 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET, val);
1682         }
1683 }
1684
1685 static int qed_hw_init_common(struct qed_hwfn *p_hwfn,
1686                               struct qed_ptt *p_ptt, int hw_mode)
1687 {
1688         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1689         struct qed_qm_common_rt_init_params params;
1690         struct qed_dev *cdev = p_hwfn->cdev;
1691         u8 vf_id, max_num_vfs;
1692         u16 num_pfs, pf_id;
1693         u32 concrete_fid;
1694         int rc = 0;
1695
1696         qed_init_cau_rt_data(cdev);
1697
1698         /* Program GTT windows */
1699         qed_gtt_init(p_hwfn);
1700
1701         if (p_hwfn->mcp_info) {
1702                 if (p_hwfn->mcp_info->func_info.bandwidth_max)
1703                         qm_info->pf_rl_en = true;
1704                 if (p_hwfn->mcp_info->func_info.bandwidth_min)
1705                         qm_info->pf_wfq_en = true;
1706         }
1707
1708         memset(&params, 0, sizeof(params));
1709         params.max_ports_per_engine = p_hwfn->cdev->num_ports_in_engine;
1710         params.max_phys_tcs_per_port = qm_info->max_phys_tcs_per_port;
1711         params.pf_rl_en = qm_info->pf_rl_en;
1712         params.pf_wfq_en = qm_info->pf_wfq_en;
1713         params.vport_rl_en = qm_info->vport_rl_en;
1714         params.vport_wfq_en = qm_info->vport_wfq_en;
1715         params.port_params = qm_info->qm_port_params;
1716
1717         qed_qm_common_rt_init(p_hwfn, &params);
1718
1719         qed_cxt_hw_init_common(p_hwfn);
1720
1721         qed_init_cache_line_size(p_hwfn, p_ptt);
1722
1723         rc = qed_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);
1724         if (rc)
1725                 return rc;
1726
1727         qed_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
1728         qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
1729
1730         if (QED_IS_BB(p_hwfn->cdev)) {
1731                 num_pfs = NUM_OF_ENG_PFS(p_hwfn->cdev);
1732                 for (pf_id = 0; pf_id < num_pfs; pf_id++) {
1733                         qed_fid_pretend(p_hwfn, p_ptt, pf_id);
1734                         qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1735                         qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1736                 }
1737                 /* pretend to original PF */
1738                 qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1739         }
1740
1741         max_num_vfs = QED_IS_AH(cdev) ? MAX_NUM_VFS_K2 : MAX_NUM_VFS_BB;
1742         for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
1743                 concrete_fid = qed_vfid_to_concrete(p_hwfn, vf_id);
1744                 qed_fid_pretend(p_hwfn, p_ptt, (u16) concrete_fid);
1745                 qed_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
1746                 qed_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
1747                 qed_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
1748                 qed_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
1749         }
1750         /* pretend to original PF */
1751         qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1752
1753         return rc;
1754 }
1755
1756 static int
1757 qed_hw_init_dpi_size(struct qed_hwfn *p_hwfn,
1758                      struct qed_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus)
1759 {
1760         u32 dpi_bit_shift, dpi_count, dpi_page_size;
1761         u32 min_dpis;
1762         u32 n_wids;
1763
1764         /* Calculate DPI size */
1765         n_wids = max_t(u32, QED_MIN_WIDS, n_cpus);
1766         dpi_page_size = QED_WID_SIZE * roundup_pow_of_two(n_wids);
1767         dpi_page_size = (dpi_page_size + PAGE_SIZE - 1) & ~(PAGE_SIZE - 1);
1768         dpi_bit_shift = ilog2(dpi_page_size / 4096);
1769         dpi_count = pwm_region_size / dpi_page_size;
1770
1771         min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis;
1772         min_dpis = max_t(u32, QED_MIN_DPIS, min_dpis);
1773
1774         p_hwfn->dpi_size = dpi_page_size;
1775         p_hwfn->dpi_count = dpi_count;
1776
1777         qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift);
1778
1779         if (dpi_count < min_dpis)
1780                 return -EINVAL;
1781
1782         return 0;
1783 }
1784
1785 enum QED_ROCE_EDPM_MODE {
1786         QED_ROCE_EDPM_MODE_ENABLE = 0,
1787         QED_ROCE_EDPM_MODE_FORCE_ON = 1,
1788         QED_ROCE_EDPM_MODE_DISABLE = 2,
1789 };
1790
1791 bool qed_edpm_enabled(struct qed_hwfn *p_hwfn)
1792 {
1793         if (p_hwfn->dcbx_no_edpm || p_hwfn->db_bar_no_edpm)
1794                 return false;
1795
1796         return true;
1797 }
1798
1799 static int
1800 qed_hw_init_pf_doorbell_bar(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1801 {
1802         u32 pwm_regsize, norm_regsize;
1803         u32 non_pwm_conn, min_addr_reg1;
1804         u32 db_bar_size, n_cpus = 1;
1805         u32 roce_edpm_mode;
1806         u32 pf_dems_shift;
1807         int rc = 0;
1808         u8 cond;
1809
1810         db_bar_size = qed_hw_bar_size(p_hwfn, p_ptt, BAR_ID_1);
1811         if (p_hwfn->cdev->num_hwfns > 1)
1812                 db_bar_size /= 2;
1813
1814         /* Calculate doorbell regions */
1815         non_pwm_conn = qed_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
1816                        qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
1817                                                    NULL) +
1818                        qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH,
1819                                                    NULL);
1820         norm_regsize = roundup(QED_PF_DEMS_SIZE * non_pwm_conn, PAGE_SIZE);
1821         min_addr_reg1 = norm_regsize / 4096;
1822         pwm_regsize = db_bar_size - norm_regsize;
1823
1824         /* Check that the normal and PWM sizes are valid */
1825         if (db_bar_size < norm_regsize) {
1826                 DP_ERR(p_hwfn->cdev,
1827                        "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n",
1828                        db_bar_size, norm_regsize);
1829                 return -EINVAL;
1830         }
1831
1832         if (pwm_regsize < QED_MIN_PWM_REGION) {
1833                 DP_ERR(p_hwfn->cdev,
1834                        "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n",
1835                        pwm_regsize,
1836                        QED_MIN_PWM_REGION, db_bar_size, norm_regsize);
1837                 return -EINVAL;
1838         }
1839
1840         /* Calculate number of DPIs */
1841         roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode;
1842         if ((roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE) ||
1843             ((roce_edpm_mode == QED_ROCE_EDPM_MODE_FORCE_ON))) {
1844                 /* Either EDPM is mandatory, or we are attempting to allocate a
1845                  * WID per CPU.
1846                  */
1847                 n_cpus = num_present_cpus();
1848                 rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1849         }
1850
1851         cond = (rc && (roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE)) ||
1852                (roce_edpm_mode == QED_ROCE_EDPM_MODE_DISABLE);
1853         if (cond || p_hwfn->dcbx_no_edpm) {
1854                 /* Either EDPM is disabled from user configuration, or it is
1855                  * disabled via DCBx, or it is not mandatory and we failed to
1856                  * allocated a WID per CPU.
1857                  */
1858                 n_cpus = 1;
1859                 rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1860
1861                 if (cond)
1862                         qed_rdma_dpm_bar(p_hwfn, p_ptt);
1863         }
1864
1865         p_hwfn->wid_count = (u16) n_cpus;
1866
1867         DP_INFO(p_hwfn,
1868                 "doorbell bar: normal_region_size=%d, pwm_region_size=%d, dpi_size=%d, dpi_count=%d, roce_edpm=%s, page_size=%lu\n",
1869                 norm_regsize,
1870                 pwm_regsize,
1871                 p_hwfn->dpi_size,
1872                 p_hwfn->dpi_count,
1873                 (!qed_edpm_enabled(p_hwfn)) ?
1874                 "disabled" : "enabled", PAGE_SIZE);
1875
1876         if (rc) {
1877                 DP_ERR(p_hwfn,
1878                        "Failed to allocate enough DPIs. Allocated %d but the current minimum is %d.\n",
1879                        p_hwfn->dpi_count,
1880                        p_hwfn->pf_params.rdma_pf_params.min_dpis);
1881                 return -EINVAL;
1882         }
1883
1884         p_hwfn->dpi_start_offset = norm_regsize;
1885
1886         /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
1887         pf_dems_shift = ilog2(QED_PF_DEMS_SIZE / 4);
1888         qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
1889         qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
1890
1891         return 0;
1892 }
1893
1894 static int qed_hw_init_port(struct qed_hwfn *p_hwfn,
1895                             struct qed_ptt *p_ptt, int hw_mode)
1896 {
1897         int rc = 0;
1898
1899         rc = qed_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id, hw_mode);
1900         if (rc)
1901                 return rc;
1902
1903         qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_WRITE_PAD_ENABLE, 0);
1904
1905         return 0;
1906 }
1907
1908 static int qed_hw_init_pf(struct qed_hwfn *p_hwfn,
1909                           struct qed_ptt *p_ptt,
1910                           struct qed_tunnel_info *p_tunn,
1911                           int hw_mode,
1912                           bool b_hw_start,
1913                           enum qed_int_mode int_mode,
1914                           bool allow_npar_tx_switch)
1915 {
1916         u8 rel_pf_id = p_hwfn->rel_pf_id;
1917         int rc = 0;
1918
1919         if (p_hwfn->mcp_info) {
1920                 struct qed_mcp_function_info *p_info;
1921
1922                 p_info = &p_hwfn->mcp_info->func_info;
1923                 if (p_info->bandwidth_min)
1924                         p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
1925
1926                 /* Update rate limit once we'll actually have a link */
1927                 p_hwfn->qm_info.pf_rl = 100000;
1928         }
1929
1930         qed_cxt_hw_init_pf(p_hwfn, p_ptt);
1931
1932         qed_int_igu_init_rt(p_hwfn);
1933
1934         /* Set VLAN in NIG if needed */
1935         if (hw_mode & BIT(MODE_MF_SD)) {
1936                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "Configuring LLH_FUNC_TAG\n");
1937                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
1938                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
1939                              p_hwfn->hw_info.ovlan);
1940
1941                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
1942                            "Configuring LLH_FUNC_FILTER_HDR_SEL\n");
1943                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET,
1944                              1);
1945         }
1946
1947         /* Enable classification by MAC if needed */
1948         if (hw_mode & BIT(MODE_MF_SI)) {
1949                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
1950                            "Configuring TAGMAC_CLS_TYPE\n");
1951                 STORE_RT_REG(p_hwfn,
1952                              NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET, 1);
1953         }
1954
1955         /* Protocol Configuration */
1956         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
1957                      (p_hwfn->hw_info.personality == QED_PCI_ISCSI) ? 1 : 0);
1958         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET,
1959                      (p_hwfn->hw_info.personality == QED_PCI_FCOE) ? 1 : 0);
1960         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
1961
1962         /* Sanity check before the PF init sequence that uses DMAE */
1963         rc = qed_dmae_sanity(p_hwfn, p_ptt, "pf_phase");
1964         if (rc)
1965                 return rc;
1966
1967         /* PF Init sequence */
1968         rc = qed_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
1969         if (rc)
1970                 return rc;
1971
1972         /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
1973         rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
1974         if (rc)
1975                 return rc;
1976
1977         /* Pure runtime initializations - directly to the HW  */
1978         qed_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
1979
1980         rc = qed_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
1981         if (rc)
1982                 return rc;
1983
1984         if (b_hw_start) {
1985                 /* enable interrupts */
1986                 qed_int_igu_enable(p_hwfn, p_ptt, int_mode);
1987
1988                 /* send function start command */
1989                 rc = qed_sp_pf_start(p_hwfn, p_ptt, p_tunn,
1990                                      allow_npar_tx_switch);
1991                 if (rc) {
1992                         DP_NOTICE(p_hwfn, "Function start ramrod failed\n");
1993                         return rc;
1994                 }
1995                 if (p_hwfn->hw_info.personality == QED_PCI_FCOE) {
1996                         qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1, BIT(2));
1997                         qed_wr(p_hwfn, p_ptt,
1998                                PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST,
1999                                0x100);
2000                 }
2001         }
2002         return rc;
2003 }
2004
2005 int qed_pglueb_set_pfid_enable(struct qed_hwfn *p_hwfn,
2006                                struct qed_ptt *p_ptt, bool b_enable)
2007 {
2008         u32 delay_idx = 0, val, set_val = b_enable ? 1 : 0;
2009
2010         /* Configure the PF's internal FID_enable for master transactions */
2011         qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
2012
2013         /* Wait until value is set - try for 1 second every 50us */
2014         for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
2015                 val = qed_rd(p_hwfn, p_ptt,
2016                              PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
2017                 if (val == set_val)
2018                         break;
2019
2020                 usleep_range(50, 60);
2021         }
2022
2023         if (val != set_val) {
2024                 DP_NOTICE(p_hwfn,
2025                           "PFID_ENABLE_MASTER wasn't changed after a second\n");
2026                 return -EAGAIN;
2027         }
2028
2029         return 0;
2030 }
2031
2032 static void qed_reset_mb_shadow(struct qed_hwfn *p_hwfn,
2033                                 struct qed_ptt *p_main_ptt)
2034 {
2035         /* Read shadow of current MFW mailbox */
2036         qed_mcp_read_mb(p_hwfn, p_main_ptt);
2037         memcpy(p_hwfn->mcp_info->mfw_mb_shadow,
2038                p_hwfn->mcp_info->mfw_mb_cur, p_hwfn->mcp_info->mfw_mb_length);
2039 }
2040
2041 static void
2042 qed_fill_load_req_params(struct qed_load_req_params *p_load_req,
2043                          struct qed_drv_load_params *p_drv_load)
2044 {
2045         memset(p_load_req, 0, sizeof(*p_load_req));
2046
2047         p_load_req->drv_role = p_drv_load->is_crash_kernel ?
2048                                QED_DRV_ROLE_KDUMP : QED_DRV_ROLE_OS;
2049         p_load_req->timeout_val = p_drv_load->mfw_timeout_val;
2050         p_load_req->avoid_eng_reset = p_drv_load->avoid_eng_reset;
2051         p_load_req->override_force_load = p_drv_load->override_force_load;
2052 }
2053
2054 static int qed_vf_start(struct qed_hwfn *p_hwfn,
2055                         struct qed_hw_init_params *p_params)
2056 {
2057         if (p_params->p_tunn) {
2058                 qed_vf_set_vf_start_tunn_update_param(p_params->p_tunn);
2059                 qed_vf_pf_tunnel_param_update(p_hwfn, p_params->p_tunn);
2060         }
2061
2062         p_hwfn->b_int_enabled = true;
2063
2064         return 0;
2065 }
2066
2067 static void qed_pglueb_clear_err(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2068 {
2069         qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR,
2070                BIT(p_hwfn->abs_pf_id));
2071 }
2072
2073 int qed_hw_init(struct qed_dev *cdev, struct qed_hw_init_params *p_params)
2074 {
2075         struct qed_load_req_params load_req_params;
2076         u32 load_code, resp, param, drv_mb_param;
2077         bool b_default_mtu = true;
2078         struct qed_hwfn *p_hwfn;
2079         int rc = 0, i;
2080         u16 ether_type;
2081
2082         if ((p_params->int_mode == QED_INT_MODE_MSI) && (cdev->num_hwfns > 1)) {
2083                 DP_NOTICE(cdev, "MSI mode is not supported for CMT devices\n");
2084                 return -EINVAL;
2085         }
2086
2087         if (IS_PF(cdev)) {
2088                 rc = qed_init_fw_data(cdev, p_params->bin_fw_data);
2089                 if (rc)
2090                         return rc;
2091         }
2092
2093         for_each_hwfn(cdev, i) {
2094                 p_hwfn = &cdev->hwfns[i];
2095
2096                 /* If management didn't provide a default, set one of our own */
2097                 if (!p_hwfn->hw_info.mtu) {
2098                         p_hwfn->hw_info.mtu = 1500;
2099                         b_default_mtu = false;
2100                 }
2101
2102                 if (IS_VF(cdev)) {
2103                         qed_vf_start(p_hwfn, p_params);
2104                         continue;
2105                 }
2106
2107                 rc = qed_calc_hw_mode(p_hwfn);
2108                 if (rc)
2109                         return rc;
2110
2111                 if (IS_PF(cdev) && (test_bit(QED_MF_8021Q_TAGGING,
2112                                              &cdev->mf_bits) ||
2113                                     test_bit(QED_MF_8021AD_TAGGING,
2114                                              &cdev->mf_bits))) {
2115                         if (test_bit(QED_MF_8021Q_TAGGING, &cdev->mf_bits))
2116                                 ether_type = ETH_P_8021Q;
2117                         else
2118                                 ether_type = ETH_P_8021AD;
2119                         STORE_RT_REG(p_hwfn, PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET,
2120                                      ether_type);
2121                         STORE_RT_REG(p_hwfn, NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET,
2122                                      ether_type);
2123                         STORE_RT_REG(p_hwfn, PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET,
2124                                      ether_type);
2125                         STORE_RT_REG(p_hwfn, DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET,
2126                                      ether_type);
2127                 }
2128
2129                 qed_fill_load_req_params(&load_req_params,
2130                                          p_params->p_drv_load_params);
2131                 rc = qed_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt,
2132                                       &load_req_params);
2133                 if (rc) {
2134                         DP_NOTICE(p_hwfn, "Failed sending a LOAD_REQ command\n");
2135                         return rc;
2136                 }
2137
2138                 load_code = load_req_params.load_code;
2139                 DP_VERBOSE(p_hwfn, QED_MSG_SP,
2140                            "Load request was sent. Load code: 0x%x\n",
2141                            load_code);
2142
2143                 /* Only relevant for recovery:
2144                  * Clear the indication after LOAD_REQ is responded by the MFW.
2145                  */
2146                 cdev->recov_in_prog = false;
2147
2148                 qed_mcp_set_capabilities(p_hwfn, p_hwfn->p_main_ptt);
2149
2150                 qed_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
2151
2152                 /* Clean up chip from previous driver if such remains exist.
2153                  * This is not needed when the PF is the first one on the
2154                  * engine, since afterwards we are going to init the FW.
2155                  */
2156                 if (load_code != FW_MSG_CODE_DRV_LOAD_ENGINE) {
2157                         rc = qed_final_cleanup(p_hwfn, p_hwfn->p_main_ptt,
2158                                                p_hwfn->rel_pf_id, false);
2159                         if (rc) {
2160                                 DP_NOTICE(p_hwfn, "Final cleanup failed\n");
2161                                 goto load_err;
2162                         }
2163                 }
2164
2165                 /* Log and clear previous pglue_b errors if such exist */
2166                 qed_pglueb_rbc_attn_handler(p_hwfn, p_hwfn->p_main_ptt);
2167
2168                 /* Enable the PF's internal FID_enable in the PXP */
2169                 rc = qed_pglueb_set_pfid_enable(p_hwfn, p_hwfn->p_main_ptt,
2170                                                 true);
2171                 if (rc)
2172                         goto load_err;
2173
2174                 /* Clear the pglue_b was_error indication.
2175                  * In E4 it must be done after the BME and the internal
2176                  * FID_enable for the PF are set, since VDMs may cause the
2177                  * indication to be set again.
2178                  */
2179                 qed_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt);
2180
2181                 switch (load_code) {
2182                 case FW_MSG_CODE_DRV_LOAD_ENGINE:
2183                         rc = qed_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
2184                                                 p_hwfn->hw_info.hw_mode);
2185                         if (rc)
2186                                 break;
2187                 /* Fall through */
2188                 case FW_MSG_CODE_DRV_LOAD_PORT:
2189                         rc = qed_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
2190                                               p_hwfn->hw_info.hw_mode);
2191                         if (rc)
2192                                 break;
2193
2194                 /* Fall through */
2195                 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
2196                         rc = qed_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
2197                                             p_params->p_tunn,
2198                                             p_hwfn->hw_info.hw_mode,
2199                                             p_params->b_hw_start,
2200                                             p_params->int_mode,
2201                                             p_params->allow_npar_tx_switch);
2202                         break;
2203                 default:
2204                         DP_NOTICE(p_hwfn,
2205                                   "Unexpected load code [0x%08x]", load_code);
2206                         rc = -EINVAL;
2207                         break;
2208                 }
2209
2210                 if (rc) {
2211                         DP_NOTICE(p_hwfn,
2212                                   "init phase failed for loadcode 0x%x (rc %d)\n",
2213                                   load_code, rc);
2214                         goto load_err;
2215                 }
2216
2217                 rc = qed_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt);
2218                 if (rc)
2219                         return rc;
2220
2221                 /* send DCBX attention request command */
2222                 DP_VERBOSE(p_hwfn,
2223                            QED_MSG_DCB,
2224                            "sending phony dcbx set command to trigger DCBx attention handling\n");
2225                 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2226                                  DRV_MSG_CODE_SET_DCBX,
2227                                  1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT,
2228                                  &resp, &param);
2229                 if (rc) {
2230                         DP_NOTICE(p_hwfn,
2231                                   "Failed to send DCBX attention request\n");
2232                         return rc;
2233                 }
2234
2235                 p_hwfn->hw_init_done = true;
2236         }
2237
2238         if (IS_PF(cdev)) {
2239                 p_hwfn = QED_LEADING_HWFN(cdev);
2240
2241                 /* Get pre-negotiated values for stag, bandwidth etc. */
2242                 DP_VERBOSE(p_hwfn,
2243                            QED_MSG_SPQ,
2244                            "Sending GET_OEM_UPDATES command to trigger stag/bandwidth attention handling\n");
2245                 drv_mb_param = 1 << DRV_MB_PARAM_DUMMY_OEM_UPDATES_OFFSET;
2246                 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2247                                  DRV_MSG_CODE_GET_OEM_UPDATES,
2248                                  drv_mb_param, &resp, &param);
2249                 if (rc)
2250                         DP_NOTICE(p_hwfn,
2251                                   "Failed to send GET_OEM_UPDATES attention request\n");
2252
2253                 drv_mb_param = STORM_FW_VERSION;
2254                 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2255                                  DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER,
2256                                  drv_mb_param, &load_code, &param);
2257                 if (rc)
2258                         DP_INFO(p_hwfn, "Failed to update firmware version\n");
2259
2260                 if (!b_default_mtu) {
2261                         rc = qed_mcp_ov_update_mtu(p_hwfn, p_hwfn->p_main_ptt,
2262                                                    p_hwfn->hw_info.mtu);
2263                         if (rc)
2264                                 DP_INFO(p_hwfn,
2265                                         "Failed to update default mtu\n");
2266                 }
2267
2268                 rc = qed_mcp_ov_update_driver_state(p_hwfn,
2269                                                     p_hwfn->p_main_ptt,
2270                                                   QED_OV_DRIVER_STATE_DISABLED);
2271                 if (rc)
2272                         DP_INFO(p_hwfn, "Failed to update driver state\n");
2273
2274                 rc = qed_mcp_ov_update_eswitch(p_hwfn, p_hwfn->p_main_ptt,
2275                                                QED_OV_ESWITCH_NONE);
2276                 if (rc)
2277                         DP_INFO(p_hwfn, "Failed to update eswitch mode\n");
2278         }
2279
2280         return 0;
2281
2282 load_err:
2283         /* The MFW load lock should be released also when initialization fails.
2284          */
2285         qed_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt);
2286         return rc;
2287 }
2288
2289 #define QED_HW_STOP_RETRY_LIMIT (10)
2290 static void qed_hw_timers_stop(struct qed_dev *cdev,
2291                                struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2292 {
2293         int i;
2294
2295         /* close timers */
2296         qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
2297         qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
2298
2299         if (cdev->recov_in_prog)
2300                 return;
2301
2302         for (i = 0; i < QED_HW_STOP_RETRY_LIMIT; i++) {
2303                 if ((!qed_rd(p_hwfn, p_ptt,
2304                              TM_REG_PF_SCAN_ACTIVE_CONN)) &&
2305                     (!qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
2306                         break;
2307
2308                 /* Dependent on number of connection/tasks, possibly
2309                  * 1ms sleep is required between polls
2310                  */
2311                 usleep_range(1000, 2000);
2312         }
2313
2314         if (i < QED_HW_STOP_RETRY_LIMIT)
2315                 return;
2316
2317         DP_NOTICE(p_hwfn,
2318                   "Timers linear scans are not over [Connection %02x Tasks %02x]\n",
2319                   (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
2320                   (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
2321 }
2322
2323 void qed_hw_timers_stop_all(struct qed_dev *cdev)
2324 {
2325         int j;
2326
2327         for_each_hwfn(cdev, j) {
2328                 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
2329                 struct qed_ptt *p_ptt = p_hwfn->p_main_ptt;
2330
2331                 qed_hw_timers_stop(cdev, p_hwfn, p_ptt);
2332         }
2333 }
2334
2335 int qed_hw_stop(struct qed_dev *cdev)
2336 {
2337         struct qed_hwfn *p_hwfn;
2338         struct qed_ptt *p_ptt;
2339         int rc, rc2 = 0;
2340         int j;
2341
2342         for_each_hwfn(cdev, j) {
2343                 p_hwfn = &cdev->hwfns[j];
2344                 p_ptt = p_hwfn->p_main_ptt;
2345
2346                 DP_VERBOSE(p_hwfn, NETIF_MSG_IFDOWN, "Stopping hw/fw\n");
2347
2348                 if (IS_VF(cdev)) {
2349                         qed_vf_pf_int_cleanup(p_hwfn);
2350                         rc = qed_vf_pf_reset(p_hwfn);
2351                         if (rc) {
2352                                 DP_NOTICE(p_hwfn,
2353                                           "qed_vf_pf_reset failed. rc = %d.\n",
2354                                           rc);
2355                                 rc2 = -EINVAL;
2356                         }
2357                         continue;
2358                 }
2359
2360                 /* mark the hw as uninitialized... */
2361                 p_hwfn->hw_init_done = false;
2362
2363                 /* Send unload command to MCP */
2364                 if (!cdev->recov_in_prog) {
2365                         rc = qed_mcp_unload_req(p_hwfn, p_ptt);
2366                         if (rc) {
2367                                 DP_NOTICE(p_hwfn,
2368                                           "Failed sending a UNLOAD_REQ command. rc = %d.\n",
2369                                           rc);
2370                                 rc2 = -EINVAL;
2371                         }
2372                 }
2373
2374                 qed_slowpath_irq_sync(p_hwfn);
2375
2376                 /* After this point no MFW attentions are expected, e.g. prevent
2377                  * race between pf stop and dcbx pf update.
2378                  */
2379                 rc = qed_sp_pf_stop(p_hwfn);
2380                 if (rc) {
2381                         DP_NOTICE(p_hwfn,
2382                                   "Failed to close PF against FW [rc = %d]. Continue to stop HW to prevent illegal host access by the device.\n",
2383                                   rc);
2384                         rc2 = -EINVAL;
2385                 }
2386
2387                 qed_wr(p_hwfn, p_ptt,
2388                        NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
2389
2390                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2391                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
2392                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
2393                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2394                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
2395
2396                 qed_hw_timers_stop(cdev, p_hwfn, p_ptt);
2397
2398                 /* Disable Attention Generation */
2399                 qed_int_igu_disable_int(p_hwfn, p_ptt);
2400
2401                 qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
2402                 qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
2403
2404                 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
2405
2406                 /* Need to wait 1ms to guarantee SBs are cleared */
2407                 usleep_range(1000, 2000);
2408
2409                 /* Disable PF in HW blocks */
2410                 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DB_ENABLE, 0);
2411                 qed_wr(p_hwfn, p_ptt, QM_REG_PF_EN, 0);
2412
2413                 if (!cdev->recov_in_prog) {
2414                         rc = qed_mcp_unload_done(p_hwfn, p_ptt);
2415                         if (rc) {
2416                                 DP_NOTICE(p_hwfn,
2417                                           "Failed sending a UNLOAD_DONE command. rc = %d.\n",
2418                                           rc);
2419                                 rc2 = -EINVAL;
2420                         }
2421                 }
2422         }
2423
2424         if (IS_PF(cdev) && !cdev->recov_in_prog) {
2425                 p_hwfn = QED_LEADING_HWFN(cdev);
2426                 p_ptt = QED_LEADING_HWFN(cdev)->p_main_ptt;
2427
2428                 /* Clear the PF's internal FID_enable in the PXP.
2429                  * In CMT this should only be done for first hw-function, and
2430                  * only after all transactions have stopped for all active
2431                  * hw-functions.
2432                  */
2433                 rc = qed_pglueb_set_pfid_enable(p_hwfn, p_ptt, false);
2434                 if (rc) {
2435                         DP_NOTICE(p_hwfn,
2436                                   "qed_pglueb_set_pfid_enable() failed. rc = %d.\n",
2437                                   rc);
2438                         rc2 = -EINVAL;
2439                 }
2440         }
2441
2442         return rc2;
2443 }
2444
2445 int qed_hw_stop_fastpath(struct qed_dev *cdev)
2446 {
2447         int j;
2448
2449         for_each_hwfn(cdev, j) {
2450                 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
2451                 struct qed_ptt *p_ptt;
2452
2453                 if (IS_VF(cdev)) {
2454                         qed_vf_pf_int_cleanup(p_hwfn);
2455                         continue;
2456                 }
2457                 p_ptt = qed_ptt_acquire(p_hwfn);
2458                 if (!p_ptt)
2459                         return -EAGAIN;
2460
2461                 DP_VERBOSE(p_hwfn,
2462                            NETIF_MSG_IFDOWN, "Shutting down the fastpath\n");
2463
2464                 qed_wr(p_hwfn, p_ptt,
2465                        NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
2466
2467                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2468                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
2469                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
2470                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2471                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
2472
2473                 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
2474
2475                 /* Need to wait 1ms to guarantee SBs are cleared */
2476                 usleep_range(1000, 2000);
2477                 qed_ptt_release(p_hwfn, p_ptt);
2478         }
2479
2480         return 0;
2481 }
2482
2483 int qed_hw_start_fastpath(struct qed_hwfn *p_hwfn)
2484 {
2485         struct qed_ptt *p_ptt;
2486
2487         if (IS_VF(p_hwfn->cdev))
2488                 return 0;
2489
2490         p_ptt = qed_ptt_acquire(p_hwfn);
2491         if (!p_ptt)
2492                 return -EAGAIN;
2493
2494         if (p_hwfn->p_rdma_info &&
2495             p_hwfn->p_rdma_info->active && p_hwfn->b_rdma_enabled_in_prs)
2496                 qed_wr(p_hwfn, p_ptt, p_hwfn->rdma_prs_search_reg, 0x1);
2497
2498         /* Re-open incoming traffic */
2499         qed_wr(p_hwfn, p_ptt, NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
2500         qed_ptt_release(p_hwfn, p_ptt);
2501
2502         return 0;
2503 }
2504
2505 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
2506 static void qed_hw_hwfn_free(struct qed_hwfn *p_hwfn)
2507 {
2508         qed_ptt_pool_free(p_hwfn);
2509         kfree(p_hwfn->hw_info.p_igu_info);
2510         p_hwfn->hw_info.p_igu_info = NULL;
2511 }
2512
2513 /* Setup bar access */
2514 static void qed_hw_hwfn_prepare(struct qed_hwfn *p_hwfn)
2515 {
2516         /* clear indirect access */
2517         if (QED_IS_AH(p_hwfn->cdev)) {
2518                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2519                        PGLUE_B_REG_PGL_ADDR_E8_F0_K2, 0);
2520                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2521                        PGLUE_B_REG_PGL_ADDR_EC_F0_K2, 0);
2522                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2523                        PGLUE_B_REG_PGL_ADDR_F0_F0_K2, 0);
2524                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2525                        PGLUE_B_REG_PGL_ADDR_F4_F0_K2, 0);
2526         } else {
2527                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2528                        PGLUE_B_REG_PGL_ADDR_88_F0_BB, 0);
2529                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2530                        PGLUE_B_REG_PGL_ADDR_8C_F0_BB, 0);
2531                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2532                        PGLUE_B_REG_PGL_ADDR_90_F0_BB, 0);
2533                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2534                        PGLUE_B_REG_PGL_ADDR_94_F0_BB, 0);
2535         }
2536
2537         /* Clean previous pglue_b errors if such exist */
2538         qed_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt);
2539
2540         /* enable internal target-read */
2541         qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2542                PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
2543 }
2544
2545 static void get_function_id(struct qed_hwfn *p_hwfn)
2546 {
2547         /* ME Register */
2548         p_hwfn->hw_info.opaque_fid = (u16) REG_RD(p_hwfn,
2549                                                   PXP_PF_ME_OPAQUE_ADDR);
2550
2551         p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
2552
2553         p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
2554         p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2555                                       PXP_CONCRETE_FID_PFID);
2556         p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2557                                     PXP_CONCRETE_FID_PORT);
2558
2559         DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE,
2560                    "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
2561                    p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
2562 }
2563
2564 static void qed_hw_set_feat(struct qed_hwfn *p_hwfn)
2565 {
2566         u32 *feat_num = p_hwfn->hw_info.feat_num;
2567         struct qed_sb_cnt_info sb_cnt;
2568         u32 non_l2_sbs = 0;
2569
2570         memset(&sb_cnt, 0, sizeof(sb_cnt));
2571         qed_int_get_num_sbs(p_hwfn, &sb_cnt);
2572
2573         if (IS_ENABLED(CONFIG_QED_RDMA) &&
2574             QED_IS_RDMA_PERSONALITY(p_hwfn)) {
2575                 /* Roce CNQ each requires: 1 status block + 1 CNQ. We divide
2576                  * the status blocks equally between L2 / RoCE but with
2577                  * consideration as to how many l2 queues / cnqs we have.
2578                  */
2579                 feat_num[QED_RDMA_CNQ] =
2580                         min_t(u32, sb_cnt.cnt / 2,
2581                               RESC_NUM(p_hwfn, QED_RDMA_CNQ_RAM));
2582
2583                 non_l2_sbs = feat_num[QED_RDMA_CNQ];
2584         }
2585         if (QED_IS_L2_PERSONALITY(p_hwfn)) {
2586                 /* Start by allocating VF queues, then PF's */
2587                 feat_num[QED_VF_L2_QUE] = min_t(u32,
2588                                                 RESC_NUM(p_hwfn, QED_L2_QUEUE),
2589                                                 sb_cnt.iov_cnt);
2590                 feat_num[QED_PF_L2_QUE] = min_t(u32,
2591                                                 sb_cnt.cnt - non_l2_sbs,
2592                                                 RESC_NUM(p_hwfn,
2593                                                          QED_L2_QUEUE) -
2594                                                 FEAT_NUM(p_hwfn,
2595                                                          QED_VF_L2_QUE));
2596         }
2597
2598         if (QED_IS_FCOE_PERSONALITY(p_hwfn))
2599                 feat_num[QED_FCOE_CQ] =  min_t(u32, sb_cnt.cnt,
2600                                                RESC_NUM(p_hwfn,
2601                                                         QED_CMDQS_CQS));
2602
2603         if (QED_IS_ISCSI_PERSONALITY(p_hwfn))
2604                 feat_num[QED_ISCSI_CQ] = min_t(u32, sb_cnt.cnt,
2605                                                RESC_NUM(p_hwfn,
2606                                                         QED_CMDQS_CQS));
2607         DP_VERBOSE(p_hwfn,
2608                    NETIF_MSG_PROBE,
2609                    "#PF_L2_QUEUES=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d FCOE_CQ=%d ISCSI_CQ=%d #SBS=%d\n",
2610                    (int)FEAT_NUM(p_hwfn, QED_PF_L2_QUE),
2611                    (int)FEAT_NUM(p_hwfn, QED_VF_L2_QUE),
2612                    (int)FEAT_NUM(p_hwfn, QED_RDMA_CNQ),
2613                    (int)FEAT_NUM(p_hwfn, QED_FCOE_CQ),
2614                    (int)FEAT_NUM(p_hwfn, QED_ISCSI_CQ),
2615                    (int)sb_cnt.cnt);
2616 }
2617
2618 const char *qed_hw_get_resc_name(enum qed_resources res_id)
2619 {
2620         switch (res_id) {
2621         case QED_L2_QUEUE:
2622                 return "L2_QUEUE";
2623         case QED_VPORT:
2624                 return "VPORT";
2625         case QED_RSS_ENG:
2626                 return "RSS_ENG";
2627         case QED_PQ:
2628                 return "PQ";
2629         case QED_RL:
2630                 return "RL";
2631         case QED_MAC:
2632                 return "MAC";
2633         case QED_VLAN:
2634                 return "VLAN";
2635         case QED_RDMA_CNQ_RAM:
2636                 return "RDMA_CNQ_RAM";
2637         case QED_ILT:
2638                 return "ILT";
2639         case QED_LL2_QUEUE:
2640                 return "LL2_QUEUE";
2641         case QED_CMDQS_CQS:
2642                 return "CMDQS_CQS";
2643         case QED_RDMA_STATS_QUEUE:
2644                 return "RDMA_STATS_QUEUE";
2645         case QED_BDQ:
2646                 return "BDQ";
2647         case QED_SB:
2648                 return "SB";
2649         default:
2650                 return "UNKNOWN_RESOURCE";
2651         }
2652 }
2653
2654 static int
2655 __qed_hw_set_soft_resc_size(struct qed_hwfn *p_hwfn,
2656                             struct qed_ptt *p_ptt,
2657                             enum qed_resources res_id,
2658                             u32 resc_max_val, u32 *p_mcp_resp)
2659 {
2660         int rc;
2661
2662         rc = qed_mcp_set_resc_max_val(p_hwfn, p_ptt, res_id,
2663                                       resc_max_val, p_mcp_resp);
2664         if (rc) {
2665                 DP_NOTICE(p_hwfn,
2666                           "MFW response failure for a max value setting of resource %d [%s]\n",
2667                           res_id, qed_hw_get_resc_name(res_id));
2668                 return rc;
2669         }
2670
2671         if (*p_mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK)
2672                 DP_INFO(p_hwfn,
2673                         "Failed to set the max value of resource %d [%s]. mcp_resp = 0x%08x.\n",
2674                         res_id, qed_hw_get_resc_name(res_id), *p_mcp_resp);
2675
2676         return 0;
2677 }
2678
2679 static int
2680 qed_hw_set_soft_resc_size(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2681 {
2682         bool b_ah = QED_IS_AH(p_hwfn->cdev);
2683         u32 resc_max_val, mcp_resp;
2684         u8 res_id;
2685         int rc;
2686
2687         for (res_id = 0; res_id < QED_MAX_RESC; res_id++) {
2688                 switch (res_id) {
2689                 case QED_LL2_QUEUE:
2690                         resc_max_val = MAX_NUM_LL2_RX_QUEUES;
2691                         break;
2692                 case QED_RDMA_CNQ_RAM:
2693                         /* No need for a case for QED_CMDQS_CQS since
2694                          * CNQ/CMDQS are the same resource.
2695                          */
2696                         resc_max_val = NUM_OF_GLOBAL_QUEUES;
2697                         break;
2698                 case QED_RDMA_STATS_QUEUE:
2699                         resc_max_val = b_ah ? RDMA_NUM_STATISTIC_COUNTERS_K2
2700                             : RDMA_NUM_STATISTIC_COUNTERS_BB;
2701                         break;
2702                 case QED_BDQ:
2703                         resc_max_val = BDQ_NUM_RESOURCES;
2704                         break;
2705                 default:
2706                         continue;
2707                 }
2708
2709                 rc = __qed_hw_set_soft_resc_size(p_hwfn, p_ptt, res_id,
2710                                                  resc_max_val, &mcp_resp);
2711                 if (rc)
2712                         return rc;
2713
2714                 /* There's no point to continue to the next resource if the
2715                  * command is not supported by the MFW.
2716                  * We do continue if the command is supported but the resource
2717                  * is unknown to the MFW. Such a resource will be later
2718                  * configured with the default allocation values.
2719                  */
2720                 if (mcp_resp == FW_MSG_CODE_UNSUPPORTED)
2721                         return -EINVAL;
2722         }
2723
2724         return 0;
2725 }
2726
2727 static
2728 int qed_hw_get_dflt_resc(struct qed_hwfn *p_hwfn,
2729                          enum qed_resources res_id,
2730                          u32 *p_resc_num, u32 *p_resc_start)
2731 {
2732         u8 num_funcs = p_hwfn->num_funcs_on_engine;
2733         bool b_ah = QED_IS_AH(p_hwfn->cdev);
2734
2735         switch (res_id) {
2736         case QED_L2_QUEUE:
2737                 *p_resc_num = (b_ah ? MAX_NUM_L2_QUEUES_K2 :
2738                                MAX_NUM_L2_QUEUES_BB) / num_funcs;
2739                 break;
2740         case QED_VPORT:
2741                 *p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
2742                                MAX_NUM_VPORTS_BB) / num_funcs;
2743                 break;
2744         case QED_RSS_ENG:
2745                 *p_resc_num = (b_ah ? ETH_RSS_ENGINE_NUM_K2 :
2746                                ETH_RSS_ENGINE_NUM_BB) / num_funcs;
2747                 break;
2748         case QED_PQ:
2749                 *p_resc_num = (b_ah ? MAX_QM_TX_QUEUES_K2 :
2750                                MAX_QM_TX_QUEUES_BB) / num_funcs;
2751                 *p_resc_num &= ~0x7;    /* The granularity of the PQs is 8 */
2752                 break;
2753         case QED_RL:
2754                 *p_resc_num = MAX_QM_GLOBAL_RLS / num_funcs;
2755                 break;
2756         case QED_MAC:
2757         case QED_VLAN:
2758                 /* Each VFC resource can accommodate both a MAC and a VLAN */
2759                 *p_resc_num = ETH_NUM_MAC_FILTERS / num_funcs;
2760                 break;
2761         case QED_ILT:
2762                 *p_resc_num = (b_ah ? PXP_NUM_ILT_RECORDS_K2 :
2763                                PXP_NUM_ILT_RECORDS_BB) / num_funcs;
2764                 break;
2765         case QED_LL2_QUEUE:
2766                 *p_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs;
2767                 break;
2768         case QED_RDMA_CNQ_RAM:
2769         case QED_CMDQS_CQS:
2770                 /* CNQ/CMDQS are the same resource */
2771                 *p_resc_num = NUM_OF_GLOBAL_QUEUES / num_funcs;
2772                 break;
2773         case QED_RDMA_STATS_QUEUE:
2774                 *p_resc_num = (b_ah ? RDMA_NUM_STATISTIC_COUNTERS_K2 :
2775                                RDMA_NUM_STATISTIC_COUNTERS_BB) / num_funcs;
2776                 break;
2777         case QED_BDQ:
2778                 if (p_hwfn->hw_info.personality != QED_PCI_ISCSI &&
2779                     p_hwfn->hw_info.personality != QED_PCI_FCOE)
2780                         *p_resc_num = 0;
2781                 else
2782                         *p_resc_num = 1;
2783                 break;
2784         case QED_SB:
2785                 /* Since we want its value to reflect whether MFW supports
2786                  * the new scheme, have a default of 0.
2787                  */
2788                 *p_resc_num = 0;
2789                 break;
2790         default:
2791                 return -EINVAL;
2792         }
2793
2794         switch (res_id) {
2795         case QED_BDQ:
2796                 if (!*p_resc_num)
2797                         *p_resc_start = 0;
2798                 else if (p_hwfn->cdev->num_ports_in_engine == 4)
2799                         *p_resc_start = p_hwfn->port_id;
2800                 else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI)
2801                         *p_resc_start = p_hwfn->port_id;
2802                 else if (p_hwfn->hw_info.personality == QED_PCI_FCOE)
2803                         *p_resc_start = p_hwfn->port_id + 2;
2804                 break;
2805         default:
2806                 *p_resc_start = *p_resc_num * p_hwfn->enabled_func_idx;
2807                 break;
2808         }
2809
2810         return 0;
2811 }
2812
2813 static int __qed_hw_set_resc_info(struct qed_hwfn *p_hwfn,
2814                                   enum qed_resources res_id)
2815 {
2816         u32 dflt_resc_num = 0, dflt_resc_start = 0;
2817         u32 mcp_resp, *p_resc_num, *p_resc_start;
2818         int rc;
2819
2820         p_resc_num = &RESC_NUM(p_hwfn, res_id);
2821         p_resc_start = &RESC_START(p_hwfn, res_id);
2822
2823         rc = qed_hw_get_dflt_resc(p_hwfn, res_id, &dflt_resc_num,
2824                                   &dflt_resc_start);
2825         if (rc) {
2826                 DP_ERR(p_hwfn,
2827                        "Failed to get default amount for resource %d [%s]\n",
2828                        res_id, qed_hw_get_resc_name(res_id));
2829                 return rc;
2830         }
2831
2832         rc = qed_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, res_id,
2833                                    &mcp_resp, p_resc_num, p_resc_start);
2834         if (rc) {
2835                 DP_NOTICE(p_hwfn,
2836                           "MFW response failure for an allocation request for resource %d [%s]\n",
2837                           res_id, qed_hw_get_resc_name(res_id));
2838                 return rc;
2839         }
2840
2841         /* Default driver values are applied in the following cases:
2842          * - The resource allocation MB command is not supported by the MFW
2843          * - There is an internal error in the MFW while processing the request
2844          * - The resource ID is unknown to the MFW
2845          */
2846         if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK) {
2847                 DP_INFO(p_hwfn,
2848                         "Failed to receive allocation info for resource %d [%s]. mcp_resp = 0x%x. Applying default values [%d,%d].\n",
2849                         res_id,
2850                         qed_hw_get_resc_name(res_id),
2851                         mcp_resp, dflt_resc_num, dflt_resc_start);
2852                 *p_resc_num = dflt_resc_num;
2853                 *p_resc_start = dflt_resc_start;
2854                 goto out;
2855         }
2856
2857 out:
2858         /* PQs have to divide by 8 [that's the HW granularity].
2859          * Reduce number so it would fit.
2860          */
2861         if ((res_id == QED_PQ) && ((*p_resc_num % 8) || (*p_resc_start % 8))) {
2862                 DP_INFO(p_hwfn,
2863                         "PQs need to align by 8; Number %08x --> %08x, Start %08x --> %08x\n",
2864                         *p_resc_num,
2865                         (*p_resc_num) & ~0x7,
2866                         *p_resc_start, (*p_resc_start) & ~0x7);
2867                 *p_resc_num &= ~0x7;
2868                 *p_resc_start &= ~0x7;
2869         }
2870
2871         return 0;
2872 }
2873
2874 static int qed_hw_set_resc_info(struct qed_hwfn *p_hwfn)
2875 {
2876         int rc;
2877         u8 res_id;
2878
2879         for (res_id = 0; res_id < QED_MAX_RESC; res_id++) {
2880                 rc = __qed_hw_set_resc_info(p_hwfn, res_id);
2881                 if (rc)
2882                         return rc;
2883         }
2884
2885         return 0;
2886 }
2887
2888 static int qed_hw_get_resc(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2889 {
2890         struct qed_resc_unlock_params resc_unlock_params;
2891         struct qed_resc_lock_params resc_lock_params;
2892         bool b_ah = QED_IS_AH(p_hwfn->cdev);
2893         u8 res_id;
2894         int rc;
2895
2896         /* Setting the max values of the soft resources and the following
2897          * resources allocation queries should be atomic. Since several PFs can
2898          * run in parallel - a resource lock is needed.
2899          * If either the resource lock or resource set value commands are not
2900          * supported - skip the the max values setting, release the lock if
2901          * needed, and proceed to the queries. Other failures, including a
2902          * failure to acquire the lock, will cause this function to fail.
2903          */
2904         qed_mcp_resc_lock_default_init(&resc_lock_params, &resc_unlock_params,
2905                                        QED_RESC_LOCK_RESC_ALLOC, false);
2906
2907         rc = qed_mcp_resc_lock(p_hwfn, p_ptt, &resc_lock_params);
2908         if (rc && rc != -EINVAL) {
2909                 return rc;
2910         } else if (rc == -EINVAL) {
2911                 DP_INFO(p_hwfn,
2912                         "Skip the max values setting of the soft resources since the resource lock is not supported by the MFW\n");
2913         } else if (!rc && !resc_lock_params.b_granted) {
2914                 DP_NOTICE(p_hwfn,
2915                           "Failed to acquire the resource lock for the resource allocation commands\n");
2916                 return -EBUSY;
2917         } else {
2918                 rc = qed_hw_set_soft_resc_size(p_hwfn, p_ptt);
2919                 if (rc && rc != -EINVAL) {
2920                         DP_NOTICE(p_hwfn,
2921                                   "Failed to set the max values of the soft resources\n");
2922                         goto unlock_and_exit;
2923                 } else if (rc == -EINVAL) {
2924                         DP_INFO(p_hwfn,
2925                                 "Skip the max values setting of the soft resources since it is not supported by the MFW\n");
2926                         rc = qed_mcp_resc_unlock(p_hwfn, p_ptt,
2927                                                  &resc_unlock_params);
2928                         if (rc)
2929                                 DP_INFO(p_hwfn,
2930                                         "Failed to release the resource lock for the resource allocation commands\n");
2931                 }
2932         }
2933
2934         rc = qed_hw_set_resc_info(p_hwfn);
2935         if (rc)
2936                 goto unlock_and_exit;
2937
2938         if (resc_lock_params.b_granted && !resc_unlock_params.b_released) {
2939                 rc = qed_mcp_resc_unlock(p_hwfn, p_ptt, &resc_unlock_params);
2940                 if (rc)
2941                         DP_INFO(p_hwfn,
2942                                 "Failed to release the resource lock for the resource allocation commands\n");
2943         }
2944
2945         /* Sanity for ILT */
2946         if ((b_ah && (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_K2)) ||
2947             (!b_ah && (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_BB))) {
2948                 DP_NOTICE(p_hwfn, "Can't assign ILT pages [%08x,...,%08x]\n",
2949                           RESC_START(p_hwfn, QED_ILT),
2950                           RESC_END(p_hwfn, QED_ILT) - 1);
2951                 return -EINVAL;
2952         }
2953
2954         /* This will also learn the number of SBs from MFW */
2955         if (qed_int_igu_reset_cam(p_hwfn, p_ptt))
2956                 return -EINVAL;
2957
2958         qed_hw_set_feat(p_hwfn);
2959
2960         for (res_id = 0; res_id < QED_MAX_RESC; res_id++)
2961                 DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE, "%s = %d start = %d\n",
2962                            qed_hw_get_resc_name(res_id),
2963                            RESC_NUM(p_hwfn, res_id),
2964                            RESC_START(p_hwfn, res_id));
2965
2966         return 0;
2967
2968 unlock_and_exit:
2969         if (resc_lock_params.b_granted && !resc_unlock_params.b_released)
2970                 qed_mcp_resc_unlock(p_hwfn, p_ptt, &resc_unlock_params);
2971         return rc;
2972 }
2973
2974 static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2975 {
2976         u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
2977         u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg;
2978         struct qed_mcp_link_capabilities *p_caps;
2979         struct qed_mcp_link_params *link;
2980
2981         /* Read global nvm_cfg address */
2982         nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
2983
2984         /* Verify MCP has initialized it */
2985         if (!nvm_cfg_addr) {
2986                 DP_NOTICE(p_hwfn, "Shared memory not initialized\n");
2987                 return -EINVAL;
2988         }
2989
2990         /* Read nvm_cfg1  (Notice this is just offset, and not offsize (TBD) */
2991         nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
2992
2993         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2994                offsetof(struct nvm_cfg1, glob) +
2995                offsetof(struct nvm_cfg1_glob, core_cfg);
2996
2997         core_cfg = qed_rd(p_hwfn, p_ptt, addr);
2998
2999         switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
3000                 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
3001         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
3002                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X40G;
3003                 break;
3004         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
3005                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X50G;
3006                 break;
3007         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
3008                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X100G;
3009                 break;
3010         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
3011                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_F;
3012                 break;
3013         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
3014                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_E;
3015                 break;
3016         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
3017                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X20G;
3018                 break;
3019         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
3020                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X40G;
3021                 break;
3022         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
3023                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X25G;
3024                 break;
3025         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G:
3026                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X10G;
3027                 break;
3028         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
3029                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X25G;
3030                 break;
3031         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G:
3032                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X25G;
3033                 break;
3034         default:
3035                 DP_NOTICE(p_hwfn, "Unknown port mode in 0x%08x\n", core_cfg);
3036                 break;
3037         }
3038
3039         /* Read default link configuration */
3040         link = &p_hwfn->mcp_info->link_input;
3041         p_caps = &p_hwfn->mcp_info->link_capabilities;
3042         port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3043                         offsetof(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
3044         link_temp = qed_rd(p_hwfn, p_ptt,
3045                            port_cfg_addr +
3046                            offsetof(struct nvm_cfg1_port, speed_cap_mask));
3047         link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
3048         link->speed.advertised_speeds = link_temp;
3049
3050         link_temp = link->speed.advertised_speeds;
3051         p_hwfn->mcp_info->link_capabilities.speed_capabilities = link_temp;
3052
3053         link_temp = qed_rd(p_hwfn, p_ptt,
3054                            port_cfg_addr +
3055                            offsetof(struct nvm_cfg1_port, link_settings));
3056         switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
3057                 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
3058         case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
3059                 link->speed.autoneg = true;
3060                 break;
3061         case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
3062                 link->speed.forced_speed = 1000;
3063                 break;
3064         case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
3065                 link->speed.forced_speed = 10000;
3066                 break;
3067         case NVM_CFG1_PORT_DRV_LINK_SPEED_20G:
3068                 link->speed.forced_speed = 20000;
3069                 break;
3070         case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
3071                 link->speed.forced_speed = 25000;
3072                 break;
3073         case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
3074                 link->speed.forced_speed = 40000;
3075                 break;
3076         case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
3077                 link->speed.forced_speed = 50000;
3078                 break;
3079         case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
3080                 link->speed.forced_speed = 100000;
3081                 break;
3082         default:
3083                 DP_NOTICE(p_hwfn, "Unknown Speed in 0x%08x\n", link_temp);
3084         }
3085
3086         p_hwfn->mcp_info->link_capabilities.default_speed_autoneg =
3087                 link->speed.autoneg;
3088
3089         link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
3090         link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
3091         link->pause.autoneg = !!(link_temp &
3092                                  NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
3093         link->pause.forced_rx = !!(link_temp &
3094                                    NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
3095         link->pause.forced_tx = !!(link_temp &
3096                                    NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
3097         link->loopback_mode = 0;
3098
3099         if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE) {
3100                 link_temp = qed_rd(p_hwfn, p_ptt, port_cfg_addr +
3101                                    offsetof(struct nvm_cfg1_port, ext_phy));
3102                 link_temp &= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK;
3103                 link_temp >>= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET;
3104                 p_caps->default_eee = QED_MCP_EEE_ENABLED;
3105                 link->eee.enable = true;
3106                 switch (link_temp) {
3107                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED:
3108                         p_caps->default_eee = QED_MCP_EEE_DISABLED;
3109                         link->eee.enable = false;
3110                         break;
3111                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED:
3112                         p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_BALANCED_TIME;
3113                         break;
3114                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE:
3115                         p_caps->eee_lpi_timer =
3116                             EEE_TX_TIMER_USEC_AGGRESSIVE_TIME;
3117                         break;
3118                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY:
3119                         p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_LATENCY_TIME;
3120                         break;
3121                 }
3122
3123                 link->eee.tx_lpi_timer = p_caps->eee_lpi_timer;
3124                 link->eee.tx_lpi_enable = link->eee.enable;
3125                 link->eee.adv_caps = QED_EEE_1G_ADV | QED_EEE_10G_ADV;
3126         } else {
3127                 p_caps->default_eee = QED_MCP_EEE_UNSUPPORTED;
3128         }
3129
3130         DP_VERBOSE(p_hwfn,
3131                    NETIF_MSG_LINK,
3132                    "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x EEE: %02x [%08x usec]\n",
3133                    link->speed.forced_speed,
3134                    link->speed.advertised_speeds,
3135                    link->speed.autoneg,
3136                    link->pause.autoneg,
3137                    p_caps->default_eee, p_caps->eee_lpi_timer);
3138
3139         if (IS_LEAD_HWFN(p_hwfn)) {
3140                 struct qed_dev *cdev = p_hwfn->cdev;
3141
3142                 /* Read Multi-function information from shmem */
3143                 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3144                        offsetof(struct nvm_cfg1, glob) +
3145                        offsetof(struct nvm_cfg1_glob, generic_cont0);
3146
3147                 generic_cont0 = qed_rd(p_hwfn, p_ptt, addr);
3148
3149                 mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
3150                           NVM_CFG1_GLOB_MF_MODE_OFFSET;
3151
3152                 switch (mf_mode) {
3153                 case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
3154                         cdev->mf_bits = BIT(QED_MF_OVLAN_CLSS);
3155                         break;
3156                 case NVM_CFG1_GLOB_MF_MODE_UFP:
3157                         cdev->mf_bits = BIT(QED_MF_OVLAN_CLSS) |
3158                                         BIT(QED_MF_LLH_PROTO_CLSS) |
3159                                         BIT(QED_MF_UFP_SPECIFIC) |
3160                                         BIT(QED_MF_8021Q_TAGGING);
3161                         break;
3162                 case NVM_CFG1_GLOB_MF_MODE_BD:
3163                         cdev->mf_bits = BIT(QED_MF_OVLAN_CLSS) |
3164                                         BIT(QED_MF_LLH_PROTO_CLSS) |
3165                                         BIT(QED_MF_8021AD_TAGGING);
3166                         break;
3167                 case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
3168                         cdev->mf_bits = BIT(QED_MF_LLH_MAC_CLSS) |
3169                                         BIT(QED_MF_LLH_PROTO_CLSS) |
3170                                         BIT(QED_MF_LL2_NON_UNICAST) |
3171                                         BIT(QED_MF_INTER_PF_SWITCH);
3172                         break;
3173                 case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
3174                         cdev->mf_bits = BIT(QED_MF_LLH_MAC_CLSS) |
3175                                         BIT(QED_MF_LLH_PROTO_CLSS) |
3176                                         BIT(QED_MF_LL2_NON_UNICAST);
3177                         if (QED_IS_BB(p_hwfn->cdev))
3178                                 cdev->mf_bits |= BIT(QED_MF_NEED_DEF_PF);
3179                         break;
3180                 }
3181
3182                 DP_INFO(p_hwfn, "Multi function mode is 0x%lx\n",
3183                         cdev->mf_bits);
3184         }
3185
3186         DP_INFO(p_hwfn, "Multi function mode is 0x%lx\n",
3187                 p_hwfn->cdev->mf_bits);
3188
3189         /* Read device capabilities information from shmem */
3190         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3191                 offsetof(struct nvm_cfg1, glob) +
3192                 offsetof(struct nvm_cfg1_glob, device_capabilities);
3193
3194         device_capabilities = qed_rd(p_hwfn, p_ptt, addr);
3195         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
3196                 __set_bit(QED_DEV_CAP_ETH,
3197                           &p_hwfn->hw_info.device_capabilities);
3198         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE)
3199                 __set_bit(QED_DEV_CAP_FCOE,
3200                           &p_hwfn->hw_info.device_capabilities);
3201         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
3202                 __set_bit(QED_DEV_CAP_ISCSI,
3203                           &p_hwfn->hw_info.device_capabilities);
3204         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
3205                 __set_bit(QED_DEV_CAP_ROCE,
3206                           &p_hwfn->hw_info.device_capabilities);
3207
3208         return qed_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
3209 }
3210
3211 static void qed_get_num_funcs(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
3212 {
3213         u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
3214         u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
3215         struct qed_dev *cdev = p_hwfn->cdev;
3216
3217         num_funcs = QED_IS_AH(cdev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB;
3218
3219         /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
3220          * in the other bits are selected.
3221          * Bits 1-15 are for functions 1-15, respectively, and their value is
3222          * '0' only for enabled functions (function 0 always exists and
3223          * enabled).
3224          * In case of CMT, only the "even" functions are enabled, and thus the
3225          * number of functions for both hwfns is learnt from the same bits.
3226          */
3227         reg_function_hide = qed_rd(p_hwfn, p_ptt, MISCS_REG_FUNCTION_HIDE);
3228
3229         if (reg_function_hide & 0x1) {
3230                 if (QED_IS_BB(cdev)) {
3231                         if (QED_PATH_ID(p_hwfn) && cdev->num_hwfns == 1) {
3232                                 num_funcs = 0;
3233                                 eng_mask = 0xaaaa;
3234                         } else {
3235                                 num_funcs = 1;
3236                                 eng_mask = 0x5554;
3237                         }
3238                 } else {
3239                         num_funcs = 1;
3240                         eng_mask = 0xfffe;
3241                 }
3242
3243                 /* Get the number of the enabled functions on the engine */
3244                 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
3245                 while (tmp) {
3246                         if (tmp & 0x1)
3247                                 num_funcs++;
3248                         tmp >>= 0x1;
3249                 }
3250
3251                 /* Get the PF index within the enabled functions */
3252                 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
3253                 tmp = reg_function_hide & eng_mask & low_pfs_mask;
3254                 while (tmp) {
3255                         if (tmp & 0x1)
3256                                 enabled_func_idx--;
3257                         tmp >>= 0x1;
3258                 }
3259         }
3260
3261         p_hwfn->num_funcs_on_engine = num_funcs;
3262         p_hwfn->enabled_func_idx = enabled_func_idx;
3263
3264         DP_VERBOSE(p_hwfn,
3265                    NETIF_MSG_PROBE,
3266                    "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n",
3267                    p_hwfn->rel_pf_id,
3268                    p_hwfn->abs_pf_id,
3269                    p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);
3270 }
3271
3272 static void qed_hw_info_port_num(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
3273 {
3274         u32 addr, global_offsize, global_addr, port_mode;
3275         struct qed_dev *cdev = p_hwfn->cdev;
3276
3277         /* In CMT there is always only one port */
3278         if (cdev->num_hwfns > 1) {
3279                 cdev->num_ports_in_engine = 1;
3280                 cdev->num_ports = 1;
3281                 return;
3282         }
3283
3284         /* Determine the number of ports per engine */
3285         port_mode = qed_rd(p_hwfn, p_ptt, MISC_REG_PORT_MODE);
3286         switch (port_mode) {
3287         case 0x0:
3288                 cdev->num_ports_in_engine = 1;
3289                 break;
3290         case 0x1:
3291                 cdev->num_ports_in_engine = 2;
3292                 break;
3293         case 0x2:
3294                 cdev->num_ports_in_engine = 4;
3295                 break;
3296         default:
3297                 DP_NOTICE(p_hwfn, "Unknown port mode 0x%08x\n", port_mode);
3298                 cdev->num_ports_in_engine = 1;  /* Default to something */
3299                 break;
3300         }
3301
3302         /* Get the total number of ports of the device */
3303         addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
3304                                     PUBLIC_GLOBAL);
3305         global_offsize = qed_rd(p_hwfn, p_ptt, addr);
3306         global_addr = SECTION_ADDR(global_offsize, 0);
3307         addr = global_addr + offsetof(struct public_global, max_ports);
3308         cdev->num_ports = (u8)qed_rd(p_hwfn, p_ptt, addr);
3309 }
3310
3311 static void qed_get_eee_caps(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
3312 {
3313         struct qed_mcp_link_capabilities *p_caps;
3314         u32 eee_status;
3315
3316         p_caps = &p_hwfn->mcp_info->link_capabilities;
3317         if (p_caps->default_eee == QED_MCP_EEE_UNSUPPORTED)
3318                 return;
3319
3320         p_caps->eee_speed_caps = 0;
3321         eee_status = qed_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
3322                             offsetof(struct public_port, eee_status));
3323         eee_status = (eee_status & EEE_SUPPORTED_SPEED_MASK) >>
3324                         EEE_SUPPORTED_SPEED_OFFSET;
3325
3326         if (eee_status & EEE_1G_SUPPORTED)
3327                 p_caps->eee_speed_caps |= QED_EEE_1G_ADV;
3328         if (eee_status & EEE_10G_ADV)
3329                 p_caps->eee_speed_caps |= QED_EEE_10G_ADV;
3330 }
3331
3332 static int
3333 qed_get_hw_info(struct qed_hwfn *p_hwfn,
3334                 struct qed_ptt *p_ptt,
3335                 enum qed_pci_personality personality)
3336 {
3337         int rc;
3338
3339         /* Since all information is common, only first hwfns should do this */
3340         if (IS_LEAD_HWFN(p_hwfn)) {
3341                 rc = qed_iov_hw_info(p_hwfn);
3342                 if (rc)
3343                         return rc;
3344         }
3345
3346         if (IS_LEAD_HWFN(p_hwfn))
3347                 qed_hw_info_port_num(p_hwfn, p_ptt);
3348
3349         qed_mcp_get_capabilities(p_hwfn, p_ptt);
3350
3351         qed_hw_get_nvm_info(p_hwfn, p_ptt);
3352
3353         rc = qed_int_igu_read_cam(p_hwfn, p_ptt);
3354         if (rc)
3355                 return rc;
3356
3357         if (qed_mcp_is_init(p_hwfn))
3358                 ether_addr_copy(p_hwfn->hw_info.hw_mac_addr,
3359                                 p_hwfn->mcp_info->func_info.mac);
3360         else
3361                 eth_random_addr(p_hwfn->hw_info.hw_mac_addr);
3362
3363         if (qed_mcp_is_init(p_hwfn)) {
3364                 if (p_hwfn->mcp_info->func_info.ovlan != QED_MCP_VLAN_UNSET)
3365                         p_hwfn->hw_info.ovlan =
3366                                 p_hwfn->mcp_info->func_info.ovlan;
3367
3368                 qed_mcp_cmd_port_init(p_hwfn, p_ptt);
3369
3370                 qed_get_eee_caps(p_hwfn, p_ptt);
3371
3372                 qed_mcp_read_ufp_config(p_hwfn, p_ptt);
3373         }
3374
3375         if (qed_mcp_is_init(p_hwfn)) {
3376                 enum qed_pci_personality protocol;
3377
3378                 protocol = p_hwfn->mcp_info->func_info.protocol;
3379                 p_hwfn->hw_info.personality = protocol;
3380         }
3381
3382         if (QED_IS_ROCE_PERSONALITY(p_hwfn))
3383                 p_hwfn->hw_info.multi_tc_roce_en = 1;
3384
3385         p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2;
3386         p_hwfn->hw_info.num_active_tc = 1;
3387
3388         qed_get_num_funcs(p_hwfn, p_ptt);
3389
3390         if (qed_mcp_is_init(p_hwfn))
3391                 p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu;
3392
3393         return qed_hw_get_resc(p_hwfn, p_ptt);
3394 }
3395
3396 static int qed_get_dev_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
3397 {
3398         struct qed_dev *cdev = p_hwfn->cdev;
3399         u16 device_id_mask;
3400         u32 tmp;
3401
3402         /* Read Vendor Id / Device Id */
3403         pci_read_config_word(cdev->pdev, PCI_VENDOR_ID, &cdev->vendor_id);
3404         pci_read_config_word(cdev->pdev, PCI_DEVICE_ID, &cdev->device_id);
3405
3406         /* Determine type */
3407         device_id_mask = cdev->device_id & QED_DEV_ID_MASK;
3408         switch (device_id_mask) {
3409         case QED_DEV_ID_MASK_BB:
3410                 cdev->type = QED_DEV_TYPE_BB;
3411                 break;
3412         case QED_DEV_ID_MASK_AH:
3413                 cdev->type = QED_DEV_TYPE_AH;
3414                 break;
3415         default:
3416                 DP_NOTICE(p_hwfn, "Unknown device id 0x%x\n", cdev->device_id);
3417                 return -EBUSY;
3418         }
3419
3420         cdev->chip_num = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_NUM);
3421         cdev->chip_rev = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_REV);
3422
3423         MASK_FIELD(CHIP_REV, cdev->chip_rev);
3424
3425         /* Learn number of HW-functions */
3426         tmp = qed_rd(p_hwfn, p_ptt, MISCS_REG_CMT_ENABLED_FOR_PAIR);
3427
3428         if (tmp & (1 << p_hwfn->rel_pf_id)) {
3429                 DP_NOTICE(cdev->hwfns, "device in CMT mode\n");
3430                 cdev->num_hwfns = 2;
3431         } else {
3432                 cdev->num_hwfns = 1;
3433         }
3434
3435         cdev->chip_bond_id = qed_rd(p_hwfn, p_ptt,
3436                                     MISCS_REG_CHIP_TEST_REG) >> 4;
3437         MASK_FIELD(CHIP_BOND_ID, cdev->chip_bond_id);
3438         cdev->chip_metal = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_METAL);
3439         MASK_FIELD(CHIP_METAL, cdev->chip_metal);
3440
3441         DP_INFO(cdev->hwfns,
3442                 "Chip details - %s %c%d, Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n",
3443                 QED_IS_BB(cdev) ? "BB" : "AH",
3444                 'A' + cdev->chip_rev,
3445                 (int)cdev->chip_metal,
3446                 cdev->chip_num, cdev->chip_rev,
3447                 cdev->chip_bond_id, cdev->chip_metal);
3448
3449         return 0;
3450 }
3451
3452 static void qed_nvm_info_free(struct qed_hwfn *p_hwfn)
3453 {
3454         kfree(p_hwfn->nvm_info.image_att);
3455         p_hwfn->nvm_info.image_att = NULL;
3456 }
3457
3458 static int qed_hw_prepare_single(struct qed_hwfn *p_hwfn,
3459                                  void __iomem *p_regview,
3460                                  void __iomem *p_doorbells,
3461                                  enum qed_pci_personality personality)
3462 {
3463         struct qed_dev *cdev = p_hwfn->cdev;
3464         int rc = 0;
3465
3466         /* Split PCI bars evenly between hwfns */
3467         p_hwfn->regview = p_regview;
3468         p_hwfn->doorbells = p_doorbells;
3469
3470         if (IS_VF(p_hwfn->cdev))
3471                 return qed_vf_hw_prepare(p_hwfn);
3472
3473         /* Validate that chip access is feasible */
3474         if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
3475                 DP_ERR(p_hwfn,
3476                        "Reading the ME register returns all Fs; Preventing further chip access\n");
3477                 return -EINVAL;
3478         }
3479
3480         get_function_id(p_hwfn);
3481
3482         /* Allocate PTT pool */
3483         rc = qed_ptt_pool_alloc(p_hwfn);
3484         if (rc)
3485                 goto err0;
3486
3487         /* Allocate the main PTT */
3488         p_hwfn->p_main_ptt = qed_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
3489
3490         /* First hwfn learns basic information, e.g., number of hwfns */
3491         if (!p_hwfn->my_id) {
3492                 rc = qed_get_dev_info(p_hwfn, p_hwfn->p_main_ptt);
3493                 if (rc)
3494                         goto err1;
3495         }
3496
3497         qed_hw_hwfn_prepare(p_hwfn);
3498
3499         /* Initialize MCP structure */
3500         rc = qed_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
3501         if (rc) {
3502                 DP_NOTICE(p_hwfn, "Failed initializing mcp command\n");
3503                 goto err1;
3504         }
3505
3506         /* Read the device configuration information from the HW and SHMEM */
3507         rc = qed_get_hw_info(p_hwfn, p_hwfn->p_main_ptt, personality);
3508         if (rc) {
3509                 DP_NOTICE(p_hwfn, "Failed to get HW information\n");
3510                 goto err2;
3511         }
3512
3513         /* Sending a mailbox to the MFW should be done after qed_get_hw_info()
3514          * is called as it sets the ports number in an engine.
3515          */
3516         if (IS_LEAD_HWFN(p_hwfn) && !cdev->recov_in_prog) {
3517                 rc = qed_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt);
3518                 if (rc)
3519                         DP_NOTICE(p_hwfn, "Failed to initiate PF FLR\n");
3520         }
3521
3522         /* NVRAM info initialization and population */
3523         if (IS_LEAD_HWFN(p_hwfn)) {
3524                 rc = qed_mcp_nvm_info_populate(p_hwfn);
3525                 if (rc) {
3526                         DP_NOTICE(p_hwfn,
3527                                   "Failed to populate nvm info shadow\n");
3528                         goto err2;
3529                 }
3530         }
3531
3532         /* Allocate the init RT array and initialize the init-ops engine */
3533         rc = qed_init_alloc(p_hwfn);
3534         if (rc)
3535                 goto err3;
3536
3537         return rc;
3538 err3:
3539         if (IS_LEAD_HWFN(p_hwfn))
3540                 qed_nvm_info_free(p_hwfn);
3541 err2:
3542         if (IS_LEAD_HWFN(p_hwfn))
3543                 qed_iov_free_hw_info(p_hwfn->cdev);
3544         qed_mcp_free(p_hwfn);
3545 err1:
3546         qed_hw_hwfn_free(p_hwfn);
3547 err0:
3548         return rc;
3549 }
3550
3551 int qed_hw_prepare(struct qed_dev *cdev,
3552                    int personality)
3553 {
3554         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
3555         int rc;
3556
3557         /* Store the precompiled init data ptrs */
3558         if (IS_PF(cdev))
3559                 qed_init_iro_array(cdev);
3560
3561         /* Initialize the first hwfn - will learn number of hwfns */
3562         rc = qed_hw_prepare_single(p_hwfn,
3563                                    cdev->regview,
3564                                    cdev->doorbells, personality);
3565         if (rc)
3566                 return rc;
3567
3568         personality = p_hwfn->hw_info.personality;
3569
3570         /* Initialize the rest of the hwfns */
3571         if (cdev->num_hwfns > 1) {
3572                 void __iomem *p_regview, *p_doorbell;
3573                 u8 __iomem *addr;
3574
3575                 /* adjust bar offset for second engine */
3576                 addr = cdev->regview +
3577                        qed_hw_bar_size(p_hwfn, p_hwfn->p_main_ptt,
3578                                        BAR_ID_0) / 2;
3579                 p_regview = addr;
3580
3581                 addr = cdev->doorbells +
3582                        qed_hw_bar_size(p_hwfn, p_hwfn->p_main_ptt,
3583                                        BAR_ID_1) / 2;
3584                 p_doorbell = addr;
3585
3586                 /* prepare second hw function */
3587                 rc = qed_hw_prepare_single(&cdev->hwfns[1], p_regview,
3588                                            p_doorbell, personality);
3589
3590                 /* in case of error, need to free the previously
3591                  * initiliazed hwfn 0.
3592                  */
3593                 if (rc) {
3594                         if (IS_PF(cdev)) {
3595                                 qed_init_free(p_hwfn);
3596                                 qed_nvm_info_free(p_hwfn);
3597                                 qed_mcp_free(p_hwfn);
3598                                 qed_hw_hwfn_free(p_hwfn);
3599                         }
3600                 }
3601         }
3602
3603         return rc;
3604 }
3605
3606 void qed_hw_remove(struct qed_dev *cdev)
3607 {
3608         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
3609         int i;
3610
3611         if (IS_PF(cdev))
3612                 qed_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt,
3613                                                QED_OV_DRIVER_STATE_NOT_LOADED);
3614
3615         for_each_hwfn(cdev, i) {
3616                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
3617
3618                 if (IS_VF(cdev)) {
3619                         qed_vf_pf_release(p_hwfn);
3620                         continue;
3621                 }
3622
3623                 qed_init_free(p_hwfn);
3624                 qed_hw_hwfn_free(p_hwfn);
3625                 qed_mcp_free(p_hwfn);
3626         }
3627
3628         qed_iov_free_hw_info(cdev);
3629
3630         qed_nvm_info_free(p_hwfn);
3631 }
3632
3633 static void qed_chain_free_next_ptr(struct qed_dev *cdev,
3634                                     struct qed_chain *p_chain)
3635 {
3636         void *p_virt = p_chain->p_virt_addr, *p_virt_next = NULL;
3637         dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
3638         struct qed_chain_next *p_next;
3639         u32 size, i;
3640
3641         if (!p_virt)
3642                 return;
3643
3644         size = p_chain->elem_size * p_chain->usable_per_page;
3645
3646         for (i = 0; i < p_chain->page_cnt; i++) {
3647                 if (!p_virt)
3648                         break;
3649
3650                 p_next = (struct qed_chain_next *)((u8 *)p_virt + size);
3651                 p_virt_next = p_next->next_virt;
3652                 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
3653
3654                 dma_free_coherent(&cdev->pdev->dev,
3655                                   QED_CHAIN_PAGE_SIZE, p_virt, p_phys);
3656
3657                 p_virt = p_virt_next;
3658                 p_phys = p_phys_next;
3659         }
3660 }
3661
3662 static void qed_chain_free_single(struct qed_dev *cdev,
3663                                   struct qed_chain *p_chain)
3664 {
3665         if (!p_chain->p_virt_addr)
3666                 return;
3667
3668         dma_free_coherent(&cdev->pdev->dev,
3669                           QED_CHAIN_PAGE_SIZE,
3670                           p_chain->p_virt_addr, p_chain->p_phys_addr);
3671 }
3672
3673 static void qed_chain_free_pbl(struct qed_dev *cdev, struct qed_chain *p_chain)
3674 {
3675         void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl;
3676         u32 page_cnt = p_chain->page_cnt, i, pbl_size;
3677         u8 *p_pbl_virt = p_chain->pbl_sp.p_virt_table;
3678
3679         if (!pp_virt_addr_tbl)
3680                 return;
3681
3682         if (!p_pbl_virt)
3683                 goto out;
3684
3685         for (i = 0; i < page_cnt; i++) {
3686                 if (!pp_virt_addr_tbl[i])
3687                         break;
3688
3689                 dma_free_coherent(&cdev->pdev->dev,
3690                                   QED_CHAIN_PAGE_SIZE,
3691                                   pp_virt_addr_tbl[i],
3692                                   *(dma_addr_t *)p_pbl_virt);
3693
3694                 p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE;
3695         }
3696
3697         pbl_size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE;
3698
3699         if (!p_chain->b_external_pbl)
3700                 dma_free_coherent(&cdev->pdev->dev,
3701                                   pbl_size,
3702                                   p_chain->pbl_sp.p_virt_table,
3703                                   p_chain->pbl_sp.p_phys_table);
3704 out:
3705         vfree(p_chain->pbl.pp_virt_addr_tbl);
3706         p_chain->pbl.pp_virt_addr_tbl = NULL;
3707 }
3708
3709 void qed_chain_free(struct qed_dev *cdev, struct qed_chain *p_chain)
3710 {
3711         switch (p_chain->mode) {
3712         case QED_CHAIN_MODE_NEXT_PTR:
3713                 qed_chain_free_next_ptr(cdev, p_chain);
3714                 break;
3715         case QED_CHAIN_MODE_SINGLE:
3716                 qed_chain_free_single(cdev, p_chain);
3717                 break;
3718         case QED_CHAIN_MODE_PBL:
3719                 qed_chain_free_pbl(cdev, p_chain);
3720                 break;
3721         }
3722 }
3723
3724 static int
3725 qed_chain_alloc_sanity_check(struct qed_dev *cdev,
3726                              enum qed_chain_cnt_type cnt_type,
3727                              size_t elem_size, u32 page_cnt)
3728 {
3729         u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
3730
3731         /* The actual chain size can be larger than the maximal possible value
3732          * after rounding up the requested elements number to pages, and after
3733          * taking into acount the unusuable elements (next-ptr elements).
3734          * The size of a "u16" chain can be (U16_MAX + 1) since the chain
3735          * size/capacity fields are of a u32 type.
3736          */
3737         if ((cnt_type == QED_CHAIN_CNT_TYPE_U16 &&
3738              chain_size > ((u32)U16_MAX + 1)) ||
3739             (cnt_type == QED_CHAIN_CNT_TYPE_U32 && chain_size > U32_MAX)) {
3740                 DP_NOTICE(cdev,
3741                           "The actual chain size (0x%llx) is larger than the maximal possible value\n",
3742                           chain_size);
3743                 return -EINVAL;
3744         }
3745
3746         return 0;
3747 }
3748
3749 static int
3750 qed_chain_alloc_next_ptr(struct qed_dev *cdev, struct qed_chain *p_chain)
3751 {
3752         void *p_virt = NULL, *p_virt_prev = NULL;
3753         dma_addr_t p_phys = 0;
3754         u32 i;
3755
3756         for (i = 0; i < p_chain->page_cnt; i++) {
3757                 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
3758                                             QED_CHAIN_PAGE_SIZE,
3759                                             &p_phys, GFP_KERNEL);
3760                 if (!p_virt)
3761                         return -ENOMEM;
3762
3763                 if (i == 0) {
3764                         qed_chain_init_mem(p_chain, p_virt, p_phys);
3765                         qed_chain_reset(p_chain);
3766                 } else {
3767                         qed_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3768                                                      p_virt, p_phys);
3769                 }
3770
3771                 p_virt_prev = p_virt;
3772         }
3773         /* Last page's next element should point to the beginning of the
3774          * chain.
3775          */
3776         qed_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3777                                      p_chain->p_virt_addr,
3778                                      p_chain->p_phys_addr);
3779
3780         return 0;
3781 }
3782
3783 static int
3784 qed_chain_alloc_single(struct qed_dev *cdev, struct qed_chain *p_chain)
3785 {
3786         dma_addr_t p_phys = 0;
3787         void *p_virt = NULL;
3788
3789         p_virt = dma_alloc_coherent(&cdev->pdev->dev,
3790                                     QED_CHAIN_PAGE_SIZE, &p_phys, GFP_KERNEL);
3791         if (!p_virt)
3792                 return -ENOMEM;
3793
3794         qed_chain_init_mem(p_chain, p_virt, p_phys);
3795         qed_chain_reset(p_chain);
3796
3797         return 0;
3798 }
3799
3800 static int
3801 qed_chain_alloc_pbl(struct qed_dev *cdev,
3802                     struct qed_chain *p_chain,
3803                     struct qed_chain_ext_pbl *ext_pbl)
3804 {
3805         u32 page_cnt = p_chain->page_cnt, size, i;
3806         dma_addr_t p_phys = 0, p_pbl_phys = 0;
3807         void **pp_virt_addr_tbl = NULL;
3808         u8 *p_pbl_virt = NULL;
3809         void *p_virt = NULL;
3810
3811         size = page_cnt * sizeof(*pp_virt_addr_tbl);
3812         pp_virt_addr_tbl = vzalloc(size);
3813         if (!pp_virt_addr_tbl)
3814                 return -ENOMEM;
3815
3816         /* The allocation of the PBL table is done with its full size, since it
3817          * is expected to be successive.
3818          * qed_chain_init_pbl_mem() is called even in a case of an allocation
3819          * failure, since pp_virt_addr_tbl was previously allocated, and it
3820          * should be saved to allow its freeing during the error flow.
3821          */
3822         size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE;
3823
3824         if (!ext_pbl) {
3825                 p_pbl_virt = dma_alloc_coherent(&cdev->pdev->dev,
3826                                                 size, &p_pbl_phys, GFP_KERNEL);
3827         } else {
3828                 p_pbl_virt = ext_pbl->p_pbl_virt;
3829                 p_pbl_phys = ext_pbl->p_pbl_phys;
3830                 p_chain->b_external_pbl = true;
3831         }
3832
3833         qed_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys,
3834                                pp_virt_addr_tbl);
3835         if (!p_pbl_virt)
3836                 return -ENOMEM;
3837
3838         for (i = 0; i < page_cnt; i++) {
3839                 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
3840                                             QED_CHAIN_PAGE_SIZE,
3841                                             &p_phys, GFP_KERNEL);
3842                 if (!p_virt)
3843                         return -ENOMEM;
3844
3845                 if (i == 0) {
3846                         qed_chain_init_mem(p_chain, p_virt, p_phys);
3847                         qed_chain_reset(p_chain);
3848                 }
3849
3850                 /* Fill the PBL table with the physical address of the page */
3851                 *(dma_addr_t *)p_pbl_virt = p_phys;
3852                 /* Keep the virtual address of the page */
3853                 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt;
3854
3855                 p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE;
3856         }
3857
3858         return 0;
3859 }
3860
3861 int qed_chain_alloc(struct qed_dev *cdev,
3862                     enum qed_chain_use_mode intended_use,
3863                     enum qed_chain_mode mode,
3864                     enum qed_chain_cnt_type cnt_type,
3865                     u32 num_elems,
3866                     size_t elem_size,
3867                     struct qed_chain *p_chain,
3868                     struct qed_chain_ext_pbl *ext_pbl)
3869 {
3870         u32 page_cnt;
3871         int rc = 0;
3872
3873         if (mode == QED_CHAIN_MODE_SINGLE)
3874                 page_cnt = 1;
3875         else
3876                 page_cnt = QED_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
3877
3878         rc = qed_chain_alloc_sanity_check(cdev, cnt_type, elem_size, page_cnt);
3879         if (rc) {
3880                 DP_NOTICE(cdev,
3881                           "Cannot allocate a chain with the given arguments:\n");
3882                 DP_NOTICE(cdev,
3883                           "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
3884                           intended_use, mode, cnt_type, num_elems, elem_size);
3885                 return rc;
3886         }
3887
3888         qed_chain_init_params(p_chain, page_cnt, (u8) elem_size, intended_use,
3889                               mode, cnt_type);
3890
3891         switch (mode) {
3892         case QED_CHAIN_MODE_NEXT_PTR:
3893                 rc = qed_chain_alloc_next_ptr(cdev, p_chain);
3894                 break;
3895         case QED_CHAIN_MODE_SINGLE:
3896                 rc = qed_chain_alloc_single(cdev, p_chain);
3897                 break;
3898         case QED_CHAIN_MODE_PBL:
3899                 rc = qed_chain_alloc_pbl(cdev, p_chain, ext_pbl);
3900                 break;
3901         }
3902         if (rc)
3903                 goto nomem;
3904
3905         return 0;
3906
3907 nomem:
3908         qed_chain_free(cdev, p_chain);
3909         return rc;
3910 }
3911
3912 int qed_fw_l2_queue(struct qed_hwfn *p_hwfn, u16 src_id, u16 *dst_id)
3913 {
3914         if (src_id >= RESC_NUM(p_hwfn, QED_L2_QUEUE)) {
3915                 u16 min, max;
3916
3917                 min = (u16) RESC_START(p_hwfn, QED_L2_QUEUE);
3918                 max = min + RESC_NUM(p_hwfn, QED_L2_QUEUE);
3919                 DP_NOTICE(p_hwfn,
3920                           "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
3921                           src_id, min, max);
3922
3923                 return -EINVAL;
3924         }
3925
3926         *dst_id = RESC_START(p_hwfn, QED_L2_QUEUE) + src_id;
3927
3928         return 0;
3929 }
3930
3931 int qed_fw_vport(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id)
3932 {
3933         if (src_id >= RESC_NUM(p_hwfn, QED_VPORT)) {
3934                 u8 min, max;
3935
3936                 min = (u8)RESC_START(p_hwfn, QED_VPORT);
3937                 max = min + RESC_NUM(p_hwfn, QED_VPORT);
3938                 DP_NOTICE(p_hwfn,
3939                           "vport id [%d] is not valid, available indices [%d - %d]\n",
3940                           src_id, min, max);
3941
3942                 return -EINVAL;
3943         }
3944
3945         *dst_id = RESC_START(p_hwfn, QED_VPORT) + src_id;
3946
3947         return 0;
3948 }
3949
3950 int qed_fw_rss_eng(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id)
3951 {
3952         if (src_id >= RESC_NUM(p_hwfn, QED_RSS_ENG)) {
3953                 u8 min, max;
3954
3955                 min = (u8)RESC_START(p_hwfn, QED_RSS_ENG);
3956                 max = min + RESC_NUM(p_hwfn, QED_RSS_ENG);
3957                 DP_NOTICE(p_hwfn,
3958                           "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
3959                           src_id, min, max);
3960
3961                 return -EINVAL;
3962         }
3963
3964         *dst_id = RESC_START(p_hwfn, QED_RSS_ENG) + src_id;
3965
3966         return 0;
3967 }
3968
3969 static void qed_llh_mac_to_filter(u32 *p_high, u32 *p_low,
3970                                   u8 *p_filter)
3971 {
3972         *p_high = p_filter[1] | (p_filter[0] << 8);
3973         *p_low = p_filter[5] | (p_filter[4] << 8) |
3974                  (p_filter[3] << 16) | (p_filter[2] << 24);
3975 }
3976
3977 int qed_llh_add_mac_filter(struct qed_hwfn *p_hwfn,
3978                            struct qed_ptt *p_ptt, u8 *p_filter)
3979 {
3980         u32 high = 0, low = 0, en;
3981         int i;
3982
3983         if (!test_bit(QED_MF_LLH_MAC_CLSS, &p_hwfn->cdev->mf_bits))
3984                 return 0;
3985
3986         qed_llh_mac_to_filter(&high, &low, p_filter);
3987
3988         /* Find a free entry and utilize it */
3989         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3990                 en = qed_rd(p_hwfn, p_ptt,
3991                             NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
3992                 if (en)
3993                         continue;
3994                 qed_wr(p_hwfn, p_ptt,
3995                        NIG_REG_LLH_FUNC_FILTER_VALUE +
3996                        2 * i * sizeof(u32), low);
3997                 qed_wr(p_hwfn, p_ptt,
3998                        NIG_REG_LLH_FUNC_FILTER_VALUE +
3999                        (2 * i + 1) * sizeof(u32), high);
4000                 qed_wr(p_hwfn, p_ptt,
4001                        NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
4002                 qed_wr(p_hwfn, p_ptt,
4003                        NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
4004                        i * sizeof(u32), 0);
4005                 qed_wr(p_hwfn, p_ptt,
4006                        NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
4007                 break;
4008         }
4009         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
4010                 DP_NOTICE(p_hwfn,
4011                           "Failed to find an empty LLH filter to utilize\n");
4012                 return -EINVAL;
4013         }
4014
4015         DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
4016                    "mac: %pM is added at %d\n",
4017                    p_filter, i);
4018
4019         return 0;
4020 }
4021
4022 void qed_llh_remove_mac_filter(struct qed_hwfn *p_hwfn,
4023                                struct qed_ptt *p_ptt, u8 *p_filter)
4024 {
4025         u32 high = 0, low = 0;
4026         int i;
4027
4028         if (!test_bit(QED_MF_LLH_MAC_CLSS, &p_hwfn->cdev->mf_bits))
4029                 return;
4030
4031         qed_llh_mac_to_filter(&high, &low, p_filter);
4032
4033         /* Find the entry and clean it */
4034         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4035                 if (qed_rd(p_hwfn, p_ptt,
4036                            NIG_REG_LLH_FUNC_FILTER_VALUE +
4037                            2 * i * sizeof(u32)) != low)
4038                         continue;
4039                 if (qed_rd(p_hwfn, p_ptt,
4040                            NIG_REG_LLH_FUNC_FILTER_VALUE +
4041                            (2 * i + 1) * sizeof(u32)) != high)
4042                         continue;
4043
4044                 qed_wr(p_hwfn, p_ptt,
4045                        NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
4046                 qed_wr(p_hwfn, p_ptt,
4047                        NIG_REG_LLH_FUNC_FILTER_VALUE + 2 * i * sizeof(u32), 0);
4048                 qed_wr(p_hwfn, p_ptt,
4049                        NIG_REG_LLH_FUNC_FILTER_VALUE +
4050                        (2 * i + 1) * sizeof(u32), 0);
4051
4052                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
4053                            "mac: %pM is removed from %d\n",
4054                            p_filter, i);
4055                 break;
4056         }
4057         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4058                 DP_NOTICE(p_hwfn, "Tried to remove a non-configured filter\n");
4059 }
4060
4061 int
4062 qed_llh_add_protocol_filter(struct qed_hwfn *p_hwfn,
4063                             struct qed_ptt *p_ptt,
4064                             u16 source_port_or_eth_type,
4065                             u16 dest_port, enum qed_llh_port_filter_type_t type)
4066 {
4067         u32 high = 0, low = 0, en;
4068         int i;
4069
4070         if (!test_bit(QED_MF_LLH_PROTO_CLSS, &p_hwfn->cdev->mf_bits))
4071                 return 0;
4072
4073         switch (type) {
4074         case QED_LLH_FILTER_ETHERTYPE:
4075                 high = source_port_or_eth_type;
4076                 break;
4077         case QED_LLH_FILTER_TCP_SRC_PORT:
4078         case QED_LLH_FILTER_UDP_SRC_PORT:
4079                 low = source_port_or_eth_type << 16;
4080                 break;
4081         case QED_LLH_FILTER_TCP_DEST_PORT:
4082         case QED_LLH_FILTER_UDP_DEST_PORT:
4083                 low = dest_port;
4084                 break;
4085         case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4086         case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4087                 low = (source_port_or_eth_type << 16) | dest_port;
4088                 break;
4089         default:
4090                 DP_NOTICE(p_hwfn,
4091                           "Non valid LLH protocol filter type %d\n", type);
4092                 return -EINVAL;
4093         }
4094         /* Find a free entry and utilize it */
4095         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4096                 en = qed_rd(p_hwfn, p_ptt,
4097                             NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
4098                 if (en)
4099                         continue;
4100                 qed_wr(p_hwfn, p_ptt,
4101                        NIG_REG_LLH_FUNC_FILTER_VALUE +
4102                        2 * i * sizeof(u32), low);
4103                 qed_wr(p_hwfn, p_ptt,
4104                        NIG_REG_LLH_FUNC_FILTER_VALUE +
4105                        (2 * i + 1) * sizeof(u32), high);
4106                 qed_wr(p_hwfn, p_ptt,
4107                        NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 1);
4108                 qed_wr(p_hwfn, p_ptt,
4109                        NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
4110                        i * sizeof(u32), 1 << type);
4111                 qed_wr(p_hwfn, p_ptt,
4112                        NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
4113                 break;
4114         }
4115         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
4116                 DP_NOTICE(p_hwfn,
4117                           "Failed to find an empty LLH filter to utilize\n");
4118                 return -EINVAL;
4119         }
4120         switch (type) {
4121         case QED_LLH_FILTER_ETHERTYPE:
4122                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
4123                            "ETH type %x is added at %d\n",
4124                            source_port_or_eth_type, i);
4125                 break;
4126         case QED_LLH_FILTER_TCP_SRC_PORT:
4127                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
4128                            "TCP src port %x is added at %d\n",
4129                            source_port_or_eth_type, i);
4130                 break;
4131         case QED_LLH_FILTER_UDP_SRC_PORT:
4132                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
4133                            "UDP src port %x is added at %d\n",
4134                            source_port_or_eth_type, i);
4135                 break;
4136         case QED_LLH_FILTER_TCP_DEST_PORT:
4137                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
4138                            "TCP dst port %x is added at %d\n", dest_port, i);
4139                 break;
4140         case QED_LLH_FILTER_UDP_DEST_PORT:
4141                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
4142                            "UDP dst port %x is added at %d\n", dest_port, i);
4143                 break;
4144         case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4145                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
4146                            "TCP src/dst ports %x/%x are added at %d\n",
4147                            source_port_or_eth_type, dest_port, i);
4148                 break;
4149         case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4150                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
4151                            "UDP src/dst ports %x/%x are added at %d\n",
4152                            source_port_or_eth_type, dest_port, i);
4153                 break;
4154         }
4155         return 0;
4156 }
4157
4158 void
4159 qed_llh_remove_protocol_filter(struct qed_hwfn *p_hwfn,
4160                                struct qed_ptt *p_ptt,
4161                                u16 source_port_or_eth_type,
4162                                u16 dest_port,
4163                                enum qed_llh_port_filter_type_t type)
4164 {
4165         u32 high = 0, low = 0;
4166         int i;
4167
4168         if (!test_bit(QED_MF_LLH_PROTO_CLSS, &p_hwfn->cdev->mf_bits))
4169                 return;
4170
4171         switch (type) {
4172         case QED_LLH_FILTER_ETHERTYPE:
4173                 high = source_port_or_eth_type;
4174                 break;
4175         case QED_LLH_FILTER_TCP_SRC_PORT:
4176         case QED_LLH_FILTER_UDP_SRC_PORT:
4177                 low = source_port_or_eth_type << 16;
4178                 break;
4179         case QED_LLH_FILTER_TCP_DEST_PORT:
4180         case QED_LLH_FILTER_UDP_DEST_PORT:
4181                 low = dest_port;
4182                 break;
4183         case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4184         case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4185                 low = (source_port_or_eth_type << 16) | dest_port;
4186                 break;
4187         default:
4188                 DP_NOTICE(p_hwfn,
4189                           "Non valid LLH protocol filter type %d\n", type);
4190                 return;
4191         }
4192
4193         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4194                 if (!qed_rd(p_hwfn, p_ptt,
4195                             NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32)))
4196                         continue;
4197                 if (!qed_rd(p_hwfn, p_ptt,
4198                             NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32)))
4199                         continue;
4200                 if (!(qed_rd(p_hwfn, p_ptt,
4201                              NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
4202                              i * sizeof(u32)) & BIT(type)))
4203                         continue;
4204                 if (qed_rd(p_hwfn, p_ptt,
4205                            NIG_REG_LLH_FUNC_FILTER_VALUE +
4206                            2 * i * sizeof(u32)) != low)
4207                         continue;
4208                 if (qed_rd(p_hwfn, p_ptt,
4209                            NIG_REG_LLH_FUNC_FILTER_VALUE +
4210                            (2 * i + 1) * sizeof(u32)) != high)
4211                         continue;
4212
4213                 qed_wr(p_hwfn, p_ptt,
4214                        NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
4215                 qed_wr(p_hwfn, p_ptt,
4216                        NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
4217                 qed_wr(p_hwfn, p_ptt,
4218                        NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
4219                        i * sizeof(u32), 0);
4220                 qed_wr(p_hwfn, p_ptt,
4221                        NIG_REG_LLH_FUNC_FILTER_VALUE + 2 * i * sizeof(u32), 0);
4222                 qed_wr(p_hwfn, p_ptt,
4223                        NIG_REG_LLH_FUNC_FILTER_VALUE +
4224                        (2 * i + 1) * sizeof(u32), 0);
4225                 break;
4226         }
4227
4228         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4229                 DP_NOTICE(p_hwfn, "Tried to remove a non-configured filter\n");
4230 }
4231
4232 static int qed_set_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
4233                             u32 hw_addr, void *p_eth_qzone,
4234                             size_t eth_qzone_size, u8 timeset)
4235 {
4236         struct coalescing_timeset *p_coal_timeset;
4237
4238         if (p_hwfn->cdev->int_coalescing_mode != QED_COAL_MODE_ENABLE) {
4239                 DP_NOTICE(p_hwfn, "Coalescing configuration not enabled\n");
4240                 return -EINVAL;
4241         }
4242
4243         p_coal_timeset = p_eth_qzone;
4244         memset(p_eth_qzone, 0, eth_qzone_size);
4245         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
4246         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
4247         qed_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
4248
4249         return 0;
4250 }
4251
4252 int qed_set_queue_coalesce(u16 rx_coal, u16 tx_coal, void *p_handle)
4253 {
4254         struct qed_queue_cid *p_cid = p_handle;
4255         struct qed_hwfn *p_hwfn;
4256         struct qed_ptt *p_ptt;
4257         int rc = 0;
4258
4259         p_hwfn = p_cid->p_owner;
4260
4261         if (IS_VF(p_hwfn->cdev))
4262                 return qed_vf_pf_set_coalesce(p_hwfn, rx_coal, tx_coal, p_cid);
4263
4264         p_ptt = qed_ptt_acquire(p_hwfn);
4265         if (!p_ptt)
4266                 return -EAGAIN;
4267
4268         if (rx_coal) {
4269                 rc = qed_set_rxq_coalesce(p_hwfn, p_ptt, rx_coal, p_cid);
4270                 if (rc)
4271                         goto out;
4272                 p_hwfn->cdev->rx_coalesce_usecs = rx_coal;
4273         }
4274
4275         if (tx_coal) {
4276                 rc = qed_set_txq_coalesce(p_hwfn, p_ptt, tx_coal, p_cid);
4277                 if (rc)
4278                         goto out;
4279                 p_hwfn->cdev->tx_coalesce_usecs = tx_coal;
4280         }
4281 out:
4282         qed_ptt_release(p_hwfn, p_ptt);
4283         return rc;
4284 }
4285
4286 int qed_set_rxq_coalesce(struct qed_hwfn *p_hwfn,
4287                          struct qed_ptt *p_ptt,
4288                          u16 coalesce, struct qed_queue_cid *p_cid)
4289 {
4290         struct ustorm_eth_queue_zone eth_qzone;
4291         u8 timeset, timer_res;
4292         u32 address;
4293         int rc;
4294
4295         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
4296         if (coalesce <= 0x7F) {
4297                 timer_res = 0;
4298         } else if (coalesce <= 0xFF) {
4299                 timer_res = 1;
4300         } else if (coalesce <= 0x1FF) {
4301                 timer_res = 2;
4302         } else {
4303                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
4304                 return -EINVAL;
4305         }
4306         timeset = (u8)(coalesce >> timer_res);
4307
4308         rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res,
4309                                    p_cid->sb_igu_id, false);
4310         if (rc)
4311                 goto out;
4312
4313         address = BAR0_MAP_REG_USDM_RAM +
4314                   USTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
4315
4316         rc = qed_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
4317                               sizeof(struct ustorm_eth_queue_zone), timeset);
4318         if (rc)
4319                 goto out;
4320
4321 out:
4322         return rc;
4323 }
4324
4325 int qed_set_txq_coalesce(struct qed_hwfn *p_hwfn,
4326                          struct qed_ptt *p_ptt,
4327                          u16 coalesce, struct qed_queue_cid *p_cid)
4328 {
4329         struct xstorm_eth_queue_zone eth_qzone;
4330         u8 timeset, timer_res;
4331         u32 address;
4332         int rc;
4333
4334         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
4335         if (coalesce <= 0x7F) {
4336                 timer_res = 0;
4337         } else if (coalesce <= 0xFF) {
4338                 timer_res = 1;
4339         } else if (coalesce <= 0x1FF) {
4340                 timer_res = 2;
4341         } else {
4342                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
4343                 return -EINVAL;
4344         }
4345         timeset = (u8)(coalesce >> timer_res);
4346
4347         rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res,
4348                                    p_cid->sb_igu_id, true);
4349         if (rc)
4350                 goto out;
4351
4352         address = BAR0_MAP_REG_XSDM_RAM +
4353                   XSTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
4354
4355         rc = qed_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
4356                               sizeof(struct xstorm_eth_queue_zone), timeset);
4357 out:
4358         return rc;
4359 }
4360
4361 /* Calculate final WFQ values for all vports and configure them.
4362  * After this configuration each vport will have
4363  * approx min rate =  min_pf_rate * (vport_wfq / QED_WFQ_UNIT)
4364  */
4365 static void qed_configure_wfq_for_all_vports(struct qed_hwfn *p_hwfn,
4366                                              struct qed_ptt *p_ptt,
4367                                              u32 min_pf_rate)
4368 {
4369         struct init_qm_vport_params *vport_params;
4370         int i;
4371
4372         vport_params = p_hwfn->qm_info.qm_vport_params;
4373
4374         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4375                 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
4376
4377                 vport_params[i].vport_wfq = (wfq_speed * QED_WFQ_UNIT) /
4378                                                 min_pf_rate;
4379                 qed_init_vport_wfq(p_hwfn, p_ptt,
4380                                    vport_params[i].first_tx_pq_id,
4381                                    vport_params[i].vport_wfq);
4382         }
4383 }
4384
4385 static void qed_init_wfq_default_param(struct qed_hwfn *p_hwfn,
4386                                        u32 min_pf_rate)
4387
4388 {
4389         int i;
4390
4391         for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
4392                 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
4393 }
4394
4395 static void qed_disable_wfq_for_all_vports(struct qed_hwfn *p_hwfn,
4396                                            struct qed_ptt *p_ptt,
4397                                            u32 min_pf_rate)
4398 {
4399         struct init_qm_vport_params *vport_params;
4400         int i;
4401
4402         vport_params = p_hwfn->qm_info.qm_vport_params;
4403
4404         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4405                 qed_init_wfq_default_param(p_hwfn, min_pf_rate);
4406                 qed_init_vport_wfq(p_hwfn, p_ptt,
4407                                    vport_params[i].first_tx_pq_id,
4408                                    vport_params[i].vport_wfq);
4409         }
4410 }
4411
4412 /* This function performs several validations for WFQ
4413  * configuration and required min rate for a given vport
4414  * 1. req_rate must be greater than one percent of min_pf_rate.
4415  * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
4416  *    rates to get less than one percent of min_pf_rate.
4417  * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
4418  */
4419 static int qed_init_wfq_param(struct qed_hwfn *p_hwfn,
4420                               u16 vport_id, u32 req_rate, u32 min_pf_rate)
4421 {
4422         u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
4423         int non_requested_count = 0, req_count = 0, i, num_vports;
4424
4425         num_vports = p_hwfn->qm_info.num_vports;
4426
4427         /* Accounting for the vports which are configured for WFQ explicitly */
4428         for (i = 0; i < num_vports; i++) {
4429                 u32 tmp_speed;
4430
4431                 if ((i != vport_id) &&
4432                     p_hwfn->qm_info.wfq_data[i].configured) {
4433                         req_count++;
4434                         tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
4435                         total_req_min_rate += tmp_speed;
4436                 }
4437         }
4438
4439         /* Include current vport data as well */
4440         req_count++;
4441         total_req_min_rate += req_rate;
4442         non_requested_count = num_vports - req_count;
4443
4444         if (req_rate < min_pf_rate / QED_WFQ_UNIT) {
4445                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
4446                            "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
4447                            vport_id, req_rate, min_pf_rate);
4448                 return -EINVAL;
4449         }
4450
4451         if (num_vports > QED_WFQ_UNIT) {
4452                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
4453                            "Number of vports is greater than %d\n",
4454                            QED_WFQ_UNIT);
4455                 return -EINVAL;
4456         }
4457
4458         if (total_req_min_rate > min_pf_rate) {
4459                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
4460                            "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
4461                            total_req_min_rate, min_pf_rate);
4462                 return -EINVAL;
4463         }
4464
4465         total_left_rate = min_pf_rate - total_req_min_rate;
4466
4467         left_rate_per_vp = total_left_rate / non_requested_count;
4468         if (left_rate_per_vp <  min_pf_rate / QED_WFQ_UNIT) {
4469                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
4470                            "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
4471                            left_rate_per_vp, min_pf_rate);
4472                 return -EINVAL;
4473         }
4474
4475         p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
4476         p_hwfn->qm_info.wfq_data[vport_id].configured = true;
4477
4478         for (i = 0; i < num_vports; i++) {
4479                 if (p_hwfn->qm_info.wfq_data[i].configured)
4480                         continue;
4481
4482                 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
4483         }
4484
4485         return 0;
4486 }
4487
4488 static int __qed_configure_vport_wfq(struct qed_hwfn *p_hwfn,
4489                                      struct qed_ptt *p_ptt, u16 vp_id, u32 rate)
4490 {
4491         struct qed_mcp_link_state *p_link;
4492         int rc = 0;
4493
4494         p_link = &p_hwfn->cdev->hwfns[0].mcp_info->link_output;
4495
4496         if (!p_link->min_pf_rate) {
4497                 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
4498                 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
4499                 return rc;
4500         }
4501
4502         rc = qed_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
4503
4504         if (!rc)
4505                 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt,
4506                                                  p_link->min_pf_rate);
4507         else
4508                 DP_NOTICE(p_hwfn,
4509                           "Validation failed while configuring min rate\n");
4510
4511         return rc;
4512 }
4513
4514 static int __qed_configure_vp_wfq_on_link_change(struct qed_hwfn *p_hwfn,
4515                                                  struct qed_ptt *p_ptt,
4516                                                  u32 min_pf_rate)
4517 {
4518         bool use_wfq = false;
4519         int rc = 0;
4520         u16 i;
4521
4522         /* Validate all pre configured vports for wfq */
4523         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4524                 u32 rate;
4525
4526                 if (!p_hwfn->qm_info.wfq_data[i].configured)
4527                         continue;
4528
4529                 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
4530                 use_wfq = true;
4531
4532                 rc = qed_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
4533                 if (rc) {
4534                         DP_NOTICE(p_hwfn,
4535                                   "WFQ validation failed while configuring min rate\n");
4536                         break;
4537                 }
4538         }
4539
4540         if (!rc && use_wfq)
4541                 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
4542         else
4543                 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
4544
4545         return rc;
4546 }
4547
4548 /* Main API for qed clients to configure vport min rate.
4549  * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
4550  * rate - Speed in Mbps needs to be assigned to a given vport.
4551  */
4552 int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate)
4553 {
4554         int i, rc = -EINVAL;
4555
4556         /* Currently not supported; Might change in future */
4557         if (cdev->num_hwfns > 1) {
4558                 DP_NOTICE(cdev,
4559                           "WFQ configuration is not supported for this device\n");
4560                 return rc;
4561         }
4562
4563         for_each_hwfn(cdev, i) {
4564                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
4565                 struct qed_ptt *p_ptt;
4566
4567                 p_ptt = qed_ptt_acquire(p_hwfn);
4568                 if (!p_ptt)
4569                         return -EBUSY;
4570
4571                 rc = __qed_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
4572
4573                 if (rc) {
4574                         qed_ptt_release(p_hwfn, p_ptt);
4575                         return rc;
4576                 }
4577
4578                 qed_ptt_release(p_hwfn, p_ptt);
4579         }
4580
4581         return rc;
4582 }
4583
4584 /* API to configure WFQ from mcp link change */
4585 void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev,
4586                                          struct qed_ptt *p_ptt, u32 min_pf_rate)
4587 {
4588         int i;
4589
4590         if (cdev->num_hwfns > 1) {
4591                 DP_VERBOSE(cdev,
4592                            NETIF_MSG_LINK,
4593                            "WFQ configuration is not supported for this device\n");
4594                 return;
4595         }
4596
4597         for_each_hwfn(cdev, i) {
4598                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
4599
4600                 __qed_configure_vp_wfq_on_link_change(p_hwfn, p_ptt,
4601                                                       min_pf_rate);
4602         }
4603 }
4604
4605 int __qed_configure_pf_max_bandwidth(struct qed_hwfn *p_hwfn,
4606                                      struct qed_ptt *p_ptt,
4607                                      struct qed_mcp_link_state *p_link,
4608                                      u8 max_bw)
4609 {
4610         int rc = 0;
4611
4612         p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
4613
4614         if (!p_link->line_speed && (max_bw != 100))
4615                 return rc;
4616
4617         p_link->speed = (p_link->line_speed * max_bw) / 100;
4618         p_hwfn->qm_info.pf_rl = p_link->speed;
4619
4620         /* Since the limiter also affects Tx-switched traffic, we don't want it
4621          * to limit such traffic in case there's no actual limit.
4622          * In that case, set limit to imaginary high boundary.
4623          */
4624         if (max_bw == 100)
4625                 p_hwfn->qm_info.pf_rl = 100000;
4626
4627         rc = qed_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
4628                             p_hwfn->qm_info.pf_rl);
4629
4630         DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
4631                    "Configured MAX bandwidth to be %08x Mb/sec\n",
4632                    p_link->speed);
4633
4634         return rc;
4635 }
4636
4637 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
4638 int qed_configure_pf_max_bandwidth(struct qed_dev *cdev, u8 max_bw)
4639 {
4640         int i, rc = -EINVAL;
4641
4642         if (max_bw < 1 || max_bw > 100) {
4643                 DP_NOTICE(cdev, "PF max bw valid range is [1-100]\n");
4644                 return rc;
4645         }
4646
4647         for_each_hwfn(cdev, i) {
4648                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
4649                 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev);
4650                 struct qed_mcp_link_state *p_link;
4651                 struct qed_ptt *p_ptt;
4652
4653                 p_link = &p_lead->mcp_info->link_output;
4654
4655                 p_ptt = qed_ptt_acquire(p_hwfn);
4656                 if (!p_ptt)
4657                         return -EBUSY;
4658
4659                 rc = __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt,
4660                                                       p_link, max_bw);
4661
4662                 qed_ptt_release(p_hwfn, p_ptt);
4663
4664                 if (rc)
4665                         break;
4666         }
4667
4668         return rc;
4669 }
4670
4671 int __qed_configure_pf_min_bandwidth(struct qed_hwfn *p_hwfn,
4672                                      struct qed_ptt *p_ptt,
4673                                      struct qed_mcp_link_state *p_link,
4674                                      u8 min_bw)
4675 {
4676         int rc = 0;
4677
4678         p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
4679         p_hwfn->qm_info.pf_wfq = min_bw;
4680
4681         if (!p_link->line_speed)
4682                 return rc;
4683
4684         p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
4685
4686         rc = qed_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
4687
4688         DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
4689                    "Configured MIN bandwidth to be %d Mb/sec\n",
4690                    p_link->min_pf_rate);
4691
4692         return rc;
4693 }
4694
4695 /* Main API to configure PF min bandwidth where bw range is [1-100] */
4696 int qed_configure_pf_min_bandwidth(struct qed_dev *cdev, u8 min_bw)
4697 {
4698         int i, rc = -EINVAL;
4699
4700         if (min_bw < 1 || min_bw > 100) {
4701                 DP_NOTICE(cdev, "PF min bw valid range is [1-100]\n");
4702                 return rc;
4703         }
4704
4705         for_each_hwfn(cdev, i) {
4706                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
4707                 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev);
4708                 struct qed_mcp_link_state *p_link;
4709                 struct qed_ptt *p_ptt;
4710
4711                 p_link = &p_lead->mcp_info->link_output;
4712
4713                 p_ptt = qed_ptt_acquire(p_hwfn);
4714                 if (!p_ptt)
4715                         return -EBUSY;
4716
4717                 rc = __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt,
4718                                                       p_link, min_bw);
4719                 if (rc) {
4720                         qed_ptt_release(p_hwfn, p_ptt);
4721                         return rc;
4722                 }
4723
4724                 if (p_link->min_pf_rate) {
4725                         u32 min_rate = p_link->min_pf_rate;
4726
4727                         rc = __qed_configure_vp_wfq_on_link_change(p_hwfn,
4728                                                                    p_ptt,
4729                                                                    min_rate);
4730                 }
4731
4732                 qed_ptt_release(p_hwfn, p_ptt);
4733         }
4734
4735         return rc;
4736 }
4737
4738 void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
4739 {
4740         struct qed_mcp_link_state *p_link;
4741
4742         p_link = &p_hwfn->mcp_info->link_output;
4743
4744         if (p_link->min_pf_rate)
4745                 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt,
4746                                                p_link->min_pf_rate);
4747
4748         memset(p_hwfn->qm_info.wfq_data, 0,
4749                sizeof(*p_hwfn->qm_info.wfq_data) * p_hwfn->qm_info.num_vports);
4750 }
4751
4752 int qed_device_num_ports(struct qed_dev *cdev)
4753 {
4754         return cdev->num_ports;
4755 }
4756
4757 void qed_set_fw_mac_addr(__le16 *fw_msb,
4758                          __le16 *fw_mid, __le16 *fw_lsb, u8 *mac)
4759 {
4760         ((u8 *)fw_msb)[0] = mac[1];
4761         ((u8 *)fw_msb)[1] = mac[0];
4762         ((u8 *)fw_mid)[0] = mac[3];
4763         ((u8 *)fw_mid)[1] = mac[2];
4764         ((u8 *)fw_lsb)[0] = mac[5];
4765         ((u8 *)fw_lsb)[1] = mac[4];
4766 }