1 /* QLogic qed NIC Driver
2 * Copyright (c) 2015-2017 QLogic Corporation
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and /or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/types.h>
34 #include <asm/byteorder.h>
36 #include <linux/delay.h>
37 #include <linux/dma-mapping.h>
38 #include <linux/errno.h>
39 #include <linux/kernel.h>
40 #include <linux/mutex.h>
41 #include <linux/pci.h>
42 #include <linux/slab.h>
43 #include <linux/string.h>
44 #include <linux/vmalloc.h>
45 #include <linux/etherdevice.h>
46 #include <linux/qed/qed_chain.h>
47 #include <linux/qed/qed_if.h>
51 #include "qed_dev_api.h"
55 #include "qed_init_ops.h"
57 #include "qed_iscsi.h"
61 #include "qed_reg_addr.h"
63 #include "qed_sriov.h"
67 static DEFINE_SPINLOCK(qm_lock);
69 /******************** Doorbell Recovery *******************/
70 /* The doorbell recovery mechanism consists of a list of entries which represent
71 * doorbelling entities (l2 queues, roce sq/rq/cqs, the slowpath spq, etc). Each
72 * entity needs to register with the mechanism and provide the parameters
73 * describing it's doorbell, including a location where last used doorbell data
74 * can be found. The doorbell execute function will traverse the list and
75 * doorbell all of the registered entries.
77 struct qed_db_recovery_entry {
78 struct list_head list_entry;
79 void __iomem *db_addr;
81 enum qed_db_rec_width db_width;
82 enum qed_db_rec_space db_space;
86 /* Display a single doorbell recovery entry */
87 static void qed_db_recovery_dp_entry(struct qed_hwfn *p_hwfn,
88 struct qed_db_recovery_entry *db_entry,
93 "(%s: db_entry %p, addr %p, data %p, width %s, %s space, hwfn %d)\n",
98 db_entry->db_width == DB_REC_WIDTH_32B ? "32b" : "64b",
99 db_entry->db_space == DB_REC_USER ? "user" : "kernel",
103 /* Doorbell address sanity (address within doorbell bar range) */
104 static bool qed_db_rec_sanity(struct qed_dev *cdev,
105 void __iomem *db_addr,
106 enum qed_db_rec_width db_width,
109 u32 width = (db_width == DB_REC_WIDTH_32B) ? 32 : 64;
111 /* Make sure doorbell address is within the doorbell bar */
112 if (db_addr < cdev->doorbells ||
113 (u8 __iomem *)db_addr + width >
114 (u8 __iomem *)cdev->doorbells + cdev->db_size) {
116 "Illegal doorbell address: %p. Legal range for doorbell addresses is [%p..%p]\n",
119 (u8 __iomem *)cdev->doorbells + cdev->db_size);
123 /* ake sure doorbell data pointer is not null */
125 WARN(true, "Illegal doorbell data pointer: %p", db_data);
132 /* Find hwfn according to the doorbell address */
133 static struct qed_hwfn *qed_db_rec_find_hwfn(struct qed_dev *cdev,
134 void __iomem *db_addr)
136 struct qed_hwfn *p_hwfn;
138 /* In CMT doorbell bar is split down the middle between engine 0 and enigne 1 */
139 if (cdev->num_hwfns > 1)
140 p_hwfn = db_addr < cdev->hwfns[1].doorbells ?
141 &cdev->hwfns[0] : &cdev->hwfns[1];
143 p_hwfn = QED_LEADING_HWFN(cdev);
148 /* Add a new entry to the doorbell recovery mechanism */
149 int qed_db_recovery_add(struct qed_dev *cdev,
150 void __iomem *db_addr,
152 enum qed_db_rec_width db_width,
153 enum qed_db_rec_space db_space)
155 struct qed_db_recovery_entry *db_entry;
156 struct qed_hwfn *p_hwfn;
158 /* Shortcircuit VFs, for now */
161 QED_MSG_IOV, "db recovery - skipping VF doorbell\n");
165 /* Sanitize doorbell address */
166 if (!qed_db_rec_sanity(cdev, db_addr, db_width, db_data))
169 /* Obtain hwfn from doorbell address */
170 p_hwfn = qed_db_rec_find_hwfn(cdev, db_addr);
173 db_entry = kzalloc(sizeof(*db_entry), GFP_KERNEL);
175 DP_NOTICE(cdev, "Failed to allocate a db recovery entry\n");
180 db_entry->db_addr = db_addr;
181 db_entry->db_data = db_data;
182 db_entry->db_width = db_width;
183 db_entry->db_space = db_space;
184 db_entry->hwfn_idx = p_hwfn->my_id;
187 qed_db_recovery_dp_entry(p_hwfn, db_entry, "Adding");
189 /* Protect the list */
190 spin_lock_bh(&p_hwfn->db_recovery_info.lock);
191 list_add_tail(&db_entry->list_entry, &p_hwfn->db_recovery_info.list);
192 spin_unlock_bh(&p_hwfn->db_recovery_info.lock);
197 /* Remove an entry from the doorbell recovery mechanism */
198 int qed_db_recovery_del(struct qed_dev *cdev,
199 void __iomem *db_addr, void *db_data)
201 struct qed_db_recovery_entry *db_entry = NULL;
202 struct qed_hwfn *p_hwfn;
205 /* Shortcircuit VFs, for now */
208 QED_MSG_IOV, "db recovery - skipping VF doorbell\n");
212 /* Obtain hwfn from doorbell address */
213 p_hwfn = qed_db_rec_find_hwfn(cdev, db_addr);
215 /* Protect the list */
216 spin_lock_bh(&p_hwfn->db_recovery_info.lock);
217 list_for_each_entry(db_entry,
218 &p_hwfn->db_recovery_info.list, list_entry) {
219 /* search according to db_data addr since db_addr is not unique (roce) */
220 if (db_entry->db_data == db_data) {
221 qed_db_recovery_dp_entry(p_hwfn, db_entry, "Deleting");
222 list_del(&db_entry->list_entry);
228 spin_unlock_bh(&p_hwfn->db_recovery_info.lock);
233 "Failed to find element in list. Key (db_data addr) was %p. db_addr was %p\n",
241 /* Initialize the doorbell recovery mechanism */
242 static int qed_db_recovery_setup(struct qed_hwfn *p_hwfn)
244 DP_VERBOSE(p_hwfn, QED_MSG_SPQ, "Setting up db recovery\n");
246 /* Make sure db_size was set in cdev */
247 if (!p_hwfn->cdev->db_size) {
248 DP_ERR(p_hwfn->cdev, "db_size not set\n");
252 INIT_LIST_HEAD(&p_hwfn->db_recovery_info.list);
253 spin_lock_init(&p_hwfn->db_recovery_info.lock);
254 p_hwfn->db_recovery_info.db_recovery_counter = 0;
259 /* Destroy the doorbell recovery mechanism */
260 static void qed_db_recovery_teardown(struct qed_hwfn *p_hwfn)
262 struct qed_db_recovery_entry *db_entry = NULL;
264 DP_VERBOSE(p_hwfn, QED_MSG_SPQ, "Tearing down db recovery\n");
265 if (!list_empty(&p_hwfn->db_recovery_info.list)) {
268 "Doorbell Recovery teardown found the doorbell recovery list was not empty (Expected in disorderly driver unload (e.g. recovery) otherwise this probably means some flow forgot to db_recovery_del). Prepare to purge doorbell recovery list...\n");
269 while (!list_empty(&p_hwfn->db_recovery_info.list)) {
271 list_first_entry(&p_hwfn->db_recovery_info.list,
272 struct qed_db_recovery_entry,
274 qed_db_recovery_dp_entry(p_hwfn, db_entry, "Purging");
275 list_del(&db_entry->list_entry);
279 p_hwfn->db_recovery_info.db_recovery_counter = 0;
282 /* Print the content of the doorbell recovery mechanism */
283 void qed_db_recovery_dp(struct qed_hwfn *p_hwfn)
285 struct qed_db_recovery_entry *db_entry = NULL;
288 "Displaying doorbell recovery database. Counter was %d\n",
289 p_hwfn->db_recovery_info.db_recovery_counter);
291 /* Protect the list */
292 spin_lock_bh(&p_hwfn->db_recovery_info.lock);
293 list_for_each_entry(db_entry,
294 &p_hwfn->db_recovery_info.list, list_entry) {
295 qed_db_recovery_dp_entry(p_hwfn, db_entry, "Printing");
298 spin_unlock_bh(&p_hwfn->db_recovery_info.lock);
301 /* Ring the doorbell of a single doorbell recovery entry */
302 static void qed_db_recovery_ring(struct qed_hwfn *p_hwfn,
303 struct qed_db_recovery_entry *db_entry)
305 /* Print according to width */
306 if (db_entry->db_width == DB_REC_WIDTH_32B) {
307 DP_VERBOSE(p_hwfn, QED_MSG_SPQ,
308 "ringing doorbell address %p data %x\n",
310 *(u32 *)db_entry->db_data);
312 DP_VERBOSE(p_hwfn, QED_MSG_SPQ,
313 "ringing doorbell address %p data %llx\n",
315 *(u64 *)(db_entry->db_data));
319 if (!qed_db_rec_sanity(p_hwfn->cdev, db_entry->db_addr,
320 db_entry->db_width, db_entry->db_data))
323 /* Flush the write combined buffer. Since there are multiple doorbelling
324 * entities using the same address, if we don't flush, a transaction
329 /* Ring the doorbell */
330 if (db_entry->db_width == DB_REC_WIDTH_32B)
331 DIRECT_REG_WR(db_entry->db_addr,
332 *(u32 *)(db_entry->db_data));
334 DIRECT_REG_WR64(db_entry->db_addr,
335 *(u64 *)(db_entry->db_data));
337 /* Flush the write combined buffer. Next doorbell may come from a
338 * different entity to the same address...
343 /* Traverse the doorbell recovery entry list and ring all the doorbells */
344 void qed_db_recovery_execute(struct qed_hwfn *p_hwfn)
346 struct qed_db_recovery_entry *db_entry = NULL;
348 DP_NOTICE(p_hwfn, "Executing doorbell recovery. Counter was %d\n",
349 p_hwfn->db_recovery_info.db_recovery_counter);
351 /* Track amount of times recovery was executed */
352 p_hwfn->db_recovery_info.db_recovery_counter++;
354 /* Protect the list */
355 spin_lock_bh(&p_hwfn->db_recovery_info.lock);
356 list_for_each_entry(db_entry,
357 &p_hwfn->db_recovery_info.list, list_entry)
358 qed_db_recovery_ring(p_hwfn, db_entry);
359 spin_unlock_bh(&p_hwfn->db_recovery_info.lock);
362 /******************** Doorbell Recovery end ****************/
364 #define QED_MIN_DPIS (4)
365 #define QED_MIN_PWM_REGION (QED_WID_SIZE * QED_MIN_DPIS)
367 static u32 qed_hw_bar_size(struct qed_hwfn *p_hwfn,
368 struct qed_ptt *p_ptt, enum BAR_ID bar_id)
370 u32 bar_reg = (bar_id == BAR_ID_0 ?
371 PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
374 if (IS_VF(p_hwfn->cdev))
375 return qed_vf_hw_bar_size(p_hwfn, bar_id);
377 val = qed_rd(p_hwfn, p_ptt, bar_reg);
379 return 1 << (val + 15);
381 /* Old MFW initialized above registered only conditionally */
382 if (p_hwfn->cdev->num_hwfns > 1) {
384 "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n");
385 return BAR_ID_0 ? 256 * 1024 : 512 * 1024;
388 "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n");
393 void qed_init_dp(struct qed_dev *cdev, u32 dp_module, u8 dp_level)
397 cdev->dp_level = dp_level;
398 cdev->dp_module = dp_module;
399 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
400 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
402 p_hwfn->dp_level = dp_level;
403 p_hwfn->dp_module = dp_module;
407 void qed_init_struct(struct qed_dev *cdev)
411 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
412 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
416 p_hwfn->b_active = false;
418 mutex_init(&p_hwfn->dmae_info.mutex);
421 /* hwfn 0 is always active */
422 cdev->hwfns[0].b_active = true;
424 /* set the default cache alignment to 128 */
425 cdev->cache_shift = 7;
428 static void qed_qm_info_free(struct qed_hwfn *p_hwfn)
430 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
432 kfree(qm_info->qm_pq_params);
433 qm_info->qm_pq_params = NULL;
434 kfree(qm_info->qm_vport_params);
435 qm_info->qm_vport_params = NULL;
436 kfree(qm_info->qm_port_params);
437 qm_info->qm_port_params = NULL;
438 kfree(qm_info->wfq_data);
439 qm_info->wfq_data = NULL;
442 static void qed_dbg_user_data_free(struct qed_hwfn *p_hwfn)
444 kfree(p_hwfn->dbg_user_info);
445 p_hwfn->dbg_user_info = NULL;
448 void qed_resc_free(struct qed_dev *cdev)
453 for_each_hwfn(cdev, i)
454 qed_l2_free(&cdev->hwfns[i]);
458 kfree(cdev->fw_data);
459 cdev->fw_data = NULL;
461 kfree(cdev->reset_stats);
462 cdev->reset_stats = NULL;
464 for_each_hwfn(cdev, i) {
465 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
467 qed_cxt_mngr_free(p_hwfn);
468 qed_qm_info_free(p_hwfn);
469 qed_spq_free(p_hwfn);
471 qed_consq_free(p_hwfn);
472 qed_int_free(p_hwfn);
473 #ifdef CONFIG_QED_LL2
474 qed_ll2_free(p_hwfn);
476 if (p_hwfn->hw_info.personality == QED_PCI_FCOE)
477 qed_fcoe_free(p_hwfn);
479 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
480 qed_iscsi_free(p_hwfn);
481 qed_ooo_free(p_hwfn);
484 if (QED_IS_RDMA_PERSONALITY(p_hwfn))
485 qed_rdma_info_free(p_hwfn);
487 qed_iov_free(p_hwfn);
489 qed_dmae_info_free(p_hwfn);
490 qed_dcbx_info_free(p_hwfn);
491 qed_dbg_user_data_free(p_hwfn);
493 /* Destroy doorbell recovery mechanism */
494 qed_db_recovery_teardown(p_hwfn);
498 /******************** QM initialization *******************/
499 #define ACTIVE_TCS_BMAP 0x9f
500 #define ACTIVE_TCS_BMAP_4PORT_K2 0xf
502 /* determines the physical queue flags for a given PF. */
503 static u32 qed_get_pq_flags(struct qed_hwfn *p_hwfn)
511 if (IS_QED_SRIOV(p_hwfn->cdev))
512 flags |= PQ_FLAGS_VFS;
515 switch (p_hwfn->hw_info.personality) {
517 flags |= PQ_FLAGS_MCOS;
520 flags |= PQ_FLAGS_OFLD;
523 flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD;
525 case QED_PCI_ETH_ROCE:
526 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_OFLD | PQ_FLAGS_LLT;
527 if (IS_QED_MULTI_TC_ROCE(p_hwfn))
528 flags |= PQ_FLAGS_MTC;
530 case QED_PCI_ETH_IWARP:
531 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_ACK | PQ_FLAGS_OOO |
536 "unknown personality %d\n", p_hwfn->hw_info.personality);
543 /* Getters for resource amounts necessary for qm initialization */
544 static u8 qed_init_qm_get_num_tcs(struct qed_hwfn *p_hwfn)
546 return p_hwfn->hw_info.num_hw_tc;
549 static u16 qed_init_qm_get_num_vfs(struct qed_hwfn *p_hwfn)
551 return IS_QED_SRIOV(p_hwfn->cdev) ?
552 p_hwfn->cdev->p_iov_info->total_vfs : 0;
555 static u8 qed_init_qm_get_num_mtc_tcs(struct qed_hwfn *p_hwfn)
557 u32 pq_flags = qed_get_pq_flags(p_hwfn);
559 if (!(PQ_FLAGS_MTC & pq_flags))
562 return qed_init_qm_get_num_tcs(p_hwfn);
565 #define NUM_DEFAULT_RLS 1
567 static u16 qed_init_qm_get_num_pf_rls(struct qed_hwfn *p_hwfn)
569 u16 num_pf_rls, num_vfs = qed_init_qm_get_num_vfs(p_hwfn);
571 /* num RLs can't exceed resource amount of rls or vports */
572 num_pf_rls = (u16) min_t(u32, RESC_NUM(p_hwfn, QED_RL),
573 RESC_NUM(p_hwfn, QED_VPORT));
575 /* Make sure after we reserve there's something left */
576 if (num_pf_rls < num_vfs + NUM_DEFAULT_RLS)
579 /* subtract rls necessary for VFs and one default one for the PF */
580 num_pf_rls -= num_vfs + NUM_DEFAULT_RLS;
585 static u16 qed_init_qm_get_num_vports(struct qed_hwfn *p_hwfn)
587 u32 pq_flags = qed_get_pq_flags(p_hwfn);
589 /* all pqs share the same vport, except for vfs and pf_rl pqs */
590 return (!!(PQ_FLAGS_RLS & pq_flags)) *
591 qed_init_qm_get_num_pf_rls(p_hwfn) +
592 (!!(PQ_FLAGS_VFS & pq_flags)) *
593 qed_init_qm_get_num_vfs(p_hwfn) + 1;
596 /* calc amount of PQs according to the requested flags */
597 static u16 qed_init_qm_get_num_pqs(struct qed_hwfn *p_hwfn)
599 u32 pq_flags = qed_get_pq_flags(p_hwfn);
601 return (!!(PQ_FLAGS_RLS & pq_flags)) *
602 qed_init_qm_get_num_pf_rls(p_hwfn) +
603 (!!(PQ_FLAGS_MCOS & pq_flags)) *
604 qed_init_qm_get_num_tcs(p_hwfn) +
605 (!!(PQ_FLAGS_LB & pq_flags)) + (!!(PQ_FLAGS_OOO & pq_flags)) +
606 (!!(PQ_FLAGS_ACK & pq_flags)) +
607 (!!(PQ_FLAGS_OFLD & pq_flags)) *
608 qed_init_qm_get_num_mtc_tcs(p_hwfn) +
609 (!!(PQ_FLAGS_LLT & pq_flags)) *
610 qed_init_qm_get_num_mtc_tcs(p_hwfn) +
611 (!!(PQ_FLAGS_VFS & pq_flags)) * qed_init_qm_get_num_vfs(p_hwfn);
614 /* initialize the top level QM params */
615 static void qed_init_qm_params(struct qed_hwfn *p_hwfn)
617 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
620 /* pq and vport bases for this PF */
621 qm_info->start_pq = (u16) RESC_START(p_hwfn, QED_PQ);
622 qm_info->start_vport = (u8) RESC_START(p_hwfn, QED_VPORT);
624 /* rate limiting and weighted fair queueing are always enabled */
625 qm_info->vport_rl_en = true;
626 qm_info->vport_wfq_en = true;
628 /* TC config is different for AH 4 port */
629 four_port = p_hwfn->cdev->num_ports_in_engine == MAX_NUM_PORTS_K2;
631 /* in AH 4 port we have fewer TCs per port */
632 qm_info->max_phys_tcs_per_port = four_port ? NUM_PHYS_TCS_4PORT_K2 :
635 /* unless MFW indicated otherwise, ooo_tc == 3 for
636 * AH 4-port and 4 otherwise.
638 if (!qm_info->ooo_tc)
639 qm_info->ooo_tc = four_port ? DCBX_TCP_OOO_K2_4PORT_TC :
643 /* initialize qm vport params */
644 static void qed_init_qm_vport_params(struct qed_hwfn *p_hwfn)
646 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
649 /* all vports participate in weighted fair queueing */
650 for (i = 0; i < qed_init_qm_get_num_vports(p_hwfn); i++)
651 qm_info->qm_vport_params[i].vport_wfq = 1;
654 /* initialize qm port params */
655 static void qed_init_qm_port_params(struct qed_hwfn *p_hwfn)
657 /* Initialize qm port parameters */
658 u8 i, active_phys_tcs, num_ports = p_hwfn->cdev->num_ports_in_engine;
660 /* indicate how ooo and high pri traffic is dealt with */
661 active_phys_tcs = num_ports == MAX_NUM_PORTS_K2 ?
662 ACTIVE_TCS_BMAP_4PORT_K2 :
665 for (i = 0; i < num_ports; i++) {
666 struct init_qm_port_params *p_qm_port =
667 &p_hwfn->qm_info.qm_port_params[i];
669 p_qm_port->active = 1;
670 p_qm_port->active_phys_tcs = active_phys_tcs;
671 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports;
672 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
676 /* Reset the params which must be reset for qm init. QM init may be called as
677 * a result of flows other than driver load (e.g. dcbx renegotiation). Other
678 * params may be affected by the init but would simply recalculate to the same
679 * values. The allocations made for QM init, ports, vports, pqs and vfqs are not
680 * affected as these amounts stay the same.
682 static void qed_init_qm_reset_params(struct qed_hwfn *p_hwfn)
684 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
686 qm_info->num_pqs = 0;
687 qm_info->num_vports = 0;
688 qm_info->num_pf_rls = 0;
689 qm_info->num_vf_pqs = 0;
690 qm_info->first_vf_pq = 0;
691 qm_info->first_mcos_pq = 0;
692 qm_info->first_rl_pq = 0;
695 static void qed_init_qm_advance_vport(struct qed_hwfn *p_hwfn)
697 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
699 qm_info->num_vports++;
701 if (qm_info->num_vports > qed_init_qm_get_num_vports(p_hwfn))
703 "vport overflow! qm_info->num_vports %d, qm_init_get_num_vports() %d\n",
704 qm_info->num_vports, qed_init_qm_get_num_vports(p_hwfn));
707 /* initialize a single pq and manage qm_info resources accounting.
708 * The pq_init_flags param determines whether the PQ is rate limited
709 * (for VF or PF) and whether a new vport is allocated to the pq or not
710 * (i.e. vport will be shared).
713 /* flags for pq init */
714 #define PQ_INIT_SHARE_VPORT (1 << 0)
715 #define PQ_INIT_PF_RL (1 << 1)
716 #define PQ_INIT_VF_RL (1 << 2)
718 /* defines for pq init */
719 #define PQ_INIT_DEFAULT_WRR_GROUP 1
720 #define PQ_INIT_DEFAULT_TC 0
722 void qed_hw_info_set_offload_tc(struct qed_hw_info *p_info, u8 tc)
724 p_info->offload_tc = tc;
725 p_info->offload_tc_set = true;
728 static bool qed_is_offload_tc_set(struct qed_hwfn *p_hwfn)
730 return p_hwfn->hw_info.offload_tc_set;
733 static u32 qed_get_offload_tc(struct qed_hwfn *p_hwfn)
735 if (qed_is_offload_tc_set(p_hwfn))
736 return p_hwfn->hw_info.offload_tc;
738 return PQ_INIT_DEFAULT_TC;
741 static void qed_init_qm_pq(struct qed_hwfn *p_hwfn,
742 struct qed_qm_info *qm_info,
743 u8 tc, u32 pq_init_flags)
745 u16 pq_idx = qm_info->num_pqs, max_pq = qed_init_qm_get_num_pqs(p_hwfn);
749 "pq overflow! pq %d, max pq %d\n", pq_idx, max_pq);
752 qm_info->qm_pq_params[pq_idx].port_id = p_hwfn->port_id;
753 qm_info->qm_pq_params[pq_idx].vport_id = qm_info->start_vport +
755 qm_info->qm_pq_params[pq_idx].tc_id = tc;
756 qm_info->qm_pq_params[pq_idx].wrr_group = PQ_INIT_DEFAULT_WRR_GROUP;
757 qm_info->qm_pq_params[pq_idx].rl_valid =
758 (pq_init_flags & PQ_INIT_PF_RL || pq_init_flags & PQ_INIT_VF_RL);
760 /* qm params accounting */
762 if (!(pq_init_flags & PQ_INIT_SHARE_VPORT))
763 qm_info->num_vports++;
765 if (pq_init_flags & PQ_INIT_PF_RL)
766 qm_info->num_pf_rls++;
768 if (qm_info->num_vports > qed_init_qm_get_num_vports(p_hwfn))
770 "vport overflow! qm_info->num_vports %d, qm_init_get_num_vports() %d\n",
771 qm_info->num_vports, qed_init_qm_get_num_vports(p_hwfn));
773 if (qm_info->num_pf_rls > qed_init_qm_get_num_pf_rls(p_hwfn))
775 "rl overflow! qm_info->num_pf_rls %d, qm_init_get_num_pf_rls() %d\n",
776 qm_info->num_pf_rls, qed_init_qm_get_num_pf_rls(p_hwfn));
779 /* get pq index according to PQ_FLAGS */
780 static u16 *qed_init_qm_get_idx_from_flags(struct qed_hwfn *p_hwfn,
781 unsigned long pq_flags)
783 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
785 /* Can't have multiple flags set here */
786 if (bitmap_weight(&pq_flags,
787 sizeof(pq_flags) * BITS_PER_BYTE) > 1) {
788 DP_ERR(p_hwfn, "requested multiple pq flags 0x%lx\n", pq_flags);
792 if (!(qed_get_pq_flags(p_hwfn) & pq_flags)) {
793 DP_ERR(p_hwfn, "pq flag 0x%lx is not set\n", pq_flags);
799 return &qm_info->first_rl_pq;
801 return &qm_info->first_mcos_pq;
803 return &qm_info->pure_lb_pq;
805 return &qm_info->ooo_pq;
807 return &qm_info->pure_ack_pq;
809 return &qm_info->first_ofld_pq;
811 return &qm_info->first_llt_pq;
813 return &qm_info->first_vf_pq;
819 return &qm_info->start_pq;
822 /* save pq index in qm info */
823 static void qed_init_qm_set_idx(struct qed_hwfn *p_hwfn,
824 u32 pq_flags, u16 pq_val)
826 u16 *base_pq_idx = qed_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
828 *base_pq_idx = p_hwfn->qm_info.start_pq + pq_val;
831 /* get tx pq index, with the PQ TX base already set (ready for context init) */
832 u16 qed_get_cm_pq_idx(struct qed_hwfn *p_hwfn, u32 pq_flags)
834 u16 *base_pq_idx = qed_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
836 return *base_pq_idx + CM_TX_PQ_BASE;
839 u16 qed_get_cm_pq_idx_mcos(struct qed_hwfn *p_hwfn, u8 tc)
841 u8 max_tc = qed_init_qm_get_num_tcs(p_hwfn);
844 DP_ERR(p_hwfn, "pq with flag 0x%lx do not exist\n",
846 return p_hwfn->qm_info.start_pq;
850 DP_ERR(p_hwfn, "tc %d must be smaller than %d\n", tc, max_tc);
852 return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_MCOS) + (tc % max_tc);
855 u16 qed_get_cm_pq_idx_vf(struct qed_hwfn *p_hwfn, u16 vf)
857 u16 max_vf = qed_init_qm_get_num_vfs(p_hwfn);
860 DP_ERR(p_hwfn, "pq with flag 0x%lx do not exist\n",
862 return p_hwfn->qm_info.start_pq;
866 DP_ERR(p_hwfn, "vf %d must be smaller than %d\n", vf, max_vf);
868 return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_VFS) + (vf % max_vf);
871 u16 qed_get_cm_pq_idx_ofld_mtc(struct qed_hwfn *p_hwfn, u8 tc)
873 u16 first_ofld_pq, pq_offset;
875 first_ofld_pq = qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_OFLD);
876 pq_offset = (tc < qed_init_qm_get_num_mtc_tcs(p_hwfn)) ?
877 tc : PQ_INIT_DEFAULT_TC;
879 return first_ofld_pq + pq_offset;
882 u16 qed_get_cm_pq_idx_llt_mtc(struct qed_hwfn *p_hwfn, u8 tc)
884 u16 first_llt_pq, pq_offset;
886 first_llt_pq = qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_LLT);
887 pq_offset = (tc < qed_init_qm_get_num_mtc_tcs(p_hwfn)) ?
888 tc : PQ_INIT_DEFAULT_TC;
890 return first_llt_pq + pq_offset;
893 /* Functions for creating specific types of pqs */
894 static void qed_init_qm_lb_pq(struct qed_hwfn *p_hwfn)
896 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
898 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_LB))
901 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_LB, qm_info->num_pqs);
902 qed_init_qm_pq(p_hwfn, qm_info, PURE_LB_TC, PQ_INIT_SHARE_VPORT);
905 static void qed_init_qm_ooo_pq(struct qed_hwfn *p_hwfn)
907 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
909 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_OOO))
912 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_OOO, qm_info->num_pqs);
913 qed_init_qm_pq(p_hwfn, qm_info, qm_info->ooo_tc, PQ_INIT_SHARE_VPORT);
916 static void qed_init_qm_pure_ack_pq(struct qed_hwfn *p_hwfn)
918 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
920 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_ACK))
923 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_ACK, qm_info->num_pqs);
924 qed_init_qm_pq(p_hwfn, qm_info, qed_get_offload_tc(p_hwfn),
925 PQ_INIT_SHARE_VPORT);
928 static void qed_init_qm_mtc_pqs(struct qed_hwfn *p_hwfn)
930 u8 num_tcs = qed_init_qm_get_num_mtc_tcs(p_hwfn);
931 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
934 /* override pq's TC if offload TC is set */
935 for (tc = 0; tc < num_tcs; tc++)
936 qed_init_qm_pq(p_hwfn, qm_info,
937 qed_is_offload_tc_set(p_hwfn) ?
938 p_hwfn->hw_info.offload_tc : tc,
939 PQ_INIT_SHARE_VPORT);
942 static void qed_init_qm_offload_pq(struct qed_hwfn *p_hwfn)
944 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
946 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_OFLD))
949 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_OFLD, qm_info->num_pqs);
950 qed_init_qm_mtc_pqs(p_hwfn);
953 static void qed_init_qm_low_latency_pq(struct qed_hwfn *p_hwfn)
955 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
957 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_LLT))
960 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_LLT, qm_info->num_pqs);
961 qed_init_qm_mtc_pqs(p_hwfn);
964 static void qed_init_qm_mcos_pqs(struct qed_hwfn *p_hwfn)
966 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
969 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_MCOS))
972 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_MCOS, qm_info->num_pqs);
973 for (tc_idx = 0; tc_idx < qed_init_qm_get_num_tcs(p_hwfn); tc_idx++)
974 qed_init_qm_pq(p_hwfn, qm_info, tc_idx, PQ_INIT_SHARE_VPORT);
977 static void qed_init_qm_vf_pqs(struct qed_hwfn *p_hwfn)
979 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
980 u16 vf_idx, num_vfs = qed_init_qm_get_num_vfs(p_hwfn);
982 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_VFS))
985 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_VFS, qm_info->num_pqs);
986 qm_info->num_vf_pqs = num_vfs;
987 for (vf_idx = 0; vf_idx < num_vfs; vf_idx++)
988 qed_init_qm_pq(p_hwfn,
989 qm_info, PQ_INIT_DEFAULT_TC, PQ_INIT_VF_RL);
992 static void qed_init_qm_rl_pqs(struct qed_hwfn *p_hwfn)
994 u16 pf_rls_idx, num_pf_rls = qed_init_qm_get_num_pf_rls(p_hwfn);
995 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
997 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_RLS))
1000 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_RLS, qm_info->num_pqs);
1001 for (pf_rls_idx = 0; pf_rls_idx < num_pf_rls; pf_rls_idx++)
1002 qed_init_qm_pq(p_hwfn, qm_info, qed_get_offload_tc(p_hwfn),
1006 static void qed_init_qm_pq_params(struct qed_hwfn *p_hwfn)
1008 /* rate limited pqs, must come first (FW assumption) */
1009 qed_init_qm_rl_pqs(p_hwfn);
1011 /* pqs for multi cos */
1012 qed_init_qm_mcos_pqs(p_hwfn);
1014 /* pure loopback pq */
1015 qed_init_qm_lb_pq(p_hwfn);
1017 /* out of order pq */
1018 qed_init_qm_ooo_pq(p_hwfn);
1021 qed_init_qm_pure_ack_pq(p_hwfn);
1023 /* pq for offloaded protocol */
1024 qed_init_qm_offload_pq(p_hwfn);
1026 /* low latency pq */
1027 qed_init_qm_low_latency_pq(p_hwfn);
1029 /* done sharing vports */
1030 qed_init_qm_advance_vport(p_hwfn);
1033 qed_init_qm_vf_pqs(p_hwfn);
1036 /* compare values of getters against resources amounts */
1037 static int qed_init_qm_sanity(struct qed_hwfn *p_hwfn)
1039 if (qed_init_qm_get_num_vports(p_hwfn) > RESC_NUM(p_hwfn, QED_VPORT)) {
1040 DP_ERR(p_hwfn, "requested amount of vports exceeds resource\n");
1044 if (qed_init_qm_get_num_pqs(p_hwfn) <= RESC_NUM(p_hwfn, QED_PQ))
1047 if (QED_IS_ROCE_PERSONALITY(p_hwfn)) {
1048 p_hwfn->hw_info.multi_tc_roce_en = 0;
1050 "multi-tc roce was disabled to reduce requested amount of pqs\n");
1051 if (qed_init_qm_get_num_pqs(p_hwfn) <= RESC_NUM(p_hwfn, QED_PQ))
1055 DP_ERR(p_hwfn, "requested amount of pqs exceeds resource\n");
1059 static void qed_dp_init_qm_params(struct qed_hwfn *p_hwfn)
1061 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1062 struct init_qm_vport_params *vport;
1063 struct init_qm_port_params *port;
1064 struct init_qm_pq_params *pq;
1067 /* top level params */
1070 "qm init top level params: start_pq %d, start_vport %d, pure_lb_pq %d, offload_pq %d, llt_pq %d, pure_ack_pq %d\n",
1072 qm_info->start_vport,
1073 qm_info->pure_lb_pq,
1074 qm_info->first_ofld_pq,
1075 qm_info->first_llt_pq,
1076 qm_info->pure_ack_pq);
1079 "ooo_pq %d, first_vf_pq %d, num_pqs %d, num_vf_pqs %d, num_vports %d, max_phys_tcs_per_port %d\n",
1081 qm_info->first_vf_pq,
1083 qm_info->num_vf_pqs,
1084 qm_info->num_vports, qm_info->max_phys_tcs_per_port);
1087 "pf_rl_en %d, pf_wfq_en %d, vport_rl_en %d, vport_wfq_en %d, pf_wfq %d, pf_rl %d, num_pf_rls %d, pq_flags %x\n",
1090 qm_info->vport_rl_en,
1091 qm_info->vport_wfq_en,
1094 qm_info->num_pf_rls, qed_get_pq_flags(p_hwfn));
1097 for (i = 0; i < p_hwfn->cdev->num_ports_in_engine; i++) {
1098 port = &(qm_info->qm_port_params[i]);
1101 "port idx %d, active %d, active_phys_tcs %d, num_pbf_cmd_lines %d, num_btb_blocks %d, reserved %d\n",
1104 port->active_phys_tcs,
1105 port->num_pbf_cmd_lines,
1106 port->num_btb_blocks, port->reserved);
1110 for (i = 0; i < qm_info->num_vports; i++) {
1111 vport = &(qm_info->qm_vport_params[i]);
1114 "vport idx %d, vport_rl %d, wfq %d, first_tx_pq_id [ ",
1115 qm_info->start_vport + i,
1116 vport->vport_rl, vport->vport_wfq);
1117 for (tc = 0; tc < NUM_OF_TCS; tc++)
1120 "%d ", vport->first_tx_pq_id[tc]);
1121 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "]\n");
1125 for (i = 0; i < qm_info->num_pqs; i++) {
1126 pq = &(qm_info->qm_pq_params[i]);
1129 "pq idx %d, port %d, vport_id %d, tc %d, wrr_grp %d, rl_valid %d\n",
1130 qm_info->start_pq + i,
1133 pq->tc_id, pq->wrr_group, pq->rl_valid);
1137 static void qed_init_qm_info(struct qed_hwfn *p_hwfn)
1139 /* reset params required for init run */
1140 qed_init_qm_reset_params(p_hwfn);
1142 /* init QM top level params */
1143 qed_init_qm_params(p_hwfn);
1145 /* init QM port params */
1146 qed_init_qm_port_params(p_hwfn);
1148 /* init QM vport params */
1149 qed_init_qm_vport_params(p_hwfn);
1151 /* init QM physical queue params */
1152 qed_init_qm_pq_params(p_hwfn);
1154 /* display all that init */
1155 qed_dp_init_qm_params(p_hwfn);
1158 /* This function reconfigures the QM pf on the fly.
1159 * For this purpose we:
1160 * 1. reconfigure the QM database
1161 * 2. set new values to runtime array
1162 * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
1163 * 4. activate init tool in QM_PF stage
1164 * 5. send an sdm_qm_cmd through rbc interface to release the QM
1166 int qed_qm_reconf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1168 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1172 /* initialize qed's qm data structure */
1173 qed_init_qm_info(p_hwfn);
1175 /* stop PF's qm queues */
1176 spin_lock_bh(&qm_lock);
1177 b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
1178 qm_info->start_pq, qm_info->num_pqs);
1179 spin_unlock_bh(&qm_lock);
1183 /* clear the QM_PF runtime phase leftovers from previous init */
1184 qed_init_clear_rt_data(p_hwfn);
1186 /* prepare QM portion of runtime array */
1187 qed_qm_init_pf(p_hwfn, p_ptt, false);
1189 /* activate init tool on runtime array */
1190 rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
1191 p_hwfn->hw_info.hw_mode);
1195 /* start PF's qm queues */
1196 spin_lock_bh(&qm_lock);
1197 b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
1198 qm_info->start_pq, qm_info->num_pqs);
1199 spin_unlock_bh(&qm_lock);
1206 static int qed_alloc_qm_data(struct qed_hwfn *p_hwfn)
1208 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1211 rc = qed_init_qm_sanity(p_hwfn);
1215 qm_info->qm_pq_params = kcalloc(qed_init_qm_get_num_pqs(p_hwfn),
1216 sizeof(*qm_info->qm_pq_params),
1218 if (!qm_info->qm_pq_params)
1221 qm_info->qm_vport_params = kcalloc(qed_init_qm_get_num_vports(p_hwfn),
1222 sizeof(*qm_info->qm_vport_params),
1224 if (!qm_info->qm_vport_params)
1227 qm_info->qm_port_params = kcalloc(p_hwfn->cdev->num_ports_in_engine,
1228 sizeof(*qm_info->qm_port_params),
1230 if (!qm_info->qm_port_params)
1233 qm_info->wfq_data = kcalloc(qed_init_qm_get_num_vports(p_hwfn),
1234 sizeof(*qm_info->wfq_data),
1236 if (!qm_info->wfq_data)
1242 DP_NOTICE(p_hwfn, "Failed to allocate memory for QM params\n");
1243 qed_qm_info_free(p_hwfn);
1247 int qed_resc_alloc(struct qed_dev *cdev)
1249 u32 rdma_tasks, excess_tasks;
1254 for_each_hwfn(cdev, i) {
1255 rc = qed_l2_alloc(&cdev->hwfns[i]);
1262 cdev->fw_data = kzalloc(sizeof(*cdev->fw_data), GFP_KERNEL);
1266 for_each_hwfn(cdev, i) {
1267 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1268 u32 n_eqes, num_cons;
1270 /* Initialize the doorbell recovery mechanism */
1271 rc = qed_db_recovery_setup(p_hwfn);
1275 /* First allocate the context manager structure */
1276 rc = qed_cxt_mngr_alloc(p_hwfn);
1280 /* Set the HW cid/tid numbers (in the contest manager)
1281 * Must be done prior to any further computations.
1283 rc = qed_cxt_set_pf_params(p_hwfn, RDMA_MAX_TIDS);
1287 rc = qed_alloc_qm_data(p_hwfn);
1292 qed_init_qm_info(p_hwfn);
1294 /* Compute the ILT client partition */
1295 rc = qed_cxt_cfg_ilt_compute(p_hwfn, &line_count);
1298 "too many ILT lines; re-computing with less lines\n");
1299 /* In case there are not enough ILT lines we reduce the
1300 * number of RDMA tasks and re-compute.
1303 qed_cxt_cfg_ilt_compute_excess(p_hwfn, line_count);
1307 rdma_tasks = RDMA_MAX_TIDS - excess_tasks;
1308 rc = qed_cxt_set_pf_params(p_hwfn, rdma_tasks);
1312 rc = qed_cxt_cfg_ilt_compute(p_hwfn, &line_count);
1315 "failed ILT compute. Requested too many lines: %u\n",
1322 /* CID map / ILT shadow table / T2
1323 * The talbes sizes are determined by the computations above
1325 rc = qed_cxt_tables_alloc(p_hwfn);
1329 /* SPQ, must follow ILT because initializes SPQ context */
1330 rc = qed_spq_alloc(p_hwfn);
1334 /* SP status block allocation */
1335 p_hwfn->p_dpc_ptt = qed_get_reserved_ptt(p_hwfn,
1338 rc = qed_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
1342 rc = qed_iov_alloc(p_hwfn);
1347 n_eqes = qed_chain_get_capacity(&p_hwfn->p_spq->chain);
1348 if (QED_IS_RDMA_PERSONALITY(p_hwfn)) {
1349 enum protocol_type rdma_proto;
1351 if (QED_IS_ROCE_PERSONALITY(p_hwfn))
1352 rdma_proto = PROTOCOLID_ROCE;
1354 rdma_proto = PROTOCOLID_IWARP;
1356 num_cons = qed_cxt_get_proto_cid_count(p_hwfn,
1359 n_eqes += num_cons + 2 * MAX_NUM_VFS_BB;
1360 } else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
1362 qed_cxt_get_proto_cid_count(p_hwfn,
1365 n_eqes += 2 * num_cons;
1368 if (n_eqes > 0xFFFF) {
1370 "Cannot allocate 0x%x EQ elements. The maximum of a u16 chain is 0x%x\n",
1375 rc = qed_eq_alloc(p_hwfn, (u16) n_eqes);
1379 rc = qed_consq_alloc(p_hwfn);
1383 rc = qed_l2_alloc(p_hwfn);
1387 #ifdef CONFIG_QED_LL2
1388 if (p_hwfn->using_ll2) {
1389 rc = qed_ll2_alloc(p_hwfn);
1395 if (p_hwfn->hw_info.personality == QED_PCI_FCOE) {
1396 rc = qed_fcoe_alloc(p_hwfn);
1401 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
1402 rc = qed_iscsi_alloc(p_hwfn);
1405 rc = qed_ooo_alloc(p_hwfn);
1410 if (QED_IS_RDMA_PERSONALITY(p_hwfn)) {
1411 rc = qed_rdma_info_alloc(p_hwfn);
1416 /* DMA info initialization */
1417 rc = qed_dmae_info_alloc(p_hwfn);
1421 /* DCBX initialization */
1422 rc = qed_dcbx_info_alloc(p_hwfn);
1426 rc = qed_dbg_alloc_user_data(p_hwfn);
1431 cdev->reset_stats = kzalloc(sizeof(*cdev->reset_stats), GFP_KERNEL);
1432 if (!cdev->reset_stats)
1440 qed_resc_free(cdev);
1444 void qed_resc_setup(struct qed_dev *cdev)
1449 for_each_hwfn(cdev, i)
1450 qed_l2_setup(&cdev->hwfns[i]);
1454 for_each_hwfn(cdev, i) {
1455 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1457 qed_cxt_mngr_setup(p_hwfn);
1458 qed_spq_setup(p_hwfn);
1459 qed_eq_setup(p_hwfn);
1460 qed_consq_setup(p_hwfn);
1462 /* Read shadow of current MFW mailbox */
1463 qed_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
1464 memcpy(p_hwfn->mcp_info->mfw_mb_shadow,
1465 p_hwfn->mcp_info->mfw_mb_cur,
1466 p_hwfn->mcp_info->mfw_mb_length);
1468 qed_int_setup(p_hwfn, p_hwfn->p_main_ptt);
1470 qed_l2_setup(p_hwfn);
1471 qed_iov_setup(p_hwfn);
1472 #ifdef CONFIG_QED_LL2
1473 if (p_hwfn->using_ll2)
1474 qed_ll2_setup(p_hwfn);
1476 if (p_hwfn->hw_info.personality == QED_PCI_FCOE)
1477 qed_fcoe_setup(p_hwfn);
1479 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
1480 qed_iscsi_setup(p_hwfn);
1481 qed_ooo_setup(p_hwfn);
1486 #define FINAL_CLEANUP_POLL_CNT (100)
1487 #define FINAL_CLEANUP_POLL_TIME (10)
1488 int qed_final_cleanup(struct qed_hwfn *p_hwfn,
1489 struct qed_ptt *p_ptt, u16 id, bool is_vf)
1491 u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
1494 addr = GTT_BAR0_MAP_REG_USDM_RAM +
1495 USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
1500 command |= X_FINAL_CLEANUP_AGG_INT <<
1501 SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
1502 command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
1503 command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
1504 command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
1506 /* Make sure notification is not set before initiating final cleanup */
1507 if (REG_RD(p_hwfn, addr)) {
1509 "Unexpected; Found final cleanup notification before initiating final cleanup\n");
1510 REG_WR(p_hwfn, addr, 0);
1513 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
1514 "Sending final cleanup for PFVF[%d] [Command %08x]\n",
1517 qed_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);
1519 /* Poll until completion */
1520 while (!REG_RD(p_hwfn, addr) && count--)
1521 msleep(FINAL_CLEANUP_POLL_TIME);
1523 if (REG_RD(p_hwfn, addr))
1527 "Failed to receive FW final cleanup notification\n");
1529 /* Cleanup afterwards */
1530 REG_WR(p_hwfn, addr, 0);
1535 static int qed_calc_hw_mode(struct qed_hwfn *p_hwfn)
1539 if (QED_IS_BB_B0(p_hwfn->cdev)) {
1540 hw_mode |= 1 << MODE_BB;
1541 } else if (QED_IS_AH(p_hwfn->cdev)) {
1542 hw_mode |= 1 << MODE_K2;
1544 DP_NOTICE(p_hwfn, "Unknown chip type %#x\n",
1545 p_hwfn->cdev->type);
1549 switch (p_hwfn->cdev->num_ports_in_engine) {
1551 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
1554 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
1557 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
1560 DP_NOTICE(p_hwfn, "num_ports_in_engine = %d not supported\n",
1561 p_hwfn->cdev->num_ports_in_engine);
1565 if (test_bit(QED_MF_OVLAN_CLSS, &p_hwfn->cdev->mf_bits))
1566 hw_mode |= 1 << MODE_MF_SD;
1568 hw_mode |= 1 << MODE_MF_SI;
1570 hw_mode |= 1 << MODE_ASIC;
1572 if (p_hwfn->cdev->num_hwfns > 1)
1573 hw_mode |= 1 << MODE_100G;
1575 p_hwfn->hw_info.hw_mode = hw_mode;
1577 DP_VERBOSE(p_hwfn, (NETIF_MSG_PROBE | NETIF_MSG_IFUP),
1578 "Configuring function for hw_mode: 0x%08x\n",
1579 p_hwfn->hw_info.hw_mode);
1584 /* Init run time data for all PFs on an engine. */
1585 static void qed_init_cau_rt_data(struct qed_dev *cdev)
1587 u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
1590 for_each_hwfn(cdev, i) {
1591 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1592 struct qed_igu_info *p_igu_info;
1593 struct qed_igu_block *p_block;
1594 struct cau_sb_entry sb_entry;
1596 p_igu_info = p_hwfn->hw_info.p_igu_info;
1599 igu_sb_id < QED_MAPPING_MEMORY_SIZE(cdev); igu_sb_id++) {
1600 p_block = &p_igu_info->entry[igu_sb_id];
1602 if (!p_block->is_pf)
1605 qed_init_cau_sb_entry(p_hwfn, &sb_entry,
1606 p_block->function_id, 0, 0);
1607 STORE_RT_REG_AGG(p_hwfn, offset + igu_sb_id * 2,
1613 static void qed_init_cache_line_size(struct qed_hwfn *p_hwfn,
1614 struct qed_ptt *p_ptt)
1616 u32 val, wr_mbs, cache_line_size;
1618 val = qed_rd(p_hwfn, p_ptt, PSWRQ2_REG_WR_MBS0);
1631 "Unexpected value of PSWRQ2_REG_WR_MBS0 [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
1636 cache_line_size = min_t(u32, L1_CACHE_BYTES, wr_mbs);
1637 switch (cache_line_size) {
1652 "Unexpected value of cache line size [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
1656 if (L1_CACHE_BYTES > wr_mbs)
1658 "The cache line size for padding is suboptimal for performance [OS cache line size 0x%x, wr mbs 0x%x]\n",
1659 L1_CACHE_BYTES, wr_mbs);
1661 STORE_RT_REG(p_hwfn, PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET, val);
1663 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET, val);
1664 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET, val);
1668 static int qed_hw_init_common(struct qed_hwfn *p_hwfn,
1669 struct qed_ptt *p_ptt, int hw_mode)
1671 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1672 struct qed_qm_common_rt_init_params params;
1673 struct qed_dev *cdev = p_hwfn->cdev;
1674 u8 vf_id, max_num_vfs;
1679 qed_init_cau_rt_data(cdev);
1681 /* Program GTT windows */
1682 qed_gtt_init(p_hwfn);
1684 if (p_hwfn->mcp_info) {
1685 if (p_hwfn->mcp_info->func_info.bandwidth_max)
1686 qm_info->pf_rl_en = true;
1687 if (p_hwfn->mcp_info->func_info.bandwidth_min)
1688 qm_info->pf_wfq_en = true;
1691 memset(¶ms, 0, sizeof(params));
1692 params.max_ports_per_engine = p_hwfn->cdev->num_ports_in_engine;
1693 params.max_phys_tcs_per_port = qm_info->max_phys_tcs_per_port;
1694 params.pf_rl_en = qm_info->pf_rl_en;
1695 params.pf_wfq_en = qm_info->pf_wfq_en;
1696 params.vport_rl_en = qm_info->vport_rl_en;
1697 params.vport_wfq_en = qm_info->vport_wfq_en;
1698 params.port_params = qm_info->qm_port_params;
1700 qed_qm_common_rt_init(p_hwfn, ¶ms);
1702 qed_cxt_hw_init_common(p_hwfn);
1704 qed_init_cache_line_size(p_hwfn, p_ptt);
1706 rc = qed_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);
1710 qed_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
1711 qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
1713 if (QED_IS_BB(p_hwfn->cdev)) {
1714 num_pfs = NUM_OF_ENG_PFS(p_hwfn->cdev);
1715 for (pf_id = 0; pf_id < num_pfs; pf_id++) {
1716 qed_fid_pretend(p_hwfn, p_ptt, pf_id);
1717 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1718 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1720 /* pretend to original PF */
1721 qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1724 max_num_vfs = QED_IS_AH(cdev) ? MAX_NUM_VFS_K2 : MAX_NUM_VFS_BB;
1725 for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
1726 concrete_fid = qed_vfid_to_concrete(p_hwfn, vf_id);
1727 qed_fid_pretend(p_hwfn, p_ptt, (u16) concrete_fid);
1728 qed_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
1729 qed_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
1730 qed_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
1731 qed_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
1733 /* pretend to original PF */
1734 qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1740 qed_hw_init_dpi_size(struct qed_hwfn *p_hwfn,
1741 struct qed_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus)
1743 u32 dpi_bit_shift, dpi_count, dpi_page_size;
1747 /* Calculate DPI size */
1748 n_wids = max_t(u32, QED_MIN_WIDS, n_cpus);
1749 dpi_page_size = QED_WID_SIZE * roundup_pow_of_two(n_wids);
1750 dpi_page_size = (dpi_page_size + PAGE_SIZE - 1) & ~(PAGE_SIZE - 1);
1751 dpi_bit_shift = ilog2(dpi_page_size / 4096);
1752 dpi_count = pwm_region_size / dpi_page_size;
1754 min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis;
1755 min_dpis = max_t(u32, QED_MIN_DPIS, min_dpis);
1757 p_hwfn->dpi_size = dpi_page_size;
1758 p_hwfn->dpi_count = dpi_count;
1760 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift);
1762 if (dpi_count < min_dpis)
1768 enum QED_ROCE_EDPM_MODE {
1769 QED_ROCE_EDPM_MODE_ENABLE = 0,
1770 QED_ROCE_EDPM_MODE_FORCE_ON = 1,
1771 QED_ROCE_EDPM_MODE_DISABLE = 2,
1774 bool qed_edpm_enabled(struct qed_hwfn *p_hwfn)
1776 if (p_hwfn->dcbx_no_edpm || p_hwfn->db_bar_no_edpm)
1783 qed_hw_init_pf_doorbell_bar(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1785 u32 pwm_regsize, norm_regsize;
1786 u32 non_pwm_conn, min_addr_reg1;
1787 u32 db_bar_size, n_cpus = 1;
1793 db_bar_size = qed_hw_bar_size(p_hwfn, p_ptt, BAR_ID_1);
1794 if (p_hwfn->cdev->num_hwfns > 1)
1797 /* Calculate doorbell regions */
1798 non_pwm_conn = qed_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
1799 qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
1801 qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH,
1803 norm_regsize = roundup(QED_PF_DEMS_SIZE * non_pwm_conn, PAGE_SIZE);
1804 min_addr_reg1 = norm_regsize / 4096;
1805 pwm_regsize = db_bar_size - norm_regsize;
1807 /* Check that the normal and PWM sizes are valid */
1808 if (db_bar_size < norm_regsize) {
1809 DP_ERR(p_hwfn->cdev,
1810 "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n",
1811 db_bar_size, norm_regsize);
1815 if (pwm_regsize < QED_MIN_PWM_REGION) {
1816 DP_ERR(p_hwfn->cdev,
1817 "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n",
1819 QED_MIN_PWM_REGION, db_bar_size, norm_regsize);
1823 /* Calculate number of DPIs */
1824 roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode;
1825 if ((roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE) ||
1826 ((roce_edpm_mode == QED_ROCE_EDPM_MODE_FORCE_ON))) {
1827 /* Either EDPM is mandatory, or we are attempting to allocate a
1830 n_cpus = num_present_cpus();
1831 rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1834 cond = (rc && (roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE)) ||
1835 (roce_edpm_mode == QED_ROCE_EDPM_MODE_DISABLE);
1836 if (cond || p_hwfn->dcbx_no_edpm) {
1837 /* Either EDPM is disabled from user configuration, or it is
1838 * disabled via DCBx, or it is not mandatory and we failed to
1839 * allocated a WID per CPU.
1842 rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1845 qed_rdma_dpm_bar(p_hwfn, p_ptt);
1848 p_hwfn->wid_count = (u16) n_cpus;
1851 "doorbell bar: normal_region_size=%d, pwm_region_size=%d, dpi_size=%d, dpi_count=%d, roce_edpm=%s, page_size=%lu\n",
1856 (!qed_edpm_enabled(p_hwfn)) ?
1857 "disabled" : "enabled", PAGE_SIZE);
1861 "Failed to allocate enough DPIs. Allocated %d but the current minimum is %d.\n",
1863 p_hwfn->pf_params.rdma_pf_params.min_dpis);
1867 p_hwfn->dpi_start_offset = norm_regsize;
1869 /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
1870 pf_dems_shift = ilog2(QED_PF_DEMS_SIZE / 4);
1871 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
1872 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
1877 static int qed_hw_init_port(struct qed_hwfn *p_hwfn,
1878 struct qed_ptt *p_ptt, int hw_mode)
1882 rc = qed_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id, hw_mode);
1886 qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_WRITE_PAD_ENABLE, 0);
1891 static int qed_hw_init_pf(struct qed_hwfn *p_hwfn,
1892 struct qed_ptt *p_ptt,
1893 struct qed_tunnel_info *p_tunn,
1896 enum qed_int_mode int_mode,
1897 bool allow_npar_tx_switch)
1899 u8 rel_pf_id = p_hwfn->rel_pf_id;
1902 if (p_hwfn->mcp_info) {
1903 struct qed_mcp_function_info *p_info;
1905 p_info = &p_hwfn->mcp_info->func_info;
1906 if (p_info->bandwidth_min)
1907 p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
1909 /* Update rate limit once we'll actually have a link */
1910 p_hwfn->qm_info.pf_rl = 100000;
1913 qed_cxt_hw_init_pf(p_hwfn, p_ptt);
1915 qed_int_igu_init_rt(p_hwfn);
1917 /* Set VLAN in NIG if needed */
1918 if (hw_mode & BIT(MODE_MF_SD)) {
1919 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "Configuring LLH_FUNC_TAG\n");
1920 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
1921 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
1922 p_hwfn->hw_info.ovlan);
1924 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
1925 "Configuring LLH_FUNC_FILTER_HDR_SEL\n");
1926 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET,
1930 /* Enable classification by MAC if needed */
1931 if (hw_mode & BIT(MODE_MF_SI)) {
1932 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
1933 "Configuring TAGMAC_CLS_TYPE\n");
1934 STORE_RT_REG(p_hwfn,
1935 NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET, 1);
1938 /* Protocol Configuration */
1939 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
1940 (p_hwfn->hw_info.personality == QED_PCI_ISCSI) ? 1 : 0);
1941 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET,
1942 (p_hwfn->hw_info.personality == QED_PCI_FCOE) ? 1 : 0);
1943 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
1945 /* Sanity check before the PF init sequence that uses DMAE */
1946 rc = qed_dmae_sanity(p_hwfn, p_ptt, "pf_phase");
1950 /* PF Init sequence */
1951 rc = qed_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
1955 /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
1956 rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
1960 /* Pure runtime initializations - directly to the HW */
1961 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
1963 rc = qed_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
1968 /* enable interrupts */
1969 qed_int_igu_enable(p_hwfn, p_ptt, int_mode);
1971 /* send function start command */
1972 rc = qed_sp_pf_start(p_hwfn, p_ptt, p_tunn,
1973 allow_npar_tx_switch);
1975 DP_NOTICE(p_hwfn, "Function start ramrod failed\n");
1978 if (p_hwfn->hw_info.personality == QED_PCI_FCOE) {
1979 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1, BIT(2));
1980 qed_wr(p_hwfn, p_ptt,
1981 PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST,
1988 int qed_pglueb_set_pfid_enable(struct qed_hwfn *p_hwfn,
1989 struct qed_ptt *p_ptt, bool b_enable)
1991 u32 delay_idx = 0, val, set_val = b_enable ? 1 : 0;
1993 /* Configure the PF's internal FID_enable for master transactions */
1994 qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
1996 /* Wait until value is set - try for 1 second every 50us */
1997 for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
1998 val = qed_rd(p_hwfn, p_ptt,
1999 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
2003 usleep_range(50, 60);
2006 if (val != set_val) {
2008 "PFID_ENABLE_MASTER wasn't changed after a second\n");
2015 static void qed_reset_mb_shadow(struct qed_hwfn *p_hwfn,
2016 struct qed_ptt *p_main_ptt)
2018 /* Read shadow of current MFW mailbox */
2019 qed_mcp_read_mb(p_hwfn, p_main_ptt);
2020 memcpy(p_hwfn->mcp_info->mfw_mb_shadow,
2021 p_hwfn->mcp_info->mfw_mb_cur, p_hwfn->mcp_info->mfw_mb_length);
2025 qed_fill_load_req_params(struct qed_load_req_params *p_load_req,
2026 struct qed_drv_load_params *p_drv_load)
2028 memset(p_load_req, 0, sizeof(*p_load_req));
2030 p_load_req->drv_role = p_drv_load->is_crash_kernel ?
2031 QED_DRV_ROLE_KDUMP : QED_DRV_ROLE_OS;
2032 p_load_req->timeout_val = p_drv_load->mfw_timeout_val;
2033 p_load_req->avoid_eng_reset = p_drv_load->avoid_eng_reset;
2034 p_load_req->override_force_load = p_drv_load->override_force_load;
2037 static int qed_vf_start(struct qed_hwfn *p_hwfn,
2038 struct qed_hw_init_params *p_params)
2040 if (p_params->p_tunn) {
2041 qed_vf_set_vf_start_tunn_update_param(p_params->p_tunn);
2042 qed_vf_pf_tunnel_param_update(p_hwfn, p_params->p_tunn);
2045 p_hwfn->b_int_enabled = true;
2050 static void qed_pglueb_clear_err(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2052 qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR,
2053 BIT(p_hwfn->abs_pf_id));
2056 int qed_hw_init(struct qed_dev *cdev, struct qed_hw_init_params *p_params)
2058 struct qed_load_req_params load_req_params;
2059 u32 load_code, resp, param, drv_mb_param;
2060 bool b_default_mtu = true;
2061 struct qed_hwfn *p_hwfn;
2065 if ((p_params->int_mode == QED_INT_MODE_MSI) && (cdev->num_hwfns > 1)) {
2066 DP_NOTICE(cdev, "MSI mode is not supported for CMT devices\n");
2071 rc = qed_init_fw_data(cdev, p_params->bin_fw_data);
2076 for_each_hwfn(cdev, i) {
2077 p_hwfn = &cdev->hwfns[i];
2079 /* If management didn't provide a default, set one of our own */
2080 if (!p_hwfn->hw_info.mtu) {
2081 p_hwfn->hw_info.mtu = 1500;
2082 b_default_mtu = false;
2086 qed_vf_start(p_hwfn, p_params);
2090 rc = qed_calc_hw_mode(p_hwfn);
2094 if (IS_PF(cdev) && (test_bit(QED_MF_8021Q_TAGGING,
2096 test_bit(QED_MF_8021AD_TAGGING,
2098 if (test_bit(QED_MF_8021Q_TAGGING, &cdev->mf_bits))
2099 ether_type = ETH_P_8021Q;
2101 ether_type = ETH_P_8021AD;
2102 STORE_RT_REG(p_hwfn, PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET,
2104 STORE_RT_REG(p_hwfn, NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET,
2106 STORE_RT_REG(p_hwfn, PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET,
2108 STORE_RT_REG(p_hwfn, DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET,
2112 qed_fill_load_req_params(&load_req_params,
2113 p_params->p_drv_load_params);
2114 rc = qed_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt,
2117 DP_NOTICE(p_hwfn, "Failed sending a LOAD_REQ command\n");
2121 load_code = load_req_params.load_code;
2122 DP_VERBOSE(p_hwfn, QED_MSG_SP,
2123 "Load request was sent. Load code: 0x%x\n",
2126 /* Only relevant for recovery:
2127 * Clear the indication after LOAD_REQ is responded by the MFW.
2129 cdev->recov_in_prog = false;
2131 qed_mcp_set_capabilities(p_hwfn, p_hwfn->p_main_ptt);
2133 qed_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
2135 /* Clean up chip from previous driver if such remains exist.
2136 * This is not needed when the PF is the first one on the
2137 * engine, since afterwards we are going to init the FW.
2139 if (load_code != FW_MSG_CODE_DRV_LOAD_ENGINE) {
2140 rc = qed_final_cleanup(p_hwfn, p_hwfn->p_main_ptt,
2141 p_hwfn->rel_pf_id, false);
2143 DP_NOTICE(p_hwfn, "Final cleanup failed\n");
2148 /* Log and clear previous pglue_b errors if such exist */
2149 qed_pglueb_rbc_attn_handler(p_hwfn, p_hwfn->p_main_ptt);
2151 /* Enable the PF's internal FID_enable in the PXP */
2152 rc = qed_pglueb_set_pfid_enable(p_hwfn, p_hwfn->p_main_ptt,
2157 /* Clear the pglue_b was_error indication.
2158 * In E4 it must be done after the BME and the internal
2159 * FID_enable for the PF are set, since VDMs may cause the
2160 * indication to be set again.
2162 qed_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt);
2164 switch (load_code) {
2165 case FW_MSG_CODE_DRV_LOAD_ENGINE:
2166 rc = qed_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
2167 p_hwfn->hw_info.hw_mode);
2171 case FW_MSG_CODE_DRV_LOAD_PORT:
2172 rc = qed_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
2173 p_hwfn->hw_info.hw_mode);
2178 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
2179 rc = qed_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
2181 p_hwfn->hw_info.hw_mode,
2182 p_params->b_hw_start,
2184 p_params->allow_npar_tx_switch);
2188 "Unexpected load code [0x%08x]", load_code);
2195 "init phase failed for loadcode 0x%x (rc %d)\n",
2200 rc = qed_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt);
2204 /* send DCBX attention request command */
2207 "sending phony dcbx set command to trigger DCBx attention handling\n");
2208 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2209 DRV_MSG_CODE_SET_DCBX,
2210 1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT,
2214 "Failed to send DCBX attention request\n");
2218 p_hwfn->hw_init_done = true;
2222 p_hwfn = QED_LEADING_HWFN(cdev);
2224 /* Get pre-negotiated values for stag, bandwidth etc. */
2227 "Sending GET_OEM_UPDATES command to trigger stag/bandwidth attention handling\n");
2228 drv_mb_param = 1 << DRV_MB_PARAM_DUMMY_OEM_UPDATES_OFFSET;
2229 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2230 DRV_MSG_CODE_GET_OEM_UPDATES,
2231 drv_mb_param, &resp, ¶m);
2234 "Failed to send GET_OEM_UPDATES attention request\n");
2236 drv_mb_param = STORM_FW_VERSION;
2237 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2238 DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER,
2239 drv_mb_param, &load_code, ¶m);
2241 DP_INFO(p_hwfn, "Failed to update firmware version\n");
2243 if (!b_default_mtu) {
2244 rc = qed_mcp_ov_update_mtu(p_hwfn, p_hwfn->p_main_ptt,
2245 p_hwfn->hw_info.mtu);
2248 "Failed to update default mtu\n");
2251 rc = qed_mcp_ov_update_driver_state(p_hwfn,
2253 QED_OV_DRIVER_STATE_DISABLED);
2255 DP_INFO(p_hwfn, "Failed to update driver state\n");
2257 rc = qed_mcp_ov_update_eswitch(p_hwfn, p_hwfn->p_main_ptt,
2258 QED_OV_ESWITCH_NONE);
2260 DP_INFO(p_hwfn, "Failed to update eswitch mode\n");
2266 /* The MFW load lock should be released also when initialization fails.
2268 qed_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt);
2272 #define QED_HW_STOP_RETRY_LIMIT (10)
2273 static void qed_hw_timers_stop(struct qed_dev *cdev,
2274 struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2279 qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
2280 qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
2282 if (cdev->recov_in_prog)
2285 for (i = 0; i < QED_HW_STOP_RETRY_LIMIT; i++) {
2286 if ((!qed_rd(p_hwfn, p_ptt,
2287 TM_REG_PF_SCAN_ACTIVE_CONN)) &&
2288 (!qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
2291 /* Dependent on number of connection/tasks, possibly
2292 * 1ms sleep is required between polls
2294 usleep_range(1000, 2000);
2297 if (i < QED_HW_STOP_RETRY_LIMIT)
2301 "Timers linear scans are not over [Connection %02x Tasks %02x]\n",
2302 (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
2303 (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
2306 void qed_hw_timers_stop_all(struct qed_dev *cdev)
2310 for_each_hwfn(cdev, j) {
2311 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
2312 struct qed_ptt *p_ptt = p_hwfn->p_main_ptt;
2314 qed_hw_timers_stop(cdev, p_hwfn, p_ptt);
2318 int qed_hw_stop(struct qed_dev *cdev)
2320 struct qed_hwfn *p_hwfn;
2321 struct qed_ptt *p_ptt;
2325 for_each_hwfn(cdev, j) {
2326 p_hwfn = &cdev->hwfns[j];
2327 p_ptt = p_hwfn->p_main_ptt;
2329 DP_VERBOSE(p_hwfn, NETIF_MSG_IFDOWN, "Stopping hw/fw\n");
2332 qed_vf_pf_int_cleanup(p_hwfn);
2333 rc = qed_vf_pf_reset(p_hwfn);
2336 "qed_vf_pf_reset failed. rc = %d.\n",
2343 /* mark the hw as uninitialized... */
2344 p_hwfn->hw_init_done = false;
2346 /* Send unload command to MCP */
2347 if (!cdev->recov_in_prog) {
2348 rc = qed_mcp_unload_req(p_hwfn, p_ptt);
2351 "Failed sending a UNLOAD_REQ command. rc = %d.\n",
2357 qed_slowpath_irq_sync(p_hwfn);
2359 /* After this point no MFW attentions are expected, e.g. prevent
2360 * race between pf stop and dcbx pf update.
2362 rc = qed_sp_pf_stop(p_hwfn);
2365 "Failed to close PF against FW [rc = %d]. Continue to stop HW to prevent illegal host access by the device.\n",
2370 qed_wr(p_hwfn, p_ptt,
2371 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
2373 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2374 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
2375 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
2376 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2377 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
2379 qed_hw_timers_stop(cdev, p_hwfn, p_ptt);
2381 /* Disable Attention Generation */
2382 qed_int_igu_disable_int(p_hwfn, p_ptt);
2384 qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
2385 qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
2387 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
2389 /* Need to wait 1ms to guarantee SBs are cleared */
2390 usleep_range(1000, 2000);
2392 /* Disable PF in HW blocks */
2393 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DB_ENABLE, 0);
2394 qed_wr(p_hwfn, p_ptt, QM_REG_PF_EN, 0);
2396 if (!cdev->recov_in_prog) {
2397 rc = qed_mcp_unload_done(p_hwfn, p_ptt);
2400 "Failed sending a UNLOAD_DONE command. rc = %d.\n",
2407 if (IS_PF(cdev) && !cdev->recov_in_prog) {
2408 p_hwfn = QED_LEADING_HWFN(cdev);
2409 p_ptt = QED_LEADING_HWFN(cdev)->p_main_ptt;
2411 /* Clear the PF's internal FID_enable in the PXP.
2412 * In CMT this should only be done for first hw-function, and
2413 * only after all transactions have stopped for all active
2416 rc = qed_pglueb_set_pfid_enable(p_hwfn, p_ptt, false);
2419 "qed_pglueb_set_pfid_enable() failed. rc = %d.\n",
2428 int qed_hw_stop_fastpath(struct qed_dev *cdev)
2432 for_each_hwfn(cdev, j) {
2433 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
2434 struct qed_ptt *p_ptt;
2437 qed_vf_pf_int_cleanup(p_hwfn);
2440 p_ptt = qed_ptt_acquire(p_hwfn);
2445 NETIF_MSG_IFDOWN, "Shutting down the fastpath\n");
2447 qed_wr(p_hwfn, p_ptt,
2448 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
2450 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2451 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
2452 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
2453 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2454 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
2456 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
2458 /* Need to wait 1ms to guarantee SBs are cleared */
2459 usleep_range(1000, 2000);
2460 qed_ptt_release(p_hwfn, p_ptt);
2466 int qed_hw_start_fastpath(struct qed_hwfn *p_hwfn)
2468 struct qed_ptt *p_ptt;
2470 if (IS_VF(p_hwfn->cdev))
2473 p_ptt = qed_ptt_acquire(p_hwfn);
2477 if (p_hwfn->p_rdma_info &&
2478 p_hwfn->p_rdma_info->active && p_hwfn->b_rdma_enabled_in_prs)
2479 qed_wr(p_hwfn, p_ptt, p_hwfn->rdma_prs_search_reg, 0x1);
2481 /* Re-open incoming traffic */
2482 qed_wr(p_hwfn, p_ptt, NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
2483 qed_ptt_release(p_hwfn, p_ptt);
2488 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
2489 static void qed_hw_hwfn_free(struct qed_hwfn *p_hwfn)
2491 qed_ptt_pool_free(p_hwfn);
2492 kfree(p_hwfn->hw_info.p_igu_info);
2493 p_hwfn->hw_info.p_igu_info = NULL;
2496 /* Setup bar access */
2497 static void qed_hw_hwfn_prepare(struct qed_hwfn *p_hwfn)
2499 /* clear indirect access */
2500 if (QED_IS_AH(p_hwfn->cdev)) {
2501 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2502 PGLUE_B_REG_PGL_ADDR_E8_F0_K2, 0);
2503 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2504 PGLUE_B_REG_PGL_ADDR_EC_F0_K2, 0);
2505 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2506 PGLUE_B_REG_PGL_ADDR_F0_F0_K2, 0);
2507 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2508 PGLUE_B_REG_PGL_ADDR_F4_F0_K2, 0);
2510 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2511 PGLUE_B_REG_PGL_ADDR_88_F0_BB, 0);
2512 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2513 PGLUE_B_REG_PGL_ADDR_8C_F0_BB, 0);
2514 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2515 PGLUE_B_REG_PGL_ADDR_90_F0_BB, 0);
2516 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2517 PGLUE_B_REG_PGL_ADDR_94_F0_BB, 0);
2520 /* Clean previous pglue_b errors if such exist */
2521 qed_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt);
2523 /* enable internal target-read */
2524 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2525 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
2528 static void get_function_id(struct qed_hwfn *p_hwfn)
2531 p_hwfn->hw_info.opaque_fid = (u16) REG_RD(p_hwfn,
2532 PXP_PF_ME_OPAQUE_ADDR);
2534 p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
2536 p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
2537 p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2538 PXP_CONCRETE_FID_PFID);
2539 p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2540 PXP_CONCRETE_FID_PORT);
2542 DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE,
2543 "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
2544 p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
2547 static void qed_hw_set_feat(struct qed_hwfn *p_hwfn)
2549 u32 *feat_num = p_hwfn->hw_info.feat_num;
2550 struct qed_sb_cnt_info sb_cnt;
2553 memset(&sb_cnt, 0, sizeof(sb_cnt));
2554 qed_int_get_num_sbs(p_hwfn, &sb_cnt);
2556 if (IS_ENABLED(CONFIG_QED_RDMA) &&
2557 QED_IS_RDMA_PERSONALITY(p_hwfn)) {
2558 /* Roce CNQ each requires: 1 status block + 1 CNQ. We divide
2559 * the status blocks equally between L2 / RoCE but with
2560 * consideration as to how many l2 queues / cnqs we have.
2562 feat_num[QED_RDMA_CNQ] =
2563 min_t(u32, sb_cnt.cnt / 2,
2564 RESC_NUM(p_hwfn, QED_RDMA_CNQ_RAM));
2566 non_l2_sbs = feat_num[QED_RDMA_CNQ];
2568 if (QED_IS_L2_PERSONALITY(p_hwfn)) {
2569 /* Start by allocating VF queues, then PF's */
2570 feat_num[QED_VF_L2_QUE] = min_t(u32,
2571 RESC_NUM(p_hwfn, QED_L2_QUEUE),
2573 feat_num[QED_PF_L2_QUE] = min_t(u32,
2574 sb_cnt.cnt - non_l2_sbs,
2581 if (QED_IS_FCOE_PERSONALITY(p_hwfn))
2582 feat_num[QED_FCOE_CQ] = min_t(u32, sb_cnt.cnt,
2586 if (QED_IS_ISCSI_PERSONALITY(p_hwfn))
2587 feat_num[QED_ISCSI_CQ] = min_t(u32, sb_cnt.cnt,
2592 "#PF_L2_QUEUES=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d FCOE_CQ=%d ISCSI_CQ=%d #SBS=%d\n",
2593 (int)FEAT_NUM(p_hwfn, QED_PF_L2_QUE),
2594 (int)FEAT_NUM(p_hwfn, QED_VF_L2_QUE),
2595 (int)FEAT_NUM(p_hwfn, QED_RDMA_CNQ),
2596 (int)FEAT_NUM(p_hwfn, QED_FCOE_CQ),
2597 (int)FEAT_NUM(p_hwfn, QED_ISCSI_CQ),
2601 const char *qed_hw_get_resc_name(enum qed_resources res_id)
2618 case QED_RDMA_CNQ_RAM:
2619 return "RDMA_CNQ_RAM";
2626 case QED_RDMA_STATS_QUEUE:
2627 return "RDMA_STATS_QUEUE";
2633 return "UNKNOWN_RESOURCE";
2638 __qed_hw_set_soft_resc_size(struct qed_hwfn *p_hwfn,
2639 struct qed_ptt *p_ptt,
2640 enum qed_resources res_id,
2641 u32 resc_max_val, u32 *p_mcp_resp)
2645 rc = qed_mcp_set_resc_max_val(p_hwfn, p_ptt, res_id,
2646 resc_max_val, p_mcp_resp);
2649 "MFW response failure for a max value setting of resource %d [%s]\n",
2650 res_id, qed_hw_get_resc_name(res_id));
2654 if (*p_mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK)
2656 "Failed to set the max value of resource %d [%s]. mcp_resp = 0x%08x.\n",
2657 res_id, qed_hw_get_resc_name(res_id), *p_mcp_resp);
2663 qed_hw_set_soft_resc_size(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2665 bool b_ah = QED_IS_AH(p_hwfn->cdev);
2666 u32 resc_max_val, mcp_resp;
2670 for (res_id = 0; res_id < QED_MAX_RESC; res_id++) {
2673 resc_max_val = MAX_NUM_LL2_RX_QUEUES;
2675 case QED_RDMA_CNQ_RAM:
2676 /* No need for a case for QED_CMDQS_CQS since
2677 * CNQ/CMDQS are the same resource.
2679 resc_max_val = NUM_OF_GLOBAL_QUEUES;
2681 case QED_RDMA_STATS_QUEUE:
2682 resc_max_val = b_ah ? RDMA_NUM_STATISTIC_COUNTERS_K2
2683 : RDMA_NUM_STATISTIC_COUNTERS_BB;
2686 resc_max_val = BDQ_NUM_RESOURCES;
2692 rc = __qed_hw_set_soft_resc_size(p_hwfn, p_ptt, res_id,
2693 resc_max_val, &mcp_resp);
2697 /* There's no point to continue to the next resource if the
2698 * command is not supported by the MFW.
2699 * We do continue if the command is supported but the resource
2700 * is unknown to the MFW. Such a resource will be later
2701 * configured with the default allocation values.
2703 if (mcp_resp == FW_MSG_CODE_UNSUPPORTED)
2711 int qed_hw_get_dflt_resc(struct qed_hwfn *p_hwfn,
2712 enum qed_resources res_id,
2713 u32 *p_resc_num, u32 *p_resc_start)
2715 u8 num_funcs = p_hwfn->num_funcs_on_engine;
2716 bool b_ah = QED_IS_AH(p_hwfn->cdev);
2720 *p_resc_num = (b_ah ? MAX_NUM_L2_QUEUES_K2 :
2721 MAX_NUM_L2_QUEUES_BB) / num_funcs;
2724 *p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
2725 MAX_NUM_VPORTS_BB) / num_funcs;
2728 *p_resc_num = (b_ah ? ETH_RSS_ENGINE_NUM_K2 :
2729 ETH_RSS_ENGINE_NUM_BB) / num_funcs;
2732 *p_resc_num = (b_ah ? MAX_QM_TX_QUEUES_K2 :
2733 MAX_QM_TX_QUEUES_BB) / num_funcs;
2734 *p_resc_num &= ~0x7; /* The granularity of the PQs is 8 */
2737 *p_resc_num = MAX_QM_GLOBAL_RLS / num_funcs;
2741 /* Each VFC resource can accommodate both a MAC and a VLAN */
2742 *p_resc_num = ETH_NUM_MAC_FILTERS / num_funcs;
2745 *p_resc_num = (b_ah ? PXP_NUM_ILT_RECORDS_K2 :
2746 PXP_NUM_ILT_RECORDS_BB) / num_funcs;
2749 *p_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs;
2751 case QED_RDMA_CNQ_RAM:
2753 /* CNQ/CMDQS are the same resource */
2754 *p_resc_num = NUM_OF_GLOBAL_QUEUES / num_funcs;
2756 case QED_RDMA_STATS_QUEUE:
2757 *p_resc_num = (b_ah ? RDMA_NUM_STATISTIC_COUNTERS_K2 :
2758 RDMA_NUM_STATISTIC_COUNTERS_BB) / num_funcs;
2761 if (p_hwfn->hw_info.personality != QED_PCI_ISCSI &&
2762 p_hwfn->hw_info.personality != QED_PCI_FCOE)
2768 /* Since we want its value to reflect whether MFW supports
2769 * the new scheme, have a default of 0.
2781 else if (p_hwfn->cdev->num_ports_in_engine == 4)
2782 *p_resc_start = p_hwfn->port_id;
2783 else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI)
2784 *p_resc_start = p_hwfn->port_id;
2785 else if (p_hwfn->hw_info.personality == QED_PCI_FCOE)
2786 *p_resc_start = p_hwfn->port_id + 2;
2789 *p_resc_start = *p_resc_num * p_hwfn->enabled_func_idx;
2796 static int __qed_hw_set_resc_info(struct qed_hwfn *p_hwfn,
2797 enum qed_resources res_id)
2799 u32 dflt_resc_num = 0, dflt_resc_start = 0;
2800 u32 mcp_resp, *p_resc_num, *p_resc_start;
2803 p_resc_num = &RESC_NUM(p_hwfn, res_id);
2804 p_resc_start = &RESC_START(p_hwfn, res_id);
2806 rc = qed_hw_get_dflt_resc(p_hwfn, res_id, &dflt_resc_num,
2810 "Failed to get default amount for resource %d [%s]\n",
2811 res_id, qed_hw_get_resc_name(res_id));
2815 rc = qed_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, res_id,
2816 &mcp_resp, p_resc_num, p_resc_start);
2819 "MFW response failure for an allocation request for resource %d [%s]\n",
2820 res_id, qed_hw_get_resc_name(res_id));
2824 /* Default driver values are applied in the following cases:
2825 * - The resource allocation MB command is not supported by the MFW
2826 * - There is an internal error in the MFW while processing the request
2827 * - The resource ID is unknown to the MFW
2829 if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK) {
2831 "Failed to receive allocation info for resource %d [%s]. mcp_resp = 0x%x. Applying default values [%d,%d].\n",
2833 qed_hw_get_resc_name(res_id),
2834 mcp_resp, dflt_resc_num, dflt_resc_start);
2835 *p_resc_num = dflt_resc_num;
2836 *p_resc_start = dflt_resc_start;
2841 /* PQs have to divide by 8 [that's the HW granularity].
2842 * Reduce number so it would fit.
2844 if ((res_id == QED_PQ) && ((*p_resc_num % 8) || (*p_resc_start % 8))) {
2846 "PQs need to align by 8; Number %08x --> %08x, Start %08x --> %08x\n",
2848 (*p_resc_num) & ~0x7,
2849 *p_resc_start, (*p_resc_start) & ~0x7);
2850 *p_resc_num &= ~0x7;
2851 *p_resc_start &= ~0x7;
2857 static int qed_hw_set_resc_info(struct qed_hwfn *p_hwfn)
2862 for (res_id = 0; res_id < QED_MAX_RESC; res_id++) {
2863 rc = __qed_hw_set_resc_info(p_hwfn, res_id);
2871 static int qed_hw_get_resc(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2873 struct qed_resc_unlock_params resc_unlock_params;
2874 struct qed_resc_lock_params resc_lock_params;
2875 bool b_ah = QED_IS_AH(p_hwfn->cdev);
2879 /* Setting the max values of the soft resources and the following
2880 * resources allocation queries should be atomic. Since several PFs can
2881 * run in parallel - a resource lock is needed.
2882 * If either the resource lock or resource set value commands are not
2883 * supported - skip the the max values setting, release the lock if
2884 * needed, and proceed to the queries. Other failures, including a
2885 * failure to acquire the lock, will cause this function to fail.
2887 qed_mcp_resc_lock_default_init(&resc_lock_params, &resc_unlock_params,
2888 QED_RESC_LOCK_RESC_ALLOC, false);
2890 rc = qed_mcp_resc_lock(p_hwfn, p_ptt, &resc_lock_params);
2891 if (rc && rc != -EINVAL) {
2893 } else if (rc == -EINVAL) {
2895 "Skip the max values setting of the soft resources since the resource lock is not supported by the MFW\n");
2896 } else if (!rc && !resc_lock_params.b_granted) {
2898 "Failed to acquire the resource lock for the resource allocation commands\n");
2901 rc = qed_hw_set_soft_resc_size(p_hwfn, p_ptt);
2902 if (rc && rc != -EINVAL) {
2904 "Failed to set the max values of the soft resources\n");
2905 goto unlock_and_exit;
2906 } else if (rc == -EINVAL) {
2908 "Skip the max values setting of the soft resources since it is not supported by the MFW\n");
2909 rc = qed_mcp_resc_unlock(p_hwfn, p_ptt,
2910 &resc_unlock_params);
2913 "Failed to release the resource lock for the resource allocation commands\n");
2917 rc = qed_hw_set_resc_info(p_hwfn);
2919 goto unlock_and_exit;
2921 if (resc_lock_params.b_granted && !resc_unlock_params.b_released) {
2922 rc = qed_mcp_resc_unlock(p_hwfn, p_ptt, &resc_unlock_params);
2925 "Failed to release the resource lock for the resource allocation commands\n");
2928 /* Sanity for ILT */
2929 if ((b_ah && (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_K2)) ||
2930 (!b_ah && (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_BB))) {
2931 DP_NOTICE(p_hwfn, "Can't assign ILT pages [%08x,...,%08x]\n",
2932 RESC_START(p_hwfn, QED_ILT),
2933 RESC_END(p_hwfn, QED_ILT) - 1);
2937 /* This will also learn the number of SBs from MFW */
2938 if (qed_int_igu_reset_cam(p_hwfn, p_ptt))
2941 qed_hw_set_feat(p_hwfn);
2943 for (res_id = 0; res_id < QED_MAX_RESC; res_id++)
2944 DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE, "%s = %d start = %d\n",
2945 qed_hw_get_resc_name(res_id),
2946 RESC_NUM(p_hwfn, res_id),
2947 RESC_START(p_hwfn, res_id));
2952 if (resc_lock_params.b_granted && !resc_unlock_params.b_released)
2953 qed_mcp_resc_unlock(p_hwfn, p_ptt, &resc_unlock_params);
2957 static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2959 u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
2960 u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg;
2961 struct qed_mcp_link_capabilities *p_caps;
2962 struct qed_mcp_link_params *link;
2964 /* Read global nvm_cfg address */
2965 nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
2967 /* Verify MCP has initialized it */
2968 if (!nvm_cfg_addr) {
2969 DP_NOTICE(p_hwfn, "Shared memory not initialized\n");
2973 /* Read nvm_cfg1 (Notice this is just offset, and not offsize (TBD) */
2974 nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
2976 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2977 offsetof(struct nvm_cfg1, glob) +
2978 offsetof(struct nvm_cfg1_glob, core_cfg);
2980 core_cfg = qed_rd(p_hwfn, p_ptt, addr);
2982 switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
2983 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
2984 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
2985 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X40G;
2987 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
2988 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X50G;
2990 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
2991 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X100G;
2993 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
2994 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_F;
2996 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
2997 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_E;
2999 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
3000 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X20G;
3002 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
3003 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X40G;
3005 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
3006 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X25G;
3008 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G:
3009 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X10G;
3011 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
3012 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X25G;
3014 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G:
3015 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X25G;
3018 DP_NOTICE(p_hwfn, "Unknown port mode in 0x%08x\n", core_cfg);
3022 /* Read default link configuration */
3023 link = &p_hwfn->mcp_info->link_input;
3024 p_caps = &p_hwfn->mcp_info->link_capabilities;
3025 port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3026 offsetof(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
3027 link_temp = qed_rd(p_hwfn, p_ptt,
3029 offsetof(struct nvm_cfg1_port, speed_cap_mask));
3030 link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
3031 link->speed.advertised_speeds = link_temp;
3033 link_temp = link->speed.advertised_speeds;
3034 p_hwfn->mcp_info->link_capabilities.speed_capabilities = link_temp;
3036 link_temp = qed_rd(p_hwfn, p_ptt,
3038 offsetof(struct nvm_cfg1_port, link_settings));
3039 switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
3040 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
3041 case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
3042 link->speed.autoneg = true;
3044 case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
3045 link->speed.forced_speed = 1000;
3047 case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
3048 link->speed.forced_speed = 10000;
3050 case NVM_CFG1_PORT_DRV_LINK_SPEED_20G:
3051 link->speed.forced_speed = 20000;
3053 case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
3054 link->speed.forced_speed = 25000;
3056 case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
3057 link->speed.forced_speed = 40000;
3059 case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
3060 link->speed.forced_speed = 50000;
3062 case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
3063 link->speed.forced_speed = 100000;
3066 DP_NOTICE(p_hwfn, "Unknown Speed in 0x%08x\n", link_temp);
3069 p_hwfn->mcp_info->link_capabilities.default_speed_autoneg =
3070 link->speed.autoneg;
3072 link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
3073 link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
3074 link->pause.autoneg = !!(link_temp &
3075 NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
3076 link->pause.forced_rx = !!(link_temp &
3077 NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
3078 link->pause.forced_tx = !!(link_temp &
3079 NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
3080 link->loopback_mode = 0;
3082 if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE) {
3083 link_temp = qed_rd(p_hwfn, p_ptt, port_cfg_addr +
3084 offsetof(struct nvm_cfg1_port, ext_phy));
3085 link_temp &= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK;
3086 link_temp >>= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET;
3087 p_caps->default_eee = QED_MCP_EEE_ENABLED;
3088 link->eee.enable = true;
3089 switch (link_temp) {
3090 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED:
3091 p_caps->default_eee = QED_MCP_EEE_DISABLED;
3092 link->eee.enable = false;
3094 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED:
3095 p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_BALANCED_TIME;
3097 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE:
3098 p_caps->eee_lpi_timer =
3099 EEE_TX_TIMER_USEC_AGGRESSIVE_TIME;
3101 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY:
3102 p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_LATENCY_TIME;
3106 link->eee.tx_lpi_timer = p_caps->eee_lpi_timer;
3107 link->eee.tx_lpi_enable = link->eee.enable;
3108 link->eee.adv_caps = QED_EEE_1G_ADV | QED_EEE_10G_ADV;
3110 p_caps->default_eee = QED_MCP_EEE_UNSUPPORTED;
3115 "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x EEE: %02x [%08x usec]\n",
3116 link->speed.forced_speed,
3117 link->speed.advertised_speeds,
3118 link->speed.autoneg,
3119 link->pause.autoneg,
3120 p_caps->default_eee, p_caps->eee_lpi_timer);
3122 if (IS_LEAD_HWFN(p_hwfn)) {
3123 struct qed_dev *cdev = p_hwfn->cdev;
3125 /* Read Multi-function information from shmem */
3126 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3127 offsetof(struct nvm_cfg1, glob) +
3128 offsetof(struct nvm_cfg1_glob, generic_cont0);
3130 generic_cont0 = qed_rd(p_hwfn, p_ptt, addr);
3132 mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
3133 NVM_CFG1_GLOB_MF_MODE_OFFSET;
3136 case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
3137 cdev->mf_bits = BIT(QED_MF_OVLAN_CLSS);
3139 case NVM_CFG1_GLOB_MF_MODE_UFP:
3140 cdev->mf_bits = BIT(QED_MF_OVLAN_CLSS) |
3141 BIT(QED_MF_LLH_PROTO_CLSS) |
3142 BIT(QED_MF_UFP_SPECIFIC) |
3143 BIT(QED_MF_8021Q_TAGGING);
3145 case NVM_CFG1_GLOB_MF_MODE_BD:
3146 cdev->mf_bits = BIT(QED_MF_OVLAN_CLSS) |
3147 BIT(QED_MF_LLH_PROTO_CLSS) |
3148 BIT(QED_MF_8021AD_TAGGING);
3150 case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
3151 cdev->mf_bits = BIT(QED_MF_LLH_MAC_CLSS) |
3152 BIT(QED_MF_LLH_PROTO_CLSS) |
3153 BIT(QED_MF_LL2_NON_UNICAST) |
3154 BIT(QED_MF_INTER_PF_SWITCH);
3156 case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
3157 cdev->mf_bits = BIT(QED_MF_LLH_MAC_CLSS) |
3158 BIT(QED_MF_LLH_PROTO_CLSS) |
3159 BIT(QED_MF_LL2_NON_UNICAST);
3160 if (QED_IS_BB(p_hwfn->cdev))
3161 cdev->mf_bits |= BIT(QED_MF_NEED_DEF_PF);
3165 DP_INFO(p_hwfn, "Multi function mode is 0x%lx\n",
3169 DP_INFO(p_hwfn, "Multi function mode is 0x%lx\n",
3170 p_hwfn->cdev->mf_bits);
3172 /* Read device capabilities information from shmem */
3173 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3174 offsetof(struct nvm_cfg1, glob) +
3175 offsetof(struct nvm_cfg1_glob, device_capabilities);
3177 device_capabilities = qed_rd(p_hwfn, p_ptt, addr);
3178 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
3179 __set_bit(QED_DEV_CAP_ETH,
3180 &p_hwfn->hw_info.device_capabilities);
3181 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE)
3182 __set_bit(QED_DEV_CAP_FCOE,
3183 &p_hwfn->hw_info.device_capabilities);
3184 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
3185 __set_bit(QED_DEV_CAP_ISCSI,
3186 &p_hwfn->hw_info.device_capabilities);
3187 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
3188 __set_bit(QED_DEV_CAP_ROCE,
3189 &p_hwfn->hw_info.device_capabilities);
3191 return qed_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
3194 static void qed_get_num_funcs(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
3196 u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
3197 u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
3198 struct qed_dev *cdev = p_hwfn->cdev;
3200 num_funcs = QED_IS_AH(cdev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB;
3202 /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
3203 * in the other bits are selected.
3204 * Bits 1-15 are for functions 1-15, respectively, and their value is
3205 * '0' only for enabled functions (function 0 always exists and
3207 * In case of CMT, only the "even" functions are enabled, and thus the
3208 * number of functions for both hwfns is learnt from the same bits.
3210 reg_function_hide = qed_rd(p_hwfn, p_ptt, MISCS_REG_FUNCTION_HIDE);
3212 if (reg_function_hide & 0x1) {
3213 if (QED_IS_BB(cdev)) {
3214 if (QED_PATH_ID(p_hwfn) && cdev->num_hwfns == 1) {
3226 /* Get the number of the enabled functions on the engine */
3227 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
3234 /* Get the PF index within the enabled functions */
3235 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
3236 tmp = reg_function_hide & eng_mask & low_pfs_mask;
3244 p_hwfn->num_funcs_on_engine = num_funcs;
3245 p_hwfn->enabled_func_idx = enabled_func_idx;
3249 "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n",
3252 p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);
3255 static void qed_hw_info_port_num(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
3257 u32 addr, global_offsize, global_addr, port_mode;
3258 struct qed_dev *cdev = p_hwfn->cdev;
3260 /* In CMT there is always only one port */
3261 if (cdev->num_hwfns > 1) {
3262 cdev->num_ports_in_engine = 1;
3263 cdev->num_ports = 1;
3267 /* Determine the number of ports per engine */
3268 port_mode = qed_rd(p_hwfn, p_ptt, MISC_REG_PORT_MODE);
3269 switch (port_mode) {
3271 cdev->num_ports_in_engine = 1;
3274 cdev->num_ports_in_engine = 2;
3277 cdev->num_ports_in_engine = 4;
3280 DP_NOTICE(p_hwfn, "Unknown port mode 0x%08x\n", port_mode);
3281 cdev->num_ports_in_engine = 1; /* Default to something */
3285 /* Get the total number of ports of the device */
3286 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
3288 global_offsize = qed_rd(p_hwfn, p_ptt, addr);
3289 global_addr = SECTION_ADDR(global_offsize, 0);
3290 addr = global_addr + offsetof(struct public_global, max_ports);
3291 cdev->num_ports = (u8)qed_rd(p_hwfn, p_ptt, addr);
3294 static void qed_get_eee_caps(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
3296 struct qed_mcp_link_capabilities *p_caps;
3299 p_caps = &p_hwfn->mcp_info->link_capabilities;
3300 if (p_caps->default_eee == QED_MCP_EEE_UNSUPPORTED)
3303 p_caps->eee_speed_caps = 0;
3304 eee_status = qed_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
3305 offsetof(struct public_port, eee_status));
3306 eee_status = (eee_status & EEE_SUPPORTED_SPEED_MASK) >>
3307 EEE_SUPPORTED_SPEED_OFFSET;
3309 if (eee_status & EEE_1G_SUPPORTED)
3310 p_caps->eee_speed_caps |= QED_EEE_1G_ADV;
3311 if (eee_status & EEE_10G_ADV)
3312 p_caps->eee_speed_caps |= QED_EEE_10G_ADV;
3316 qed_get_hw_info(struct qed_hwfn *p_hwfn,
3317 struct qed_ptt *p_ptt,
3318 enum qed_pci_personality personality)
3322 /* Since all information is common, only first hwfns should do this */
3323 if (IS_LEAD_HWFN(p_hwfn)) {
3324 rc = qed_iov_hw_info(p_hwfn);
3329 if (IS_LEAD_HWFN(p_hwfn))
3330 qed_hw_info_port_num(p_hwfn, p_ptt);
3332 qed_mcp_get_capabilities(p_hwfn, p_ptt);
3334 qed_hw_get_nvm_info(p_hwfn, p_ptt);
3336 rc = qed_int_igu_read_cam(p_hwfn, p_ptt);
3340 if (qed_mcp_is_init(p_hwfn))
3341 ether_addr_copy(p_hwfn->hw_info.hw_mac_addr,
3342 p_hwfn->mcp_info->func_info.mac);
3344 eth_random_addr(p_hwfn->hw_info.hw_mac_addr);
3346 if (qed_mcp_is_init(p_hwfn)) {
3347 if (p_hwfn->mcp_info->func_info.ovlan != QED_MCP_VLAN_UNSET)
3348 p_hwfn->hw_info.ovlan =
3349 p_hwfn->mcp_info->func_info.ovlan;
3351 qed_mcp_cmd_port_init(p_hwfn, p_ptt);
3353 qed_get_eee_caps(p_hwfn, p_ptt);
3355 qed_mcp_read_ufp_config(p_hwfn, p_ptt);
3358 if (qed_mcp_is_init(p_hwfn)) {
3359 enum qed_pci_personality protocol;
3361 protocol = p_hwfn->mcp_info->func_info.protocol;
3362 p_hwfn->hw_info.personality = protocol;
3365 if (QED_IS_ROCE_PERSONALITY(p_hwfn))
3366 p_hwfn->hw_info.multi_tc_roce_en = 1;
3368 p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2;
3369 p_hwfn->hw_info.num_active_tc = 1;
3371 qed_get_num_funcs(p_hwfn, p_ptt);
3373 if (qed_mcp_is_init(p_hwfn))
3374 p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu;
3376 return qed_hw_get_resc(p_hwfn, p_ptt);
3379 static int qed_get_dev_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
3381 struct qed_dev *cdev = p_hwfn->cdev;
3385 /* Read Vendor Id / Device Id */
3386 pci_read_config_word(cdev->pdev, PCI_VENDOR_ID, &cdev->vendor_id);
3387 pci_read_config_word(cdev->pdev, PCI_DEVICE_ID, &cdev->device_id);
3389 /* Determine type */
3390 device_id_mask = cdev->device_id & QED_DEV_ID_MASK;
3391 switch (device_id_mask) {
3392 case QED_DEV_ID_MASK_BB:
3393 cdev->type = QED_DEV_TYPE_BB;
3395 case QED_DEV_ID_MASK_AH:
3396 cdev->type = QED_DEV_TYPE_AH;
3399 DP_NOTICE(p_hwfn, "Unknown device id 0x%x\n", cdev->device_id);
3403 cdev->chip_num = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_NUM);
3404 cdev->chip_rev = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_REV);
3406 MASK_FIELD(CHIP_REV, cdev->chip_rev);
3408 /* Learn number of HW-functions */
3409 tmp = qed_rd(p_hwfn, p_ptt, MISCS_REG_CMT_ENABLED_FOR_PAIR);
3411 if (tmp & (1 << p_hwfn->rel_pf_id)) {
3412 DP_NOTICE(cdev->hwfns, "device in CMT mode\n");
3413 cdev->num_hwfns = 2;
3415 cdev->num_hwfns = 1;
3418 cdev->chip_bond_id = qed_rd(p_hwfn, p_ptt,
3419 MISCS_REG_CHIP_TEST_REG) >> 4;
3420 MASK_FIELD(CHIP_BOND_ID, cdev->chip_bond_id);
3421 cdev->chip_metal = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_METAL);
3422 MASK_FIELD(CHIP_METAL, cdev->chip_metal);
3424 DP_INFO(cdev->hwfns,
3425 "Chip details - %s %c%d, Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n",
3426 QED_IS_BB(cdev) ? "BB" : "AH",
3427 'A' + cdev->chip_rev,
3428 (int)cdev->chip_metal,
3429 cdev->chip_num, cdev->chip_rev,
3430 cdev->chip_bond_id, cdev->chip_metal);
3435 static void qed_nvm_info_free(struct qed_hwfn *p_hwfn)
3437 kfree(p_hwfn->nvm_info.image_att);
3438 p_hwfn->nvm_info.image_att = NULL;
3441 static int qed_hw_prepare_single(struct qed_hwfn *p_hwfn,
3442 void __iomem *p_regview,
3443 void __iomem *p_doorbells,
3444 enum qed_pci_personality personality)
3446 struct qed_dev *cdev = p_hwfn->cdev;
3449 /* Split PCI bars evenly between hwfns */
3450 p_hwfn->regview = p_regview;
3451 p_hwfn->doorbells = p_doorbells;
3453 if (IS_VF(p_hwfn->cdev))
3454 return qed_vf_hw_prepare(p_hwfn);
3456 /* Validate that chip access is feasible */
3457 if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
3459 "Reading the ME register returns all Fs; Preventing further chip access\n");
3463 get_function_id(p_hwfn);
3465 /* Allocate PTT pool */
3466 rc = qed_ptt_pool_alloc(p_hwfn);
3470 /* Allocate the main PTT */
3471 p_hwfn->p_main_ptt = qed_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
3473 /* First hwfn learns basic information, e.g., number of hwfns */
3474 if (!p_hwfn->my_id) {
3475 rc = qed_get_dev_info(p_hwfn, p_hwfn->p_main_ptt);
3480 qed_hw_hwfn_prepare(p_hwfn);
3482 /* Initialize MCP structure */
3483 rc = qed_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
3485 DP_NOTICE(p_hwfn, "Failed initializing mcp command\n");
3489 /* Read the device configuration information from the HW and SHMEM */
3490 rc = qed_get_hw_info(p_hwfn, p_hwfn->p_main_ptt, personality);
3492 DP_NOTICE(p_hwfn, "Failed to get HW information\n");
3496 /* Sending a mailbox to the MFW should be done after qed_get_hw_info()
3497 * is called as it sets the ports number in an engine.
3499 if (IS_LEAD_HWFN(p_hwfn) && !cdev->recov_in_prog) {
3500 rc = qed_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt);
3502 DP_NOTICE(p_hwfn, "Failed to initiate PF FLR\n");
3505 /* NVRAM info initialization and population */
3506 if (IS_LEAD_HWFN(p_hwfn)) {
3507 rc = qed_mcp_nvm_info_populate(p_hwfn);
3510 "Failed to populate nvm info shadow\n");
3515 /* Allocate the init RT array and initialize the init-ops engine */
3516 rc = qed_init_alloc(p_hwfn);
3522 if (IS_LEAD_HWFN(p_hwfn))
3523 qed_nvm_info_free(p_hwfn);
3525 if (IS_LEAD_HWFN(p_hwfn))
3526 qed_iov_free_hw_info(p_hwfn->cdev);
3527 qed_mcp_free(p_hwfn);
3529 qed_hw_hwfn_free(p_hwfn);
3534 int qed_hw_prepare(struct qed_dev *cdev,
3537 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
3540 /* Store the precompiled init data ptrs */
3542 qed_init_iro_array(cdev);
3544 /* Initialize the first hwfn - will learn number of hwfns */
3545 rc = qed_hw_prepare_single(p_hwfn,
3547 cdev->doorbells, personality);
3551 personality = p_hwfn->hw_info.personality;
3553 /* Initialize the rest of the hwfns */
3554 if (cdev->num_hwfns > 1) {
3555 void __iomem *p_regview, *p_doorbell;
3558 /* adjust bar offset for second engine */
3559 addr = cdev->regview +
3560 qed_hw_bar_size(p_hwfn, p_hwfn->p_main_ptt,
3564 addr = cdev->doorbells +
3565 qed_hw_bar_size(p_hwfn, p_hwfn->p_main_ptt,
3569 /* prepare second hw function */
3570 rc = qed_hw_prepare_single(&cdev->hwfns[1], p_regview,
3571 p_doorbell, personality);
3573 /* in case of error, need to free the previously
3574 * initiliazed hwfn 0.
3578 qed_init_free(p_hwfn);
3579 qed_nvm_info_free(p_hwfn);
3580 qed_mcp_free(p_hwfn);
3581 qed_hw_hwfn_free(p_hwfn);
3589 void qed_hw_remove(struct qed_dev *cdev)
3591 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
3595 qed_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt,
3596 QED_OV_DRIVER_STATE_NOT_LOADED);
3598 for_each_hwfn(cdev, i) {
3599 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
3602 qed_vf_pf_release(p_hwfn);
3606 qed_init_free(p_hwfn);
3607 qed_hw_hwfn_free(p_hwfn);
3608 qed_mcp_free(p_hwfn);
3611 qed_iov_free_hw_info(cdev);
3613 qed_nvm_info_free(p_hwfn);
3616 static void qed_chain_free_next_ptr(struct qed_dev *cdev,
3617 struct qed_chain *p_chain)
3619 void *p_virt = p_chain->p_virt_addr, *p_virt_next = NULL;
3620 dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
3621 struct qed_chain_next *p_next;
3627 size = p_chain->elem_size * p_chain->usable_per_page;
3629 for (i = 0; i < p_chain->page_cnt; i++) {
3633 p_next = (struct qed_chain_next *)((u8 *)p_virt + size);
3634 p_virt_next = p_next->next_virt;
3635 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
3637 dma_free_coherent(&cdev->pdev->dev,
3638 QED_CHAIN_PAGE_SIZE, p_virt, p_phys);
3640 p_virt = p_virt_next;
3641 p_phys = p_phys_next;
3645 static void qed_chain_free_single(struct qed_dev *cdev,
3646 struct qed_chain *p_chain)
3648 if (!p_chain->p_virt_addr)
3651 dma_free_coherent(&cdev->pdev->dev,
3652 QED_CHAIN_PAGE_SIZE,
3653 p_chain->p_virt_addr, p_chain->p_phys_addr);
3656 static void qed_chain_free_pbl(struct qed_dev *cdev, struct qed_chain *p_chain)
3658 void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl;
3659 u32 page_cnt = p_chain->page_cnt, i, pbl_size;
3660 u8 *p_pbl_virt = p_chain->pbl_sp.p_virt_table;
3662 if (!pp_virt_addr_tbl)
3668 for (i = 0; i < page_cnt; i++) {
3669 if (!pp_virt_addr_tbl[i])
3672 dma_free_coherent(&cdev->pdev->dev,
3673 QED_CHAIN_PAGE_SIZE,
3674 pp_virt_addr_tbl[i],
3675 *(dma_addr_t *)p_pbl_virt);
3677 p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE;
3680 pbl_size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE;
3682 if (!p_chain->b_external_pbl)
3683 dma_free_coherent(&cdev->pdev->dev,
3685 p_chain->pbl_sp.p_virt_table,
3686 p_chain->pbl_sp.p_phys_table);
3688 vfree(p_chain->pbl.pp_virt_addr_tbl);
3689 p_chain->pbl.pp_virt_addr_tbl = NULL;
3692 void qed_chain_free(struct qed_dev *cdev, struct qed_chain *p_chain)
3694 switch (p_chain->mode) {
3695 case QED_CHAIN_MODE_NEXT_PTR:
3696 qed_chain_free_next_ptr(cdev, p_chain);
3698 case QED_CHAIN_MODE_SINGLE:
3699 qed_chain_free_single(cdev, p_chain);
3701 case QED_CHAIN_MODE_PBL:
3702 qed_chain_free_pbl(cdev, p_chain);
3708 qed_chain_alloc_sanity_check(struct qed_dev *cdev,
3709 enum qed_chain_cnt_type cnt_type,
3710 size_t elem_size, u32 page_cnt)
3712 u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
3714 /* The actual chain size can be larger than the maximal possible value
3715 * after rounding up the requested elements number to pages, and after
3716 * taking into acount the unusuable elements (next-ptr elements).
3717 * The size of a "u16" chain can be (U16_MAX + 1) since the chain
3718 * size/capacity fields are of a u32 type.
3720 if ((cnt_type == QED_CHAIN_CNT_TYPE_U16 &&
3721 chain_size > ((u32)U16_MAX + 1)) ||
3722 (cnt_type == QED_CHAIN_CNT_TYPE_U32 && chain_size > U32_MAX)) {
3724 "The actual chain size (0x%llx) is larger than the maximal possible value\n",
3733 qed_chain_alloc_next_ptr(struct qed_dev *cdev, struct qed_chain *p_chain)
3735 void *p_virt = NULL, *p_virt_prev = NULL;
3736 dma_addr_t p_phys = 0;
3739 for (i = 0; i < p_chain->page_cnt; i++) {
3740 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
3741 QED_CHAIN_PAGE_SIZE,
3742 &p_phys, GFP_KERNEL);
3747 qed_chain_init_mem(p_chain, p_virt, p_phys);
3748 qed_chain_reset(p_chain);
3750 qed_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3754 p_virt_prev = p_virt;
3756 /* Last page's next element should point to the beginning of the
3759 qed_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3760 p_chain->p_virt_addr,
3761 p_chain->p_phys_addr);
3767 qed_chain_alloc_single(struct qed_dev *cdev, struct qed_chain *p_chain)
3769 dma_addr_t p_phys = 0;
3770 void *p_virt = NULL;
3772 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
3773 QED_CHAIN_PAGE_SIZE, &p_phys, GFP_KERNEL);
3777 qed_chain_init_mem(p_chain, p_virt, p_phys);
3778 qed_chain_reset(p_chain);
3784 qed_chain_alloc_pbl(struct qed_dev *cdev,
3785 struct qed_chain *p_chain,
3786 struct qed_chain_ext_pbl *ext_pbl)
3788 u32 page_cnt = p_chain->page_cnt, size, i;
3789 dma_addr_t p_phys = 0, p_pbl_phys = 0;
3790 void **pp_virt_addr_tbl = NULL;
3791 u8 *p_pbl_virt = NULL;
3792 void *p_virt = NULL;
3794 size = page_cnt * sizeof(*pp_virt_addr_tbl);
3795 pp_virt_addr_tbl = vzalloc(size);
3796 if (!pp_virt_addr_tbl)
3799 /* The allocation of the PBL table is done with its full size, since it
3800 * is expected to be successive.
3801 * qed_chain_init_pbl_mem() is called even in a case of an allocation
3802 * failure, since pp_virt_addr_tbl was previously allocated, and it
3803 * should be saved to allow its freeing during the error flow.
3805 size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE;
3808 p_pbl_virt = dma_alloc_coherent(&cdev->pdev->dev,
3809 size, &p_pbl_phys, GFP_KERNEL);
3811 p_pbl_virt = ext_pbl->p_pbl_virt;
3812 p_pbl_phys = ext_pbl->p_pbl_phys;
3813 p_chain->b_external_pbl = true;
3816 qed_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys,
3821 for (i = 0; i < page_cnt; i++) {
3822 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
3823 QED_CHAIN_PAGE_SIZE,
3824 &p_phys, GFP_KERNEL);
3829 qed_chain_init_mem(p_chain, p_virt, p_phys);
3830 qed_chain_reset(p_chain);
3833 /* Fill the PBL table with the physical address of the page */
3834 *(dma_addr_t *)p_pbl_virt = p_phys;
3835 /* Keep the virtual address of the page */
3836 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt;
3838 p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE;
3844 int qed_chain_alloc(struct qed_dev *cdev,
3845 enum qed_chain_use_mode intended_use,
3846 enum qed_chain_mode mode,
3847 enum qed_chain_cnt_type cnt_type,
3850 struct qed_chain *p_chain,
3851 struct qed_chain_ext_pbl *ext_pbl)
3856 if (mode == QED_CHAIN_MODE_SINGLE)
3859 page_cnt = QED_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
3861 rc = qed_chain_alloc_sanity_check(cdev, cnt_type, elem_size, page_cnt);
3864 "Cannot allocate a chain with the given arguments:\n");
3866 "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
3867 intended_use, mode, cnt_type, num_elems, elem_size);
3871 qed_chain_init_params(p_chain, page_cnt, (u8) elem_size, intended_use,
3875 case QED_CHAIN_MODE_NEXT_PTR:
3876 rc = qed_chain_alloc_next_ptr(cdev, p_chain);
3878 case QED_CHAIN_MODE_SINGLE:
3879 rc = qed_chain_alloc_single(cdev, p_chain);
3881 case QED_CHAIN_MODE_PBL:
3882 rc = qed_chain_alloc_pbl(cdev, p_chain, ext_pbl);
3891 qed_chain_free(cdev, p_chain);
3895 int qed_fw_l2_queue(struct qed_hwfn *p_hwfn, u16 src_id, u16 *dst_id)
3897 if (src_id >= RESC_NUM(p_hwfn, QED_L2_QUEUE)) {
3900 min = (u16) RESC_START(p_hwfn, QED_L2_QUEUE);
3901 max = min + RESC_NUM(p_hwfn, QED_L2_QUEUE);
3903 "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
3909 *dst_id = RESC_START(p_hwfn, QED_L2_QUEUE) + src_id;
3914 int qed_fw_vport(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id)
3916 if (src_id >= RESC_NUM(p_hwfn, QED_VPORT)) {
3919 min = (u8)RESC_START(p_hwfn, QED_VPORT);
3920 max = min + RESC_NUM(p_hwfn, QED_VPORT);
3922 "vport id [%d] is not valid, available indices [%d - %d]\n",
3928 *dst_id = RESC_START(p_hwfn, QED_VPORT) + src_id;
3933 int qed_fw_rss_eng(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id)
3935 if (src_id >= RESC_NUM(p_hwfn, QED_RSS_ENG)) {
3938 min = (u8)RESC_START(p_hwfn, QED_RSS_ENG);
3939 max = min + RESC_NUM(p_hwfn, QED_RSS_ENG);
3941 "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
3947 *dst_id = RESC_START(p_hwfn, QED_RSS_ENG) + src_id;
3952 static void qed_llh_mac_to_filter(u32 *p_high, u32 *p_low,
3955 *p_high = p_filter[1] | (p_filter[0] << 8);
3956 *p_low = p_filter[5] | (p_filter[4] << 8) |
3957 (p_filter[3] << 16) | (p_filter[2] << 24);
3960 int qed_llh_add_mac_filter(struct qed_hwfn *p_hwfn,
3961 struct qed_ptt *p_ptt, u8 *p_filter)
3963 u32 high = 0, low = 0, en;
3966 if (!test_bit(QED_MF_LLH_MAC_CLSS, &p_hwfn->cdev->mf_bits))
3969 qed_llh_mac_to_filter(&high, &low, p_filter);
3971 /* Find a free entry and utilize it */
3972 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3973 en = qed_rd(p_hwfn, p_ptt,
3974 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
3977 qed_wr(p_hwfn, p_ptt,
3978 NIG_REG_LLH_FUNC_FILTER_VALUE +
3979 2 * i * sizeof(u32), low);
3980 qed_wr(p_hwfn, p_ptt,
3981 NIG_REG_LLH_FUNC_FILTER_VALUE +
3982 (2 * i + 1) * sizeof(u32), high);
3983 qed_wr(p_hwfn, p_ptt,
3984 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
3985 qed_wr(p_hwfn, p_ptt,
3986 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3987 i * sizeof(u32), 0);
3988 qed_wr(p_hwfn, p_ptt,
3989 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
3992 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
3994 "Failed to find an empty LLH filter to utilize\n");
3998 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3999 "mac: %pM is added at %d\n",
4005 void qed_llh_remove_mac_filter(struct qed_hwfn *p_hwfn,
4006 struct qed_ptt *p_ptt, u8 *p_filter)
4008 u32 high = 0, low = 0;
4011 if (!test_bit(QED_MF_LLH_MAC_CLSS, &p_hwfn->cdev->mf_bits))
4014 qed_llh_mac_to_filter(&high, &low, p_filter);
4016 /* Find the entry and clean it */
4017 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4018 if (qed_rd(p_hwfn, p_ptt,
4019 NIG_REG_LLH_FUNC_FILTER_VALUE +
4020 2 * i * sizeof(u32)) != low)
4022 if (qed_rd(p_hwfn, p_ptt,
4023 NIG_REG_LLH_FUNC_FILTER_VALUE +
4024 (2 * i + 1) * sizeof(u32)) != high)
4027 qed_wr(p_hwfn, p_ptt,
4028 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
4029 qed_wr(p_hwfn, p_ptt,
4030 NIG_REG_LLH_FUNC_FILTER_VALUE + 2 * i * sizeof(u32), 0);
4031 qed_wr(p_hwfn, p_ptt,
4032 NIG_REG_LLH_FUNC_FILTER_VALUE +
4033 (2 * i + 1) * sizeof(u32), 0);
4035 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
4036 "mac: %pM is removed from %d\n",
4040 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4041 DP_NOTICE(p_hwfn, "Tried to remove a non-configured filter\n");
4045 qed_llh_add_protocol_filter(struct qed_hwfn *p_hwfn,
4046 struct qed_ptt *p_ptt,
4047 u16 source_port_or_eth_type,
4048 u16 dest_port, enum qed_llh_port_filter_type_t type)
4050 u32 high = 0, low = 0, en;
4053 if (!test_bit(QED_MF_LLH_PROTO_CLSS, &p_hwfn->cdev->mf_bits))
4057 case QED_LLH_FILTER_ETHERTYPE:
4058 high = source_port_or_eth_type;
4060 case QED_LLH_FILTER_TCP_SRC_PORT:
4061 case QED_LLH_FILTER_UDP_SRC_PORT:
4062 low = source_port_or_eth_type << 16;
4064 case QED_LLH_FILTER_TCP_DEST_PORT:
4065 case QED_LLH_FILTER_UDP_DEST_PORT:
4068 case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4069 case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4070 low = (source_port_or_eth_type << 16) | dest_port;
4074 "Non valid LLH protocol filter type %d\n", type);
4077 /* Find a free entry and utilize it */
4078 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4079 en = qed_rd(p_hwfn, p_ptt,
4080 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
4083 qed_wr(p_hwfn, p_ptt,
4084 NIG_REG_LLH_FUNC_FILTER_VALUE +
4085 2 * i * sizeof(u32), low);
4086 qed_wr(p_hwfn, p_ptt,
4087 NIG_REG_LLH_FUNC_FILTER_VALUE +
4088 (2 * i + 1) * sizeof(u32), high);
4089 qed_wr(p_hwfn, p_ptt,
4090 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 1);
4091 qed_wr(p_hwfn, p_ptt,
4092 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
4093 i * sizeof(u32), 1 << type);
4094 qed_wr(p_hwfn, p_ptt,
4095 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
4098 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
4100 "Failed to find an empty LLH filter to utilize\n");
4104 case QED_LLH_FILTER_ETHERTYPE:
4105 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
4106 "ETH type %x is added at %d\n",
4107 source_port_or_eth_type, i);
4109 case QED_LLH_FILTER_TCP_SRC_PORT:
4110 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
4111 "TCP src port %x is added at %d\n",
4112 source_port_or_eth_type, i);
4114 case QED_LLH_FILTER_UDP_SRC_PORT:
4115 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
4116 "UDP src port %x is added at %d\n",
4117 source_port_or_eth_type, i);
4119 case QED_LLH_FILTER_TCP_DEST_PORT:
4120 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
4121 "TCP dst port %x is added at %d\n", dest_port, i);
4123 case QED_LLH_FILTER_UDP_DEST_PORT:
4124 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
4125 "UDP dst port %x is added at %d\n", dest_port, i);
4127 case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4128 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
4129 "TCP src/dst ports %x/%x are added at %d\n",
4130 source_port_or_eth_type, dest_port, i);
4132 case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4133 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
4134 "UDP src/dst ports %x/%x are added at %d\n",
4135 source_port_or_eth_type, dest_port, i);
4142 qed_llh_remove_protocol_filter(struct qed_hwfn *p_hwfn,
4143 struct qed_ptt *p_ptt,
4144 u16 source_port_or_eth_type,
4146 enum qed_llh_port_filter_type_t type)
4148 u32 high = 0, low = 0;
4151 if (!test_bit(QED_MF_LLH_PROTO_CLSS, &p_hwfn->cdev->mf_bits))
4155 case QED_LLH_FILTER_ETHERTYPE:
4156 high = source_port_or_eth_type;
4158 case QED_LLH_FILTER_TCP_SRC_PORT:
4159 case QED_LLH_FILTER_UDP_SRC_PORT:
4160 low = source_port_or_eth_type << 16;
4162 case QED_LLH_FILTER_TCP_DEST_PORT:
4163 case QED_LLH_FILTER_UDP_DEST_PORT:
4166 case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4167 case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4168 low = (source_port_or_eth_type << 16) | dest_port;
4172 "Non valid LLH protocol filter type %d\n", type);
4176 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4177 if (!qed_rd(p_hwfn, p_ptt,
4178 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32)))
4180 if (!qed_rd(p_hwfn, p_ptt,
4181 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32)))
4183 if (!(qed_rd(p_hwfn, p_ptt,
4184 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
4185 i * sizeof(u32)) & BIT(type)))
4187 if (qed_rd(p_hwfn, p_ptt,
4188 NIG_REG_LLH_FUNC_FILTER_VALUE +
4189 2 * i * sizeof(u32)) != low)
4191 if (qed_rd(p_hwfn, p_ptt,
4192 NIG_REG_LLH_FUNC_FILTER_VALUE +
4193 (2 * i + 1) * sizeof(u32)) != high)
4196 qed_wr(p_hwfn, p_ptt,
4197 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
4198 qed_wr(p_hwfn, p_ptt,
4199 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
4200 qed_wr(p_hwfn, p_ptt,
4201 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
4202 i * sizeof(u32), 0);
4203 qed_wr(p_hwfn, p_ptt,
4204 NIG_REG_LLH_FUNC_FILTER_VALUE + 2 * i * sizeof(u32), 0);
4205 qed_wr(p_hwfn, p_ptt,
4206 NIG_REG_LLH_FUNC_FILTER_VALUE +
4207 (2 * i + 1) * sizeof(u32), 0);
4211 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4212 DP_NOTICE(p_hwfn, "Tried to remove a non-configured filter\n");
4215 static int qed_set_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
4216 u32 hw_addr, void *p_eth_qzone,
4217 size_t eth_qzone_size, u8 timeset)
4219 struct coalescing_timeset *p_coal_timeset;
4221 if (p_hwfn->cdev->int_coalescing_mode != QED_COAL_MODE_ENABLE) {
4222 DP_NOTICE(p_hwfn, "Coalescing configuration not enabled\n");
4226 p_coal_timeset = p_eth_qzone;
4227 memset(p_eth_qzone, 0, eth_qzone_size);
4228 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
4229 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
4230 qed_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
4235 int qed_set_queue_coalesce(u16 rx_coal, u16 tx_coal, void *p_handle)
4237 struct qed_queue_cid *p_cid = p_handle;
4238 struct qed_hwfn *p_hwfn;
4239 struct qed_ptt *p_ptt;
4242 p_hwfn = p_cid->p_owner;
4244 if (IS_VF(p_hwfn->cdev))
4245 return qed_vf_pf_set_coalesce(p_hwfn, rx_coal, tx_coal, p_cid);
4247 p_ptt = qed_ptt_acquire(p_hwfn);
4252 rc = qed_set_rxq_coalesce(p_hwfn, p_ptt, rx_coal, p_cid);
4255 p_hwfn->cdev->rx_coalesce_usecs = rx_coal;
4259 rc = qed_set_txq_coalesce(p_hwfn, p_ptt, tx_coal, p_cid);
4262 p_hwfn->cdev->tx_coalesce_usecs = tx_coal;
4265 qed_ptt_release(p_hwfn, p_ptt);
4269 int qed_set_rxq_coalesce(struct qed_hwfn *p_hwfn,
4270 struct qed_ptt *p_ptt,
4271 u16 coalesce, struct qed_queue_cid *p_cid)
4273 struct ustorm_eth_queue_zone eth_qzone;
4274 u8 timeset, timer_res;
4278 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
4279 if (coalesce <= 0x7F) {
4281 } else if (coalesce <= 0xFF) {
4283 } else if (coalesce <= 0x1FF) {
4286 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
4289 timeset = (u8)(coalesce >> timer_res);
4291 rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res,
4292 p_cid->sb_igu_id, false);
4296 address = BAR0_MAP_REG_USDM_RAM +
4297 USTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
4299 rc = qed_set_coalesce(p_hwfn, p_ptt, address, ð_qzone,
4300 sizeof(struct ustorm_eth_queue_zone), timeset);
4308 int qed_set_txq_coalesce(struct qed_hwfn *p_hwfn,
4309 struct qed_ptt *p_ptt,
4310 u16 coalesce, struct qed_queue_cid *p_cid)
4312 struct xstorm_eth_queue_zone eth_qzone;
4313 u8 timeset, timer_res;
4317 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
4318 if (coalesce <= 0x7F) {
4320 } else if (coalesce <= 0xFF) {
4322 } else if (coalesce <= 0x1FF) {
4325 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
4328 timeset = (u8)(coalesce >> timer_res);
4330 rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res,
4331 p_cid->sb_igu_id, true);
4335 address = BAR0_MAP_REG_XSDM_RAM +
4336 XSTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
4338 rc = qed_set_coalesce(p_hwfn, p_ptt, address, ð_qzone,
4339 sizeof(struct xstorm_eth_queue_zone), timeset);
4344 /* Calculate final WFQ values for all vports and configure them.
4345 * After this configuration each vport will have
4346 * approx min rate = min_pf_rate * (vport_wfq / QED_WFQ_UNIT)
4348 static void qed_configure_wfq_for_all_vports(struct qed_hwfn *p_hwfn,
4349 struct qed_ptt *p_ptt,
4352 struct init_qm_vport_params *vport_params;
4355 vport_params = p_hwfn->qm_info.qm_vport_params;
4357 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4358 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
4360 vport_params[i].vport_wfq = (wfq_speed * QED_WFQ_UNIT) /
4362 qed_init_vport_wfq(p_hwfn, p_ptt,
4363 vport_params[i].first_tx_pq_id,
4364 vport_params[i].vport_wfq);
4368 static void qed_init_wfq_default_param(struct qed_hwfn *p_hwfn,
4374 for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
4375 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
4378 static void qed_disable_wfq_for_all_vports(struct qed_hwfn *p_hwfn,
4379 struct qed_ptt *p_ptt,
4382 struct init_qm_vport_params *vport_params;
4385 vport_params = p_hwfn->qm_info.qm_vport_params;
4387 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4388 qed_init_wfq_default_param(p_hwfn, min_pf_rate);
4389 qed_init_vport_wfq(p_hwfn, p_ptt,
4390 vport_params[i].first_tx_pq_id,
4391 vport_params[i].vport_wfq);
4395 /* This function performs several validations for WFQ
4396 * configuration and required min rate for a given vport
4397 * 1. req_rate must be greater than one percent of min_pf_rate.
4398 * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
4399 * rates to get less than one percent of min_pf_rate.
4400 * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
4402 static int qed_init_wfq_param(struct qed_hwfn *p_hwfn,
4403 u16 vport_id, u32 req_rate, u32 min_pf_rate)
4405 u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
4406 int non_requested_count = 0, req_count = 0, i, num_vports;
4408 num_vports = p_hwfn->qm_info.num_vports;
4410 /* Accounting for the vports which are configured for WFQ explicitly */
4411 for (i = 0; i < num_vports; i++) {
4414 if ((i != vport_id) &&
4415 p_hwfn->qm_info.wfq_data[i].configured) {
4417 tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
4418 total_req_min_rate += tmp_speed;
4422 /* Include current vport data as well */
4424 total_req_min_rate += req_rate;
4425 non_requested_count = num_vports - req_count;
4427 if (req_rate < min_pf_rate / QED_WFQ_UNIT) {
4428 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
4429 "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
4430 vport_id, req_rate, min_pf_rate);
4434 if (num_vports > QED_WFQ_UNIT) {
4435 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
4436 "Number of vports is greater than %d\n",
4441 if (total_req_min_rate > min_pf_rate) {
4442 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
4443 "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
4444 total_req_min_rate, min_pf_rate);
4448 total_left_rate = min_pf_rate - total_req_min_rate;
4450 left_rate_per_vp = total_left_rate / non_requested_count;
4451 if (left_rate_per_vp < min_pf_rate / QED_WFQ_UNIT) {
4452 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
4453 "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
4454 left_rate_per_vp, min_pf_rate);
4458 p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
4459 p_hwfn->qm_info.wfq_data[vport_id].configured = true;
4461 for (i = 0; i < num_vports; i++) {
4462 if (p_hwfn->qm_info.wfq_data[i].configured)
4465 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
4471 static int __qed_configure_vport_wfq(struct qed_hwfn *p_hwfn,
4472 struct qed_ptt *p_ptt, u16 vp_id, u32 rate)
4474 struct qed_mcp_link_state *p_link;
4477 p_link = &p_hwfn->cdev->hwfns[0].mcp_info->link_output;
4479 if (!p_link->min_pf_rate) {
4480 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
4481 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
4485 rc = qed_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
4488 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt,
4489 p_link->min_pf_rate);
4492 "Validation failed while configuring min rate\n");
4497 static int __qed_configure_vp_wfq_on_link_change(struct qed_hwfn *p_hwfn,
4498 struct qed_ptt *p_ptt,
4501 bool use_wfq = false;
4505 /* Validate all pre configured vports for wfq */
4506 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4509 if (!p_hwfn->qm_info.wfq_data[i].configured)
4512 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
4515 rc = qed_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
4518 "WFQ validation failed while configuring min rate\n");
4524 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
4526 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
4531 /* Main API for qed clients to configure vport min rate.
4532 * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
4533 * rate - Speed in Mbps needs to be assigned to a given vport.
4535 int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate)
4537 int i, rc = -EINVAL;
4539 /* Currently not supported; Might change in future */
4540 if (cdev->num_hwfns > 1) {
4542 "WFQ configuration is not supported for this device\n");
4546 for_each_hwfn(cdev, i) {
4547 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
4548 struct qed_ptt *p_ptt;
4550 p_ptt = qed_ptt_acquire(p_hwfn);
4554 rc = __qed_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
4557 qed_ptt_release(p_hwfn, p_ptt);
4561 qed_ptt_release(p_hwfn, p_ptt);
4567 /* API to configure WFQ from mcp link change */
4568 void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev,
4569 struct qed_ptt *p_ptt, u32 min_pf_rate)
4573 if (cdev->num_hwfns > 1) {
4576 "WFQ configuration is not supported for this device\n");
4580 for_each_hwfn(cdev, i) {
4581 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
4583 __qed_configure_vp_wfq_on_link_change(p_hwfn, p_ptt,
4588 int __qed_configure_pf_max_bandwidth(struct qed_hwfn *p_hwfn,
4589 struct qed_ptt *p_ptt,
4590 struct qed_mcp_link_state *p_link,
4595 p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
4597 if (!p_link->line_speed && (max_bw != 100))
4600 p_link->speed = (p_link->line_speed * max_bw) / 100;
4601 p_hwfn->qm_info.pf_rl = p_link->speed;
4603 /* Since the limiter also affects Tx-switched traffic, we don't want it
4604 * to limit such traffic in case there's no actual limit.
4605 * In that case, set limit to imaginary high boundary.
4608 p_hwfn->qm_info.pf_rl = 100000;
4610 rc = qed_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
4611 p_hwfn->qm_info.pf_rl);
4613 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
4614 "Configured MAX bandwidth to be %08x Mb/sec\n",
4620 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
4621 int qed_configure_pf_max_bandwidth(struct qed_dev *cdev, u8 max_bw)
4623 int i, rc = -EINVAL;
4625 if (max_bw < 1 || max_bw > 100) {
4626 DP_NOTICE(cdev, "PF max bw valid range is [1-100]\n");
4630 for_each_hwfn(cdev, i) {
4631 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
4632 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev);
4633 struct qed_mcp_link_state *p_link;
4634 struct qed_ptt *p_ptt;
4636 p_link = &p_lead->mcp_info->link_output;
4638 p_ptt = qed_ptt_acquire(p_hwfn);
4642 rc = __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt,
4645 qed_ptt_release(p_hwfn, p_ptt);
4654 int __qed_configure_pf_min_bandwidth(struct qed_hwfn *p_hwfn,
4655 struct qed_ptt *p_ptt,
4656 struct qed_mcp_link_state *p_link,
4661 p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
4662 p_hwfn->qm_info.pf_wfq = min_bw;
4664 if (!p_link->line_speed)
4667 p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
4669 rc = qed_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
4671 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
4672 "Configured MIN bandwidth to be %d Mb/sec\n",
4673 p_link->min_pf_rate);
4678 /* Main API to configure PF min bandwidth where bw range is [1-100] */
4679 int qed_configure_pf_min_bandwidth(struct qed_dev *cdev, u8 min_bw)
4681 int i, rc = -EINVAL;
4683 if (min_bw < 1 || min_bw > 100) {
4684 DP_NOTICE(cdev, "PF min bw valid range is [1-100]\n");
4688 for_each_hwfn(cdev, i) {
4689 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
4690 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev);
4691 struct qed_mcp_link_state *p_link;
4692 struct qed_ptt *p_ptt;
4694 p_link = &p_lead->mcp_info->link_output;
4696 p_ptt = qed_ptt_acquire(p_hwfn);
4700 rc = __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt,
4703 qed_ptt_release(p_hwfn, p_ptt);
4707 if (p_link->min_pf_rate) {
4708 u32 min_rate = p_link->min_pf_rate;
4710 rc = __qed_configure_vp_wfq_on_link_change(p_hwfn,
4715 qed_ptt_release(p_hwfn, p_ptt);
4721 void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
4723 struct qed_mcp_link_state *p_link;
4725 p_link = &p_hwfn->mcp_info->link_output;
4727 if (p_link->min_pf_rate)
4728 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt,
4729 p_link->min_pf_rate);
4731 memset(p_hwfn->qm_info.wfq_data, 0,
4732 sizeof(*p_hwfn->qm_info.wfq_data) * p_hwfn->qm_info.num_vports);
4735 int qed_device_num_ports(struct qed_dev *cdev)
4737 return cdev->num_ports;
4740 void qed_set_fw_mac_addr(__le16 *fw_msb,
4741 __le16 *fw_mid, __le16 *fw_lsb, u8 *mac)
4743 ((u8 *)fw_msb)[0] = mac[1];
4744 ((u8 *)fw_msb)[1] = mac[0];
4745 ((u8 *)fw_mid)[0] = mac[3];
4746 ((u8 *)fw_mid)[1] = mac[2];
4747 ((u8 *)fw_lsb)[0] = mac[5];
4748 ((u8 *)fw_lsb)[1] = mac[4];