drivers/net/ethernet/qlogic/qed/qed_dev.c

   1 /* QLogic qed NIC Driver
   2  * Copyright (c) 2015 QLogic Corporation
   3  *
   4  * This software is available under the terms of the GNU General Public License
   5  * (GPL) Version 2, available from the file COPYING in the main directory of
   6  * this source tree.
   7  */
   8
   9 #include <linux/types.h>
  10 #include <asm/byteorder.h>
  11 #include <linux/io.h>
  12 #include <linux/delay.h>
  13 #include <linux/dma-mapping.h>
  14 #include <linux/errno.h>
  15 #include <linux/kernel.h>
  16 #include <linux/mutex.h>
  17 #include <linux/pci.h>
  18 #include <linux/slab.h>
  19 #include <linux/string.h>
  20 #include <linux/etherdevice.h>
  21 #include <linux/qed/qed_chain.h>
  22 #include <linux/qed/qed_if.h>
  23 #include "qed.h"
  24 #include "qed_cxt.h"
  25 #include "qed_dev_api.h"
  26 #include "qed_hsi.h"
  27 #include "qed_hw.h"
  28 #include "qed_init_ops.h"
  29 #include "qed_int.h"
  30 #include "qed_mcp.h"
  31 #include "qed_reg_addr.h"
  32 #include "qed_sp.h"
  33 #include "qed_sriov.h"
  34
  35 /* API common to all protocols */
  36 enum BAR_ID {
  37         BAR_ID_0,       /* used for GRC */
  38         BAR_ID_1        /* Used for doorbells */
  39 };
  40
  41 static u32 qed_hw_bar_size(struct qed_hwfn      *p_hwfn,
  42                            enum BAR_ID          bar_id)
  43 {
  44         u32 bar_reg = (bar_id == BAR_ID_0 ?
  45                        PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
  46         u32 val;
  47
  48         if (IS_VF(p_hwfn->cdev))
  49                 return 1 << 17;
  50
  51         val = qed_rd(p_hwfn, p_hwfn->p_main_ptt, bar_reg);
  52         if (val)
  53                 return 1 << (val + 15);
  54
  55         /* Old MFW initialized above registered only conditionally */
  56         if (p_hwfn->cdev->num_hwfns > 1) {
  57                 DP_INFO(p_hwfn,
  58                         "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n");
  59                         return BAR_ID_0 ? 256 * 1024 : 512 * 1024;
  60         } else {
  61                 DP_INFO(p_hwfn,
  62                         "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n");
  63                         return 512 * 1024;
  64         }
  65 }
  66
  67 void qed_init_dp(struct qed_dev *cdev,
  68                  u32 dp_module, u8 dp_level)
  69 {
  70         u32 i;
  71
  72         cdev->dp_level = dp_level;
  73         cdev->dp_module = dp_module;
  74         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
  75                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
  76
  77                 p_hwfn->dp_level = dp_level;
  78                 p_hwfn->dp_module = dp_module;
  79         }
  80 }
  81
  82 void qed_init_struct(struct qed_dev *cdev)
  83 {
  84         u8 i;
  85
  86         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
  87                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
  88
  89                 p_hwfn->cdev = cdev;
  90                 p_hwfn->my_id = i;
  91                 p_hwfn->b_active = false;
  92
  93                 mutex_init(&p_hwfn->dmae_info.mutex);
  94         }
  95
  96         /* hwfn 0 is always active */
  97         cdev->hwfns[0].b_active = true;
  98
  99         /* set the default cache alignment to 128 */
 100         cdev->cache_shift = 7;
 101 }
 102
 103 static void qed_qm_info_free(struct qed_hwfn *p_hwfn)
 104 {
 105         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 106
 107         kfree(qm_info->qm_pq_params);
 108         qm_info->qm_pq_params = NULL;
 109         kfree(qm_info->qm_vport_params);
 110         qm_info->qm_vport_params = NULL;
 111         kfree(qm_info->qm_port_params);
 112         qm_info->qm_port_params = NULL;
 113         kfree(qm_info->wfq_data);
 114         qm_info->wfq_data = NULL;
 115 }
 116
 117 void qed_resc_free(struct qed_dev *cdev)
 118 {
 119         int i;
 120
 121         if (IS_VF(cdev))
 122                 return;
 123
 124         kfree(cdev->fw_data);
 125         cdev->fw_data = NULL;
 126
 127         kfree(cdev->reset_stats);
 128
 129         for_each_hwfn(cdev, i) {
 130                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 131
 132                 kfree(p_hwfn->p_tx_cids);
 133                 p_hwfn->p_tx_cids = NULL;
 134                 kfree(p_hwfn->p_rx_cids);
 135                 p_hwfn->p_rx_cids = NULL;
 136         }
 137
 138         for_each_hwfn(cdev, i) {
 139                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 140
 141                 qed_cxt_mngr_free(p_hwfn);
 142                 qed_qm_info_free(p_hwfn);
 143                 qed_spq_free(p_hwfn);
 144                 qed_eq_free(p_hwfn, p_hwfn->p_eq);
 145                 qed_consq_free(p_hwfn, p_hwfn->p_consq);
 146                 qed_int_free(p_hwfn);
 147                 qed_iov_free(p_hwfn);
 148                 qed_dmae_info_free(p_hwfn);
 149         }
 150 }
 151
 152 static int qed_init_qm_info(struct qed_hwfn *p_hwfn)
 153 {
 154         u8 num_vports, vf_offset = 0, i, vport_id, num_ports, curr_queue = 0;
 155         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 156         struct init_qm_port_params *p_qm_port;
 157         u16 num_pqs, multi_cos_tcs = 1;
 158         u16 num_vfs = 0;
 159
 160 #ifdef CONFIG_QED_SRIOV
 161         if (p_hwfn->cdev->p_iov_info)
 162                 num_vfs = p_hwfn->cdev->p_iov_info->total_vfs;
 163 #endif
 164         memset(qm_info, 0, sizeof(*qm_info));
 165
 166         num_pqs = multi_cos_tcs + num_vfs + 1;  /* The '1' is for pure-LB */
 167         num_vports = (u8)RESC_NUM(p_hwfn, QED_VPORT);
 168
 169         /* Sanity checking that setup requires legal number of resources */
 170         if (num_pqs > RESC_NUM(p_hwfn, QED_PQ)) {
 171                 DP_ERR(p_hwfn,
 172                        "Need too many Physical queues - 0x%04x when only %04x are available\n",
 173                        num_pqs, RESC_NUM(p_hwfn, QED_PQ));
 174                 return -EINVAL;
 175         }
 176
 177         /* PQs will be arranged as follows: First per-TC PQ then pure-LB quete.
 178          */
 179         qm_info->qm_pq_params = kzalloc(sizeof(*qm_info->qm_pq_params) *
 180                                         num_pqs, GFP_KERNEL);
 181         if (!qm_info->qm_pq_params)
 182                 goto alloc_err;
 183
 184         qm_info->qm_vport_params = kzalloc(sizeof(*qm_info->qm_vport_params) *
 185                                            num_vports, GFP_KERNEL);
 186         if (!qm_info->qm_vport_params)
 187                 goto alloc_err;
 188
 189         qm_info->qm_port_params = kzalloc(sizeof(*qm_info->qm_port_params) *
 190                                           MAX_NUM_PORTS, GFP_KERNEL);
 191         if (!qm_info->qm_port_params)
 192                 goto alloc_err;
 193
 194         qm_info->wfq_data = kcalloc(num_vports, sizeof(*qm_info->wfq_data),
 195                                     GFP_KERNEL);
 196         if (!qm_info->wfq_data)
 197                 goto alloc_err;
 198
 199         vport_id = (u8)RESC_START(p_hwfn, QED_VPORT);
 200
 201         /* First init per-TC PQs */
 202         for (i = 0; i < multi_cos_tcs; i++, curr_queue++) {
 203                 struct init_qm_pq_params *params =
 204                     &qm_info->qm_pq_params[curr_queue];
 205
 206                 params->vport_id = vport_id;
 207                 params->tc_id = p_hwfn->hw_info.non_offload_tc;
 208                 params->wrr_group = 1;
 209         }
 210
 211         /* Then init pure-LB PQ */
 212         qm_info->pure_lb_pq = curr_queue;
 213         qm_info->qm_pq_params[curr_queue].vport_id =
 214             (u8) RESC_START(p_hwfn, QED_VPORT);
 215         qm_info->qm_pq_params[curr_queue].tc_id = PURE_LB_TC;
 216         qm_info->qm_pq_params[curr_queue].wrr_group = 1;
 217         curr_queue++;
 218
 219         qm_info->offload_pq = 0;
 220         /* Then init per-VF PQs */
 221         vf_offset = curr_queue;
 222         for (i = 0; i < num_vfs; i++) {
 223                 /* First vport is used by the PF */
 224                 qm_info->qm_pq_params[curr_queue].vport_id = vport_id + i + 1;
 225                 qm_info->qm_pq_params[curr_queue].tc_id =
 226                     p_hwfn->hw_info.non_offload_tc;
 227                 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
 228                 curr_queue++;
 229         }
 230
 231         qm_info->vf_queues_offset = vf_offset;
 232         qm_info->num_pqs = num_pqs;
 233         qm_info->num_vports = num_vports;
 234
 235         /* Initialize qm port parameters */
 236         num_ports = p_hwfn->cdev->num_ports_in_engines;
 237         for (i = 0; i < num_ports; i++) {
 238                 p_qm_port = &qm_info->qm_port_params[i];
 239                 p_qm_port->active = 1;
 240                 p_qm_port->num_active_phys_tcs = 4;
 241                 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports;
 242                 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
 243         }
 244
 245         qm_info->max_phys_tcs_per_port = NUM_OF_PHYS_TCS;
 246
 247         qm_info->start_pq = (u16)RESC_START(p_hwfn, QED_PQ);
 248
 249         qm_info->num_vf_pqs = num_vfs;
 250         qm_info->start_vport = (u8) RESC_START(p_hwfn, QED_VPORT);
 251
 252         for (i = 0; i < qm_info->num_vports; i++)
 253                 qm_info->qm_vport_params[i].vport_wfq = 1;
 254
 255         qm_info->pf_wfq = 0;
 256         qm_info->pf_rl = 0;
 257         qm_info->vport_rl_en = 1;
 258         qm_info->vport_wfq_en = 1;
 259
 260         return 0;
 261
 262 alloc_err:
 263         DP_NOTICE(p_hwfn, "Failed to allocate memory for QM params\n");
 264         qed_qm_info_free(p_hwfn);
 265         return -ENOMEM;
 266 }
 267
 268 int qed_resc_alloc(struct qed_dev *cdev)
 269 {
 270         struct qed_consq *p_consq;
 271         struct qed_eq *p_eq;
 272         int i, rc = 0;
 273
 274         if (IS_VF(cdev))
 275                 return rc;
 276
 277         cdev->fw_data = kzalloc(sizeof(*cdev->fw_data), GFP_KERNEL);
 278         if (!cdev->fw_data)
 279                 return -ENOMEM;
 280
 281         /* Allocate Memory for the Queue->CID mapping */
 282         for_each_hwfn(cdev, i) {
 283                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 284                 int tx_size = sizeof(struct qed_hw_cid_data) *
 285                                      RESC_NUM(p_hwfn, QED_L2_QUEUE);
 286                 int rx_size = sizeof(struct qed_hw_cid_data) *
 287                                      RESC_NUM(p_hwfn, QED_L2_QUEUE);
 288
 289                 p_hwfn->p_tx_cids = kzalloc(tx_size, GFP_KERNEL);
 290                 if (!p_hwfn->p_tx_cids) {
 291                         DP_NOTICE(p_hwfn,
 292                                   "Failed to allocate memory for Tx Cids\n");
 293                         rc = -ENOMEM;
 294                         goto alloc_err;
 295                 }
 296
 297                 p_hwfn->p_rx_cids = kzalloc(rx_size, GFP_KERNEL);
 298                 if (!p_hwfn->p_rx_cids) {
 299                         DP_NOTICE(p_hwfn,
 300                                   "Failed to allocate memory for Rx Cids\n");
 301                         rc = -ENOMEM;
 302                         goto alloc_err;
 303                 }
 304         }
 305
 306         for_each_hwfn(cdev, i) {
 307                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 308
 309                 /* First allocate the context manager structure */
 310                 rc = qed_cxt_mngr_alloc(p_hwfn);
 311                 if (rc)
 312                         goto alloc_err;
 313
 314                 /* Set the HW cid/tid numbers (in the contest manager)
 315                  * Must be done prior to any further computations.
 316                  */
 317                 rc = qed_cxt_set_pf_params(p_hwfn);
 318                 if (rc)
 319                         goto alloc_err;
 320
 321                 /* Prepare and process QM requirements */
 322                 rc = qed_init_qm_info(p_hwfn);
 323                 if (rc)
 324                         goto alloc_err;
 325
 326                 /* Compute the ILT client partition */
 327                 rc = qed_cxt_cfg_ilt_compute(p_hwfn);
 328                 if (rc)
 329                         goto alloc_err;
 330
 331                 /* CID map / ILT shadow table / T2
 332                  * The talbes sizes are determined by the computations above
 333                  */
 334                 rc = qed_cxt_tables_alloc(p_hwfn);
 335                 if (rc)
 336                         goto alloc_err;
 337
 338                 /* SPQ, must follow ILT because initializes SPQ context */
 339                 rc = qed_spq_alloc(p_hwfn);
 340                 if (rc)
 341                         goto alloc_err;
 342
 343                 /* SP status block allocation */
 344                 p_hwfn->p_dpc_ptt = qed_get_reserved_ptt(p_hwfn,
 345                                                          RESERVED_PTT_DPC);
 346
 347                 rc = qed_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
 348                 if (rc)
 349                         goto alloc_err;
 350
 351                 rc = qed_iov_alloc(p_hwfn);
 352                 if (rc)
 353                         goto alloc_err;
 354
 355                 /* EQ */
 356                 p_eq = qed_eq_alloc(p_hwfn, 256);
 357                 if (!p_eq) {
 358                         rc = -ENOMEM;
 359                         goto alloc_err;
 360                 }
 361                 p_hwfn->p_eq = p_eq;
 362
 363                 p_consq = qed_consq_alloc(p_hwfn);
 364                 if (!p_consq) {
 365                         rc = -ENOMEM;
 366                         goto alloc_err;
 367                 }
 368                 p_hwfn->p_consq = p_consq;
 369
 370                 /* DMA info initialization */
 371                 rc = qed_dmae_info_alloc(p_hwfn);
 372                 if (rc) {
 373                         DP_NOTICE(p_hwfn,
 374                                   "Failed to allocate memory for dmae_info structure\n");
 375                         goto alloc_err;
 376                 }
 377         }
 378
 379         cdev->reset_stats = kzalloc(sizeof(*cdev->reset_stats), GFP_KERNEL);
 380         if (!cdev->reset_stats) {
 381                 DP_NOTICE(cdev, "Failed to allocate reset statistics\n");
 382                 rc = -ENOMEM;
 383                 goto alloc_err;
 384         }
 385
 386         return 0;
 387
 388 alloc_err:
 389         qed_resc_free(cdev);
 390         return rc;
 391 }
 392
 393 void qed_resc_setup(struct qed_dev *cdev)
 394 {
 395         int i;
 396
 397         if (IS_VF(cdev))
 398                 return;
 399
 400         for_each_hwfn(cdev, i) {
 401                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 402
 403                 qed_cxt_mngr_setup(p_hwfn);
 404                 qed_spq_setup(p_hwfn);
 405                 qed_eq_setup(p_hwfn, p_hwfn->p_eq);
 406                 qed_consq_setup(p_hwfn, p_hwfn->p_consq);
 407
 408                 /* Read shadow of current MFW mailbox */
 409                 qed_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
 410                 memcpy(p_hwfn->mcp_info->mfw_mb_shadow,
 411                        p_hwfn->mcp_info->mfw_mb_cur,
 412                        p_hwfn->mcp_info->mfw_mb_length);
 413
 414                 qed_int_setup(p_hwfn, p_hwfn->p_main_ptt);
 415
 416                 qed_iov_setup(p_hwfn, p_hwfn->p_main_ptt);
 417         }
 418 }
 419
 420 #define FINAL_CLEANUP_POLL_CNT          (100)
 421 #define FINAL_CLEANUP_POLL_TIME         (10)
 422 int qed_final_cleanup(struct qed_hwfn *p_hwfn,
 423                       struct qed_ptt *p_ptt,
 424                       u16 id)
 425 {
 426         u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
 427         int rc = -EBUSY;
 428
 429         addr = GTT_BAR0_MAP_REG_USDM_RAM +
 430                 USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
 431
 432         command |= X_FINAL_CLEANUP_AGG_INT <<
 433                 SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
 434         command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
 435         command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
 436         command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
 437
 438         /* Make sure notification is not set before initiating final cleanup */
 439         if (REG_RD(p_hwfn, addr)) {
 440                 DP_NOTICE(
 441                         p_hwfn,
 442                         "Unexpected; Found final cleanup notification before initiating final cleanup\n");
 443                 REG_WR(p_hwfn, addr, 0);
 444         }
 445
 446         DP_VERBOSE(p_hwfn, QED_MSG_IOV,
 447                    "Sending final cleanup for PFVF[%d] [Command %08x\n]",
 448                    id, command);
 449
 450         qed_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);
 451
 452         /* Poll until completion */
 453         while (!REG_RD(p_hwfn, addr) && count--)
 454                 msleep(FINAL_CLEANUP_POLL_TIME);
 455
 456         if (REG_RD(p_hwfn, addr))
 457                 rc = 0;
 458         else
 459                 DP_NOTICE(p_hwfn,
 460                           "Failed to receive FW final cleanup notification\n");
 461
 462         /* Cleanup afterwards */
 463         REG_WR(p_hwfn, addr, 0);
 464
 465         return rc;
 466 }
 467
 468 static void qed_calc_hw_mode(struct qed_hwfn *p_hwfn)
 469 {
 470         int hw_mode = 0;
 471
 472         hw_mode = (1 << MODE_BB_B0);
 473
 474         switch (p_hwfn->cdev->num_ports_in_engines) {
 475         case 1:
 476                 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
 477                 break;
 478         case 2:
 479                 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
 480                 break;
 481         case 4:
 482                 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
 483                 break;
 484         default:
 485                 DP_NOTICE(p_hwfn, "num_ports_in_engine = %d not supported\n",
 486                           p_hwfn->cdev->num_ports_in_engines);
 487                 return;
 488         }
 489
 490         switch (p_hwfn->cdev->mf_mode) {
 491         case QED_MF_DEFAULT:
 492         case QED_MF_NPAR:
 493                 hw_mode |= 1 << MODE_MF_SI;
 494                 break;
 495         case QED_MF_OVLAN:
 496                 hw_mode |= 1 << MODE_MF_SD;
 497                 break;
 498         default:
 499                 DP_NOTICE(p_hwfn, "Unsupported MF mode, init as DEFAULT\n");
 500                 hw_mode |= 1 << MODE_MF_SI;
 501         }
 502
 503         hw_mode |= 1 << MODE_ASIC;
 504
 505         p_hwfn->hw_info.hw_mode = hw_mode;
 506 }
 507
 508 /* Init run time data for all PFs on an engine. */
 509 static void qed_init_cau_rt_data(struct qed_dev *cdev)
 510 {
 511         u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
 512         int i, sb_id;
 513
 514         for_each_hwfn(cdev, i) {
 515                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 516                 struct qed_igu_info *p_igu_info;
 517                 struct qed_igu_block *p_block;
 518                 struct cau_sb_entry sb_entry;
 519
 520                 p_igu_info = p_hwfn->hw_info.p_igu_info;
 521
 522                 for (sb_id = 0; sb_id < QED_MAPPING_MEMORY_SIZE(cdev);
 523                      sb_id++) {
 524                         p_block = &p_igu_info->igu_map.igu_blocks[sb_id];
 525                         if (!p_block->is_pf)
 526                                 continue;
 527
 528                         qed_init_cau_sb_entry(p_hwfn, &sb_entry,
 529                                               p_block->function_id,
 530                                               0, 0);
 531                         STORE_RT_REG_AGG(p_hwfn, offset + sb_id * 2,
 532                                          sb_entry);
 533                 }
 534         }
 535 }
 536
 537 static int qed_hw_init_common(struct qed_hwfn *p_hwfn,
 538                               struct qed_ptt *p_ptt,
 539                               int hw_mode)
 540 {
 541         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 542         struct qed_qm_common_rt_init_params params;
 543         struct qed_dev *cdev = p_hwfn->cdev;
 544         u32 concrete_fid;
 545         int rc = 0;
 546         u8 vf_id;
 547
 548         qed_init_cau_rt_data(cdev);
 549
 550         /* Program GTT windows */
 551         qed_gtt_init(p_hwfn);
 552
 553         if (p_hwfn->mcp_info) {
 554                 if (p_hwfn->mcp_info->func_info.bandwidth_max)
 555                         qm_info->pf_rl_en = 1;
 556                 if (p_hwfn->mcp_info->func_info.bandwidth_min)
 557                         qm_info->pf_wfq_en = 1;
 558         }
 559
 560         memset(&params, 0, sizeof(params));
 561         params.max_ports_per_engine = p_hwfn->cdev->num_ports_in_engines;
 562         params.max_phys_tcs_per_port = qm_info->max_phys_tcs_per_port;
 563         params.pf_rl_en = qm_info->pf_rl_en;
 564         params.pf_wfq_en = qm_info->pf_wfq_en;
 565         params.vport_rl_en = qm_info->vport_rl_en;
 566         params.vport_wfq_en = qm_info->vport_wfq_en;
 567         params.port_params = qm_info->qm_port_params;
 568
 569         qed_qm_common_rt_init(p_hwfn, &params);
 570
 571         qed_cxt_hw_init_common(p_hwfn);
 572
 573         /* Close gate from NIG to BRB/Storm; By default they are open, but
 574          * we close them to prevent NIG from passing data to reset blocks.
 575          * Should have been done in the ENGINE phase, but init-tool lacks
 576          * proper port-pretend capabilities.
 577          */
 578         qed_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0);
 579         qed_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0);
 580         qed_port_pretend(p_hwfn, p_ptt, p_hwfn->port_id ^ 1);
 581         qed_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0);
 582         qed_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0);
 583         qed_port_unpretend(p_hwfn, p_ptt);
 584
 585         rc = qed_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);
 586         if (rc != 0)
 587                 return rc;
 588
 589         qed_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
 590         qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
 591
 592         /* Disable relaxed ordering in the PCI config space */
 593         qed_wr(p_hwfn, p_ptt, 0x20b4,
 594                qed_rd(p_hwfn, p_ptt, 0x20b4) & ~0x10);
 595
 596         for (vf_id = 0; vf_id < MAX_NUM_VFS_BB; vf_id++) {
 597                 concrete_fid = qed_vfid_to_concrete(p_hwfn, vf_id);
 598                 qed_fid_pretend(p_hwfn, p_ptt, (u16) concrete_fid);
 599                 qed_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
 600         }
 601         /* pretend to original PF */
 602         qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
 603
 604         return rc;
 605 }
 606
 607 static int qed_hw_init_port(struct qed_hwfn *p_hwfn,
 608                             struct qed_ptt *p_ptt,
 609                             int hw_mode)
 610 {
 611         int rc = 0;
 612
 613         rc = qed_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id,
 614                           hw_mode);
 615         return rc;
 616 }
 617
 618 static int qed_hw_init_pf(struct qed_hwfn *p_hwfn,
 619                           struct qed_ptt *p_ptt,
 620                           struct qed_tunn_start_params *p_tunn,
 621                           int hw_mode,
 622                           bool b_hw_start,
 623                           enum qed_int_mode int_mode,
 624                           bool allow_npar_tx_switch)
 625 {
 626         u8 rel_pf_id = p_hwfn->rel_pf_id;
 627         int rc = 0;
 628
 629         if (p_hwfn->mcp_info) {
 630                 struct qed_mcp_function_info *p_info;
 631
 632                 p_info = &p_hwfn->mcp_info->func_info;
 633                 if (p_info->bandwidth_min)
 634                         p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
 635
 636                 /* Update rate limit once we'll actually have a link */
 637                 p_hwfn->qm_info.pf_rl = 100000;
 638         }
 639
 640         qed_cxt_hw_init_pf(p_hwfn);
 641
 642         qed_int_igu_init_rt(p_hwfn);
 643
 644         /* Set VLAN in NIG if needed */
 645         if (hw_mode & (1 << MODE_MF_SD)) {
 646                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "Configuring LLH_FUNC_TAG\n");
 647                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
 648                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
 649                              p_hwfn->hw_info.ovlan);
 650         }
 651
 652         /* Enable classification by MAC if needed */
 653         if (hw_mode & (1 << MODE_MF_SI)) {
 654                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
 655                            "Configuring TAGMAC_CLS_TYPE\n");
 656                 STORE_RT_REG(p_hwfn,
 657                              NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET, 1);
 658         }
 659
 660         /* Protocl Configuration  */
 661         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET, 0);
 662         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET, 0);
 663         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
 664
 665         /* Cleanup chip from previous driver if such remains exist */
 666         rc = qed_final_cleanup(p_hwfn, p_ptt, rel_pf_id);
 667         if (rc != 0)
 668                 return rc;
 669
 670         /* PF Init sequence */
 671         rc = qed_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
 672         if (rc)
 673                 return rc;
 674
 675         /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
 676         rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
 677         if (rc)
 678                 return rc;
 679
 680         /* Pure runtime initializations - directly to the HW  */
 681         qed_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
 682
 683         if (b_hw_start) {
 684                 /* enable interrupts */
 685                 qed_int_igu_enable(p_hwfn, p_ptt, int_mode);
 686
 687                 /* send function start command */
 688                 rc = qed_sp_pf_start(p_hwfn, p_tunn, p_hwfn->cdev->mf_mode);
 689                 if (rc)
 690                         DP_NOTICE(p_hwfn, "Function start ramrod failed\n");
 691         }
 692         return rc;
 693 }
 694
 695 static int qed_change_pci_hwfn(struct qed_hwfn *p_hwfn,
 696                                struct qed_ptt *p_ptt,
 697                                u8 enable)
 698 {
 699         u32 delay_idx = 0, val, set_val = enable ? 1 : 0;
 700
 701         /* Change PF in PXP */
 702         qed_wr(p_hwfn, p_ptt,
 703                PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
 704
 705         /* wait until value is set - try for 1 second every 50us */
 706         for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
 707                 val = qed_rd(p_hwfn, p_ptt,
 708                              PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
 709                 if (val == set_val)
 710                         break;
 711
 712                 usleep_range(50, 60);
 713         }
 714
 715         if (val != set_val) {
 716                 DP_NOTICE(p_hwfn,
 717                           "PFID_ENABLE_MASTER wasn't changed after a second\n");
 718                 return -EAGAIN;
 719         }
 720
 721         return 0;
 722 }
 723
 724 static void qed_reset_mb_shadow(struct qed_hwfn *p_hwfn,
 725                                 struct qed_ptt *p_main_ptt)
 726 {
 727         /* Read shadow of current MFW mailbox */
 728         qed_mcp_read_mb(p_hwfn, p_main_ptt);
 729         memcpy(p_hwfn->mcp_info->mfw_mb_shadow,
 730                p_hwfn->mcp_info->mfw_mb_cur,
 731                p_hwfn->mcp_info->mfw_mb_length);
 732 }
 733
 734 int qed_hw_init(struct qed_dev *cdev,
 735                 struct qed_tunn_start_params *p_tunn,
 736                 bool b_hw_start,
 737                 enum qed_int_mode int_mode,
 738                 bool allow_npar_tx_switch,
 739                 const u8 *bin_fw_data)
 740 {
 741         u32 load_code, param;
 742         int rc, mfw_rc, i;
 743
 744         if (IS_PF(cdev)) {
 745                 rc = qed_init_fw_data(cdev, bin_fw_data);
 746                 if (rc != 0)
 747                         return rc;
 748         }
 749
 750         for_each_hwfn(cdev, i) {
 751                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 752
 753                 if (IS_VF(cdev)) {
 754                         p_hwfn->b_int_enabled = 1;
 755                         continue;
 756                 }
 757
 758                 /* Enable DMAE in PXP */
 759                 rc = qed_change_pci_hwfn(p_hwfn, p_hwfn->p_main_ptt, true);
 760
 761                 qed_calc_hw_mode(p_hwfn);
 762
 763                 rc = qed_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt,
 764                                       &load_code);
 765                 if (rc) {
 766                         DP_NOTICE(p_hwfn, "Failed sending LOAD_REQ command\n");
 767                         return rc;
 768                 }
 769
 770                 qed_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
 771
 772                 DP_VERBOSE(p_hwfn, QED_MSG_SP,
 773                            "Load request was sent. Resp:0x%x, Load code: 0x%x\n",
 774                            rc, load_code);
 775
 776                 p_hwfn->first_on_engine = (load_code ==
 777                                            FW_MSG_CODE_DRV_LOAD_ENGINE);
 778
 779                 switch (load_code) {
 780                 case FW_MSG_CODE_DRV_LOAD_ENGINE:
 781                         rc = qed_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
 782                                                 p_hwfn->hw_info.hw_mode);
 783                         if (rc)
 784                                 break;
 785                 /* Fall into */
 786                 case FW_MSG_CODE_DRV_LOAD_PORT:
 787                         rc = qed_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
 788                                               p_hwfn->hw_info.hw_mode);
 789                         if (rc)
 790                                 break;
 791
 792                 /* Fall into */
 793                 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
 794                         rc = qed_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
 795                                             p_tunn, p_hwfn->hw_info.hw_mode,
 796                                             b_hw_start, int_mode,
 797                                             allow_npar_tx_switch);
 798                         break;
 799                 default:
 800                         rc = -EINVAL;
 801                         break;
 802                 }
 803
 804                 if (rc)
 805                         DP_NOTICE(p_hwfn,
 806                                   "init phase failed for loadcode 0x%x (rc %d)\n",
 807                                    load_code, rc);
 808
 809                 /* ACK mfw regardless of success or failure of initialization */
 810                 mfw_rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
 811                                      DRV_MSG_CODE_LOAD_DONE,
 812                                      0, &load_code, &param);
 813                 if (rc)
 814                         return rc;
 815                 if (mfw_rc) {
 816                         DP_NOTICE(p_hwfn, "Failed sending LOAD_DONE command\n");
 817                         return mfw_rc;
 818                 }
 819
 820                 p_hwfn->hw_init_done = true;
 821         }
 822
 823         return 0;
 824 }
 825
 826 #define QED_HW_STOP_RETRY_LIMIT (10)
 827 static inline void qed_hw_timers_stop(struct qed_dev *cdev,
 828                                       struct qed_hwfn *p_hwfn,
 829                                       struct qed_ptt *p_ptt)
 830 {
 831         int i;
 832
 833         /* close timers */
 834         qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
 835         qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
 836
 837         for (i = 0; i < QED_HW_STOP_RETRY_LIMIT; i++) {
 838                 if ((!qed_rd(p_hwfn, p_ptt,
 839                              TM_REG_PF_SCAN_ACTIVE_CONN)) &&
 840                     (!qed_rd(p_hwfn, p_ptt,
 841                              TM_REG_PF_SCAN_ACTIVE_TASK)))
 842                         break;
 843
 844                 /* Dependent on number of connection/tasks, possibly
 845                  * 1ms sleep is required between polls
 846                  */
 847                 usleep_range(1000, 2000);
 848         }
 849
 850         if (i < QED_HW_STOP_RETRY_LIMIT)
 851                 return;
 852
 853         DP_NOTICE(p_hwfn,
 854                   "Timers linear scans are not over [Connection %02x Tasks %02x]\n",
 855                   (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
 856                   (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
 857 }
 858
 859 void qed_hw_timers_stop_all(struct qed_dev *cdev)
 860 {
 861         int j;
 862
 863         for_each_hwfn(cdev, j) {
 864                 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
 865                 struct qed_ptt *p_ptt = p_hwfn->p_main_ptt;
 866
 867                 qed_hw_timers_stop(cdev, p_hwfn, p_ptt);
 868         }
 869 }
 870
 871 int qed_hw_stop(struct qed_dev *cdev)
 872 {
 873         int rc = 0, t_rc;
 874         int j;
 875
 876         for_each_hwfn(cdev, j) {
 877                 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
 878                 struct qed_ptt *p_ptt = p_hwfn->p_main_ptt;
 879
 880                 DP_VERBOSE(p_hwfn, NETIF_MSG_IFDOWN, "Stopping hw/fw\n");
 881
 882                 if (IS_VF(cdev)) {
 883                         /* To be implemented in a later patch */
 884                         continue;
 885                 }
 886
 887                 /* mark the hw as uninitialized... */
 888                 p_hwfn->hw_init_done = false;
 889
 890                 rc = qed_sp_pf_stop(p_hwfn);
 891                 if (rc)
 892                         DP_NOTICE(p_hwfn,
 893                                   "Failed to close PF against FW. Continue to stop HW to prevent illegal host access by the device\n");
 894
 895                 qed_wr(p_hwfn, p_ptt,
 896                        NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
 897
 898                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
 899                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
 900                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
 901                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
 902                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
 903
 904                 qed_hw_timers_stop(cdev, p_hwfn, p_ptt);
 905
 906                 /* Disable Attention Generation */
 907                 qed_int_igu_disable_int(p_hwfn, p_ptt);
 908
 909                 qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
 910                 qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
 911
 912                 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
 913
 914                 /* Need to wait 1ms to guarantee SBs are cleared */
 915                 usleep_range(1000, 2000);
 916         }
 917
 918         if (IS_PF(cdev)) {
 919                 /* Disable DMAE in PXP - in CMT, this should only be done for
 920                  * first hw-function, and only after all transactions have
 921                  * stopped for all active hw-functions.
 922                  */
 923                 t_rc = qed_change_pci_hwfn(&cdev->hwfns[0],
 924                                            cdev->hwfns[0].p_main_ptt, false);
 925                 if (t_rc != 0)
 926                         rc = t_rc;
 927         }
 928
 929         return rc;
 930 }
 931
 932 void qed_hw_stop_fastpath(struct qed_dev *cdev)
 933 {
 934         int j;
 935
 936         for_each_hwfn(cdev, j) {
 937                 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
 938                 struct qed_ptt *p_ptt   = p_hwfn->p_main_ptt;
 939
 940                 DP_VERBOSE(p_hwfn,
 941                            NETIF_MSG_IFDOWN,
 942                            "Shutting down the fastpath\n");
 943
 944                 qed_wr(p_hwfn, p_ptt,
 945                        NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
 946
 947                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
 948                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
 949                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
 950                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
 951                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
 952
 953                 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
 954
 955                 /* Need to wait 1ms to guarantee SBs are cleared */
 956                 usleep_range(1000, 2000);
 957         }
 958 }
 959
 960 void qed_hw_start_fastpath(struct qed_hwfn *p_hwfn)
 961 {
 962         /* Re-open incoming traffic */
 963         qed_wr(p_hwfn, p_hwfn->p_main_ptt,
 964                NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
 965 }
 966
 967 static int qed_reg_assert(struct qed_hwfn *hwfn,
 968                           struct qed_ptt *ptt, u32 reg,
 969                           bool expected)
 970 {
 971         u32 assert_val = qed_rd(hwfn, ptt, reg);
 972
 973         if (assert_val != expected) {
 974                 DP_NOTICE(hwfn, "Value at address 0x%x != 0x%08x\n",
 975                           reg, expected);
 976                 return -EINVAL;
 977         }
 978
 979         return 0;
 980 }
 981
 982 int qed_hw_reset(struct qed_dev *cdev)
 983 {
 984         int rc = 0;
 985         u32 unload_resp, unload_param;
 986         int i;
 987
 988         for_each_hwfn(cdev, i) {
 989                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 990
 991                 if (IS_VF(cdev)) {
 992                         /* Will be implemented in a later patch */
 993                         continue;
 994                 }
 995
 996                 DP_VERBOSE(p_hwfn, NETIF_MSG_IFDOWN, "Resetting hw/fw\n");
 997
 998                 /* Check for incorrect states */
 999                 qed_reg_assert(p_hwfn, p_hwfn->p_main_ptt,
1000                                QM_REG_USG_CNT_PF_TX, 0);
1001                 qed_reg_assert(p_hwfn, p_hwfn->p_main_ptt,
1002                                QM_REG_USG_CNT_PF_OTHER, 0);
1003
1004                 /* Disable PF in HW blocks */
1005                 qed_wr(p_hwfn, p_hwfn->p_main_ptt, DORQ_REG_PF_DB_ENABLE, 0);
1006                 qed_wr(p_hwfn, p_hwfn->p_main_ptt, QM_REG_PF_EN, 0);
1007                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1008                        TCFC_REG_STRONG_ENABLE_PF, 0);
1009                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1010                        CCFC_REG_STRONG_ENABLE_PF, 0);
1011
1012                 /* Send unload command to MCP */
1013                 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1014                                  DRV_MSG_CODE_UNLOAD_REQ,
1015                                  DRV_MB_PARAM_UNLOAD_WOL_MCP,
1016                                  &unload_resp, &unload_param);
1017                 if (rc) {
1018                         DP_NOTICE(p_hwfn, "qed_hw_reset: UNLOAD_REQ failed\n");
1019                         unload_resp = FW_MSG_CODE_DRV_UNLOAD_ENGINE;
1020                 }
1021
1022                 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1023                                  DRV_MSG_CODE_UNLOAD_DONE,
1024                                  0, &unload_resp, &unload_param);
1025                 if (rc) {
1026                         DP_NOTICE(p_hwfn, "qed_hw_reset: UNLOAD_DONE failed\n");
1027                         return rc;
1028                 }
1029         }
1030
1031         return rc;
1032 }
1033
1034 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
1035 static void qed_hw_hwfn_free(struct qed_hwfn *p_hwfn)
1036 {
1037         qed_ptt_pool_free(p_hwfn);
1038         kfree(p_hwfn->hw_info.p_igu_info);
1039 }
1040
1041 /* Setup bar access */
1042 static void qed_hw_hwfn_prepare(struct qed_hwfn *p_hwfn)
1043 {
1044         /* clear indirect access */
1045         qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_88_F0, 0);
1046         qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_8C_F0, 0);
1047         qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_90_F0, 0);
1048         qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_94_F0, 0);
1049
1050         /* Clean Previous errors if such exist */
1051         qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1052                PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR,
1053                1 << p_hwfn->abs_pf_id);
1054
1055         /* enable internal target-read */
1056         qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1057                PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1058 }
1059
1060 static void get_function_id(struct qed_hwfn *p_hwfn)
1061 {
1062         /* ME Register */
1063         p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR);
1064
1065         p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
1066
1067         p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
1068         p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
1069                                       PXP_CONCRETE_FID_PFID);
1070         p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
1071                                     PXP_CONCRETE_FID_PORT);
1072 }
1073
1074 static void qed_hw_set_feat(struct qed_hwfn *p_hwfn)
1075 {
1076         u32 *feat_num = p_hwfn->hw_info.feat_num;
1077         int num_features = 1;
1078
1079         feat_num[QED_PF_L2_QUE] = min_t(u32, RESC_NUM(p_hwfn, QED_SB) /
1080                                                 num_features,
1081                                         RESC_NUM(p_hwfn, QED_L2_QUEUE));
1082         DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE,
1083                    "#PF_L2_QUEUES=%d #SBS=%d num_features=%d\n",
1084                    feat_num[QED_PF_L2_QUE], RESC_NUM(p_hwfn, QED_SB),
1085                    num_features);
1086 }
1087
1088 static void qed_hw_get_resc(struct qed_hwfn *p_hwfn)
1089 {
1090         u32 *resc_start = p_hwfn->hw_info.resc_start;
1091         u8 num_funcs = p_hwfn->num_funcs_on_engine;
1092         u32 *resc_num = p_hwfn->hw_info.resc_num;
1093         struct qed_sb_cnt_info sb_cnt_info;
1094         int i;
1095
1096         memset(&sb_cnt_info, 0, sizeof(sb_cnt_info));
1097         qed_int_get_num_sbs(p_hwfn, &sb_cnt_info);
1098
1099         resc_num[QED_SB] = min_t(u32,
1100                                  (MAX_SB_PER_PATH_BB / num_funcs),
1101                                  sb_cnt_info.sb_cnt);
1102         resc_num[QED_L2_QUEUE] = MAX_NUM_L2_QUEUES_BB / num_funcs;
1103         resc_num[QED_VPORT] = MAX_NUM_VPORTS_BB / num_funcs;
1104         resc_num[QED_RSS_ENG] = ETH_RSS_ENGINE_NUM_BB / num_funcs;
1105         resc_num[QED_PQ] = MAX_QM_TX_QUEUES_BB / num_funcs;
1106         resc_num[QED_RL] = 8;
1107         resc_num[QED_MAC] = ETH_NUM_MAC_FILTERS / num_funcs;
1108         resc_num[QED_VLAN] = (ETH_NUM_VLAN_FILTERS - 1 /*For vlan0*/) /
1109                              num_funcs;
1110         resc_num[QED_ILT] = 950;
1111
1112         for (i = 0; i < QED_MAX_RESC; i++)
1113                 resc_start[i] = resc_num[i] * p_hwfn->rel_pf_id;
1114
1115         qed_hw_set_feat(p_hwfn);
1116
1117         DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE,
1118                    "The numbers for each resource are:\n"
1119                    "SB = %d start = %d\n"
1120                    "L2_QUEUE = %d start = %d\n"
1121                    "VPORT = %d start = %d\n"
1122                    "PQ = %d start = %d\n"
1123                    "RL = %d start = %d\n"
1124                    "MAC = %d start = %d\n"
1125                    "VLAN = %d start = %d\n"
1126                    "ILT = %d start = %d\n",
1127                    p_hwfn->hw_info.resc_num[QED_SB],
1128                    p_hwfn->hw_info.resc_start[QED_SB],
1129                    p_hwfn->hw_info.resc_num[QED_L2_QUEUE],
1130                    p_hwfn->hw_info.resc_start[QED_L2_QUEUE],
1131                    p_hwfn->hw_info.resc_num[QED_VPORT],
1132                    p_hwfn->hw_info.resc_start[QED_VPORT],
1133                    p_hwfn->hw_info.resc_num[QED_PQ],
1134                    p_hwfn->hw_info.resc_start[QED_PQ],
1135                    p_hwfn->hw_info.resc_num[QED_RL],
1136                    p_hwfn->hw_info.resc_start[QED_RL],
1137                    p_hwfn->hw_info.resc_num[QED_MAC],
1138                    p_hwfn->hw_info.resc_start[QED_MAC],
1139                    p_hwfn->hw_info.resc_num[QED_VLAN],
1140                    p_hwfn->hw_info.resc_start[QED_VLAN],
1141                    p_hwfn->hw_info.resc_num[QED_ILT],
1142                    p_hwfn->hw_info.resc_start[QED_ILT]);
1143 }
1144
1145 static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn,
1146                                struct qed_ptt *p_ptt)
1147 {
1148         u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg;
1149         u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
1150         struct qed_mcp_link_params *link;
1151
1152         /* Read global nvm_cfg address */
1153         nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
1154
1155         /* Verify MCP has initialized it */
1156         if (!nvm_cfg_addr) {
1157                 DP_NOTICE(p_hwfn, "Shared memory not initialized\n");
1158                 return -EINVAL;
1159         }
1160
1161         /* Read nvm_cfg1  (Notice this is just offset, and not offsize (TBD) */
1162         nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
1163
1164         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
1165                offsetof(struct nvm_cfg1, glob) +
1166                offsetof(struct nvm_cfg1_glob, core_cfg);
1167
1168         core_cfg = qed_rd(p_hwfn, p_ptt, addr);
1169
1170         switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
1171                 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
1172         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_2X40G:
1173                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X40G;
1174                 break;
1175         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_2X50G:
1176                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X50G;
1177                 break;
1178         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_1X100G:
1179                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X100G;
1180                 break;
1181         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_4X10G_F:
1182                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_F;
1183                 break;
1184         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_4X10G_E:
1185                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_E;
1186                 break;
1187         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_4X20G:
1188                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X20G;
1189                 break;
1190         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_1X40G:
1191                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X40G;
1192                 break;
1193         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_2X25G:
1194                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X25G;
1195                 break;
1196         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_1X25G:
1197                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X25G;
1198                 break;
1199         default:
1200                 DP_NOTICE(p_hwfn, "Unknown port mode in 0x%08x\n",
1201                           core_cfg);
1202                 break;
1203         }
1204
1205         /* Read default link configuration */
1206         link = &p_hwfn->mcp_info->link_input;
1207         port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
1208                         offsetof(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
1209         link_temp = qed_rd(p_hwfn, p_ptt,
1210                            port_cfg_addr +
1211                            offsetof(struct nvm_cfg1_port, speed_cap_mask));
1212         link->speed.advertised_speeds =
1213                 link_temp & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
1214
1215         p_hwfn->mcp_info->link_capabilities.speed_capabilities =
1216                                                 link->speed.advertised_speeds;
1217
1218         link_temp = qed_rd(p_hwfn, p_ptt,
1219                            port_cfg_addr +
1220                            offsetof(struct nvm_cfg1_port, link_settings));
1221         switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
1222                 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
1223         case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
1224                 link->speed.autoneg = true;
1225                 break;
1226         case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
1227                 link->speed.forced_speed = 1000;
1228                 break;
1229         case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
1230                 link->speed.forced_speed = 10000;
1231                 break;
1232         case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
1233                 link->speed.forced_speed = 25000;
1234                 break;
1235         case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
1236                 link->speed.forced_speed = 40000;
1237                 break;
1238         case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
1239                 link->speed.forced_speed = 50000;
1240                 break;
1241         case NVM_CFG1_PORT_DRV_LINK_SPEED_100G:
1242                 link->speed.forced_speed = 100000;
1243                 break;
1244         default:
1245                 DP_NOTICE(p_hwfn, "Unknown Speed in 0x%08x\n",
1246                           link_temp);
1247         }
1248
1249         link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
1250         link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
1251         link->pause.autoneg = !!(link_temp &
1252                                  NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
1253         link->pause.forced_rx = !!(link_temp &
1254                                    NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
1255         link->pause.forced_tx = !!(link_temp &
1256                                    NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
1257         link->loopback_mode = 0;
1258
1259         DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
1260                    "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n",
1261                    link->speed.forced_speed, link->speed.advertised_speeds,
1262                    link->speed.autoneg, link->pause.autoneg);
1263
1264         /* Read Multi-function information from shmem */
1265         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
1266                offsetof(struct nvm_cfg1, glob) +
1267                offsetof(struct nvm_cfg1_glob, generic_cont0);
1268
1269         generic_cont0 = qed_rd(p_hwfn, p_ptt, addr);
1270
1271         mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
1272                   NVM_CFG1_GLOB_MF_MODE_OFFSET;
1273
1274         switch (mf_mode) {
1275         case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
1276                 p_hwfn->cdev->mf_mode = QED_MF_OVLAN;
1277                 break;
1278         case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
1279                 p_hwfn->cdev->mf_mode = QED_MF_NPAR;
1280                 break;
1281         case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
1282                 p_hwfn->cdev->mf_mode = QED_MF_DEFAULT;
1283                 break;
1284         }
1285         DP_INFO(p_hwfn, "Multi function mode is %08x\n",
1286                 p_hwfn->cdev->mf_mode);
1287
1288         /* Read Multi-function information from shmem */
1289         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
1290                 offsetof(struct nvm_cfg1, glob) +
1291                 offsetof(struct nvm_cfg1_glob, device_capabilities);
1292
1293         device_capabilities = qed_rd(p_hwfn, p_ptt, addr);
1294         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
1295                 __set_bit(QED_DEV_CAP_ETH,
1296                           &p_hwfn->hw_info.device_capabilities);
1297
1298         return qed_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
1299 }
1300
1301 static void qed_get_num_funcs(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1302 {
1303         u32 reg_function_hide, tmp, eng_mask;
1304         u8 num_funcs;
1305
1306         num_funcs = MAX_NUM_PFS_BB;
1307
1308         /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
1309          * in the other bits are selected.
1310          * Bits 1-15 are for functions 1-15, respectively, and their value is
1311          * '0' only for enabled functions (function 0 always exists and
1312          * enabled).
1313          * In case of CMT, only the "even" functions are enabled, and thus the
1314          * number of functions for both hwfns is learnt from the same bits.
1315          */
1316         reg_function_hide = qed_rd(p_hwfn, p_ptt, MISCS_REG_FUNCTION_HIDE);
1317
1318         if (reg_function_hide & 0x1) {
1319                 if (QED_PATH_ID(p_hwfn) && p_hwfn->cdev->num_hwfns == 1) {
1320                         num_funcs = 0;
1321                         eng_mask = 0xaaaa;
1322                 } else {
1323                         num_funcs = 1;
1324                         eng_mask = 0x5554;
1325                 }
1326
1327                 /* Get the number of the enabled functions on the engine */
1328                 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
1329                 while (tmp) {
1330                         if (tmp & 0x1)
1331                                 num_funcs++;
1332                         tmp >>= 0x1;
1333                 }
1334         }
1335
1336         p_hwfn->num_funcs_on_engine = num_funcs;
1337
1338         DP_VERBOSE(p_hwfn,
1339                    NETIF_MSG_PROBE,
1340                    "PF [rel_id %d, abs_id %d] within the %d enabled functions on the engine\n",
1341                    p_hwfn->rel_pf_id,
1342                    p_hwfn->abs_pf_id,
1343                    p_hwfn->num_funcs_on_engine);
1344 }
1345
1346 static int
1347 qed_get_hw_info(struct qed_hwfn *p_hwfn,
1348                 struct qed_ptt *p_ptt,
1349                 enum qed_pci_personality personality)
1350 {
1351         u32 port_mode;
1352         int rc;
1353
1354         /* Since all information is common, only first hwfns should do this */
1355         if (IS_LEAD_HWFN(p_hwfn)) {
1356                 rc = qed_iov_hw_info(p_hwfn);
1357                 if (rc)
1358                         return rc;
1359         }
1360
1361         /* Read the port mode */
1362         port_mode = qed_rd(p_hwfn, p_ptt,
1363                            CNIG_REG_NW_PORT_MODE_BB_B0);
1364
1365         if (port_mode < 3) {
1366                 p_hwfn->cdev->num_ports_in_engines = 1;
1367         } else if (port_mode <= 5) {
1368                 p_hwfn->cdev->num_ports_in_engines = 2;
1369         } else {
1370                 DP_NOTICE(p_hwfn, "PORT MODE: %d not supported\n",
1371                           p_hwfn->cdev->num_ports_in_engines);
1372
1373                 /* Default num_ports_in_engines to something */
1374                 p_hwfn->cdev->num_ports_in_engines = 1;
1375         }
1376
1377         qed_hw_get_nvm_info(p_hwfn, p_ptt);
1378
1379         rc = qed_int_igu_read_cam(p_hwfn, p_ptt);
1380         if (rc)
1381                 return rc;
1382
1383         if (qed_mcp_is_init(p_hwfn))
1384                 ether_addr_copy(p_hwfn->hw_info.hw_mac_addr,
1385                                 p_hwfn->mcp_info->func_info.mac);
1386         else
1387                 eth_random_addr(p_hwfn->hw_info.hw_mac_addr);
1388
1389         if (qed_mcp_is_init(p_hwfn)) {
1390                 if (p_hwfn->mcp_info->func_info.ovlan != QED_MCP_VLAN_UNSET)
1391                         p_hwfn->hw_info.ovlan =
1392                                 p_hwfn->mcp_info->func_info.ovlan;
1393
1394                 qed_mcp_cmd_port_init(p_hwfn, p_ptt);
1395         }
1396
1397         if (qed_mcp_is_init(p_hwfn)) {
1398                 enum qed_pci_personality protocol;
1399
1400                 protocol = p_hwfn->mcp_info->func_info.protocol;
1401                 p_hwfn->hw_info.personality = protocol;
1402         }
1403
1404         qed_get_num_funcs(p_hwfn, p_ptt);
1405
1406         qed_hw_get_resc(p_hwfn);
1407
1408         return rc;
1409 }
1410
1411 static int qed_get_dev_info(struct qed_dev *cdev)
1412 {
1413         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
1414         u32 tmp;
1415
1416         /* Read Vendor Id / Device Id */
1417         pci_read_config_word(cdev->pdev, PCI_VENDOR_ID,
1418                              &cdev->vendor_id);
1419         pci_read_config_word(cdev->pdev, PCI_DEVICE_ID,
1420                              &cdev->device_id);
1421         cdev->chip_num = (u16)qed_rd(p_hwfn, p_hwfn->p_main_ptt,
1422                                      MISCS_REG_CHIP_NUM);
1423         cdev->chip_rev = (u16)qed_rd(p_hwfn, p_hwfn->p_main_ptt,
1424                                      MISCS_REG_CHIP_REV);
1425         MASK_FIELD(CHIP_REV, cdev->chip_rev);
1426
1427         cdev->type = QED_DEV_TYPE_BB;
1428         /* Learn number of HW-functions */
1429         tmp = qed_rd(p_hwfn, p_hwfn->p_main_ptt,
1430                      MISCS_REG_CMT_ENABLED_FOR_PAIR);
1431
1432         if (tmp & (1 << p_hwfn->rel_pf_id)) {
1433                 DP_NOTICE(cdev->hwfns, "device in CMT mode\n");
1434                 cdev->num_hwfns = 2;
1435         } else {
1436                 cdev->num_hwfns = 1;
1437         }
1438
1439         cdev->chip_bond_id = qed_rd(p_hwfn, p_hwfn->p_main_ptt,
1440                                     MISCS_REG_CHIP_TEST_REG) >> 4;
1441         MASK_FIELD(CHIP_BOND_ID, cdev->chip_bond_id);
1442         cdev->chip_metal = (u16)qed_rd(p_hwfn, p_hwfn->p_main_ptt,
1443                                        MISCS_REG_CHIP_METAL);
1444         MASK_FIELD(CHIP_METAL, cdev->chip_metal);
1445
1446         DP_INFO(cdev->hwfns,
1447                 "Chip details - Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n",
1448                 cdev->chip_num, cdev->chip_rev,
1449                 cdev->chip_bond_id, cdev->chip_metal);
1450
1451         if (QED_IS_BB(cdev) && CHIP_REV_IS_A0(cdev)) {
1452                 DP_NOTICE(cdev->hwfns,
1453                           "The chip type/rev (BB A0) is not supported!\n");
1454                 return -EINVAL;
1455         }
1456
1457         return 0;
1458 }
1459
1460 static int qed_hw_prepare_single(struct qed_hwfn *p_hwfn,
1461                                  void __iomem *p_regview,
1462                                  void __iomem *p_doorbells,
1463                                  enum qed_pci_personality personality)
1464 {
1465         int rc = 0;
1466
1467         /* Split PCI bars evenly between hwfns */
1468         p_hwfn->regview = p_regview;
1469         p_hwfn->doorbells = p_doorbells;
1470
1471         if (IS_VF(p_hwfn->cdev))
1472                 return qed_vf_hw_prepare(p_hwfn);
1473
1474         /* Validate that chip access is feasible */
1475         if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
1476                 DP_ERR(p_hwfn,
1477                        "Reading the ME register returns all Fs; Preventing further chip access\n");
1478                 return -EINVAL;
1479         }
1480
1481         get_function_id(p_hwfn);
1482
1483         /* Allocate PTT pool */
1484         rc = qed_ptt_pool_alloc(p_hwfn);
1485         if (rc) {
1486                 DP_NOTICE(p_hwfn, "Failed to prepare hwfn's hw\n");
1487                 goto err0;
1488         }
1489
1490         /* Allocate the main PTT */
1491         p_hwfn->p_main_ptt = qed_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
1492
1493         /* First hwfn learns basic information, e.g., number of hwfns */
1494         if (!p_hwfn->my_id) {
1495                 rc = qed_get_dev_info(p_hwfn->cdev);
1496                 if (rc != 0)
1497                         goto err1;
1498         }
1499
1500         qed_hw_hwfn_prepare(p_hwfn);
1501
1502         /* Initialize MCP structure */
1503         rc = qed_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
1504         if (rc) {
1505                 DP_NOTICE(p_hwfn, "Failed initializing mcp command\n");
1506                 goto err1;
1507         }
1508
1509         /* Read the device configuration information from the HW and SHMEM */
1510         rc = qed_get_hw_info(p_hwfn, p_hwfn->p_main_ptt, personality);
1511         if (rc) {
1512                 DP_NOTICE(p_hwfn, "Failed to get HW information\n");
1513                 goto err2;
1514         }
1515
1516         /* Allocate the init RT array and initialize the init-ops engine */
1517         rc = qed_init_alloc(p_hwfn);
1518         if (rc) {
1519                 DP_NOTICE(p_hwfn, "Failed to allocate the init array\n");
1520                 goto err2;
1521         }
1522
1523         return rc;
1524 err2:
1525         if (IS_LEAD_HWFN(p_hwfn))
1526                 qed_iov_free_hw_info(p_hwfn->cdev);
1527         qed_mcp_free(p_hwfn);
1528 err1:
1529         qed_hw_hwfn_free(p_hwfn);
1530 err0:
1531         return rc;
1532 }
1533
1534 int qed_hw_prepare(struct qed_dev *cdev,
1535                    int personality)
1536 {
1537         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
1538         int rc;
1539
1540         /* Store the precompiled init data ptrs */
1541         if (IS_PF(cdev))
1542                 qed_init_iro_array(cdev);
1543
1544         /* Initialize the first hwfn - will learn number of hwfns */
1545         rc = qed_hw_prepare_single(p_hwfn,
1546                                    cdev->regview,
1547                                    cdev->doorbells, personality);
1548         if (rc)
1549                 return rc;
1550
1551         personality = p_hwfn->hw_info.personality;
1552
1553         /* Initialize the rest of the hwfns */
1554         if (cdev->num_hwfns > 1) {
1555                 void __iomem *p_regview, *p_doorbell;
1556                 u8 __iomem *addr;
1557
1558                 /* adjust bar offset for second engine */
1559                 addr = cdev->regview + qed_hw_bar_size(p_hwfn, BAR_ID_0) / 2;
1560                 p_regview = addr;
1561
1562                 /* adjust doorbell bar offset for second engine */
1563                 addr = cdev->doorbells + qed_hw_bar_size(p_hwfn, BAR_ID_1) / 2;
1564                 p_doorbell = addr;
1565
1566                 /* prepare second hw function */
1567                 rc = qed_hw_prepare_single(&cdev->hwfns[1], p_regview,
1568                                            p_doorbell, personality);
1569
1570                 /* in case of error, need to free the previously
1571                  * initiliazed hwfn 0.
1572                  */
1573                 if (rc) {
1574                         if (IS_PF(cdev)) {
1575                                 qed_init_free(p_hwfn);
1576                                 qed_mcp_free(p_hwfn);
1577                                 qed_hw_hwfn_free(p_hwfn);
1578                         }
1579                 }
1580         }
1581
1582         return rc;
1583 }
1584
1585 void qed_hw_remove(struct qed_dev *cdev)
1586 {
1587         int i;
1588
1589         for_each_hwfn(cdev, i) {
1590                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1591
1592                 if (IS_VF(cdev)) {
1593                         /* Will be implemented in a later patch */
1594                         continue;
1595                 }
1596
1597                 qed_init_free(p_hwfn);
1598                 qed_hw_hwfn_free(p_hwfn);
1599                 qed_mcp_free(p_hwfn);
1600         }
1601
1602         qed_iov_free_hw_info(cdev);
1603 }
1604
1605 int qed_chain_alloc(struct qed_dev *cdev,
1606                     enum qed_chain_use_mode intended_use,
1607                     enum qed_chain_mode mode,
1608                     u16 num_elems,
1609                     size_t elem_size,
1610                     struct qed_chain *p_chain)
1611 {
1612         dma_addr_t p_pbl_phys = 0;
1613         void *p_pbl_virt = NULL;
1614         dma_addr_t p_phys = 0;
1615         void *p_virt = NULL;
1616         u16 page_cnt = 0;
1617         size_t size;
1618
1619         if (mode == QED_CHAIN_MODE_SINGLE)
1620                 page_cnt = 1;
1621         else
1622                 page_cnt = QED_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
1623
1624         size = page_cnt * QED_CHAIN_PAGE_SIZE;
1625         p_virt = dma_alloc_coherent(&cdev->pdev->dev,
1626                                     size, &p_phys, GFP_KERNEL);
1627         if (!p_virt) {
1628                 DP_NOTICE(cdev, "Failed to allocate chain mem\n");
1629                 goto nomem;
1630         }
1631
1632         if (mode == QED_CHAIN_MODE_PBL) {
1633                 size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE;
1634                 p_pbl_virt = dma_alloc_coherent(&cdev->pdev->dev,
1635                                                 size, &p_pbl_phys,
1636                                                 GFP_KERNEL);
1637                 if (!p_pbl_virt) {
1638                         DP_NOTICE(cdev, "Failed to allocate chain pbl mem\n");
1639                         goto nomem;
1640                 }
1641
1642                 qed_chain_pbl_init(p_chain, p_virt, p_phys, page_cnt,
1643                                    (u8)elem_size, intended_use,
1644                                    p_pbl_phys, p_pbl_virt);
1645         } else {
1646                 qed_chain_init(p_chain, p_virt, p_phys, page_cnt,
1647                                (u8)elem_size, intended_use, mode);
1648         }
1649
1650         return 0;
1651
1652 nomem:
1653         dma_free_coherent(&cdev->pdev->dev,
1654                           page_cnt * QED_CHAIN_PAGE_SIZE,
1655                           p_virt, p_phys);
1656         dma_free_coherent(&cdev->pdev->dev,
1657                           page_cnt * QED_CHAIN_PBL_ENTRY_SIZE,
1658                           p_pbl_virt, p_pbl_phys);
1659
1660         return -ENOMEM;
1661 }
1662
1663 void qed_chain_free(struct qed_dev *cdev,
1664                     struct qed_chain *p_chain)
1665 {
1666         size_t size;
1667
1668         if (!p_chain->p_virt_addr)
1669                 return;
1670
1671         if (p_chain->mode == QED_CHAIN_MODE_PBL) {
1672                 size = p_chain->page_cnt * QED_CHAIN_PBL_ENTRY_SIZE;
1673                 dma_free_coherent(&cdev->pdev->dev, size,
1674                                   p_chain->pbl.p_virt_table,
1675                                   p_chain->pbl.p_phys_table);
1676         }
1677
1678         size = p_chain->page_cnt * QED_CHAIN_PAGE_SIZE;
1679         dma_free_coherent(&cdev->pdev->dev, size,
1680                           p_chain->p_virt_addr,
1681                           p_chain->p_phys_addr);
1682 }
1683
1684 int qed_fw_l2_queue(struct qed_hwfn *p_hwfn,
1685                     u16 src_id, u16 *dst_id)
1686 {
1687         if (src_id >= RESC_NUM(p_hwfn, QED_L2_QUEUE)) {
1688                 u16 min, max;
1689
1690                 min = (u16)RESC_START(p_hwfn, QED_L2_QUEUE);
1691                 max = min + RESC_NUM(p_hwfn, QED_L2_QUEUE);
1692                 DP_NOTICE(p_hwfn,
1693                           "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
1694                           src_id, min, max);
1695
1696                 return -EINVAL;
1697         }
1698
1699         *dst_id = RESC_START(p_hwfn, QED_L2_QUEUE) + src_id;
1700
1701         return 0;
1702 }
1703
1704 int qed_fw_vport(struct qed_hwfn *p_hwfn,
1705                  u8 src_id, u8 *dst_id)
1706 {
1707         if (src_id >= RESC_NUM(p_hwfn, QED_VPORT)) {
1708                 u8 min, max;
1709
1710                 min = (u8)RESC_START(p_hwfn, QED_VPORT);
1711                 max = min + RESC_NUM(p_hwfn, QED_VPORT);
1712                 DP_NOTICE(p_hwfn,
1713                           "vport id [%d] is not valid, available indices [%d - %d]\n",
1714                           src_id, min, max);
1715
1716                 return -EINVAL;
1717         }
1718
1719         *dst_id = RESC_START(p_hwfn, QED_VPORT) + src_id;
1720
1721         return 0;
1722 }
1723
1724 int qed_fw_rss_eng(struct qed_hwfn *p_hwfn,
1725                    u8 src_id, u8 *dst_id)
1726 {
1727         if (src_id >= RESC_NUM(p_hwfn, QED_RSS_ENG)) {
1728                 u8 min, max;
1729
1730                 min = (u8)RESC_START(p_hwfn, QED_RSS_ENG);
1731                 max = min + RESC_NUM(p_hwfn, QED_RSS_ENG);
1732                 DP_NOTICE(p_hwfn,
1733                           "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
1734                           src_id, min, max);
1735
1736                 return -EINVAL;
1737         }
1738
1739         *dst_id = RESC_START(p_hwfn, QED_RSS_ENG) + src_id;
1740
1741         return 0;
1742 }
1743
1744 /* Calculate final WFQ values for all vports and configure them.
1745  * After this configuration each vport will have
1746  * approx min rate =  min_pf_rate * (vport_wfq / QED_WFQ_UNIT)
1747  */
1748 static void qed_configure_wfq_for_all_vports(struct qed_hwfn *p_hwfn,
1749                                              struct qed_ptt *p_ptt,
1750                                              u32 min_pf_rate)
1751 {
1752         struct init_qm_vport_params *vport_params;
1753         int i;
1754
1755         vport_params = p_hwfn->qm_info.qm_vport_params;
1756
1757         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
1758                 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
1759
1760                 vport_params[i].vport_wfq = (wfq_speed * QED_WFQ_UNIT) /
1761                                                 min_pf_rate;
1762                 qed_init_vport_wfq(p_hwfn, p_ptt,
1763                                    vport_params[i].first_tx_pq_id,
1764                                    vport_params[i].vport_wfq);
1765         }
1766 }
1767
1768 static void qed_init_wfq_default_param(struct qed_hwfn *p_hwfn,
1769                                        u32 min_pf_rate)
1770
1771 {
1772         int i;
1773
1774         for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
1775                 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
1776 }
1777
1778 static void qed_disable_wfq_for_all_vports(struct qed_hwfn *p_hwfn,
1779                                            struct qed_ptt *p_ptt,
1780                                            u32 min_pf_rate)
1781 {
1782         struct init_qm_vport_params *vport_params;
1783         int i;
1784
1785         vport_params = p_hwfn->qm_info.qm_vport_params;
1786
1787         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
1788                 qed_init_wfq_default_param(p_hwfn, min_pf_rate);
1789                 qed_init_vport_wfq(p_hwfn, p_ptt,
1790                                    vport_params[i].first_tx_pq_id,
1791                                    vport_params[i].vport_wfq);
1792         }
1793 }
1794
1795 /* This function performs several validations for WFQ
1796  * configuration and required min rate for a given vport
1797  * 1. req_rate must be greater than one percent of min_pf_rate.
1798  * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
1799  *    rates to get less than one percent of min_pf_rate.
1800  * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
1801  */
1802 static int qed_init_wfq_param(struct qed_hwfn *p_hwfn,
1803                               u16 vport_id, u32 req_rate,
1804                               u32 min_pf_rate)
1805 {
1806         u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
1807         int non_requested_count = 0, req_count = 0, i, num_vports;
1808
1809         num_vports = p_hwfn->qm_info.num_vports;
1810
1811         /* Accounting for the vports which are configured for WFQ explicitly */
1812         for (i = 0; i < num_vports; i++) {
1813                 u32 tmp_speed;
1814
1815                 if ((i != vport_id) &&
1816                     p_hwfn->qm_info.wfq_data[i].configured) {
1817                         req_count++;
1818                         tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
1819                         total_req_min_rate += tmp_speed;
1820                 }
1821         }
1822
1823         /* Include current vport data as well */
1824         req_count++;
1825         total_req_min_rate += req_rate;
1826         non_requested_count = num_vports - req_count;
1827
1828         if (req_rate < min_pf_rate / QED_WFQ_UNIT) {
1829                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
1830                            "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
1831                            vport_id, req_rate, min_pf_rate);
1832                 return -EINVAL;
1833         }
1834
1835         if (num_vports > QED_WFQ_UNIT) {
1836                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
1837                            "Number of vports is greater than %d\n",
1838                            QED_WFQ_UNIT);
1839                 return -EINVAL;
1840         }
1841
1842         if (total_req_min_rate > min_pf_rate) {
1843                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
1844                            "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
1845                            total_req_min_rate, min_pf_rate);
1846                 return -EINVAL;
1847         }
1848
1849         total_left_rate = min_pf_rate - total_req_min_rate;
1850
1851         left_rate_per_vp = total_left_rate / non_requested_count;
1852         if (left_rate_per_vp <  min_pf_rate / QED_WFQ_UNIT) {
1853                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
1854                            "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
1855                            left_rate_per_vp, min_pf_rate);
1856                 return -EINVAL;
1857         }
1858
1859         p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
1860         p_hwfn->qm_info.wfq_data[vport_id].configured = true;
1861
1862         for (i = 0; i < num_vports; i++) {
1863                 if (p_hwfn->qm_info.wfq_data[i].configured)
1864                         continue;
1865
1866                 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
1867         }
1868
1869         return 0;
1870 }
1871
1872 static int __qed_configure_vp_wfq_on_link_change(struct qed_hwfn *p_hwfn,
1873                                                  struct qed_ptt *p_ptt,
1874                                                  u32 min_pf_rate)
1875 {
1876         bool use_wfq = false;
1877         int rc = 0;
1878         u16 i;
1879
1880         /* Validate all pre configured vports for wfq */
1881         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
1882                 u32 rate;
1883
1884                 if (!p_hwfn->qm_info.wfq_data[i].configured)
1885                         continue;
1886
1887                 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
1888                 use_wfq = true;
1889
1890                 rc = qed_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
1891                 if (rc) {
1892                         DP_NOTICE(p_hwfn,
1893                                   "WFQ validation failed while configuring min rate\n");
1894                         break;
1895                 }
1896         }
1897
1898         if (!rc && use_wfq)
1899                 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
1900         else
1901                 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
1902
1903         return rc;
1904 }
1905
1906 /* API to configure WFQ from mcp link change */
1907 void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev, u32 min_pf_rate)
1908 {
1909         int i;
1910
1911         for_each_hwfn(cdev, i) {
1912                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1913
1914                 __qed_configure_vp_wfq_on_link_change(p_hwfn,
1915                                                       p_hwfn->p_dpc_ptt,
1916                                                       min_pf_rate);
1917         }
1918 }
1919
1920 int __qed_configure_pf_max_bandwidth(struct qed_hwfn *p_hwfn,
1921                                      struct qed_ptt *p_ptt,
1922                                      struct qed_mcp_link_state *p_link,
1923                                      u8 max_bw)
1924 {
1925         int rc = 0;
1926
1927         p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
1928
1929         if (!p_link->line_speed && (max_bw != 100))
1930                 return rc;
1931
1932         p_link->speed = (p_link->line_speed * max_bw) / 100;
1933         p_hwfn->qm_info.pf_rl = p_link->speed;
1934
1935         /* Since the limiter also affects Tx-switched traffic, we don't want it
1936          * to limit such traffic in case there's no actual limit.
1937          * In that case, set limit to imaginary high boundary.
1938          */
1939         if (max_bw == 100)
1940                 p_hwfn->qm_info.pf_rl = 100000;
1941
1942         rc = qed_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
1943                             p_hwfn->qm_info.pf_rl);
1944
1945         DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
1946                    "Configured MAX bandwidth to be %08x Mb/sec\n",
1947                    p_link->speed);
1948
1949         return rc;
1950 }
1951
1952 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
1953 int qed_configure_pf_max_bandwidth(struct qed_dev *cdev, u8 max_bw)
1954 {
1955         int i, rc = -EINVAL;
1956
1957         if (max_bw < 1 || max_bw > 100) {
1958                 DP_NOTICE(cdev, "PF max bw valid range is [1-100]\n");
1959                 return rc;
1960         }
1961
1962         for_each_hwfn(cdev, i) {
1963                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1964                 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev);
1965                 struct qed_mcp_link_state *p_link;
1966                 struct qed_ptt *p_ptt;
1967
1968                 p_link = &p_lead->mcp_info->link_output;
1969
1970                 p_ptt = qed_ptt_acquire(p_hwfn);
1971                 if (!p_ptt)
1972                         return -EBUSY;
1973
1974                 rc = __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt,
1975                                                       p_link, max_bw);
1976
1977                 qed_ptt_release(p_hwfn, p_ptt);
1978
1979                 if (rc)
1980                         break;
1981         }
1982
1983         return rc;
1984 }
1985
1986 int __qed_configure_pf_min_bandwidth(struct qed_hwfn *p_hwfn,
1987                                      struct qed_ptt *p_ptt,
1988                                      struct qed_mcp_link_state *p_link,
1989                                      u8 min_bw)
1990 {
1991         int rc = 0;
1992
1993         p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
1994         p_hwfn->qm_info.pf_wfq = min_bw;
1995
1996         if (!p_link->line_speed)
1997                 return rc;
1998
1999         p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
2000
2001         rc = qed_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
2002
2003         DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
2004                    "Configured MIN bandwidth to be %d Mb/sec\n",
2005                    p_link->min_pf_rate);
2006
2007         return rc;
2008 }
2009
2010 /* Main API to configure PF min bandwidth where bw range is [1-100] */
2011 int qed_configure_pf_min_bandwidth(struct qed_dev *cdev, u8 min_bw)
2012 {
2013         int i, rc = -EINVAL;
2014
2015         if (min_bw < 1 || min_bw > 100) {
2016                 DP_NOTICE(cdev, "PF min bw valid range is [1-100]\n");
2017                 return rc;
2018         }
2019
2020         for_each_hwfn(cdev, i) {
2021                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2022                 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev);
2023                 struct qed_mcp_link_state *p_link;
2024                 struct qed_ptt *p_ptt;
2025
2026                 p_link = &p_lead->mcp_info->link_output;
2027
2028                 p_ptt = qed_ptt_acquire(p_hwfn);
2029                 if (!p_ptt)
2030                         return -EBUSY;
2031
2032                 rc = __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt,
2033                                                       p_link, min_bw);
2034                 if (rc) {
2035                         qed_ptt_release(p_hwfn, p_ptt);
2036                         return rc;
2037                 }
2038
2039                 if (p_link->min_pf_rate) {
2040                         u32 min_rate = p_link->min_pf_rate;
2041
2042                         rc = __qed_configure_vp_wfq_on_link_change(p_hwfn,
2043                                                                    p_ptt,
2044                                                                    min_rate);
2045                 }
2046
2047                 qed_ptt_release(p_hwfn, p_ptt);
2048         }
2049
2050         return rc;
2051 }