drivers/net/ethernet/qlogic/qed/qed_dev.c

   1 /* QLogic qed NIC Driver
   2  * Copyright (c) 2015-2017  QLogic Corporation
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and /or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/types.h>
  34 #include <asm/byteorder.h>
  35 #include <linux/io.h>
  36 #include <linux/delay.h>
  37 #include <linux/dma-mapping.h>
  38 #include <linux/errno.h>
  39 #include <linux/kernel.h>
  40 #include <linux/mutex.h>
  41 #include <linux/pci.h>
  42 #include <linux/slab.h>
  43 #include <linux/string.h>
  44 #include <linux/vmalloc.h>
  45 #include <linux/etherdevice.h>
  46 #include <linux/qed/qed_chain.h>
  47 #include <linux/qed/qed_if.h>
  48 #include "qed.h"
  49 #include "qed_cxt.h"
  50 #include "qed_dcbx.h"
  51 #include "qed_dev_api.h"
  52 #include "qed_fcoe.h"
  53 #include "qed_hsi.h"
  54 #include "qed_hw.h"
  55 #include "qed_init_ops.h"
  56 #include "qed_int.h"
  57 #include "qed_iscsi.h"
  58 #include "qed_ll2.h"
  59 #include "qed_mcp.h"
  60 #include "qed_ooo.h"
  61 #include "qed_reg_addr.h"
  62 #include "qed_sp.h"
  63 #include "qed_sriov.h"
  64 #include "qed_vf.h"
  65 #include "qed_rdma.h"
  66
  67 static DEFINE_SPINLOCK(qm_lock);
  68
  69 /******************** Doorbell Recovery *******************/
  70 /* The doorbell recovery mechanism consists of a list of entries which represent
  71  * doorbelling entities (l2 queues, roce sq/rq/cqs, the slowpath spq, etc). Each
  72  * entity needs to register with the mechanism and provide the parameters
  73  * describing it's doorbell, including a location where last used doorbell data
  74  * can be found. The doorbell execute function will traverse the list and
  75  * doorbell all of the registered entries.
  76  */
  77 struct qed_db_recovery_entry {
  78         struct list_head list_entry;
  79         void __iomem *db_addr;
  80         void *db_data;
  81         enum qed_db_rec_width db_width;
  82         enum qed_db_rec_space db_space;
  83         u8 hwfn_idx;
  84 };
  85
  86 /* Display a single doorbell recovery entry */
  87 static void qed_db_recovery_dp_entry(struct qed_hwfn *p_hwfn,
  88                                      struct qed_db_recovery_entry *db_entry,
  89                                      char *action)
  90 {
  91         DP_VERBOSE(p_hwfn,
  92                    QED_MSG_SPQ,
  93                    "(%s: db_entry %p, addr %p, data %p, width %s, %s space, hwfn %d)\n",
  94                    action,
  95                    db_entry,
  96                    db_entry->db_addr,
  97                    db_entry->db_data,
  98                    db_entry->db_width == DB_REC_WIDTH_32B ? "32b" : "64b",
  99                    db_entry->db_space == DB_REC_USER ? "user" : "kernel",
 100                    db_entry->hwfn_idx);
 101 }
 102
 103 /* Doorbell address sanity (address within doorbell bar range) */
 104 static bool qed_db_rec_sanity(struct qed_dev *cdev,
 105                               void __iomem *db_addr,
 106                               enum qed_db_rec_width db_width,
 107                               void *db_data)
 108 {
 109         u32 width = (db_width == DB_REC_WIDTH_32B) ? 32 : 64;
 110
 111         /* Make sure doorbell address is within the doorbell bar */
 112         if (db_addr < cdev->doorbells ||
 113             (u8 __iomem *)db_addr + width >
 114             (u8 __iomem *)cdev->doorbells + cdev->db_size) {
 115                 WARN(true,
 116                      "Illegal doorbell address: %p. Legal range for doorbell addresses is [%p..%p]\n",
 117                      db_addr,
 118                      cdev->doorbells,
 119                      (u8 __iomem *)cdev->doorbells + cdev->db_size);
 120                 return false;
 121         }
 122
 123         /* ake sure doorbell data pointer is not null */
 124         if (!db_data) {
 125                 WARN(true, "Illegal doorbell data pointer: %p", db_data);
 126                 return false;
 127         }
 128
 129         return true;
 130 }
 131
 132 /* Find hwfn according to the doorbell address */
 133 static struct qed_hwfn *qed_db_rec_find_hwfn(struct qed_dev *cdev,
 134                                              void __iomem *db_addr)
 135 {
 136         struct qed_hwfn *p_hwfn;
 137
 138         /* In CMT doorbell bar is split down the middle between engine 0 and enigne 1 */
 139         if (cdev->num_hwfns > 1)
 140                 p_hwfn = db_addr < cdev->hwfns[1].doorbells ?
 141                     &cdev->hwfns[0] : &cdev->hwfns[1];
 142         else
 143                 p_hwfn = QED_LEADING_HWFN(cdev);
 144
 145         return p_hwfn;
 146 }
 147
 148 /* Add a new entry to the doorbell recovery mechanism */
 149 int qed_db_recovery_add(struct qed_dev *cdev,
 150                         void __iomem *db_addr,
 151                         void *db_data,
 152                         enum qed_db_rec_width db_width,
 153                         enum qed_db_rec_space db_space)
 154 {
 155         struct qed_db_recovery_entry *db_entry;
 156         struct qed_hwfn *p_hwfn;
 157
 158         /* Shortcircuit VFs, for now */
 159         if (IS_VF(cdev)) {
 160                 DP_VERBOSE(cdev,
 161                            QED_MSG_IOV, "db recovery - skipping VF doorbell\n");
 162                 return 0;
 163         }
 164
 165         /* Sanitize doorbell address */
 166         if (!qed_db_rec_sanity(cdev, db_addr, db_width, db_data))
 167                 return -EINVAL;
 168
 169         /* Obtain hwfn from doorbell address */
 170         p_hwfn = qed_db_rec_find_hwfn(cdev, db_addr);
 171
 172         /* Create entry */
 173         db_entry = kzalloc(sizeof(*db_entry), GFP_KERNEL);
 174         if (!db_entry) {
 175                 DP_NOTICE(cdev, "Failed to allocate a db recovery entry\n");
 176                 return -ENOMEM;
 177         }
 178
 179         /* Populate entry */
 180         db_entry->db_addr = db_addr;
 181         db_entry->db_data = db_data;
 182         db_entry->db_width = db_width;
 183         db_entry->db_space = db_space;
 184         db_entry->hwfn_idx = p_hwfn->my_id;
 185
 186         /* Display */
 187         qed_db_recovery_dp_entry(p_hwfn, db_entry, "Adding");
 188
 189         /* Protect the list */
 190         spin_lock_bh(&p_hwfn->db_recovery_info.lock);
 191         list_add_tail(&db_entry->list_entry, &p_hwfn->db_recovery_info.list);
 192         spin_unlock_bh(&p_hwfn->db_recovery_info.lock);
 193
 194         return 0;
 195 }
 196
 197 /* Remove an entry from the doorbell recovery mechanism */
 198 int qed_db_recovery_del(struct qed_dev *cdev,
 199                         void __iomem *db_addr, void *db_data)
 200 {
 201         struct qed_db_recovery_entry *db_entry = NULL;
 202         struct qed_hwfn *p_hwfn;
 203         int rc = -EINVAL;
 204
 205         /* Shortcircuit VFs, for now */
 206         if (IS_VF(cdev)) {
 207                 DP_VERBOSE(cdev,
 208                            QED_MSG_IOV, "db recovery - skipping VF doorbell\n");
 209                 return 0;
 210         }
 211
 212         /* Obtain hwfn from doorbell address */
 213         p_hwfn = qed_db_rec_find_hwfn(cdev, db_addr);
 214
 215         /* Protect the list */
 216         spin_lock_bh(&p_hwfn->db_recovery_info.lock);
 217         list_for_each_entry(db_entry,
 218                             &p_hwfn->db_recovery_info.list, list_entry) {
 219                 /* search according to db_data addr since db_addr is not unique (roce) */
 220                 if (db_entry->db_data == db_data) {
 221                         qed_db_recovery_dp_entry(p_hwfn, db_entry, "Deleting");
 222                         list_del(&db_entry->list_entry);
 223                         rc = 0;
 224                         break;
 225                 }
 226         }
 227
 228         spin_unlock_bh(&p_hwfn->db_recovery_info.lock);
 229
 230         if (rc == -EINVAL)
 231
 232                 DP_NOTICE(p_hwfn,
 233                           "Failed to find element in list. Key (db_data addr) was %p. db_addr was %p\n",
 234                           db_data, db_addr);
 235         else
 236                 kfree(db_entry);
 237
 238         return rc;
 239 }
 240
 241 /* Initialize the doorbell recovery mechanism */
 242 static int qed_db_recovery_setup(struct qed_hwfn *p_hwfn)
 243 {
 244         DP_VERBOSE(p_hwfn, QED_MSG_SPQ, "Setting up db recovery\n");
 245
 246         /* Make sure db_size was set in cdev */
 247         if (!p_hwfn->cdev->db_size) {
 248                 DP_ERR(p_hwfn->cdev, "db_size not set\n");
 249                 return -EINVAL;
 250         }
 251
 252         INIT_LIST_HEAD(&p_hwfn->db_recovery_info.list);
 253         spin_lock_init(&p_hwfn->db_recovery_info.lock);
 254         p_hwfn->db_recovery_info.db_recovery_counter = 0;
 255
 256         return 0;
 257 }
 258
 259 /* Destroy the doorbell recovery mechanism */
 260 static void qed_db_recovery_teardown(struct qed_hwfn *p_hwfn)
 261 {
 262         struct qed_db_recovery_entry *db_entry = NULL;
 263
 264         DP_VERBOSE(p_hwfn, QED_MSG_SPQ, "Tearing down db recovery\n");
 265         if (!list_empty(&p_hwfn->db_recovery_info.list)) {
 266                 DP_VERBOSE(p_hwfn,
 267                            QED_MSG_SPQ,
 268                            "Doorbell Recovery teardown found the doorbell recovery list was not empty (Expected in disorderly driver unload (e.g. recovery) otherwise this probably means some flow forgot to db_recovery_del). Prepare to purge doorbell recovery list...\n");
 269                 while (!list_empty(&p_hwfn->db_recovery_info.list)) {
 270                         db_entry =
 271                             list_first_entry(&p_hwfn->db_recovery_info.list,
 272                                              struct qed_db_recovery_entry,
 273                                              list_entry);
 274                         qed_db_recovery_dp_entry(p_hwfn, db_entry, "Purging");
 275                         list_del(&db_entry->list_entry);
 276                         kfree(db_entry);
 277                 }
 278         }
 279         p_hwfn->db_recovery_info.db_recovery_counter = 0;
 280 }
 281
 282 /* Print the content of the doorbell recovery mechanism */
 283 void qed_db_recovery_dp(struct qed_hwfn *p_hwfn)
 284 {
 285         struct qed_db_recovery_entry *db_entry = NULL;
 286
 287         DP_NOTICE(p_hwfn,
 288                   "Displaying doorbell recovery database. Counter was %d\n",
 289                   p_hwfn->db_recovery_info.db_recovery_counter);
 290
 291         /* Protect the list */
 292         spin_lock_bh(&p_hwfn->db_recovery_info.lock);
 293         list_for_each_entry(db_entry,
 294                             &p_hwfn->db_recovery_info.list, list_entry) {
 295                 qed_db_recovery_dp_entry(p_hwfn, db_entry, "Printing");
 296         }
 297
 298         spin_unlock_bh(&p_hwfn->db_recovery_info.lock);
 299 }
 300
 301 /* Ring the doorbell of a single doorbell recovery entry */
 302 static void qed_db_recovery_ring(struct qed_hwfn *p_hwfn,
 303                                  struct qed_db_recovery_entry *db_entry)
 304 {
 305         /* Print according to width */
 306         if (db_entry->db_width == DB_REC_WIDTH_32B) {
 307                 DP_VERBOSE(p_hwfn, QED_MSG_SPQ,
 308                            "ringing doorbell address %p data %x\n",
 309                            db_entry->db_addr,
 310                            *(u32 *)db_entry->db_data);
 311         } else {
 312                 DP_VERBOSE(p_hwfn, QED_MSG_SPQ,
 313                            "ringing doorbell address %p data %llx\n",
 314                            db_entry->db_addr,
 315                            *(u64 *)(db_entry->db_data));
 316         }
 317
 318         /* Sanity */
 319         if (!qed_db_rec_sanity(p_hwfn->cdev, db_entry->db_addr,
 320                                db_entry->db_width, db_entry->db_data))
 321                 return;
 322
 323         /* Flush the write combined buffer. Since there are multiple doorbelling
 324          * entities using the same address, if we don't flush, a transaction
 325          * could be lost.
 326          */
 327         wmb();
 328
 329         /* Ring the doorbell */
 330         if (db_entry->db_width == DB_REC_WIDTH_32B)
 331                 DIRECT_REG_WR(db_entry->db_addr,
 332                               *(u32 *)(db_entry->db_data));
 333         else
 334                 DIRECT_REG_WR64(db_entry->db_addr,
 335                                 *(u64 *)(db_entry->db_data));
 336
 337         /* Flush the write combined buffer. Next doorbell may come from a
 338          * different entity to the same address...
 339          */
 340         wmb();
 341 }
 342
 343 /* Traverse the doorbell recovery entry list and ring all the doorbells */
 344 void qed_db_recovery_execute(struct qed_hwfn *p_hwfn)
 345 {
 346         struct qed_db_recovery_entry *db_entry = NULL;
 347
 348         DP_NOTICE(p_hwfn, "Executing doorbell recovery. Counter was %d\n",
 349                   p_hwfn->db_recovery_info.db_recovery_counter);
 350
 351         /* Track amount of times recovery was executed */
 352         p_hwfn->db_recovery_info.db_recovery_counter++;
 353
 354         /* Protect the list */
 355         spin_lock_bh(&p_hwfn->db_recovery_info.lock);
 356         list_for_each_entry(db_entry,
 357                             &p_hwfn->db_recovery_info.list, list_entry)
 358                 qed_db_recovery_ring(p_hwfn, db_entry);
 359         spin_unlock_bh(&p_hwfn->db_recovery_info.lock);
 360 }
 361
 362 /******************** Doorbell Recovery end ****************/
 363
 364 /********************************** NIG LLH ***********************************/
 365
 366 enum qed_llh_filter_type {
 367         QED_LLH_FILTER_TYPE_MAC,
 368         QED_LLH_FILTER_TYPE_PROTOCOL,
 369 };
 370
 371 struct qed_llh_mac_filter {
 372         u8 addr[ETH_ALEN];
 373 };
 374
 375 struct qed_llh_protocol_filter {
 376         enum qed_llh_prot_filter_type_t type;
 377         u16 source_port_or_eth_type;
 378         u16 dest_port;
 379 };
 380
 381 union qed_llh_filter {
 382         struct qed_llh_mac_filter mac;
 383         struct qed_llh_protocol_filter protocol;
 384 };
 385
 386 struct qed_llh_filter_info {
 387         bool b_enabled;
 388         u32 ref_cnt;
 389         enum qed_llh_filter_type type;
 390         union qed_llh_filter filter;
 391 };
 392
 393 struct qed_llh_info {
 394         /* Number of LLH filters banks */
 395         u8 num_ppfid;
 396
 397 #define MAX_NUM_PPFID   8
 398         u8 ppfid_array[MAX_NUM_PPFID];
 399
 400         /* Array of filters arrays:
 401          * "num_ppfid" elements of filters banks, where each is an array of
 402          * "NIG_REG_LLH_FUNC_FILTER_EN_SIZE" filters.
 403          */
 404         struct qed_llh_filter_info **pp_filters;
 405 };
 406
 407 static void qed_llh_free(struct qed_dev *cdev)
 408 {
 409         struct qed_llh_info *p_llh_info = cdev->p_llh_info;
 410         u32 i;
 411
 412         if (p_llh_info) {
 413                 if (p_llh_info->pp_filters)
 414                         for (i = 0; i < p_llh_info->num_ppfid; i++)
 415                                 kfree(p_llh_info->pp_filters[i]);
 416
 417                 kfree(p_llh_info->pp_filters);
 418         }
 419
 420         kfree(p_llh_info);
 421         cdev->p_llh_info = NULL;
 422 }
 423
 424 static int qed_llh_alloc(struct qed_dev *cdev)
 425 {
 426         struct qed_llh_info *p_llh_info;
 427         u32 size, i;
 428
 429         p_llh_info = kzalloc(sizeof(*p_llh_info), GFP_KERNEL);
 430         if (!p_llh_info)
 431                 return -ENOMEM;
 432         cdev->p_llh_info = p_llh_info;
 433
 434         for (i = 0; i < MAX_NUM_PPFID; i++) {
 435                 if (!(cdev->ppfid_bitmap & (0x1 << i)))
 436                         continue;
 437
 438                 p_llh_info->ppfid_array[p_llh_info->num_ppfid] = i;
 439                 DP_VERBOSE(cdev, QED_MSG_SP, "ppfid_array[%d] = %hhd\n",
 440                            p_llh_info->num_ppfid, i);
 441                 p_llh_info->num_ppfid++;
 442         }
 443
 444         size = p_llh_info->num_ppfid * sizeof(*p_llh_info->pp_filters);
 445         p_llh_info->pp_filters = kzalloc(size, GFP_KERNEL);
 446         if (!p_llh_info->pp_filters)
 447                 return -ENOMEM;
 448
 449         size = NIG_REG_LLH_FUNC_FILTER_EN_SIZE *
 450             sizeof(**p_llh_info->pp_filters);
 451         for (i = 0; i < p_llh_info->num_ppfid; i++) {
 452                 p_llh_info->pp_filters[i] = kzalloc(size, GFP_KERNEL);
 453                 if (!p_llh_info->pp_filters[i])
 454                         return -ENOMEM;
 455         }
 456
 457         return 0;
 458 }
 459
 460 static int qed_llh_shadow_sanity(struct qed_dev *cdev,
 461                                  u8 ppfid, u8 filter_idx, const char *action)
 462 {
 463         struct qed_llh_info *p_llh_info = cdev->p_llh_info;
 464
 465         if (ppfid >= p_llh_info->num_ppfid) {
 466                 DP_NOTICE(cdev,
 467                           "LLH shadow [%s]: using ppfid %d while only %d ppfids are available\n",
 468                           action, ppfid, p_llh_info->num_ppfid);
 469                 return -EINVAL;
 470         }
 471
 472         if (filter_idx >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
 473                 DP_NOTICE(cdev,
 474                           "LLH shadow [%s]: using filter_idx %d while only %d filters are available\n",
 475                           action, filter_idx, NIG_REG_LLH_FUNC_FILTER_EN_SIZE);
 476                 return -EINVAL;
 477         }
 478
 479         return 0;
 480 }
 481
 482 #define QED_LLH_INVALID_FILTER_IDX      0xff
 483
 484 static int
 485 qed_llh_shadow_search_filter(struct qed_dev *cdev,
 486                              u8 ppfid,
 487                              union qed_llh_filter *p_filter, u8 *p_filter_idx)
 488 {
 489         struct qed_llh_info *p_llh_info = cdev->p_llh_info;
 490         struct qed_llh_filter_info *p_filters;
 491         int rc;
 492         u8 i;
 493
 494         rc = qed_llh_shadow_sanity(cdev, ppfid, 0, "search");
 495         if (rc)
 496                 return rc;
 497
 498         *p_filter_idx = QED_LLH_INVALID_FILTER_IDX;
 499
 500         p_filters = p_llh_info->pp_filters[ppfid];
 501         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
 502                 if (!memcmp(p_filter, &p_filters[i].filter,
 503                             sizeof(*p_filter))) {
 504                         *p_filter_idx = i;
 505                         break;
 506                 }
 507         }
 508
 509         return 0;
 510 }
 511
 512 static int
 513 qed_llh_shadow_get_free_idx(struct qed_dev *cdev, u8 ppfid, u8 *p_filter_idx)
 514 {
 515         struct qed_llh_info *p_llh_info = cdev->p_llh_info;
 516         struct qed_llh_filter_info *p_filters;
 517         int rc;
 518         u8 i;
 519
 520         rc = qed_llh_shadow_sanity(cdev, ppfid, 0, "get_free_idx");
 521         if (rc)
 522                 return rc;
 523
 524         *p_filter_idx = QED_LLH_INVALID_FILTER_IDX;
 525
 526         p_filters = p_llh_info->pp_filters[ppfid];
 527         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
 528                 if (!p_filters[i].b_enabled) {
 529                         *p_filter_idx = i;
 530                         break;
 531                 }
 532         }
 533
 534         return 0;
 535 }
 536
 537 static int
 538 __qed_llh_shadow_add_filter(struct qed_dev *cdev,
 539                             u8 ppfid,
 540                             u8 filter_idx,
 541                             enum qed_llh_filter_type type,
 542                             union qed_llh_filter *p_filter, u32 *p_ref_cnt)
 543 {
 544         struct qed_llh_info *p_llh_info = cdev->p_llh_info;
 545         struct qed_llh_filter_info *p_filters;
 546         int rc;
 547
 548         rc = qed_llh_shadow_sanity(cdev, ppfid, filter_idx, "add");
 549         if (rc)
 550                 return rc;
 551
 552         p_filters = p_llh_info->pp_filters[ppfid];
 553         if (!p_filters[filter_idx].ref_cnt) {
 554                 p_filters[filter_idx].b_enabled = true;
 555                 p_filters[filter_idx].type = type;
 556                 memcpy(&p_filters[filter_idx].filter, p_filter,
 557                        sizeof(p_filters[filter_idx].filter));
 558         }
 559
 560         *p_ref_cnt = ++p_filters[filter_idx].ref_cnt;
 561
 562         return 0;
 563 }
 564
 565 static int
 566 qed_llh_shadow_add_filter(struct qed_dev *cdev,
 567                           u8 ppfid,
 568                           enum qed_llh_filter_type type,
 569                           union qed_llh_filter *p_filter,
 570                           u8 *p_filter_idx, u32 *p_ref_cnt)
 571 {
 572         int rc;
 573
 574         /* Check if the same filter already exist */
 575         rc = qed_llh_shadow_search_filter(cdev, ppfid, p_filter, p_filter_idx);
 576         if (rc)
 577                 return rc;
 578
 579         /* Find a new entry in case of a new filter */
 580         if (*p_filter_idx == QED_LLH_INVALID_FILTER_IDX) {
 581                 rc = qed_llh_shadow_get_free_idx(cdev, ppfid, p_filter_idx);
 582                 if (rc)
 583                         return rc;
 584         }
 585
 586         /* No free entry was found */
 587         if (*p_filter_idx == QED_LLH_INVALID_FILTER_IDX) {
 588                 DP_NOTICE(cdev,
 589                           "Failed to find an empty LLH filter to utilize [ppfid %d]\n",
 590                           ppfid);
 591                 return -EINVAL;
 592         }
 593
 594         return __qed_llh_shadow_add_filter(cdev, ppfid, *p_filter_idx, type,
 595                                            p_filter, p_ref_cnt);
 596 }
 597
 598 static int
 599 __qed_llh_shadow_remove_filter(struct qed_dev *cdev,
 600                                u8 ppfid, u8 filter_idx, u32 *p_ref_cnt)
 601 {
 602         struct qed_llh_info *p_llh_info = cdev->p_llh_info;
 603         struct qed_llh_filter_info *p_filters;
 604         int rc;
 605
 606         rc = qed_llh_shadow_sanity(cdev, ppfid, filter_idx, "remove");
 607         if (rc)
 608                 return rc;
 609
 610         p_filters = p_llh_info->pp_filters[ppfid];
 611         if (!p_filters[filter_idx].ref_cnt) {
 612                 DP_NOTICE(cdev,
 613                           "LLH shadow: trying to remove a filter with ref_cnt=0\n");
 614                 return -EINVAL;
 615         }
 616
 617         *p_ref_cnt = --p_filters[filter_idx].ref_cnt;
 618         if (!p_filters[filter_idx].ref_cnt)
 619                 memset(&p_filters[filter_idx],
 620                        0, sizeof(p_filters[filter_idx]));
 621
 622         return 0;
 623 }
 624
 625 static int
 626 qed_llh_shadow_remove_filter(struct qed_dev *cdev,
 627                              u8 ppfid,
 628                              union qed_llh_filter *p_filter,
 629                              u8 *p_filter_idx, u32 *p_ref_cnt)
 630 {
 631         int rc;
 632
 633         rc = qed_llh_shadow_search_filter(cdev, ppfid, p_filter, p_filter_idx);
 634         if (rc)
 635                 return rc;
 636
 637         /* No matching filter was found */
 638         if (*p_filter_idx == QED_LLH_INVALID_FILTER_IDX) {
 639                 DP_NOTICE(cdev, "Failed to find a filter in the LLH shadow\n");
 640                 return -EINVAL;
 641         }
 642
 643         return __qed_llh_shadow_remove_filter(cdev, ppfid, *p_filter_idx,
 644                                               p_ref_cnt);
 645 }
 646
 647 static int qed_llh_abs_ppfid(struct qed_dev *cdev, u8 ppfid, u8 *p_abs_ppfid)
 648 {
 649         struct qed_llh_info *p_llh_info = cdev->p_llh_info;
 650
 651         if (ppfid >= p_llh_info->num_ppfid) {
 652                 DP_NOTICE(cdev,
 653                           "ppfid %d is not valid, available indices are 0..%hhd\n",
 654                           ppfid, p_llh_info->num_ppfid - 1);
 655                 *p_abs_ppfid = 0;
 656                 return -EINVAL;
 657         }
 658
 659         *p_abs_ppfid = p_llh_info->ppfid_array[ppfid];
 660
 661         return 0;
 662 }
 663
 664 static int
 665 qed_llh_set_engine_affin(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
 666 {
 667         struct qed_dev *cdev = p_hwfn->cdev;
 668         enum qed_eng eng;
 669         u8 ppfid;
 670         int rc;
 671
 672         rc = qed_mcp_get_engine_config(p_hwfn, p_ptt);
 673         if (rc != 0 && rc != -EOPNOTSUPP) {
 674                 DP_NOTICE(p_hwfn,
 675                           "Failed to get the engine affinity configuration\n");
 676                 return rc;
 677         }
 678
 679         /* RoCE PF is bound to a single engine */
 680         if (QED_IS_ROCE_PERSONALITY(p_hwfn)) {
 681                 eng = cdev->fir_affin ? QED_ENG1 : QED_ENG0;
 682                 rc = qed_llh_set_roce_affinity(cdev, eng);
 683                 if (rc) {
 684                         DP_NOTICE(cdev,
 685                                   "Failed to set the RoCE engine affinity\n");
 686                         return rc;
 687                 }
 688
 689                 DP_VERBOSE(cdev,
 690                            QED_MSG_SP,
 691                            "LLH: Set the engine affinity of RoCE packets as %d\n",
 692                            eng);
 693         }
 694
 695         /* Storage PF is bound to a single engine while L2 PF uses both */
 696         if (QED_IS_FCOE_PERSONALITY(p_hwfn) || QED_IS_ISCSI_PERSONALITY(p_hwfn))
 697                 eng = cdev->fir_affin ? QED_ENG1 : QED_ENG0;
 698         else                    /* L2_PERSONALITY */
 699                 eng = QED_BOTH_ENG;
 700
 701         for (ppfid = 0; ppfid < cdev->p_llh_info->num_ppfid; ppfid++) {
 702                 rc = qed_llh_set_ppfid_affinity(cdev, ppfid, eng);
 703                 if (rc) {
 704                         DP_NOTICE(cdev,
 705                                   "Failed to set the engine affinity of ppfid %d\n",
 706                                   ppfid);
 707                         return rc;
 708                 }
 709         }
 710
 711         DP_VERBOSE(cdev, QED_MSG_SP,
 712                    "LLH: Set the engine affinity of non-RoCE packets as %d\n",
 713                    eng);
 714
 715         return 0;
 716 }
 717
 718 static int qed_llh_hw_init_pf(struct qed_hwfn *p_hwfn,
 719                               struct qed_ptt *p_ptt)
 720 {
 721         struct qed_dev *cdev = p_hwfn->cdev;
 722         u8 ppfid, abs_ppfid;
 723         int rc;
 724
 725         for (ppfid = 0; ppfid < cdev->p_llh_info->num_ppfid; ppfid++) {
 726                 u32 addr;
 727
 728                 rc = qed_llh_abs_ppfid(cdev, ppfid, &abs_ppfid);
 729                 if (rc)
 730                         return rc;
 731
 732                 addr = NIG_REG_LLH_PPFID2PFID_TBL_0 + abs_ppfid * 0x4;
 733                 qed_wr(p_hwfn, p_ptt, addr, p_hwfn->rel_pf_id);
 734         }
 735
 736         if (test_bit(QED_MF_LLH_MAC_CLSS, &cdev->mf_bits) &&
 737             !QED_IS_FCOE_PERSONALITY(p_hwfn)) {
 738                 rc = qed_llh_add_mac_filter(cdev, 0,
 739                                             p_hwfn->hw_info.hw_mac_addr);
 740                 if (rc)
 741                         DP_NOTICE(cdev,
 742                                   "Failed to add an LLH filter with the primary MAC\n");
 743         }
 744
 745         if (QED_IS_CMT(cdev)) {
 746                 rc = qed_llh_set_engine_affin(p_hwfn, p_ptt);
 747                 if (rc)
 748                         return rc;
 749         }
 750
 751         return 0;
 752 }
 753
 754 u8 qed_llh_get_num_ppfid(struct qed_dev *cdev)
 755 {
 756         return cdev->p_llh_info->num_ppfid;
 757 }
 758
 759 #define NIG_REG_PPF_TO_ENGINE_SEL_ROCE_MASK             0x3
 760 #define NIG_REG_PPF_TO_ENGINE_SEL_ROCE_SHIFT            0
 761 #define NIG_REG_PPF_TO_ENGINE_SEL_NON_ROCE_MASK         0x3
 762 #define NIG_REG_PPF_TO_ENGINE_SEL_NON_ROCE_SHIFT        2
 763
 764 int qed_llh_set_ppfid_affinity(struct qed_dev *cdev, u8 ppfid, enum qed_eng eng)
 765 {
 766         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
 767         struct qed_ptt *p_ptt = qed_ptt_acquire(p_hwfn);
 768         u32 addr, val, eng_sel;
 769         u8 abs_ppfid;
 770         int rc = 0;
 771
 772         if (!p_ptt)
 773                 return -EAGAIN;
 774
 775         if (!QED_IS_CMT(cdev))
 776                 goto out;
 777
 778         rc = qed_llh_abs_ppfid(cdev, ppfid, &abs_ppfid);
 779         if (rc)
 780                 goto out;
 781
 782         switch (eng) {
 783         case QED_ENG0:
 784                 eng_sel = 0;
 785                 break;
 786         case QED_ENG1:
 787                 eng_sel = 1;
 788                 break;
 789         case QED_BOTH_ENG:
 790                 eng_sel = 2;
 791                 break;
 792         default:
 793                 DP_NOTICE(cdev, "Invalid affinity value for ppfid [%d]\n", eng);
 794                 rc = -EINVAL;
 795                 goto out;
 796         }
 797
 798         addr = NIG_REG_PPF_TO_ENGINE_SEL + abs_ppfid * 0x4;
 799         val = qed_rd(p_hwfn, p_ptt, addr);
 800         SET_FIELD(val, NIG_REG_PPF_TO_ENGINE_SEL_NON_ROCE, eng_sel);
 801         qed_wr(p_hwfn, p_ptt, addr, val);
 802
 803         /* The iWARP affinity is set as the affinity of ppfid 0 */
 804         if (!ppfid && QED_IS_IWARP_PERSONALITY(p_hwfn))
 805                 cdev->iwarp_affin = (eng == QED_ENG1) ? 1 : 0;
 806 out:
 807         qed_ptt_release(p_hwfn, p_ptt);
 808
 809         return rc;
 810 }
 811
 812 int qed_llh_set_roce_affinity(struct qed_dev *cdev, enum qed_eng eng)
 813 {
 814         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
 815         struct qed_ptt *p_ptt = qed_ptt_acquire(p_hwfn);
 816         u32 addr, val, eng_sel;
 817         u8 ppfid, abs_ppfid;
 818         int rc = 0;
 819
 820         if (!p_ptt)
 821                 return -EAGAIN;
 822
 823         if (!QED_IS_CMT(cdev))
 824                 goto out;
 825
 826         switch (eng) {
 827         case QED_ENG0:
 828                 eng_sel = 0;
 829                 break;
 830         case QED_ENG1:
 831                 eng_sel = 1;
 832                 break;
 833         case QED_BOTH_ENG:
 834                 eng_sel = 2;
 835                 qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_ENG_CLS_ROCE_QP_SEL,
 836                        0xf);  /* QP bit 15 */
 837                 break;
 838         default:
 839                 DP_NOTICE(cdev, "Invalid affinity value for RoCE [%d]\n", eng);
 840                 rc = -EINVAL;
 841                 goto out;
 842         }
 843
 844         for (ppfid = 0; ppfid < cdev->p_llh_info->num_ppfid; ppfid++) {
 845                 rc = qed_llh_abs_ppfid(cdev, ppfid, &abs_ppfid);
 846                 if (rc)
 847                         goto out;
 848
 849                 addr = NIG_REG_PPF_TO_ENGINE_SEL + abs_ppfid * 0x4;
 850                 val = qed_rd(p_hwfn, p_ptt, addr);
 851                 SET_FIELD(val, NIG_REG_PPF_TO_ENGINE_SEL_ROCE, eng_sel);
 852                 qed_wr(p_hwfn, p_ptt, addr, val);
 853         }
 854 out:
 855         qed_ptt_release(p_hwfn, p_ptt);
 856
 857         return rc;
 858 }
 859
 860 struct qed_llh_filter_details {
 861         u64 value;
 862         u32 mode;
 863         u32 protocol_type;
 864         u32 hdr_sel;
 865         u32 enable;
 866 };
 867
 868 static int
 869 qed_llh_access_filter(struct qed_hwfn *p_hwfn,
 870                       struct qed_ptt *p_ptt,
 871                       u8 abs_ppfid,
 872                       u8 filter_idx,
 873                       struct qed_llh_filter_details *p_details)
 874 {
 875         struct qed_dmae_params params = {0};
 876         u32 addr;
 877         u8 pfid;
 878         int rc;
 879
 880         /* The NIG/LLH registers that are accessed in this function have only 16
 881          * rows which are exposed to a PF. I.e. only the 16 filters of its
 882          * default ppfid. Accessing filters of other ppfids requires pretending
 883          * to another PFs.
 884          * The calculation of PPFID->PFID in AH is based on the relative index
 885          * of a PF on its port.
 886          * For BB the pfid is actually the abs_ppfid.
 887          */
 888         if (QED_IS_BB(p_hwfn->cdev))
 889                 pfid = abs_ppfid;
 890         else
 891                 pfid = abs_ppfid * p_hwfn->cdev->num_ports_in_engine +
 892                     MFW_PORT(p_hwfn);
 893
 894         /* Filter enable - should be done first when removing a filter */
 895         if (!p_details->enable) {
 896                 qed_fid_pretend(p_hwfn, p_ptt,
 897                                 pfid << PXP_PRETEND_CONCRETE_FID_PFID_SHIFT);
 898
 899                 addr = NIG_REG_LLH_FUNC_FILTER_EN + filter_idx * 0x4;
 900                 qed_wr(p_hwfn, p_ptt, addr, p_details->enable);
 901
 902                 qed_fid_pretend(p_hwfn, p_ptt,
 903                                 p_hwfn->rel_pf_id <<
 904                                 PXP_PRETEND_CONCRETE_FID_PFID_SHIFT);
 905         }
 906
 907         /* Filter value */
 908         addr = NIG_REG_LLH_FUNC_FILTER_VALUE + 2 * filter_idx * 0x4;
 909
 910         SET_FIELD(params.flags, QED_DMAE_PARAMS_DST_PF_VALID, 0x1);
 911         params.dst_pfid = pfid;
 912         rc = qed_dmae_host2grc(p_hwfn,
 913                                p_ptt,
 914                                (u64)(uintptr_t)&p_details->value,
 915                                addr, 2 /* size_in_dwords */,
 916                                &params);
 917         if (rc)
 918                 return rc;
 919
 920         qed_fid_pretend(p_hwfn, p_ptt,
 921                         pfid << PXP_PRETEND_CONCRETE_FID_PFID_SHIFT);
 922
 923         /* Filter mode */
 924         addr = NIG_REG_LLH_FUNC_FILTER_MODE + filter_idx * 0x4;
 925         qed_wr(p_hwfn, p_ptt, addr, p_details->mode);
 926
 927         /* Filter protocol type */
 928         addr = NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE + filter_idx * 0x4;
 929         qed_wr(p_hwfn, p_ptt, addr, p_details->protocol_type);
 930
 931         /* Filter header select */
 932         addr = NIG_REG_LLH_FUNC_FILTER_HDR_SEL + filter_idx * 0x4;
 933         qed_wr(p_hwfn, p_ptt, addr, p_details->hdr_sel);
 934
 935         /* Filter enable - should be done last when adding a filter */
 936         if (p_details->enable) {
 937                 addr = NIG_REG_LLH_FUNC_FILTER_EN + filter_idx * 0x4;
 938                 qed_wr(p_hwfn, p_ptt, addr, p_details->enable);
 939         }
 940
 941         qed_fid_pretend(p_hwfn, p_ptt,
 942                         p_hwfn->rel_pf_id <<
 943                         PXP_PRETEND_CONCRETE_FID_PFID_SHIFT);
 944
 945         return 0;
 946 }
 947
 948 static int
 949 qed_llh_add_filter(struct qed_hwfn *p_hwfn,
 950                    struct qed_ptt *p_ptt,
 951                    u8 abs_ppfid,
 952                    u8 filter_idx, u8 filter_prot_type, u32 high, u32 low)
 953 {
 954         struct qed_llh_filter_details filter_details;
 955
 956         filter_details.enable = 1;
 957         filter_details.value = ((u64)high << 32) | low;
 958         filter_details.hdr_sel = 0;
 959         filter_details.protocol_type = filter_prot_type;
 960         /* Mode: 0: MAC-address classification 1: protocol classification */
 961         filter_details.mode = filter_prot_type ? 1 : 0;
 962
 963         return qed_llh_access_filter(p_hwfn, p_ptt, abs_ppfid, filter_idx,
 964                                      &filter_details);
 965 }
 966
 967 static int
 968 qed_llh_remove_filter(struct qed_hwfn *p_hwfn,
 969                       struct qed_ptt *p_ptt, u8 abs_ppfid, u8 filter_idx)
 970 {
 971         struct qed_llh_filter_details filter_details = {0};
 972
 973         return qed_llh_access_filter(p_hwfn, p_ptt, abs_ppfid, filter_idx,
 974                                      &filter_details);
 975 }
 976
 977 int qed_llh_add_mac_filter(struct qed_dev *cdev,
 978                            u8 ppfid, u8 mac_addr[ETH_ALEN])
 979 {
 980         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
 981         struct qed_ptt *p_ptt = qed_ptt_acquire(p_hwfn);
 982         union qed_llh_filter filter = {};
 983         u8 filter_idx, abs_ppfid;
 984         u32 high, low, ref_cnt;
 985         int rc = 0;
 986
 987         if (!p_ptt)
 988                 return -EAGAIN;
 989
 990         if (!test_bit(QED_MF_LLH_MAC_CLSS, &cdev->mf_bits))
 991                 goto out;
 992
 993         memcpy(filter.mac.addr, mac_addr, ETH_ALEN);
 994         rc = qed_llh_shadow_add_filter(cdev, ppfid,
 995                                        QED_LLH_FILTER_TYPE_MAC,
 996                                        &filter, &filter_idx, &ref_cnt);
 997         if (rc)
 998                 goto err;
 999
1000         /* Configure the LLH only in case of a new the filter */
1001         if (ref_cnt == 1) {
1002                 rc = qed_llh_abs_ppfid(cdev, ppfid, &abs_ppfid);
1003                 if (rc)
1004                         goto err;
1005
1006                 high = mac_addr[1] | (mac_addr[0] << 8);
1007                 low = mac_addr[5] | (mac_addr[4] << 8) | (mac_addr[3] << 16) |
1008                       (mac_addr[2] << 24);
1009                 rc = qed_llh_add_filter(p_hwfn, p_ptt, abs_ppfid, filter_idx,
1010                                         0, high, low);
1011                 if (rc)
1012                         goto err;
1013         }
1014
1015         DP_VERBOSE(cdev,
1016                    QED_MSG_SP,
1017                    "LLH: Added MAC filter [%pM] to ppfid %hhd [abs %hhd] at idx %hhd [ref_cnt %d]\n",
1018                    mac_addr, ppfid, abs_ppfid, filter_idx, ref_cnt);
1019
1020         goto out;
1021
1022 err:    DP_NOTICE(cdev,
1023                   "LLH: Failed to add MAC filter [%pM] to ppfid %hhd\n",
1024                   mac_addr, ppfid);
1025 out:
1026         qed_ptt_release(p_hwfn, p_ptt);
1027
1028         return rc;
1029 }
1030
1031 static int
1032 qed_llh_protocol_filter_stringify(struct qed_dev *cdev,
1033                                   enum qed_llh_prot_filter_type_t type,
1034                                   u16 source_port_or_eth_type,
1035                                   u16 dest_port, u8 *str, size_t str_len)
1036 {
1037         switch (type) {
1038         case QED_LLH_FILTER_ETHERTYPE:
1039                 snprintf(str, str_len, "Ethertype 0x%04x",
1040                          source_port_or_eth_type);
1041                 break;
1042         case QED_LLH_FILTER_TCP_SRC_PORT:
1043                 snprintf(str, str_len, "TCP src port 0x%04x",
1044                          source_port_or_eth_type);
1045                 break;
1046         case QED_LLH_FILTER_UDP_SRC_PORT:
1047                 snprintf(str, str_len, "UDP src port 0x%04x",
1048                          source_port_or_eth_type);
1049                 break;
1050         case QED_LLH_FILTER_TCP_DEST_PORT:
1051                 snprintf(str, str_len, "TCP dst port 0x%04x", dest_port);
1052                 break;
1053         case QED_LLH_FILTER_UDP_DEST_PORT:
1054                 snprintf(str, str_len, "UDP dst port 0x%04x", dest_port);
1055                 break;
1056         case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
1057                 snprintf(str, str_len, "TCP src/dst ports 0x%04x/0x%04x",
1058                          source_port_or_eth_type, dest_port);
1059                 break;
1060         case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
1061                 snprintf(str, str_len, "UDP src/dst ports 0x%04x/0x%04x",
1062                          source_port_or_eth_type, dest_port);
1063                 break;
1064         default:
1065                 DP_NOTICE(cdev,
1066                           "Non valid LLH protocol filter type %d\n", type);
1067                 return -EINVAL;
1068         }
1069
1070         return 0;
1071 }
1072
1073 static int
1074 qed_llh_protocol_filter_to_hilo(struct qed_dev *cdev,
1075                                 enum qed_llh_prot_filter_type_t type,
1076                                 u16 source_port_or_eth_type,
1077                                 u16 dest_port, u32 *p_high, u32 *p_low)
1078 {
1079         *p_high = 0;
1080         *p_low = 0;
1081
1082         switch (type) {
1083         case QED_LLH_FILTER_ETHERTYPE:
1084                 *p_high = source_port_or_eth_type;
1085                 break;
1086         case QED_LLH_FILTER_TCP_SRC_PORT:
1087         case QED_LLH_FILTER_UDP_SRC_PORT:
1088                 *p_low = source_port_or_eth_type << 16;
1089                 break;
1090         case QED_LLH_FILTER_TCP_DEST_PORT:
1091         case QED_LLH_FILTER_UDP_DEST_PORT:
1092                 *p_low = dest_port;
1093                 break;
1094         case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
1095         case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
1096                 *p_low = (source_port_or_eth_type << 16) | dest_port;
1097                 break;
1098         default:
1099                 DP_NOTICE(cdev,
1100                           "Non valid LLH protocol filter type %d\n", type);
1101                 return -EINVAL;
1102         }
1103
1104         return 0;
1105 }
1106
1107 int
1108 qed_llh_add_protocol_filter(struct qed_dev *cdev,
1109                             u8 ppfid,
1110                             enum qed_llh_prot_filter_type_t type,
1111                             u16 source_port_or_eth_type, u16 dest_port)
1112 {
1113         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
1114         struct qed_ptt *p_ptt = qed_ptt_acquire(p_hwfn);
1115         u8 filter_idx, abs_ppfid, str[32], type_bitmap;
1116         union qed_llh_filter filter = {};
1117         u32 high, low, ref_cnt;
1118         int rc = 0;
1119
1120         if (!p_ptt)
1121                 return -EAGAIN;
1122
1123         if (!test_bit(QED_MF_LLH_PROTO_CLSS, &cdev->mf_bits))
1124                 goto out;
1125
1126         rc = qed_llh_protocol_filter_stringify(cdev, type,
1127                                                source_port_or_eth_type,
1128                                                dest_port, str, sizeof(str));
1129         if (rc)
1130                 goto err;
1131
1132         filter.protocol.type = type;
1133         filter.protocol.source_port_or_eth_type = source_port_or_eth_type;
1134         filter.protocol.dest_port = dest_port;
1135         rc = qed_llh_shadow_add_filter(cdev,
1136                                        ppfid,
1137                                        QED_LLH_FILTER_TYPE_PROTOCOL,
1138                                        &filter, &filter_idx, &ref_cnt);
1139         if (rc)
1140                 goto err;
1141
1142         rc = qed_llh_abs_ppfid(cdev, ppfid, &abs_ppfid);
1143         if (rc)
1144                 goto err;
1145
1146         /* Configure the LLH only in case of a new the filter */
1147         if (ref_cnt == 1) {
1148                 rc = qed_llh_protocol_filter_to_hilo(cdev, type,
1149                                                      source_port_or_eth_type,
1150                                                      dest_port, &high, &low);
1151                 if (rc)
1152                         goto err;
1153
1154                 type_bitmap = 0x1 << type;
1155                 rc = qed_llh_add_filter(p_hwfn, p_ptt, abs_ppfid,
1156                                         filter_idx, type_bitmap, high, low);
1157                 if (rc)
1158                         goto err;
1159         }
1160
1161         DP_VERBOSE(cdev,
1162                    QED_MSG_SP,
1163                    "LLH: Added protocol filter [%s] to ppfid %hhd [abs %hhd] at idx %hhd [ref_cnt %d]\n",
1164                    str, ppfid, abs_ppfid, filter_idx, ref_cnt);
1165
1166         goto out;
1167
1168 err:    DP_NOTICE(p_hwfn,
1169                   "LLH: Failed to add protocol filter [%s] to ppfid %hhd\n",
1170                   str, ppfid);
1171 out:
1172         qed_ptt_release(p_hwfn, p_ptt);
1173
1174         return rc;
1175 }
1176
1177 void qed_llh_remove_mac_filter(struct qed_dev *cdev,
1178                                u8 ppfid, u8 mac_addr[ETH_ALEN])
1179 {
1180         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
1181         struct qed_ptt *p_ptt = qed_ptt_acquire(p_hwfn);
1182         union qed_llh_filter filter = {};
1183         u8 filter_idx, abs_ppfid;
1184         int rc = 0;
1185         u32 ref_cnt;
1186
1187         if (!p_ptt)
1188                 return;
1189
1190         if (!test_bit(QED_MF_LLH_MAC_CLSS, &cdev->mf_bits))
1191                 goto out;
1192
1193         ether_addr_copy(filter.mac.addr, mac_addr);
1194         rc = qed_llh_shadow_remove_filter(cdev, ppfid, &filter, &filter_idx,
1195                                           &ref_cnt);
1196         if (rc)
1197                 goto err;
1198
1199         rc = qed_llh_abs_ppfid(cdev, ppfid, &abs_ppfid);
1200         if (rc)
1201                 goto err;
1202
1203         /* Remove from the LLH in case the filter is not in use */
1204         if (!ref_cnt) {
1205                 rc = qed_llh_remove_filter(p_hwfn, p_ptt, abs_ppfid,
1206                                            filter_idx);
1207                 if (rc)
1208                         goto err;
1209         }
1210
1211         DP_VERBOSE(cdev,
1212                    QED_MSG_SP,
1213                    "LLH: Removed MAC filter [%pM] from ppfid %hhd [abs %hhd] at idx %hhd [ref_cnt %d]\n",
1214                    mac_addr, ppfid, abs_ppfid, filter_idx, ref_cnt);
1215
1216         goto out;
1217
1218 err:    DP_NOTICE(cdev,
1219                   "LLH: Failed to remove MAC filter [%pM] from ppfid %hhd\n",
1220                   mac_addr, ppfid);
1221 out:
1222         qed_ptt_release(p_hwfn, p_ptt);
1223 }
1224
1225 void qed_llh_remove_protocol_filter(struct qed_dev *cdev,
1226                                     u8 ppfid,
1227                                     enum qed_llh_prot_filter_type_t type,
1228                                     u16 source_port_or_eth_type, u16 dest_port)
1229 {
1230         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
1231         struct qed_ptt *p_ptt = qed_ptt_acquire(p_hwfn);
1232         u8 filter_idx, abs_ppfid, str[32];
1233         union qed_llh_filter filter = {};
1234         int rc = 0;
1235         u32 ref_cnt;
1236
1237         if (!p_ptt)
1238                 return;
1239
1240         if (!test_bit(QED_MF_LLH_PROTO_CLSS, &cdev->mf_bits))
1241                 goto out;
1242
1243         rc = qed_llh_protocol_filter_stringify(cdev, type,
1244                                                source_port_or_eth_type,
1245                                                dest_port, str, sizeof(str));
1246         if (rc)
1247                 goto err;
1248
1249         filter.protocol.type = type;
1250         filter.protocol.source_port_or_eth_type = source_port_or_eth_type;
1251         filter.protocol.dest_port = dest_port;
1252         rc = qed_llh_shadow_remove_filter(cdev, ppfid, &filter, &filter_idx,
1253                                           &ref_cnt);
1254         if (rc)
1255                 goto err;
1256
1257         rc = qed_llh_abs_ppfid(cdev, ppfid, &abs_ppfid);
1258         if (rc)
1259                 goto err;
1260
1261         /* Remove from the LLH in case the filter is not in use */
1262         if (!ref_cnt) {
1263                 rc = qed_llh_remove_filter(p_hwfn, p_ptt, abs_ppfid,
1264                                            filter_idx);
1265                 if (rc)
1266                         goto err;
1267         }
1268
1269         DP_VERBOSE(cdev,
1270                    QED_MSG_SP,
1271                    "LLH: Removed protocol filter [%s] from ppfid %hhd [abs %hhd] at idx %hhd [ref_cnt %d]\n",
1272                    str, ppfid, abs_ppfid, filter_idx, ref_cnt);
1273
1274         goto out;
1275
1276 err:    DP_NOTICE(cdev,
1277                   "LLH: Failed to remove protocol filter [%s] from ppfid %hhd\n",
1278                   str, ppfid);
1279 out:
1280         qed_ptt_release(p_hwfn, p_ptt);
1281 }
1282
1283 /******************************* NIG LLH - End ********************************/
1284
1285 #define QED_MIN_DPIS            (4)
1286 #define QED_MIN_PWM_REGION      (QED_WID_SIZE * QED_MIN_DPIS)
1287
1288 static u32 qed_hw_bar_size(struct qed_hwfn *p_hwfn,
1289                            struct qed_ptt *p_ptt, enum BAR_ID bar_id)
1290 {
1291         u32 bar_reg = (bar_id == BAR_ID_0 ?
1292                        PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
1293         u32 val;
1294
1295         if (IS_VF(p_hwfn->cdev))
1296                 return qed_vf_hw_bar_size(p_hwfn, bar_id);
1297
1298         val = qed_rd(p_hwfn, p_ptt, bar_reg);
1299         if (val)
1300                 return 1 << (val + 15);
1301
1302         /* Old MFW initialized above registered only conditionally */
1303         if (p_hwfn->cdev->num_hwfns > 1) {
1304                 DP_INFO(p_hwfn,
1305                         "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n");
1306                         return BAR_ID_0 ? 256 * 1024 : 512 * 1024;
1307         } else {
1308                 DP_INFO(p_hwfn,
1309                         "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n");
1310                         return 512 * 1024;
1311         }
1312 }
1313
1314 void qed_init_dp(struct qed_dev *cdev, u32 dp_module, u8 dp_level)
1315 {
1316         u32 i;
1317
1318         cdev->dp_level = dp_level;
1319         cdev->dp_module = dp_module;
1320         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
1321                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1322
1323                 p_hwfn->dp_level = dp_level;
1324                 p_hwfn->dp_module = dp_module;
1325         }
1326 }
1327
1328 void qed_init_struct(struct qed_dev *cdev)
1329 {
1330         u8 i;
1331
1332         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
1333                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1334
1335                 p_hwfn->cdev = cdev;
1336                 p_hwfn->my_id = i;
1337                 p_hwfn->b_active = false;
1338
1339                 mutex_init(&p_hwfn->dmae_info.mutex);
1340         }
1341
1342         /* hwfn 0 is always active */
1343         cdev->hwfns[0].b_active = true;
1344
1345         /* set the default cache alignment to 128 */
1346         cdev->cache_shift = 7;
1347 }
1348
1349 static void qed_qm_info_free(struct qed_hwfn *p_hwfn)
1350 {
1351         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1352
1353         kfree(qm_info->qm_pq_params);
1354         qm_info->qm_pq_params = NULL;
1355         kfree(qm_info->qm_vport_params);
1356         qm_info->qm_vport_params = NULL;
1357         kfree(qm_info->qm_port_params);
1358         qm_info->qm_port_params = NULL;
1359         kfree(qm_info->wfq_data);
1360         qm_info->wfq_data = NULL;
1361 }
1362
1363 static void qed_dbg_user_data_free(struct qed_hwfn *p_hwfn)
1364 {
1365         kfree(p_hwfn->dbg_user_info);
1366         p_hwfn->dbg_user_info = NULL;
1367 }
1368
1369 void qed_resc_free(struct qed_dev *cdev)
1370 {
1371         int i;
1372
1373         if (IS_VF(cdev)) {
1374                 for_each_hwfn(cdev, i)
1375                         qed_l2_free(&cdev->hwfns[i]);
1376                 return;
1377         }
1378
1379         kfree(cdev->fw_data);
1380         cdev->fw_data = NULL;
1381
1382         kfree(cdev->reset_stats);
1383         cdev->reset_stats = NULL;
1384
1385         qed_llh_free(cdev);
1386
1387         for_each_hwfn(cdev, i) {
1388                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1389
1390                 qed_cxt_mngr_free(p_hwfn);
1391                 qed_qm_info_free(p_hwfn);
1392                 qed_spq_free(p_hwfn);
1393                 qed_eq_free(p_hwfn);
1394                 qed_consq_free(p_hwfn);
1395                 qed_int_free(p_hwfn);
1396 #ifdef CONFIG_QED_LL2
1397                 qed_ll2_free(p_hwfn);
1398 #endif
1399                 if (p_hwfn->hw_info.personality == QED_PCI_FCOE)
1400                         qed_fcoe_free(p_hwfn);
1401
1402                 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
1403                         qed_iscsi_free(p_hwfn);
1404                         qed_ooo_free(p_hwfn);
1405                 }
1406
1407                 if (QED_IS_RDMA_PERSONALITY(p_hwfn))
1408                         qed_rdma_info_free(p_hwfn);
1409
1410                 qed_iov_free(p_hwfn);
1411                 qed_l2_free(p_hwfn);
1412                 qed_dmae_info_free(p_hwfn);
1413                 qed_dcbx_info_free(p_hwfn);
1414                 qed_dbg_user_data_free(p_hwfn);
1415                 qed_fw_overlay_mem_free(p_hwfn, p_hwfn->fw_overlay_mem);
1416
1417                 /* Destroy doorbell recovery mechanism */
1418                 qed_db_recovery_teardown(p_hwfn);
1419         }
1420 }
1421
1422 /******************** QM initialization *******************/
1423 #define ACTIVE_TCS_BMAP 0x9f
1424 #define ACTIVE_TCS_BMAP_4PORT_K2 0xf
1425
1426 /* determines the physical queue flags for a given PF. */
1427 static u32 qed_get_pq_flags(struct qed_hwfn *p_hwfn)
1428 {
1429         u32 flags;
1430
1431         /* common flags */
1432         flags = PQ_FLAGS_LB;
1433
1434         /* feature flags */
1435         if (IS_QED_SRIOV(p_hwfn->cdev))
1436                 flags |= PQ_FLAGS_VFS;
1437
1438         /* protocol flags */
1439         switch (p_hwfn->hw_info.personality) {
1440         case QED_PCI_ETH:
1441                 flags |= PQ_FLAGS_MCOS;
1442                 break;
1443         case QED_PCI_FCOE:
1444                 flags |= PQ_FLAGS_OFLD;
1445                 break;
1446         case QED_PCI_ISCSI:
1447                 flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD;
1448                 break;
1449         case QED_PCI_ETH_ROCE:
1450                 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_OFLD | PQ_FLAGS_LLT;
1451                 if (IS_QED_MULTI_TC_ROCE(p_hwfn))
1452                         flags |= PQ_FLAGS_MTC;
1453                 break;
1454         case QED_PCI_ETH_IWARP:
1455                 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_ACK | PQ_FLAGS_OOO |
1456                     PQ_FLAGS_OFLD;
1457                 break;
1458         default:
1459                 DP_ERR(p_hwfn,
1460                        "unknown personality %d\n", p_hwfn->hw_info.personality);
1461                 return 0;
1462         }
1463
1464         return flags;
1465 }
1466
1467 /* Getters for resource amounts necessary for qm initialization */
1468 static u8 qed_init_qm_get_num_tcs(struct qed_hwfn *p_hwfn)
1469 {
1470         return p_hwfn->hw_info.num_hw_tc;
1471 }
1472
1473 static u16 qed_init_qm_get_num_vfs(struct qed_hwfn *p_hwfn)
1474 {
1475         return IS_QED_SRIOV(p_hwfn->cdev) ?
1476                p_hwfn->cdev->p_iov_info->total_vfs : 0;
1477 }
1478
1479 static u8 qed_init_qm_get_num_mtc_tcs(struct qed_hwfn *p_hwfn)
1480 {
1481         u32 pq_flags = qed_get_pq_flags(p_hwfn);
1482
1483         if (!(PQ_FLAGS_MTC & pq_flags))
1484                 return 1;
1485
1486         return qed_init_qm_get_num_tcs(p_hwfn);
1487 }
1488
1489 #define NUM_DEFAULT_RLS 1
1490
1491 static u16 qed_init_qm_get_num_pf_rls(struct qed_hwfn *p_hwfn)
1492 {
1493         u16 num_pf_rls, num_vfs = qed_init_qm_get_num_vfs(p_hwfn);
1494
1495         /* num RLs can't exceed resource amount of rls or vports */
1496         num_pf_rls = (u16) min_t(u32, RESC_NUM(p_hwfn, QED_RL),
1497                                  RESC_NUM(p_hwfn, QED_VPORT));
1498
1499         /* Make sure after we reserve there's something left */
1500         if (num_pf_rls < num_vfs + NUM_DEFAULT_RLS)
1501                 return 0;
1502
1503         /* subtract rls necessary for VFs and one default one for the PF */
1504         num_pf_rls -= num_vfs + NUM_DEFAULT_RLS;
1505
1506         return num_pf_rls;
1507 }
1508
1509 static u16 qed_init_qm_get_num_vports(struct qed_hwfn *p_hwfn)
1510 {
1511         u32 pq_flags = qed_get_pq_flags(p_hwfn);
1512
1513         /* all pqs share the same vport, except for vfs and pf_rl pqs */
1514         return (!!(PQ_FLAGS_RLS & pq_flags)) *
1515                qed_init_qm_get_num_pf_rls(p_hwfn) +
1516                (!!(PQ_FLAGS_VFS & pq_flags)) *
1517                qed_init_qm_get_num_vfs(p_hwfn) + 1;
1518 }
1519
1520 /* calc amount of PQs according to the requested flags */
1521 static u16 qed_init_qm_get_num_pqs(struct qed_hwfn *p_hwfn)
1522 {
1523         u32 pq_flags = qed_get_pq_flags(p_hwfn);
1524
1525         return (!!(PQ_FLAGS_RLS & pq_flags)) *
1526                qed_init_qm_get_num_pf_rls(p_hwfn) +
1527                (!!(PQ_FLAGS_MCOS & pq_flags)) *
1528                qed_init_qm_get_num_tcs(p_hwfn) +
1529                (!!(PQ_FLAGS_LB & pq_flags)) + (!!(PQ_FLAGS_OOO & pq_flags)) +
1530                (!!(PQ_FLAGS_ACK & pq_flags)) +
1531                (!!(PQ_FLAGS_OFLD & pq_flags)) *
1532                qed_init_qm_get_num_mtc_tcs(p_hwfn) +
1533                (!!(PQ_FLAGS_LLT & pq_flags)) *
1534                qed_init_qm_get_num_mtc_tcs(p_hwfn) +
1535                (!!(PQ_FLAGS_VFS & pq_flags)) * qed_init_qm_get_num_vfs(p_hwfn);
1536 }
1537
1538 /* initialize the top level QM params */
1539 static void qed_init_qm_params(struct qed_hwfn *p_hwfn)
1540 {
1541         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1542         bool four_port;
1543
1544         /* pq and vport bases for this PF */
1545         qm_info->start_pq = (u16) RESC_START(p_hwfn, QED_PQ);
1546         qm_info->start_vport = (u8) RESC_START(p_hwfn, QED_VPORT);
1547
1548         /* rate limiting and weighted fair queueing are always enabled */
1549         qm_info->vport_rl_en = true;
1550         qm_info->vport_wfq_en = true;
1551
1552         /* TC config is different for AH 4 port */
1553         four_port = p_hwfn->cdev->num_ports_in_engine == MAX_NUM_PORTS_K2;
1554
1555         /* in AH 4 port we have fewer TCs per port */
1556         qm_info->max_phys_tcs_per_port = four_port ? NUM_PHYS_TCS_4PORT_K2 :
1557                                                      NUM_OF_PHYS_TCS;
1558
1559         /* unless MFW indicated otherwise, ooo_tc == 3 for
1560          * AH 4-port and 4 otherwise.
1561          */
1562         if (!qm_info->ooo_tc)
1563                 qm_info->ooo_tc = four_port ? DCBX_TCP_OOO_K2_4PORT_TC :
1564                                               DCBX_TCP_OOO_TC;
1565 }
1566
1567 /* initialize qm vport params */
1568 static void qed_init_qm_vport_params(struct qed_hwfn *p_hwfn)
1569 {
1570         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1571         u8 i;
1572
1573         /* all vports participate in weighted fair queueing */
1574         for (i = 0; i < qed_init_qm_get_num_vports(p_hwfn); i++)
1575                 qm_info->qm_vport_params[i].wfq = 1;
1576 }
1577
1578 /* initialize qm port params */
1579 static void qed_init_qm_port_params(struct qed_hwfn *p_hwfn)
1580 {
1581         /* Initialize qm port parameters */
1582         u8 i, active_phys_tcs, num_ports = p_hwfn->cdev->num_ports_in_engine;
1583         struct qed_dev *cdev = p_hwfn->cdev;
1584
1585         /* indicate how ooo and high pri traffic is dealt with */
1586         active_phys_tcs = num_ports == MAX_NUM_PORTS_K2 ?
1587                           ACTIVE_TCS_BMAP_4PORT_K2 :
1588                           ACTIVE_TCS_BMAP;
1589
1590         for (i = 0; i < num_ports; i++) {
1591                 struct init_qm_port_params *p_qm_port =
1592                     &p_hwfn->qm_info.qm_port_params[i];
1593                 u16 pbf_max_cmd_lines;
1594
1595                 p_qm_port->active = 1;
1596                 p_qm_port->active_phys_tcs = active_phys_tcs;
1597                 pbf_max_cmd_lines = (u16)NUM_OF_PBF_CMD_LINES(cdev);
1598                 p_qm_port->num_pbf_cmd_lines = pbf_max_cmd_lines / num_ports;
1599                 p_qm_port->num_btb_blocks = NUM_OF_BTB_BLOCKS(cdev) / num_ports;
1600         }
1601 }
1602
1603 /* Reset the params which must be reset for qm init. QM init may be called as
1604  * a result of flows other than driver load (e.g. dcbx renegotiation). Other
1605  * params may be affected by the init but would simply recalculate to the same
1606  * values. The allocations made for QM init, ports, vports, pqs and vfqs are not
1607  * affected as these amounts stay the same.
1608  */
1609 static void qed_init_qm_reset_params(struct qed_hwfn *p_hwfn)
1610 {
1611         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1612
1613         qm_info->num_pqs = 0;
1614         qm_info->num_vports = 0;
1615         qm_info->num_pf_rls = 0;
1616         qm_info->num_vf_pqs = 0;
1617         qm_info->first_vf_pq = 0;
1618         qm_info->first_mcos_pq = 0;
1619         qm_info->first_rl_pq = 0;
1620 }
1621
1622 static void qed_init_qm_advance_vport(struct qed_hwfn *p_hwfn)
1623 {
1624         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1625
1626         qm_info->num_vports++;
1627
1628         if (qm_info->num_vports > qed_init_qm_get_num_vports(p_hwfn))
1629                 DP_ERR(p_hwfn,
1630                        "vport overflow! qm_info->num_vports %d, qm_init_get_num_vports() %d\n",
1631                        qm_info->num_vports, qed_init_qm_get_num_vports(p_hwfn));
1632 }
1633
1634 /* initialize a single pq and manage qm_info resources accounting.
1635  * The pq_init_flags param determines whether the PQ is rate limited
1636  * (for VF or PF) and whether a new vport is allocated to the pq or not
1637  * (i.e. vport will be shared).
1638  */
1639
1640 /* flags for pq init */
1641 #define PQ_INIT_SHARE_VPORT     (1 << 0)
1642 #define PQ_INIT_PF_RL           (1 << 1)
1643 #define PQ_INIT_VF_RL           (1 << 2)
1644
1645 /* defines for pq init */
1646 #define PQ_INIT_DEFAULT_WRR_GROUP       1
1647 #define PQ_INIT_DEFAULT_TC              0
1648
1649 void qed_hw_info_set_offload_tc(struct qed_hw_info *p_info, u8 tc)
1650 {
1651         p_info->offload_tc = tc;
1652         p_info->offload_tc_set = true;
1653 }
1654
1655 static bool qed_is_offload_tc_set(struct qed_hwfn *p_hwfn)
1656 {
1657         return p_hwfn->hw_info.offload_tc_set;
1658 }
1659
1660 static u32 qed_get_offload_tc(struct qed_hwfn *p_hwfn)
1661 {
1662         if (qed_is_offload_tc_set(p_hwfn))
1663                 return p_hwfn->hw_info.offload_tc;
1664
1665         return PQ_INIT_DEFAULT_TC;
1666 }
1667
1668 static void qed_init_qm_pq(struct qed_hwfn *p_hwfn,
1669                            struct qed_qm_info *qm_info,
1670                            u8 tc, u32 pq_init_flags)
1671 {
1672         u16 pq_idx = qm_info->num_pqs, max_pq = qed_init_qm_get_num_pqs(p_hwfn);
1673
1674         if (pq_idx > max_pq)
1675                 DP_ERR(p_hwfn,
1676                        "pq overflow! pq %d, max pq %d\n", pq_idx, max_pq);
1677
1678         /* init pq params */
1679         qm_info->qm_pq_params[pq_idx].port_id = p_hwfn->port_id;
1680         qm_info->qm_pq_params[pq_idx].vport_id = qm_info->start_vport +
1681             qm_info->num_vports;
1682         qm_info->qm_pq_params[pq_idx].tc_id = tc;
1683         qm_info->qm_pq_params[pq_idx].wrr_group = PQ_INIT_DEFAULT_WRR_GROUP;
1684         qm_info->qm_pq_params[pq_idx].rl_valid =
1685             (pq_init_flags & PQ_INIT_PF_RL || pq_init_flags & PQ_INIT_VF_RL);
1686
1687         /* qm params accounting */
1688         qm_info->num_pqs++;
1689         if (!(pq_init_flags & PQ_INIT_SHARE_VPORT))
1690                 qm_info->num_vports++;
1691
1692         if (pq_init_flags & PQ_INIT_PF_RL)
1693                 qm_info->num_pf_rls++;
1694
1695         if (qm_info->num_vports > qed_init_qm_get_num_vports(p_hwfn))
1696                 DP_ERR(p_hwfn,
1697                        "vport overflow! qm_info->num_vports %d, qm_init_get_num_vports() %d\n",
1698                        qm_info->num_vports, qed_init_qm_get_num_vports(p_hwfn));
1699
1700         if (qm_info->num_pf_rls > qed_init_qm_get_num_pf_rls(p_hwfn))
1701                 DP_ERR(p_hwfn,
1702                        "rl overflow! qm_info->num_pf_rls %d, qm_init_get_num_pf_rls() %d\n",
1703                        qm_info->num_pf_rls, qed_init_qm_get_num_pf_rls(p_hwfn));
1704 }
1705
1706 /* get pq index according to PQ_FLAGS */
1707 static u16 *qed_init_qm_get_idx_from_flags(struct qed_hwfn *p_hwfn,
1708                                            unsigned long pq_flags)
1709 {
1710         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1711
1712         /* Can't have multiple flags set here */
1713         if (bitmap_weight(&pq_flags,
1714                           sizeof(pq_flags) * BITS_PER_BYTE) > 1) {
1715                 DP_ERR(p_hwfn, "requested multiple pq flags 0x%lx\n", pq_flags);
1716                 goto err;
1717         }
1718
1719         if (!(qed_get_pq_flags(p_hwfn) & pq_flags)) {
1720                 DP_ERR(p_hwfn, "pq flag 0x%lx is not set\n", pq_flags);
1721                 goto err;
1722         }
1723
1724         switch (pq_flags) {
1725         case PQ_FLAGS_RLS:
1726                 return &qm_info->first_rl_pq;
1727         case PQ_FLAGS_MCOS:
1728                 return &qm_info->first_mcos_pq;
1729         case PQ_FLAGS_LB:
1730                 return &qm_info->pure_lb_pq;
1731         case PQ_FLAGS_OOO:
1732                 return &qm_info->ooo_pq;
1733         case PQ_FLAGS_ACK:
1734                 return &qm_info->pure_ack_pq;
1735         case PQ_FLAGS_OFLD:
1736                 return &qm_info->first_ofld_pq;
1737         case PQ_FLAGS_LLT:
1738                 return &qm_info->first_llt_pq;
1739         case PQ_FLAGS_VFS:
1740                 return &qm_info->first_vf_pq;
1741         default:
1742                 goto err;
1743         }
1744
1745 err:
1746         return &qm_info->start_pq;
1747 }
1748
1749 /* save pq index in qm info */
1750 static void qed_init_qm_set_idx(struct qed_hwfn *p_hwfn,
1751                                 u32 pq_flags, u16 pq_val)
1752 {
1753         u16 *base_pq_idx = qed_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
1754
1755         *base_pq_idx = p_hwfn->qm_info.start_pq + pq_val;
1756 }
1757
1758 /* get tx pq index, with the PQ TX base already set (ready for context init) */
1759 u16 qed_get_cm_pq_idx(struct qed_hwfn *p_hwfn, u32 pq_flags)
1760 {
1761         u16 *base_pq_idx = qed_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
1762
1763         return *base_pq_idx + CM_TX_PQ_BASE;
1764 }
1765
1766 u16 qed_get_cm_pq_idx_mcos(struct qed_hwfn *p_hwfn, u8 tc)
1767 {
1768         u8 max_tc = qed_init_qm_get_num_tcs(p_hwfn);
1769
1770         if (max_tc == 0) {
1771                 DP_ERR(p_hwfn, "pq with flag 0x%lx do not exist\n",
1772                        PQ_FLAGS_MCOS);
1773                 return p_hwfn->qm_info.start_pq;
1774         }
1775
1776         if (tc > max_tc)
1777                 DP_ERR(p_hwfn, "tc %d must be smaller than %d\n", tc, max_tc);
1778
1779         return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_MCOS) + (tc % max_tc);
1780 }
1781
1782 u16 qed_get_cm_pq_idx_vf(struct qed_hwfn *p_hwfn, u16 vf)
1783 {
1784         u16 max_vf = qed_init_qm_get_num_vfs(p_hwfn);
1785
1786         if (max_vf == 0) {
1787                 DP_ERR(p_hwfn, "pq with flag 0x%lx do not exist\n",
1788                        PQ_FLAGS_VFS);
1789                 return p_hwfn->qm_info.start_pq;
1790         }
1791
1792         if (vf > max_vf)
1793                 DP_ERR(p_hwfn, "vf %d must be smaller than %d\n", vf, max_vf);
1794
1795         return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_VFS) + (vf % max_vf);
1796 }
1797
1798 u16 qed_get_cm_pq_idx_ofld_mtc(struct qed_hwfn *p_hwfn, u8 tc)
1799 {
1800         u16 first_ofld_pq, pq_offset;
1801
1802         first_ofld_pq = qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_OFLD);
1803         pq_offset = (tc < qed_init_qm_get_num_mtc_tcs(p_hwfn)) ?
1804                     tc : PQ_INIT_DEFAULT_TC;
1805
1806         return first_ofld_pq + pq_offset;
1807 }
1808
1809 u16 qed_get_cm_pq_idx_llt_mtc(struct qed_hwfn *p_hwfn, u8 tc)
1810 {
1811         u16 first_llt_pq, pq_offset;
1812
1813         first_llt_pq = qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_LLT);
1814         pq_offset = (tc < qed_init_qm_get_num_mtc_tcs(p_hwfn)) ?
1815                     tc : PQ_INIT_DEFAULT_TC;
1816
1817         return first_llt_pq + pq_offset;
1818 }
1819
1820 /* Functions for creating specific types of pqs */
1821 static void qed_init_qm_lb_pq(struct qed_hwfn *p_hwfn)
1822 {
1823         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1824
1825         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_LB))
1826                 return;
1827
1828         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_LB, qm_info->num_pqs);
1829         qed_init_qm_pq(p_hwfn, qm_info, PURE_LB_TC, PQ_INIT_SHARE_VPORT);
1830 }
1831
1832 static void qed_init_qm_ooo_pq(struct qed_hwfn *p_hwfn)
1833 {
1834         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1835
1836         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_OOO))
1837                 return;
1838
1839         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_OOO, qm_info->num_pqs);
1840         qed_init_qm_pq(p_hwfn, qm_info, qm_info->ooo_tc, PQ_INIT_SHARE_VPORT);
1841 }
1842
1843 static void qed_init_qm_pure_ack_pq(struct qed_hwfn *p_hwfn)
1844 {
1845         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1846
1847         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_ACK))
1848                 return;
1849
1850         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_ACK, qm_info->num_pqs);
1851         qed_init_qm_pq(p_hwfn, qm_info, qed_get_offload_tc(p_hwfn),
1852                        PQ_INIT_SHARE_VPORT);
1853 }
1854
1855 static void qed_init_qm_mtc_pqs(struct qed_hwfn *p_hwfn)
1856 {
1857         u8 num_tcs = qed_init_qm_get_num_mtc_tcs(p_hwfn);
1858         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1859         u8 tc;
1860
1861         /* override pq's TC if offload TC is set */
1862         for (tc = 0; tc < num_tcs; tc++)
1863                 qed_init_qm_pq(p_hwfn, qm_info,
1864                                qed_is_offload_tc_set(p_hwfn) ?
1865                                p_hwfn->hw_info.offload_tc : tc,
1866                                PQ_INIT_SHARE_VPORT);
1867 }
1868
1869 static void qed_init_qm_offload_pq(struct qed_hwfn *p_hwfn)
1870 {
1871         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1872
1873         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_OFLD))
1874                 return;
1875
1876         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_OFLD, qm_info->num_pqs);
1877         qed_init_qm_mtc_pqs(p_hwfn);
1878 }
1879
1880 static void qed_init_qm_low_latency_pq(struct qed_hwfn *p_hwfn)
1881 {
1882         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1883
1884         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_LLT))
1885                 return;
1886
1887         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_LLT, qm_info->num_pqs);
1888         qed_init_qm_mtc_pqs(p_hwfn);
1889 }
1890
1891 static void qed_init_qm_mcos_pqs(struct qed_hwfn *p_hwfn)
1892 {
1893         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1894         u8 tc_idx;
1895
1896         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_MCOS))
1897                 return;
1898
1899         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_MCOS, qm_info->num_pqs);
1900         for (tc_idx = 0; tc_idx < qed_init_qm_get_num_tcs(p_hwfn); tc_idx++)
1901                 qed_init_qm_pq(p_hwfn, qm_info, tc_idx, PQ_INIT_SHARE_VPORT);
1902 }
1903
1904 static void qed_init_qm_vf_pqs(struct qed_hwfn *p_hwfn)
1905 {
1906         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1907         u16 vf_idx, num_vfs = qed_init_qm_get_num_vfs(p_hwfn);
1908
1909         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_VFS))
1910                 return;
1911
1912         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_VFS, qm_info->num_pqs);
1913         qm_info->num_vf_pqs = num_vfs;
1914         for (vf_idx = 0; vf_idx < num_vfs; vf_idx++)
1915                 qed_init_qm_pq(p_hwfn,
1916                                qm_info, PQ_INIT_DEFAULT_TC, PQ_INIT_VF_RL);
1917 }
1918
1919 static void qed_init_qm_rl_pqs(struct qed_hwfn *p_hwfn)
1920 {
1921         u16 pf_rls_idx, num_pf_rls = qed_init_qm_get_num_pf_rls(p_hwfn);
1922         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1923
1924         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_RLS))
1925                 return;
1926
1927         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_RLS, qm_info->num_pqs);
1928         for (pf_rls_idx = 0; pf_rls_idx < num_pf_rls; pf_rls_idx++)
1929                 qed_init_qm_pq(p_hwfn, qm_info, qed_get_offload_tc(p_hwfn),
1930                                PQ_INIT_PF_RL);
1931 }
1932
1933 static void qed_init_qm_pq_params(struct qed_hwfn *p_hwfn)
1934 {
1935         /* rate limited pqs, must come first (FW assumption) */
1936         qed_init_qm_rl_pqs(p_hwfn);
1937
1938         /* pqs for multi cos */
1939         qed_init_qm_mcos_pqs(p_hwfn);
1940
1941         /* pure loopback pq */
1942         qed_init_qm_lb_pq(p_hwfn);
1943
1944         /* out of order pq */
1945         qed_init_qm_ooo_pq(p_hwfn);
1946
1947         /* pure ack pq */
1948         qed_init_qm_pure_ack_pq(p_hwfn);
1949
1950         /* pq for offloaded protocol */
1951         qed_init_qm_offload_pq(p_hwfn);
1952
1953         /* low latency pq */
1954         qed_init_qm_low_latency_pq(p_hwfn);
1955
1956         /* done sharing vports */
1957         qed_init_qm_advance_vport(p_hwfn);
1958
1959         /* pqs for vfs */
1960         qed_init_qm_vf_pqs(p_hwfn);
1961 }
1962
1963 /* compare values of getters against resources amounts */
1964 static int qed_init_qm_sanity(struct qed_hwfn *p_hwfn)
1965 {
1966         if (qed_init_qm_get_num_vports(p_hwfn) > RESC_NUM(p_hwfn, QED_VPORT)) {
1967                 DP_ERR(p_hwfn, "requested amount of vports exceeds resource\n");
1968                 return -EINVAL;
1969         }
1970
1971         if (qed_init_qm_get_num_pqs(p_hwfn) <= RESC_NUM(p_hwfn, QED_PQ))
1972                 return 0;
1973
1974         if (QED_IS_ROCE_PERSONALITY(p_hwfn)) {
1975                 p_hwfn->hw_info.multi_tc_roce_en = false;
1976                 DP_NOTICE(p_hwfn,
1977                           "multi-tc roce was disabled to reduce requested amount of pqs\n");
1978                 if (qed_init_qm_get_num_pqs(p_hwfn) <= RESC_NUM(p_hwfn, QED_PQ))
1979                         return 0;
1980         }
1981
1982         DP_ERR(p_hwfn, "requested amount of pqs exceeds resource\n");
1983         return -EINVAL;
1984 }
1985
1986 static void qed_dp_init_qm_params(struct qed_hwfn *p_hwfn)
1987 {
1988         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1989         struct init_qm_vport_params *vport;
1990         struct init_qm_port_params *port;
1991         struct init_qm_pq_params *pq;
1992         int i, tc;
1993
1994         /* top level params */
1995         DP_VERBOSE(p_hwfn,
1996                    NETIF_MSG_HW,
1997                    "qm init top level params: start_pq %d, start_vport %d, pure_lb_pq %d, offload_pq %d, llt_pq %d, pure_ack_pq %d\n",
1998                    qm_info->start_pq,
1999                    qm_info->start_vport,
2000                    qm_info->pure_lb_pq,
2001                    qm_info->first_ofld_pq,
2002                    qm_info->first_llt_pq,
2003                    qm_info->pure_ack_pq);
2004         DP_VERBOSE(p_hwfn,
2005                    NETIF_MSG_HW,
2006                    "ooo_pq %d, first_vf_pq %d, num_pqs %d, num_vf_pqs %d, num_vports %d, max_phys_tcs_per_port %d\n",
2007                    qm_info->ooo_pq,
2008                    qm_info->first_vf_pq,
2009                    qm_info->num_pqs,
2010                    qm_info->num_vf_pqs,
2011                    qm_info->num_vports, qm_info->max_phys_tcs_per_port);
2012         DP_VERBOSE(p_hwfn,
2013                    NETIF_MSG_HW,
2014                    "pf_rl_en %d, pf_wfq_en %d, vport_rl_en %d, vport_wfq_en %d, pf_wfq %d, pf_rl %d, num_pf_rls %d, pq_flags %x\n",
2015                    qm_info->pf_rl_en,
2016                    qm_info->pf_wfq_en,
2017                    qm_info->vport_rl_en,
2018                    qm_info->vport_wfq_en,
2019                    qm_info->pf_wfq,
2020                    qm_info->pf_rl,
2021                    qm_info->num_pf_rls, qed_get_pq_flags(p_hwfn));
2022
2023         /* port table */
2024         for (i = 0; i < p_hwfn->cdev->num_ports_in_engine; i++) {
2025                 port = &(qm_info->qm_port_params[i]);
2026                 DP_VERBOSE(p_hwfn,
2027                            NETIF_MSG_HW,
2028                            "port idx %d, active %d, active_phys_tcs %d, num_pbf_cmd_lines %d, num_btb_blocks %d, reserved %d\n",
2029                            i,
2030                            port->active,
2031                            port->active_phys_tcs,
2032                            port->num_pbf_cmd_lines,
2033                            port->num_btb_blocks, port->reserved);
2034         }
2035
2036         /* vport table */
2037         for (i = 0; i < qm_info->num_vports; i++) {
2038                 vport = &(qm_info->qm_vport_params[i]);
2039                 DP_VERBOSE(p_hwfn,
2040                            NETIF_MSG_HW,
2041                            "vport idx %d, wfq %d, first_tx_pq_id [ ",
2042                            qm_info->start_vport + i, vport->wfq);
2043                 for (tc = 0; tc < NUM_OF_TCS; tc++)
2044                         DP_VERBOSE(p_hwfn,
2045                                    NETIF_MSG_HW,
2046                                    "%d ", vport->first_tx_pq_id[tc]);
2047                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "]\n");
2048         }
2049
2050         /* pq table */
2051         for (i = 0; i < qm_info->num_pqs; i++) {
2052                 pq = &(qm_info->qm_pq_params[i]);
2053                 DP_VERBOSE(p_hwfn,
2054                            NETIF_MSG_HW,
2055                            "pq idx %d, port %d, vport_id %d, tc %d, wrr_grp %d, rl_valid %d rl_id %d\n",
2056                            qm_info->start_pq + i,
2057                            pq->port_id,
2058                            pq->vport_id,
2059                            pq->tc_id, pq->wrr_group, pq->rl_valid, pq->rl_id);
2060         }
2061 }
2062
2063 static void qed_init_qm_info(struct qed_hwfn *p_hwfn)
2064 {
2065         /* reset params required for init run */
2066         qed_init_qm_reset_params(p_hwfn);
2067
2068         /* init QM top level params */
2069         qed_init_qm_params(p_hwfn);
2070
2071         /* init QM port params */
2072         qed_init_qm_port_params(p_hwfn);
2073
2074         /* init QM vport params */
2075         qed_init_qm_vport_params(p_hwfn);
2076
2077         /* init QM physical queue params */
2078         qed_init_qm_pq_params(p_hwfn);
2079
2080         /* display all that init */
2081         qed_dp_init_qm_params(p_hwfn);
2082 }
2083
2084 /* This function reconfigures the QM pf on the fly.
2085  * For this purpose we:
2086  * 1. reconfigure the QM database
2087  * 2. set new values to runtime array
2088  * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
2089  * 4. activate init tool in QM_PF stage
2090  * 5. send an sdm_qm_cmd through rbc interface to release the QM
2091  */
2092 int qed_qm_reconf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2093 {
2094         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
2095         bool b_rc;
2096         int rc;
2097
2098         /* initialize qed's qm data structure */
2099         qed_init_qm_info(p_hwfn);
2100
2101         /* stop PF's qm queues */
2102         spin_lock_bh(&qm_lock);
2103         b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
2104                                     qm_info->start_pq, qm_info->num_pqs);
2105         spin_unlock_bh(&qm_lock);
2106         if (!b_rc)
2107                 return -EINVAL;
2108
2109         /* prepare QM portion of runtime array */
2110         qed_qm_init_pf(p_hwfn, p_ptt, false);
2111
2112         /* activate init tool on runtime array */
2113         rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
2114                           p_hwfn->hw_info.hw_mode);
2115         if (rc)
2116                 return rc;
2117
2118         /* start PF's qm queues */
2119         spin_lock_bh(&qm_lock);
2120         b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
2121                                     qm_info->start_pq, qm_info->num_pqs);
2122         spin_unlock_bh(&qm_lock);
2123         if (!b_rc)
2124                 return -EINVAL;
2125
2126         return 0;
2127 }
2128
2129 static int qed_alloc_qm_data(struct qed_hwfn *p_hwfn)
2130 {
2131         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
2132         int rc;
2133
2134         rc = qed_init_qm_sanity(p_hwfn);
2135         if (rc)
2136                 goto alloc_err;
2137
2138         qm_info->qm_pq_params = kcalloc(qed_init_qm_get_num_pqs(p_hwfn),
2139                                         sizeof(*qm_info->qm_pq_params),
2140                                         GFP_KERNEL);
2141         if (!qm_info->qm_pq_params)
2142                 goto alloc_err;
2143
2144         qm_info->qm_vport_params = kcalloc(qed_init_qm_get_num_vports(p_hwfn),
2145                                            sizeof(*qm_info->qm_vport_params),
2146                                            GFP_KERNEL);
2147         if (!qm_info->qm_vport_params)
2148                 goto alloc_err;
2149
2150         qm_info->qm_port_params = kcalloc(p_hwfn->cdev->num_ports_in_engine,
2151                                           sizeof(*qm_info->qm_port_params),
2152                                           GFP_KERNEL);
2153         if (!qm_info->qm_port_params)
2154                 goto alloc_err;
2155
2156         qm_info->wfq_data = kcalloc(qed_init_qm_get_num_vports(p_hwfn),
2157                                     sizeof(*qm_info->wfq_data),
2158                                     GFP_KERNEL);
2159         if (!qm_info->wfq_data)
2160                 goto alloc_err;
2161
2162         return 0;
2163
2164 alloc_err:
2165         DP_NOTICE(p_hwfn, "Failed to allocate memory for QM params\n");
2166         qed_qm_info_free(p_hwfn);
2167         return -ENOMEM;
2168 }
2169
2170 int qed_resc_alloc(struct qed_dev *cdev)
2171 {
2172         u32 rdma_tasks, excess_tasks;
2173         u32 line_count;
2174         int i, rc = 0;
2175
2176         if (IS_VF(cdev)) {
2177                 for_each_hwfn(cdev, i) {
2178                         rc = qed_l2_alloc(&cdev->hwfns[i]);
2179                         if (rc)
2180                                 return rc;
2181                 }
2182                 return rc;
2183         }
2184
2185         cdev->fw_data = kzalloc(sizeof(*cdev->fw_data), GFP_KERNEL);
2186         if (!cdev->fw_data)
2187                 return -ENOMEM;
2188
2189         for_each_hwfn(cdev, i) {
2190                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2191                 u32 n_eqes, num_cons;
2192
2193                 /* Initialize the doorbell recovery mechanism */
2194                 rc = qed_db_recovery_setup(p_hwfn);
2195                 if (rc)
2196                         goto alloc_err;
2197
2198                 /* First allocate the context manager structure */
2199                 rc = qed_cxt_mngr_alloc(p_hwfn);
2200                 if (rc)
2201                         goto alloc_err;
2202
2203                 /* Set the HW cid/tid numbers (in the contest manager)
2204                  * Must be done prior to any further computations.
2205                  */
2206                 rc = qed_cxt_set_pf_params(p_hwfn, RDMA_MAX_TIDS);
2207                 if (rc)
2208                         goto alloc_err;
2209
2210                 rc = qed_alloc_qm_data(p_hwfn);
2211                 if (rc)
2212                         goto alloc_err;
2213
2214                 /* init qm info */
2215                 qed_init_qm_info(p_hwfn);
2216
2217                 /* Compute the ILT client partition */
2218                 rc = qed_cxt_cfg_ilt_compute(p_hwfn, &line_count);
2219                 if (rc) {
2220                         DP_NOTICE(p_hwfn,
2221                                   "too many ILT lines; re-computing with less lines\n");
2222                         /* In case there are not enough ILT lines we reduce the
2223                          * number of RDMA tasks and re-compute.
2224                          */
2225                         excess_tasks =
2226                             qed_cxt_cfg_ilt_compute_excess(p_hwfn, line_count);
2227                         if (!excess_tasks)
2228                                 goto alloc_err;
2229
2230                         rdma_tasks = RDMA_MAX_TIDS - excess_tasks;
2231                         rc = qed_cxt_set_pf_params(p_hwfn, rdma_tasks);
2232                         if (rc)
2233                                 goto alloc_err;
2234
2235                         rc = qed_cxt_cfg_ilt_compute(p_hwfn, &line_count);
2236                         if (rc) {
2237                                 DP_ERR(p_hwfn,
2238                                        "failed ILT compute. Requested too many lines: %u\n",
2239                                        line_count);
2240
2241                                 goto alloc_err;
2242                         }
2243                 }
2244
2245                 /* CID map / ILT shadow table / T2
2246                  * The talbes sizes are determined by the computations above
2247                  */
2248                 rc = qed_cxt_tables_alloc(p_hwfn);
2249                 if (rc)
2250                         goto alloc_err;
2251
2252                 /* SPQ, must follow ILT because initializes SPQ context */
2253                 rc = qed_spq_alloc(p_hwfn);
2254                 if (rc)
2255                         goto alloc_err;
2256
2257                 /* SP status block allocation */
2258                 p_hwfn->p_dpc_ptt = qed_get_reserved_ptt(p_hwfn,
2259                                                          RESERVED_PTT_DPC);
2260
2261                 rc = qed_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
2262                 if (rc)
2263                         goto alloc_err;
2264
2265                 rc = qed_iov_alloc(p_hwfn);
2266                 if (rc)
2267                         goto alloc_err;
2268
2269                 /* EQ */
2270                 n_eqes = qed_chain_get_capacity(&p_hwfn->p_spq->chain);
2271                 if (QED_IS_RDMA_PERSONALITY(p_hwfn)) {
2272                         u32 n_srq = qed_cxt_get_total_srq_count(p_hwfn);
2273                         enum protocol_type rdma_proto;
2274
2275                         if (QED_IS_ROCE_PERSONALITY(p_hwfn))
2276                                 rdma_proto = PROTOCOLID_ROCE;
2277                         else
2278                                 rdma_proto = PROTOCOLID_IWARP;
2279
2280                         num_cons = qed_cxt_get_proto_cid_count(p_hwfn,
2281                                                                rdma_proto,
2282                                                                NULL) * 2;
2283                         /* EQ should be able to get events from all SRQ's
2284                          * at the same time
2285                          */
2286                         n_eqes += num_cons + 2 * MAX_NUM_VFS_BB + n_srq;
2287                 } else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
2288                         num_cons =
2289                             qed_cxt_get_proto_cid_count(p_hwfn,
2290                                                         PROTOCOLID_ISCSI,
2291                                                         NULL);
2292                         n_eqes += 2 * num_cons;
2293                 }
2294
2295                 if (n_eqes > 0xFFFF) {
2296                         DP_ERR(p_hwfn,
2297                                "Cannot allocate 0x%x EQ elements. The maximum of a u16 chain is 0x%x\n",
2298                                n_eqes, 0xFFFF);
2299                         goto alloc_no_mem;
2300                 }
2301
2302                 rc = qed_eq_alloc(p_hwfn, (u16) n_eqes);
2303                 if (rc)
2304                         goto alloc_err;
2305
2306                 rc = qed_consq_alloc(p_hwfn);
2307                 if (rc)
2308                         goto alloc_err;
2309
2310                 rc = qed_l2_alloc(p_hwfn);
2311                 if (rc)
2312                         goto alloc_err;
2313
2314 #ifdef CONFIG_QED_LL2
2315                 if (p_hwfn->using_ll2) {
2316                         rc = qed_ll2_alloc(p_hwfn);
2317                         if (rc)
2318                                 goto alloc_err;
2319                 }
2320 #endif
2321
2322                 if (p_hwfn->hw_info.personality == QED_PCI_FCOE) {
2323                         rc = qed_fcoe_alloc(p_hwfn);
2324                         if (rc)
2325                                 goto alloc_err;
2326                 }
2327
2328                 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
2329                         rc = qed_iscsi_alloc(p_hwfn);
2330                         if (rc)
2331                                 goto alloc_err;
2332                         rc = qed_ooo_alloc(p_hwfn);
2333                         if (rc)
2334                                 goto alloc_err;
2335                 }
2336
2337                 if (QED_IS_RDMA_PERSONALITY(p_hwfn)) {
2338                         rc = qed_rdma_info_alloc(p_hwfn);
2339                         if (rc)
2340                                 goto alloc_err;
2341                 }
2342
2343                 /* DMA info initialization */
2344                 rc = qed_dmae_info_alloc(p_hwfn);
2345                 if (rc)
2346                         goto alloc_err;
2347
2348                 /* DCBX initialization */
2349                 rc = qed_dcbx_info_alloc(p_hwfn);
2350                 if (rc)
2351                         goto alloc_err;
2352
2353                 rc = qed_dbg_alloc_user_data(p_hwfn, &p_hwfn->dbg_user_info);
2354                 if (rc)
2355                         goto alloc_err;
2356         }
2357
2358         rc = qed_llh_alloc(cdev);
2359         if (rc) {
2360                 DP_NOTICE(cdev,
2361                           "Failed to allocate memory for the llh_info structure\n");
2362                 goto alloc_err;
2363         }
2364
2365         cdev->reset_stats = kzalloc(sizeof(*cdev->reset_stats), GFP_KERNEL);
2366         if (!cdev->reset_stats)
2367                 goto alloc_no_mem;
2368
2369         return 0;
2370
2371 alloc_no_mem:
2372         rc = -ENOMEM;
2373 alloc_err:
2374         qed_resc_free(cdev);
2375         return rc;
2376 }
2377
2378 void qed_resc_setup(struct qed_dev *cdev)
2379 {
2380         int i;
2381
2382         if (IS_VF(cdev)) {
2383                 for_each_hwfn(cdev, i)
2384                         qed_l2_setup(&cdev->hwfns[i]);
2385                 return;
2386         }
2387
2388         for_each_hwfn(cdev, i) {
2389                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2390
2391                 qed_cxt_mngr_setup(p_hwfn);
2392                 qed_spq_setup(p_hwfn);
2393                 qed_eq_setup(p_hwfn);
2394                 qed_consq_setup(p_hwfn);
2395
2396                 /* Read shadow of current MFW mailbox */
2397                 qed_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
2398                 memcpy(p_hwfn->mcp_info->mfw_mb_shadow,
2399                        p_hwfn->mcp_info->mfw_mb_cur,
2400                        p_hwfn->mcp_info->mfw_mb_length);
2401
2402                 qed_int_setup(p_hwfn, p_hwfn->p_main_ptt);
2403
2404                 qed_l2_setup(p_hwfn);
2405                 qed_iov_setup(p_hwfn);
2406 #ifdef CONFIG_QED_LL2
2407                 if (p_hwfn->using_ll2)
2408                         qed_ll2_setup(p_hwfn);
2409 #endif
2410                 if (p_hwfn->hw_info.personality == QED_PCI_FCOE)
2411                         qed_fcoe_setup(p_hwfn);
2412
2413                 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
2414                         qed_iscsi_setup(p_hwfn);
2415                         qed_ooo_setup(p_hwfn);
2416                 }
2417         }
2418 }
2419
2420 #define FINAL_CLEANUP_POLL_CNT          (100)
2421 #define FINAL_CLEANUP_POLL_TIME         (10)
2422 int qed_final_cleanup(struct qed_hwfn *p_hwfn,
2423                       struct qed_ptt *p_ptt, u16 id, bool is_vf)
2424 {
2425         u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
2426         int rc = -EBUSY;
2427
2428         addr = GTT_BAR0_MAP_REG_USDM_RAM +
2429                 USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
2430
2431         if (is_vf)
2432                 id += 0x10;
2433
2434         command |= X_FINAL_CLEANUP_AGG_INT <<
2435                 SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
2436         command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
2437         command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
2438         command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
2439
2440         /* Make sure notification is not set before initiating final cleanup */
2441         if (REG_RD(p_hwfn, addr)) {
2442                 DP_NOTICE(p_hwfn,
2443                           "Unexpected; Found final cleanup notification before initiating final cleanup\n");
2444                 REG_WR(p_hwfn, addr, 0);
2445         }
2446
2447         DP_VERBOSE(p_hwfn, QED_MSG_IOV,
2448                    "Sending final cleanup for PFVF[%d] [Command %08x]\n",
2449                    id, command);
2450
2451         qed_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);
2452
2453         /* Poll until completion */
2454         while (!REG_RD(p_hwfn, addr) && count--)
2455                 msleep(FINAL_CLEANUP_POLL_TIME);
2456
2457         if (REG_RD(p_hwfn, addr))
2458                 rc = 0;
2459         else
2460                 DP_NOTICE(p_hwfn,
2461                           "Failed to receive FW final cleanup notification\n");
2462
2463         /* Cleanup afterwards */
2464         REG_WR(p_hwfn, addr, 0);
2465
2466         return rc;
2467 }
2468
2469 static int qed_calc_hw_mode(struct qed_hwfn *p_hwfn)
2470 {
2471         int hw_mode = 0;
2472
2473         if (QED_IS_BB_B0(p_hwfn->cdev)) {
2474                 hw_mode |= 1 << MODE_BB;
2475         } else if (QED_IS_AH(p_hwfn->cdev)) {
2476                 hw_mode |= 1 << MODE_K2;
2477         } else {
2478                 DP_NOTICE(p_hwfn, "Unknown chip type %#x\n",
2479                           p_hwfn->cdev->type);
2480                 return -EINVAL;
2481         }
2482
2483         switch (p_hwfn->cdev->num_ports_in_engine) {
2484         case 1:
2485                 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
2486                 break;
2487         case 2:
2488                 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
2489                 break;
2490         case 4:
2491                 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
2492                 break;
2493         default:
2494                 DP_NOTICE(p_hwfn, "num_ports_in_engine = %d not supported\n",
2495                           p_hwfn->cdev->num_ports_in_engine);
2496                 return -EINVAL;
2497         }
2498
2499         if (test_bit(QED_MF_OVLAN_CLSS, &p_hwfn->cdev->mf_bits))
2500                 hw_mode |= 1 << MODE_MF_SD;
2501         else
2502                 hw_mode |= 1 << MODE_MF_SI;
2503
2504         hw_mode |= 1 << MODE_ASIC;
2505
2506         if (p_hwfn->cdev->num_hwfns > 1)
2507                 hw_mode |= 1 << MODE_100G;
2508
2509         p_hwfn->hw_info.hw_mode = hw_mode;
2510
2511         DP_VERBOSE(p_hwfn, (NETIF_MSG_PROBE | NETIF_MSG_IFUP),
2512                    "Configuring function for hw_mode: 0x%08x\n",
2513                    p_hwfn->hw_info.hw_mode);
2514
2515         return 0;
2516 }
2517
2518 /* Init run time data for all PFs on an engine. */
2519 static void qed_init_cau_rt_data(struct qed_dev *cdev)
2520 {
2521         u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
2522         int i, igu_sb_id;
2523
2524         for_each_hwfn(cdev, i) {
2525                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2526                 struct qed_igu_info *p_igu_info;
2527                 struct qed_igu_block *p_block;
2528                 struct cau_sb_entry sb_entry;
2529
2530                 p_igu_info = p_hwfn->hw_info.p_igu_info;
2531
2532                 for (igu_sb_id = 0;
2533                      igu_sb_id < QED_MAPPING_MEMORY_SIZE(cdev); igu_sb_id++) {
2534                         p_block = &p_igu_info->entry[igu_sb_id];
2535
2536                         if (!p_block->is_pf)
2537                                 continue;
2538
2539                         qed_init_cau_sb_entry(p_hwfn, &sb_entry,
2540                                               p_block->function_id, 0, 0);
2541                         STORE_RT_REG_AGG(p_hwfn, offset + igu_sb_id * 2,
2542                                          sb_entry);
2543                 }
2544         }
2545 }
2546
2547 static void qed_init_cache_line_size(struct qed_hwfn *p_hwfn,
2548                                      struct qed_ptt *p_ptt)
2549 {
2550         u32 val, wr_mbs, cache_line_size;
2551
2552         val = qed_rd(p_hwfn, p_ptt, PSWRQ2_REG_WR_MBS0);
2553         switch (val) {
2554         case 0:
2555                 wr_mbs = 128;
2556                 break;
2557         case 1:
2558                 wr_mbs = 256;
2559                 break;
2560         case 2:
2561                 wr_mbs = 512;
2562                 break;
2563         default:
2564                 DP_INFO(p_hwfn,
2565                         "Unexpected value of PSWRQ2_REG_WR_MBS0 [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
2566                         val);
2567                 return;
2568         }
2569
2570         cache_line_size = min_t(u32, L1_CACHE_BYTES, wr_mbs);
2571         switch (cache_line_size) {
2572         case 32:
2573                 val = 0;
2574                 break;
2575         case 64:
2576                 val = 1;
2577                 break;
2578         case 128:
2579                 val = 2;
2580                 break;
2581         case 256:
2582                 val = 3;
2583                 break;
2584         default:
2585                 DP_INFO(p_hwfn,
2586                         "Unexpected value of cache line size [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
2587                         cache_line_size);
2588         }
2589
2590         if (L1_CACHE_BYTES > wr_mbs)
2591                 DP_INFO(p_hwfn,
2592                         "The cache line size for padding is suboptimal for performance [OS cache line size 0x%x, wr mbs 0x%x]\n",
2593                         L1_CACHE_BYTES, wr_mbs);
2594
2595         STORE_RT_REG(p_hwfn, PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET, val);
2596         if (val > 0) {
2597                 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET, val);
2598                 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET, val);
2599         }
2600 }
2601
2602 static int qed_hw_init_common(struct qed_hwfn *p_hwfn,
2603                               struct qed_ptt *p_ptt, int hw_mode)
2604 {
2605         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
2606         struct qed_qm_common_rt_init_params params;
2607         struct qed_dev *cdev = p_hwfn->cdev;
2608         u8 vf_id, max_num_vfs;
2609         u16 num_pfs, pf_id;
2610         u32 concrete_fid;
2611         int rc = 0;
2612
2613         qed_init_cau_rt_data(cdev);
2614
2615         /* Program GTT windows */
2616         qed_gtt_init(p_hwfn);
2617
2618         if (p_hwfn->mcp_info) {
2619                 if (p_hwfn->mcp_info->func_info.bandwidth_max)
2620                         qm_info->pf_rl_en = true;
2621                 if (p_hwfn->mcp_info->func_info.bandwidth_min)
2622                         qm_info->pf_wfq_en = true;
2623         }
2624
2625         memset(&params, 0, sizeof(params));
2626         params.max_ports_per_engine = p_hwfn->cdev->num_ports_in_engine;
2627         params.max_phys_tcs_per_port = qm_info->max_phys_tcs_per_port;
2628         params.pf_rl_en = qm_info->pf_rl_en;
2629         params.pf_wfq_en = qm_info->pf_wfq_en;
2630         params.global_rl_en = qm_info->vport_rl_en;
2631         params.vport_wfq_en = qm_info->vport_wfq_en;
2632         params.port_params = qm_info->qm_port_params;
2633
2634         qed_qm_common_rt_init(p_hwfn, &params);
2635
2636         qed_cxt_hw_init_common(p_hwfn);
2637
2638         qed_init_cache_line_size(p_hwfn, p_ptt);
2639
2640         rc = qed_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);
2641         if (rc)
2642                 return rc;
2643
2644         qed_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
2645         qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
2646
2647         if (QED_IS_BB(p_hwfn->cdev)) {
2648                 num_pfs = NUM_OF_ENG_PFS(p_hwfn->cdev);
2649                 for (pf_id = 0; pf_id < num_pfs; pf_id++) {
2650                         qed_fid_pretend(p_hwfn, p_ptt, pf_id);
2651                         qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2652                         qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2653                 }
2654                 /* pretend to original PF */
2655                 qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
2656         }
2657
2658         max_num_vfs = QED_IS_AH(cdev) ? MAX_NUM_VFS_K2 : MAX_NUM_VFS_BB;
2659         for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
2660                 concrete_fid = qed_vfid_to_concrete(p_hwfn, vf_id);
2661                 qed_fid_pretend(p_hwfn, p_ptt, (u16) concrete_fid);
2662                 qed_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
2663                 qed_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
2664                 qed_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
2665                 qed_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
2666         }
2667         /* pretend to original PF */
2668         qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
2669
2670         return rc;
2671 }
2672
2673 static int
2674 qed_hw_init_dpi_size(struct qed_hwfn *p_hwfn,
2675                      struct qed_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus)
2676 {
2677         u32 dpi_bit_shift, dpi_count, dpi_page_size;
2678         u32 min_dpis;
2679         u32 n_wids;
2680
2681         /* Calculate DPI size */
2682         n_wids = max_t(u32, QED_MIN_WIDS, n_cpus);
2683         dpi_page_size = QED_WID_SIZE * roundup_pow_of_two(n_wids);
2684         dpi_page_size = (dpi_page_size + PAGE_SIZE - 1) & ~(PAGE_SIZE - 1);
2685         dpi_bit_shift = ilog2(dpi_page_size / 4096);
2686         dpi_count = pwm_region_size / dpi_page_size;
2687
2688         min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis;
2689         min_dpis = max_t(u32, QED_MIN_DPIS, min_dpis);
2690
2691         p_hwfn->dpi_size = dpi_page_size;
2692         p_hwfn->dpi_count = dpi_count;
2693
2694         qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift);
2695
2696         if (dpi_count < min_dpis)
2697                 return -EINVAL;
2698
2699         return 0;
2700 }
2701
2702 enum QED_ROCE_EDPM_MODE {
2703         QED_ROCE_EDPM_MODE_ENABLE = 0,
2704         QED_ROCE_EDPM_MODE_FORCE_ON = 1,
2705         QED_ROCE_EDPM_MODE_DISABLE = 2,
2706 };
2707
2708 bool qed_edpm_enabled(struct qed_hwfn *p_hwfn)
2709 {
2710         if (p_hwfn->dcbx_no_edpm || p_hwfn->db_bar_no_edpm)
2711                 return false;
2712
2713         return true;
2714 }
2715
2716 static int
2717 qed_hw_init_pf_doorbell_bar(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2718 {
2719         u32 pwm_regsize, norm_regsize;
2720         u32 non_pwm_conn, min_addr_reg1;
2721         u32 db_bar_size, n_cpus = 1;
2722         u32 roce_edpm_mode;
2723         u32 pf_dems_shift;
2724         int rc = 0;
2725         u8 cond;
2726
2727         db_bar_size = qed_hw_bar_size(p_hwfn, p_ptt, BAR_ID_1);
2728         if (p_hwfn->cdev->num_hwfns > 1)
2729                 db_bar_size /= 2;
2730
2731         /* Calculate doorbell regions */
2732         non_pwm_conn = qed_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
2733                        qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
2734                                                    NULL) +
2735                        qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH,
2736                                                    NULL);
2737         norm_regsize = roundup(QED_PF_DEMS_SIZE * non_pwm_conn, PAGE_SIZE);
2738         min_addr_reg1 = norm_regsize / 4096;
2739         pwm_regsize = db_bar_size - norm_regsize;
2740
2741         /* Check that the normal and PWM sizes are valid */
2742         if (db_bar_size < norm_regsize) {
2743                 DP_ERR(p_hwfn->cdev,
2744                        "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n",
2745                        db_bar_size, norm_regsize);
2746                 return -EINVAL;
2747         }
2748
2749         if (pwm_regsize < QED_MIN_PWM_REGION) {
2750                 DP_ERR(p_hwfn->cdev,
2751                        "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n",
2752                        pwm_regsize,
2753                        QED_MIN_PWM_REGION, db_bar_size, norm_regsize);
2754                 return -EINVAL;
2755         }
2756
2757         /* Calculate number of DPIs */
2758         roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode;
2759         if ((roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE) ||
2760             ((roce_edpm_mode == QED_ROCE_EDPM_MODE_FORCE_ON))) {
2761                 /* Either EDPM is mandatory, or we are attempting to allocate a
2762                  * WID per CPU.
2763                  */
2764                 n_cpus = num_present_cpus();
2765                 rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
2766         }
2767
2768         cond = (rc && (roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE)) ||
2769                (roce_edpm_mode == QED_ROCE_EDPM_MODE_DISABLE);
2770         if (cond || p_hwfn->dcbx_no_edpm) {
2771                 /* Either EDPM is disabled from user configuration, or it is
2772                  * disabled via DCBx, or it is not mandatory and we failed to
2773                  * allocated a WID per CPU.
2774                  */
2775                 n_cpus = 1;
2776                 rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
2777
2778                 if (cond)
2779                         qed_rdma_dpm_bar(p_hwfn, p_ptt);
2780         }
2781
2782         p_hwfn->wid_count = (u16) n_cpus;
2783
2784         DP_INFO(p_hwfn,
2785                 "doorbell bar: normal_region_size=%d, pwm_region_size=%d, dpi_size=%d, dpi_count=%d, roce_edpm=%s, page_size=%lu\n",
2786                 norm_regsize,
2787                 pwm_regsize,
2788                 p_hwfn->dpi_size,
2789                 p_hwfn->dpi_count,
2790                 (!qed_edpm_enabled(p_hwfn)) ?
2791                 "disabled" : "enabled", PAGE_SIZE);
2792
2793         if (rc) {
2794                 DP_ERR(p_hwfn,
2795                        "Failed to allocate enough DPIs. Allocated %d but the current minimum is %d.\n",
2796                        p_hwfn->dpi_count,
2797                        p_hwfn->pf_params.rdma_pf_params.min_dpis);
2798                 return -EINVAL;
2799         }
2800
2801         p_hwfn->dpi_start_offset = norm_regsize;
2802
2803         /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
2804         pf_dems_shift = ilog2(QED_PF_DEMS_SIZE / 4);
2805         qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
2806         qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
2807
2808         return 0;
2809 }
2810
2811 static int qed_hw_init_port(struct qed_hwfn *p_hwfn,
2812                             struct qed_ptt *p_ptt, int hw_mode)
2813 {
2814         int rc = 0;
2815
2816         /* In CMT the gate should be cleared by the 2nd hwfn */
2817         if (!QED_IS_CMT(p_hwfn->cdev) || !IS_LEAD_HWFN(p_hwfn))
2818                 STORE_RT_REG(p_hwfn, NIG_REG_BRB_GATE_DNTFWD_PORT_RT_OFFSET, 0);
2819
2820         rc = qed_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id, hw_mode);
2821         if (rc)
2822                 return rc;
2823
2824         qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_WRITE_PAD_ENABLE, 0);
2825
2826         return 0;
2827 }
2828
2829 static int qed_hw_init_pf(struct qed_hwfn *p_hwfn,
2830                           struct qed_ptt *p_ptt,
2831                           struct qed_tunnel_info *p_tunn,
2832                           int hw_mode,
2833                           bool b_hw_start,
2834                           enum qed_int_mode int_mode,
2835                           bool allow_npar_tx_switch)
2836 {
2837         u8 rel_pf_id = p_hwfn->rel_pf_id;
2838         int rc = 0;
2839
2840         if (p_hwfn->mcp_info) {
2841                 struct qed_mcp_function_info *p_info;
2842
2843                 p_info = &p_hwfn->mcp_info->func_info;
2844                 if (p_info->bandwidth_min)
2845                         p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
2846
2847                 /* Update rate limit once we'll actually have a link */
2848                 p_hwfn->qm_info.pf_rl = 100000;
2849         }
2850
2851         qed_cxt_hw_init_pf(p_hwfn, p_ptt);
2852
2853         qed_int_igu_init_rt(p_hwfn);
2854
2855         /* Set VLAN in NIG if needed */
2856         if (hw_mode & BIT(MODE_MF_SD)) {
2857                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "Configuring LLH_FUNC_TAG\n");
2858                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
2859                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
2860                              p_hwfn->hw_info.ovlan);
2861
2862                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
2863                            "Configuring LLH_FUNC_FILTER_HDR_SEL\n");
2864                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET,
2865                              1);
2866         }
2867
2868         /* Enable classification by MAC if needed */
2869         if (hw_mode & BIT(MODE_MF_SI)) {
2870                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
2871                            "Configuring TAGMAC_CLS_TYPE\n");
2872                 STORE_RT_REG(p_hwfn,
2873                              NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET, 1);
2874         }
2875
2876         /* Protocol Configuration */
2877         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
2878                      (p_hwfn->hw_info.personality == QED_PCI_ISCSI) ? 1 : 0);
2879         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET,
2880                      (p_hwfn->hw_info.personality == QED_PCI_FCOE) ? 1 : 0);
2881         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
2882
2883         /* Sanity check before the PF init sequence that uses DMAE */
2884         rc = qed_dmae_sanity(p_hwfn, p_ptt, "pf_phase");
2885         if (rc)
2886                 return rc;
2887
2888         /* PF Init sequence */
2889         rc = qed_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
2890         if (rc)
2891                 return rc;
2892
2893         /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
2894         rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
2895         if (rc)
2896                 return rc;
2897
2898         qed_fw_overlay_init_ram(p_hwfn, p_ptt, p_hwfn->fw_overlay_mem);
2899
2900         /* Pure runtime initializations - directly to the HW  */
2901         qed_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
2902
2903         rc = qed_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
2904         if (rc)
2905                 return rc;
2906
2907         /* Use the leading hwfn since in CMT only NIG #0 is operational */
2908         if (IS_LEAD_HWFN(p_hwfn)) {
2909                 rc = qed_llh_hw_init_pf(p_hwfn, p_ptt);
2910                 if (rc)
2911                         return rc;
2912         }
2913
2914         if (b_hw_start) {
2915                 /* enable interrupts */
2916                 qed_int_igu_enable(p_hwfn, p_ptt, int_mode);
2917
2918                 /* send function start command */
2919                 rc = qed_sp_pf_start(p_hwfn, p_ptt, p_tunn,
2920                                      allow_npar_tx_switch);
2921                 if (rc) {
2922                         DP_NOTICE(p_hwfn, "Function start ramrod failed\n");
2923                         return rc;
2924                 }
2925                 if (p_hwfn->hw_info.personality == QED_PCI_FCOE) {
2926                         qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1, BIT(2));
2927                         qed_wr(p_hwfn, p_ptt,
2928                                PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST,
2929                                0x100);
2930                 }
2931         }
2932         return rc;
2933 }
2934
2935 int qed_pglueb_set_pfid_enable(struct qed_hwfn *p_hwfn,
2936                                struct qed_ptt *p_ptt, bool b_enable)
2937 {
2938         u32 delay_idx = 0, val, set_val = b_enable ? 1 : 0;
2939
2940         /* Configure the PF's internal FID_enable for master transactions */
2941         qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
2942
2943         /* Wait until value is set - try for 1 second every 50us */
2944         for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
2945                 val = qed_rd(p_hwfn, p_ptt,
2946                              PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
2947                 if (val == set_val)
2948                         break;
2949
2950                 usleep_range(50, 60);
2951         }
2952
2953         if (val != set_val) {
2954                 DP_NOTICE(p_hwfn,
2955                           "PFID_ENABLE_MASTER wasn't changed after a second\n");
2956                 return -EAGAIN;
2957         }
2958
2959         return 0;
2960 }
2961
2962 static void qed_reset_mb_shadow(struct qed_hwfn *p_hwfn,
2963                                 struct qed_ptt *p_main_ptt)
2964 {
2965         /* Read shadow of current MFW mailbox */
2966         qed_mcp_read_mb(p_hwfn, p_main_ptt);
2967         memcpy(p_hwfn->mcp_info->mfw_mb_shadow,
2968                p_hwfn->mcp_info->mfw_mb_cur, p_hwfn->mcp_info->mfw_mb_length);
2969 }
2970
2971 static void
2972 qed_fill_load_req_params(struct qed_load_req_params *p_load_req,
2973                          struct qed_drv_load_params *p_drv_load)
2974 {
2975         memset(p_load_req, 0, sizeof(*p_load_req));
2976
2977         p_load_req->drv_role = p_drv_load->is_crash_kernel ?
2978                                QED_DRV_ROLE_KDUMP : QED_DRV_ROLE_OS;
2979         p_load_req->timeout_val = p_drv_load->mfw_timeout_val;
2980         p_load_req->avoid_eng_reset = p_drv_load->avoid_eng_reset;
2981         p_load_req->override_force_load = p_drv_load->override_force_load;
2982 }
2983
2984 static int qed_vf_start(struct qed_hwfn *p_hwfn,
2985                         struct qed_hw_init_params *p_params)
2986 {
2987         if (p_params->p_tunn) {
2988                 qed_vf_set_vf_start_tunn_update_param(p_params->p_tunn);
2989                 qed_vf_pf_tunnel_param_update(p_hwfn, p_params->p_tunn);
2990         }
2991
2992         p_hwfn->b_int_enabled = true;
2993
2994         return 0;
2995 }
2996
2997 static void qed_pglueb_clear_err(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2998 {
2999         qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR,
3000                BIT(p_hwfn->abs_pf_id));
3001 }
3002
3003 int qed_hw_init(struct qed_dev *cdev, struct qed_hw_init_params *p_params)
3004 {
3005         struct qed_load_req_params load_req_params;
3006         u32 load_code, resp, param, drv_mb_param;
3007         bool b_default_mtu = true;
3008         struct qed_hwfn *p_hwfn;
3009         const u32 *fw_overlays;
3010         u32 fw_overlays_len;
3011         u16 ether_type;
3012         int rc = 0, i;
3013
3014         if ((p_params->int_mode == QED_INT_MODE_MSI) && (cdev->num_hwfns > 1)) {
3015                 DP_NOTICE(cdev, "MSI mode is not supported for CMT devices\n");
3016                 return -EINVAL;
3017         }
3018
3019         if (IS_PF(cdev)) {
3020                 rc = qed_init_fw_data(cdev, p_params->bin_fw_data);
3021                 if (rc)
3022                         return rc;
3023         }
3024
3025         for_each_hwfn(cdev, i) {
3026                 p_hwfn = &cdev->hwfns[i];
3027
3028                 /* If management didn't provide a default, set one of our own */
3029                 if (!p_hwfn->hw_info.mtu) {
3030                         p_hwfn->hw_info.mtu = 1500;
3031                         b_default_mtu = false;
3032                 }
3033
3034                 if (IS_VF(cdev)) {
3035                         qed_vf_start(p_hwfn, p_params);
3036                         continue;
3037                 }
3038
3039                 rc = qed_calc_hw_mode(p_hwfn);
3040                 if (rc)
3041                         return rc;
3042
3043                 if (IS_PF(cdev) && (test_bit(QED_MF_8021Q_TAGGING,
3044                                              &cdev->mf_bits) ||
3045                                     test_bit(QED_MF_8021AD_TAGGING,
3046                                              &cdev->mf_bits))) {
3047                         if (test_bit(QED_MF_8021Q_TAGGING, &cdev->mf_bits))
3048                                 ether_type = ETH_P_8021Q;
3049                         else
3050                                 ether_type = ETH_P_8021AD;
3051                         STORE_RT_REG(p_hwfn, PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET,
3052                                      ether_type);
3053                         STORE_RT_REG(p_hwfn, NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET,
3054                                      ether_type);
3055                         STORE_RT_REG(p_hwfn, PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET,
3056                                      ether_type);
3057                         STORE_RT_REG(p_hwfn, DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET,
3058                                      ether_type);
3059                 }
3060
3061                 qed_fill_load_req_params(&load_req_params,
3062                                          p_params->p_drv_load_params);
3063                 rc = qed_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt,
3064                                       &load_req_params);
3065                 if (rc) {
3066                         DP_NOTICE(p_hwfn, "Failed sending a LOAD_REQ command\n");
3067                         return rc;
3068                 }
3069
3070                 load_code = load_req_params.load_code;
3071                 DP_VERBOSE(p_hwfn, QED_MSG_SP,
3072                            "Load request was sent. Load code: 0x%x\n",
3073                            load_code);
3074
3075                 /* Only relevant for recovery:
3076                  * Clear the indication after LOAD_REQ is responded by the MFW.
3077                  */
3078                 cdev->recov_in_prog = false;
3079
3080                 qed_mcp_set_capabilities(p_hwfn, p_hwfn->p_main_ptt);
3081
3082                 qed_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
3083
3084                 /* Clean up chip from previous driver if such remains exist.
3085                  * This is not needed when the PF is the first one on the
3086                  * engine, since afterwards we are going to init the FW.
3087                  */
3088                 if (load_code != FW_MSG_CODE_DRV_LOAD_ENGINE) {
3089                         rc = qed_final_cleanup(p_hwfn, p_hwfn->p_main_ptt,
3090                                                p_hwfn->rel_pf_id, false);
3091                         if (rc) {
3092                                 qed_hw_err_notify(p_hwfn, p_hwfn->p_main_ptt,
3093                                                   QED_HW_ERR_RAMROD_FAIL,
3094                                                   "Final cleanup failed\n");
3095                                 goto load_err;
3096                         }
3097                 }
3098
3099                 /* Log and clear previous pglue_b errors if such exist */
3100                 qed_pglueb_rbc_attn_handler(p_hwfn, p_hwfn->p_main_ptt);
3101
3102                 /* Enable the PF's internal FID_enable in the PXP */
3103                 rc = qed_pglueb_set_pfid_enable(p_hwfn, p_hwfn->p_main_ptt,
3104                                                 true);
3105                 if (rc)
3106                         goto load_err;
3107
3108                 /* Clear the pglue_b was_error indication.
3109                  * In E4 it must be done after the BME and the internal
3110                  * FID_enable for the PF are set, since VDMs may cause the
3111                  * indication to be set again.
3112                  */
3113                 qed_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt);
3114
3115                 fw_overlays = cdev->fw_data->fw_overlays;
3116                 fw_overlays_len = cdev->fw_data->fw_overlays_len;
3117                 p_hwfn->fw_overlay_mem =
3118                     qed_fw_overlay_mem_alloc(p_hwfn, fw_overlays,
3119                                              fw_overlays_len);
3120                 if (!p_hwfn->fw_overlay_mem) {
3121                         DP_NOTICE(p_hwfn,
3122                                   "Failed to allocate fw overlay memory\n");
3123                         rc = -ENOMEM;
3124                         goto load_err;
3125                 }
3126
3127                 switch (load_code) {
3128                 case FW_MSG_CODE_DRV_LOAD_ENGINE:
3129                         rc = qed_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
3130                                                 p_hwfn->hw_info.hw_mode);
3131                         if (rc)
3132                                 break;
3133                 /* Fall through */
3134                 case FW_MSG_CODE_DRV_LOAD_PORT:
3135                         rc = qed_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
3136                                               p_hwfn->hw_info.hw_mode);
3137                         if (rc)
3138                                 break;
3139
3140                 /* Fall through */
3141                 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
3142                         rc = qed_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
3143                                             p_params->p_tunn,
3144                                             p_hwfn->hw_info.hw_mode,
3145                                             p_params->b_hw_start,
3146                                             p_params->int_mode,
3147                                             p_params->allow_npar_tx_switch);
3148                         break;
3149                 default:
3150                         DP_NOTICE(p_hwfn,
3151                                   "Unexpected load code [0x%08x]", load_code);
3152                         rc = -EINVAL;
3153                         break;
3154                 }
3155
3156                 if (rc) {
3157                         DP_NOTICE(p_hwfn,
3158                                   "init phase failed for loadcode 0x%x (rc %d)\n",
3159                                   load_code, rc);
3160                         goto load_err;
3161                 }
3162
3163                 rc = qed_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt);
3164                 if (rc)
3165                         return rc;
3166
3167                 /* send DCBX attention request command */
3168                 DP_VERBOSE(p_hwfn,
3169                            QED_MSG_DCB,
3170                            "sending phony dcbx set command to trigger DCBx attention handling\n");
3171                 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
3172                                  DRV_MSG_CODE_SET_DCBX,
3173                                  1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT,
3174                                  &resp, &param);
3175                 if (rc) {
3176                         DP_NOTICE(p_hwfn,
3177                                   "Failed to send DCBX attention request\n");
3178                         return rc;
3179                 }
3180
3181                 p_hwfn->hw_init_done = true;
3182         }
3183
3184         if (IS_PF(cdev)) {
3185                 p_hwfn = QED_LEADING_HWFN(cdev);
3186
3187                 /* Get pre-negotiated values for stag, bandwidth etc. */
3188                 DP_VERBOSE(p_hwfn,
3189                            QED_MSG_SPQ,
3190                            "Sending GET_OEM_UPDATES command to trigger stag/bandwidth attention handling\n");
3191                 drv_mb_param = 1 << DRV_MB_PARAM_DUMMY_OEM_UPDATES_OFFSET;
3192                 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
3193                                  DRV_MSG_CODE_GET_OEM_UPDATES,
3194                                  drv_mb_param, &resp, &param);
3195                 if (rc)
3196                         DP_NOTICE(p_hwfn,
3197                                   "Failed to send GET_OEM_UPDATES attention request\n");
3198
3199                 drv_mb_param = STORM_FW_VERSION;
3200                 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
3201                                  DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER,
3202                                  drv_mb_param, &load_code, &param);
3203                 if (rc)
3204                         DP_INFO(p_hwfn, "Failed to update firmware version\n");
3205
3206                 if (!b_default_mtu) {
3207                         rc = qed_mcp_ov_update_mtu(p_hwfn, p_hwfn->p_main_ptt,
3208                                                    p_hwfn->hw_info.mtu);
3209                         if (rc)
3210                                 DP_INFO(p_hwfn,
3211                                         "Failed to update default mtu\n");
3212                 }
3213
3214                 rc = qed_mcp_ov_update_driver_state(p_hwfn,
3215                                                     p_hwfn->p_main_ptt,
3216                                                   QED_OV_DRIVER_STATE_DISABLED);
3217                 if (rc)
3218                         DP_INFO(p_hwfn, "Failed to update driver state\n");
3219
3220                 rc = qed_mcp_ov_update_eswitch(p_hwfn, p_hwfn->p_main_ptt,
3221                                                QED_OV_ESWITCH_NONE);
3222                 if (rc)
3223                         DP_INFO(p_hwfn, "Failed to update eswitch mode\n");
3224         }
3225
3226         return 0;
3227
3228 load_err:
3229         /* The MFW load lock should be released also when initialization fails.
3230          */
3231         qed_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt);
3232         return rc;
3233 }
3234
3235 #define QED_HW_STOP_RETRY_LIMIT (10)
3236 static void qed_hw_timers_stop(struct qed_dev *cdev,
3237                                struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
3238 {
3239         int i;
3240
3241         /* close timers */
3242         qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
3243         qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
3244
3245         if (cdev->recov_in_prog)
3246                 return;
3247
3248         for (i = 0; i < QED_HW_STOP_RETRY_LIMIT; i++) {
3249                 if ((!qed_rd(p_hwfn, p_ptt,
3250                              TM_REG_PF_SCAN_ACTIVE_CONN)) &&
3251                     (!qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
3252                         break;
3253
3254                 /* Dependent on number of connection/tasks, possibly
3255                  * 1ms sleep is required between polls
3256                  */
3257                 usleep_range(1000, 2000);
3258         }
3259
3260         if (i < QED_HW_STOP_RETRY_LIMIT)
3261                 return;
3262
3263         DP_NOTICE(p_hwfn,
3264                   "Timers linear scans are not over [Connection %02x Tasks %02x]\n",
3265                   (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
3266                   (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
3267 }
3268
3269 void qed_hw_timers_stop_all(struct qed_dev *cdev)
3270 {
3271         int j;
3272
3273         for_each_hwfn(cdev, j) {
3274                 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
3275                 struct qed_ptt *p_ptt = p_hwfn->p_main_ptt;
3276
3277                 qed_hw_timers_stop(cdev, p_hwfn, p_ptt);
3278         }
3279 }
3280
3281 int qed_hw_stop(struct qed_dev *cdev)
3282 {
3283         struct qed_hwfn *p_hwfn;
3284         struct qed_ptt *p_ptt;
3285         int rc, rc2 = 0;
3286         int j;
3287
3288         for_each_hwfn(cdev, j) {
3289                 p_hwfn = &cdev->hwfns[j];
3290                 p_ptt = p_hwfn->p_main_ptt;
3291
3292                 DP_VERBOSE(p_hwfn, NETIF_MSG_IFDOWN, "Stopping hw/fw\n");
3293
3294                 if (IS_VF(cdev)) {
3295                         qed_vf_pf_int_cleanup(p_hwfn);
3296                         rc = qed_vf_pf_reset(p_hwfn);
3297                         if (rc) {
3298                                 DP_NOTICE(p_hwfn,
3299                                           "qed_vf_pf_reset failed. rc = %d.\n",
3300                                           rc);
3301                                 rc2 = -EINVAL;
3302                         }
3303                         continue;
3304                 }
3305
3306                 /* mark the hw as uninitialized... */
3307                 p_hwfn->hw_init_done = false;
3308
3309                 /* Send unload command to MCP */
3310                 if (!cdev->recov_in_prog) {
3311                         rc = qed_mcp_unload_req(p_hwfn, p_ptt);
3312                         if (rc) {
3313                                 DP_NOTICE(p_hwfn,
3314                                           "Failed sending a UNLOAD_REQ command. rc = %d.\n",
3315                                           rc);
3316                                 rc2 = -EINVAL;
3317                         }
3318                 }
3319
3320                 qed_slowpath_irq_sync(p_hwfn);
3321
3322                 /* After this point no MFW attentions are expected, e.g. prevent
3323                  * race between pf stop and dcbx pf update.
3324                  */
3325                 rc = qed_sp_pf_stop(p_hwfn);
3326                 if (rc) {
3327                         DP_NOTICE(p_hwfn,
3328                                   "Failed to close PF against FW [rc = %d]. Continue to stop HW to prevent illegal host access by the device.\n",
3329                                   rc);
3330                         rc2 = -EINVAL;
3331                 }
3332
3333                 qed_wr(p_hwfn, p_ptt,
3334                        NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
3335
3336                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
3337                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
3338                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
3339                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
3340                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
3341
3342                 qed_hw_timers_stop(cdev, p_hwfn, p_ptt);
3343
3344                 /* Disable Attention Generation */
3345                 qed_int_igu_disable_int(p_hwfn, p_ptt);
3346
3347                 qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
3348                 qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
3349
3350                 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
3351
3352                 /* Need to wait 1ms to guarantee SBs are cleared */
3353                 usleep_range(1000, 2000);
3354
3355                 /* Disable PF in HW blocks */
3356                 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DB_ENABLE, 0);
3357                 qed_wr(p_hwfn, p_ptt, QM_REG_PF_EN, 0);
3358
3359                 if (IS_LEAD_HWFN(p_hwfn) &&
3360                     test_bit(QED_MF_LLH_MAC_CLSS, &cdev->mf_bits) &&
3361                     !QED_IS_FCOE_PERSONALITY(p_hwfn))
3362                         qed_llh_remove_mac_filter(cdev, 0,
3363                                                   p_hwfn->hw_info.hw_mac_addr);
3364
3365                 if (!cdev->recov_in_prog) {
3366                         rc = qed_mcp_unload_done(p_hwfn, p_ptt);
3367                         if (rc) {
3368                                 DP_NOTICE(p_hwfn,
3369                                           "Failed sending a UNLOAD_DONE command. rc = %d.\n",
3370                                           rc);
3371                                 rc2 = -EINVAL;
3372                         }
3373                 }
3374         }
3375
3376         if (IS_PF(cdev) && !cdev->recov_in_prog) {
3377                 p_hwfn = QED_LEADING_HWFN(cdev);
3378                 p_ptt = QED_LEADING_HWFN(cdev)->p_main_ptt;
3379
3380                 /* Clear the PF's internal FID_enable in the PXP.
3381                  * In CMT this should only be done for first hw-function, and
3382                  * only after all transactions have stopped for all active
3383                  * hw-functions.
3384                  */
3385                 rc = qed_pglueb_set_pfid_enable(p_hwfn, p_ptt, false);
3386                 if (rc) {
3387                         DP_NOTICE(p_hwfn,
3388                                   "qed_pglueb_set_pfid_enable() failed. rc = %d.\n",
3389                                   rc);
3390                         rc2 = -EINVAL;
3391                 }
3392         }
3393
3394         return rc2;
3395 }
3396
3397 int qed_hw_stop_fastpath(struct qed_dev *cdev)
3398 {
3399         int j;
3400
3401         for_each_hwfn(cdev, j) {
3402                 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
3403                 struct qed_ptt *p_ptt;
3404
3405                 if (IS_VF(cdev)) {
3406                         qed_vf_pf_int_cleanup(p_hwfn);
3407                         continue;
3408                 }
3409                 p_ptt = qed_ptt_acquire(p_hwfn);
3410                 if (!p_ptt)
3411                         return -EAGAIN;
3412
3413                 DP_VERBOSE(p_hwfn,
3414                            NETIF_MSG_IFDOWN, "Shutting down the fastpath\n");
3415
3416                 qed_wr(p_hwfn, p_ptt,
3417                        NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
3418
3419                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
3420                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
3421                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
3422                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
3423                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
3424
3425                 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
3426
3427                 /* Need to wait 1ms to guarantee SBs are cleared */
3428                 usleep_range(1000, 2000);
3429                 qed_ptt_release(p_hwfn, p_ptt);
3430         }
3431
3432         return 0;
3433 }
3434
3435 int qed_hw_start_fastpath(struct qed_hwfn *p_hwfn)
3436 {
3437         struct qed_ptt *p_ptt;
3438
3439         if (IS_VF(p_hwfn->cdev))
3440                 return 0;
3441
3442         p_ptt = qed_ptt_acquire(p_hwfn);
3443         if (!p_ptt)
3444                 return -EAGAIN;
3445
3446         if (p_hwfn->p_rdma_info &&
3447             p_hwfn->p_rdma_info->active && p_hwfn->b_rdma_enabled_in_prs)
3448                 qed_wr(p_hwfn, p_ptt, p_hwfn->rdma_prs_search_reg, 0x1);
3449
3450         /* Re-open incoming traffic */
3451         qed_wr(p_hwfn, p_ptt, NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
3452         qed_ptt_release(p_hwfn, p_ptt);
3453
3454         return 0;
3455 }
3456
3457 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
3458 static void qed_hw_hwfn_free(struct qed_hwfn *p_hwfn)
3459 {
3460         qed_ptt_pool_free(p_hwfn);
3461         kfree(p_hwfn->hw_info.p_igu_info);
3462         p_hwfn->hw_info.p_igu_info = NULL;
3463 }
3464
3465 /* Setup bar access */
3466 static void qed_hw_hwfn_prepare(struct qed_hwfn *p_hwfn)
3467 {
3468         /* clear indirect access */
3469         if (QED_IS_AH(p_hwfn->cdev)) {
3470                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
3471                        PGLUE_B_REG_PGL_ADDR_E8_F0_K2, 0);
3472                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
3473                        PGLUE_B_REG_PGL_ADDR_EC_F0_K2, 0);
3474                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
3475                        PGLUE_B_REG_PGL_ADDR_F0_F0_K2, 0);
3476                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
3477                        PGLUE_B_REG_PGL_ADDR_F4_F0_K2, 0);
3478         } else {
3479                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
3480                        PGLUE_B_REG_PGL_ADDR_88_F0_BB, 0);
3481                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
3482                        PGLUE_B_REG_PGL_ADDR_8C_F0_BB, 0);
3483                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
3484                        PGLUE_B_REG_PGL_ADDR_90_F0_BB, 0);
3485                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
3486                        PGLUE_B_REG_PGL_ADDR_94_F0_BB, 0);
3487         }
3488
3489         /* Clean previous pglue_b errors if such exist */
3490         qed_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt);
3491
3492         /* enable internal target-read */
3493         qed_wr(p_hwfn, p_hwfn->p_main_ptt,
3494                PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
3495 }
3496
3497 static void get_function_id(struct qed_hwfn *p_hwfn)
3498 {
3499         /* ME Register */
3500         p_hwfn->hw_info.opaque_fid = (u16) REG_RD(p_hwfn,
3501                                                   PXP_PF_ME_OPAQUE_ADDR);
3502
3503         p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
3504
3505         p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
3506         p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
3507                                       PXP_CONCRETE_FID_PFID);
3508         p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
3509                                     PXP_CONCRETE_FID_PORT);
3510
3511         DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE,
3512                    "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
3513                    p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
3514 }
3515
3516 static void qed_hw_set_feat(struct qed_hwfn *p_hwfn)
3517 {
3518         u32 *feat_num = p_hwfn->hw_info.feat_num;
3519         struct qed_sb_cnt_info sb_cnt;
3520         u32 non_l2_sbs = 0;
3521
3522         memset(&sb_cnt, 0, sizeof(sb_cnt));
3523         qed_int_get_num_sbs(p_hwfn, &sb_cnt);
3524
3525         if (IS_ENABLED(CONFIG_QED_RDMA) &&
3526             QED_IS_RDMA_PERSONALITY(p_hwfn)) {
3527                 /* Roce CNQ each requires: 1 status block + 1 CNQ. We divide
3528                  * the status blocks equally between L2 / RoCE but with
3529                  * consideration as to how many l2 queues / cnqs we have.
3530                  */
3531                 feat_num[QED_RDMA_CNQ] =
3532                         min_t(u32, sb_cnt.cnt / 2,
3533                               RESC_NUM(p_hwfn, QED_RDMA_CNQ_RAM));
3534
3535                 non_l2_sbs = feat_num[QED_RDMA_CNQ];
3536         }
3537         if (QED_IS_L2_PERSONALITY(p_hwfn)) {
3538                 /* Start by allocating VF queues, then PF's */
3539                 feat_num[QED_VF_L2_QUE] = min_t(u32,
3540                                                 RESC_NUM(p_hwfn, QED_L2_QUEUE),
3541                                                 sb_cnt.iov_cnt);
3542                 feat_num[QED_PF_L2_QUE] = min_t(u32,
3543                                                 sb_cnt.cnt - non_l2_sbs,
3544                                                 RESC_NUM(p_hwfn,
3545                                                          QED_L2_QUEUE) -
3546                                                 FEAT_NUM(p_hwfn,
3547                                                          QED_VF_L2_QUE));
3548         }
3549
3550         if (QED_IS_FCOE_PERSONALITY(p_hwfn))
3551                 feat_num[QED_FCOE_CQ] =  min_t(u32, sb_cnt.cnt,
3552                                                RESC_NUM(p_hwfn,
3553                                                         QED_CMDQS_CQS));
3554
3555         if (QED_IS_ISCSI_PERSONALITY(p_hwfn))
3556                 feat_num[QED_ISCSI_CQ] = min_t(u32, sb_cnt.cnt,
3557                                                RESC_NUM(p_hwfn,
3558                                                         QED_CMDQS_CQS));
3559         DP_VERBOSE(p_hwfn,
3560                    NETIF_MSG_PROBE,
3561                    "#PF_L2_QUEUES=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d FCOE_CQ=%d ISCSI_CQ=%d #SBS=%d\n",
3562                    (int)FEAT_NUM(p_hwfn, QED_PF_L2_QUE),
3563                    (int)FEAT_NUM(p_hwfn, QED_VF_L2_QUE),
3564                    (int)FEAT_NUM(p_hwfn, QED_RDMA_CNQ),
3565                    (int)FEAT_NUM(p_hwfn, QED_FCOE_CQ),
3566                    (int)FEAT_NUM(p_hwfn, QED_ISCSI_CQ),
3567                    (int)sb_cnt.cnt);
3568 }
3569
3570 const char *qed_hw_get_resc_name(enum qed_resources res_id)
3571 {
3572         switch (res_id) {
3573         case QED_L2_QUEUE:
3574                 return "L2_QUEUE";
3575         case QED_VPORT:
3576                 return "VPORT";
3577         case QED_RSS_ENG:
3578                 return "RSS_ENG";
3579         case QED_PQ:
3580                 return "PQ";
3581         case QED_RL:
3582                 return "RL";
3583         case QED_MAC:
3584                 return "MAC";
3585         case QED_VLAN:
3586                 return "VLAN";
3587         case QED_RDMA_CNQ_RAM:
3588                 return "RDMA_CNQ_RAM";
3589         case QED_ILT:
3590                 return "ILT";
3591         case QED_LL2_RAM_QUEUE:
3592                 return "LL2_RAM_QUEUE";
3593         case QED_LL2_CTX_QUEUE:
3594                 return "LL2_CTX_QUEUE";
3595         case QED_CMDQS_CQS:
3596                 return "CMDQS_CQS";
3597         case QED_RDMA_STATS_QUEUE:
3598                 return "RDMA_STATS_QUEUE";
3599         case QED_BDQ:
3600                 return "BDQ";
3601         case QED_SB:
3602                 return "SB";
3603         default:
3604                 return "UNKNOWN_RESOURCE";
3605         }
3606 }
3607
3608 static int
3609 __qed_hw_set_soft_resc_size(struct qed_hwfn *p_hwfn,
3610                             struct qed_ptt *p_ptt,
3611                             enum qed_resources res_id,
3612                             u32 resc_max_val, u32 *p_mcp_resp)
3613 {
3614         int rc;
3615
3616         rc = qed_mcp_set_resc_max_val(p_hwfn, p_ptt, res_id,
3617                                       resc_max_val, p_mcp_resp);
3618         if (rc) {
3619                 DP_NOTICE(p_hwfn,
3620                           "MFW response failure for a max value setting of resource %d [%s]\n",
3621                           res_id, qed_hw_get_resc_name(res_id));
3622                 return rc;
3623         }
3624
3625         if (*p_mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK)
3626                 DP_INFO(p_hwfn,
3627                         "Failed to set the max value of resource %d [%s]. mcp_resp = 0x%08x.\n",
3628                         res_id, qed_hw_get_resc_name(res_id), *p_mcp_resp);
3629
3630         return 0;
3631 }
3632
3633 static u32 qed_hsi_def_val[][MAX_CHIP_IDS] = {
3634         {MAX_NUM_VFS_BB, MAX_NUM_VFS_K2},
3635         {MAX_NUM_L2_QUEUES_BB, MAX_NUM_L2_QUEUES_K2},
3636         {MAX_NUM_PORTS_BB, MAX_NUM_PORTS_K2},
3637         {MAX_SB_PER_PATH_BB, MAX_SB_PER_PATH_K2,},
3638         {MAX_NUM_PFS_BB, MAX_NUM_PFS_K2},
3639         {MAX_NUM_VPORTS_BB, MAX_NUM_VPORTS_K2},
3640         {ETH_RSS_ENGINE_NUM_BB, ETH_RSS_ENGINE_NUM_K2},
3641         {MAX_QM_TX_QUEUES_BB, MAX_QM_TX_QUEUES_K2},
3642         {PXP_NUM_ILT_RECORDS_BB, PXP_NUM_ILT_RECORDS_K2},
3643         {RDMA_NUM_STATISTIC_COUNTERS_BB, RDMA_NUM_STATISTIC_COUNTERS_K2},
3644         {MAX_QM_GLOBAL_RLS, MAX_QM_GLOBAL_RLS},
3645         {PBF_MAX_CMD_LINES, PBF_MAX_CMD_LINES},
3646         {BTB_MAX_BLOCKS_BB, BTB_MAX_BLOCKS_K2},
3647 };
3648
3649 u32 qed_get_hsi_def_val(struct qed_dev *cdev, enum qed_hsi_def_type type)
3650 {
3651         enum chip_ids chip_id = QED_IS_BB(cdev) ? CHIP_BB : CHIP_K2;
3652
3653         if (type >= QED_NUM_HSI_DEFS) {
3654                 DP_ERR(cdev, "Unexpected HSI definition type [%d]\n", type);
3655                 return 0;
3656         }
3657
3658         return qed_hsi_def_val[type][chip_id];
3659 }
3660 static int
3661 qed_hw_set_soft_resc_size(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
3662 {
3663         u32 resc_max_val, mcp_resp;
3664         u8 res_id;
3665         int rc;
3666         for (res_id = 0; res_id < QED_MAX_RESC; res_id++) {
3667                 switch (res_id) {
3668                 case QED_LL2_RAM_QUEUE:
3669                         resc_max_val = MAX_NUM_LL2_RX_RAM_QUEUES;
3670                         break;
3671                 case QED_LL2_CTX_QUEUE:
3672                         resc_max_val = MAX_NUM_LL2_RX_CTX_QUEUES;
3673                         break;
3674                 case QED_RDMA_CNQ_RAM:
3675                         /* No need for a case for QED_CMDQS_CQS since
3676                          * CNQ/CMDQS are the same resource.
3677                          */
3678                         resc_max_val = NUM_OF_GLOBAL_QUEUES;
3679                         break;
3680                 case QED_RDMA_STATS_QUEUE:
3681                         resc_max_val =
3682                             NUM_OF_RDMA_STATISTIC_COUNTERS(p_hwfn->cdev);
3683                         break;
3684                 case QED_BDQ:
3685                         resc_max_val = BDQ_NUM_RESOURCES;
3686                         break;
3687                 default:
3688                         continue;
3689                 }
3690
3691                 rc = __qed_hw_set_soft_resc_size(p_hwfn, p_ptt, res_id,
3692                                                  resc_max_val, &mcp_resp);
3693                 if (rc)
3694                         return rc;
3695
3696                 /* There's no point to continue to the next resource if the
3697                  * command is not supported by the MFW.
3698                  * We do continue if the command is supported but the resource
3699                  * is unknown to the MFW. Such a resource will be later
3700                  * configured with the default allocation values.
3701                  */
3702                 if (mcp_resp == FW_MSG_CODE_UNSUPPORTED)
3703                         return -EINVAL;
3704         }
3705
3706         return 0;
3707 }
3708
3709 static
3710 int qed_hw_get_dflt_resc(struct qed_hwfn *p_hwfn,
3711                          enum qed_resources res_id,
3712                          u32 *p_resc_num, u32 *p_resc_start)
3713 {
3714         u8 num_funcs = p_hwfn->num_funcs_on_engine;
3715         struct qed_dev *cdev = p_hwfn->cdev;
3716
3717         switch (res_id) {
3718         case QED_L2_QUEUE:
3719                 *p_resc_num = NUM_OF_L2_QUEUES(cdev) / num_funcs;
3720                 break;
3721         case QED_VPORT:
3722                 *p_resc_num = NUM_OF_VPORTS(cdev) / num_funcs;
3723                 break;
3724         case QED_RSS_ENG:
3725                 *p_resc_num = NUM_OF_RSS_ENGINES(cdev) / num_funcs;
3726                 break;
3727         case QED_PQ:
3728                 *p_resc_num = NUM_OF_QM_TX_QUEUES(cdev) / num_funcs;
3729                 *p_resc_num &= ~0x7;    /* The granularity of the PQs is 8 */
3730                 break;
3731         case QED_RL:
3732                 *p_resc_num = NUM_OF_QM_GLOBAL_RLS(cdev) / num_funcs;
3733                 break;
3734         case QED_MAC:
3735         case QED_VLAN:
3736                 /* Each VFC resource can accommodate both a MAC and a VLAN */
3737                 *p_resc_num = ETH_NUM_MAC_FILTERS / num_funcs;
3738                 break;
3739         case QED_ILT:
3740                 *p_resc_num = NUM_OF_PXP_ILT_RECORDS(cdev) / num_funcs;
3741                 break;
3742         case QED_LL2_RAM_QUEUE:
3743                 *p_resc_num = MAX_NUM_LL2_RX_RAM_QUEUES / num_funcs;
3744                 break;
3745         case QED_LL2_CTX_QUEUE:
3746                 *p_resc_num = MAX_NUM_LL2_RX_CTX_QUEUES / num_funcs;
3747                 break;
3748         case QED_RDMA_CNQ_RAM:
3749         case QED_CMDQS_CQS:
3750                 /* CNQ/CMDQS are the same resource */
3751                 *p_resc_num = NUM_OF_GLOBAL_QUEUES / num_funcs;
3752                 break;
3753         case QED_RDMA_STATS_QUEUE:
3754                 *p_resc_num = NUM_OF_RDMA_STATISTIC_COUNTERS(cdev) / num_funcs;
3755                 break;
3756         case QED_BDQ:
3757                 if (p_hwfn->hw_info.personality != QED_PCI_ISCSI &&
3758                     p_hwfn->hw_info.personality != QED_PCI_FCOE)
3759                         *p_resc_num = 0;
3760                 else
3761                         *p_resc_num = 1;
3762                 break;
3763         case QED_SB:
3764                 /* Since we want its value to reflect whether MFW supports
3765                  * the new scheme, have a default of 0.
3766                  */
3767                 *p_resc_num = 0;
3768                 break;
3769         default:
3770                 return -EINVAL;
3771         }
3772
3773         switch (res_id) {
3774         case QED_BDQ:
3775                 if (!*p_resc_num)
3776                         *p_resc_start = 0;
3777                 else if (p_hwfn->cdev->num_ports_in_engine == 4)
3778                         *p_resc_start = p_hwfn->port_id;
3779                 else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI)
3780                         *p_resc_start = p_hwfn->port_id;
3781                 else if (p_hwfn->hw_info.personality == QED_PCI_FCOE)
3782                         *p_resc_start = p_hwfn->port_id + 2;
3783                 break;
3784         default:
3785                 *p_resc_start = *p_resc_num * p_hwfn->enabled_func_idx;
3786                 break;
3787         }
3788
3789         return 0;
3790 }
3791
3792 static int __qed_hw_set_resc_info(struct qed_hwfn *p_hwfn,
3793                                   enum qed_resources res_id)
3794 {
3795         u32 dflt_resc_num = 0, dflt_resc_start = 0;
3796         u32 mcp_resp, *p_resc_num, *p_resc_start;
3797         int rc;
3798
3799         p_resc_num = &RESC_NUM(p_hwfn, res_id);
3800         p_resc_start = &RESC_START(p_hwfn, res_id);
3801
3802         rc = qed_hw_get_dflt_resc(p_hwfn, res_id, &dflt_resc_num,
3803                                   &dflt_resc_start);
3804         if (rc) {
3805                 DP_ERR(p_hwfn,
3806                        "Failed to get default amount for resource %d [%s]\n",
3807                        res_id, qed_hw_get_resc_name(res_id));
3808                 return rc;
3809         }
3810
3811         rc = qed_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, res_id,
3812                                    &mcp_resp, p_resc_num, p_resc_start);
3813         if (rc) {
3814                 DP_NOTICE(p_hwfn,
3815                           "MFW response failure for an allocation request for resource %d [%s]\n",
3816                           res_id, qed_hw_get_resc_name(res_id));
3817                 return rc;
3818         }
3819
3820         /* Default driver values are applied in the following cases:
3821          * - The resource allocation MB command is not supported by the MFW
3822          * - There is an internal error in the MFW while processing the request
3823          * - The resource ID is unknown to the MFW
3824          */
3825         if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK) {
3826                 DP_INFO(p_hwfn,
3827                         "Failed to receive allocation info for resource %d [%s]. mcp_resp = 0x%x. Applying default values [%d,%d].\n",
3828                         res_id,
3829                         qed_hw_get_resc_name(res_id),
3830                         mcp_resp, dflt_resc_num, dflt_resc_start);
3831                 *p_resc_num = dflt_resc_num;
3832                 *p_resc_start = dflt_resc_start;
3833                 goto out;
3834         }
3835
3836 out:
3837         /* PQs have to divide by 8 [that's the HW granularity].
3838          * Reduce number so it would fit.
3839          */
3840         if ((res_id == QED_PQ) && ((*p_resc_num % 8) || (*p_resc_start % 8))) {
3841                 DP_INFO(p_hwfn,
3842                         "PQs need to align by 8; Number %08x --> %08x, Start %08x --> %08x\n",
3843                         *p_resc_num,
3844                         (*p_resc_num) & ~0x7,
3845                         *p_resc_start, (*p_resc_start) & ~0x7);
3846                 *p_resc_num &= ~0x7;
3847                 *p_resc_start &= ~0x7;
3848         }
3849
3850         return 0;
3851 }
3852
3853 static int qed_hw_set_resc_info(struct qed_hwfn *p_hwfn)
3854 {
3855         int rc;
3856         u8 res_id;
3857
3858         for (res_id = 0; res_id < QED_MAX_RESC; res_id++) {
3859                 rc = __qed_hw_set_resc_info(p_hwfn, res_id);
3860                 if (rc)
3861                         return rc;
3862         }
3863
3864         return 0;
3865 }
3866
3867 static int qed_hw_get_ppfid_bitmap(struct qed_hwfn *p_hwfn,
3868                                    struct qed_ptt *p_ptt)
3869 {
3870         struct qed_dev *cdev = p_hwfn->cdev;
3871         u8 native_ppfid_idx;
3872         int rc;
3873
3874         /* Calculation of BB/AH is different for native_ppfid_idx */
3875         if (QED_IS_BB(cdev))
3876                 native_ppfid_idx = p_hwfn->rel_pf_id;
3877         else
3878                 native_ppfid_idx = p_hwfn->rel_pf_id /
3879                     cdev->num_ports_in_engine;
3880
3881         rc = qed_mcp_get_ppfid_bitmap(p_hwfn, p_ptt);
3882         if (rc != 0 && rc != -EOPNOTSUPP)
3883                 return rc;
3884         else if (rc == -EOPNOTSUPP)
3885                 cdev->ppfid_bitmap = 0x1 << native_ppfid_idx;
3886
3887         if (!(cdev->ppfid_bitmap & (0x1 << native_ppfid_idx))) {
3888                 DP_INFO(p_hwfn,
3889                         "Fix the PPFID bitmap to include the native PPFID [native_ppfid_idx %hhd, orig_bitmap 0x%hhx]\n",
3890                         native_ppfid_idx, cdev->ppfid_bitmap);
3891                 cdev->ppfid_bitmap = 0x1 << native_ppfid_idx;
3892         }
3893
3894         return 0;
3895 }
3896
3897 static int qed_hw_get_resc(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
3898 {
3899         struct qed_resc_unlock_params resc_unlock_params;
3900         struct qed_resc_lock_params resc_lock_params;
3901         bool b_ah = QED_IS_AH(p_hwfn->cdev);
3902         u8 res_id;
3903         int rc;
3904
3905         /* Setting the max values of the soft resources and the following
3906          * resources allocation queries should be atomic. Since several PFs can
3907          * run in parallel - a resource lock is needed.
3908          * If either the resource lock or resource set value commands are not
3909          * supported - skip the the max values setting, release the lock if
3910          * needed, and proceed to the queries. Other failures, including a
3911          * failure to acquire the lock, will cause this function to fail.
3912          */
3913         qed_mcp_resc_lock_default_init(&resc_lock_params, &resc_unlock_params,
3914                                        QED_RESC_LOCK_RESC_ALLOC, false);
3915
3916         rc = qed_mcp_resc_lock(p_hwfn, p_ptt, &resc_lock_params);
3917         if (rc && rc != -EINVAL) {
3918                 return rc;
3919         } else if (rc == -EINVAL) {
3920                 DP_INFO(p_hwfn,
3921                         "Skip the max values setting of the soft resources since the resource lock is not supported by the MFW\n");
3922         } else if (!rc && !resc_lock_params.b_granted) {
3923                 DP_NOTICE(p_hwfn,
3924                           "Failed to acquire the resource lock for the resource allocation commands\n");
3925                 return -EBUSY;
3926         } else {
3927                 rc = qed_hw_set_soft_resc_size(p_hwfn, p_ptt);
3928                 if (rc && rc != -EINVAL) {
3929                         DP_NOTICE(p_hwfn,
3930                                   "Failed to set the max values of the soft resources\n");
3931                         goto unlock_and_exit;
3932                 } else if (rc == -EINVAL) {
3933                         DP_INFO(p_hwfn,
3934                                 "Skip the max values setting of the soft resources since it is not supported by the MFW\n");
3935                         rc = qed_mcp_resc_unlock(p_hwfn, p_ptt,
3936                                                  &resc_unlock_params);
3937                         if (rc)
3938                                 DP_INFO(p_hwfn,
3939                                         "Failed to release the resource lock for the resource allocation commands\n");
3940                 }
3941         }
3942
3943         rc = qed_hw_set_resc_info(p_hwfn);
3944         if (rc)
3945                 goto unlock_and_exit;
3946
3947         if (resc_lock_params.b_granted && !resc_unlock_params.b_released) {
3948                 rc = qed_mcp_resc_unlock(p_hwfn, p_ptt, &resc_unlock_params);
3949                 if (rc)
3950                         DP_INFO(p_hwfn,
3951                                 "Failed to release the resource lock for the resource allocation commands\n");
3952         }
3953
3954         /* PPFID bitmap */
3955         if (IS_LEAD_HWFN(p_hwfn)) {
3956                 rc = qed_hw_get_ppfid_bitmap(p_hwfn, p_ptt);
3957                 if (rc)
3958                         return rc;
3959         }
3960
3961         /* Sanity for ILT */
3962         if ((b_ah && (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_K2)) ||
3963             (!b_ah && (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_BB))) {
3964                 DP_NOTICE(p_hwfn, "Can't assign ILT pages [%08x,...,%08x]\n",
3965                           RESC_START(p_hwfn, QED_ILT),
3966                           RESC_END(p_hwfn, QED_ILT) - 1);
3967                 return -EINVAL;
3968         }
3969
3970         /* This will also learn the number of SBs from MFW */
3971         if (qed_int_igu_reset_cam(p_hwfn, p_ptt))
3972                 return -EINVAL;
3973
3974         qed_hw_set_feat(p_hwfn);
3975
3976         for (res_id = 0; res_id < QED_MAX_RESC; res_id++)
3977                 DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE, "%s = %d start = %d\n",
3978                            qed_hw_get_resc_name(res_id),
3979                            RESC_NUM(p_hwfn, res_id),
3980                            RESC_START(p_hwfn, res_id));
3981
3982         return 0;
3983
3984 unlock_and_exit:
3985         if (resc_lock_params.b_granted && !resc_unlock_params.b_released)
3986                 qed_mcp_resc_unlock(p_hwfn, p_ptt, &resc_unlock_params);
3987         return rc;
3988 }
3989
3990 static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
3991 {
3992         u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
3993         u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg;
3994         struct qed_mcp_link_capabilities *p_caps;
3995         struct qed_mcp_link_params *link;
3996
3997         /* Read global nvm_cfg address */
3998         nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
3999
4000         /* Verify MCP has initialized it */
4001         if (!nvm_cfg_addr) {
4002                 DP_NOTICE(p_hwfn, "Shared memory not initialized\n");
4003                 return -EINVAL;
4004         }
4005
4006         /* Read nvm_cfg1  (Notice this is just offset, and not offsize (TBD) */
4007         nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
4008
4009         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
4010                offsetof(struct nvm_cfg1, glob) +
4011                offsetof(struct nvm_cfg1_glob, core_cfg);
4012
4013         core_cfg = qed_rd(p_hwfn, p_ptt, addr);
4014
4015         switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
4016                 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
4017         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
4018                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X40G;
4019                 break;
4020         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
4021                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X50G;
4022                 break;
4023         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
4024                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X100G;
4025                 break;
4026         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
4027                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_F;
4028                 break;
4029         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
4030                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_E;
4031                 break;
4032         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
4033                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X20G;
4034                 break;
4035         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
4036                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X40G;
4037                 break;
4038         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
4039                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X25G;
4040                 break;
4041         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G:
4042                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X10G;
4043                 break;
4044         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
4045                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X25G;
4046                 break;
4047         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G:
4048                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X25G;
4049                 break;
4050         default:
4051                 DP_NOTICE(p_hwfn, "Unknown port mode in 0x%08x\n", core_cfg);
4052                 break;
4053         }
4054
4055         /* Read default link configuration */
4056         link = &p_hwfn->mcp_info->link_input;
4057         p_caps = &p_hwfn->mcp_info->link_capabilities;
4058         port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
4059                         offsetof(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
4060         link_temp = qed_rd(p_hwfn, p_ptt,
4061                            port_cfg_addr +
4062                            offsetof(struct nvm_cfg1_port, speed_cap_mask));
4063         link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
4064         link->speed.advertised_speeds = link_temp;
4065
4066         link_temp = link->speed.advertised_speeds;
4067         p_hwfn->mcp_info->link_capabilities.speed_capabilities = link_temp;
4068
4069         link_temp = qed_rd(p_hwfn, p_ptt,
4070                            port_cfg_addr +
4071                            offsetof(struct nvm_cfg1_port, link_settings));
4072         switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
4073                 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
4074         case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
4075                 link->speed.autoneg = true;
4076                 break;
4077         case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
4078                 link->speed.forced_speed = 1000;
4079                 break;
4080         case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
4081                 link->speed.forced_speed = 10000;
4082                 break;
4083         case NVM_CFG1_PORT_DRV_LINK_SPEED_20G:
4084                 link->speed.forced_speed = 20000;
4085                 break;
4086         case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
4087                 link->speed.forced_speed = 25000;
4088                 break;
4089         case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
4090                 link->speed.forced_speed = 40000;
4091                 break;
4092         case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
4093                 link->speed.forced_speed = 50000;
4094                 break;
4095         case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
4096                 link->speed.forced_speed = 100000;
4097                 break;
4098         default:
4099                 DP_NOTICE(p_hwfn, "Unknown Speed in 0x%08x\n", link_temp);
4100         }
4101
4102         p_hwfn->mcp_info->link_capabilities.default_speed_autoneg =
4103                 link->speed.autoneg;
4104
4105         link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
4106         link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
4107         link->pause.autoneg = !!(link_temp &
4108                                  NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
4109         link->pause.forced_rx = !!(link_temp &
4110                                    NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
4111         link->pause.forced_tx = !!(link_temp &
4112                                    NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
4113         link->loopback_mode = 0;
4114
4115         if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE) {
4116                 link_temp = qed_rd(p_hwfn, p_ptt, port_cfg_addr +
4117                                    offsetof(struct nvm_cfg1_port, ext_phy));
4118                 link_temp &= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK;
4119                 link_temp >>= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET;
4120                 p_caps->default_eee = QED_MCP_EEE_ENABLED;
4121                 link->eee.enable = true;
4122                 switch (link_temp) {
4123                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED:
4124                         p_caps->default_eee = QED_MCP_EEE_DISABLED;
4125                         link->eee.enable = false;
4126                         break;
4127                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED:
4128                         p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_BALANCED_TIME;
4129                         break;
4130                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE:
4131                         p_caps->eee_lpi_timer =
4132                             EEE_TX_TIMER_USEC_AGGRESSIVE_TIME;
4133                         break;
4134                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY:
4135                         p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_LATENCY_TIME;
4136                         break;
4137                 }
4138
4139                 link->eee.tx_lpi_timer = p_caps->eee_lpi_timer;
4140                 link->eee.tx_lpi_enable = link->eee.enable;
4141                 link->eee.adv_caps = QED_EEE_1G_ADV | QED_EEE_10G_ADV;
4142         } else {
4143                 p_caps->default_eee = QED_MCP_EEE_UNSUPPORTED;
4144         }
4145
4146         DP_VERBOSE(p_hwfn,
4147                    NETIF_MSG_LINK,
4148                    "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x EEE: %02x [%08x usec]\n",
4149                    link->speed.forced_speed,
4150                    link->speed.advertised_speeds,
4151                    link->speed.autoneg,
4152                    link->pause.autoneg,
4153                    p_caps->default_eee, p_caps->eee_lpi_timer);
4154
4155         if (IS_LEAD_HWFN(p_hwfn)) {
4156                 struct qed_dev *cdev = p_hwfn->cdev;
4157
4158                 /* Read Multi-function information from shmem */
4159                 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
4160                        offsetof(struct nvm_cfg1, glob) +
4161                        offsetof(struct nvm_cfg1_glob, generic_cont0);
4162
4163                 generic_cont0 = qed_rd(p_hwfn, p_ptt, addr);
4164
4165                 mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
4166                           NVM_CFG1_GLOB_MF_MODE_OFFSET;
4167
4168                 switch (mf_mode) {
4169                 case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
4170                         cdev->mf_bits = BIT(QED_MF_OVLAN_CLSS);
4171                         break;
4172                 case NVM_CFG1_GLOB_MF_MODE_UFP:
4173                         cdev->mf_bits = BIT(QED_MF_OVLAN_CLSS) |
4174                                         BIT(QED_MF_LLH_PROTO_CLSS) |
4175                                         BIT(QED_MF_UFP_SPECIFIC) |
4176                                         BIT(QED_MF_8021Q_TAGGING) |
4177                                         BIT(QED_MF_DONT_ADD_VLAN0_TAG);
4178                         break;
4179                 case NVM_CFG1_GLOB_MF_MODE_BD:
4180                         cdev->mf_bits = BIT(QED_MF_OVLAN_CLSS) |
4181                                         BIT(QED_MF_LLH_PROTO_CLSS) |
4182                                         BIT(QED_MF_8021AD_TAGGING) |
4183                                         BIT(QED_MF_DONT_ADD_VLAN0_TAG);
4184                         break;
4185                 case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
4186                         cdev->mf_bits = BIT(QED_MF_LLH_MAC_CLSS) |
4187                                         BIT(QED_MF_LLH_PROTO_CLSS) |
4188                                         BIT(QED_MF_LL2_NON_UNICAST) |
4189                                         BIT(QED_MF_INTER_PF_SWITCH);
4190                         break;
4191                 case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
4192                         cdev->mf_bits = BIT(QED_MF_LLH_MAC_CLSS) |
4193                                         BIT(QED_MF_LLH_PROTO_CLSS) |
4194                                         BIT(QED_MF_LL2_NON_UNICAST);
4195                         if (QED_IS_BB(p_hwfn->cdev))
4196                                 cdev->mf_bits |= BIT(QED_MF_NEED_DEF_PF);
4197                         break;
4198                 }
4199
4200                 DP_INFO(p_hwfn, "Multi function mode is 0x%lx\n",
4201                         cdev->mf_bits);
4202         }
4203
4204         DP_INFO(p_hwfn, "Multi function mode is 0x%lx\n",
4205                 p_hwfn->cdev->mf_bits);
4206
4207         /* Read device capabilities information from shmem */
4208         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
4209                 offsetof(struct nvm_cfg1, glob) +
4210                 offsetof(struct nvm_cfg1_glob, device_capabilities);
4211
4212         device_capabilities = qed_rd(p_hwfn, p_ptt, addr);
4213         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
4214                 __set_bit(QED_DEV_CAP_ETH,
4215                           &p_hwfn->hw_info.device_capabilities);
4216         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE)
4217                 __set_bit(QED_DEV_CAP_FCOE,
4218                           &p_hwfn->hw_info.device_capabilities);
4219         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
4220                 __set_bit(QED_DEV_CAP_ISCSI,
4221                           &p_hwfn->hw_info.device_capabilities);
4222         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
4223                 __set_bit(QED_DEV_CAP_ROCE,
4224                           &p_hwfn->hw_info.device_capabilities);
4225
4226         return qed_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
4227 }
4228
4229 static void qed_get_num_funcs(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
4230 {
4231         u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
4232         u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
4233         struct qed_dev *cdev = p_hwfn->cdev;
4234
4235         num_funcs = QED_IS_AH(cdev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB;
4236
4237         /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
4238          * in the other bits are selected.
4239          * Bits 1-15 are for functions 1-15, respectively, and their value is
4240          * '0' only for enabled functions (function 0 always exists and
4241          * enabled).
4242          * In case of CMT, only the "even" functions are enabled, and thus the
4243          * number of functions for both hwfns is learnt from the same bits.
4244          */
4245         reg_function_hide = qed_rd(p_hwfn, p_ptt, MISCS_REG_FUNCTION_HIDE);
4246
4247         if (reg_function_hide & 0x1) {
4248                 if (QED_IS_BB(cdev)) {
4249                         if (QED_PATH_ID(p_hwfn) && cdev->num_hwfns == 1) {
4250                                 num_funcs = 0;
4251                                 eng_mask = 0xaaaa;
4252                         } else {
4253                                 num_funcs = 1;
4254                                 eng_mask = 0x5554;
4255                         }
4256                 } else {
4257                         num_funcs = 1;
4258                         eng_mask = 0xfffe;
4259                 }
4260
4261                 /* Get the number of the enabled functions on the engine */
4262                 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
4263                 while (tmp) {
4264                         if (tmp & 0x1)
4265                                 num_funcs++;
4266                         tmp >>= 0x1;
4267                 }
4268
4269                 /* Get the PF index within the enabled functions */
4270                 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
4271                 tmp = reg_function_hide & eng_mask & low_pfs_mask;
4272                 while (tmp) {
4273                         if (tmp & 0x1)
4274                                 enabled_func_idx--;
4275                         tmp >>= 0x1;
4276                 }
4277         }
4278
4279         p_hwfn->num_funcs_on_engine = num_funcs;
4280         p_hwfn->enabled_func_idx = enabled_func_idx;
4281
4282         DP_VERBOSE(p_hwfn,
4283                    NETIF_MSG_PROBE,
4284                    "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n",
4285                    p_hwfn->rel_pf_id,
4286                    p_hwfn->abs_pf_id,
4287                    p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);
4288 }
4289
4290 static void qed_hw_info_port_num(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
4291 {
4292         u32 addr, global_offsize, global_addr, port_mode;
4293         struct qed_dev *cdev = p_hwfn->cdev;
4294
4295         /* In CMT there is always only one port */
4296         if (cdev->num_hwfns > 1) {
4297                 cdev->num_ports_in_engine = 1;
4298                 cdev->num_ports = 1;
4299                 return;
4300         }
4301
4302         /* Determine the number of ports per engine */
4303         port_mode = qed_rd(p_hwfn, p_ptt, MISC_REG_PORT_MODE);
4304         switch (port_mode) {
4305         case 0x0:
4306                 cdev->num_ports_in_engine = 1;
4307                 break;
4308         case 0x1:
4309                 cdev->num_ports_in_engine = 2;
4310                 break;
4311         case 0x2:
4312                 cdev->num_ports_in_engine = 4;
4313                 break;
4314         default:
4315                 DP_NOTICE(p_hwfn, "Unknown port mode 0x%08x\n", port_mode);
4316                 cdev->num_ports_in_engine = 1;  /* Default to something */
4317                 break;
4318         }
4319
4320         /* Get the total number of ports of the device */
4321         addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
4322                                     PUBLIC_GLOBAL);
4323         global_offsize = qed_rd(p_hwfn, p_ptt, addr);
4324         global_addr = SECTION_ADDR(global_offsize, 0);
4325         addr = global_addr + offsetof(struct public_global, max_ports);
4326         cdev->num_ports = (u8)qed_rd(p_hwfn, p_ptt, addr);
4327 }
4328
4329 static void qed_get_eee_caps(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
4330 {
4331         struct qed_mcp_link_capabilities *p_caps;
4332         u32 eee_status;
4333
4334         p_caps = &p_hwfn->mcp_info->link_capabilities;
4335         if (p_caps->default_eee == QED_MCP_EEE_UNSUPPORTED)
4336                 return;
4337
4338         p_caps->eee_speed_caps = 0;
4339         eee_status = qed_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
4340                             offsetof(struct public_port, eee_status));
4341         eee_status = (eee_status & EEE_SUPPORTED_SPEED_MASK) >>
4342                         EEE_SUPPORTED_SPEED_OFFSET;
4343
4344         if (eee_status & EEE_1G_SUPPORTED)
4345                 p_caps->eee_speed_caps |= QED_EEE_1G_ADV;
4346         if (eee_status & EEE_10G_ADV)
4347                 p_caps->eee_speed_caps |= QED_EEE_10G_ADV;
4348 }
4349
4350 static int
4351 qed_get_hw_info(struct qed_hwfn *p_hwfn,
4352                 struct qed_ptt *p_ptt,
4353                 enum qed_pci_personality personality)
4354 {
4355         int rc;
4356
4357         /* Since all information is common, only first hwfns should do this */
4358         if (IS_LEAD_HWFN(p_hwfn)) {
4359                 rc = qed_iov_hw_info(p_hwfn);
4360                 if (rc)
4361                         return rc;
4362         }
4363
4364         if (IS_LEAD_HWFN(p_hwfn))
4365                 qed_hw_info_port_num(p_hwfn, p_ptt);
4366
4367         qed_mcp_get_capabilities(p_hwfn, p_ptt);
4368
4369         qed_hw_get_nvm_info(p_hwfn, p_ptt);
4370
4371         rc = qed_int_igu_read_cam(p_hwfn, p_ptt);
4372         if (rc)
4373                 return rc;
4374
4375         if (qed_mcp_is_init(p_hwfn))
4376                 ether_addr_copy(p_hwfn->hw_info.hw_mac_addr,
4377                                 p_hwfn->mcp_info->func_info.mac);
4378         else
4379                 eth_random_addr(p_hwfn->hw_info.hw_mac_addr);
4380
4381         if (qed_mcp_is_init(p_hwfn)) {
4382                 if (p_hwfn->mcp_info->func_info.ovlan != QED_MCP_VLAN_UNSET)
4383                         p_hwfn->hw_info.ovlan =
4384                                 p_hwfn->mcp_info->func_info.ovlan;
4385
4386                 qed_mcp_cmd_port_init(p_hwfn, p_ptt);
4387
4388                 qed_get_eee_caps(p_hwfn, p_ptt);
4389
4390                 qed_mcp_read_ufp_config(p_hwfn, p_ptt);
4391         }
4392
4393         if (qed_mcp_is_init(p_hwfn)) {
4394                 enum qed_pci_personality protocol;
4395
4396                 protocol = p_hwfn->mcp_info->func_info.protocol;
4397                 p_hwfn->hw_info.personality = protocol;
4398         }
4399
4400         if (QED_IS_ROCE_PERSONALITY(p_hwfn))
4401                 p_hwfn->hw_info.multi_tc_roce_en = true;
4402
4403         p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2;
4404         p_hwfn->hw_info.num_active_tc = 1;
4405
4406         qed_get_num_funcs(p_hwfn, p_ptt);
4407
4408         if (qed_mcp_is_init(p_hwfn))
4409                 p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu;
4410
4411         return qed_hw_get_resc(p_hwfn, p_ptt);
4412 }
4413
4414 static int qed_get_dev_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
4415 {
4416         struct qed_dev *cdev = p_hwfn->cdev;
4417         u16 device_id_mask;
4418         u32 tmp;
4419
4420         /* Read Vendor Id / Device Id */
4421         pci_read_config_word(cdev->pdev, PCI_VENDOR_ID, &cdev->vendor_id);
4422         pci_read_config_word(cdev->pdev, PCI_DEVICE_ID, &cdev->device_id);
4423
4424         /* Determine type */
4425         device_id_mask = cdev->device_id & QED_DEV_ID_MASK;
4426         switch (device_id_mask) {
4427         case QED_DEV_ID_MASK_BB:
4428                 cdev->type = QED_DEV_TYPE_BB;
4429                 break;
4430         case QED_DEV_ID_MASK_AH:
4431                 cdev->type = QED_DEV_TYPE_AH;
4432                 break;
4433         default:
4434                 DP_NOTICE(p_hwfn, "Unknown device id 0x%x\n", cdev->device_id);
4435                 return -EBUSY;
4436         }
4437
4438         cdev->chip_num = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_NUM);
4439         cdev->chip_rev = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_REV);
4440
4441         MASK_FIELD(CHIP_REV, cdev->chip_rev);
4442
4443         /* Learn number of HW-functions */
4444         tmp = qed_rd(p_hwfn, p_ptt, MISCS_REG_CMT_ENABLED_FOR_PAIR);
4445
4446         if (tmp & (1 << p_hwfn->rel_pf_id)) {
4447                 DP_NOTICE(cdev->hwfns, "device in CMT mode\n");
4448                 cdev->num_hwfns = 2;
4449         } else {
4450                 cdev->num_hwfns = 1;
4451         }
4452
4453         cdev->chip_bond_id = qed_rd(p_hwfn, p_ptt,
4454                                     MISCS_REG_CHIP_TEST_REG) >> 4;
4455         MASK_FIELD(CHIP_BOND_ID, cdev->chip_bond_id);
4456         cdev->chip_metal = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_METAL);
4457         MASK_FIELD(CHIP_METAL, cdev->chip_metal);
4458
4459         DP_INFO(cdev->hwfns,
4460                 "Chip details - %s %c%d, Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n",
4461                 QED_IS_BB(cdev) ? "BB" : "AH",
4462                 'A' + cdev->chip_rev,
4463                 (int)cdev->chip_metal,
4464                 cdev->chip_num, cdev->chip_rev,
4465                 cdev->chip_bond_id, cdev->chip_metal);
4466
4467         return 0;
4468 }
4469
4470 static void qed_nvm_info_free(struct qed_hwfn *p_hwfn)
4471 {
4472         kfree(p_hwfn->nvm_info.image_att);
4473         p_hwfn->nvm_info.image_att = NULL;
4474 }
4475
4476 static int qed_hw_prepare_single(struct qed_hwfn *p_hwfn,
4477                                  void __iomem *p_regview,
4478                                  void __iomem *p_doorbells,
4479                                  u64 db_phys_addr,
4480                                  enum qed_pci_personality personality)
4481 {
4482         struct qed_dev *cdev = p_hwfn->cdev;
4483         int rc = 0;
4484
4485         /* Split PCI bars evenly between hwfns */
4486         p_hwfn->regview = p_regview;
4487         p_hwfn->doorbells = p_doorbells;
4488         p_hwfn->db_phys_addr = db_phys_addr;
4489
4490         if (IS_VF(p_hwfn->cdev))
4491                 return qed_vf_hw_prepare(p_hwfn);
4492
4493         /* Validate that chip access is feasible */
4494         if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
4495                 DP_ERR(p_hwfn,
4496                        "Reading the ME register returns all Fs; Preventing further chip access\n");
4497                 return -EINVAL;
4498         }
4499
4500         get_function_id(p_hwfn);
4501
4502         /* Allocate PTT pool */
4503         rc = qed_ptt_pool_alloc(p_hwfn);
4504         if (rc)
4505                 goto err0;
4506
4507         /* Allocate the main PTT */
4508         p_hwfn->p_main_ptt = qed_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
4509
4510         /* First hwfn learns basic information, e.g., number of hwfns */
4511         if (!p_hwfn->my_id) {
4512                 rc = qed_get_dev_info(p_hwfn, p_hwfn->p_main_ptt);
4513                 if (rc)
4514                         goto err1;
4515         }
4516
4517         qed_hw_hwfn_prepare(p_hwfn);
4518
4519         /* Initialize MCP structure */
4520         rc = qed_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
4521         if (rc) {
4522                 DP_NOTICE(p_hwfn, "Failed initializing mcp command\n");
4523                 goto err1;
4524         }
4525
4526         /* Read the device configuration information from the HW and SHMEM */
4527         rc = qed_get_hw_info(p_hwfn, p_hwfn->p_main_ptt, personality);
4528         if (rc) {
4529                 DP_NOTICE(p_hwfn, "Failed to get HW information\n");
4530                 goto err2;
4531         }
4532
4533         /* Sending a mailbox to the MFW should be done after qed_get_hw_info()
4534          * is called as it sets the ports number in an engine.
4535          */
4536         if (IS_LEAD_HWFN(p_hwfn) && !cdev->recov_in_prog) {
4537                 rc = qed_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt);
4538                 if (rc)
4539                         DP_NOTICE(p_hwfn, "Failed to initiate PF FLR\n");
4540         }
4541
4542         /* NVRAM info initialization and population */
4543         if (IS_LEAD_HWFN(p_hwfn)) {
4544                 rc = qed_mcp_nvm_info_populate(p_hwfn);
4545                 if (rc) {
4546                         DP_NOTICE(p_hwfn,
4547                                   "Failed to populate nvm info shadow\n");
4548                         goto err2;
4549                 }
4550         }
4551
4552         /* Allocate the init RT array and initialize the init-ops engine */
4553         rc = qed_init_alloc(p_hwfn);
4554         if (rc)
4555                 goto err3;
4556
4557         return rc;
4558 err3:
4559         if (IS_LEAD_HWFN(p_hwfn))
4560                 qed_nvm_info_free(p_hwfn);
4561 err2:
4562         if (IS_LEAD_HWFN(p_hwfn))
4563                 qed_iov_free_hw_info(p_hwfn->cdev);
4564         qed_mcp_free(p_hwfn);
4565 err1:
4566         qed_hw_hwfn_free(p_hwfn);
4567 err0:
4568         return rc;
4569 }
4570
4571 int qed_hw_prepare(struct qed_dev *cdev,
4572                    int personality)
4573 {
4574         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
4575         int rc;
4576
4577         /* Store the precompiled init data ptrs */
4578         if (IS_PF(cdev))
4579                 qed_init_iro_array(cdev);
4580
4581         /* Initialize the first hwfn - will learn number of hwfns */
4582         rc = qed_hw_prepare_single(p_hwfn,
4583                                    cdev->regview,
4584                                    cdev->doorbells,
4585                                    cdev->db_phys_addr,
4586                                    personality);
4587         if (rc)
4588                 return rc;
4589
4590         personality = p_hwfn->hw_info.personality;
4591
4592         /* Initialize the rest of the hwfns */
4593         if (cdev->num_hwfns > 1) {
4594                 void __iomem *p_regview, *p_doorbell;
4595                 u64 db_phys_addr;
4596                 u32 offset;
4597
4598                 /* adjust bar offset for second engine */
4599                 offset = qed_hw_bar_size(p_hwfn, p_hwfn->p_main_ptt,
4600                                          BAR_ID_0) / 2;
4601                 p_regview = cdev->regview + offset;
4602
4603                 offset = qed_hw_bar_size(p_hwfn, p_hwfn->p_main_ptt,
4604                                          BAR_ID_1) / 2;
4605
4606                 p_doorbell = cdev->doorbells + offset;
4607
4608                 db_phys_addr = cdev->db_phys_addr + offset;
4609
4610                 /* prepare second hw function */
4611                 rc = qed_hw_prepare_single(&cdev->hwfns[1], p_regview,
4612                                            p_doorbell, db_phys_addr,
4613                                            personality);
4614
4615                 /* in case of error, need to free the previously
4616                  * initiliazed hwfn 0.
4617                  */
4618                 if (rc) {
4619                         if (IS_PF(cdev)) {
4620                                 qed_init_free(p_hwfn);
4621                                 qed_nvm_info_free(p_hwfn);
4622                                 qed_mcp_free(p_hwfn);
4623                                 qed_hw_hwfn_free(p_hwfn);
4624                         }
4625                 }
4626         }
4627
4628         return rc;
4629 }
4630
4631 void qed_hw_remove(struct qed_dev *cdev)
4632 {
4633         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
4634         int i;
4635
4636         if (IS_PF(cdev))
4637                 qed_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt,
4638                                                QED_OV_DRIVER_STATE_NOT_LOADED);
4639
4640         for_each_hwfn(cdev, i) {
4641                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
4642
4643                 if (IS_VF(cdev)) {
4644                         qed_vf_pf_release(p_hwfn);
4645                         continue;
4646                 }
4647
4648                 qed_init_free(p_hwfn);
4649                 qed_hw_hwfn_free(p_hwfn);
4650                 qed_mcp_free(p_hwfn);
4651         }
4652
4653         qed_iov_free_hw_info(cdev);
4654
4655         qed_nvm_info_free(p_hwfn);
4656 }
4657
4658 static void qed_chain_free_next_ptr(struct qed_dev *cdev,
4659                                     struct qed_chain *p_chain)
4660 {
4661         void *p_virt = p_chain->p_virt_addr, *p_virt_next = NULL;
4662         dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
4663         struct qed_chain_next *p_next;
4664         u32 size, i;
4665
4666         if (!p_virt)
4667                 return;
4668
4669         size = p_chain->elem_size * p_chain->usable_per_page;
4670
4671         for (i = 0; i < p_chain->page_cnt; i++) {
4672                 if (!p_virt)
4673                         break;
4674
4675                 p_next = (struct qed_chain_next *)((u8 *)p_virt + size);
4676                 p_virt_next = p_next->next_virt;
4677                 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
4678
4679                 dma_free_coherent(&cdev->pdev->dev,
4680                                   QED_CHAIN_PAGE_SIZE, p_virt, p_phys);
4681
4682                 p_virt = p_virt_next;
4683                 p_phys = p_phys_next;
4684         }
4685 }
4686
4687 static void qed_chain_free_single(struct qed_dev *cdev,
4688                                   struct qed_chain *p_chain)
4689 {
4690         if (!p_chain->p_virt_addr)
4691                 return;
4692
4693         dma_free_coherent(&cdev->pdev->dev,
4694                           QED_CHAIN_PAGE_SIZE,
4695                           p_chain->p_virt_addr, p_chain->p_phys_addr);
4696 }
4697
4698 static void qed_chain_free_pbl(struct qed_dev *cdev, struct qed_chain *p_chain)
4699 {
4700         struct addr_tbl_entry *pp_addr_tbl = p_chain->pbl.pp_addr_tbl;
4701         u32 page_cnt = p_chain->page_cnt, i, pbl_size;
4702
4703         if (!pp_addr_tbl)
4704                 return;
4705
4706         for (i = 0; i < page_cnt; i++) {
4707                 if (!pp_addr_tbl[i].virt_addr || !pp_addr_tbl[i].dma_map)
4708                         break;
4709
4710                 dma_free_coherent(&cdev->pdev->dev,
4711                                   QED_CHAIN_PAGE_SIZE,
4712                                   pp_addr_tbl[i].virt_addr,
4713                                   pp_addr_tbl[i].dma_map);
4714         }
4715
4716         pbl_size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE;
4717
4718         if (!p_chain->b_external_pbl)
4719                 dma_free_coherent(&cdev->pdev->dev,
4720                                   pbl_size,
4721                                   p_chain->pbl_sp.p_virt_table,
4722                                   p_chain->pbl_sp.p_phys_table);
4723
4724         vfree(p_chain->pbl.pp_addr_tbl);
4725         p_chain->pbl.pp_addr_tbl = NULL;
4726 }
4727
4728 void qed_chain_free(struct qed_dev *cdev, struct qed_chain *p_chain)
4729 {
4730         switch (p_chain->mode) {
4731         case QED_CHAIN_MODE_NEXT_PTR:
4732                 qed_chain_free_next_ptr(cdev, p_chain);
4733                 break;
4734         case QED_CHAIN_MODE_SINGLE:
4735                 qed_chain_free_single(cdev, p_chain);
4736                 break;
4737         case QED_CHAIN_MODE_PBL:
4738                 qed_chain_free_pbl(cdev, p_chain);
4739                 break;
4740         }
4741 }
4742
4743 static int
4744 qed_chain_alloc_sanity_check(struct qed_dev *cdev,
4745                              enum qed_chain_cnt_type cnt_type,
4746                              size_t elem_size, u32 page_cnt)
4747 {
4748         u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
4749
4750         /* The actual chain size can be larger than the maximal possible value
4751          * after rounding up the requested elements number to pages, and after
4752          * taking into acount the unusuable elements (next-ptr elements).
4753          * The size of a "u16" chain can be (U16_MAX + 1) since the chain
4754          * size/capacity fields are of a u32 type.
4755          */
4756         if ((cnt_type == QED_CHAIN_CNT_TYPE_U16 &&
4757              chain_size > ((u32)U16_MAX + 1)) ||
4758             (cnt_type == QED_CHAIN_CNT_TYPE_U32 && chain_size > U32_MAX)) {
4759                 DP_NOTICE(cdev,
4760                           "The actual chain size (0x%llx) is larger than the maximal possible value\n",
4761                           chain_size);
4762                 return -EINVAL;
4763         }
4764
4765         return 0;
4766 }
4767
4768 static int
4769 qed_chain_alloc_next_ptr(struct qed_dev *cdev, struct qed_chain *p_chain)
4770 {
4771         void *p_virt = NULL, *p_virt_prev = NULL;
4772         dma_addr_t p_phys = 0;
4773         u32 i;
4774
4775         for (i = 0; i < p_chain->page_cnt; i++) {
4776                 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
4777                                             QED_CHAIN_PAGE_SIZE,
4778                                             &p_phys, GFP_KERNEL);
4779                 if (!p_virt)
4780                         return -ENOMEM;
4781
4782                 if (i == 0) {
4783                         qed_chain_init_mem(p_chain, p_virt, p_phys);
4784                         qed_chain_reset(p_chain);
4785                 } else {
4786                         qed_chain_init_next_ptr_elem(p_chain, p_virt_prev,
4787                                                      p_virt, p_phys);
4788                 }
4789
4790                 p_virt_prev = p_virt;
4791         }
4792         /* Last page's next element should point to the beginning of the
4793          * chain.
4794          */
4795         qed_chain_init_next_ptr_elem(p_chain, p_virt_prev,
4796                                      p_chain->p_virt_addr,
4797                                      p_chain->p_phys_addr);
4798
4799         return 0;
4800 }
4801
4802 static int
4803 qed_chain_alloc_single(struct qed_dev *cdev, struct qed_chain *p_chain)
4804 {
4805         dma_addr_t p_phys = 0;
4806         void *p_virt = NULL;
4807
4808         p_virt = dma_alloc_coherent(&cdev->pdev->dev,
4809                                     QED_CHAIN_PAGE_SIZE, &p_phys, GFP_KERNEL);
4810         if (!p_virt)
4811                 return -ENOMEM;
4812
4813         qed_chain_init_mem(p_chain, p_virt, p_phys);
4814         qed_chain_reset(p_chain);
4815
4816         return 0;
4817 }
4818
4819 static int
4820 qed_chain_alloc_pbl(struct qed_dev *cdev,
4821                     struct qed_chain *p_chain,
4822                     struct qed_chain_ext_pbl *ext_pbl)
4823 {
4824         u32 page_cnt = p_chain->page_cnt, size, i;
4825         dma_addr_t p_phys = 0, p_pbl_phys = 0;
4826         struct addr_tbl_entry *pp_addr_tbl;
4827         u8 *p_pbl_virt = NULL;
4828         void *p_virt = NULL;
4829
4830         size = page_cnt * sizeof(*pp_addr_tbl);
4831         pp_addr_tbl =  vzalloc(size);
4832         if (!pp_addr_tbl)
4833                 return -ENOMEM;
4834
4835         /* The allocation of the PBL table is done with its full size, since it
4836          * is expected to be successive.
4837          * qed_chain_init_pbl_mem() is called even in a case of an allocation
4838          * failure, since tbl was previously allocated, and it
4839          * should be saved to allow its freeing during the error flow.
4840          */
4841         size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE;
4842
4843         if (!ext_pbl) {
4844                 p_pbl_virt = dma_alloc_coherent(&cdev->pdev->dev,
4845                                                 size, &p_pbl_phys, GFP_KERNEL);
4846         } else {
4847                 p_pbl_virt = ext_pbl->p_pbl_virt;
4848                 p_pbl_phys = ext_pbl->p_pbl_phys;
4849                 p_chain->b_external_pbl = true;
4850         }
4851
4852         qed_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys, pp_addr_tbl);
4853         if (!p_pbl_virt)
4854                 return -ENOMEM;
4855
4856         for (i = 0; i < page_cnt; i++) {
4857                 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
4858                                             QED_CHAIN_PAGE_SIZE,
4859                                             &p_phys, GFP_KERNEL);
4860                 if (!p_virt)
4861                         return -ENOMEM;
4862
4863                 if (i == 0) {
4864                         qed_chain_init_mem(p_chain, p_virt, p_phys);
4865                         qed_chain_reset(p_chain);
4866                 }
4867
4868                 /* Fill the PBL table with the physical address of the page */
4869                 *(dma_addr_t *)p_pbl_virt = p_phys;
4870                 /* Keep the virtual address of the page */
4871                 p_chain->pbl.pp_addr_tbl[i].virt_addr = p_virt;
4872                 p_chain->pbl.pp_addr_tbl[i].dma_map = p_phys;
4873
4874                 p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE;
4875         }
4876
4877         return 0;
4878 }
4879
4880 int qed_chain_alloc(struct qed_dev *cdev,
4881                     enum qed_chain_use_mode intended_use,
4882                     enum qed_chain_mode mode,
4883                     enum qed_chain_cnt_type cnt_type,
4884                     u32 num_elems,
4885                     size_t elem_size,
4886                     struct qed_chain *p_chain,
4887                     struct qed_chain_ext_pbl *ext_pbl)
4888 {
4889         u32 page_cnt;
4890         int rc = 0;
4891
4892         if (mode == QED_CHAIN_MODE_SINGLE)
4893                 page_cnt = 1;
4894         else
4895                 page_cnt = QED_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
4896
4897         rc = qed_chain_alloc_sanity_check(cdev, cnt_type, elem_size, page_cnt);
4898         if (rc) {
4899                 DP_NOTICE(cdev,
4900                           "Cannot allocate a chain with the given arguments:\n");
4901                 DP_NOTICE(cdev,
4902                           "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
4903                           intended_use, mode, cnt_type, num_elems, elem_size);
4904                 return rc;
4905         }
4906
4907         qed_chain_init_params(p_chain, page_cnt, (u8) elem_size, intended_use,
4908                               mode, cnt_type);
4909
4910         switch (mode) {
4911         case QED_CHAIN_MODE_NEXT_PTR:
4912                 rc = qed_chain_alloc_next_ptr(cdev, p_chain);
4913                 break;
4914         case QED_CHAIN_MODE_SINGLE:
4915                 rc = qed_chain_alloc_single(cdev, p_chain);
4916                 break;
4917         case QED_CHAIN_MODE_PBL:
4918                 rc = qed_chain_alloc_pbl(cdev, p_chain, ext_pbl);
4919                 break;
4920         }
4921         if (rc)
4922                 goto nomem;
4923
4924         return 0;
4925
4926 nomem:
4927         qed_chain_free(cdev, p_chain);
4928         return rc;
4929 }
4930
4931 int qed_fw_l2_queue(struct qed_hwfn *p_hwfn, u16 src_id, u16 *dst_id)
4932 {
4933         if (src_id >= RESC_NUM(p_hwfn, QED_L2_QUEUE)) {
4934                 u16 min, max;
4935
4936                 min = (u16) RESC_START(p_hwfn, QED_L2_QUEUE);
4937                 max = min + RESC_NUM(p_hwfn, QED_L2_QUEUE);
4938                 DP_NOTICE(p_hwfn,
4939                           "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
4940                           src_id, min, max);
4941
4942                 return -EINVAL;
4943         }
4944
4945         *dst_id = RESC_START(p_hwfn, QED_L2_QUEUE) + src_id;
4946
4947         return 0;
4948 }
4949
4950 int qed_fw_vport(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id)
4951 {
4952         if (src_id >= RESC_NUM(p_hwfn, QED_VPORT)) {
4953                 u8 min, max;
4954
4955                 min = (u8)RESC_START(p_hwfn, QED_VPORT);
4956                 max = min + RESC_NUM(p_hwfn, QED_VPORT);
4957                 DP_NOTICE(p_hwfn,
4958                           "vport id [%d] is not valid, available indices [%d - %d]\n",
4959                           src_id, min, max);
4960
4961                 return -EINVAL;
4962         }
4963
4964         *dst_id = RESC_START(p_hwfn, QED_VPORT) + src_id;
4965
4966         return 0;
4967 }
4968
4969 int qed_fw_rss_eng(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id)
4970 {
4971         if (src_id >= RESC_NUM(p_hwfn, QED_RSS_ENG)) {
4972                 u8 min, max;
4973
4974                 min = (u8)RESC_START(p_hwfn, QED_RSS_ENG);
4975                 max = min + RESC_NUM(p_hwfn, QED_RSS_ENG);
4976                 DP_NOTICE(p_hwfn,
4977                           "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
4978                           src_id, min, max);
4979
4980                 return -EINVAL;
4981         }
4982
4983         *dst_id = RESC_START(p_hwfn, QED_RSS_ENG) + src_id;
4984
4985         return 0;
4986 }
4987
4988 static int qed_set_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
4989                             u32 hw_addr, void *p_eth_qzone,
4990                             size_t eth_qzone_size, u8 timeset)
4991 {
4992         struct coalescing_timeset *p_coal_timeset;
4993
4994         if (p_hwfn->cdev->int_coalescing_mode != QED_COAL_MODE_ENABLE) {
4995                 DP_NOTICE(p_hwfn, "Coalescing configuration not enabled\n");
4996                 return -EINVAL;
4997         }
4998
4999         p_coal_timeset = p_eth_qzone;
5000         memset(p_eth_qzone, 0, eth_qzone_size);
5001         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
5002         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
5003         qed_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
5004
5005         return 0;
5006 }
5007
5008 int qed_set_queue_coalesce(u16 rx_coal, u16 tx_coal, void *p_handle)
5009 {
5010         struct qed_queue_cid *p_cid = p_handle;
5011         struct qed_hwfn *p_hwfn;
5012         struct qed_ptt *p_ptt;
5013         int rc = 0;
5014
5015         p_hwfn = p_cid->p_owner;
5016
5017         if (IS_VF(p_hwfn->cdev))
5018                 return qed_vf_pf_set_coalesce(p_hwfn, rx_coal, tx_coal, p_cid);
5019
5020         p_ptt = qed_ptt_acquire(p_hwfn);
5021         if (!p_ptt)
5022                 return -EAGAIN;
5023
5024         if (rx_coal) {
5025                 rc = qed_set_rxq_coalesce(p_hwfn, p_ptt, rx_coal, p_cid);
5026                 if (rc)
5027                         goto out;
5028                 p_hwfn->cdev->rx_coalesce_usecs = rx_coal;
5029         }
5030
5031         if (tx_coal) {
5032                 rc = qed_set_txq_coalesce(p_hwfn, p_ptt, tx_coal, p_cid);
5033                 if (rc)
5034                         goto out;
5035                 p_hwfn->cdev->tx_coalesce_usecs = tx_coal;
5036         }
5037 out:
5038         qed_ptt_release(p_hwfn, p_ptt);
5039         return rc;
5040 }
5041
5042 int qed_set_rxq_coalesce(struct qed_hwfn *p_hwfn,
5043                          struct qed_ptt *p_ptt,
5044                          u16 coalesce, struct qed_queue_cid *p_cid)
5045 {
5046         struct ustorm_eth_queue_zone eth_qzone;
5047         u8 timeset, timer_res;
5048         u32 address;
5049         int rc;
5050
5051         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
5052         if (coalesce <= 0x7F) {
5053                 timer_res = 0;
5054         } else if (coalesce <= 0xFF) {
5055                 timer_res = 1;
5056         } else if (coalesce <= 0x1FF) {
5057                 timer_res = 2;
5058         } else {
5059                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
5060                 return -EINVAL;
5061         }
5062         timeset = (u8)(coalesce >> timer_res);
5063
5064         rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res,
5065                                    p_cid->sb_igu_id, false);
5066         if (rc)
5067                 goto out;
5068
5069         address = BAR0_MAP_REG_USDM_RAM +
5070                   USTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
5071
5072         rc = qed_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
5073                               sizeof(struct ustorm_eth_queue_zone), timeset);
5074         if (rc)
5075                 goto out;
5076
5077 out:
5078         return rc;
5079 }
5080
5081 int qed_set_txq_coalesce(struct qed_hwfn *p_hwfn,
5082                          struct qed_ptt *p_ptt,
5083                          u16 coalesce, struct qed_queue_cid *p_cid)
5084 {
5085         struct xstorm_eth_queue_zone eth_qzone;
5086         u8 timeset, timer_res;
5087         u32 address;
5088         int rc;
5089
5090         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
5091         if (coalesce <= 0x7F) {
5092                 timer_res = 0;
5093         } else if (coalesce <= 0xFF) {
5094                 timer_res = 1;
5095         } else if (coalesce <= 0x1FF) {
5096                 timer_res = 2;
5097         } else {
5098                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
5099                 return -EINVAL;
5100         }
5101         timeset = (u8)(coalesce >> timer_res);
5102
5103         rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res,
5104                                    p_cid->sb_igu_id, true);
5105         if (rc)
5106                 goto out;
5107
5108         address = BAR0_MAP_REG_XSDM_RAM +
5109                   XSTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
5110
5111         rc = qed_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
5112                               sizeof(struct xstorm_eth_queue_zone), timeset);
5113 out:
5114         return rc;
5115 }
5116
5117 /* Calculate final WFQ values for all vports and configure them.
5118  * After this configuration each vport will have
5119  * approx min rate =  min_pf_rate * (vport_wfq / QED_WFQ_UNIT)
5120  */
5121 static void qed_configure_wfq_for_all_vports(struct qed_hwfn *p_hwfn,
5122                                              struct qed_ptt *p_ptt,
5123                                              u32 min_pf_rate)
5124 {
5125         struct init_qm_vport_params *vport_params;
5126         int i;
5127
5128         vport_params = p_hwfn->qm_info.qm_vport_params;
5129
5130         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
5131                 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
5132
5133                 vport_params[i].wfq = (wfq_speed * QED_WFQ_UNIT) /
5134                                                 min_pf_rate;
5135                 qed_init_vport_wfq(p_hwfn, p_ptt,
5136                                    vport_params[i].first_tx_pq_id,
5137                                    vport_params[i].wfq);
5138         }
5139 }
5140
5141 static void qed_init_wfq_default_param(struct qed_hwfn *p_hwfn,
5142                                        u32 min_pf_rate)
5143
5144 {
5145         int i;
5146
5147         for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
5148                 p_hwfn->qm_info.qm_vport_params[i].wfq = 1;
5149 }
5150
5151 static void qed_disable_wfq_for_all_vports(struct qed_hwfn *p_hwfn,
5152                                            struct qed_ptt *p_ptt,
5153                                            u32 min_pf_rate)
5154 {
5155         struct init_qm_vport_params *vport_params;
5156         int i;
5157
5158         vport_params = p_hwfn->qm_info.qm_vport_params;
5159
5160         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
5161                 qed_init_wfq_default_param(p_hwfn, min_pf_rate);
5162                 qed_init_vport_wfq(p_hwfn, p_ptt,
5163                                    vport_params[i].first_tx_pq_id,
5164                                    vport_params[i].wfq);
5165         }
5166 }
5167
5168 /* This function performs several validations for WFQ
5169  * configuration and required min rate for a given vport
5170  * 1. req_rate must be greater than one percent of min_pf_rate.
5171  * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
5172  *    rates to get less than one percent of min_pf_rate.
5173  * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
5174  */
5175 static int qed_init_wfq_param(struct qed_hwfn *p_hwfn,
5176                               u16 vport_id, u32 req_rate, u32 min_pf_rate)
5177 {
5178         u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
5179         int non_requested_count = 0, req_count = 0, i, num_vports;
5180
5181         num_vports = p_hwfn->qm_info.num_vports;
5182
5183         /* Accounting for the vports which are configured for WFQ explicitly */
5184         for (i = 0; i < num_vports; i++) {
5185                 u32 tmp_speed;
5186
5187                 if ((i != vport_id) &&
5188                     p_hwfn->qm_info.wfq_data[i].configured) {
5189                         req_count++;
5190                         tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
5191                         total_req_min_rate += tmp_speed;
5192                 }
5193         }
5194
5195         /* Include current vport data as well */
5196         req_count++;
5197         total_req_min_rate += req_rate;
5198         non_requested_count = num_vports - req_count;
5199
5200         if (req_rate < min_pf_rate / QED_WFQ_UNIT) {
5201                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
5202                            "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
5203                            vport_id, req_rate, min_pf_rate);
5204                 return -EINVAL;
5205         }
5206
5207         if (num_vports > QED_WFQ_UNIT) {
5208                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
5209                            "Number of vports is greater than %d\n",
5210                            QED_WFQ_UNIT);
5211                 return -EINVAL;
5212         }
5213
5214         if (total_req_min_rate > min_pf_rate) {
5215                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
5216                            "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
5217                            total_req_min_rate, min_pf_rate);
5218                 return -EINVAL;
5219         }
5220
5221         total_left_rate = min_pf_rate - total_req_min_rate;
5222
5223         left_rate_per_vp = total_left_rate / non_requested_count;
5224         if (left_rate_per_vp <  min_pf_rate / QED_WFQ_UNIT) {
5225                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
5226                            "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
5227                            left_rate_per_vp, min_pf_rate);
5228                 return -EINVAL;
5229         }
5230
5231         p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
5232         p_hwfn->qm_info.wfq_data[vport_id].configured = true;
5233
5234         for (i = 0; i < num_vports; i++) {
5235                 if (p_hwfn->qm_info.wfq_data[i].configured)
5236                         continue;
5237
5238                 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
5239         }
5240
5241         return 0;
5242 }
5243
5244 static int __qed_configure_vport_wfq(struct qed_hwfn *p_hwfn,
5245                                      struct qed_ptt *p_ptt, u16 vp_id, u32 rate)
5246 {
5247         struct qed_mcp_link_state *p_link;
5248         int rc = 0;
5249
5250         p_link = &p_hwfn->cdev->hwfns[0].mcp_info->link_output;
5251
5252         if (!p_link->min_pf_rate) {
5253                 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
5254                 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
5255                 return rc;
5256         }
5257
5258         rc = qed_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
5259
5260         if (!rc)
5261                 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt,
5262                                                  p_link->min_pf_rate);
5263         else
5264                 DP_NOTICE(p_hwfn,
5265                           "Validation failed while configuring min rate\n");
5266
5267         return rc;
5268 }
5269
5270 static int __qed_configure_vp_wfq_on_link_change(struct qed_hwfn *p_hwfn,
5271                                                  struct qed_ptt *p_ptt,
5272                                                  u32 min_pf_rate)
5273 {
5274         bool use_wfq = false;
5275         int rc = 0;
5276         u16 i;
5277
5278         /* Validate all pre configured vports for wfq */
5279         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
5280                 u32 rate;
5281
5282                 if (!p_hwfn->qm_info.wfq_data[i].configured)
5283                         continue;
5284
5285                 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
5286                 use_wfq = true;
5287
5288                 rc = qed_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
5289                 if (rc) {
5290                         DP_NOTICE(p_hwfn,
5291                                   "WFQ validation failed while configuring min rate\n");
5292                         break;
5293                 }
5294         }
5295
5296         if (!rc && use_wfq)
5297                 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
5298         else
5299                 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
5300
5301         return rc;
5302 }
5303
5304 /* Main API for qed clients to configure vport min rate.
5305  * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
5306  * rate - Speed in Mbps needs to be assigned to a given vport.
5307  */
5308 int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate)
5309 {
5310         int i, rc = -EINVAL;
5311
5312         /* Currently not supported; Might change in future */
5313         if (cdev->num_hwfns > 1) {
5314                 DP_NOTICE(cdev,
5315                           "WFQ configuration is not supported for this device\n");
5316                 return rc;
5317         }
5318
5319         for_each_hwfn(cdev, i) {
5320                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
5321                 struct qed_ptt *p_ptt;
5322
5323                 p_ptt = qed_ptt_acquire(p_hwfn);
5324                 if (!p_ptt)
5325                         return -EBUSY;
5326
5327                 rc = __qed_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
5328
5329                 if (rc) {
5330                         qed_ptt_release(p_hwfn, p_ptt);
5331                         return rc;
5332                 }
5333
5334                 qed_ptt_release(p_hwfn, p_ptt);
5335         }
5336
5337         return rc;
5338 }
5339
5340 /* API to configure WFQ from mcp link change */
5341 void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev,
5342                                          struct qed_ptt *p_ptt, u32 min_pf_rate)
5343 {
5344         int i;
5345
5346         if (cdev->num_hwfns > 1) {
5347                 DP_VERBOSE(cdev,
5348                            NETIF_MSG_LINK,
5349                            "WFQ configuration is not supported for this device\n");
5350                 return;
5351         }
5352
5353         for_each_hwfn(cdev, i) {
5354                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
5355
5356                 __qed_configure_vp_wfq_on_link_change(p_hwfn, p_ptt,
5357                                                       min_pf_rate);
5358         }
5359 }
5360
5361 int __qed_configure_pf_max_bandwidth(struct qed_hwfn *p_hwfn,
5362                                      struct qed_ptt *p_ptt,
5363                                      struct qed_mcp_link_state *p_link,
5364                                      u8 max_bw)
5365 {
5366         int rc = 0;
5367
5368         p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
5369
5370         if (!p_link->line_speed && (max_bw != 100))
5371                 return rc;
5372
5373         p_link->speed = (p_link->line_speed * max_bw) / 100;
5374         p_hwfn->qm_info.pf_rl = p_link->speed;
5375
5376         /* Since the limiter also affects Tx-switched traffic, we don't want it
5377          * to limit such traffic in case there's no actual limit.
5378          * In that case, set limit to imaginary high boundary.
5379          */
5380         if (max_bw == 100)
5381                 p_hwfn->qm_info.pf_rl = 100000;
5382
5383         rc = qed_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
5384                             p_hwfn->qm_info.pf_rl);
5385
5386         DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
5387                    "Configured MAX bandwidth to be %08x Mb/sec\n",
5388                    p_link->speed);
5389
5390         return rc;
5391 }
5392
5393 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
5394 int qed_configure_pf_max_bandwidth(struct qed_dev *cdev, u8 max_bw)
5395 {
5396         int i, rc = -EINVAL;
5397
5398         if (max_bw < 1 || max_bw > 100) {
5399                 DP_NOTICE(cdev, "PF max bw valid range is [1-100]\n");
5400                 return rc;
5401         }
5402
5403         for_each_hwfn(cdev, i) {
5404                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
5405                 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev);
5406                 struct qed_mcp_link_state *p_link;
5407                 struct qed_ptt *p_ptt;
5408
5409                 p_link = &p_lead->mcp_info->link_output;
5410
5411                 p_ptt = qed_ptt_acquire(p_hwfn);
5412                 if (!p_ptt)
5413                         return -EBUSY;
5414
5415                 rc = __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt,
5416                                                       p_link, max_bw);
5417
5418                 qed_ptt_release(p_hwfn, p_ptt);
5419
5420                 if (rc)
5421                         break;
5422         }
5423
5424         return rc;
5425 }
5426
5427 int __qed_configure_pf_min_bandwidth(struct qed_hwfn *p_hwfn,
5428                                      struct qed_ptt *p_ptt,
5429                                      struct qed_mcp_link_state *p_link,
5430                                      u8 min_bw)
5431 {
5432         int rc = 0;
5433
5434         p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
5435         p_hwfn->qm_info.pf_wfq = min_bw;
5436
5437         if (!p_link->line_speed)
5438                 return rc;
5439
5440         p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
5441
5442         rc = qed_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
5443
5444         DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
5445                    "Configured MIN bandwidth to be %d Mb/sec\n",
5446                    p_link->min_pf_rate);
5447
5448         return rc;
5449 }
5450
5451 /* Main API to configure PF min bandwidth where bw range is [1-100] */
5452 int qed_configure_pf_min_bandwidth(struct qed_dev *cdev, u8 min_bw)
5453 {
5454         int i, rc = -EINVAL;
5455
5456         if (min_bw < 1 || min_bw > 100) {
5457                 DP_NOTICE(cdev, "PF min bw valid range is [1-100]\n");
5458                 return rc;
5459         }
5460
5461         for_each_hwfn(cdev, i) {
5462                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
5463                 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev);
5464                 struct qed_mcp_link_state *p_link;
5465                 struct qed_ptt *p_ptt;
5466
5467                 p_link = &p_lead->mcp_info->link_output;
5468
5469                 p_ptt = qed_ptt_acquire(p_hwfn);
5470                 if (!p_ptt)
5471                         return -EBUSY;
5472
5473                 rc = __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt,
5474                                                       p_link, min_bw);
5475                 if (rc) {
5476                         qed_ptt_release(p_hwfn, p_ptt);
5477                         return rc;
5478                 }
5479
5480                 if (p_link->min_pf_rate) {
5481                         u32 min_rate = p_link->min_pf_rate;
5482
5483                         rc = __qed_configure_vp_wfq_on_link_change(p_hwfn,
5484                                                                    p_ptt,
5485                                                                    min_rate);
5486                 }
5487
5488                 qed_ptt_release(p_hwfn, p_ptt);
5489         }
5490
5491         return rc;
5492 }
5493
5494 void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
5495 {
5496         struct qed_mcp_link_state *p_link;
5497
5498         p_link = &p_hwfn->mcp_info->link_output;
5499
5500         if (p_link->min_pf_rate)
5501                 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt,
5502                                                p_link->min_pf_rate);
5503
5504         memset(p_hwfn->qm_info.wfq_data, 0,
5505                sizeof(*p_hwfn->qm_info.wfq_data) * p_hwfn->qm_info.num_vports);
5506 }
5507
5508 int qed_device_num_ports(struct qed_dev *cdev)
5509 {
5510         return cdev->num_ports;
5511 }
5512
5513 void qed_set_fw_mac_addr(__le16 *fw_msb,
5514                          __le16 *fw_mid, __le16 *fw_lsb, u8 *mac)
5515 {
5516         ((u8 *)fw_msb)[0] = mac[1];
5517         ((u8 *)fw_msb)[1] = mac[0];
5518         ((u8 *)fw_mid)[0] = mac[3];
5519         ((u8 *)fw_mid)[1] = mac[2];
5520         ((u8 *)fw_lsb)[0] = mac[5];
5521         ((u8 *)fw_lsb)[1] = mac[4];
5522 }