drivers/net/ethernet/qlogic/qed/qed.h

   1 /* QLogic qed NIC Driver
   2  * Copyright (c) 2015-2017  QLogic Corporation
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and /or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #ifndef _QED_H
  34 #define _QED_H
  35
  36 #include <linux/types.h>
  37 #include <linux/io.h>
  38 #include <linux/delay.h>
  39 #include <linux/firmware.h>
  40 #include <linux/interrupt.h>
  41 #include <linux/list.h>
  42 #include <linux/mutex.h>
  43 #include <linux/pci.h>
  44 #include <linux/slab.h>
  45 #include <linux/string.h>
  46 #include <linux/workqueue.h>
  47 #include <linux/zlib.h>
  48 #include <linux/hashtable.h>
  49 #include <linux/qed/qed_if.h>
  50 #include "qed_debug.h"
  51 #include "qed_hsi.h"
  52
  53 extern const struct qed_common_ops qed_common_ops_pass;
  54
  55 #define QED_MAJOR_VERSION               8
  56 #define QED_MINOR_VERSION               37
  57 #define QED_REVISION_VERSION            0
  58 #define QED_ENGINEERING_VERSION         20
  59
  60 #define QED_VERSION                                              \
  61         ((QED_MAJOR_VERSION << 24) | (QED_MINOR_VERSION << 16) | \
  62          (QED_REVISION_VERSION << 8) | QED_ENGINEERING_VERSION)
  63
  64 #define STORM_FW_VERSION                                       \
  65         ((FW_MAJOR_VERSION << 24) | (FW_MINOR_VERSION << 16) | \
  66          (FW_REVISION_VERSION << 8) | FW_ENGINEERING_VERSION)
  67
  68 #define MAX_HWFNS_PER_DEVICE    (4)
  69 #define NAME_SIZE 16
  70 #define VER_SIZE 16
  71
  72 #define QED_WFQ_UNIT    100
  73
  74 #define QED_WID_SIZE            (1024)
  75 #define QED_MIN_WIDS            (4)
  76 #define QED_PF_DEMS_SIZE        (4)
  77
  78 /* cau states */
  79 enum qed_coalescing_mode {
  80         QED_COAL_MODE_DISABLE,
  81         QED_COAL_MODE_ENABLE
  82 };
  83
  84 enum qed_nvm_cmd {
  85         QED_PUT_FILE_BEGIN = DRV_MSG_CODE_NVM_PUT_FILE_BEGIN,
  86         QED_PUT_FILE_DATA = DRV_MSG_CODE_NVM_PUT_FILE_DATA,
  87         QED_NVM_WRITE_NVRAM = DRV_MSG_CODE_NVM_WRITE_NVRAM,
  88         QED_GET_MCP_NVM_RESP = 0xFFFFFF00
  89 };
  90
  91 struct qed_eth_cb_ops;
  92 struct qed_dev_info;
  93 union qed_mcp_protocol_stats;
  94 enum qed_mcp_protocol_type;
  95 enum qed_mfw_tlv_type;
  96 union qed_mfw_tlv_data;
  97
  98 /* helpers */
  99 #define QED_MFW_GET_FIELD(name, field) \
 100         (((name) & (field ## _MASK)) >> (field ## _SHIFT))
 101
 102 #define QED_MFW_SET_FIELD(name, field, value)                                  \
 103         do {                                                                   \
 104                 (name)  &= ~(field ## _MASK);          \
 105                 (name)  |= (((value) << (field ## _SHIFT)) & (field ## _MASK));\
 106         } while (0)
 107
 108 static inline u32 qed_db_addr(u32 cid, u32 DEMS)
 109 {
 110         u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
 111                       (cid * QED_PF_DEMS_SIZE);
 112
 113         return db_addr;
 114 }
 115
 116 static inline u32 qed_db_addr_vf(u32 cid, u32 DEMS)
 117 {
 118         u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
 119                       FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid);
 120
 121         return db_addr;
 122 }
 123
 124 #define ALIGNED_TYPE_SIZE(type_name, p_hwfn)                                 \
 125         ((sizeof(type_name) + (u32)(1 << (p_hwfn->cdev->cache_shift)) - 1) & \
 126          ~((1 << (p_hwfn->cdev->cache_shift)) - 1))
 127
 128 #define for_each_hwfn(cdev, i)  for (i = 0; i < cdev->num_hwfns; i++)
 129
 130 #define D_TRINE(val, cond1, cond2, true1, true2, def) \
 131         (val == (cond1) ? true1 :                     \
 132          (val == (cond2) ? true2 : def))
 133
 134 /* forward */
 135 struct qed_ptt_pool;
 136 struct qed_spq;
 137 struct qed_sb_info;
 138 struct qed_sb_attn_info;
 139 struct qed_cxt_mngr;
 140 struct qed_sb_sp_info;
 141 struct qed_ll2_info;
 142 struct qed_mcp_info;
 143 struct qed_llh_info;
 144
 145 struct qed_rt_data {
 146         u32     *init_val;
 147         bool    *b_valid;
 148 };
 149
 150 enum qed_tunn_mode {
 151         QED_MODE_L2GENEVE_TUNN,
 152         QED_MODE_IPGENEVE_TUNN,
 153         QED_MODE_L2GRE_TUNN,
 154         QED_MODE_IPGRE_TUNN,
 155         QED_MODE_VXLAN_TUNN,
 156 };
 157
 158 enum qed_tunn_clss {
 159         QED_TUNN_CLSS_MAC_VLAN,
 160         QED_TUNN_CLSS_MAC_VNI,
 161         QED_TUNN_CLSS_INNER_MAC_VLAN,
 162         QED_TUNN_CLSS_INNER_MAC_VNI,
 163         QED_TUNN_CLSS_MAC_VLAN_DUAL_STAGE,
 164         MAX_QED_TUNN_CLSS,
 165 };
 166
 167 struct qed_tunn_update_type {
 168         bool b_update_mode;
 169         bool b_mode_enabled;
 170         enum qed_tunn_clss tun_cls;
 171 };
 172
 173 struct qed_tunn_update_udp_port {
 174         bool b_update_port;
 175         u16 port;
 176 };
 177
 178 struct qed_tunnel_info {
 179         struct qed_tunn_update_type vxlan;
 180         struct qed_tunn_update_type l2_geneve;
 181         struct qed_tunn_update_type ip_geneve;
 182         struct qed_tunn_update_type l2_gre;
 183         struct qed_tunn_update_type ip_gre;
 184
 185         struct qed_tunn_update_udp_port vxlan_port;
 186         struct qed_tunn_update_udp_port geneve_port;
 187
 188         bool b_update_rx_cls;
 189         bool b_update_tx_cls;
 190 };
 191
 192 struct qed_tunn_start_params {
 193         unsigned long   tunn_mode;
 194         u16             vxlan_udp_port;
 195         u16             geneve_udp_port;
 196         u8              update_vxlan_udp_port;
 197         u8              update_geneve_udp_port;
 198         u8              tunn_clss_vxlan;
 199         u8              tunn_clss_l2geneve;
 200         u8              tunn_clss_ipgeneve;
 201         u8              tunn_clss_l2gre;
 202         u8              tunn_clss_ipgre;
 203 };
 204
 205 struct qed_tunn_update_params {
 206         unsigned long   tunn_mode_update_mask;
 207         unsigned long   tunn_mode;
 208         u16             vxlan_udp_port;
 209         u16             geneve_udp_port;
 210         u8              update_rx_pf_clss;
 211         u8              update_tx_pf_clss;
 212         u8              update_vxlan_udp_port;
 213         u8              update_geneve_udp_port;
 214         u8              tunn_clss_vxlan;
 215         u8              tunn_clss_l2geneve;
 216         u8              tunn_clss_ipgeneve;
 217         u8              tunn_clss_l2gre;
 218         u8              tunn_clss_ipgre;
 219 };
 220
 221 /* The PCI personality is not quite synonymous to protocol ID:
 222  * 1. All personalities need CORE connections
 223  * 2. The Ethernet personality may support also the RoCE/iWARP protocol
 224  */
 225 enum qed_pci_personality {
 226         QED_PCI_ETH,
 227         QED_PCI_FCOE,
 228         QED_PCI_ISCSI,
 229         QED_PCI_ETH_ROCE,
 230         QED_PCI_ETH_IWARP,
 231         QED_PCI_ETH_RDMA,
 232         QED_PCI_DEFAULT, /* default in shmem */
 233 };
 234
 235 /* All VFs are symmetric, all counters are PF + all VFs */
 236 struct qed_qm_iids {
 237         u32 cids;
 238         u32 vf_cids;
 239         u32 tids;
 240 };
 241
 242 /* HW / FW resources, output of features supported below, most information
 243  * is received from MFW.
 244  */
 245 enum qed_resources {
 246         QED_SB,
 247         QED_L2_QUEUE,
 248         QED_VPORT,
 249         QED_RSS_ENG,
 250         QED_PQ,
 251         QED_RL,
 252         QED_MAC,
 253         QED_VLAN,
 254         QED_RDMA_CNQ_RAM,
 255         QED_ILT,
 256         QED_LL2_RAM_QUEUE,
 257         QED_LL2_CTX_QUEUE,
 258         QED_CMDQS_CQS,
 259         QED_RDMA_STATS_QUEUE,
 260         QED_BDQ,
 261         QED_MAX_RESC,
 262 };
 263
 264 enum QED_FEATURE {
 265         QED_PF_L2_QUE,
 266         QED_VF,
 267         QED_RDMA_CNQ,
 268         QED_ISCSI_CQ,
 269         QED_FCOE_CQ,
 270         QED_VF_L2_QUE,
 271         QED_MAX_FEATURES,
 272 };
 273
 274 enum QED_PORT_MODE {
 275         QED_PORT_MODE_DE_2X40G,
 276         QED_PORT_MODE_DE_2X50G,
 277         QED_PORT_MODE_DE_1X100G,
 278         QED_PORT_MODE_DE_4X10G_F,
 279         QED_PORT_MODE_DE_4X10G_E,
 280         QED_PORT_MODE_DE_4X20G,
 281         QED_PORT_MODE_DE_1X40G,
 282         QED_PORT_MODE_DE_2X25G,
 283         QED_PORT_MODE_DE_1X25G,
 284         QED_PORT_MODE_DE_4X25G,
 285         QED_PORT_MODE_DE_2X10G,
 286 };
 287
 288 enum qed_dev_cap {
 289         QED_DEV_CAP_ETH,
 290         QED_DEV_CAP_FCOE,
 291         QED_DEV_CAP_ISCSI,
 292         QED_DEV_CAP_ROCE,
 293         QED_DEV_CAP_IWARP,
 294 };
 295
 296 enum qed_wol_support {
 297         QED_WOL_SUPPORT_NONE,
 298         QED_WOL_SUPPORT_PME,
 299 };
 300
 301 enum qed_db_rec_exec {
 302         DB_REC_DRY_RUN,
 303         DB_REC_REAL_DEAL,
 304         DB_REC_ONCE,
 305 };
 306
 307 struct qed_hw_info {
 308         /* PCI personality */
 309         enum qed_pci_personality personality;
 310 #define QED_IS_RDMA_PERSONALITY(dev)                        \
 311         ((dev)->hw_info.personality == QED_PCI_ETH_ROCE ||  \
 312          (dev)->hw_info.personality == QED_PCI_ETH_IWARP || \
 313          (dev)->hw_info.personality == QED_PCI_ETH_RDMA)
 314 #define QED_IS_ROCE_PERSONALITY(dev)                       \
 315         ((dev)->hw_info.personality == QED_PCI_ETH_ROCE || \
 316          (dev)->hw_info.personality == QED_PCI_ETH_RDMA)
 317 #define QED_IS_IWARP_PERSONALITY(dev)                       \
 318         ((dev)->hw_info.personality == QED_PCI_ETH_IWARP || \
 319          (dev)->hw_info.personality == QED_PCI_ETH_RDMA)
 320 #define QED_IS_L2_PERSONALITY(dev)                    \
 321         ((dev)->hw_info.personality == QED_PCI_ETH || \
 322          QED_IS_RDMA_PERSONALITY(dev))
 323 #define QED_IS_FCOE_PERSONALITY(dev) \
 324         ((dev)->hw_info.personality == QED_PCI_FCOE)
 325 #define QED_IS_ISCSI_PERSONALITY(dev) \
 326         ((dev)->hw_info.personality == QED_PCI_ISCSI)
 327
 328         /* Resource Allocation scheme results */
 329         u32                             resc_start[QED_MAX_RESC];
 330         u32                             resc_num[QED_MAX_RESC];
 331         u32                             feat_num[QED_MAX_FEATURES];
 332
 333 #define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc])
 334 #define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc])
 335 #define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \
 336                                  RESC_NUM(_p_hwfn, resc))
 337 #define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc])
 338
 339         /* Amount of traffic classes HW supports */
 340         u8 num_hw_tc;
 341
 342         /* Amount of TCs which should be active according to DCBx or upper
 343          * layer driver configuration.
 344          */
 345         u8 num_active_tc;
 346         u8                              offload_tc;
 347         bool                            offload_tc_set;
 348
 349         bool                            multi_tc_roce_en;
 350 #define IS_QED_MULTI_TC_ROCE(p_hwfn) (((p_hwfn)->hw_info.multi_tc_roce_en))
 351
 352         u32                             concrete_fid;
 353         u16                             opaque_fid;
 354         u16                             ovlan;
 355         u32                             part_num[4];
 356
 357         unsigned char                   hw_mac_addr[ETH_ALEN];
 358         u64                             node_wwn;
 359         u64                             port_wwn;
 360
 361         u16                             num_fcoe_conns;
 362
 363         struct qed_igu_info             *p_igu_info;
 364
 365         u32                             port_mode;
 366         u32                             hw_mode;
 367         unsigned long           device_capabilities;
 368         u16                             mtu;
 369
 370         enum qed_wol_support b_wol_support;
 371 };
 372
 373 /* maximun size of read/write commands (HW limit) */
 374 #define DMAE_MAX_RW_SIZE        0x2000
 375
 376 struct qed_dmae_info {
 377         /* Mutex for synchronizing access to functions */
 378         struct mutex    mutex;
 379
 380         u8              channel;
 381
 382         dma_addr_t      completion_word_phys_addr;
 383
 384         /* The memory location where the DMAE writes the completion
 385          * value when an operation is finished on this context.
 386          */
 387         u32             *p_completion_word;
 388
 389         dma_addr_t      intermediate_buffer_phys_addr;
 390
 391         /* An intermediate buffer for DMAE operations that use virtual
 392          * addresses - data is DMA'd to/from this buffer and then
 393          * memcpy'd to/from the virtual address
 394          */
 395         u32             *p_intermediate_buffer;
 396
 397         dma_addr_t      dmae_cmd_phys_addr;
 398         struct dmae_cmd *p_dmae_cmd;
 399 };
 400
 401 struct qed_wfq_data {
 402         /* when feature is configured for at least 1 vport */
 403         u32     min_speed;
 404         bool    configured;
 405 };
 406
 407 struct qed_qm_info {
 408         struct init_qm_pq_params        *qm_pq_params;
 409         struct init_qm_vport_params     *qm_vport_params;
 410         struct init_qm_port_params      *qm_port_params;
 411         u16                             start_pq;
 412         u8                              start_vport;
 413         u16                              pure_lb_pq;
 414         u16                             first_ofld_pq;
 415         u16                             first_llt_pq;
 416         u16                             pure_ack_pq;
 417         u16                             ooo_pq;
 418         u16                             first_vf_pq;
 419         u16                             first_mcos_pq;
 420         u16                             first_rl_pq;
 421         u16                             num_pqs;
 422         u16                             num_vf_pqs;
 423         u8                              num_vports;
 424         u8                              max_phys_tcs_per_port;
 425         u8                              ooo_tc;
 426         bool                            pf_rl_en;
 427         bool                            pf_wfq_en;
 428         bool                            vport_rl_en;
 429         bool                            vport_wfq_en;
 430         u8                              pf_wfq;
 431         u32                             pf_rl;
 432         struct qed_wfq_data             *wfq_data;
 433         u8 num_pf_rls;
 434 };
 435
 436 #define QED_OVERFLOW_BIT        1
 437
 438 struct qed_db_recovery_info {
 439         struct list_head list;
 440
 441         /* Lock to protect the doorbell recovery mechanism list */
 442         spinlock_t lock;
 443         bool dorq_attn;
 444         u32 db_recovery_counter;
 445         unsigned long overflow;
 446 };
 447
 448 struct storm_stats {
 449         u32     address;
 450         u32     len;
 451 };
 452
 453 struct qed_storm_stats {
 454         struct storm_stats mstats;
 455         struct storm_stats pstats;
 456         struct storm_stats tstats;
 457         struct storm_stats ustats;
 458 };
 459
 460 struct qed_fw_data {
 461         struct fw_ver_info      *fw_ver_info;
 462         const u8                *modes_tree_buf;
 463         union init_op           *init_ops;
 464         const u32               *arr_data;
 465         const u32               *fw_overlays;
 466         u32                     fw_overlays_len;
 467         u32                     init_ops_size;
 468 };
 469
 470 enum qed_mf_mode_bit {
 471         /* Supports PF-classification based on tag */
 472         QED_MF_OVLAN_CLSS,
 473
 474         /* Supports PF-classification based on MAC */
 475         QED_MF_LLH_MAC_CLSS,
 476
 477         /* Supports PF-classification based on protocol type */
 478         QED_MF_LLH_PROTO_CLSS,
 479
 480         /* Requires a default PF to be set */
 481         QED_MF_NEED_DEF_PF,
 482
 483         /* Allow LL2 to multicast/broadcast */
 484         QED_MF_LL2_NON_UNICAST,
 485
 486         /* Allow Cross-PF [& child VFs] Tx-switching */
 487         QED_MF_INTER_PF_SWITCH,
 488
 489         /* Unified Fabtic Port support enabled */
 490         QED_MF_UFP_SPECIFIC,
 491
 492         /* Disable Accelerated Receive Flow Steering (aRFS) */
 493         QED_MF_DISABLE_ARFS,
 494
 495         /* Use vlan for steering */
 496         QED_MF_8021Q_TAGGING,
 497
 498         /* Use stag for steering */
 499         QED_MF_8021AD_TAGGING,
 500
 501         /* Allow DSCP to TC mapping */
 502         QED_MF_DSCP_TO_TC_MAP,
 503
 504         /* Do not insert a vlan tag with id 0 */
 505         QED_MF_DONT_ADD_VLAN0_TAG,
 506 };
 507
 508 enum qed_ufp_mode {
 509         QED_UFP_MODE_ETS,
 510         QED_UFP_MODE_VNIC_BW,
 511         QED_UFP_MODE_UNKNOWN
 512 };
 513
 514 enum qed_ufp_pri_type {
 515         QED_UFP_PRI_OS,
 516         QED_UFP_PRI_VNIC,
 517         QED_UFP_PRI_UNKNOWN
 518 };
 519
 520 struct qed_ufp_info {
 521         enum qed_ufp_pri_type pri_type;
 522         enum qed_ufp_mode mode;
 523         u8 tc;
 524 };
 525
 526 enum BAR_ID {
 527         BAR_ID_0,               /* used for GRC */
 528         BAR_ID_1                /* Used for doorbells */
 529 };
 530
 531 struct qed_nvm_image_info {
 532         u32 num_images;
 533         struct bist_nvm_image_att *image_att;
 534         bool valid;
 535 };
 536
 537 enum qed_hsi_def_type {
 538         QED_HSI_DEF_MAX_NUM_VFS,
 539         QED_HSI_DEF_MAX_NUM_L2_QUEUES,
 540         QED_HSI_DEF_MAX_NUM_PORTS,
 541         QED_HSI_DEF_MAX_SB_PER_PATH,
 542         QED_HSI_DEF_MAX_NUM_PFS,
 543         QED_HSI_DEF_MAX_NUM_VPORTS,
 544         QED_HSI_DEF_NUM_ETH_RSS_ENGINE,
 545         QED_HSI_DEF_MAX_QM_TX_QUEUES,
 546         QED_HSI_DEF_NUM_PXP_ILT_RECORDS,
 547         QED_HSI_DEF_NUM_RDMA_STATISTIC_COUNTERS,
 548         QED_HSI_DEF_MAX_QM_GLOBAL_RLS,
 549         QED_HSI_DEF_MAX_PBF_CMD_LINES,
 550         QED_HSI_DEF_MAX_BTB_BLOCKS,
 551         QED_NUM_HSI_DEFS
 552 };
 553
 554 #define DRV_MODULE_VERSION                    \
 555         __stringify(QED_MAJOR_VERSION) "."    \
 556         __stringify(QED_MINOR_VERSION) "."    \
 557         __stringify(QED_REVISION_VERSION) "." \
 558         __stringify(QED_ENGINEERING_VERSION)
 559
 560 struct qed_simd_fp_handler {
 561         void    *token;
 562         void    (*func)(void *);
 563 };
 564
 565 enum qed_slowpath_wq_flag {
 566         QED_SLOWPATH_MFW_TLV_REQ,
 567         QED_SLOWPATH_PERIODIC_DB_REC,
 568 };
 569
 570 struct qed_hwfn {
 571         struct qed_dev                  *cdev;
 572         u8                              my_id;          /* ID inside the PF */
 573 #define IS_LEAD_HWFN(edev)              (!((edev)->my_id))
 574         u8                              rel_pf_id;      /* Relative to engine*/
 575         u8                              abs_pf_id;
 576 #define QED_PATH_ID(_p_hwfn) \
 577         (QED_IS_K2((_p_hwfn)->cdev) ? 0 : ((_p_hwfn)->abs_pf_id & 1))
 578         u8                              port_id;
 579         bool                            b_active;
 580
 581         u32                             dp_module;
 582         u8                              dp_level;
 583         char                            name[NAME_SIZE];
 584
 585         bool                            hw_init_done;
 586
 587         u8                              num_funcs_on_engine;
 588         u8 enabled_func_idx;
 589
 590         /* BAR access */
 591         void __iomem                    *regview;
 592         void __iomem                    *doorbells;
 593         u64                             db_phys_addr;
 594         unsigned long                   db_size;
 595
 596         /* PTT pool */
 597         struct qed_ptt_pool             *p_ptt_pool;
 598
 599         /* HW info */
 600         struct qed_hw_info              hw_info;
 601
 602         /* rt_array (for init-tool) */
 603         struct qed_rt_data              rt_data;
 604
 605         /* SPQ */
 606         struct qed_spq                  *p_spq;
 607
 608         /* EQ */
 609         struct qed_eq                   *p_eq;
 610
 611         /* Consolidate Q*/
 612         struct qed_consq                *p_consq;
 613
 614         /* Slow-Path definitions */
 615         struct tasklet_struct           *sp_dpc;
 616         bool                            b_sp_dpc_enabled;
 617
 618         struct qed_ptt                  *p_main_ptt;
 619         struct qed_ptt                  *p_dpc_ptt;
 620
 621         /* PTP will be used only by the leading function.
 622          * Usage of all PTP-apis should be synchronized as result.
 623          */
 624         struct qed_ptt *p_ptp_ptt;
 625
 626         struct qed_sb_sp_info           *p_sp_sb;
 627         struct qed_sb_attn_info         *p_sb_attn;
 628
 629         /* Protocol related */
 630         bool                            using_ll2;
 631         struct qed_ll2_info             *p_ll2_info;
 632         struct qed_ooo_info             *p_ooo_info;
 633         struct qed_rdma_info            *p_rdma_info;
 634         struct qed_iscsi_info           *p_iscsi_info;
 635         struct qed_fcoe_info            *p_fcoe_info;
 636         struct qed_pf_params            pf_params;
 637
 638         bool b_rdma_enabled_in_prs;
 639         u32 rdma_prs_search_reg;
 640
 641         struct qed_cxt_mngr             *p_cxt_mngr;
 642
 643         /* Flag indicating whether interrupts are enabled or not*/
 644         bool                            b_int_enabled;
 645         bool                            b_int_requested;
 646
 647         /* True if the driver requests for the link */
 648         bool                            b_drv_link_init;
 649
 650         struct qed_vf_iov               *vf_iov_info;
 651         struct qed_pf_iov               *pf_iov_info;
 652         struct qed_mcp_info             *mcp_info;
 653
 654         struct qed_dcbx_info            *p_dcbx_info;
 655
 656         struct qed_ufp_info             ufp_info;
 657
 658         struct qed_dmae_info            dmae_info;
 659
 660         /* QM init */
 661         struct qed_qm_info              qm_info;
 662         struct qed_storm_stats          storm_stats;
 663
 664         /* Buffer for unzipping firmware data */
 665         void                            *unzip_buf;
 666
 667         struct dbg_tools_data           dbg_info;
 668         void                            *dbg_user_info;
 669         struct virt_mem_desc            dbg_arrays[MAX_BIN_DBG_BUFFER_TYPE];
 670
 671         /* PWM region specific data */
 672         u16                             wid_count;
 673         u32                             dpi_size;
 674         u32                             dpi_count;
 675
 676         /* This is used to calculate the doorbell address */
 677         u32 dpi_start_offset;
 678
 679         /* If one of the following is set then EDPM shouldn't be used */
 680         u8 dcbx_no_edpm;
 681         u8 db_bar_no_edpm;
 682
 683         /* L2-related */
 684         struct qed_l2_info *p_l2_info;
 685
 686         /* Mechanism for recovering from doorbell drop */
 687         struct qed_db_recovery_info db_recovery_info;
 688
 689         /* Nvm images number and attributes */
 690         struct qed_nvm_image_info nvm_info;
 691
 692         struct phys_mem_desc *fw_overlay_mem;
 693         struct qed_ptt *p_arfs_ptt;
 694
 695         struct qed_simd_fp_handler      simd_proto_handler[64];
 696
 697 #ifdef CONFIG_QED_SRIOV
 698         struct workqueue_struct *iov_wq;
 699         struct delayed_work iov_task;
 700         unsigned long iov_task_flags;
 701 #endif
 702         struct z_stream_s *stream;
 703         bool slowpath_wq_active;
 704         struct workqueue_struct *slowpath_wq;
 705         struct delayed_work slowpath_task;
 706         unsigned long slowpath_task_flags;
 707         u32 periodic_db_rec_count;
 708 };
 709
 710 struct pci_params {
 711         int             pm_cap;
 712
 713         unsigned long   mem_start;
 714         unsigned long   mem_end;
 715         unsigned int    irq;
 716         u8              pf_num;
 717 };
 718
 719 struct qed_int_param {
 720         u32     int_mode;
 721         u8      num_vectors;
 722         u8      min_msix_cnt; /* for minimal functionality */
 723 };
 724
 725 struct qed_int_params {
 726         struct qed_int_param    in;
 727         struct qed_int_param    out;
 728         struct msix_entry       *msix_table;
 729         bool                    fp_initialized;
 730         u8                      fp_msix_base;
 731         u8                      fp_msix_cnt;
 732         u8                      rdma_msix_base;
 733         u8                      rdma_msix_cnt;
 734 };
 735
 736 struct qed_dbg_feature {
 737         struct dentry *dentry;
 738         u8 *dump_buf;
 739         u32 buf_size;
 740         u32 dumped_dwords;
 741 };
 742
 743 struct qed_dbg_params {
 744         struct qed_dbg_feature features[DBG_FEATURE_NUM];
 745         u8 engine_for_debug;
 746         bool print_data;
 747 };
 748
 749 struct qed_dev {
 750         u32     dp_module;
 751         u8      dp_level;
 752         char    name[NAME_SIZE];
 753
 754         enum    qed_dev_type type;
 755 /* Translate type/revision combo into the proper conditions */
 756 #define QED_IS_BB(dev)  ((dev)->type == QED_DEV_TYPE_BB)
 757 #define QED_IS_BB_B0(dev)       (QED_IS_BB(dev) && \
 758                                  CHIP_REV_IS_B0(dev))
 759 #define QED_IS_AH(dev)  ((dev)->type == QED_DEV_TYPE_AH)
 760 #define QED_IS_K2(dev)  QED_IS_AH(dev)
 761
 762         u16     vendor_id;
 763         u16     device_id;
 764 #define QED_DEV_ID_MASK         0xff00
 765 #define QED_DEV_ID_MASK_BB      0x1600
 766 #define QED_DEV_ID_MASK_AH      0x8000
 767 #define QED_IS_E4(dev)  (QED_IS_BB(dev) || QED_IS_AH(dev))
 768
 769         u16     chip_num;
 770 #define CHIP_NUM_MASK                   0xffff
 771 #define CHIP_NUM_SHIFT                  16
 772
 773         u16     chip_rev;
 774 #define CHIP_REV_MASK                   0xf
 775 #define CHIP_REV_SHIFT                  12
 776 #define CHIP_REV_IS_B0(_cdev)   ((_cdev)->chip_rev == 1)
 777
 778         u16                             chip_metal;
 779 #define CHIP_METAL_MASK                 0xff
 780 #define CHIP_METAL_SHIFT                4
 781
 782         u16                             chip_bond_id;
 783 #define CHIP_BOND_ID_MASK               0xf
 784 #define CHIP_BOND_ID_SHIFT              0
 785
 786         u8                              num_engines;
 787         u8                              num_ports;
 788         u8                              num_ports_in_engine;
 789         u8                              num_funcs_in_port;
 790
 791         u8                              path_id;
 792
 793         unsigned long                   mf_bits;
 794
 795         int                             pcie_width;
 796         int                             pcie_speed;
 797
 798         /* Add MF related configuration */
 799         u8                              mcp_rev;
 800         u8                              boot_mode;
 801
 802         /* WoL related configurations */
 803         u8 wol_config;
 804         u8 wol_mac[ETH_ALEN];
 805
 806         u32                             int_mode;
 807         enum qed_coalescing_mode        int_coalescing_mode;
 808         u16                             rx_coalesce_usecs;
 809         u16                             tx_coalesce_usecs;
 810
 811         /* Start Bar offset of first hwfn */
 812         void __iomem                    *regview;
 813         void __iomem                    *doorbells;
 814         u64                             db_phys_addr;
 815         unsigned long                   db_size;
 816
 817         /* PCI */
 818         u8                              cache_shift;
 819
 820         /* Init */
 821         const u32 *iro_arr;
 822 #define IRO ((const struct iro *)p_hwfn->cdev->iro_arr)
 823
 824         /* HW functions */
 825         u8                              num_hwfns;
 826         struct qed_hwfn                 hwfns[MAX_HWFNS_PER_DEVICE];
 827
 828         /* Engine affinity */
 829         u8                              l2_affin_hint;
 830         u8                              fir_affin;
 831         u8                              iwarp_affin;
 832
 833         /* SRIOV */
 834         struct qed_hw_sriov_info *p_iov_info;
 835 #define IS_QED_SRIOV(cdev)              (!!(cdev)->p_iov_info)
 836         struct qed_tunnel_info          tunnel;
 837         bool                            b_is_vf;
 838         u32                             drv_type;
 839         struct qed_eth_stats            *reset_stats;
 840         struct qed_fw_data              *fw_data;
 841
 842         u32                             mcp_nvm_resp;
 843
 844         /* Recovery */
 845         bool recov_in_prog;
 846
 847         /* LLH info */
 848         u8 ppfid_bitmap;
 849         struct qed_llh_info *p_llh_info;
 850
 851         /* Linux specific here */
 852         struct  qede_dev                *edev;
 853         struct  pci_dev                 *pdev;
 854         u32 flags;
 855 #define QED_FLAG_STORAGE_STARTED        (BIT(0))
 856         int                             msg_enable;
 857
 858         struct pci_params               pci_params;
 859
 860         struct qed_int_params           int_params;
 861
 862         u8                              protocol;
 863 #define IS_QED_ETH_IF(cdev)     ((cdev)->protocol == QED_PROTOCOL_ETH)
 864 #define IS_QED_FCOE_IF(cdev)    ((cdev)->protocol == QED_PROTOCOL_FCOE)
 865
 866         /* Callbacks to protocol driver */
 867         union {
 868                 struct qed_common_cb_ops        *common;
 869                 struct qed_eth_cb_ops           *eth;
 870                 struct qed_fcoe_cb_ops          *fcoe;
 871                 struct qed_iscsi_cb_ops         *iscsi;
 872         } protocol_ops;
 873         void                            *ops_cookie;
 874
 875         struct qed_dbg_params           dbg_params;
 876
 877 #ifdef CONFIG_QED_LL2
 878         struct qed_cb_ll2_info          *ll2;
 879         u8                              ll2_mac_address[ETH_ALEN];
 880 #endif
 881         struct qed_dbg_feature dbg_features[DBG_FEATURE_NUM];
 882         bool disable_ilt_dump;
 883         DECLARE_HASHTABLE(connections, 10);
 884         const struct firmware           *firmware;
 885
 886         u32 rdma_max_sge;
 887         u32 rdma_max_inline;
 888         u32 rdma_max_srq_sge;
 889         u16 tunn_feature_mask;
 890
 891         struct devlink                  *dl;
 892         bool                            iwarp_cmt;
 893 };
 894
 895 u32 qed_get_hsi_def_val(struct qed_dev *cdev, enum qed_hsi_def_type type);
 896
 897 #define NUM_OF_VFS(dev) \
 898         qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_NUM_VFS)
 899 #define NUM_OF_L2_QUEUES(dev) \
 900         qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_NUM_L2_QUEUES)
 901 #define NUM_OF_PORTS(dev) \
 902         qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_NUM_PORTS)
 903 #define NUM_OF_SBS(dev) \
 904         qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_SB_PER_PATH)
 905 #define NUM_OF_ENG_PFS(dev) \
 906         qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_NUM_PFS)
 907 #define NUM_OF_VPORTS(dev) \
 908         qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_NUM_VPORTS)
 909 #define NUM_OF_RSS_ENGINES(dev) \
 910         qed_get_hsi_def_val(dev, QED_HSI_DEF_NUM_ETH_RSS_ENGINE)
 911 #define NUM_OF_QM_TX_QUEUES(dev) \
 912         qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_QM_TX_QUEUES)
 913 #define NUM_OF_PXP_ILT_RECORDS(dev) \
 914         qed_get_hsi_def_val(dev, QED_HSI_DEF_NUM_PXP_ILT_RECORDS)
 915 #define NUM_OF_RDMA_STATISTIC_COUNTERS(dev) \
 916         qed_get_hsi_def_val(dev, QED_HSI_DEF_NUM_RDMA_STATISTIC_COUNTERS)
 917 #define NUM_OF_QM_GLOBAL_RLS(dev) \
 918         qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_QM_GLOBAL_RLS)
 919 #define NUM_OF_PBF_CMD_LINES(dev) \
 920         qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_PBF_CMD_LINES)
 921 #define NUM_OF_BTB_BLOCKS(dev) \
 922         qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_BTB_BLOCKS)
 923
 924
 925 /**
 926  * @brief qed_concrete_to_sw_fid - get the sw function id from
 927  *        the concrete value.
 928  *
 929  * @param concrete_fid
 930  *
 931  * @return inline u8
 932  */
 933 static inline u8 qed_concrete_to_sw_fid(struct qed_dev *cdev,
 934                                         u32 concrete_fid)
 935 {
 936         u8 vfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID);
 937         u8 pfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID);
 938         u8 vf_valid = GET_FIELD(concrete_fid,
 939                                 PXP_CONCRETE_FID_VFVALID);
 940         u8 sw_fid;
 941
 942         if (vf_valid)
 943                 sw_fid = vfid + MAX_NUM_PFS;
 944         else
 945                 sw_fid = pfid;
 946
 947         return sw_fid;
 948 }
 949
 950 #define PKT_LB_TC       9
 951 #define MAX_NUM_VOQS_E4 20
 952
 953 int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate);
 954 void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev,
 955                                          struct qed_ptt *p_ptt,
 956                                          u32 min_pf_rate);
 957
 958 void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt);
 959 int qed_device_num_engines(struct qed_dev *cdev);
 960 void qed_set_fw_mac_addr(__le16 *fw_msb,
 961                          __le16 *fw_mid, __le16 *fw_lsb, u8 *mac);
 962
 963 #define QED_LEADING_HWFN(dev)   (&dev->hwfns[0])
 964 #define QED_IS_CMT(dev)         ((dev)->num_hwfns > 1)
 965 /* Macros for getting the engine-affinitized hwfn (FIR: fcoe,iscsi,roce) */
 966 #define QED_FIR_AFFIN_HWFN(dev)         (&(dev)->hwfns[dev->fir_affin])
 967 #define QED_IWARP_AFFIN_HWFN(dev)       (&(dev)->hwfns[dev->iwarp_affin])
 968 #define QED_AFFIN_HWFN(dev)                                \
 969         (QED_IS_IWARP_PERSONALITY(QED_LEADING_HWFN(dev)) ? \
 970          QED_IWARP_AFFIN_HWFN(dev) : QED_FIR_AFFIN_HWFN(dev))
 971 #define QED_AFFIN_HWFN_IDX(dev) (IS_LEAD_HWFN(QED_AFFIN_HWFN(dev)) ? 0 : 1)
 972
 973 /* Flags for indication of required queues */
 974 #define PQ_FLAGS_RLS    (BIT(0))
 975 #define PQ_FLAGS_MCOS   (BIT(1))
 976 #define PQ_FLAGS_LB     (BIT(2))
 977 #define PQ_FLAGS_OOO    (BIT(3))
 978 #define PQ_FLAGS_ACK    (BIT(4))
 979 #define PQ_FLAGS_OFLD   (BIT(5))
 980 #define PQ_FLAGS_VFS    (BIT(6))
 981 #define PQ_FLAGS_LLT    (BIT(7))
 982 #define PQ_FLAGS_MTC    (BIT(8))
 983
 984 /* physical queue index for cm context intialization */
 985 u16 qed_get_cm_pq_idx(struct qed_hwfn *p_hwfn, u32 pq_flags);
 986 u16 qed_get_cm_pq_idx_mcos(struct qed_hwfn *p_hwfn, u8 tc);
 987 u16 qed_get_cm_pq_idx_vf(struct qed_hwfn *p_hwfn, u16 vf);
 988 u16 qed_get_cm_pq_idx_ofld_mtc(struct qed_hwfn *p_hwfn, u8 tc);
 989 u16 qed_get_cm_pq_idx_llt_mtc(struct qed_hwfn *p_hwfn, u8 tc);
 990
 991 /* doorbell recovery mechanism */
 992 void qed_db_recovery_dp(struct qed_hwfn *p_hwfn);
 993 void qed_db_recovery_execute(struct qed_hwfn *p_hwfn);
 994 bool qed_edpm_enabled(struct qed_hwfn *p_hwfn);
 995
 996 /* Other Linux specific common definitions */
 997 #define DP_NAME(cdev) ((cdev)->name)
 998
 999 #define REG_ADDR(cdev, offset)          (void __iomem *)((u8 __iomem *)\
1000                                                 (cdev->regview) + \
1001                                                          (offset))
1002
1003 #define REG_RD(cdev, offset)            readl(REG_ADDR(cdev, offset))
1004 #define REG_WR(cdev, offset, val)       writel((u32)val, REG_ADDR(cdev, offset))
1005 #define REG_WR16(cdev, offset, val)     writew((u16)val, REG_ADDR(cdev, offset))
1006
1007 #define DOORBELL(cdev, db_addr, val)                     \
1008         writel((u32)val, (void __iomem *)((u8 __iomem *)\
1009                                           (cdev->doorbells) + (db_addr)))
1010
1011 #define MFW_PORT(_p_hwfn)       ((_p_hwfn)->abs_pf_id %                   \
1012                                   qed_device_num_ports((_p_hwfn)->cdev))
1013 int qed_device_num_ports(struct qed_dev *cdev);
1014
1015 /* Prototypes */
1016 int qed_fill_dev_info(struct qed_dev *cdev,
1017                       struct qed_dev_info *dev_info);
1018 void qed_link_update(struct qed_hwfn *hwfn, struct qed_ptt *ptt);
1019 u32 qed_unzip_data(struct qed_hwfn *p_hwfn,
1020                    u32 input_len, u8 *input_buf,
1021                    u32 max_size, u8 *unzip_buf);
1022 void qed_schedule_recovery_handler(struct qed_hwfn *p_hwfn);
1023 void qed_get_protocol_stats(struct qed_dev *cdev,
1024                             enum qed_mcp_protocol_type type,
1025                             union qed_mcp_protocol_stats *stats);
1026 int qed_slowpath_irq_req(struct qed_hwfn *hwfn);
1027 void qed_slowpath_irq_sync(struct qed_hwfn *p_hwfn);
1028 int qed_mfw_tlv_req(struct qed_hwfn *hwfn);
1029
1030 int qed_mfw_fill_tlv_data(struct qed_hwfn *hwfn,
1031                           enum qed_mfw_tlv_type type,
1032                           union qed_mfw_tlv_data *tlv_data);
1033
1034 void qed_hw_info_set_offload_tc(struct qed_hw_info *p_info, u8 tc);
1035
1036 void qed_periodic_db_rec_start(struct qed_hwfn *p_hwfn);
1037 #endif /* _QED_H */