1 /* QLogic qed NIC Driver
2 * Copyright (c) 2015 QLogic Corporation
4 * This software is available under the terms of the GNU General Public License
5 * (GPL) Version 2, available from the file COPYING in the main directory of
12 #include <linux/types.h>
14 #include <linux/delay.h>
15 #include <linux/firmware.h>
16 #include <linux/interrupt.h>
17 #include <linux/list.h>
18 #include <linux/mutex.h>
19 #include <linux/pci.h>
20 #include <linux/slab.h>
21 #include <linux/string.h>
22 #include <linux/workqueue.h>
23 #include <linux/zlib.h>
24 #include <linux/hashtable.h>
25 #include <linux/qed/qed_if.h>
28 extern const struct qed_common_ops qed_common_ops_pass;
29 #define DRV_MODULE_VERSION "8.7.1.20"
31 #define MAX_HWFNS_PER_DEVICE (4)
35 #define QED_WFQ_UNIT 100
38 enum qed_coalescing_mode {
39 QED_COAL_MODE_DISABLE,
43 struct qed_eth_cb_ops;
47 static inline u32 qed_db_addr(u32 cid, u32 DEMS)
49 u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
50 FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid);
55 #define ALIGNED_TYPE_SIZE(type_name, p_hwfn) \
56 ((sizeof(type_name) + (u32)(1 << (p_hwfn->cdev->cache_shift)) - 1) & \
57 ~((1 << (p_hwfn->cdev->cache_shift)) - 1))
59 #define for_each_hwfn(cdev, i) for (i = 0; i < cdev->num_hwfns; i++)
61 #define D_TRINE(val, cond1, cond2, true1, true2, def) \
62 (val == (cond1) ? true1 : \
63 (val == (cond2) ? true2 : def))
69 struct qed_sb_attn_info;
71 struct qed_sb_sp_info;
80 QED_MODE_L2GENEVE_TUNN,
81 QED_MODE_IPGENEVE_TUNN,
88 QED_TUNN_CLSS_MAC_VLAN,
89 QED_TUNN_CLSS_MAC_VNI,
90 QED_TUNN_CLSS_INNER_MAC_VLAN,
91 QED_TUNN_CLSS_INNER_MAC_VNI,
95 struct qed_tunn_start_params {
96 unsigned long tunn_mode;
99 u8 update_vxlan_udp_port;
100 u8 update_geneve_udp_port;
102 u8 tunn_clss_l2geneve;
103 u8 tunn_clss_ipgeneve;
108 struct qed_tunn_update_params {
109 unsigned long tunn_mode_update_mask;
110 unsigned long tunn_mode;
113 u8 update_rx_pf_clss;
114 u8 update_tx_pf_clss;
115 u8 update_vxlan_udp_port;
116 u8 update_geneve_udp_port;
118 u8 tunn_clss_l2geneve;
119 u8 tunn_clss_ipgeneve;
124 /* The PCI personality is not quite synonymous to protocol ID:
125 * 1. All personalities need CORE connections
126 * 2. The Ethernet personality may support also the RoCE protocol
128 enum qed_pci_personality {
130 QED_PCI_DEFAULT /* default in shmem */
133 /* All VFs are symmetric, all counters are PF + all VFs */
160 QED_PORT_MODE_DE_2X40G,
161 QED_PORT_MODE_DE_2X50G,
162 QED_PORT_MODE_DE_1X100G,
163 QED_PORT_MODE_DE_4X10G_F,
164 QED_PORT_MODE_DE_4X10G_E,
165 QED_PORT_MODE_DE_4X20G,
166 QED_PORT_MODE_DE_1X40G,
167 QED_PORT_MODE_DE_2X25G,
168 QED_PORT_MODE_DE_1X25G
176 /* PCI personality */
177 enum qed_pci_personality personality;
179 /* Resource Allocation scheme results */
180 u32 resc_start[QED_MAX_RESC];
181 u32 resc_num[QED_MAX_RESC];
182 u32 feat_num[QED_MAX_FEATURES];
184 #define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc])
185 #define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc])
186 #define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc])
197 unsigned char hw_mac_addr[ETH_ALEN];
199 struct qed_igu_info *p_igu_info;
203 unsigned long device_capabilities;
206 struct qed_hw_cid_data {
208 bool b_cid_allocated;
210 /* Additional identifiers */
215 /* maximun size of read/write commands (HW limit) */
216 #define DMAE_MAX_RW_SIZE 0x2000
218 struct qed_dmae_info {
219 /* Mutex for synchronizing access to functions */
224 dma_addr_t completion_word_phys_addr;
226 /* The memory location where the DMAE writes the completion
227 * value when an operation is finished on this context.
229 u32 *p_completion_word;
231 dma_addr_t intermediate_buffer_phys_addr;
233 /* An intermediate buffer for DMAE operations that use virtual
234 * addresses - data is DMA'd to/from this buffer and then
235 * memcpy'd to/from the virtual address
237 u32 *p_intermediate_buffer;
239 dma_addr_t dmae_cmd_phys_addr;
240 struct dmae_cmd *p_dmae_cmd;
243 struct qed_wfq_data {
244 /* when feature is configured for at least 1 vport */
250 struct init_qm_pq_params *qm_pq_params;
251 struct init_qm_vport_params *qm_vport_params;
252 struct init_qm_port_params *qm_port_params;
262 u8 max_phys_tcs_per_port;
269 struct qed_wfq_data *wfq_data;
277 struct qed_storm_stats {
278 struct storm_stats mstats;
279 struct storm_stats pstats;
280 struct storm_stats tstats;
281 struct storm_stats ustats;
285 struct fw_ver_info *fw_ver_info;
286 const u8 *modes_tree_buf;
287 union init_op *init_ops;
292 struct qed_simd_fp_handler {
294 void (*func)(void *);
298 struct qed_dev *cdev;
299 u8 my_id; /* ID inside the PF */
300 #define IS_LEAD_HWFN(edev) (!((edev)->my_id))
301 u8 rel_pf_id; /* Relative to engine*/
303 #define QED_PATH_ID(_p_hwfn) ((_p_hwfn)->abs_pf_id & 1)
309 char name[NAME_SIZE];
311 bool first_on_engine;
314 u8 num_funcs_on_engine;
317 void __iomem *regview;
318 void __iomem *doorbells;
320 unsigned long db_size;
323 struct qed_ptt_pool *p_ptt_pool;
326 struct qed_hw_info hw_info;
328 /* rt_array (for init-tool) */
329 struct qed_rt_data rt_data;
332 struct qed_spq *p_spq;
338 struct qed_consq *p_consq;
340 /* Slow-Path definitions */
341 struct tasklet_struct *sp_dpc;
342 bool b_sp_dpc_enabled;
344 struct qed_ptt *p_main_ptt;
345 struct qed_ptt *p_dpc_ptt;
347 struct qed_sb_sp_info *p_sp_sb;
348 struct qed_sb_attn_info *p_sb_attn;
350 /* Protocol related */
351 struct qed_pf_params pf_params;
353 /* Array of sb_info of all status blocks */
354 struct qed_sb_info *sbs_info[MAX_SB_PER_PF_MIMD];
357 struct qed_cxt_mngr *p_cxt_mngr;
359 /* Flag indicating whether interrupts are enabled or not*/
361 bool b_int_requested;
363 /* True if the driver requests for the link */
364 bool b_drv_link_init;
366 struct qed_vf_iov *vf_iov_info;
367 struct qed_pf_iov *pf_iov_info;
368 struct qed_mcp_info *mcp_info;
370 struct qed_hw_cid_data *p_tx_cids;
371 struct qed_hw_cid_data *p_rx_cids;
373 struct qed_dmae_info dmae_info;
376 struct qed_qm_info qm_info;
377 struct qed_storm_stats storm_stats;
379 /* Buffer for unzipping firmware data */
382 struct qed_simd_fp_handler simd_proto_handler[64];
384 #ifdef CONFIG_QED_SRIOV
385 struct workqueue_struct *iov_wq;
386 struct delayed_work iov_task;
387 unsigned long iov_task_flags;
390 struct z_stream_s *stream;
396 unsigned long mem_start;
397 unsigned long mem_end;
402 struct qed_int_param {
405 u8 min_msix_cnt; /* for minimal functionality */
408 struct qed_int_params {
409 struct qed_int_param in;
410 struct qed_int_param out;
411 struct msix_entry *msix_table;
420 char name[NAME_SIZE];
423 #define QED_DEV_TYPE_BB (0 << 0)
424 #define QED_DEV_TYPE_AH BIT(0)
425 /* Translate type/revision combo into the proper conditions */
426 #define QED_IS_BB(dev) ((dev)->type == QED_DEV_TYPE_BB)
427 #define QED_IS_BB_A0(dev) (QED_IS_BB(dev) && \
429 #define QED_IS_BB_B0(dev) (QED_IS_BB(dev) && \
432 #define QED_GET_TYPE(dev) (QED_IS_BB_A0(dev) ? CHIP_BB_A0 : \
433 QED_IS_BB_B0(dev) ? CHIP_BB_B0 : CHIP_K2)
439 #define CHIP_NUM_MASK 0xffff
440 #define CHIP_NUM_SHIFT 16
443 #define CHIP_REV_MASK 0xf
444 #define CHIP_REV_SHIFT 12
445 #define CHIP_REV_IS_A0(_cdev) (!(_cdev)->chip_rev)
446 #define CHIP_REV_IS_B0(_cdev) ((_cdev)->chip_rev == 1)
449 #define CHIP_METAL_MASK 0xff
450 #define CHIP_METAL_SHIFT 4
453 #define CHIP_BOND_ID_MASK 0xf
454 #define CHIP_BOND_ID_SHIFT 0
457 u8 num_ports_in_engines;
458 u8 num_funcs_in_port;
461 enum qed_mf_mode mf_mode;
462 #define IS_MF_DEFAULT(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_DEFAULT)
463 #define IS_MF_SI(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_NPAR)
464 #define IS_MF_SD(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_OVLAN)
468 u8 ver_str[VER_SIZE];
470 /* Add MF related configuration */
477 enum qed_coalescing_mode int_coalescing_mode;
478 u8 rx_coalesce_usecs;
479 u8 tx_coalesce_usecs;
481 /* Start Bar offset of first hwfn */
482 void __iomem *regview;
483 void __iomem *doorbells;
485 unsigned long db_size;
491 const struct iro *iro_arr;
492 #define IRO (p_hwfn->cdev->iro_arr)
496 struct qed_hwfn hwfns[MAX_HWFNS_PER_DEVICE];
499 struct qed_hw_sriov_info *p_iov_info;
500 #define IS_QED_SRIOV(cdev) (!!(cdev)->p_iov_info)
502 unsigned long tunn_mode;
507 struct qed_eth_stats *reset_stats;
508 struct qed_fw_data *fw_data;
512 /* Linux specific here */
513 struct qede_dev *edev;
514 struct pci_dev *pdev;
517 struct pci_params pci_params;
519 struct qed_int_params int_params;
522 #define IS_QED_ETH_IF(cdev) ((cdev)->protocol == QED_PROTOCOL_ETH)
524 /* Callbacks to protocol driver */
526 struct qed_common_cb_ops *common;
527 struct qed_eth_cb_ops *eth;
531 const struct firmware *firmware;
534 #define NUM_OF_VFS(dev) MAX_NUM_VFS_BB
535 #define NUM_OF_SBS(dev) MAX_SB_PER_PATH_BB
536 #define NUM_OF_ENG_PFS(dev) MAX_NUM_PFS_BB
539 * @brief qed_concrete_to_sw_fid - get the sw function id from
540 * the concrete value.
542 * @param concrete_fid
546 static inline u8 qed_concrete_to_sw_fid(struct qed_dev *cdev,
549 u8 pfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID);
556 void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev, u32 min_pf_rate);
558 #define QED_LEADING_HWFN(dev) (&dev->hwfns[0])
560 /* Other Linux specific common definitions */
561 #define DP_NAME(cdev) ((cdev)->name)
563 #define REG_ADDR(cdev, offset) (void __iomem *)((u8 __iomem *)\
567 #define REG_RD(cdev, offset) readl(REG_ADDR(cdev, offset))
568 #define REG_WR(cdev, offset, val) writel((u32)val, REG_ADDR(cdev, offset))
569 #define REG_WR16(cdev, offset, val) writew((u16)val, REG_ADDR(cdev, offset))
571 #define DOORBELL(cdev, db_addr, val) \
572 writel((u32)val, (void __iomem *)((u8 __iomem *)\
573 (cdev->doorbells) + (db_addr)))
576 int qed_fill_dev_info(struct qed_dev *cdev,
577 struct qed_dev_info *dev_info);
578 void qed_link_update(struct qed_hwfn *hwfn);
579 u32 qed_unzip_data(struct qed_hwfn *p_hwfn,
580 u32 input_len, u8 *input_buf,
581 u32 max_size, u8 *unzip_buf);
583 int qed_slowpath_irq_req(struct qed_hwfn *hwfn);