drivers/net/ethernet/qlogic/qed/qed.h

   1 /* QLogic qed NIC Driver
   2  * Copyright (c) 2015-2017  QLogic Corporation
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and /or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #ifndef _QED_H
  34 #define _QED_H
  35
  36 #include <linux/types.h>
  37 #include <linux/io.h>
  38 #include <linux/delay.h>
  39 #include <linux/firmware.h>
  40 #include <linux/interrupt.h>
  41 #include <linux/list.h>
  42 #include <linux/mutex.h>
  43 #include <linux/pci.h>
  44 #include <linux/slab.h>
  45 #include <linux/string.h>
  46 #include <linux/workqueue.h>
  47 #include <linux/zlib.h>
  48 #include <linux/hashtable.h>
  49 #include <linux/qed/qed_if.h>
  50 #include "qed_debug.h"
  51 #include "qed_hsi.h"
  52
  53 extern const struct qed_common_ops qed_common_ops_pass;
  54
  55 #define QED_MAJOR_VERSION               8
  56 #define QED_MINOR_VERSION               10
  57 #define QED_REVISION_VERSION            10
  58 #define QED_ENGINEERING_VERSION 21
  59
  60 #define QED_VERSION                                              \
  61         ((QED_MAJOR_VERSION << 24) | (QED_MINOR_VERSION << 16) | \
  62          (QED_REVISION_VERSION << 8) | QED_ENGINEERING_VERSION)
  63
  64 #define STORM_FW_VERSION                                       \
  65         ((FW_MAJOR_VERSION << 24) | (FW_MINOR_VERSION << 16) | \
  66          (FW_REVISION_VERSION << 8) | FW_ENGINEERING_VERSION)
  67
  68 #define MAX_HWFNS_PER_DEVICE    (4)
  69 #define NAME_SIZE 16
  70 #define VER_SIZE 16
  71
  72 #define QED_WFQ_UNIT    100
  73
  74 #define ISCSI_BDQ_ID(_port_id) (_port_id)
  75 #define FCOE_BDQ_ID(_port_id) ((_port_id) + 2)
  76 #define QED_WID_SIZE            (1024)
  77 #define QED_PF_DEMS_SIZE        (4)
  78
  79 /* cau states */
  80 enum qed_coalescing_mode {
  81         QED_COAL_MODE_DISABLE,
  82         QED_COAL_MODE_ENABLE
  83 };
  84
  85 struct qed_eth_cb_ops;
  86 struct qed_dev_info;
  87 union qed_mcp_protocol_stats;
  88 enum qed_mcp_protocol_type;
  89
  90 /* helpers */
  91 #define QED_MFW_GET_FIELD(name, field) \
  92         (((name) & (field ## _MASK)) >> (field ## _SHIFT))
  93
  94 #define QED_MFW_SET_FIELD(name, field, value)                                  \
  95         do {                                                                   \
  96                 (name)  &= ~((field ## _MASK) << (field ## _SHIFT));           \
  97                 (name)  |= (((value) << (field ## _SHIFT)) & (field ## _MASK));\
  98         } while (0)
  99
 100 static inline u32 qed_db_addr(u32 cid, u32 DEMS)
 101 {
 102         u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
 103                       (cid * QED_PF_DEMS_SIZE);
 104
 105         return db_addr;
 106 }
 107
 108 static inline u32 qed_db_addr_vf(u32 cid, u32 DEMS)
 109 {
 110         u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
 111                       FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid);
 112
 113         return db_addr;
 114 }
 115
 116 #define ALIGNED_TYPE_SIZE(type_name, p_hwfn)                                 \
 117         ((sizeof(type_name) + (u32)(1 << (p_hwfn->cdev->cache_shift)) - 1) & \
 118          ~((1 << (p_hwfn->cdev->cache_shift)) - 1))
 119
 120 #define for_each_hwfn(cdev, i)  for (i = 0; i < cdev->num_hwfns; i++)
 121
 122 #define D_TRINE(val, cond1, cond2, true1, true2, def) \
 123         (val == (cond1) ? true1 :                     \
 124          (val == (cond2) ? true2 : def))
 125
 126 /* forward */
 127 struct qed_ptt_pool;
 128 struct qed_spq;
 129 struct qed_sb_info;
 130 struct qed_sb_attn_info;
 131 struct qed_cxt_mngr;
 132 struct qed_sb_sp_info;
 133 struct qed_ll2_info;
 134 struct qed_mcp_info;
 135
 136 struct qed_rt_data {
 137         u32     *init_val;
 138         bool    *b_valid;
 139 };
 140
 141 enum qed_tunn_mode {
 142         QED_MODE_L2GENEVE_TUNN,
 143         QED_MODE_IPGENEVE_TUNN,
 144         QED_MODE_L2GRE_TUNN,
 145         QED_MODE_IPGRE_TUNN,
 146         QED_MODE_VXLAN_TUNN,
 147 };
 148
 149 enum qed_tunn_clss {
 150         QED_TUNN_CLSS_MAC_VLAN,
 151         QED_TUNN_CLSS_MAC_VNI,
 152         QED_TUNN_CLSS_INNER_MAC_VLAN,
 153         QED_TUNN_CLSS_INNER_MAC_VNI,
 154         MAX_QED_TUNN_CLSS,
 155 };
 156
 157 struct qed_tunn_start_params {
 158         unsigned long   tunn_mode;
 159         u16             vxlan_udp_port;
 160         u16             geneve_udp_port;
 161         u8              update_vxlan_udp_port;
 162         u8              update_geneve_udp_port;
 163         u8              tunn_clss_vxlan;
 164         u8              tunn_clss_l2geneve;
 165         u8              tunn_clss_ipgeneve;
 166         u8              tunn_clss_l2gre;
 167         u8              tunn_clss_ipgre;
 168 };
 169
 170 struct qed_tunn_update_params {
 171         unsigned long   tunn_mode_update_mask;
 172         unsigned long   tunn_mode;
 173         u16             vxlan_udp_port;
 174         u16             geneve_udp_port;
 175         u8              update_rx_pf_clss;
 176         u8              update_tx_pf_clss;
 177         u8              update_vxlan_udp_port;
 178         u8              update_geneve_udp_port;
 179         u8              tunn_clss_vxlan;
 180         u8              tunn_clss_l2geneve;
 181         u8              tunn_clss_ipgeneve;
 182         u8              tunn_clss_l2gre;
 183         u8              tunn_clss_ipgre;
 184 };
 185
 186 /* The PCI personality is not quite synonymous to protocol ID:
 187  * 1. All personalities need CORE connections
 188  * 2. The Ethernet personality may support also the RoCE protocol
 189  */
 190 enum qed_pci_personality {
 191         QED_PCI_ETH,
 192         QED_PCI_FCOE,
 193         QED_PCI_ISCSI,
 194         QED_PCI_ETH_ROCE,
 195         QED_PCI_DEFAULT /* default in shmem */
 196 };
 197
 198 /* All VFs are symmetric, all counters are PF + all VFs */
 199 struct qed_qm_iids {
 200         u32 cids;
 201         u32 vf_cids;
 202         u32 tids;
 203 };
 204
 205 /* HW / FW resources, output of features supported below, most information
 206  * is received from MFW.
 207  */
 208 enum qed_resources {
 209         QED_SB,
 210         QED_L2_QUEUE,
 211         QED_VPORT,
 212         QED_RSS_ENG,
 213         QED_PQ,
 214         QED_RL,
 215         QED_MAC,
 216         QED_VLAN,
 217         QED_RDMA_CNQ_RAM,
 218         QED_ILT,
 219         QED_LL2_QUEUE,
 220         QED_CMDQS_CQS,
 221         QED_RDMA_STATS_QUEUE,
 222         QED_BDQ,
 223         QED_MAX_RESC,
 224 };
 225
 226 enum QED_FEATURE {
 227         QED_PF_L2_QUE,
 228         QED_VF,
 229         QED_RDMA_CNQ,
 230         QED_VF_L2_QUE,
 231         QED_FCOE_CQ,
 232         QED_MAX_FEATURES,
 233 };
 234
 235 enum QED_PORT_MODE {
 236         QED_PORT_MODE_DE_2X40G,
 237         QED_PORT_MODE_DE_2X50G,
 238         QED_PORT_MODE_DE_1X100G,
 239         QED_PORT_MODE_DE_4X10G_F,
 240         QED_PORT_MODE_DE_4X10G_E,
 241         QED_PORT_MODE_DE_4X20G,
 242         QED_PORT_MODE_DE_1X40G,
 243         QED_PORT_MODE_DE_2X25G,
 244         QED_PORT_MODE_DE_1X25G,
 245         QED_PORT_MODE_DE_4X25G,
 246         QED_PORT_MODE_DE_2X10G,
 247 };
 248
 249 enum qed_dev_cap {
 250         QED_DEV_CAP_ETH,
 251         QED_DEV_CAP_FCOE,
 252         QED_DEV_CAP_ISCSI,
 253         QED_DEV_CAP_ROCE,
 254 };
 255
 256 enum qed_wol_support {
 257         QED_WOL_SUPPORT_NONE,
 258         QED_WOL_SUPPORT_PME,
 259 };
 260
 261 struct qed_hw_info {
 262         /* PCI personality */
 263         enum qed_pci_personality        personality;
 264
 265         /* Resource Allocation scheme results */
 266         u32                             resc_start[QED_MAX_RESC];
 267         u32                             resc_num[QED_MAX_RESC];
 268         u32                             feat_num[QED_MAX_FEATURES];
 269
 270 #define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc])
 271 #define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc])
 272 #define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \
 273                                  RESC_NUM(_p_hwfn, resc))
 274 #define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc])
 275
 276         u8                              num_tc;
 277         u8                              offload_tc;
 278         u8                              non_offload_tc;
 279
 280         u32                             concrete_fid;
 281         u16                             opaque_fid;
 282         u16                             ovlan;
 283         u32                             part_num[4];
 284
 285         unsigned char                   hw_mac_addr[ETH_ALEN];
 286         u64                             node_wwn;
 287         u64                             port_wwn;
 288
 289         u16                             num_fcoe_conns;
 290
 291         struct qed_igu_info             *p_igu_info;
 292
 293         u32                             port_mode;
 294         u32                             hw_mode;
 295         unsigned long           device_capabilities;
 296         u16                             mtu;
 297
 298         enum qed_wol_support b_wol_support;
 299 };
 300
 301 /* maximun size of read/write commands (HW limit) */
 302 #define DMAE_MAX_RW_SIZE        0x2000
 303
 304 struct qed_dmae_info {
 305         /* Mutex for synchronizing access to functions */
 306         struct mutex    mutex;
 307
 308         u8              channel;
 309
 310         dma_addr_t      completion_word_phys_addr;
 311
 312         /* The memory location where the DMAE writes the completion
 313          * value when an operation is finished on this context.
 314          */
 315         u32             *p_completion_word;
 316
 317         dma_addr_t      intermediate_buffer_phys_addr;
 318
 319         /* An intermediate buffer for DMAE operations that use virtual
 320          * addresses - data is DMA'd to/from this buffer and then
 321          * memcpy'd to/from the virtual address
 322          */
 323         u32             *p_intermediate_buffer;
 324
 325         dma_addr_t      dmae_cmd_phys_addr;
 326         struct dmae_cmd *p_dmae_cmd;
 327 };
 328
 329 struct qed_wfq_data {
 330         /* when feature is configured for at least 1 vport */
 331         u32     min_speed;
 332         bool    configured;
 333 };
 334
 335 struct qed_qm_info {
 336         struct init_qm_pq_params        *qm_pq_params;
 337         struct init_qm_vport_params     *qm_vport_params;
 338         struct init_qm_port_params      *qm_port_params;
 339         u16                             start_pq;
 340         u8                              start_vport;
 341         u8                              pure_lb_pq;
 342         u8                              offload_pq;
 343         u8                              pure_ack_pq;
 344         u8 ooo_pq;
 345         u8                              vf_queues_offset;
 346         u16                             num_pqs;
 347         u16                             num_vf_pqs;
 348         u8                              num_vports;
 349         u8                              max_phys_tcs_per_port;
 350         bool                            pf_rl_en;
 351         bool                            pf_wfq_en;
 352         bool                            vport_rl_en;
 353         bool                            vport_wfq_en;
 354         u8                              pf_wfq;
 355         u32                             pf_rl;
 356         struct qed_wfq_data             *wfq_data;
 357         u8 num_pf_rls;
 358 };
 359
 360 struct storm_stats {
 361         u32     address;
 362         u32     len;
 363 };
 364
 365 struct qed_storm_stats {
 366         struct storm_stats mstats;
 367         struct storm_stats pstats;
 368         struct storm_stats tstats;
 369         struct storm_stats ustats;
 370 };
 371
 372 struct qed_fw_data {
 373         struct fw_ver_info      *fw_ver_info;
 374         const u8                *modes_tree_buf;
 375         union init_op           *init_ops;
 376         const u32               *arr_data;
 377         u32                     init_ops_size;
 378 };
 379
 380 #define DRV_MODULE_VERSION                    \
 381         __stringify(QED_MAJOR_VERSION) "."    \
 382         __stringify(QED_MINOR_VERSION) "."    \
 383         __stringify(QED_REVISION_VERSION) "." \
 384         __stringify(QED_ENGINEERING_VERSION)
 385
 386 struct qed_simd_fp_handler {
 387         void    *token;
 388         void    (*func)(void *);
 389 };
 390
 391 struct qed_hwfn {
 392         struct qed_dev                  *cdev;
 393         u8                              my_id;          /* ID inside the PF */
 394 #define IS_LEAD_HWFN(edev)              (!((edev)->my_id))
 395         u8                              rel_pf_id;      /* Relative to engine*/
 396         u8                              abs_pf_id;
 397 #define QED_PATH_ID(_p_hwfn) \
 398         (QED_IS_K2((_p_hwfn)->cdev) ? 0 : ((_p_hwfn)->abs_pf_id & 1))
 399         u8                              port_id;
 400         bool                            b_active;
 401
 402         u32                             dp_module;
 403         u8                              dp_level;
 404         char                            name[NAME_SIZE];
 405
 406         bool                            first_on_engine;
 407         bool                            hw_init_done;
 408
 409         u8                              num_funcs_on_engine;
 410         u8 enabled_func_idx;
 411
 412         /* BAR access */
 413         void __iomem                    *regview;
 414         void __iomem                    *doorbells;
 415         u64                             db_phys_addr;
 416         unsigned long                   db_size;
 417
 418         /* PTT pool */
 419         struct qed_ptt_pool             *p_ptt_pool;
 420
 421         /* HW info */
 422         struct qed_hw_info              hw_info;
 423
 424         /* rt_array (for init-tool) */
 425         struct qed_rt_data              rt_data;
 426
 427         /* SPQ */
 428         struct qed_spq                  *p_spq;
 429
 430         /* EQ */
 431         struct qed_eq                   *p_eq;
 432
 433         /* Consolidate Q*/
 434         struct qed_consq                *p_consq;
 435
 436         /* Slow-Path definitions */
 437         struct tasklet_struct           *sp_dpc;
 438         bool                            b_sp_dpc_enabled;
 439
 440         struct qed_ptt                  *p_main_ptt;
 441         struct qed_ptt                  *p_dpc_ptt;
 442
 443         struct qed_sb_sp_info           *p_sp_sb;
 444         struct qed_sb_attn_info         *p_sb_attn;
 445
 446         /* Protocol related */
 447         bool                            using_ll2;
 448         struct qed_ll2_info             *p_ll2_info;
 449         struct qed_ooo_info             *p_ooo_info;
 450         struct qed_rdma_info            *p_rdma_info;
 451         struct qed_iscsi_info           *p_iscsi_info;
 452         struct qed_fcoe_info            *p_fcoe_info;
 453         struct qed_pf_params            pf_params;
 454
 455         bool b_rdma_enabled_in_prs;
 456         u32 rdma_prs_search_reg;
 457
 458         /* Array of sb_info of all status blocks */
 459         struct qed_sb_info              *sbs_info[MAX_SB_PER_PF_MIMD];
 460         u16                             num_sbs;
 461
 462         struct qed_cxt_mngr             *p_cxt_mngr;
 463
 464         /* Flag indicating whether interrupts are enabled or not*/
 465         bool                            b_int_enabled;
 466         bool                            b_int_requested;
 467
 468         /* True if the driver requests for the link */
 469         bool                            b_drv_link_init;
 470
 471         struct qed_vf_iov               *vf_iov_info;
 472         struct qed_pf_iov               *pf_iov_info;
 473         struct qed_mcp_info             *mcp_info;
 474
 475         struct qed_dcbx_info            *p_dcbx_info;
 476
 477         struct qed_dmae_info            dmae_info;
 478
 479         /* QM init */
 480         struct qed_qm_info              qm_info;
 481         struct qed_storm_stats          storm_stats;
 482
 483         /* Buffer for unzipping firmware data */
 484         void                            *unzip_buf;
 485
 486         struct dbg_tools_data           dbg_info;
 487
 488         /* PWM region specific data */
 489         u32                             dpi_size;
 490         u32                             dpi_count;
 491
 492         /* This is used to calculate the doorbell address */
 493         u32 dpi_start_offset;
 494
 495         /* If one of the following is set then EDPM shouldn't be used */
 496         u8 dcbx_no_edpm;
 497         u8 db_bar_no_edpm;
 498
 499         /* p_ptp_ptt is valid for leading HWFN only */
 500         struct qed_ptt *p_ptp_ptt;
 501         struct qed_simd_fp_handler      simd_proto_handler[64];
 502
 503 #ifdef CONFIG_QED_SRIOV
 504         struct workqueue_struct *iov_wq;
 505         struct delayed_work iov_task;
 506         unsigned long iov_task_flags;
 507 #endif
 508
 509         struct z_stream_s               *stream;
 510         struct qed_roce_ll2_info        *ll2;
 511 };
 512
 513 struct pci_params {
 514         int             pm_cap;
 515
 516         unsigned long   mem_start;
 517         unsigned long   mem_end;
 518         unsigned int    irq;
 519         u8              pf_num;
 520 };
 521
 522 struct qed_int_param {
 523         u32     int_mode;
 524         u8      num_vectors;
 525         u8      min_msix_cnt; /* for minimal functionality */
 526 };
 527
 528 struct qed_int_params {
 529         struct qed_int_param    in;
 530         struct qed_int_param    out;
 531         struct msix_entry       *msix_table;
 532         bool                    fp_initialized;
 533         u8                      fp_msix_base;
 534         u8                      fp_msix_cnt;
 535         u8                      rdma_msix_base;
 536         u8                      rdma_msix_cnt;
 537 };
 538
 539 struct qed_dbg_feature {
 540         struct dentry *dentry;
 541         u8 *dump_buf;
 542         u32 buf_size;
 543         u32 dumped_dwords;
 544 };
 545
 546 struct qed_dbg_params {
 547         struct qed_dbg_feature features[DBG_FEATURE_NUM];
 548         u8 engine_for_debug;
 549         bool print_data;
 550 };
 551
 552 struct qed_dev {
 553         u32     dp_module;
 554         u8      dp_level;
 555         char    name[NAME_SIZE];
 556
 557         enum    qed_dev_type type;
 558 /* Translate type/revision combo into the proper conditions */
 559 #define QED_IS_BB(dev)  ((dev)->type == QED_DEV_TYPE_BB)
 560 #define QED_IS_BB_A0(dev)       (QED_IS_BB(dev) && \
 561                                  CHIP_REV_IS_A0(dev))
 562 #define QED_IS_BB_B0(dev)       (QED_IS_BB(dev) && \
 563                                  CHIP_REV_IS_B0(dev))
 564 #define QED_IS_AH(dev)  ((dev)->type == QED_DEV_TYPE_AH)
 565 #define QED_IS_K2(dev)  QED_IS_AH(dev)
 566
 567 #define QED_GET_TYPE(dev)       (QED_IS_BB_A0(dev) ? CHIP_BB_A0 : \
 568                                  QED_IS_BB_B0(dev) ? CHIP_BB_B0 : CHIP_K2)
 569
 570         u16     vendor_id;
 571         u16     device_id;
 572 #define QED_DEV_ID_MASK         0xff00
 573 #define QED_DEV_ID_MASK_BB      0x1600
 574 #define QED_DEV_ID_MASK_AH      0x8000
 575
 576         u16     chip_num;
 577 #define CHIP_NUM_MASK                   0xffff
 578 #define CHIP_NUM_SHIFT                  16
 579
 580         u16     chip_rev;
 581 #define CHIP_REV_MASK                   0xf
 582 #define CHIP_REV_SHIFT                  12
 583 #define CHIP_REV_IS_A0(_cdev)   (!(_cdev)->chip_rev)
 584 #define CHIP_REV_IS_B0(_cdev)   ((_cdev)->chip_rev == 1)
 585
 586         u16                             chip_metal;
 587 #define CHIP_METAL_MASK                 0xff
 588 #define CHIP_METAL_SHIFT                4
 589
 590         u16                             chip_bond_id;
 591 #define CHIP_BOND_ID_MASK               0xf
 592 #define CHIP_BOND_ID_SHIFT              0
 593
 594         u8                              num_engines;
 595         u8                              num_ports_in_engines;
 596         u8                              num_funcs_in_port;
 597
 598         u8                              path_id;
 599         enum qed_mf_mode                mf_mode;
 600 #define IS_MF_DEFAULT(_p_hwfn)  (((_p_hwfn)->cdev)->mf_mode == QED_MF_DEFAULT)
 601 #define IS_MF_SI(_p_hwfn)       (((_p_hwfn)->cdev)->mf_mode == QED_MF_NPAR)
 602 #define IS_MF_SD(_p_hwfn)       (((_p_hwfn)->cdev)->mf_mode == QED_MF_OVLAN)
 603
 604         int                             pcie_width;
 605         int                             pcie_speed;
 606         u8                              ver_str[VER_SIZE];
 607
 608         /* Add MF related configuration */
 609         u8                              mcp_rev;
 610         u8                              boot_mode;
 611
 612         /* WoL related configurations */
 613         u8 wol_config;
 614         u8 wol_mac[ETH_ALEN];
 615
 616         u32                             int_mode;
 617         enum qed_coalescing_mode        int_coalescing_mode;
 618         u16                             rx_coalesce_usecs;
 619         u16                             tx_coalesce_usecs;
 620
 621         /* Start Bar offset of first hwfn */
 622         void __iomem                    *regview;
 623         void __iomem                    *doorbells;
 624         u64                             db_phys_addr;
 625         unsigned long                   db_size;
 626
 627         /* PCI */
 628         u8                              cache_shift;
 629
 630         /* Init */
 631         const struct iro                *iro_arr;
 632 #define IRO (p_hwfn->cdev->iro_arr)
 633
 634         /* HW functions */
 635         u8                              num_hwfns;
 636         struct qed_hwfn                 hwfns[MAX_HWFNS_PER_DEVICE];
 637
 638         /* SRIOV */
 639         struct qed_hw_sriov_info *p_iov_info;
 640 #define IS_QED_SRIOV(cdev)              (!!(cdev)->p_iov_info)
 641
 642         unsigned long                   tunn_mode;
 643
 644         bool                            b_is_vf;
 645         u32                             drv_type;
 646         struct qed_eth_stats            *reset_stats;
 647         struct qed_fw_data              *fw_data;
 648
 649         u32                             mcp_nvm_resp;
 650
 651         /* Linux specific here */
 652         struct  qede_dev                *edev;
 653         struct  pci_dev                 *pdev;
 654         u32 flags;
 655 #define QED_FLAG_STORAGE_STARTED        (BIT(0))
 656         int                             msg_enable;
 657
 658         struct pci_params               pci_params;
 659
 660         struct qed_int_params           int_params;
 661
 662         u8                              protocol;
 663 #define IS_QED_ETH_IF(cdev)     ((cdev)->protocol == QED_PROTOCOL_ETH)
 664 #define IS_QED_FCOE_IF(cdev)    ((cdev)->protocol == QED_PROTOCOL_FCOE)
 665
 666         /* Callbacks to protocol driver */
 667         union {
 668                 struct qed_common_cb_ops        *common;
 669                 struct qed_eth_cb_ops           *eth;
 670                 struct qed_fcoe_cb_ops          *fcoe;
 671                 struct qed_iscsi_cb_ops         *iscsi;
 672         } protocol_ops;
 673         void                            *ops_cookie;
 674
 675         struct qed_dbg_params           dbg_params;
 676
 677 #ifdef CONFIG_QED_LL2
 678         struct qed_cb_ll2_info          *ll2;
 679         u8                              ll2_mac_address[ETH_ALEN];
 680 #endif
 681         DECLARE_HASHTABLE(connections, 10);
 682         const struct firmware           *firmware;
 683
 684         u32 rdma_max_sge;
 685         u32 rdma_max_inline;
 686         u32 rdma_max_srq_sge;
 687 };
 688
 689 #define NUM_OF_VFS(dev)         (QED_IS_BB(dev) ? MAX_NUM_VFS_BB \
 690                                                 : MAX_NUM_VFS_K2)
 691 #define NUM_OF_L2_QUEUES(dev)   (QED_IS_BB(dev) ? MAX_NUM_L2_QUEUES_BB \
 692                                                 : MAX_NUM_L2_QUEUES_K2)
 693 #define NUM_OF_PORTS(dev)       (QED_IS_BB(dev) ? MAX_NUM_PORTS_BB \
 694                                                 : MAX_NUM_PORTS_K2)
 695 #define NUM_OF_SBS(dev)         (QED_IS_BB(dev) ? MAX_SB_PER_PATH_BB \
 696                                                 : MAX_SB_PER_PATH_K2)
 697 #define NUM_OF_ENG_PFS(dev)     (QED_IS_BB(dev) ? MAX_NUM_PFS_BB \
 698                                                 : MAX_NUM_PFS_K2)
 699
 700 /**
 701  * @brief qed_concrete_to_sw_fid - get the sw function id from
 702  *        the concrete value.
 703  *
 704  * @param concrete_fid
 705  *
 706  * @return inline u8
 707  */
 708 static inline u8 qed_concrete_to_sw_fid(struct qed_dev *cdev,
 709                                         u32 concrete_fid)
 710 {
 711         u8 vfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID);
 712         u8 pfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID);
 713         u8 vf_valid = GET_FIELD(concrete_fid,
 714                                 PXP_CONCRETE_FID_VFVALID);
 715         u8 sw_fid;
 716
 717         if (vf_valid)
 718                 sw_fid = vfid + MAX_NUM_PFS;
 719         else
 720                 sw_fid = pfid;
 721
 722         return sw_fid;
 723 }
 724
 725 #define PURE_LB_TC 8
 726 #define OOO_LB_TC 9
 727
 728 int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate);
 729 void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev,
 730                                          struct qed_ptt *p_ptt,
 731                                          u32 min_pf_rate);
 732
 733 void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt);
 734 #define QED_LEADING_HWFN(dev)   (&dev->hwfns[0])
 735 int qed_device_num_engines(struct qed_dev *cdev);
 736
 737 /* Other Linux specific common definitions */
 738 #define DP_NAME(cdev) ((cdev)->name)
 739
 740 #define REG_ADDR(cdev, offset)          (void __iomem *)((u8 __iomem *)\
 741                                                 (cdev->regview) + \
 742                                                          (offset))
 743
 744 #define REG_RD(cdev, offset)            readl(REG_ADDR(cdev, offset))
 745 #define REG_WR(cdev, offset, val)       writel((u32)val, REG_ADDR(cdev, offset))
 746 #define REG_WR16(cdev, offset, val)     writew((u16)val, REG_ADDR(cdev, offset))
 747
 748 #define DOORBELL(cdev, db_addr, val)                     \
 749         writel((u32)val, (void __iomem *)((u8 __iomem *)\
 750                                           (cdev->doorbells) + (db_addr)))
 751
 752 /* Prototypes */
 753 int qed_fill_dev_info(struct qed_dev *cdev,
 754                       struct qed_dev_info *dev_info);
 755 void qed_link_update(struct qed_hwfn *hwfn);
 756 u32 qed_unzip_data(struct qed_hwfn *p_hwfn,
 757                    u32 input_len, u8 *input_buf,
 758                    u32 max_size, u8 *unzip_buf);
 759 void qed_get_protocol_stats(struct qed_dev *cdev,
 760                             enum qed_mcp_protocol_type type,
 761                             union qed_mcp_protocol_stats *stats);
 762 int qed_slowpath_irq_req(struct qed_hwfn *hwfn);
 763 void qed_slowpath_irq_sync(struct qed_hwfn *p_hwfn);
 764
 765 #endif /* _QED_H */