drivers/net/ethernet/qlogic/qed/qed.h

   1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
   2 /* QLogic qed NIC Driver
   3  * Copyright (c) 2015-2017  QLogic Corporation
   4  * Copyright (c) 2019-2020 Marvell International Ltd.
   5  */
   6
   7 #ifndef _QED_H
   8 #define _QED_H
   9
  10 #include <linux/types.h>
  11 #include <linux/io.h>
  12 #include <linux/delay.h>
  13 #include <linux/firmware.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/list.h>
  16 #include <linux/mutex.h>
  17 #include <linux/pci.h>
  18 #include <linux/slab.h>
  19 #include <linux/string.h>
  20 #include <linux/workqueue.h>
  21 #include <linux/zlib.h>
  22 #include <linux/hashtable.h>
  23 #include <linux/qed/qed_if.h>
  24 #include "qed_debug.h"
  25 #include "qed_hsi.h"
  26
  27 extern const struct qed_common_ops qed_common_ops_pass;
  28
  29 #define QED_MAJOR_VERSION               8
  30 #define QED_MINOR_VERSION               37
  31 #define QED_REVISION_VERSION            0
  32 #define QED_ENGINEERING_VERSION         20
  33
  34 #define QED_VERSION                                              \
  35         ((QED_MAJOR_VERSION << 24) | (QED_MINOR_VERSION << 16) | \
  36          (QED_REVISION_VERSION << 8) | QED_ENGINEERING_VERSION)
  37
  38 #define STORM_FW_VERSION                                       \
  39         ((FW_MAJOR_VERSION << 24) | (FW_MINOR_VERSION << 16) | \
  40          (FW_REVISION_VERSION << 8) | FW_ENGINEERING_VERSION)
  41
  42 #define MAX_HWFNS_PER_DEVICE    (4)
  43 #define NAME_SIZE 16
  44 #define VER_SIZE 16
  45
  46 #define QED_WFQ_UNIT    100
  47
  48 #define QED_WID_SIZE            (1024)
  49 #define QED_MIN_WIDS            (4)
  50 #define QED_PF_DEMS_SIZE        (4)
  51
  52 /* cau states */
  53 enum qed_coalescing_mode {
  54         QED_COAL_MODE_DISABLE,
  55         QED_COAL_MODE_ENABLE
  56 };
  57
  58 enum qed_nvm_cmd {
  59         QED_PUT_FILE_BEGIN = DRV_MSG_CODE_NVM_PUT_FILE_BEGIN,
  60         QED_PUT_FILE_DATA = DRV_MSG_CODE_NVM_PUT_FILE_DATA,
  61         QED_NVM_WRITE_NVRAM = DRV_MSG_CODE_NVM_WRITE_NVRAM,
  62         QED_GET_MCP_NVM_RESP = 0xFFFFFF00
  63 };
  64
  65 struct qed_eth_cb_ops;
  66 struct qed_dev_info;
  67 union qed_mcp_protocol_stats;
  68 enum qed_mcp_protocol_type;
  69 enum qed_mfw_tlv_type;
  70 union qed_mfw_tlv_data;
  71
  72 /* helpers */
  73 #define QED_MFW_GET_FIELD(name, field) \
  74         (((name) & (field ## _MASK)) >> (field ## _SHIFT))
  75
  76 #define QED_MFW_SET_FIELD(name, field, value)                                  \
  77         do {                                                                   \
  78                 (name)  &= ~(field ## _MASK);          \
  79                 (name)  |= (((value) << (field ## _SHIFT)) & (field ## _MASK));\
  80         } while (0)
  81
  82 static inline u32 qed_db_addr(u32 cid, u32 DEMS)
  83 {
  84         u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
  85                       (cid * QED_PF_DEMS_SIZE);
  86
  87         return db_addr;
  88 }
  89
  90 static inline u32 qed_db_addr_vf(u32 cid, u32 DEMS)
  91 {
  92         u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
  93                       FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid);
  94
  95         return db_addr;
  96 }
  97
  98 #define ALIGNED_TYPE_SIZE(type_name, p_hwfn)                                 \
  99         ((sizeof(type_name) + (u32)(1 << (p_hwfn->cdev->cache_shift)) - 1) & \
 100          ~((1 << (p_hwfn->cdev->cache_shift)) - 1))
 101
 102 #define for_each_hwfn(cdev, i)  for (i = 0; i < cdev->num_hwfns; i++)
 103
 104 #define D_TRINE(val, cond1, cond2, true1, true2, def) \
 105         (val == (cond1) ? true1 :                     \
 106          (val == (cond2) ? true2 : def))
 107
 108 /* forward */
 109 struct qed_ptt_pool;
 110 struct qed_spq;
 111 struct qed_sb_info;
 112 struct qed_sb_attn_info;
 113 struct qed_cxt_mngr;
 114 struct qed_sb_sp_info;
 115 struct qed_ll2_info;
 116 struct qed_mcp_info;
 117 struct qed_llh_info;
 118
 119 struct qed_rt_data {
 120         u32     *init_val;
 121         bool    *b_valid;
 122 };
 123
 124 enum qed_tunn_mode {
 125         QED_MODE_L2GENEVE_TUNN,
 126         QED_MODE_IPGENEVE_TUNN,
 127         QED_MODE_L2GRE_TUNN,
 128         QED_MODE_IPGRE_TUNN,
 129         QED_MODE_VXLAN_TUNN,
 130 };
 131
 132 enum qed_tunn_clss {
 133         QED_TUNN_CLSS_MAC_VLAN,
 134         QED_TUNN_CLSS_MAC_VNI,
 135         QED_TUNN_CLSS_INNER_MAC_VLAN,
 136         QED_TUNN_CLSS_INNER_MAC_VNI,
 137         QED_TUNN_CLSS_MAC_VLAN_DUAL_STAGE,
 138         MAX_QED_TUNN_CLSS,
 139 };
 140
 141 struct qed_tunn_update_type {
 142         bool b_update_mode;
 143         bool b_mode_enabled;
 144         enum qed_tunn_clss tun_cls;
 145 };
 146
 147 struct qed_tunn_update_udp_port {
 148         bool b_update_port;
 149         u16 port;
 150 };
 151
 152 struct qed_tunnel_info {
 153         struct qed_tunn_update_type vxlan;
 154         struct qed_tunn_update_type l2_geneve;
 155         struct qed_tunn_update_type ip_geneve;
 156         struct qed_tunn_update_type l2_gre;
 157         struct qed_tunn_update_type ip_gre;
 158
 159         struct qed_tunn_update_udp_port vxlan_port;
 160         struct qed_tunn_update_udp_port geneve_port;
 161
 162         bool b_update_rx_cls;
 163         bool b_update_tx_cls;
 164 };
 165
 166 struct qed_tunn_start_params {
 167         unsigned long   tunn_mode;
 168         u16             vxlan_udp_port;
 169         u16             geneve_udp_port;
 170         u8              update_vxlan_udp_port;
 171         u8              update_geneve_udp_port;
 172         u8              tunn_clss_vxlan;
 173         u8              tunn_clss_l2geneve;
 174         u8              tunn_clss_ipgeneve;
 175         u8              tunn_clss_l2gre;
 176         u8              tunn_clss_ipgre;
 177 };
 178
 179 struct qed_tunn_update_params {
 180         unsigned long   tunn_mode_update_mask;
 181         unsigned long   tunn_mode;
 182         u16             vxlan_udp_port;
 183         u16             geneve_udp_port;
 184         u8              update_rx_pf_clss;
 185         u8              update_tx_pf_clss;
 186         u8              update_vxlan_udp_port;
 187         u8              update_geneve_udp_port;
 188         u8              tunn_clss_vxlan;
 189         u8              tunn_clss_l2geneve;
 190         u8              tunn_clss_ipgeneve;
 191         u8              tunn_clss_l2gre;
 192         u8              tunn_clss_ipgre;
 193 };
 194
 195 /* The PCI personality is not quite synonymous to protocol ID:
 196  * 1. All personalities need CORE connections
 197  * 2. The Ethernet personality may support also the RoCE/iWARP protocol
 198  */
 199 enum qed_pci_personality {
 200         QED_PCI_ETH,
 201         QED_PCI_FCOE,
 202         QED_PCI_ISCSI,
 203         QED_PCI_ETH_ROCE,
 204         QED_PCI_ETH_IWARP,
 205         QED_PCI_ETH_RDMA,
 206         QED_PCI_DEFAULT, /* default in shmem */
 207 };
 208
 209 /* All VFs are symmetric, all counters are PF + all VFs */
 210 struct qed_qm_iids {
 211         u32 cids;
 212         u32 vf_cids;
 213         u32 tids;
 214 };
 215
 216 /* HW / FW resources, output of features supported below, most information
 217  * is received from MFW.
 218  */
 219 enum qed_resources {
 220         QED_SB,
 221         QED_L2_QUEUE,
 222         QED_VPORT,
 223         QED_RSS_ENG,
 224         QED_PQ,
 225         QED_RL,
 226         QED_MAC,
 227         QED_VLAN,
 228         QED_RDMA_CNQ_RAM,
 229         QED_ILT,
 230         QED_LL2_RAM_QUEUE,
 231         QED_LL2_CTX_QUEUE,
 232         QED_CMDQS_CQS,
 233         QED_RDMA_STATS_QUEUE,
 234         QED_BDQ,
 235         QED_MAX_RESC,
 236 };
 237
 238 enum QED_FEATURE {
 239         QED_PF_L2_QUE,
 240         QED_VF,
 241         QED_RDMA_CNQ,
 242         QED_ISCSI_CQ,
 243         QED_FCOE_CQ,
 244         QED_VF_L2_QUE,
 245         QED_MAX_FEATURES,
 246 };
 247
 248 enum QED_PORT_MODE {
 249         QED_PORT_MODE_DE_2X40G,
 250         QED_PORT_MODE_DE_2X50G,
 251         QED_PORT_MODE_DE_1X100G,
 252         QED_PORT_MODE_DE_4X10G_F,
 253         QED_PORT_MODE_DE_4X10G_E,
 254         QED_PORT_MODE_DE_4X20G,
 255         QED_PORT_MODE_DE_1X40G,
 256         QED_PORT_MODE_DE_2X25G,
 257         QED_PORT_MODE_DE_1X25G,
 258         QED_PORT_MODE_DE_4X25G,
 259         QED_PORT_MODE_DE_2X10G,
 260 };
 261
 262 enum qed_dev_cap {
 263         QED_DEV_CAP_ETH,
 264         QED_DEV_CAP_FCOE,
 265         QED_DEV_CAP_ISCSI,
 266         QED_DEV_CAP_ROCE,
 267         QED_DEV_CAP_IWARP,
 268 };
 269
 270 enum qed_wol_support {
 271         QED_WOL_SUPPORT_NONE,
 272         QED_WOL_SUPPORT_PME,
 273 };
 274
 275 enum qed_db_rec_exec {
 276         DB_REC_DRY_RUN,
 277         DB_REC_REAL_DEAL,
 278         DB_REC_ONCE,
 279 };
 280
 281 struct qed_hw_info {
 282         /* PCI personality */
 283         enum qed_pci_personality personality;
 284 #define QED_IS_RDMA_PERSONALITY(dev)                        \
 285         ((dev)->hw_info.personality == QED_PCI_ETH_ROCE ||  \
 286          (dev)->hw_info.personality == QED_PCI_ETH_IWARP || \
 287          (dev)->hw_info.personality == QED_PCI_ETH_RDMA)
 288 #define QED_IS_ROCE_PERSONALITY(dev)                       \
 289         ((dev)->hw_info.personality == QED_PCI_ETH_ROCE || \
 290          (dev)->hw_info.personality == QED_PCI_ETH_RDMA)
 291 #define QED_IS_IWARP_PERSONALITY(dev)                       \
 292         ((dev)->hw_info.personality == QED_PCI_ETH_IWARP || \
 293          (dev)->hw_info.personality == QED_PCI_ETH_RDMA)
 294 #define QED_IS_L2_PERSONALITY(dev)                    \
 295         ((dev)->hw_info.personality == QED_PCI_ETH || \
 296          QED_IS_RDMA_PERSONALITY(dev))
 297 #define QED_IS_FCOE_PERSONALITY(dev) \
 298         ((dev)->hw_info.personality == QED_PCI_FCOE)
 299 #define QED_IS_ISCSI_PERSONALITY(dev) \
 300         ((dev)->hw_info.personality == QED_PCI_ISCSI)
 301
 302         /* Resource Allocation scheme results */
 303         u32                             resc_start[QED_MAX_RESC];
 304         u32                             resc_num[QED_MAX_RESC];
 305         u32                             feat_num[QED_MAX_FEATURES];
 306
 307 #define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc])
 308 #define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc])
 309 #define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \
 310                                  RESC_NUM(_p_hwfn, resc))
 311 #define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc])
 312
 313         /* Amount of traffic classes HW supports */
 314         u8 num_hw_tc;
 315
 316         /* Amount of TCs which should be active according to DCBx or upper
 317          * layer driver configuration.
 318          */
 319         u8 num_active_tc;
 320         u8                              offload_tc;
 321         bool                            offload_tc_set;
 322
 323         bool                            multi_tc_roce_en;
 324 #define IS_QED_MULTI_TC_ROCE(p_hwfn) (((p_hwfn)->hw_info.multi_tc_roce_en))
 325
 326         u32                             concrete_fid;
 327         u16                             opaque_fid;
 328         u16                             ovlan;
 329         u32                             part_num[4];
 330
 331         unsigned char                   hw_mac_addr[ETH_ALEN];
 332         u64                             node_wwn;
 333         u64                             port_wwn;
 334
 335         u16                             num_fcoe_conns;
 336
 337         struct qed_igu_info             *p_igu_info;
 338
 339         u32                             port_mode;
 340         u32                             hw_mode;
 341         unsigned long           device_capabilities;
 342         u16                             mtu;
 343
 344         enum qed_wol_support b_wol_support;
 345 };
 346
 347 /* maximun size of read/write commands (HW limit) */
 348 #define DMAE_MAX_RW_SIZE        0x2000
 349
 350 struct qed_dmae_info {
 351         /* Mutex for synchronizing access to functions */
 352         struct mutex    mutex;
 353
 354         u8              channel;
 355
 356         dma_addr_t      completion_word_phys_addr;
 357
 358         /* The memory location where the DMAE writes the completion
 359          * value when an operation is finished on this context.
 360          */
 361         u32             *p_completion_word;
 362
 363         dma_addr_t      intermediate_buffer_phys_addr;
 364
 365         /* An intermediate buffer for DMAE operations that use virtual
 366          * addresses - data is DMA'd to/from this buffer and then
 367          * memcpy'd to/from the virtual address
 368          */
 369         u32             *p_intermediate_buffer;
 370
 371         dma_addr_t      dmae_cmd_phys_addr;
 372         struct dmae_cmd *p_dmae_cmd;
 373 };
 374
 375 struct qed_wfq_data {
 376         /* when feature is configured for at least 1 vport */
 377         u32     min_speed;
 378         bool    configured;
 379 };
 380
 381 struct qed_qm_info {
 382         struct init_qm_pq_params        *qm_pq_params;
 383         struct init_qm_vport_params     *qm_vport_params;
 384         struct init_qm_port_params      *qm_port_params;
 385         u16                             start_pq;
 386         u8                              start_vport;
 387         u16                              pure_lb_pq;
 388         u16                             first_ofld_pq;
 389         u16                             first_llt_pq;
 390         u16                             pure_ack_pq;
 391         u16                             ooo_pq;
 392         u16                             first_vf_pq;
 393         u16                             first_mcos_pq;
 394         u16                             first_rl_pq;
 395         u16                             num_pqs;
 396         u16                             num_vf_pqs;
 397         u8                              num_vports;
 398         u8                              max_phys_tcs_per_port;
 399         u8                              ooo_tc;
 400         bool                            pf_rl_en;
 401         bool                            pf_wfq_en;
 402         bool                            vport_rl_en;
 403         bool                            vport_wfq_en;
 404         u8                              pf_wfq;
 405         u32                             pf_rl;
 406         struct qed_wfq_data             *wfq_data;
 407         u8 num_pf_rls;
 408 };
 409
 410 #define QED_OVERFLOW_BIT        1
 411
 412 struct qed_db_recovery_info {
 413         struct list_head list;
 414
 415         /* Lock to protect the doorbell recovery mechanism list */
 416         spinlock_t lock;
 417         bool dorq_attn;
 418         u32 db_recovery_counter;
 419         unsigned long overflow;
 420 };
 421
 422 struct storm_stats {
 423         u32     address;
 424         u32     len;
 425 };
 426
 427 struct qed_storm_stats {
 428         struct storm_stats mstats;
 429         struct storm_stats pstats;
 430         struct storm_stats tstats;
 431         struct storm_stats ustats;
 432 };
 433
 434 struct qed_fw_data {
 435         struct fw_ver_info      *fw_ver_info;
 436         const u8                *modes_tree_buf;
 437         union init_op           *init_ops;
 438         const u32               *arr_data;
 439         const u32               *fw_overlays;
 440         u32                     fw_overlays_len;
 441         u32                     init_ops_size;
 442 };
 443
 444 enum qed_mf_mode_bit {
 445         /* Supports PF-classification based on tag */
 446         QED_MF_OVLAN_CLSS,
 447
 448         /* Supports PF-classification based on MAC */
 449         QED_MF_LLH_MAC_CLSS,
 450
 451         /* Supports PF-classification based on protocol type */
 452         QED_MF_LLH_PROTO_CLSS,
 453
 454         /* Requires a default PF to be set */
 455         QED_MF_NEED_DEF_PF,
 456
 457         /* Allow LL2 to multicast/broadcast */
 458         QED_MF_LL2_NON_UNICAST,
 459
 460         /* Allow Cross-PF [& child VFs] Tx-switching */
 461         QED_MF_INTER_PF_SWITCH,
 462
 463         /* Unified Fabtic Port support enabled */
 464         QED_MF_UFP_SPECIFIC,
 465
 466         /* Disable Accelerated Receive Flow Steering (aRFS) */
 467         QED_MF_DISABLE_ARFS,
 468
 469         /* Use vlan for steering */
 470         QED_MF_8021Q_TAGGING,
 471
 472         /* Use stag for steering */
 473         QED_MF_8021AD_TAGGING,
 474
 475         /* Allow DSCP to TC mapping */
 476         QED_MF_DSCP_TO_TC_MAP,
 477
 478         /* Do not insert a vlan tag with id 0 */
 479         QED_MF_DONT_ADD_VLAN0_TAG,
 480 };
 481
 482 enum qed_ufp_mode {
 483         QED_UFP_MODE_ETS,
 484         QED_UFP_MODE_VNIC_BW,
 485         QED_UFP_MODE_UNKNOWN
 486 };
 487
 488 enum qed_ufp_pri_type {
 489         QED_UFP_PRI_OS,
 490         QED_UFP_PRI_VNIC,
 491         QED_UFP_PRI_UNKNOWN
 492 };
 493
 494 struct qed_ufp_info {
 495         enum qed_ufp_pri_type pri_type;
 496         enum qed_ufp_mode mode;
 497         u8 tc;
 498 };
 499
 500 enum BAR_ID {
 501         BAR_ID_0,               /* used for GRC */
 502         BAR_ID_1                /* Used for doorbells */
 503 };
 504
 505 struct qed_nvm_image_info {
 506         u32 num_images;
 507         struct bist_nvm_image_att *image_att;
 508         bool valid;
 509 };
 510
 511 enum qed_hsi_def_type {
 512         QED_HSI_DEF_MAX_NUM_VFS,
 513         QED_HSI_DEF_MAX_NUM_L2_QUEUES,
 514         QED_HSI_DEF_MAX_NUM_PORTS,
 515         QED_HSI_DEF_MAX_SB_PER_PATH,
 516         QED_HSI_DEF_MAX_NUM_PFS,
 517         QED_HSI_DEF_MAX_NUM_VPORTS,
 518         QED_HSI_DEF_NUM_ETH_RSS_ENGINE,
 519         QED_HSI_DEF_MAX_QM_TX_QUEUES,
 520         QED_HSI_DEF_NUM_PXP_ILT_RECORDS,
 521         QED_HSI_DEF_NUM_RDMA_STATISTIC_COUNTERS,
 522         QED_HSI_DEF_MAX_QM_GLOBAL_RLS,
 523         QED_HSI_DEF_MAX_PBF_CMD_LINES,
 524         QED_HSI_DEF_MAX_BTB_BLOCKS,
 525         QED_NUM_HSI_DEFS
 526 };
 527
 528 #define DRV_MODULE_VERSION                    \
 529         __stringify(QED_MAJOR_VERSION) "."    \
 530         __stringify(QED_MINOR_VERSION) "."    \
 531         __stringify(QED_REVISION_VERSION) "." \
 532         __stringify(QED_ENGINEERING_VERSION)
 533
 534 struct qed_simd_fp_handler {
 535         void    *token;
 536         void    (*func)(void *);
 537 };
 538
 539 enum qed_slowpath_wq_flag {
 540         QED_SLOWPATH_MFW_TLV_REQ,
 541         QED_SLOWPATH_PERIODIC_DB_REC,
 542 };
 543
 544 struct qed_hwfn {
 545         struct qed_dev                  *cdev;
 546         u8                              my_id;          /* ID inside the PF */
 547 #define IS_LEAD_HWFN(edev)              (!((edev)->my_id))
 548         u8                              rel_pf_id;      /* Relative to engine*/
 549         u8                              abs_pf_id;
 550 #define QED_PATH_ID(_p_hwfn) \
 551         (QED_IS_K2((_p_hwfn)->cdev) ? 0 : ((_p_hwfn)->abs_pf_id & 1))
 552         u8                              port_id;
 553         bool                            b_active;
 554
 555         u32                             dp_module;
 556         u8                              dp_level;
 557         char                            name[NAME_SIZE];
 558
 559         bool                            hw_init_done;
 560
 561         u8                              num_funcs_on_engine;
 562         u8 enabled_func_idx;
 563
 564         /* BAR access */
 565         void __iomem                    *regview;
 566         void __iomem                    *doorbells;
 567         u64                             db_phys_addr;
 568         unsigned long                   db_size;
 569
 570         /* PTT pool */
 571         struct qed_ptt_pool             *p_ptt_pool;
 572
 573         /* HW info */
 574         struct qed_hw_info              hw_info;
 575
 576         /* rt_array (for init-tool) */
 577         struct qed_rt_data              rt_data;
 578
 579         /* SPQ */
 580         struct qed_spq                  *p_spq;
 581
 582         /* EQ */
 583         struct qed_eq                   *p_eq;
 584
 585         /* Consolidate Q*/
 586         struct qed_consq                *p_consq;
 587
 588         /* Slow-Path definitions */
 589         struct tasklet_struct           *sp_dpc;
 590         bool                            b_sp_dpc_enabled;
 591
 592         struct qed_ptt                  *p_main_ptt;
 593         struct qed_ptt                  *p_dpc_ptt;
 594
 595         /* PTP will be used only by the leading function.
 596          * Usage of all PTP-apis should be synchronized as result.
 597          */
 598         struct qed_ptt *p_ptp_ptt;
 599
 600         struct qed_sb_sp_info           *p_sp_sb;
 601         struct qed_sb_attn_info         *p_sb_attn;
 602
 603         /* Protocol related */
 604         bool                            using_ll2;
 605         struct qed_ll2_info             *p_ll2_info;
 606         struct qed_ooo_info             *p_ooo_info;
 607         struct qed_rdma_info            *p_rdma_info;
 608         struct qed_iscsi_info           *p_iscsi_info;
 609         struct qed_fcoe_info            *p_fcoe_info;
 610         struct qed_pf_params            pf_params;
 611
 612         bool b_rdma_enabled_in_prs;
 613         u32 rdma_prs_search_reg;
 614
 615         struct qed_cxt_mngr             *p_cxt_mngr;
 616
 617         /* Flag indicating whether interrupts are enabled or not*/
 618         bool                            b_int_enabled;
 619         bool                            b_int_requested;
 620
 621         /* True if the driver requests for the link */
 622         bool                            b_drv_link_init;
 623
 624         struct qed_vf_iov               *vf_iov_info;
 625         struct qed_pf_iov               *pf_iov_info;
 626         struct qed_mcp_info             *mcp_info;
 627
 628         struct qed_dcbx_info            *p_dcbx_info;
 629
 630         struct qed_ufp_info             ufp_info;
 631
 632         struct qed_dmae_info            dmae_info;
 633
 634         /* QM init */
 635         struct qed_qm_info              qm_info;
 636         struct qed_storm_stats          storm_stats;
 637
 638         /* Buffer for unzipping firmware data */
 639         void                            *unzip_buf;
 640
 641         struct dbg_tools_data           dbg_info;
 642         void                            *dbg_user_info;
 643         struct virt_mem_desc            dbg_arrays[MAX_BIN_DBG_BUFFER_TYPE];
 644
 645         /* PWM region specific data */
 646         u16                             wid_count;
 647         u32                             dpi_size;
 648         u32                             dpi_count;
 649
 650         /* This is used to calculate the doorbell address */
 651         u32 dpi_start_offset;
 652
 653         /* If one of the following is set then EDPM shouldn't be used */
 654         u8 dcbx_no_edpm;
 655         u8 db_bar_no_edpm;
 656
 657         /* L2-related */
 658         struct qed_l2_info *p_l2_info;
 659
 660         /* Mechanism for recovering from doorbell drop */
 661         struct qed_db_recovery_info db_recovery_info;
 662
 663         /* Nvm images number and attributes */
 664         struct qed_nvm_image_info nvm_info;
 665
 666         struct phys_mem_desc *fw_overlay_mem;
 667         struct qed_ptt *p_arfs_ptt;
 668
 669         struct qed_simd_fp_handler      simd_proto_handler[64];
 670
 671 #ifdef CONFIG_QED_SRIOV
 672         struct workqueue_struct *iov_wq;
 673         struct delayed_work iov_task;
 674         unsigned long iov_task_flags;
 675 #endif
 676         struct z_stream_s *stream;
 677         bool slowpath_wq_active;
 678         struct workqueue_struct *slowpath_wq;
 679         struct delayed_work slowpath_task;
 680         unsigned long slowpath_task_flags;
 681         u32 periodic_db_rec_count;
 682 };
 683
 684 struct pci_params {
 685         int             pm_cap;
 686
 687         unsigned long   mem_start;
 688         unsigned long   mem_end;
 689         unsigned int    irq;
 690         u8              pf_num;
 691 };
 692
 693 struct qed_int_param {
 694         u32     int_mode;
 695         u8      num_vectors;
 696         u8      min_msix_cnt; /* for minimal functionality */
 697 };
 698
 699 struct qed_int_params {
 700         struct qed_int_param    in;
 701         struct qed_int_param    out;
 702         struct msix_entry       *msix_table;
 703         bool                    fp_initialized;
 704         u8                      fp_msix_base;
 705         u8                      fp_msix_cnt;
 706         u8                      rdma_msix_base;
 707         u8                      rdma_msix_cnt;
 708 };
 709
 710 struct qed_dbg_feature {
 711         struct dentry *dentry;
 712         u8 *dump_buf;
 713         u32 buf_size;
 714         u32 dumped_dwords;
 715 };
 716
 717 struct qed_dev {
 718         u32     dp_module;
 719         u8      dp_level;
 720         char    name[NAME_SIZE];
 721
 722         enum    qed_dev_type type;
 723 /* Translate type/revision combo into the proper conditions */
 724 #define QED_IS_BB(dev)  ((dev)->type == QED_DEV_TYPE_BB)
 725 #define QED_IS_BB_B0(dev)       (QED_IS_BB(dev) && \
 726                                  CHIP_REV_IS_B0(dev))
 727 #define QED_IS_AH(dev)  ((dev)->type == QED_DEV_TYPE_AH)
 728 #define QED_IS_K2(dev)  QED_IS_AH(dev)
 729
 730         u16     vendor_id;
 731         u16     device_id;
 732 #define QED_DEV_ID_MASK         0xff00
 733 #define QED_DEV_ID_MASK_BB      0x1600
 734 #define QED_DEV_ID_MASK_AH      0x8000
 735 #define QED_IS_E4(dev)  (QED_IS_BB(dev) || QED_IS_AH(dev))
 736
 737         u16     chip_num;
 738 #define CHIP_NUM_MASK                   0xffff
 739 #define CHIP_NUM_SHIFT                  16
 740
 741         u16     chip_rev;
 742 #define CHIP_REV_MASK                   0xf
 743 #define CHIP_REV_SHIFT                  12
 744 #define CHIP_REV_IS_B0(_cdev)   ((_cdev)->chip_rev == 1)
 745
 746         u16                             chip_metal;
 747 #define CHIP_METAL_MASK                 0xff
 748 #define CHIP_METAL_SHIFT                4
 749
 750         u16                             chip_bond_id;
 751 #define CHIP_BOND_ID_MASK               0xf
 752 #define CHIP_BOND_ID_SHIFT              0
 753
 754         u8                              num_engines;
 755         u8                              num_ports;
 756         u8                              num_ports_in_engine;
 757         u8                              num_funcs_in_port;
 758
 759         u8                              path_id;
 760
 761         unsigned long                   mf_bits;
 762
 763         int                             pcie_width;
 764         int                             pcie_speed;
 765
 766         /* Add MF related configuration */
 767         u8                              mcp_rev;
 768         u8                              boot_mode;
 769
 770         /* WoL related configurations */
 771         u8 wol_config;
 772         u8 wol_mac[ETH_ALEN];
 773
 774         u32                             int_mode;
 775         enum qed_coalescing_mode        int_coalescing_mode;
 776         u16                             rx_coalesce_usecs;
 777         u16                             tx_coalesce_usecs;
 778
 779         /* Start Bar offset of first hwfn */
 780         void __iomem                    *regview;
 781         void __iomem                    *doorbells;
 782         u64                             db_phys_addr;
 783         unsigned long                   db_size;
 784
 785         /* PCI */
 786         u8                              cache_shift;
 787
 788         /* Init */
 789         const u32 *iro_arr;
 790 #define IRO ((const struct iro *)p_hwfn->cdev->iro_arr)
 791
 792         /* HW functions */
 793         u8                              num_hwfns;
 794         struct qed_hwfn                 hwfns[MAX_HWFNS_PER_DEVICE];
 795
 796         /* Engine affinity */
 797         u8                              l2_affin_hint;
 798         u8                              fir_affin;
 799         u8                              iwarp_affin;
 800
 801         /* SRIOV */
 802         struct qed_hw_sriov_info *p_iov_info;
 803 #define IS_QED_SRIOV(cdev)              (!!(cdev)->p_iov_info)
 804         struct qed_tunnel_info          tunnel;
 805         bool                            b_is_vf;
 806         u32                             drv_type;
 807         struct qed_eth_stats            *reset_stats;
 808         struct qed_fw_data              *fw_data;
 809
 810         u32                             mcp_nvm_resp;
 811
 812         /* Recovery */
 813         bool recov_in_prog;
 814
 815         /* Indicates whether should prevent attentions from being reasserted */
 816         bool attn_clr_en;
 817
 818         /* LLH info */
 819         u8 ppfid_bitmap;
 820         struct qed_llh_info *p_llh_info;
 821
 822         /* Linux specific here */
 823         struct  qede_dev                *edev;
 824         struct  pci_dev                 *pdev;
 825         u32 flags;
 826 #define QED_FLAG_STORAGE_STARTED        (BIT(0))
 827         int                             msg_enable;
 828
 829         struct pci_params               pci_params;
 830
 831         struct qed_int_params           int_params;
 832
 833         u8                              protocol;
 834 #define IS_QED_ETH_IF(cdev)     ((cdev)->protocol == QED_PROTOCOL_ETH)
 835 #define IS_QED_FCOE_IF(cdev)    ((cdev)->protocol == QED_PROTOCOL_FCOE)
 836
 837         /* Callbacks to protocol driver */
 838         union {
 839                 struct qed_common_cb_ops        *common;
 840                 struct qed_eth_cb_ops           *eth;
 841                 struct qed_fcoe_cb_ops          *fcoe;
 842                 struct qed_iscsi_cb_ops         *iscsi;
 843         } protocol_ops;
 844         void                            *ops_cookie;
 845
 846 #ifdef CONFIG_QED_LL2
 847         struct qed_cb_ll2_info          *ll2;
 848         u8                              ll2_mac_address[ETH_ALEN];
 849 #endif
 850         struct qed_dbg_feature dbg_features[DBG_FEATURE_NUM];
 851         u8 engine_for_debug;
 852         bool disable_ilt_dump;
 853         bool                            dbg_bin_dump;
 854
 855         DECLARE_HASHTABLE(connections, 10);
 856         const struct firmware           *firmware;
 857
 858         bool print_dbg_data;
 859
 860         u32 rdma_max_sge;
 861         u32 rdma_max_inline;
 862         u32 rdma_max_srq_sge;
 863         u16 tunn_feature_mask;
 864
 865         struct devlink                  *dl;
 866         bool                            iwarp_cmt;
 867 };
 868
 869 u32 qed_get_hsi_def_val(struct qed_dev *cdev, enum qed_hsi_def_type type);
 870
 871 #define NUM_OF_VFS(dev) \
 872         qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_NUM_VFS)
 873 #define NUM_OF_L2_QUEUES(dev) \
 874         qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_NUM_L2_QUEUES)
 875 #define NUM_OF_PORTS(dev) \
 876         qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_NUM_PORTS)
 877 #define NUM_OF_SBS(dev) \
 878         qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_SB_PER_PATH)
 879 #define NUM_OF_ENG_PFS(dev) \
 880         qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_NUM_PFS)
 881 #define NUM_OF_VPORTS(dev) \
 882         qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_NUM_VPORTS)
 883 #define NUM_OF_RSS_ENGINES(dev) \
 884         qed_get_hsi_def_val(dev, QED_HSI_DEF_NUM_ETH_RSS_ENGINE)
 885 #define NUM_OF_QM_TX_QUEUES(dev) \
 886         qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_QM_TX_QUEUES)
 887 #define NUM_OF_PXP_ILT_RECORDS(dev) \
 888         qed_get_hsi_def_val(dev, QED_HSI_DEF_NUM_PXP_ILT_RECORDS)
 889 #define NUM_OF_RDMA_STATISTIC_COUNTERS(dev) \
 890         qed_get_hsi_def_val(dev, QED_HSI_DEF_NUM_RDMA_STATISTIC_COUNTERS)
 891 #define NUM_OF_QM_GLOBAL_RLS(dev) \
 892         qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_QM_GLOBAL_RLS)
 893 #define NUM_OF_PBF_CMD_LINES(dev) \
 894         qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_PBF_CMD_LINES)
 895 #define NUM_OF_BTB_BLOCKS(dev) \
 896         qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_BTB_BLOCKS)
 897
 898
 899 /**
 900  * @brief qed_concrete_to_sw_fid - get the sw function id from
 901  *        the concrete value.
 902  *
 903  * @param concrete_fid
 904  *
 905  * @return inline u8
 906  */
 907 static inline u8 qed_concrete_to_sw_fid(struct qed_dev *cdev,
 908                                         u32 concrete_fid)
 909 {
 910         u8 vfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID);
 911         u8 pfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID);
 912         u8 vf_valid = GET_FIELD(concrete_fid,
 913                                 PXP_CONCRETE_FID_VFVALID);
 914         u8 sw_fid;
 915
 916         if (vf_valid)
 917                 sw_fid = vfid + MAX_NUM_PFS;
 918         else
 919                 sw_fid = pfid;
 920
 921         return sw_fid;
 922 }
 923
 924 #define PKT_LB_TC       9
 925 #define MAX_NUM_VOQS_E4 20
 926
 927 int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate);
 928 void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev,
 929                                          struct qed_ptt *p_ptt,
 930                                          u32 min_pf_rate);
 931
 932 void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt);
 933 int qed_device_num_engines(struct qed_dev *cdev);
 934 void qed_set_fw_mac_addr(__le16 *fw_msb,
 935                          __le16 *fw_mid, __le16 *fw_lsb, u8 *mac);
 936
 937 #define QED_LEADING_HWFN(dev)   (&dev->hwfns[0])
 938 #define QED_IS_CMT(dev)         ((dev)->num_hwfns > 1)
 939 /* Macros for getting the engine-affinitized hwfn (FIR: fcoe,iscsi,roce) */
 940 #define QED_FIR_AFFIN_HWFN(dev)         (&(dev)->hwfns[dev->fir_affin])
 941 #define QED_IWARP_AFFIN_HWFN(dev)       (&(dev)->hwfns[dev->iwarp_affin])
 942 #define QED_AFFIN_HWFN(dev)                                \
 943         (QED_IS_IWARP_PERSONALITY(QED_LEADING_HWFN(dev)) ? \
 944          QED_IWARP_AFFIN_HWFN(dev) : QED_FIR_AFFIN_HWFN(dev))
 945 #define QED_AFFIN_HWFN_IDX(dev) (IS_LEAD_HWFN(QED_AFFIN_HWFN(dev)) ? 0 : 1)
 946
 947 /* Flags for indication of required queues */
 948 #define PQ_FLAGS_RLS    (BIT(0))
 949 #define PQ_FLAGS_MCOS   (BIT(1))
 950 #define PQ_FLAGS_LB     (BIT(2))
 951 #define PQ_FLAGS_OOO    (BIT(3))
 952 #define PQ_FLAGS_ACK    (BIT(4))
 953 #define PQ_FLAGS_OFLD   (BIT(5))
 954 #define PQ_FLAGS_VFS    (BIT(6))
 955 #define PQ_FLAGS_LLT    (BIT(7))
 956 #define PQ_FLAGS_MTC    (BIT(8))
 957
 958 /* physical queue index for cm context intialization */
 959 u16 qed_get_cm_pq_idx(struct qed_hwfn *p_hwfn, u32 pq_flags);
 960 u16 qed_get_cm_pq_idx_mcos(struct qed_hwfn *p_hwfn, u8 tc);
 961 u16 qed_get_cm_pq_idx_vf(struct qed_hwfn *p_hwfn, u16 vf);
 962 u16 qed_get_cm_pq_idx_ofld_mtc(struct qed_hwfn *p_hwfn, u8 tc);
 963 u16 qed_get_cm_pq_idx_llt_mtc(struct qed_hwfn *p_hwfn, u8 tc);
 964
 965 /* doorbell recovery mechanism */
 966 void qed_db_recovery_dp(struct qed_hwfn *p_hwfn);
 967 void qed_db_recovery_execute(struct qed_hwfn *p_hwfn);
 968 bool qed_edpm_enabled(struct qed_hwfn *p_hwfn);
 969
 970 /* Other Linux specific common definitions */
 971 #define DP_NAME(cdev) ((cdev)->name)
 972
 973 #define REG_ADDR(cdev, offset)          (void __iomem *)((u8 __iomem *)\
 974                                                 (cdev->regview) + \
 975                                                          (offset))
 976
 977 #define REG_RD(cdev, offset)            readl(REG_ADDR(cdev, offset))
 978 #define REG_WR(cdev, offset, val)       writel((u32)val, REG_ADDR(cdev, offset))
 979 #define REG_WR16(cdev, offset, val)     writew((u16)val, REG_ADDR(cdev, offset))
 980
 981 #define DOORBELL(cdev, db_addr, val)                     \
 982         writel((u32)val, (void __iomem *)((u8 __iomem *)\
 983                                           (cdev->doorbells) + (db_addr)))
 984
 985 #define MFW_PORT(_p_hwfn)       ((_p_hwfn)->abs_pf_id %                   \
 986                                   qed_device_num_ports((_p_hwfn)->cdev))
 987 int qed_device_num_ports(struct qed_dev *cdev);
 988
 989 /* Prototypes */
 990 int qed_fill_dev_info(struct qed_dev *cdev,
 991                       struct qed_dev_info *dev_info);
 992 void qed_link_update(struct qed_hwfn *hwfn, struct qed_ptt *ptt);
 993 void qed_bw_update(struct qed_hwfn *hwfn, struct qed_ptt *ptt);
 994 u32 qed_unzip_data(struct qed_hwfn *p_hwfn,
 995                    u32 input_len, u8 *input_buf,
 996                    u32 max_size, u8 *unzip_buf);
 997 void qed_schedule_recovery_handler(struct qed_hwfn *p_hwfn);
 998 void qed_hw_error_occurred(struct qed_hwfn *p_hwfn,
 999                            enum qed_hw_err_type err_type);
1000 void qed_get_protocol_stats(struct qed_dev *cdev,
1001                             enum qed_mcp_protocol_type type,
1002                             union qed_mcp_protocol_stats *stats);
1003 int qed_slowpath_irq_req(struct qed_hwfn *hwfn);
1004 void qed_slowpath_irq_sync(struct qed_hwfn *p_hwfn);
1005 int qed_mfw_tlv_req(struct qed_hwfn *hwfn);
1006
1007 int qed_mfw_fill_tlv_data(struct qed_hwfn *hwfn,
1008                           enum qed_mfw_tlv_type type,
1009                           union qed_mfw_tlv_data *tlv_data);
1010
1011 void qed_hw_info_set_offload_tc(struct qed_hw_info *p_info, u8 tc);
1012
1013 void qed_periodic_db_rec_start(struct qed_hwfn *p_hwfn);
1014 #endif /* _QED_H */