1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2017 - 2019 Pensando Systems, Inc */
5 #include <linux/ipv6.h>
6 #include <linux/if_vlan.h>
7 #include <net/ip6_checksum.h>
10 #include "ionic_lif.h"
11 #include "ionic_txrx.h"
14 static inline void ionic_txq_post(struct ionic_queue *q, bool ring_dbell,
15 ionic_desc_cb cb_func, void *cb_arg)
17 DEBUG_STATS_TXQ_POST(q, ring_dbell);
19 ionic_q_post(q, ring_dbell, cb_func, cb_arg);
22 static inline void ionic_rxq_post(struct ionic_queue *q, bool ring_dbell,
23 ionic_desc_cb cb_func, void *cb_arg)
25 ionic_q_post(q, ring_dbell, cb_func, cb_arg);
27 DEBUG_STATS_RX_BUFF_CNT(q);
30 static inline struct netdev_queue *q_to_ndq(struct ionic_queue *q)
32 return netdev_get_tx_queue(q->lif->netdev, q->index);
35 static void ionic_rx_buf_reset(struct ionic_buf_info *buf_info)
37 buf_info->page = NULL;
38 buf_info->page_offset = 0;
39 buf_info->dma_addr = 0;
42 static int ionic_rx_page_alloc(struct ionic_queue *q,
43 struct ionic_buf_info *buf_info)
45 struct net_device *netdev = q->lif->netdev;
46 struct ionic_rx_stats *stats;
50 stats = q_to_rx_stats(q);
52 if (unlikely(!buf_info)) {
53 net_err_ratelimited("%s: %s invalid buf_info in alloc\n",
54 netdev->name, q->name);
58 buf_info->page = alloc_pages(IONIC_PAGE_GFP_MASK, 0);
59 if (unlikely(!buf_info->page)) {
60 net_err_ratelimited("%s: %s page alloc failed\n",
61 netdev->name, q->name);
65 buf_info->page_offset = 0;
67 buf_info->dma_addr = dma_map_page(dev, buf_info->page, buf_info->page_offset,
68 IONIC_PAGE_SIZE, DMA_FROM_DEVICE);
69 if (unlikely(dma_mapping_error(dev, buf_info->dma_addr))) {
70 __free_pages(buf_info->page, 0);
71 ionic_rx_buf_reset(buf_info);
72 net_err_ratelimited("%s: %s dma map failed\n",
73 netdev->name, q->name);
81 static void ionic_rx_page_free(struct ionic_queue *q,
82 struct ionic_buf_info *buf_info)
84 struct net_device *netdev = q->lif->netdev;
85 struct device *dev = q->dev;
87 if (unlikely(!buf_info)) {
88 net_err_ratelimited("%s: %s invalid buf_info in free\n",
89 netdev->name, q->name);
96 dma_unmap_page(dev, buf_info->dma_addr, IONIC_PAGE_SIZE, DMA_FROM_DEVICE);
97 __free_pages(buf_info->page, 0);
98 ionic_rx_buf_reset(buf_info);
101 static bool ionic_rx_buf_recycle(struct ionic_queue *q,
102 struct ionic_buf_info *buf_info, u32 used)
106 /* don't re-use pages allocated in low-mem condition */
107 if (page_is_pfmemalloc(buf_info->page))
110 /* don't re-use buffers from non-local numa nodes */
111 if (page_to_nid(buf_info->page) != numa_mem_id())
114 size = ALIGN(used, IONIC_PAGE_SPLIT_SZ);
115 buf_info->page_offset += size;
116 if (buf_info->page_offset >= IONIC_PAGE_SIZE)
119 get_page(buf_info->page);
124 static struct sk_buff *ionic_rx_frags(struct ionic_queue *q,
125 struct ionic_desc_info *desc_info,
126 struct ionic_rxq_comp *comp)
128 struct net_device *netdev = q->lif->netdev;
129 struct ionic_buf_info *buf_info;
130 struct ionic_rx_stats *stats;
131 struct device *dev = q->dev;
137 stats = q_to_rx_stats(q);
139 buf_info = &desc_info->bufs[0];
140 len = le16_to_cpu(comp->len);
142 prefetch(buf_info->page);
144 skb = napi_get_frags(&q_to_qcq(q)->napi);
145 if (unlikely(!skb)) {
146 net_warn_ratelimited("%s: SKB alloc failed on %s!\n",
147 netdev->name, q->name);
152 i = comp->num_sg_elems + 1;
154 if (unlikely(!buf_info->page)) {
159 frag_len = min_t(u16, len, IONIC_PAGE_SIZE - buf_info->page_offset);
162 dma_sync_single_for_cpu(dev,
163 buf_info->dma_addr + buf_info->page_offset,
164 frag_len, DMA_FROM_DEVICE);
166 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
167 buf_info->page, buf_info->page_offset, frag_len,
170 if (!ionic_rx_buf_recycle(q, buf_info, frag_len)) {
171 dma_unmap_page(dev, buf_info->dma_addr,
172 IONIC_PAGE_SIZE, DMA_FROM_DEVICE);
173 ionic_rx_buf_reset(buf_info);
184 static struct sk_buff *ionic_rx_copybreak(struct ionic_queue *q,
185 struct ionic_desc_info *desc_info,
186 struct ionic_rxq_comp *comp)
188 struct net_device *netdev = q->lif->netdev;
189 struct ionic_buf_info *buf_info;
190 struct ionic_rx_stats *stats;
191 struct device *dev = q->dev;
195 stats = q_to_rx_stats(q);
197 buf_info = &desc_info->bufs[0];
198 len = le16_to_cpu(comp->len);
200 skb = napi_alloc_skb(&q_to_qcq(q)->napi, len);
201 if (unlikely(!skb)) {
202 net_warn_ratelimited("%s: SKB alloc failed on %s!\n",
203 netdev->name, q->name);
208 if (unlikely(!buf_info->page)) {
213 dma_sync_single_for_cpu(dev, buf_info->dma_addr + buf_info->page_offset,
214 len, DMA_FROM_DEVICE);
215 skb_copy_to_linear_data(skb, page_address(buf_info->page) + buf_info->page_offset, len);
216 dma_sync_single_for_device(dev, buf_info->dma_addr + buf_info->page_offset,
217 len, DMA_FROM_DEVICE);
220 skb->protocol = eth_type_trans(skb, q->lif->netdev);
225 static void ionic_rx_clean(struct ionic_queue *q,
226 struct ionic_desc_info *desc_info,
227 struct ionic_cq_info *cq_info,
230 struct net_device *netdev = q->lif->netdev;
231 struct ionic_qcq *qcq = q_to_qcq(q);
232 struct ionic_rx_stats *stats;
233 struct ionic_rxq_comp *comp;
236 comp = cq_info->cq_desc + qcq->cq.desc_size - sizeof(*comp);
238 stats = q_to_rx_stats(q);
246 stats->bytes += le16_to_cpu(comp->len);
248 if (le16_to_cpu(comp->len) <= q->lif->rx_copybreak)
249 skb = ionic_rx_copybreak(q, desc_info, comp);
251 skb = ionic_rx_frags(q, desc_info, comp);
253 if (unlikely(!skb)) {
258 skb_record_rx_queue(skb, q->index);
260 if (likely(netdev->features & NETIF_F_RXHASH)) {
261 switch (comp->pkt_type_color & IONIC_RXQ_COMP_PKT_TYPE_MASK) {
262 case IONIC_PKT_TYPE_IPV4:
263 case IONIC_PKT_TYPE_IPV6:
264 skb_set_hash(skb, le32_to_cpu(comp->rss_hash),
267 case IONIC_PKT_TYPE_IPV4_TCP:
268 case IONIC_PKT_TYPE_IPV6_TCP:
269 case IONIC_PKT_TYPE_IPV4_UDP:
270 case IONIC_PKT_TYPE_IPV6_UDP:
271 skb_set_hash(skb, le32_to_cpu(comp->rss_hash),
277 if (likely(netdev->features & NETIF_F_RXCSUM) &&
278 (comp->csum_flags & IONIC_RXQ_COMP_CSUM_F_CALC)) {
279 skb->ip_summed = CHECKSUM_COMPLETE;
280 skb->csum = (__force __wsum)le16_to_cpu(comp->csum);
281 stats->csum_complete++;
286 if (unlikely((comp->csum_flags & IONIC_RXQ_COMP_CSUM_F_TCP_BAD) ||
287 (comp->csum_flags & IONIC_RXQ_COMP_CSUM_F_UDP_BAD) ||
288 (comp->csum_flags & IONIC_RXQ_COMP_CSUM_F_IP_BAD)))
291 if (likely(netdev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
292 (comp->csum_flags & IONIC_RXQ_COMP_CSUM_F_VLAN)) {
293 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
294 le16_to_cpu(comp->vlan_tci));
295 stats->vlan_stripped++;
298 if (unlikely(q->features & IONIC_RXQ_F_HWSTAMP)) {
299 __le64 *cq_desc_hwstamp;
305 sizeof(struct ionic_rxq_comp) -
306 IONIC_HWSTAMP_CQ_NEGOFFSET;
308 hwstamp = le64_to_cpu(*cq_desc_hwstamp);
310 if (hwstamp != IONIC_HWSTAMP_INVALID) {
311 skb_hwtstamps(skb)->hwtstamp = ionic_lif_phc_ktime(q->lif, hwstamp);
312 stats->hwstamp_valid++;
314 stats->hwstamp_invalid++;
318 if (le16_to_cpu(comp->len) <= q->lif->rx_copybreak)
319 napi_gro_receive(&qcq->napi, skb);
321 napi_gro_frags(&qcq->napi);
324 bool ionic_rx_service(struct ionic_cq *cq, struct ionic_cq_info *cq_info)
326 struct ionic_queue *q = cq->bound_q;
327 struct ionic_desc_info *desc_info;
328 struct ionic_rxq_comp *comp;
330 comp = cq_info->cq_desc + cq->desc_size - sizeof(*comp);
332 if (!color_match(comp->pkt_type_color, cq->done_color))
335 /* check for empty queue */
336 if (q->tail_idx == q->head_idx)
339 if (q->tail_idx != le16_to_cpu(comp->comp_index))
342 desc_info = &q->info[q->tail_idx];
343 q->tail_idx = (q->tail_idx + 1) & (q->num_descs - 1);
345 /* clean the related q entry, only one per qc completion */
346 ionic_rx_clean(q, desc_info, cq_info, desc_info->cb_arg);
348 desc_info->cb = NULL;
349 desc_info->cb_arg = NULL;
354 void ionic_rx_fill(struct ionic_queue *q)
356 struct net_device *netdev = q->lif->netdev;
357 struct ionic_desc_info *desc_info;
358 struct ionic_rxq_sg_desc *sg_desc;
359 struct ionic_rxq_sg_elem *sg_elem;
360 struct ionic_buf_info *buf_info;
361 struct ionic_rxq_desc *desc;
362 unsigned int remain_len;
363 unsigned int frag_len;
368 len = netdev->mtu + ETH_HLEN + VLAN_HLEN;
370 for (i = ionic_q_space_avail(q); i; i--) {
373 desc_info = &q->info[q->head_idx];
374 desc = desc_info->desc;
375 buf_info = &desc_info->bufs[0];
377 if (!buf_info->page) { /* alloc a new buffer? */
378 if (unlikely(ionic_rx_page_alloc(q, buf_info))) {
385 /* fill main descriptor - buf[0] */
386 desc->addr = cpu_to_le64(buf_info->dma_addr + buf_info->page_offset);
387 frag_len = min_t(u16, len, IONIC_PAGE_SIZE - buf_info->page_offset);
388 desc->len = cpu_to_le16(frag_len);
389 remain_len -= frag_len;
393 /* fill sg descriptors - buf[1..n] */
394 sg_desc = desc_info->sg_desc;
395 for (j = 0; remain_len > 0 && j < q->max_sg_elems; j++) {
396 sg_elem = &sg_desc->elems[j];
397 if (!buf_info->page) { /* alloc a new sg buffer? */
398 if (unlikely(ionic_rx_page_alloc(q, buf_info))) {
405 sg_elem->addr = cpu_to_le64(buf_info->dma_addr + buf_info->page_offset);
406 frag_len = min_t(u16, remain_len, IONIC_PAGE_SIZE - buf_info->page_offset);
407 sg_elem->len = cpu_to_le16(frag_len);
408 remain_len -= frag_len;
413 /* clear end sg element as a sentinel */
414 if (j < q->max_sg_elems) {
415 sg_elem = &sg_desc->elems[j];
416 memset(sg_elem, 0, sizeof(*sg_elem));
419 desc->opcode = (nfrags > 1) ? IONIC_RXQ_DESC_OPCODE_SG :
420 IONIC_RXQ_DESC_OPCODE_SIMPLE;
421 desc_info->nbufs = nfrags;
423 ionic_rxq_post(q, false, ionic_rx_clean, NULL);
426 ionic_dbell_ring(q->lif->kern_dbpage, q->hw_type,
427 q->dbval | q->head_idx);
430 void ionic_rx_empty(struct ionic_queue *q)
432 struct ionic_desc_info *desc_info;
433 struct ionic_buf_info *buf_info;
436 for (i = 0; i < q->num_descs; i++) {
437 desc_info = &q->info[i];
438 for (j = 0; j < IONIC_RX_MAX_SG_ELEMS + 1; j++) {
439 buf_info = &desc_info->bufs[j];
441 ionic_rx_page_free(q, buf_info);
444 desc_info->nbufs = 0;
445 desc_info->cb = NULL;
446 desc_info->cb_arg = NULL;
453 static void ionic_dim_update(struct ionic_qcq *qcq, int napi_mode)
455 struct dim_sample dim_sample;
456 struct ionic_lif *lif;
460 if (!qcq->intr.dim_coal_hw)
464 qi = qcq->cq.bound_q->index;
467 case IONIC_LIF_F_TX_DIM_INTR:
468 pkts = lif->txqstats[qi].pkts;
469 bytes = lif->txqstats[qi].bytes;
471 case IONIC_LIF_F_RX_DIM_INTR:
472 pkts = lif->rxqstats[qi].pkts;
473 bytes = lif->rxqstats[qi].bytes;
476 pkts = lif->txqstats[qi].pkts + lif->rxqstats[qi].pkts;
477 bytes = lif->txqstats[qi].bytes + lif->rxqstats[qi].bytes;
481 dim_update_sample(qcq->cq.bound_intr->rearm_count,
482 pkts, bytes, &dim_sample);
484 net_dim(&qcq->dim, dim_sample);
487 int ionic_tx_napi(struct napi_struct *napi, int budget)
489 struct ionic_qcq *qcq = napi_to_qcq(napi);
490 struct ionic_cq *cq = napi_to_cq(napi);
491 struct ionic_dev *idev;
492 struct ionic_lif *lif;
496 lif = cq->bound_q->lif;
497 idev = &lif->ionic->idev;
499 work_done = ionic_cq_service(cq, budget,
500 ionic_tx_service, NULL, NULL);
502 if (work_done < budget && napi_complete_done(napi, work_done)) {
503 ionic_dim_update(qcq, IONIC_LIF_F_TX_DIM_INTR);
504 flags |= IONIC_INTR_CRED_UNMASK;
505 cq->bound_intr->rearm_count++;
508 if (work_done || flags) {
509 flags |= IONIC_INTR_CRED_RESET_COALESCE;
510 ionic_intr_credits(idev->intr_ctrl,
511 cq->bound_intr->index,
515 DEBUG_STATS_NAPI_POLL(qcq, work_done);
520 int ionic_rx_napi(struct napi_struct *napi, int budget)
522 struct ionic_qcq *qcq = napi_to_qcq(napi);
523 struct ionic_cq *cq = napi_to_cq(napi);
524 struct ionic_dev *idev;
525 struct ionic_lif *lif;
526 u16 rx_fill_threshold;
530 lif = cq->bound_q->lif;
531 idev = &lif->ionic->idev;
533 work_done = ionic_cq_service(cq, budget,
534 ionic_rx_service, NULL, NULL);
536 rx_fill_threshold = min_t(u16, IONIC_RX_FILL_THRESHOLD,
537 cq->num_descs / IONIC_RX_FILL_DIV);
538 if (work_done && ionic_q_space_avail(cq->bound_q) >= rx_fill_threshold)
539 ionic_rx_fill(cq->bound_q);
541 if (work_done < budget && napi_complete_done(napi, work_done)) {
542 ionic_dim_update(qcq, IONIC_LIF_F_RX_DIM_INTR);
543 flags |= IONIC_INTR_CRED_UNMASK;
544 cq->bound_intr->rearm_count++;
547 if (work_done || flags) {
548 flags |= IONIC_INTR_CRED_RESET_COALESCE;
549 ionic_intr_credits(idev->intr_ctrl,
550 cq->bound_intr->index,
554 DEBUG_STATS_NAPI_POLL(qcq, work_done);
559 int ionic_txrx_napi(struct napi_struct *napi, int budget)
561 struct ionic_qcq *qcq = napi_to_qcq(napi);
562 struct ionic_cq *rxcq = napi_to_cq(napi);
563 unsigned int qi = rxcq->bound_q->index;
564 struct ionic_dev *idev;
565 struct ionic_lif *lif;
566 struct ionic_cq *txcq;
567 u16 rx_fill_threshold;
568 u32 rx_work_done = 0;
569 u32 tx_work_done = 0;
572 lif = rxcq->bound_q->lif;
573 idev = &lif->ionic->idev;
574 txcq = &lif->txqcqs[qi]->cq;
576 tx_work_done = ionic_cq_service(txcq, IONIC_TX_BUDGET_DEFAULT,
577 ionic_tx_service, NULL, NULL);
579 rx_work_done = ionic_cq_service(rxcq, budget,
580 ionic_rx_service, NULL, NULL);
582 rx_fill_threshold = min_t(u16, IONIC_RX_FILL_THRESHOLD,
583 rxcq->num_descs / IONIC_RX_FILL_DIV);
584 if (rx_work_done && ionic_q_space_avail(rxcq->bound_q) >= rx_fill_threshold)
585 ionic_rx_fill(rxcq->bound_q);
587 if (rx_work_done < budget && napi_complete_done(napi, rx_work_done)) {
588 ionic_dim_update(qcq, 0);
589 flags |= IONIC_INTR_CRED_UNMASK;
590 rxcq->bound_intr->rearm_count++;
593 if (rx_work_done || flags) {
594 flags |= IONIC_INTR_CRED_RESET_COALESCE;
595 ionic_intr_credits(idev->intr_ctrl, rxcq->bound_intr->index,
596 tx_work_done + rx_work_done, flags);
599 DEBUG_STATS_NAPI_POLL(qcq, rx_work_done);
600 DEBUG_STATS_NAPI_POLL(qcq, tx_work_done);
605 static dma_addr_t ionic_tx_map_single(struct ionic_queue *q,
606 void *data, size_t len)
608 struct ionic_tx_stats *stats = q_to_tx_stats(q);
609 struct device *dev = q->dev;
612 dma_addr = dma_map_single(dev, data, len, DMA_TO_DEVICE);
613 if (dma_mapping_error(dev, dma_addr)) {
614 net_warn_ratelimited("%s: DMA single map failed on %s!\n",
615 q->lif->netdev->name, q->name);
616 stats->dma_map_err++;
622 static dma_addr_t ionic_tx_map_frag(struct ionic_queue *q,
623 const skb_frag_t *frag,
624 size_t offset, size_t len)
626 struct ionic_tx_stats *stats = q_to_tx_stats(q);
627 struct device *dev = q->dev;
630 dma_addr = skb_frag_dma_map(dev, frag, offset, len, DMA_TO_DEVICE);
631 if (dma_mapping_error(dev, dma_addr)) {
632 net_warn_ratelimited("%s: DMA frag map failed on %s!\n",
633 q->lif->netdev->name, q->name);
634 stats->dma_map_err++;
639 static int ionic_tx_map_skb(struct ionic_queue *q, struct sk_buff *skb,
640 struct ionic_desc_info *desc_info)
642 struct ionic_buf_info *buf_info = desc_info->bufs;
643 struct ionic_tx_stats *stats = q_to_tx_stats(q);
644 struct device *dev = q->dev;
650 dma_addr = ionic_tx_map_single(q, skb->data, skb_headlen(skb));
651 if (dma_mapping_error(dev, dma_addr)) {
652 stats->dma_map_err++;
655 buf_info->dma_addr = dma_addr;
656 buf_info->len = skb_headlen(skb);
659 frag = skb_shinfo(skb)->frags;
660 nfrags = skb_shinfo(skb)->nr_frags;
661 for (frag_idx = 0; frag_idx < nfrags; frag_idx++, frag++) {
662 dma_addr = ionic_tx_map_frag(q, frag, 0, skb_frag_size(frag));
663 if (dma_mapping_error(dev, dma_addr)) {
664 stats->dma_map_err++;
667 buf_info->dma_addr = dma_addr;
668 buf_info->len = skb_frag_size(frag);
672 desc_info->nbufs = 1 + nfrags;
677 /* unwind the frag mappings and the head mapping */
678 while (frag_idx > 0) {
681 dma_unmap_page(dev, buf_info->dma_addr,
682 buf_info->len, DMA_TO_DEVICE);
684 dma_unmap_single(dev, buf_info->dma_addr, buf_info->len, DMA_TO_DEVICE);
688 static void ionic_tx_clean(struct ionic_queue *q,
689 struct ionic_desc_info *desc_info,
690 struct ionic_cq_info *cq_info,
693 struct ionic_buf_info *buf_info = desc_info->bufs;
694 struct ionic_tx_stats *stats = q_to_tx_stats(q);
695 struct ionic_qcq *qcq = q_to_qcq(q);
696 struct sk_buff *skb = cb_arg;
697 struct device *dev = q->dev;
701 if (desc_info->nbufs) {
702 dma_unmap_single(dev, (dma_addr_t)buf_info->dma_addr,
703 buf_info->len, DMA_TO_DEVICE);
705 for (i = 1; i < desc_info->nbufs; i++, buf_info++)
706 dma_unmap_page(dev, (dma_addr_t)buf_info->dma_addr,
707 buf_info->len, DMA_TO_DEVICE);
713 qi = skb_get_queue_mapping(skb);
715 if (unlikely(q->features & IONIC_TXQ_F_HWSTAMP)) {
717 struct skb_shared_hwtstamps hwts = {};
718 __le64 *cq_desc_hwstamp;
724 sizeof(struct ionic_txq_comp) -
725 IONIC_HWSTAMP_CQ_NEGOFFSET;
727 hwstamp = le64_to_cpu(*cq_desc_hwstamp);
729 if (hwstamp != IONIC_HWSTAMP_INVALID) {
730 hwts.hwtstamp = ionic_lif_phc_ktime(q->lif, hwstamp);
732 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
733 skb_tstamp_tx(skb, &hwts);
735 stats->hwstamp_valid++;
737 stats->hwstamp_invalid++;
741 } else if (unlikely(__netif_subqueue_stopped(q->lif->netdev, qi))) {
742 netif_wake_subqueue(q->lif->netdev, qi);
746 desc_info->bytes = skb->len;
749 dev_consume_skb_any(skb);
752 bool ionic_tx_service(struct ionic_cq *cq, struct ionic_cq_info *cq_info)
754 struct ionic_queue *q = cq->bound_q;
755 struct ionic_desc_info *desc_info;
756 struct ionic_txq_comp *comp;
761 comp = cq_info->cq_desc + cq->desc_size - sizeof(*comp);
763 if (!color_match(comp->color, cq->done_color))
766 /* clean the related q entries, there could be
767 * several q entries completed for each cq completion
770 desc_info = &q->info[q->tail_idx];
771 desc_info->bytes = 0;
773 q->tail_idx = (q->tail_idx + 1) & (q->num_descs - 1);
774 ionic_tx_clean(q, desc_info, cq_info, desc_info->cb_arg);
775 if (desc_info->cb_arg) {
777 bytes += desc_info->bytes;
779 desc_info->cb = NULL;
780 desc_info->cb_arg = NULL;
781 } while (index != le16_to_cpu(comp->comp_index));
783 if (pkts && bytes && !unlikely(q->features & IONIC_TXQ_F_HWSTAMP))
784 netdev_tx_completed_queue(q_to_ndq(q), pkts, bytes);
789 void ionic_tx_flush(struct ionic_cq *cq)
791 struct ionic_dev *idev = &cq->lif->ionic->idev;
794 work_done = ionic_cq_service(cq, cq->num_descs,
795 ionic_tx_service, NULL, NULL);
797 ionic_intr_credits(idev->intr_ctrl, cq->bound_intr->index,
798 work_done, IONIC_INTR_CRED_RESET_COALESCE);
801 void ionic_tx_empty(struct ionic_queue *q)
803 struct ionic_desc_info *desc_info;
807 /* walk the not completed tx entries, if any */
808 while (q->head_idx != q->tail_idx) {
809 desc_info = &q->info[q->tail_idx];
810 desc_info->bytes = 0;
811 q->tail_idx = (q->tail_idx + 1) & (q->num_descs - 1);
812 ionic_tx_clean(q, desc_info, NULL, desc_info->cb_arg);
813 if (desc_info->cb_arg) {
815 bytes += desc_info->bytes;
817 desc_info->cb = NULL;
818 desc_info->cb_arg = NULL;
821 if (pkts && bytes && !unlikely(q->features & IONIC_TXQ_F_HWSTAMP))
822 netdev_tx_completed_queue(q_to_ndq(q), pkts, bytes);
825 static int ionic_tx_tcp_inner_pseudo_csum(struct sk_buff *skb)
829 err = skb_cow_head(skb, 0);
833 if (skb->protocol == cpu_to_be16(ETH_P_IP)) {
834 inner_ip_hdr(skb)->check = 0;
835 inner_tcp_hdr(skb)->check =
836 ~csum_tcpudp_magic(inner_ip_hdr(skb)->saddr,
837 inner_ip_hdr(skb)->daddr,
839 } else if (skb->protocol == cpu_to_be16(ETH_P_IPV6)) {
840 inner_tcp_hdr(skb)->check =
841 ~csum_ipv6_magic(&inner_ipv6_hdr(skb)->saddr,
842 &inner_ipv6_hdr(skb)->daddr,
849 static int ionic_tx_tcp_pseudo_csum(struct sk_buff *skb)
853 err = skb_cow_head(skb, 0);
857 if (skb->protocol == cpu_to_be16(ETH_P_IP)) {
858 ip_hdr(skb)->check = 0;
859 tcp_hdr(skb)->check =
860 ~csum_tcpudp_magic(ip_hdr(skb)->saddr,
863 } else if (skb->protocol == cpu_to_be16(ETH_P_IPV6)) {
864 tcp_v6_gso_csum_prep(skb);
870 static void ionic_tx_tso_post(struct ionic_queue *q, struct ionic_txq_desc *desc,
872 dma_addr_t addr, u8 nsge, u16 len,
873 unsigned int hdrlen, unsigned int mss,
875 u16 vlan_tci, bool has_vlan,
876 bool start, bool done)
881 flags |= has_vlan ? IONIC_TXQ_DESC_FLAG_VLAN : 0;
882 flags |= outer_csum ? IONIC_TXQ_DESC_FLAG_ENCAP : 0;
883 flags |= start ? IONIC_TXQ_DESC_FLAG_TSO_SOT : 0;
884 flags |= done ? IONIC_TXQ_DESC_FLAG_TSO_EOT : 0;
886 cmd = encode_txq_desc_cmd(IONIC_TXQ_DESC_OPCODE_TSO, flags, nsge, addr);
887 desc->cmd = cpu_to_le64(cmd);
888 desc->len = cpu_to_le16(len);
889 desc->vlan_tci = cpu_to_le16(vlan_tci);
890 desc->hdr_len = cpu_to_le16(hdrlen);
891 desc->mss = cpu_to_le16(mss);
894 skb_tx_timestamp(skb);
895 if (!unlikely(q->features & IONIC_TXQ_F_HWSTAMP))
896 netdev_tx_sent_queue(q_to_ndq(q), skb->len);
897 ionic_txq_post(q, false, ionic_tx_clean, skb);
899 ionic_txq_post(q, done, NULL, NULL);
903 static int ionic_tx_tso(struct ionic_queue *q, struct sk_buff *skb)
905 struct ionic_tx_stats *stats = q_to_tx_stats(q);
906 struct ionic_desc_info *desc_info;
907 struct ionic_buf_info *buf_info;
908 struct ionic_txq_sg_elem *elem;
909 struct ionic_txq_desc *desc;
910 unsigned int chunk_len;
911 unsigned int frag_rem;
912 unsigned int tso_rem;
913 unsigned int seg_rem;
914 dma_addr_t desc_addr;
915 dma_addr_t frag_addr;
928 desc_info = &q->info[q->head_idx];
929 buf_info = desc_info->bufs;
931 if (unlikely(ionic_tx_map_skb(q, skb, desc_info)))
935 mss = skb_shinfo(skb)->gso_size;
936 outer_csum = (skb_shinfo(skb)->gso_type & SKB_GSO_GRE_CSUM) ||
937 (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM);
938 has_vlan = !!skb_vlan_tag_present(skb);
939 vlan_tci = skb_vlan_tag_get(skb);
940 encap = skb->encapsulation;
942 /* Preload inner-most TCP csum field with IP pseudo hdr
943 * calculated with IP length set to zero. HW will later
944 * add in length to each TCP segment resulting from the TSO.
948 err = ionic_tx_tcp_inner_pseudo_csum(skb);
950 err = ionic_tx_tcp_pseudo_csum(skb);
955 hdrlen = skb_inner_transport_header(skb) - skb->data +
956 inner_tcp_hdrlen(skb);
958 hdrlen = skb_transport_offset(skb) + tcp_hdrlen(skb);
961 seg_rem = min(tso_rem, hdrlen + mss);
968 while (tso_rem > 0) {
974 /* use fragments until we have enough to post a single descriptor */
975 while (seg_rem > 0) {
976 /* if the fragment is exhausted then move to the next one */
978 /* grab the next fragment */
979 frag_addr = buf_info->dma_addr;
980 frag_rem = buf_info->len;
983 chunk_len = min(frag_rem, seg_rem);
985 /* fill main descriptor */
986 desc = desc_info->txq_desc;
987 elem = desc_info->txq_sg_desc->elems;
988 desc_addr = frag_addr;
989 desc_len = chunk_len;
991 /* fill sg descriptor */
992 elem->addr = cpu_to_le64(frag_addr);
993 elem->len = cpu_to_le16(chunk_len);
997 frag_addr += chunk_len;
998 frag_rem -= chunk_len;
999 tso_rem -= chunk_len;
1000 seg_rem -= chunk_len;
1002 seg_rem = min(tso_rem, mss);
1003 done = (tso_rem == 0);
1004 /* post descriptor */
1005 ionic_tx_tso_post(q, desc, skb,
1006 desc_addr, desc_nsge, desc_len,
1007 hdrlen, mss, outer_csum, vlan_tci, has_vlan,
1010 /* Buffer information is stored with the first tso descriptor */
1011 desc_info = &q->info[q->head_idx];
1012 desc_info->nbufs = 0;
1015 stats->pkts += DIV_ROUND_UP(len - hdrlen, mss);
1016 stats->bytes += len;
1018 stats->tso_bytes = len;
1023 static int ionic_tx_calc_csum(struct ionic_queue *q, struct sk_buff *skb,
1024 struct ionic_desc_info *desc_info)
1026 struct ionic_txq_desc *desc = desc_info->txq_desc;
1027 struct ionic_buf_info *buf_info = desc_info->bufs;
1028 struct ionic_tx_stats *stats = q_to_tx_stats(q);
1034 has_vlan = !!skb_vlan_tag_present(skb);
1035 encap = skb->encapsulation;
1037 flags |= has_vlan ? IONIC_TXQ_DESC_FLAG_VLAN : 0;
1038 flags |= encap ? IONIC_TXQ_DESC_FLAG_ENCAP : 0;
1040 cmd = encode_txq_desc_cmd(IONIC_TXQ_DESC_OPCODE_CSUM_PARTIAL,
1041 flags, skb_shinfo(skb)->nr_frags,
1042 buf_info->dma_addr);
1043 desc->cmd = cpu_to_le64(cmd);
1044 desc->len = cpu_to_le16(buf_info->len);
1046 desc->vlan_tci = cpu_to_le16(skb_vlan_tag_get(skb));
1047 stats->vlan_inserted++;
1051 desc->csum_start = cpu_to_le16(skb_checksum_start_offset(skb));
1052 desc->csum_offset = cpu_to_le16(skb->csum_offset);
1054 if (skb_csum_is_sctp(skb))
1055 stats->crc32_csum++;
1062 static int ionic_tx_calc_no_csum(struct ionic_queue *q, struct sk_buff *skb,
1063 struct ionic_desc_info *desc_info)
1065 struct ionic_txq_desc *desc = desc_info->txq_desc;
1066 struct ionic_buf_info *buf_info = desc_info->bufs;
1067 struct ionic_tx_stats *stats = q_to_tx_stats(q);
1073 has_vlan = !!skb_vlan_tag_present(skb);
1074 encap = skb->encapsulation;
1076 flags |= has_vlan ? IONIC_TXQ_DESC_FLAG_VLAN : 0;
1077 flags |= encap ? IONIC_TXQ_DESC_FLAG_ENCAP : 0;
1079 cmd = encode_txq_desc_cmd(IONIC_TXQ_DESC_OPCODE_CSUM_NONE,
1080 flags, skb_shinfo(skb)->nr_frags,
1081 buf_info->dma_addr);
1082 desc->cmd = cpu_to_le64(cmd);
1083 desc->len = cpu_to_le16(buf_info->len);
1085 desc->vlan_tci = cpu_to_le16(skb_vlan_tag_get(skb));
1086 stats->vlan_inserted++;
1090 desc->csum_start = 0;
1091 desc->csum_offset = 0;
1098 static int ionic_tx_skb_frags(struct ionic_queue *q, struct sk_buff *skb,
1099 struct ionic_desc_info *desc_info)
1101 struct ionic_txq_sg_desc *sg_desc = desc_info->txq_sg_desc;
1102 struct ionic_buf_info *buf_info = &desc_info->bufs[1];
1103 struct ionic_txq_sg_elem *elem = sg_desc->elems;
1104 struct ionic_tx_stats *stats = q_to_tx_stats(q);
1107 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++, buf_info++, elem++) {
1108 elem->addr = cpu_to_le64(buf_info->dma_addr);
1109 elem->len = cpu_to_le16(buf_info->len);
1112 stats->frags += skb_shinfo(skb)->nr_frags;
1117 static int ionic_tx(struct ionic_queue *q, struct sk_buff *skb)
1119 struct ionic_desc_info *desc_info = &q->info[q->head_idx];
1120 struct ionic_tx_stats *stats = q_to_tx_stats(q);
1123 if (unlikely(ionic_tx_map_skb(q, skb, desc_info)))
1126 /* set up the initial descriptor */
1127 if (skb->ip_summed == CHECKSUM_PARTIAL)
1128 err = ionic_tx_calc_csum(q, skb, desc_info);
1130 err = ionic_tx_calc_no_csum(q, skb, desc_info);
1135 err = ionic_tx_skb_frags(q, skb, desc_info);
1139 skb_tx_timestamp(skb);
1141 stats->bytes += skb->len;
1143 if (!unlikely(q->features & IONIC_TXQ_F_HWSTAMP))
1144 netdev_tx_sent_queue(q_to_ndq(q), skb->len);
1145 ionic_txq_post(q, !netdev_xmit_more(), ionic_tx_clean, skb);
1150 static int ionic_tx_descs_needed(struct ionic_queue *q, struct sk_buff *skb)
1152 struct ionic_tx_stats *stats = q_to_tx_stats(q);
1156 /* Each desc is mss long max, so a descriptor for each gso_seg */
1157 if (skb_is_gso(skb))
1158 ndescs = skb_shinfo(skb)->gso_segs;
1162 /* If non-TSO, just need 1 desc and nr_frags sg elems */
1163 if (skb_shinfo(skb)->nr_frags <= q->max_sg_elems)
1166 /* Too many frags, so linearize */
1167 err = skb_linearize(skb);
1176 static int ionic_maybe_stop_tx(struct ionic_queue *q, int ndescs)
1180 if (unlikely(!ionic_q_has_space(q, ndescs))) {
1181 netif_stop_subqueue(q->lif->netdev, q->index);
1185 /* Might race with ionic_tx_clean, check again */
1187 if (ionic_q_has_space(q, ndescs)) {
1188 netif_wake_subqueue(q->lif->netdev, q->index);
1196 static netdev_tx_t ionic_start_hwstamp_xmit(struct sk_buff *skb,
1197 struct net_device *netdev)
1199 struct ionic_lif *lif = netdev_priv(netdev);
1200 struct ionic_queue *q = &lif->hwstamp_txq->q;
1203 /* Does not stop/start txq, because we post to a separate tx queue
1204 * for timestamping, and if a packet can't be posted immediately to
1205 * the timestamping queue, it is dropped.
1208 ndescs = ionic_tx_descs_needed(q, skb);
1209 if (unlikely(ndescs < 0))
1212 if (unlikely(!ionic_q_has_space(q, ndescs)))
1215 skb_shinfo(skb)->tx_flags |= SKBTX_HW_TSTAMP;
1216 if (skb_is_gso(skb))
1217 err = ionic_tx_tso(q, skb);
1219 err = ionic_tx(q, skb);
1224 return NETDEV_TX_OK;
1229 return NETDEV_TX_OK;
1232 netdev_tx_t ionic_start_xmit(struct sk_buff *skb, struct net_device *netdev)
1234 u16 queue_index = skb_get_queue_mapping(skb);
1235 struct ionic_lif *lif = netdev_priv(netdev);
1236 struct ionic_queue *q;
1240 if (unlikely(!test_bit(IONIC_LIF_F_UP, lif->state))) {
1242 return NETDEV_TX_OK;
1245 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP))
1246 if (lif->hwstamp_txq && lif->phc->ts_config_tx_mode)
1247 return ionic_start_hwstamp_xmit(skb, netdev);
1249 if (unlikely(queue_index >= lif->nxqs))
1251 q = &lif->txqcqs[queue_index]->q;
1253 ndescs = ionic_tx_descs_needed(q, skb);
1257 if (unlikely(ionic_maybe_stop_tx(q, ndescs)))
1258 return NETDEV_TX_BUSY;
1260 if (skb_is_gso(skb))
1261 err = ionic_tx_tso(q, skb);
1263 err = ionic_tx(q, skb);
1268 /* Stop the queue if there aren't descriptors for the next packet.
1269 * Since our SG lists per descriptor take care of most of the possible
1270 * fragmentation, we don't need to have many descriptors available.
1272 ionic_maybe_stop_tx(q, 4);
1274 return NETDEV_TX_OK;
1280 return NETDEV_TX_OK;