drivers/net/ethernet/pensando/ionic/ionic_txrx.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Copyright(c) 2017 - 2019 Pensando Systems, Inc */
   3
   4 #include <linux/ip.h>
   5 #include <linux/ipv6.h>
   6 #include <linux/if_vlan.h>
   7 #include <net/ip6_checksum.h>
   8
   9 #include "ionic.h"
  10 #include "ionic_lif.h"
  11 #include "ionic_txrx.h"
  12
  13 static void ionic_rx_clean(struct ionic_queue *q,
  14                            struct ionic_desc_info *desc_info,
  15                            struct ionic_cq_info *cq_info,
  16                            void *cb_arg);
  17
  18 static bool ionic_rx_service(struct ionic_cq *cq, struct ionic_cq_info *cq_info);
  19
  20 static bool ionic_tx_service(struct ionic_cq *cq, struct ionic_cq_info *cq_info);
  21
  22 static inline void ionic_txq_post(struct ionic_queue *q, bool ring_dbell,
  23                                   ionic_desc_cb cb_func, void *cb_arg)
  24 {
  25         DEBUG_STATS_TXQ_POST(q, ring_dbell);
  26
  27         ionic_q_post(q, ring_dbell, cb_func, cb_arg);
  28 }
  29
  30 static inline void ionic_rxq_post(struct ionic_queue *q, bool ring_dbell,
  31                                   ionic_desc_cb cb_func, void *cb_arg)
  32 {
  33         ionic_q_post(q, ring_dbell, cb_func, cb_arg);
  34
  35         DEBUG_STATS_RX_BUFF_CNT(q);
  36 }
  37
  38 static inline struct netdev_queue *q_to_ndq(struct ionic_queue *q)
  39 {
  40         return netdev_get_tx_queue(q->lif->netdev, q->index);
  41 }
  42
  43 static struct sk_buff *ionic_rx_skb_alloc(struct ionic_queue *q,
  44                                           unsigned int len, bool frags)
  45 {
  46         struct ionic_lif *lif = q->lif;
  47         struct ionic_rx_stats *stats;
  48         struct net_device *netdev;
  49         struct sk_buff *skb;
  50
  51         netdev = lif->netdev;
  52         stats = &q->lif->rxqstats[q->index];
  53
  54         if (frags)
  55                 skb = napi_get_frags(&q_to_qcq(q)->napi);
  56         else
  57                 skb = netdev_alloc_skb_ip_align(netdev, len);
  58
  59         if (unlikely(!skb)) {
  60                 net_warn_ratelimited("%s: SKB alloc failed on %s!\n",
  61                                      netdev->name, q->name);
  62                 stats->alloc_err++;
  63                 return NULL;
  64         }
  65
  66         return skb;
  67 }
  68
  69 static struct sk_buff *ionic_rx_frags(struct ionic_queue *q,
  70                                       struct ionic_desc_info *desc_info,
  71                                       struct ionic_cq_info *cq_info)
  72 {
  73         struct ionic_rxq_comp *comp = cq_info->cq_desc;
  74         struct device *dev = q->lif->ionic->dev;
  75         struct ionic_page_info *page_info;
  76         struct sk_buff *skb;
  77         unsigned int i;
  78         u16 frag_len;
  79         u16 len;
  80
  81         page_info = &desc_info->pages[0];
  82         len = le16_to_cpu(comp->len);
  83
  84         prefetch(page_address(page_info->page) + NET_IP_ALIGN);
  85
  86         skb = ionic_rx_skb_alloc(q, len, true);
  87         if (unlikely(!skb))
  88                 return NULL;
  89
  90         i = comp->num_sg_elems + 1;
  91         do {
  92                 if (unlikely(!page_info->page)) {
  93                         struct napi_struct *napi = &q_to_qcq(q)->napi;
  94
  95                         napi->skb = NULL;
  96                         dev_kfree_skb(skb);
  97                         return NULL;
  98                 }
  99
 100                 frag_len = min(len, (u16)PAGE_SIZE);
 101                 len -= frag_len;
 102
 103                 dma_unmap_page(dev, dma_unmap_addr(page_info, dma_addr),
 104                                PAGE_SIZE, DMA_FROM_DEVICE);
 105                 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
 106                                 page_info->page, 0, frag_len, PAGE_SIZE);
 107                 page_info->page = NULL;
 108                 page_info++;
 109                 i--;
 110         } while (i > 0);
 111
 112         return skb;
 113 }
 114
 115 static struct sk_buff *ionic_rx_copybreak(struct ionic_queue *q,
 116                                           struct ionic_desc_info *desc_info,
 117                                           struct ionic_cq_info *cq_info)
 118 {
 119         struct ionic_rxq_comp *comp = cq_info->cq_desc;
 120         struct device *dev = q->lif->ionic->dev;
 121         struct ionic_page_info *page_info;
 122         struct sk_buff *skb;
 123         u16 len;
 124
 125         page_info = &desc_info->pages[0];
 126         len = le16_to_cpu(comp->len);
 127
 128         skb = ionic_rx_skb_alloc(q, len, false);
 129         if (unlikely(!skb))
 130                 return NULL;
 131
 132         if (unlikely(!page_info->page)) {
 133                 dev_kfree_skb(skb);
 134                 return NULL;
 135         }
 136
 137         dma_sync_single_for_cpu(dev, dma_unmap_addr(page_info, dma_addr),
 138                                 len, DMA_FROM_DEVICE);
 139         skb_copy_to_linear_data(skb, page_address(page_info->page), len);
 140         dma_sync_single_for_device(dev, dma_unmap_addr(page_info, dma_addr),
 141                                    len, DMA_FROM_DEVICE);
 142
 143         skb_put(skb, len);
 144         skb->protocol = eth_type_trans(skb, q->lif->netdev);
 145
 146         return skb;
 147 }
 148
 149 static void ionic_rx_clean(struct ionic_queue *q,
 150                            struct ionic_desc_info *desc_info,
 151                            struct ionic_cq_info *cq_info,
 152                            void *cb_arg)
 153 {
 154         struct ionic_rxq_comp *comp = cq_info->cq_desc;
 155         struct ionic_qcq *qcq = q_to_qcq(q);
 156         struct ionic_rx_stats *stats;
 157         struct net_device *netdev;
 158         struct sk_buff *skb;
 159
 160         stats = q_to_rx_stats(q);
 161         netdev = q->lif->netdev;
 162
 163         if (comp->status) {
 164                 stats->dropped++;
 165                 return;
 166         }
 167
 168         stats->pkts++;
 169         stats->bytes += le16_to_cpu(comp->len);
 170
 171         if (le16_to_cpu(comp->len) <= q->lif->rx_copybreak)
 172                 skb = ionic_rx_copybreak(q, desc_info, cq_info);
 173         else
 174                 skb = ionic_rx_frags(q, desc_info, cq_info);
 175
 176         if (unlikely(!skb)) {
 177                 stats->dropped++;
 178                 return;
 179         }
 180
 181         skb_record_rx_queue(skb, q->index);
 182
 183         if (likely(netdev->features & NETIF_F_RXHASH)) {
 184                 switch (comp->pkt_type_color & IONIC_RXQ_COMP_PKT_TYPE_MASK) {
 185                 case IONIC_PKT_TYPE_IPV4:
 186                 case IONIC_PKT_TYPE_IPV6:
 187                         skb_set_hash(skb, le32_to_cpu(comp->rss_hash),
 188                                      PKT_HASH_TYPE_L3);
 189                         break;
 190                 case IONIC_PKT_TYPE_IPV4_TCP:
 191                 case IONIC_PKT_TYPE_IPV6_TCP:
 192                 case IONIC_PKT_TYPE_IPV4_UDP:
 193                 case IONIC_PKT_TYPE_IPV6_UDP:
 194                         skb_set_hash(skb, le32_to_cpu(comp->rss_hash),
 195                                      PKT_HASH_TYPE_L4);
 196                         break;
 197                 }
 198         }
 199
 200         if (likely(netdev->features & NETIF_F_RXCSUM)) {
 201                 if (comp->csum_flags & IONIC_RXQ_COMP_CSUM_F_CALC) {
 202                         skb->ip_summed = CHECKSUM_COMPLETE;
 203                         skb->csum = (__force __wsum)le16_to_cpu(comp->csum);
 204                         stats->csum_complete++;
 205                 }
 206         } else {
 207                 stats->csum_none++;
 208         }
 209
 210         if (unlikely((comp->csum_flags & IONIC_RXQ_COMP_CSUM_F_TCP_BAD) ||
 211                      (comp->csum_flags & IONIC_RXQ_COMP_CSUM_F_UDP_BAD) ||
 212                      (comp->csum_flags & IONIC_RXQ_COMP_CSUM_F_IP_BAD)))
 213                 stats->csum_error++;
 214
 215         if (likely(netdev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
 216             (comp->csum_flags & IONIC_RXQ_COMP_CSUM_F_VLAN)) {
 217                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
 218                                        le16_to_cpu(comp->vlan_tci));
 219                 stats->vlan_stripped++;
 220         }
 221
 222         if (le16_to_cpu(comp->len) <= q->lif->rx_copybreak)
 223                 napi_gro_receive(&qcq->napi, skb);
 224         else
 225                 napi_gro_frags(&qcq->napi);
 226 }
 227
 228 static bool ionic_rx_service(struct ionic_cq *cq, struct ionic_cq_info *cq_info)
 229 {
 230         struct ionic_rxq_comp *comp = cq_info->cq_desc;
 231         struct ionic_queue *q = cq->bound_q;
 232         struct ionic_desc_info *desc_info;
 233
 234         if (!color_match(comp->pkt_type_color, cq->done_color))
 235                 return false;
 236
 237         /* check for empty queue */
 238         if (q->tail_idx == q->head_idx)
 239                 return false;
 240
 241         if (q->tail_idx != le16_to_cpu(comp->comp_index))
 242                 return false;
 243
 244         desc_info = &q->info[q->tail_idx];
 245         q->tail_idx = (q->tail_idx + 1) & (q->num_descs - 1);
 246
 247         /* clean the related q entry, only one per qc completion */
 248         ionic_rx_clean(q, desc_info, cq_info, desc_info->cb_arg);
 249
 250         desc_info->cb = NULL;
 251         desc_info->cb_arg = NULL;
 252
 253         return true;
 254 }
 255
 256 static int ionic_rx_page_alloc(struct ionic_queue *q,
 257                                struct ionic_page_info *page_info)
 258 {
 259         struct ionic_lif *lif = q->lif;
 260         struct ionic_rx_stats *stats;
 261         struct net_device *netdev;
 262         struct device *dev;
 263
 264         netdev = lif->netdev;
 265         dev = lif->ionic->dev;
 266         stats = q_to_rx_stats(q);
 267
 268         if (unlikely(!page_info)) {
 269                 net_err_ratelimited("%s: %s invalid page_info in alloc\n",
 270                                     netdev->name, q->name);
 271                 return -EINVAL;
 272         }
 273
 274         page_info->page = dev_alloc_page();
 275         if (unlikely(!page_info->page)) {
 276                 net_err_ratelimited("%s: %s page alloc failed\n",
 277                                     netdev->name, q->name);
 278                 stats->alloc_err++;
 279                 return -ENOMEM;
 280         }
 281
 282         page_info->dma_addr = dma_map_page(dev, page_info->page, 0, PAGE_SIZE,
 283                                            DMA_FROM_DEVICE);
 284         if (unlikely(dma_mapping_error(dev, page_info->dma_addr))) {
 285                 put_page(page_info->page);
 286                 page_info->dma_addr = 0;
 287                 page_info->page = NULL;
 288                 net_err_ratelimited("%s: %s dma map failed\n",
 289                                     netdev->name, q->name);
 290                 stats->dma_map_err++;
 291                 return -EIO;
 292         }
 293
 294         return 0;
 295 }
 296
 297 static void ionic_rx_page_free(struct ionic_queue *q,
 298                                struct ionic_page_info *page_info)
 299 {
 300         struct ionic_lif *lif = q->lif;
 301         struct net_device *netdev;
 302         struct device *dev;
 303
 304         netdev = lif->netdev;
 305         dev = lif->ionic->dev;
 306
 307         if (unlikely(!page_info)) {
 308                 net_err_ratelimited("%s: %s invalid page_info in free\n",
 309                                     netdev->name, q->name);
 310                 return;
 311         }
 312
 313         if (unlikely(!page_info->page)) {
 314                 net_err_ratelimited("%s: %s invalid page in free\n",
 315                                     netdev->name, q->name);
 316                 return;
 317         }
 318
 319         dma_unmap_page(dev, page_info->dma_addr, PAGE_SIZE, DMA_FROM_DEVICE);
 320
 321         put_page(page_info->page);
 322         page_info->dma_addr = 0;
 323         page_info->page = NULL;
 324 }
 325
 326 void ionic_rx_fill(struct ionic_queue *q)
 327 {
 328         struct net_device *netdev = q->lif->netdev;
 329         struct ionic_desc_info *desc_info;
 330         struct ionic_page_info *page_info;
 331         struct ionic_rxq_sg_desc *sg_desc;
 332         struct ionic_rxq_sg_elem *sg_elem;
 333         struct ionic_rxq_desc *desc;
 334         unsigned int remain_len;
 335         unsigned int seg_len;
 336         unsigned int nfrags;
 337         unsigned int i, j;
 338         unsigned int len;
 339
 340         len = netdev->mtu + ETH_HLEN + VLAN_HLEN;
 341         nfrags = round_up(len, PAGE_SIZE) / PAGE_SIZE;
 342
 343         for (i = ionic_q_space_avail(q); i; i--) {
 344                 remain_len = len;
 345                 desc_info = &q->info[q->head_idx];
 346                 desc = desc_info->desc;
 347                 sg_desc = desc_info->sg_desc;
 348                 page_info = &desc_info->pages[0];
 349
 350                 if (page_info->page) { /* recycle the buffer */
 351                         ionic_rxq_post(q, false, ionic_rx_clean, NULL);
 352                         continue;
 353                 }
 354
 355                 /* fill main descriptor - pages[0] */
 356                 desc->opcode = (nfrags > 1) ? IONIC_RXQ_DESC_OPCODE_SG :
 357                                               IONIC_RXQ_DESC_OPCODE_SIMPLE;
 358                 desc_info->npages = nfrags;
 359                 if (unlikely(ionic_rx_page_alloc(q, page_info))) {
 360                         desc->addr = 0;
 361                         desc->len = 0;
 362                         return;
 363                 }
 364                 desc->addr = cpu_to_le64(page_info->dma_addr);
 365                 seg_len = min_t(unsigned int, PAGE_SIZE, len);
 366                 desc->len = cpu_to_le16(seg_len);
 367                 remain_len -= seg_len;
 368                 page_info++;
 369
 370                 /* fill sg descriptors - pages[1..n] */
 371                 for (j = 0; j < nfrags - 1; j++) {
 372                         if (page_info->page) /* recycle the sg buffer */
 373                                 continue;
 374
 375                         sg_elem = &sg_desc->elems[j];
 376                         if (unlikely(ionic_rx_page_alloc(q, page_info))) {
 377                                 sg_elem->addr = 0;
 378                                 sg_elem->len = 0;
 379                                 return;
 380                         }
 381                         sg_elem->addr = cpu_to_le64(page_info->dma_addr);
 382                         seg_len = min_t(unsigned int, PAGE_SIZE, remain_len);
 383                         sg_elem->len = cpu_to_le16(seg_len);
 384                         remain_len -= seg_len;
 385                         page_info++;
 386                 }
 387
 388                 ionic_rxq_post(q, false, ionic_rx_clean, NULL);
 389         }
 390
 391         ionic_dbell_ring(q->lif->kern_dbpage, q->hw_type,
 392                          q->dbval | q->head_idx);
 393 }
 394
 395 void ionic_rx_empty(struct ionic_queue *q)
 396 {
 397         struct ionic_desc_info *desc_info;
 398         struct ionic_page_info *page_info;
 399         unsigned int i, j;
 400
 401         for (i = 0; i < q->num_descs; i++) {
 402                 desc_info = &q->info[i];
 403                 for (j = 0; j < IONIC_RX_MAX_SG_ELEMS + 1; j++) {
 404                         page_info = &desc_info->pages[j];
 405                         if (page_info->page)
 406                                 ionic_rx_page_free(q, page_info);
 407                 }
 408
 409                 desc_info->npages = 0;
 410                 desc_info->cb = NULL;
 411                 desc_info->cb_arg = NULL;
 412         }
 413 }
 414
 415 static void ionic_dim_update(struct ionic_qcq *qcq)
 416 {
 417         struct dim_sample dim_sample;
 418         struct ionic_lif *lif;
 419         unsigned int qi;
 420
 421         if (!qcq->intr.dim_coal_hw)
 422                 return;
 423
 424         lif = qcq->q.lif;
 425         qi = qcq->cq.bound_q->index;
 426
 427         ionic_intr_coal_init(lif->ionic->idev.intr_ctrl,
 428                              lif->rxqcqs[qi]->intr.index,
 429                              qcq->intr.dim_coal_hw);
 430
 431         dim_update_sample(qcq->cq.bound_intr->rearm_count,
 432                           lif->txqstats[qi].pkts,
 433                           lif->txqstats[qi].bytes,
 434                           &dim_sample);
 435
 436         net_dim(&qcq->dim, dim_sample);
 437 }
 438
 439 int ionic_tx_napi(struct napi_struct *napi, int budget)
 440 {
 441         struct ionic_qcq *qcq = napi_to_qcq(napi);
 442         struct ionic_cq *cq = napi_to_cq(napi);
 443         struct ionic_dev *idev;
 444         struct ionic_lif *lif;
 445         u32 work_done = 0;
 446         u32 flags = 0;
 447
 448         lif = cq->bound_q->lif;
 449         idev = &lif->ionic->idev;
 450
 451         work_done = ionic_cq_service(cq, budget,
 452                                      ionic_tx_service, NULL, NULL);
 453
 454         if (work_done < budget && napi_complete_done(napi, work_done)) {
 455                 ionic_dim_update(qcq);
 456                 flags |= IONIC_INTR_CRED_UNMASK;
 457                 cq->bound_intr->rearm_count++;
 458         }
 459
 460         if (work_done || flags) {
 461                 flags |= IONIC_INTR_CRED_RESET_COALESCE;
 462                 ionic_intr_credits(idev->intr_ctrl,
 463                                    cq->bound_intr->index,
 464                                    work_done, flags);
 465         }
 466
 467         DEBUG_STATS_NAPI_POLL(qcq, work_done);
 468
 469         return work_done;
 470 }
 471
 472 int ionic_rx_napi(struct napi_struct *napi, int budget)
 473 {
 474         struct ionic_qcq *qcq = napi_to_qcq(napi);
 475         struct ionic_cq *cq = napi_to_cq(napi);
 476         struct ionic_dev *idev;
 477         struct ionic_lif *lif;
 478         u16 rx_fill_threshold;
 479         u32 work_done = 0;
 480         u32 flags = 0;
 481
 482         lif = cq->bound_q->lif;
 483         idev = &lif->ionic->idev;
 484
 485         work_done = ionic_cq_service(cq, budget,
 486                                      ionic_rx_service, NULL, NULL);
 487
 488         rx_fill_threshold = min_t(u16, IONIC_RX_FILL_THRESHOLD,
 489                                   cq->num_descs / IONIC_RX_FILL_DIV);
 490         if (work_done && ionic_q_space_avail(cq->bound_q) >= rx_fill_threshold)
 491                 ionic_rx_fill(cq->bound_q);
 492
 493         if (work_done < budget && napi_complete_done(napi, work_done)) {
 494                 ionic_dim_update(qcq);
 495                 flags |= IONIC_INTR_CRED_UNMASK;
 496                 cq->bound_intr->rearm_count++;
 497         }
 498
 499         if (work_done || flags) {
 500                 flags |= IONIC_INTR_CRED_RESET_COALESCE;
 501                 ionic_intr_credits(idev->intr_ctrl,
 502                                    cq->bound_intr->index,
 503                                    work_done, flags);
 504         }
 505
 506         DEBUG_STATS_NAPI_POLL(qcq, work_done);
 507
 508         return work_done;
 509 }
 510
 511 int ionic_txrx_napi(struct napi_struct *napi, int budget)
 512 {
 513         struct ionic_qcq *qcq = napi_to_qcq(napi);
 514         struct ionic_cq *rxcq = napi_to_cq(napi);
 515         unsigned int qi = rxcq->bound_q->index;
 516         struct ionic_dev *idev;
 517         struct ionic_lif *lif;
 518         struct ionic_cq *txcq;
 519         u16 rx_fill_threshold;
 520         u32 rx_work_done = 0;
 521         u32 tx_work_done = 0;
 522         u32 flags = 0;
 523
 524         lif = rxcq->bound_q->lif;
 525         idev = &lif->ionic->idev;
 526         txcq = &lif->txqcqs[qi]->cq;
 527
 528         tx_work_done = ionic_cq_service(txcq, lif->tx_budget,
 529                                         ionic_tx_service, NULL, NULL);
 530
 531         rx_work_done = ionic_cq_service(rxcq, budget,
 532                                         ionic_rx_service, NULL, NULL);
 533
 534         rx_fill_threshold = min_t(u16, IONIC_RX_FILL_THRESHOLD,
 535                                   rxcq->num_descs / IONIC_RX_FILL_DIV);
 536         if (rx_work_done && ionic_q_space_avail(rxcq->bound_q) >= rx_fill_threshold)
 537                 ionic_rx_fill(rxcq->bound_q);
 538
 539         if (rx_work_done < budget && napi_complete_done(napi, rx_work_done)) {
 540                 ionic_dim_update(qcq);
 541                 flags |= IONIC_INTR_CRED_UNMASK;
 542                 rxcq->bound_intr->rearm_count++;
 543         }
 544
 545         if (rx_work_done || flags) {
 546                 flags |= IONIC_INTR_CRED_RESET_COALESCE;
 547                 ionic_intr_credits(idev->intr_ctrl, rxcq->bound_intr->index,
 548                                    tx_work_done + rx_work_done, flags);
 549         }
 550
 551         DEBUG_STATS_NAPI_POLL(qcq, rx_work_done);
 552         DEBUG_STATS_NAPI_POLL(qcq, tx_work_done);
 553
 554         return rx_work_done;
 555 }
 556
 557 static dma_addr_t ionic_tx_map_single(struct ionic_queue *q,
 558                                       void *data, size_t len)
 559 {
 560         struct ionic_tx_stats *stats = q_to_tx_stats(q);
 561         struct device *dev = q->lif->ionic->dev;
 562         dma_addr_t dma_addr;
 563
 564         dma_addr = dma_map_single(dev, data, len, DMA_TO_DEVICE);
 565         if (dma_mapping_error(dev, dma_addr)) {
 566                 net_warn_ratelimited("%s: DMA single map failed on %s!\n",
 567                                      q->lif->netdev->name, q->name);
 568                 stats->dma_map_err++;
 569                 return 0;
 570         }
 571         return dma_addr;
 572 }
 573
 574 static dma_addr_t ionic_tx_map_frag(struct ionic_queue *q,
 575                                     const skb_frag_t *frag,
 576                                     size_t offset, size_t len)
 577 {
 578         struct ionic_tx_stats *stats = q_to_tx_stats(q);
 579         struct device *dev = q->lif->ionic->dev;
 580         dma_addr_t dma_addr;
 581
 582         dma_addr = skb_frag_dma_map(dev, frag, offset, len, DMA_TO_DEVICE);
 583         if (dma_mapping_error(dev, dma_addr)) {
 584                 net_warn_ratelimited("%s: DMA frag map failed on %s!\n",
 585                                      q->lif->netdev->name, q->name);
 586                 stats->dma_map_err++;
 587         }
 588         return dma_addr;
 589 }
 590
 591 static void ionic_tx_clean(struct ionic_queue *q,
 592                            struct ionic_desc_info *desc_info,
 593                            struct ionic_cq_info *cq_info,
 594                            void *cb_arg)
 595 {
 596         struct ionic_txq_sg_desc *sg_desc = desc_info->sg_desc;
 597         struct ionic_txq_sg_elem *elem = sg_desc->elems;
 598         struct ionic_tx_stats *stats = q_to_tx_stats(q);
 599         struct ionic_txq_desc *desc = desc_info->desc;
 600         struct device *dev = q->lif->ionic->dev;
 601         u8 opcode, flags, nsge;
 602         u16 queue_index;
 603         unsigned int i;
 604         u64 addr;
 605
 606         decode_txq_desc_cmd(le64_to_cpu(desc->cmd),
 607                             &opcode, &flags, &nsge, &addr);
 608
 609         /* use unmap_single only if either this is not TSO,
 610          * or this is first descriptor of a TSO
 611          */
 612         if (opcode != IONIC_TXQ_DESC_OPCODE_TSO ||
 613             flags & IONIC_TXQ_DESC_FLAG_TSO_SOT)
 614                 dma_unmap_single(dev, (dma_addr_t)addr,
 615                                  le16_to_cpu(desc->len), DMA_TO_DEVICE);
 616         else
 617                 dma_unmap_page(dev, (dma_addr_t)addr,
 618                                le16_to_cpu(desc->len), DMA_TO_DEVICE);
 619
 620         for (i = 0; i < nsge; i++, elem++)
 621                 dma_unmap_page(dev, (dma_addr_t)le64_to_cpu(elem->addr),
 622                                le16_to_cpu(elem->len), DMA_TO_DEVICE);
 623
 624         if (cb_arg) {
 625                 struct sk_buff *skb = cb_arg;
 626                 u32 len = skb->len;
 627
 628                 queue_index = skb_get_queue_mapping(skb);
 629                 if (unlikely(__netif_subqueue_stopped(q->lif->netdev,
 630                                                       queue_index))) {
 631                         netif_wake_subqueue(q->lif->netdev, queue_index);
 632                         q->wake++;
 633                 }
 634                 dev_kfree_skb_any(skb);
 635                 stats->clean++;
 636                 netdev_tx_completed_queue(q_to_ndq(q), 1, len);
 637         }
 638 }
 639
 640 static bool ionic_tx_service(struct ionic_cq *cq, struct ionic_cq_info *cq_info)
 641 {
 642         struct ionic_txq_comp *comp = cq_info->cq_desc;
 643         struct ionic_queue *q = cq->bound_q;
 644         struct ionic_desc_info *desc_info;
 645         u16 index;
 646
 647         if (!color_match(comp->color, cq->done_color))
 648                 return false;
 649
 650         /* clean the related q entries, there could be
 651          * several q entries completed for each cq completion
 652          */
 653         do {
 654                 desc_info = &q->info[q->tail_idx];
 655                 index = q->tail_idx;
 656                 q->tail_idx = (q->tail_idx + 1) & (q->num_descs - 1);
 657                 ionic_tx_clean(q, desc_info, cq_info, desc_info->cb_arg);
 658                 desc_info->cb = NULL;
 659                 desc_info->cb_arg = NULL;
 660         } while (index != le16_to_cpu(comp->comp_index));
 661
 662         return true;
 663 }
 664
 665 void ionic_tx_flush(struct ionic_cq *cq)
 666 {
 667         struct ionic_dev *idev = &cq->lif->ionic->idev;
 668         u32 work_done;
 669
 670         work_done = ionic_cq_service(cq, cq->num_descs,
 671                                      ionic_tx_service, NULL, NULL);
 672         if (work_done)
 673                 ionic_intr_credits(idev->intr_ctrl, cq->bound_intr->index,
 674                                    work_done, IONIC_INTR_CRED_RESET_COALESCE);
 675 }
 676
 677 void ionic_tx_empty(struct ionic_queue *q)
 678 {
 679         struct ionic_desc_info *desc_info;
 680
 681         /* walk the not completed tx entries, if any */
 682         while (q->head_idx != q->tail_idx) {
 683                 desc_info = &q->info[q->tail_idx];
 684                 q->tail_idx = (q->tail_idx + 1) & (q->num_descs - 1);
 685                 ionic_tx_clean(q, desc_info, NULL, desc_info->cb_arg);
 686                 desc_info->cb = NULL;
 687                 desc_info->cb_arg = NULL;
 688         }
 689 }
 690
 691 static int ionic_tx_tcp_inner_pseudo_csum(struct sk_buff *skb)
 692 {
 693         int err;
 694
 695         err = skb_cow_head(skb, 0);
 696         if (err)
 697                 return err;
 698
 699         if (skb->protocol == cpu_to_be16(ETH_P_IP)) {
 700                 inner_ip_hdr(skb)->check = 0;
 701                 inner_tcp_hdr(skb)->check =
 702                         ~csum_tcpudp_magic(inner_ip_hdr(skb)->saddr,
 703                                            inner_ip_hdr(skb)->daddr,
 704                                            0, IPPROTO_TCP, 0);
 705         } else if (skb->protocol == cpu_to_be16(ETH_P_IPV6)) {
 706                 inner_tcp_hdr(skb)->check =
 707                         ~csum_ipv6_magic(&inner_ipv6_hdr(skb)->saddr,
 708                                          &inner_ipv6_hdr(skb)->daddr,
 709                                          0, IPPROTO_TCP, 0);
 710         }
 711
 712         return 0;
 713 }
 714
 715 static int ionic_tx_tcp_pseudo_csum(struct sk_buff *skb)
 716 {
 717         int err;
 718
 719         err = skb_cow_head(skb, 0);
 720         if (err)
 721                 return err;
 722
 723         if (skb->protocol == cpu_to_be16(ETH_P_IP)) {
 724                 ip_hdr(skb)->check = 0;
 725                 tcp_hdr(skb)->check =
 726                         ~csum_tcpudp_magic(ip_hdr(skb)->saddr,
 727                                            ip_hdr(skb)->daddr,
 728                                            0, IPPROTO_TCP, 0);
 729         } else if (skb->protocol == cpu_to_be16(ETH_P_IPV6)) {
 730                 tcp_v6_gso_csum_prep(skb);
 731         }
 732
 733         return 0;
 734 }
 735
 736 static void ionic_tx_tso_post(struct ionic_queue *q, struct ionic_txq_desc *desc,
 737                               struct sk_buff *skb,
 738                               dma_addr_t addr, u8 nsge, u16 len,
 739                               unsigned int hdrlen, unsigned int mss,
 740                               bool outer_csum,
 741                               u16 vlan_tci, bool has_vlan,
 742                               bool start, bool done)
 743 {
 744         u8 flags = 0;
 745         u64 cmd;
 746
 747         flags |= has_vlan ? IONIC_TXQ_DESC_FLAG_VLAN : 0;
 748         flags |= outer_csum ? IONIC_TXQ_DESC_FLAG_ENCAP : 0;
 749         flags |= start ? IONIC_TXQ_DESC_FLAG_TSO_SOT : 0;
 750         flags |= done ? IONIC_TXQ_DESC_FLAG_TSO_EOT : 0;
 751
 752         cmd = encode_txq_desc_cmd(IONIC_TXQ_DESC_OPCODE_TSO, flags, nsge, addr);
 753         desc->cmd = cpu_to_le64(cmd);
 754         desc->len = cpu_to_le16(len);
 755         desc->vlan_tci = cpu_to_le16(vlan_tci);
 756         desc->hdr_len = cpu_to_le16(hdrlen);
 757         desc->mss = cpu_to_le16(mss);
 758
 759         if (done) {
 760                 skb_tx_timestamp(skb);
 761                 netdev_tx_sent_queue(q_to_ndq(q), skb->len);
 762                 ionic_txq_post(q, !netdev_xmit_more(), ionic_tx_clean, skb);
 763         } else {
 764                 ionic_txq_post(q, false, ionic_tx_clean, NULL);
 765         }
 766 }
 767
 768 static struct ionic_txq_desc *ionic_tx_tso_next(struct ionic_queue *q,
 769                                                 struct ionic_txq_sg_elem **elem)
 770 {
 771         struct ionic_txq_sg_desc *sg_desc = q->info[q->head_idx].txq_sg_desc;
 772         struct ionic_txq_desc *desc = q->info[q->head_idx].txq_desc;
 773
 774         *elem = sg_desc->elems;
 775         return desc;
 776 }
 777
 778 static int ionic_tx_tso(struct ionic_queue *q, struct sk_buff *skb)
 779 {
 780         struct ionic_tx_stats *stats = q_to_tx_stats(q);
 781         struct ionic_desc_info *rewind_desc_info;
 782         struct device *dev = q->lif->ionic->dev;
 783         struct ionic_txq_sg_elem *elem;
 784         struct ionic_txq_desc *desc;
 785         unsigned int frag_left = 0;
 786         unsigned int offset = 0;
 787         u16 abort = q->head_idx;
 788         unsigned int len_left;
 789         dma_addr_t desc_addr;
 790         unsigned int hdrlen;
 791         unsigned int nfrags;
 792         unsigned int seglen;
 793         u64 total_bytes = 0;
 794         u64 total_pkts = 0;
 795         u16 rewind = abort;
 796         unsigned int left;
 797         unsigned int len;
 798         unsigned int mss;
 799         skb_frag_t *frag;
 800         bool start, done;
 801         bool outer_csum;
 802         dma_addr_t addr;
 803         bool has_vlan;
 804         u16 desc_len;
 805         u8 desc_nsge;
 806         u16 vlan_tci;
 807         bool encap;
 808         int err;
 809
 810         mss = skb_shinfo(skb)->gso_size;
 811         nfrags = skb_shinfo(skb)->nr_frags;
 812         len_left = skb->len - skb_headlen(skb);
 813         outer_csum = (skb_shinfo(skb)->gso_type & SKB_GSO_GRE_CSUM) ||
 814                      (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM);
 815         has_vlan = !!skb_vlan_tag_present(skb);
 816         vlan_tci = skb_vlan_tag_get(skb);
 817         encap = skb->encapsulation;
 818
 819         /* Preload inner-most TCP csum field with IP pseudo hdr
 820          * calculated with IP length set to zero.  HW will later
 821          * add in length to each TCP segment resulting from the TSO.
 822          */
 823
 824         if (encap)
 825                 err = ionic_tx_tcp_inner_pseudo_csum(skb);
 826         else
 827                 err = ionic_tx_tcp_pseudo_csum(skb);
 828         if (err)
 829                 return err;
 830
 831         if (encap)
 832                 hdrlen = skb_inner_transport_header(skb) - skb->data +
 833                          inner_tcp_hdrlen(skb);
 834         else
 835                 hdrlen = skb_transport_offset(skb) + tcp_hdrlen(skb);
 836
 837         seglen = hdrlen + mss;
 838         left = skb_headlen(skb);
 839
 840         desc = ionic_tx_tso_next(q, &elem);
 841         start = true;
 842
 843         /* Chop skb->data up into desc segments */
 844
 845         while (left > 0) {
 846                 len = min(seglen, left);
 847                 frag_left = seglen - len;
 848                 desc_addr = ionic_tx_map_single(q, skb->data + offset, len);
 849                 if (dma_mapping_error(dev, desc_addr))
 850                         goto err_out_abort;
 851                 desc_len = len;
 852                 desc_nsge = 0;
 853                 left -= len;
 854                 offset += len;
 855                 if (nfrags > 0 && frag_left > 0)
 856                         continue;
 857                 done = (nfrags == 0 && left == 0);
 858                 ionic_tx_tso_post(q, desc, skb,
 859                                   desc_addr, desc_nsge, desc_len,
 860                                   hdrlen, mss,
 861                                   outer_csum,
 862                                   vlan_tci, has_vlan,
 863                                   start, done);
 864                 total_pkts++;
 865                 total_bytes += start ? len : len + hdrlen;
 866                 desc = ionic_tx_tso_next(q, &elem);
 867                 start = false;
 868                 seglen = mss;
 869         }
 870
 871         /* Chop skb frags into desc segments */
 872
 873         for (frag = skb_shinfo(skb)->frags; len_left; frag++) {
 874                 offset = 0;
 875                 left = skb_frag_size(frag);
 876                 len_left -= left;
 877                 nfrags--;
 878                 stats->frags++;
 879
 880                 while (left > 0) {
 881                         if (frag_left > 0) {
 882                                 len = min(frag_left, left);
 883                                 frag_left -= len;
 884                                 addr = ionic_tx_map_frag(q, frag, offset, len);
 885                                 if (dma_mapping_error(dev, addr))
 886                                         goto err_out_abort;
 887                                 elem->addr = cpu_to_le64(addr);
 888                                 elem->len = cpu_to_le16(len);
 889                                 elem++;
 890                                 desc_nsge++;
 891                                 left -= len;
 892                                 offset += len;
 893                                 if (nfrags > 0 && frag_left > 0)
 894                                         continue;
 895                                 done = (nfrags == 0 && left == 0);
 896                                 ionic_tx_tso_post(q, desc, skb, desc_addr,
 897                                                   desc_nsge, desc_len,
 898                                                   hdrlen, mss, outer_csum,
 899                                                   vlan_tci, has_vlan,
 900                                                   start, done);
 901                                 total_pkts++;
 902                                 total_bytes += start ? len : len + hdrlen;
 903                                 desc = ionic_tx_tso_next(q, &elem);
 904                                 start = false;
 905                         } else {
 906                                 len = min(mss, left);
 907                                 frag_left = mss - len;
 908                                 desc_addr = ionic_tx_map_frag(q, frag,
 909                                                               offset, len);
 910                                 if (dma_mapping_error(dev, desc_addr))
 911                                         goto err_out_abort;
 912                                 desc_len = len;
 913                                 desc_nsge = 0;
 914                                 left -= len;
 915                                 offset += len;
 916                                 if (nfrags > 0 && frag_left > 0)
 917                                         continue;
 918                                 done = (nfrags == 0 && left == 0);
 919                                 ionic_tx_tso_post(q, desc, skb, desc_addr,
 920                                                   desc_nsge, desc_len,
 921                                                   hdrlen, mss, outer_csum,
 922                                                   vlan_tci, has_vlan,
 923                                                   start, done);
 924                                 total_pkts++;
 925                                 total_bytes += start ? len : len + hdrlen;
 926                                 desc = ionic_tx_tso_next(q, &elem);
 927                                 start = false;
 928                         }
 929                 }
 930         }
 931
 932         stats->pkts += total_pkts;
 933         stats->bytes += total_bytes;
 934         stats->tso++;
 935         stats->tso_bytes += total_bytes;
 936
 937         return 0;
 938
 939 err_out_abort:
 940         while (rewind != q->head_idx) {
 941                 rewind_desc_info = &q->info[rewind];
 942                 ionic_tx_clean(q, rewind_desc_info, NULL, NULL);
 943                 rewind = (rewind + 1) & (q->num_descs - 1);
 944         }
 945         q->head_idx = abort;
 946
 947         return -ENOMEM;
 948 }
 949
 950 static int ionic_tx_calc_csum(struct ionic_queue *q, struct sk_buff *skb)
 951 {
 952         struct ionic_txq_desc *desc = q->info[q->head_idx].txq_desc;
 953         struct ionic_tx_stats *stats = q_to_tx_stats(q);
 954         struct device *dev = q->lif->ionic->dev;
 955         dma_addr_t dma_addr;
 956         bool has_vlan;
 957         u8 flags = 0;
 958         bool encap;
 959         u64 cmd;
 960
 961         has_vlan = !!skb_vlan_tag_present(skb);
 962         encap = skb->encapsulation;
 963
 964         dma_addr = ionic_tx_map_single(q, skb->data, skb_headlen(skb));
 965         if (dma_mapping_error(dev, dma_addr))
 966                 return -ENOMEM;
 967
 968         flags |= has_vlan ? IONIC_TXQ_DESC_FLAG_VLAN : 0;
 969         flags |= encap ? IONIC_TXQ_DESC_FLAG_ENCAP : 0;
 970
 971         cmd = encode_txq_desc_cmd(IONIC_TXQ_DESC_OPCODE_CSUM_PARTIAL,
 972                                   flags, skb_shinfo(skb)->nr_frags, dma_addr);
 973         desc->cmd = cpu_to_le64(cmd);
 974         desc->len = cpu_to_le16(skb_headlen(skb));
 975         desc->csum_start = cpu_to_le16(skb_checksum_start_offset(skb));
 976         desc->csum_offset = cpu_to_le16(skb->csum_offset);
 977         if (has_vlan) {
 978                 desc->vlan_tci = cpu_to_le16(skb_vlan_tag_get(skb));
 979                 stats->vlan_inserted++;
 980         }
 981
 982         if (skb_csum_is_sctp(skb))
 983                 stats->crc32_csum++;
 984         else
 985                 stats->csum++;
 986
 987         return 0;
 988 }
 989
 990 static int ionic_tx_calc_no_csum(struct ionic_queue *q, struct sk_buff *skb)
 991 {
 992         struct ionic_txq_desc *desc = q->info[q->head_idx].txq_desc;
 993         struct ionic_tx_stats *stats = q_to_tx_stats(q);
 994         struct device *dev = q->lif->ionic->dev;
 995         dma_addr_t dma_addr;
 996         bool has_vlan;
 997         u8 flags = 0;
 998         bool encap;
 999         u64 cmd;
1000
1001         has_vlan = !!skb_vlan_tag_present(skb);
1002         encap = skb->encapsulation;
1003
1004         dma_addr = ionic_tx_map_single(q, skb->data, skb_headlen(skb));
1005         if (dma_mapping_error(dev, dma_addr))
1006                 return -ENOMEM;
1007
1008         flags |= has_vlan ? IONIC_TXQ_DESC_FLAG_VLAN : 0;
1009         flags |= encap ? IONIC_TXQ_DESC_FLAG_ENCAP : 0;
1010
1011         cmd = encode_txq_desc_cmd(IONIC_TXQ_DESC_OPCODE_CSUM_NONE,
1012                                   flags, skb_shinfo(skb)->nr_frags, dma_addr);
1013         desc->cmd = cpu_to_le64(cmd);
1014         desc->len = cpu_to_le16(skb_headlen(skb));
1015         if (has_vlan) {
1016                 desc->vlan_tci = cpu_to_le16(skb_vlan_tag_get(skb));
1017                 stats->vlan_inserted++;
1018         }
1019
1020         stats->csum_none++;
1021
1022         return 0;
1023 }
1024
1025 static int ionic_tx_skb_frags(struct ionic_queue *q, struct sk_buff *skb)
1026 {
1027         struct ionic_txq_sg_desc *sg_desc = q->info[q->head_idx].txq_sg_desc;
1028         unsigned int len_left = skb->len - skb_headlen(skb);
1029         struct ionic_txq_sg_elem *elem = sg_desc->elems;
1030         struct ionic_tx_stats *stats = q_to_tx_stats(q);
1031         struct device *dev = q->lif->ionic->dev;
1032         dma_addr_t dma_addr;
1033         skb_frag_t *frag;
1034         u16 len;
1035
1036         for (frag = skb_shinfo(skb)->frags; len_left; frag++, elem++) {
1037                 len = skb_frag_size(frag);
1038                 elem->len = cpu_to_le16(len);
1039                 dma_addr = ionic_tx_map_frag(q, frag, 0, len);
1040                 if (dma_mapping_error(dev, dma_addr))
1041                         return -ENOMEM;
1042                 elem->addr = cpu_to_le64(dma_addr);
1043                 len_left -= len;
1044                 stats->frags++;
1045         }
1046
1047         return 0;
1048 }
1049
1050 static int ionic_tx(struct ionic_queue *q, struct sk_buff *skb)
1051 {
1052         struct ionic_tx_stats *stats = q_to_tx_stats(q);
1053         int err;
1054
1055         /* set up the initial descriptor */
1056         if (skb->ip_summed == CHECKSUM_PARTIAL)
1057                 err = ionic_tx_calc_csum(q, skb);
1058         else
1059                 err = ionic_tx_calc_no_csum(q, skb);
1060         if (err)
1061                 return err;
1062
1063         /* add frags */
1064         err = ionic_tx_skb_frags(q, skb);
1065         if (err)
1066                 return err;
1067
1068         skb_tx_timestamp(skb);
1069         stats->pkts++;
1070         stats->bytes += skb->len;
1071
1072         netdev_tx_sent_queue(q_to_ndq(q), skb->len);
1073         ionic_txq_post(q, !netdev_xmit_more(), ionic_tx_clean, skb);
1074
1075         return 0;
1076 }
1077
1078 static int ionic_tx_descs_needed(struct ionic_queue *q, struct sk_buff *skb)
1079 {
1080         int sg_elems = q->lif->qtype_info[IONIC_QTYPE_TXQ].max_sg_elems;
1081         struct ionic_tx_stats *stats = q_to_tx_stats(q);
1082         int err;
1083
1084         /* If TSO, need roundup(skb->len/mss) descs */
1085         if (skb_is_gso(skb))
1086                 return (skb->len / skb_shinfo(skb)->gso_size) + 1;
1087
1088         /* If non-TSO, just need 1 desc and nr_frags sg elems */
1089         if (skb_shinfo(skb)->nr_frags <= sg_elems)
1090                 return 1;
1091
1092         /* Too many frags, so linearize */
1093         err = skb_linearize(skb);
1094         if (err)
1095                 return err;
1096
1097         stats->linearize++;
1098
1099         /* Need 1 desc and zero sg elems */
1100         return 1;
1101 }
1102
1103 static int ionic_maybe_stop_tx(struct ionic_queue *q, int ndescs)
1104 {
1105         int stopped = 0;
1106
1107         if (unlikely(!ionic_q_has_space(q, ndescs))) {
1108                 netif_stop_subqueue(q->lif->netdev, q->index);
1109                 q->stop++;
1110                 stopped = 1;
1111
1112                 /* Might race with ionic_tx_clean, check again */
1113                 smp_rmb();
1114                 if (ionic_q_has_space(q, ndescs)) {
1115                         netif_wake_subqueue(q->lif->netdev, q->index);
1116                         stopped = 0;
1117                 }
1118         }
1119
1120         return stopped;
1121 }
1122
1123 netdev_tx_t ionic_start_xmit(struct sk_buff *skb, struct net_device *netdev)
1124 {
1125         u16 queue_index = skb_get_queue_mapping(skb);
1126         struct ionic_lif *lif = netdev_priv(netdev);
1127         struct ionic_queue *q;
1128         int ndescs;
1129         int err;
1130
1131         if (unlikely(!test_bit(IONIC_LIF_F_UP, lif->state))) {
1132                 dev_kfree_skb(skb);
1133                 return NETDEV_TX_OK;
1134         }
1135
1136         if (unlikely(queue_index >= lif->nxqs))
1137                 queue_index = 0;
1138         q = &lif->txqcqs[queue_index]->q;
1139
1140         ndescs = ionic_tx_descs_needed(q, skb);
1141         if (ndescs < 0)
1142                 goto err_out_drop;
1143
1144         if (unlikely(ionic_maybe_stop_tx(q, ndescs)))
1145                 return NETDEV_TX_BUSY;
1146
1147         if (skb_is_gso(skb))
1148                 err = ionic_tx_tso(q, skb);
1149         else
1150                 err = ionic_tx(q, skb);
1151
1152         if (err)
1153                 goto err_out_drop;
1154
1155         /* Stop the queue if there aren't descriptors for the next packet.
1156          * Since our SG lists per descriptor take care of most of the possible
1157          * fragmentation, we don't need to have many descriptors available.
1158          */
1159         ionic_maybe_stop_tx(q, 4);
1160
1161         return NETDEV_TX_OK;
1162
1163 err_out_drop:
1164         q->stop++;
1165         q->drop++;
1166         dev_kfree_skb(skb);
1167         return NETDEV_TX_OK;
1168 }