1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2017 - 2021 Pensando Systems, Inc */
4 #include <linux/netdevice.h>
5 #include <linux/etherdevice.h>
10 #include "ionic_ethtool.h"
12 static int ionic_hwstamp_tx_mode(int config_tx_type)
14 switch (config_tx_type) {
16 return IONIC_TXSTAMP_OFF;
18 return IONIC_TXSTAMP_ON;
19 case HWTSTAMP_TX_ONESTEP_SYNC:
20 return IONIC_TXSTAMP_ONESTEP_SYNC;
21 case HWTSTAMP_TX_ONESTEP_P2P:
22 return IONIC_TXSTAMP_ONESTEP_P2P;
28 static u64 ionic_hwstamp_rx_filt(int config_rx_filter)
30 switch (config_rx_filter) {
31 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
32 return IONIC_PKT_CLS_PTP1_ALL;
33 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
34 return IONIC_PKT_CLS_PTP1_SYNC;
35 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
36 return IONIC_PKT_CLS_PTP1_SYNC | IONIC_PKT_CLS_PTP1_DREQ;
38 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
39 return IONIC_PKT_CLS_PTP2_L4_ALL;
40 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
41 return IONIC_PKT_CLS_PTP2_L4_SYNC;
42 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
43 return IONIC_PKT_CLS_PTP2_L4_SYNC | IONIC_PKT_CLS_PTP2_L4_DREQ;
45 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
46 return IONIC_PKT_CLS_PTP2_L2_ALL;
47 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
48 return IONIC_PKT_CLS_PTP2_L2_SYNC;
49 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
50 return IONIC_PKT_CLS_PTP2_L2_SYNC | IONIC_PKT_CLS_PTP2_L2_DREQ;
52 case HWTSTAMP_FILTER_PTP_V2_EVENT:
53 return IONIC_PKT_CLS_PTP2_ALL;
54 case HWTSTAMP_FILTER_PTP_V2_SYNC:
55 return IONIC_PKT_CLS_PTP2_SYNC;
56 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
57 return IONIC_PKT_CLS_PTP2_SYNC | IONIC_PKT_CLS_PTP2_DREQ;
59 case HWTSTAMP_FILTER_NTP_ALL:
60 return IONIC_PKT_CLS_NTP_ALL;
67 static int ionic_lif_hwstamp_set_ts_config(struct ionic_lif *lif,
68 struct hwtstamp_config *new_ts)
70 struct ionic *ionic = lif->ionic;
71 struct hwtstamp_config *config;
72 struct hwtstamp_config ts;
79 if (!lif->phc || !lif->phc->ptp)
82 mutex_lock(&lif->phc->config_lock);
87 /* If called with new_ts == NULL, replay the previous request
88 * primarily for recovery after a FW_RESET.
89 * We saved the previous configuration request info, so copy
90 * the previous request for reference, clear the current state
91 * to match the device's reset state, and run with it.
94 memcpy(config, &lif->phc->ts_config, sizeof(*config));
95 memset(&lif->phc->ts_config, 0, sizeof(lif->phc->ts_config));
96 lif->phc->ts_config_tx_mode = 0;
97 lif->phc->ts_config_rx_filt = 0;
100 tx_mode = ionic_hwstamp_tx_mode(config->tx_type);
106 mask = cpu_to_le64(BIT_ULL(tx_mode));
107 if ((ionic->ident.lif.eth.hwstamp_tx_modes & mask) != mask) {
112 rx_filt = ionic_hwstamp_rx_filt(config->rx_filter);
113 rx_all = config->rx_filter != HWTSTAMP_FILTER_NONE && !rx_filt;
115 mask = cpu_to_le64(rx_filt);
116 if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) != mask) {
119 config->rx_filter = HWTSTAMP_FILTER_ALL;
122 dev_dbg(ionic->dev, "%s: config_rx_filter %d rx_filt %#llx rx_all %d\n",
123 __func__, config->rx_filter, rx_filt, rx_all);
126 err = ionic_lif_create_hwstamp_txq(lif);
132 err = ionic_lif_create_hwstamp_rxq(lif);
137 if (tx_mode != lif->phc->ts_config_tx_mode) {
138 err = ionic_lif_set_hwstamp_txmode(lif, tx_mode);
143 if (rx_filt != lif->phc->ts_config_rx_filt) {
144 err = ionic_lif_set_hwstamp_rxfilt(lif, rx_filt);
149 if (rx_all != (lif->phc->ts_config.rx_filter == HWTSTAMP_FILTER_ALL)) {
150 err = ionic_lif_config_hwstamp_rxq_all(lif, rx_all);
155 memcpy(&lif->phc->ts_config, config, sizeof(*config));
156 lif->phc->ts_config_rx_filt = rx_filt;
157 lif->phc->ts_config_tx_mode = tx_mode;
159 mutex_unlock(&lif->phc->config_lock);
164 if (rx_filt != lif->phc->ts_config_rx_filt) {
165 rx_filt = lif->phc->ts_config_rx_filt;
166 err2 = ionic_lif_set_hwstamp_rxfilt(lif, rx_filt);
169 "Failed to revert rx timestamp filter: %d\n", err2);
172 if (tx_mode != lif->phc->ts_config_tx_mode) {
173 tx_mode = lif->phc->ts_config_tx_mode;
174 err2 = ionic_lif_set_hwstamp_txmode(lif, tx_mode);
177 "Failed to revert tx timestamp mode: %d\n", err2);
180 /* special queues remain allocated, just unused */
182 mutex_unlock(&lif->phc->config_lock);
186 int ionic_lif_hwstamp_set(struct ionic_lif *lif, struct ifreq *ifr)
188 struct hwtstamp_config config;
191 if (!lif->phc || !lif->phc->ptp)
194 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
197 mutex_lock(&lif->queue_lock);
198 err = ionic_lif_hwstamp_set_ts_config(lif, &config);
199 mutex_unlock(&lif->queue_lock);
201 netdev_info(lif->netdev, "hwstamp set failed: %d\n", err);
205 if (copy_to_user(ifr->ifr_data, &config, sizeof(config)))
211 void ionic_lif_hwstamp_replay(struct ionic_lif *lif)
215 if (!lif->phc || !lif->phc->ptp)
218 mutex_lock(&lif->queue_lock);
219 err = ionic_lif_hwstamp_set_ts_config(lif, NULL);
220 mutex_unlock(&lif->queue_lock);
222 netdev_info(lif->netdev, "hwstamp replay failed: %d\n", err);
225 int ionic_lif_hwstamp_get(struct ionic_lif *lif, struct ifreq *ifr)
227 struct hwtstamp_config config;
229 if (!lif->phc || !lif->phc->ptp)
232 mutex_lock(&lif->phc->config_lock);
233 memcpy(&config, &lif->phc->ts_config, sizeof(config));
234 mutex_unlock(&lif->phc->config_lock);
236 if (copy_to_user(ifr->ifr_data, &config, sizeof(config)))
241 static u64 ionic_hwstamp_read(struct ionic *ionic,
242 struct ptp_system_timestamp *sts)
244 u32 tick_high_before, tick_high, tick_low;
246 /* read and discard low part to defeat hw staging of high part */
247 (void)ioread32(&ionic->idev.hwstamp_regs->tick_low);
249 tick_high_before = ioread32(&ionic->idev.hwstamp_regs->tick_high);
251 ptp_read_system_prets(sts);
252 tick_low = ioread32(&ionic->idev.hwstamp_regs->tick_low);
253 ptp_read_system_postts(sts);
255 tick_high = ioread32(&ionic->idev.hwstamp_regs->tick_high);
257 /* If tick_high changed, re-read tick_low once more. Assume tick_high
258 * cannot change again so soon as in the span of re-reading tick_low.
260 if (tick_high != tick_high_before) {
261 ptp_read_system_prets(sts);
262 tick_low = ioread32(&ionic->idev.hwstamp_regs->tick_low);
263 ptp_read_system_postts(sts);
266 return (u64)tick_low | ((u64)tick_high << 32);
269 static u64 ionic_cc_read(const struct cyclecounter *cc)
271 struct ionic_phc *phc = container_of(cc, struct ionic_phc, cc);
272 struct ionic *ionic = phc->lif->ionic;
274 return ionic_hwstamp_read(ionic, NULL);
277 static int ionic_setphc_cmd(struct ionic_phc *phc, struct ionic_admin_ctx *ctx)
279 ctx->work = COMPLETION_INITIALIZER_ONSTACK(ctx->work);
281 ctx->cmd.lif_setphc.opcode = IONIC_CMD_LIF_SETPHC;
282 ctx->cmd.lif_setphc.lif_index = cpu_to_le16(phc->lif->index);
284 ctx->cmd.lif_setphc.tick = cpu_to_le64(phc->tc.cycle_last);
285 ctx->cmd.lif_setphc.nsec = cpu_to_le64(phc->tc.nsec);
286 ctx->cmd.lif_setphc.frac = cpu_to_le64(phc->tc.frac);
287 ctx->cmd.lif_setphc.mult = cpu_to_le32(phc->cc.mult);
288 ctx->cmd.lif_setphc.shift = cpu_to_le32(phc->cc.shift);
290 return ionic_adminq_post(phc->lif, ctx);
293 static int ionic_phc_adjfine(struct ptp_clock_info *info, long scaled_ppm)
295 struct ionic_phc *phc = container_of(info, struct ionic_phc, ptp_info);
296 struct ionic_admin_ctx ctx = {};
297 unsigned long irqflags;
301 /* Reject phc adjustments during device upgrade */
302 if (test_bit(IONIC_LIF_F_FW_RESET, phc->lif->state))
305 /* Adjustment value scaled by 2^16 million */
306 adj = (s64)scaled_ppm * phc->init_cc_mult;
308 /* Adjustment value to scale */
309 adj /= (s64)SCALED_PPM;
311 /* Final adjusted multiplier */
312 adj += phc->init_cc_mult;
314 spin_lock_irqsave(&phc->lock, irqflags);
316 /* update the point-in-time basis to now, before adjusting the rate */
317 timecounter_read(&phc->tc);
320 /* Setphc commands are posted in-order, sequenced by phc->lock. We
321 * need to drop the lock before waiting for the command to complete.
323 err = ionic_setphc_cmd(phc, &ctx);
325 spin_unlock_irqrestore(&phc->lock, irqflags);
327 return ionic_adminq_wait(phc->lif, &ctx, err);
330 static int ionic_phc_adjtime(struct ptp_clock_info *info, s64 delta)
332 struct ionic_phc *phc = container_of(info, struct ionic_phc, ptp_info);
333 struct ionic_admin_ctx ctx = {};
334 unsigned long irqflags;
337 /* Reject phc adjustments during device upgrade */
338 if (test_bit(IONIC_LIF_F_FW_RESET, phc->lif->state))
341 spin_lock_irqsave(&phc->lock, irqflags);
343 timecounter_adjtime(&phc->tc, delta);
345 /* Setphc commands are posted in-order, sequenced by phc->lock. We
346 * need to drop the lock before waiting for the command to complete.
348 err = ionic_setphc_cmd(phc, &ctx);
350 spin_unlock_irqrestore(&phc->lock, irqflags);
352 return ionic_adminq_wait(phc->lif, &ctx, err);
355 static int ionic_phc_settime64(struct ptp_clock_info *info,
356 const struct timespec64 *ts)
358 struct ionic_phc *phc = container_of(info, struct ionic_phc, ptp_info);
359 struct ionic_admin_ctx ctx = {};
360 unsigned long irqflags;
364 /* Reject phc adjustments during device upgrade */
365 if (test_bit(IONIC_LIF_F_FW_RESET, phc->lif->state))
368 ns = timespec64_to_ns(ts);
370 spin_lock_irqsave(&phc->lock, irqflags);
372 timecounter_init(&phc->tc, &phc->cc, ns);
374 /* Setphc commands are posted in-order, sequenced by phc->lock. We
375 * need to drop the lock before waiting for the command to complete.
377 err = ionic_setphc_cmd(phc, &ctx);
379 spin_unlock_irqrestore(&phc->lock, irqflags);
381 return ionic_adminq_wait(phc->lif, &ctx, err);
384 static int ionic_phc_gettimex64(struct ptp_clock_info *info,
385 struct timespec64 *ts,
386 struct ptp_system_timestamp *sts)
388 struct ionic_phc *phc = container_of(info, struct ionic_phc, ptp_info);
389 struct ionic *ionic = phc->lif->ionic;
390 unsigned long irqflags;
393 /* Do not attempt to read device time during upgrade */
394 if (test_bit(IONIC_LIF_F_FW_RESET, phc->lif->state))
397 spin_lock_irqsave(&phc->lock, irqflags);
399 tick = ionic_hwstamp_read(ionic, sts);
401 ns = timecounter_cyc2time(&phc->tc, tick);
403 spin_unlock_irqrestore(&phc->lock, irqflags);
405 *ts = ns_to_timespec64(ns);
410 static long ionic_phc_aux_work(struct ptp_clock_info *info)
412 struct ionic_phc *phc = container_of(info, struct ionic_phc, ptp_info);
413 struct ionic_admin_ctx ctx = {};
414 unsigned long irqflags;
417 /* Do not update phc during device upgrade, but keep polling to resume
418 * after upgrade. Since we don't update the point in time basis, there
419 * is no expectation that we are maintaining the phc time during the
420 * upgrade. After upgrade, it will need to be readjusted back to the
421 * correct time by the ptp daemon.
423 if (test_bit(IONIC_LIF_F_FW_RESET, phc->lif->state))
424 return phc->aux_work_delay;
426 spin_lock_irqsave(&phc->lock, irqflags);
428 /* update point-in-time basis to now */
429 timecounter_read(&phc->tc);
431 /* Setphc commands are posted in-order, sequenced by phc->lock. We
432 * need to drop the lock before waiting for the command to complete.
434 err = ionic_setphc_cmd(phc, &ctx);
436 spin_unlock_irqrestore(&phc->lock, irqflags);
438 ionic_adminq_wait(phc->lif, &ctx, err);
440 return phc->aux_work_delay;
443 ktime_t ionic_lif_phc_ktime(struct ionic_lif *lif, u64 tick)
445 unsigned long irqflags;
451 spin_lock_irqsave(&lif->phc->lock, irqflags);
452 ns = timecounter_cyc2time(&lif->phc->tc, tick);
453 spin_unlock_irqrestore(&lif->phc->lock, irqflags);
455 return ns_to_ktime(ns);
458 static const struct ptp_clock_info ionic_ptp_info = {
459 .owner = THIS_MODULE,
461 .adjfine = ionic_phc_adjfine,
462 .adjtime = ionic_phc_adjtime,
463 .gettimex64 = ionic_phc_gettimex64,
464 .settime64 = ionic_phc_settime64,
465 .do_aux_work = ionic_phc_aux_work,
468 void ionic_lif_register_phc(struct ionic_lif *lif)
470 if (!lif->phc || !(lif->hw_features & IONIC_ETH_HW_TIMESTAMP))
473 lif->phc->ptp = ptp_clock_register(&lif->phc->ptp_info, lif->ionic->dev);
475 if (IS_ERR(lif->phc->ptp)) {
476 dev_warn(lif->ionic->dev, "Cannot register phc device: %ld\n",
477 PTR_ERR(lif->phc->ptp));
479 lif->phc->ptp = NULL;
483 ptp_schedule_worker(lif->phc->ptp, lif->phc->aux_work_delay);
486 void ionic_lif_unregister_phc(struct ionic_lif *lif)
488 if (!lif->phc || !lif->phc->ptp)
491 ptp_clock_unregister(lif->phc->ptp);
493 lif->phc->ptp = NULL;
496 void ionic_lif_alloc_phc(struct ionic_lif *lif)
498 struct ionic *ionic = lif->ionic;
499 struct ionic_phc *phc;
500 u64 delay, diff, mult;
505 if (!ionic->idev.hwstamp_regs)
508 features = le64_to_cpu(ionic->ident.lif.eth.config.features);
509 if (!(features & IONIC_ETH_HW_TIMESTAMP))
512 phc = devm_kzalloc(ionic->dev, sizeof(*phc), GFP_KERNEL);
518 phc->cc.read = ionic_cc_read;
519 phc->cc.mask = le64_to_cpu(ionic->ident.dev.hwstamp_mask);
520 phc->cc.mult = le32_to_cpu(ionic->ident.dev.hwstamp_mult);
521 phc->cc.shift = le32_to_cpu(ionic->ident.dev.hwstamp_shift);
524 dev_err(lif->ionic->dev,
525 "Invalid device PHC mask multiplier %u, disabling HW timestamp support\n",
527 devm_kfree(lif->ionic->dev, phc);
532 dev_dbg(lif->ionic->dev, "Device PHC mask %#llx mult %u shift %u\n",
533 phc->cc.mask, phc->cc.mult, phc->cc.shift);
535 spin_lock_init(&phc->lock);
536 mutex_init(&phc->config_lock);
538 /* max ticks is limited by the multiplier, or by the update period. */
539 if (phc->cc.shift + 2 + ilog2(IONIC_PHC_UPDATE_NS) >= 64) {
540 /* max ticks that do not overflow when multiplied by max
541 * adjusted multiplier (twice the initial multiplier)
543 diff = U64_MAX / phc->cc.mult / 2;
545 /* approx ticks at four times the update period */
546 diff = (u64)IONIC_PHC_UPDATE_NS << (phc->cc.shift + 2);
547 diff = DIV_ROUND_UP(diff, phc->cc.mult);
550 /* transform to bitmask */
558 /* constrain to the hardware bitmask, and use this as the bitmask */
559 diff &= phc->cc.mask;
562 /* the wrap period is now defined by diff (or phc->cc.mask)
564 * we will update the time basis at about 1/4 the wrap period, so
565 * should not see a difference of more than +/- diff/4.
567 * this is sufficient not see a difference of more than +/- diff/2, as
568 * required by timecounter_cyc2time, to detect an old time stamp.
570 * adjust the initial multiplier, being careful to avoid overflow:
571 * - do not overflow 63 bits: init_cc_mult * SCALED_PPM
572 * - do not overflow 64 bits: max_mult * (diff / 2)
574 * we want to increase the initial multiplier as much as possible, to
575 * allow for more precise adjustment in ionic_phc_adjfine.
577 * only adjust the multiplier if we can double it or more.
579 mult = U64_MAX / 2 / max(diff / 2, SCALED_PPM);
580 shift = mult / phc->cc.mult;
582 /* initial multiplier will be 2^n of hardware cc.mult */
584 /* increase cc.mult and cc.shift by the same 2^n and n. */
585 phc->cc.mult <<= shift;
586 phc->cc.shift += shift;
589 dev_dbg(lif->ionic->dev, "Initial PHC mask %#llx mult %u shift %u\n",
590 phc->cc.mask, phc->cc.mult, phc->cc.shift);
592 /* frequency adjustments are relative to the initial multiplier */
593 phc->init_cc_mult = phc->cc.mult;
595 timecounter_init(&phc->tc, &phc->cc, ktime_get_real_ns());
597 /* Update cycle_last at 1/4 the wrap period, or IONIC_PHC_UPDATE_NS */
598 delay = min_t(u64, IONIC_PHC_UPDATE_NS,
599 cyclecounter_cyc2ns(&phc->cc, diff / 4, 0, &frac));
600 dev_dbg(lif->ionic->dev, "Work delay %llu ms\n", delay / NSEC_PER_MSEC);
602 phc->aux_work_delay = nsecs_to_jiffies(delay);
604 phc->ptp_info = ionic_ptp_info;
606 /* We have allowed to adjust the multiplier up to +/- 1 part per 1.
607 * Here expressed as NORMAL_PPB (1 billion parts per billion).
609 phc->ptp_info.max_adj = NORMAL_PPB;
614 void ionic_lif_free_phc(struct ionic_lif *lif)
619 mutex_destroy(&lif->phc->config_lock);
621 devm_kfree(lif->ionic->dev, lif->phc);