1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2017 - 2019 Pensando Systems, Inc */
7 #include <linux/ptp_clock_kernel.h>
8 #include <linux/timecounter.h>
9 #include <uapi/linux/net_tstamp.h>
10 #include <linux/dim.h>
11 #include <linux/pci.h>
12 #include "ionic_rx_filter.h"
14 #define IONIC_ADMINQ_LENGTH 16 /* must be a power of two */
15 #define IONIC_NOTIFYQ_LENGTH 64 /* must be a power of two */
17 #define IONIC_MAX_NUM_NAPI_CNTR (NAPI_POLL_WEIGHT + 1)
18 #define IONIC_MAX_NUM_SG_CNTR (IONIC_TX_MAX_SG_ELEMS + 1)
21 #define DEL_ADDR false
22 #define CAN_SLEEP true
23 #define CAN_NOT_SLEEP false
25 #define IONIC_RX_COPYBREAK_DEFAULT 256
26 #define IONIC_TX_BUDGET_DEFAULT 256
28 struct ionic_tx_stats {
40 u64 sg_cntr[IONIC_MAX_NUM_SG_CNTR];
46 struct ionic_rx_stats {
61 #define IONIC_QCQ_F_INITED BIT(0)
62 #define IONIC_QCQ_F_SG BIT(1)
63 #define IONIC_QCQ_F_INTR BIT(2)
64 #define IONIC_QCQ_F_TX_STATS BIT(3)
65 #define IONIC_QCQ_F_RX_STATS BIT(4)
66 #define IONIC_QCQ_F_NOTIFYQ BIT(5)
68 struct ionic_napi_stats {
70 u64 work_done_cntr[IONIC_MAX_NUM_NAPI_CNTR];
78 dma_addr_t cq_base_pa;
81 dma_addr_t sg_base_pa;
86 struct ionic_intr_info intr;
87 struct napi_struct napi;
88 struct ionic_napi_stats napi_stats;
90 struct dentry *dentry;
93 #define q_to_qcq(q) container_of(q, struct ionic_qcq, q)
94 #define q_to_tx_stats(q) (&(q)->lif->txqstats[(q)->index])
95 #define q_to_rx_stats(q) (&(q)->lif->rxqstats[(q)->index])
96 #define napi_to_qcq(napi) container_of(napi, struct ionic_qcq, napi)
97 #define napi_to_cq(napi) (&napi_to_qcq(napi)->cq)
99 enum ionic_deferred_work_type {
100 IONIC_DW_TYPE_RX_MODE,
101 IONIC_DW_TYPE_RX_ADDR_ADD,
102 IONIC_DW_TYPE_RX_ADDR_DEL,
103 IONIC_DW_TYPE_LINK_STATUS,
104 IONIC_DW_TYPE_LIF_RESET,
107 struct ionic_deferred_work {
108 struct list_head list;
109 enum ionic_deferred_work_type type;
116 struct ionic_deferred {
117 spinlock_t lock; /* lock for deferred work list */
118 struct list_head list;
119 struct work_struct work;
122 struct ionic_lif_sw_stats {
132 u64 rx_csum_complete;
134 u64 tx_hwstamp_valid;
135 u64 tx_hwstamp_invalid;
136 u64 rx_hwstamp_valid;
137 u64 rx_hwstamp_invalid;
140 u64 hw_rx_over_errors;
141 u64 hw_rx_missed_errors;
142 u64 hw_tx_aborted_errors;
145 enum ionic_lif_state_flags {
147 IONIC_LIF_F_SW_DEBUG_STATS,
149 IONIC_LIF_F_LINK_CHECK_REQUESTED,
150 IONIC_LIF_F_FW_RESET,
151 IONIC_LIF_F_SPLIT_INTR,
153 IONIC_LIF_F_TX_DIM_INTR,
154 IONIC_LIF_F_RX_DIM_INTR,
156 /* leave this as last */
157 IONIC_LIF_F_STATE_SIZE
160 struct ionic_qtype_info {
173 #define IONIC_LIF_NAME_MAX_SZ 32
175 struct net_device *netdev;
176 DECLARE_BITMAP(state, IONIC_LIF_F_STATE_SIZE);
179 unsigned int hw_index;
180 struct mutex queue_lock; /* lock for queue structures */
181 struct mutex config_lock; /* lock for config actions */
182 spinlock_t adminq_lock; /* lock for AdminQ operations */
183 struct ionic_qcq *adminqcq;
184 struct ionic_qcq *notifyqcq;
185 struct ionic_qcq **txqcqs;
186 struct ionic_qcq *hwstamp_txq;
187 struct ionic_tx_stats *txqstats;
188 struct ionic_qcq **rxqcqs;
189 struct ionic_qcq *hwstamp_rxq;
190 struct ionic_rx_stats *rxqstats;
191 struct ionic_deferred deferred;
192 struct work_struct tx_timeout_work;
194 unsigned int kern_pid;
195 u64 __iomem *kern_dbpage;
198 unsigned int ntxq_descs;
199 unsigned int nrxq_descs;
210 char name[IONIC_LIF_NAME_MAX_SZ];
212 union ionic_lif_identity *identity;
213 struct ionic_lif_info *info;
216 struct ionic_qtype_info qtype_info[IONIC_QTYPE_MAX];
219 u8 rss_hash_key[IONIC_RSS_HASH_KEY_SIZE];
221 dma_addr_t rss_ind_tbl_pa;
224 struct ionic_rx_filters rx_filters;
225 u32 rx_coalesce_usecs; /* what the user asked for */
226 u32 rx_coalesce_hw; /* what the hw is using */
227 u32 tx_coalesce_usecs; /* what the user asked for */
228 u32 tx_coalesce_hw; /* what the hw is using */
229 unsigned long *dbid_inuse;
230 unsigned int dbid_count;
232 struct ionic_phc *phc;
234 struct dentry *dentry;
238 spinlock_t lock; /* lock for cc and tc */
239 struct cyclecounter cc;
240 struct timecounter tc;
242 struct mutex config_lock; /* lock for ts_config */
243 struct hwtstamp_config ts_config;
244 u64 ts_config_rx_filt;
245 u32 ts_config_tx_mode;
250 struct ptp_clock_info ptp_info;
251 struct ptp_clock *ptp;
252 struct ionic_lif *lif;
255 struct ionic_queue_params {
257 unsigned int ntxq_descs;
258 unsigned int nrxq_descs;
259 unsigned int intr_split;
263 static inline void ionic_init_queue_params(struct ionic_lif *lif,
264 struct ionic_queue_params *qparam)
266 qparam->nxqs = lif->nxqs;
267 qparam->ntxq_descs = lif->ntxq_descs;
268 qparam->nrxq_descs = lif->nrxq_descs;
269 qparam->intr_split = test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state);
270 qparam->rxq_features = lif->rxq_features;
273 static inline u32 ionic_coal_usec_to_hw(struct ionic *ionic, u32 usecs)
275 u32 mult = le32_to_cpu(ionic->ident.dev.intr_coal_mult);
276 u32 div = le32_to_cpu(ionic->ident.dev.intr_coal_div);
278 /* Div-by-zero should never be an issue, but check anyway */
282 /* Round up in case usecs is close to the next hw unit */
283 usecs += (div / mult) >> 1;
285 /* Convert from usecs to device units */
286 return (usecs * mult) / div;
289 void ionic_link_status_check_request(struct ionic_lif *lif, bool can_sleep);
290 void ionic_get_stats64(struct net_device *netdev,
291 struct rtnl_link_stats64 *ns);
292 void ionic_lif_deferred_enqueue(struct ionic_deferred *def,
293 struct ionic_deferred_work *work);
294 int ionic_lif_alloc(struct ionic *ionic);
295 int ionic_lif_init(struct ionic_lif *lif);
296 void ionic_lif_free(struct ionic_lif *lif);
297 void ionic_lif_deinit(struct ionic_lif *lif);
298 int ionic_lif_register(struct ionic_lif *lif);
299 void ionic_lif_unregister(struct ionic_lif *lif);
300 int ionic_lif_identify(struct ionic *ionic, u8 lif_type,
301 union ionic_lif_identity *lif_ident);
302 int ionic_lif_size(struct ionic *ionic);
304 #if IS_ENABLED(CONFIG_PTP_1588_CLOCK)
305 void ionic_lif_hwstamp_replay(struct ionic_lif *lif);
306 int ionic_lif_hwstamp_set(struct ionic_lif *lif, struct ifreq *ifr);
307 int ionic_lif_hwstamp_get(struct ionic_lif *lif, struct ifreq *ifr);
308 ktime_t ionic_lif_phc_ktime(struct ionic_lif *lif, u64 counter);
309 void ionic_lif_register_phc(struct ionic_lif *lif);
310 void ionic_lif_unregister_phc(struct ionic_lif *lif);
311 void ionic_lif_alloc_phc(struct ionic_lif *lif);
312 void ionic_lif_free_phc(struct ionic_lif *lif);
314 static inline void ionic_lif_hwstamp_replay(struct ionic_lif *lif) {}
316 static inline int ionic_lif_hwstamp_set(struct ionic_lif *lif, struct ifreq *ifr)
321 static inline int ionic_lif_hwstamp_get(struct ionic_lif *lif, struct ifreq *ifr)
326 static inline ktime_t ionic_lif_phc_ktime(struct ionic_lif *lif, u64 counter)
328 return ns_to_ktime(0);
331 static inline void ionic_lif_register_phc(struct ionic_lif *lif) {}
332 static inline void ionic_lif_unregister_phc(struct ionic_lif *lif) {}
333 static inline void ionic_lif_alloc_phc(struct ionic_lif *lif) {}
334 static inline void ionic_lif_free_phc(struct ionic_lif *lif) {}
337 int ionic_lif_create_hwstamp_txq(struct ionic_lif *lif);
338 int ionic_lif_create_hwstamp_rxq(struct ionic_lif *lif);
339 int ionic_lif_config_hwstamp_rxq_all(struct ionic_lif *lif, bool rx_all);
340 int ionic_lif_set_hwstamp_txmode(struct ionic_lif *lif, u16 txstamp_mode);
341 int ionic_lif_set_hwstamp_rxfilt(struct ionic_lif *lif, u64 pkt_class);
343 int ionic_lif_rss_config(struct ionic_lif *lif, u16 types,
344 const u8 *key, const u32 *indir);
345 int ionic_reconfigure_queues(struct ionic_lif *lif,
346 struct ionic_queue_params *qparam);
348 static inline void debug_stats_txq_post(struct ionic_queue *q, bool dbell)
350 struct ionic_txq_desc *desc = &q->txq[q->head_idx];
353 q->dbell_count += dbell;
355 num_sg_elems = ((le64_to_cpu(desc->cmd) >> IONIC_TXQ_DESC_NSGE_SHIFT)
356 & IONIC_TXQ_DESC_NSGE_MASK);
357 if (num_sg_elems > (IONIC_MAX_NUM_SG_CNTR - 1))
358 num_sg_elems = IONIC_MAX_NUM_SG_CNTR - 1;
360 q->lif->txqstats[q->index].sg_cntr[num_sg_elems]++;
363 static inline void debug_stats_napi_poll(struct ionic_qcq *qcq,
364 unsigned int work_done)
366 qcq->napi_stats.poll_count++;
368 if (work_done > (IONIC_MAX_NUM_NAPI_CNTR - 1))
369 work_done = IONIC_MAX_NUM_NAPI_CNTR - 1;
371 qcq->napi_stats.work_done_cntr[work_done]++;
374 #define DEBUG_STATS_CQE_CNT(cq) ((cq)->compl_count++)
375 #define DEBUG_STATS_RX_BUFF_CNT(q) ((q)->lif->rxqstats[q->index].buffers_posted++)
376 #define DEBUG_STATS_TXQ_POST(q, dbell) debug_stats_txq_post(q, dbell)
377 #define DEBUG_STATS_NAPI_POLL(qcq, work_done) \
378 debug_stats_napi_poll(qcq, work_done)
380 #endif /* _IONIC_LIF_H_ */