1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2 /* Copyright (C) 2015-2018 Netronome Systems, Inc. */
5 * Netronome network device driver: Control BAR layout
6 * Authors: Jakub Kicinski <jakub.kicinski@netronome.com>
7 * Jason McMullan <jason.mcmullan@netronome.com>
8 * Rolf Neugebauer <rolf.neugebauer@netronome.com>
9 * Brad Petrus <brad.petrus@netronome.com>
12 #ifndef _NFP_NET_CTRL_H_
13 #define _NFP_NET_CTRL_H_
15 #include <linux/types.h>
17 /* Configuration BAR size.
19 * The configuration BAR is 8K in size, but due to
20 * THB-350, 32k needs to be reserved.
22 #define NFP_NET_CFG_BAR_SZ (32 * 1024)
24 /* Offset in Freelist buffer where packet starts on RX */
25 #define NFP_NET_RX_OFFSET 32
28 * %NFP_NET_LSO_MAX_HDR_SZ: Maximum header size supported for LSO frames
29 * %NFP_NET_LSO_MAX_SEGS: Maximum number of segments LSO frame can produce
31 #define NFP_NET_LSO_MAX_HDR_SZ 255
32 #define NFP_NET_LSO_MAX_SEGS 64
34 /* Prepend field types */
35 #define NFP_NET_META_FIELD_SIZE 4
36 #define NFP_NET_META_HASH 1 /* next field carries hash type */
37 #define NFP_NET_META_MARK 2
38 #define NFP_NET_META_PORTID 5
39 #define NFP_NET_META_CSUM 6 /* checksum complete type */
40 #define NFP_NET_META_CONN_HANDLE 7
41 #define NFP_NET_META_RESYNC_INFO 8 /* RX resync info request */
43 #define NFP_META_PORT_ID_CTRL ~0U
45 /* Hash type pre-pended when a RSS hash was computed */
46 #define NFP_NET_RSS_NONE 0
47 #define NFP_NET_RSS_IPV4 1
48 #define NFP_NET_RSS_IPV6 2
49 #define NFP_NET_RSS_IPV6_EX 3
50 #define NFP_NET_RSS_IPV4_TCP 4
51 #define NFP_NET_RSS_IPV6_TCP 5
52 #define NFP_NET_RSS_IPV6_EX_TCP 6
53 #define NFP_NET_RSS_IPV4_UDP 7
54 #define NFP_NET_RSS_IPV6_UDP 8
55 #define NFP_NET_RSS_IPV6_EX_UDP 9
58 * %NFP_NET_TXR_MAX: Maximum number of TX rings
59 * %NFP_NET_RXR_MAX: Maximum number of RX rings
61 #define NFP_NET_TXR_MAX 64
62 #define NFP_NET_RXR_MAX 64
64 /* Read/Write config words (0x0000 - 0x002c)
65 * %NFP_NET_CFG_CTRL: Global control
66 * %NFP_NET_CFG_UPDATE: Indicate which fields are updated
67 * %NFP_NET_CFG_TXRS_ENABLE: Bitmask of enabled TX rings
68 * %NFP_NET_CFG_RXRS_ENABLE: Bitmask of enabled RX rings
69 * %NFP_NET_CFG_MTU: Set MTU size
70 * %NFP_NET_CFG_FLBUFSZ: Set freelist buffer size (must be larger than MTU)
71 * %NFP_NET_CFG_EXN: MSI-X table entry for exceptions
72 * %NFP_NET_CFG_LSC: MSI-X table entry for link state changes
73 * %NFP_NET_CFG_MACADDR: MAC address
76 * - define Error details in UPDATE
78 #define NFP_NET_CFG_CTRL 0x0000
79 #define NFP_NET_CFG_CTRL_ENABLE (0x1 << 0) /* Global enable */
80 #define NFP_NET_CFG_CTRL_PROMISC (0x1 << 1) /* Enable Promisc mode */
81 #define NFP_NET_CFG_CTRL_L2BC (0x1 << 2) /* Allow L2 Broadcast */
82 #define NFP_NET_CFG_CTRL_L2MC (0x1 << 3) /* Allow L2 Multicast */
83 #define NFP_NET_CFG_CTRL_RXCSUM (0x1 << 4) /* Enable RX Checksum */
84 #define NFP_NET_CFG_CTRL_TXCSUM (0x1 << 5) /* Enable TX Checksum */
85 #define NFP_NET_CFG_CTRL_RXVLAN (0x1 << 6) /* Enable VLAN strip */
86 #define NFP_NET_CFG_CTRL_TXVLAN (0x1 << 7) /* Enable VLAN insert */
87 #define NFP_NET_CFG_CTRL_SCATTER (0x1 << 8) /* Scatter DMA */
88 #define NFP_NET_CFG_CTRL_GATHER (0x1 << 9) /* Gather DMA */
89 #define NFP_NET_CFG_CTRL_LSO (0x1 << 10) /* LSO/TSO (version 1) */
90 #define NFP_NET_CFG_CTRL_CTAG_FILTER (0x1 << 11) /* VLAN CTAG filtering */
91 #define NFP_NET_CFG_CTRL_CMSG_DATA (0x1 << 12) /* RX cmsgs on data Qs */
92 #define NFP_NET_CFG_CTRL_RINGCFG (0x1 << 16) /* Ring runtime changes */
93 #define NFP_NET_CFG_CTRL_RSS (0x1 << 17) /* RSS (version 1) */
94 #define NFP_NET_CFG_CTRL_IRQMOD (0x1 << 18) /* Interrupt moderation */
95 #define NFP_NET_CFG_CTRL_MSIXAUTO (0x1 << 20) /* MSI-X auto-masking */
96 #define NFP_NET_CFG_CTRL_TXRWB (0x1 << 21) /* Write-back of TX ring*/
97 #define NFP_NET_CFG_CTRL_VXLAN (0x1 << 24) /* VXLAN tunnel support */
98 #define NFP_NET_CFG_CTRL_NVGRE (0x1 << 25) /* NVGRE tunnel support */
99 #define NFP_NET_CFG_CTRL_BPF (0x1 << 27) /* BPF offload capable */
100 #define NFP_NET_CFG_CTRL_LSO2 (0x1 << 28) /* LSO/TSO (version 2) */
101 #define NFP_NET_CFG_CTRL_RSS2 (0x1 << 29) /* RSS (version 2) */
102 #define NFP_NET_CFG_CTRL_CSUM_COMPLETE (0x1 << 30) /* Checksum complete */
103 #define NFP_NET_CFG_CTRL_LIVE_ADDR (0x1 << 31) /* live MAC addr change */
105 #define NFP_NET_CFG_CTRL_LSO_ANY (NFP_NET_CFG_CTRL_LSO | \
106 NFP_NET_CFG_CTRL_LSO2)
107 #define NFP_NET_CFG_CTRL_RSS_ANY (NFP_NET_CFG_CTRL_RSS | \
108 NFP_NET_CFG_CTRL_RSS2)
109 #define NFP_NET_CFG_CTRL_RXCSUM_ANY (NFP_NET_CFG_CTRL_RXCSUM | \
110 NFP_NET_CFG_CTRL_CSUM_COMPLETE)
111 #define NFP_NET_CFG_CTRL_CHAIN_META (NFP_NET_CFG_CTRL_RSS2 | \
112 NFP_NET_CFG_CTRL_CSUM_COMPLETE)
114 #define NFP_NET_CFG_UPDATE 0x0004
115 #define NFP_NET_CFG_UPDATE_GEN (0x1 << 0) /* General update */
116 #define NFP_NET_CFG_UPDATE_RING (0x1 << 1) /* Ring config change */
117 #define NFP_NET_CFG_UPDATE_RSS (0x1 << 2) /* RSS config change */
118 #define NFP_NET_CFG_UPDATE_TXRPRIO (0x1 << 3) /* TX Ring prio change */
119 #define NFP_NET_CFG_UPDATE_RXRPRIO (0x1 << 4) /* RX Ring prio change */
120 #define NFP_NET_CFG_UPDATE_MSIX (0x1 << 5) /* MSI-X change */
121 #define NFP_NET_CFG_UPDATE_RESET (0x1 << 7) /* Update due to FLR */
122 #define NFP_NET_CFG_UPDATE_IRQMOD (0x1 << 8) /* IRQ mod change */
123 #define NFP_NET_CFG_UPDATE_VXLAN (0x1 << 9) /* VXLAN port change */
124 #define NFP_NET_CFG_UPDATE_BPF (0x1 << 10) /* BPF program load */
125 #define NFP_NET_CFG_UPDATE_MACADDR (0x1 << 11) /* MAC address change */
126 #define NFP_NET_CFG_UPDATE_MBOX (0x1 << 12) /* Mailbox update */
127 #define NFP_NET_CFG_UPDATE_VF (0x1 << 13) /* VF settings change */
128 #define NFP_NET_CFG_UPDATE_CRYPTO (0x1 << 14) /* Crypto on/off */
129 #define NFP_NET_CFG_UPDATE_ERR (0x1 << 31) /* A error occurred */
130 #define NFP_NET_CFG_TXRS_ENABLE 0x0008
131 #define NFP_NET_CFG_RXRS_ENABLE 0x0010
132 #define NFP_NET_CFG_MTU 0x0018
133 #define NFP_NET_CFG_FLBUFSZ 0x001c
134 #define NFP_NET_CFG_EXN 0x001f
135 #define NFP_NET_CFG_LSC 0x0020
136 #define NFP_NET_CFG_MACADDR 0x0024
138 /* Read-only words (0x0030 - 0x0050):
139 * %NFP_NET_CFG_VERSION: Firmware version number
140 * %NFP_NET_CFG_STS: Status
141 * %NFP_NET_CFG_CAP: Capabilities (same bits as %NFP_NET_CFG_CTRL)
142 * %NFP_NET_CFG_MAX_TXRINGS: Maximum number of TX rings
143 * %NFP_NET_CFG_MAX_RXRINGS: Maximum number of RX rings
144 * %NFP_NET_CFG_MAX_MTU: Maximum support MTU
145 * %NFP_NET_CFG_START_TXQ: Start Queue Control Queue to use for TX (PF only)
146 * %NFP_NET_CFG_START_RXQ: Start Queue Control Queue to use for RX (PF only)
149 * - define more STS bits
151 #define NFP_NET_CFG_VERSION 0x0030
152 #define NFP_NET_CFG_VERSION_RESERVED_MASK (0xff << 24)
153 #define NFP_NET_CFG_VERSION_CLASS_MASK (0xff << 16)
154 #define NFP_NET_CFG_VERSION_CLASS(x) (((x) & 0xff) << 16)
155 #define NFP_NET_CFG_VERSION_CLASS_GENERIC 0
156 #define NFP_NET_CFG_VERSION_MAJOR_MASK (0xff << 8)
157 #define NFP_NET_CFG_VERSION_MAJOR(x) (((x) & 0xff) << 8)
158 #define NFP_NET_CFG_VERSION_MINOR_MASK (0xff << 0)
159 #define NFP_NET_CFG_VERSION_MINOR(x) (((x) & 0xff) << 0)
160 #define NFP_NET_CFG_STS 0x0034
161 #define NFP_NET_CFG_STS_LINK (0x1 << 0) /* Link up or down */
163 #define NFP_NET_CFG_STS_LINK_RATE_SHIFT 1
164 #define NFP_NET_CFG_STS_LINK_RATE_MASK 0xF
165 #define NFP_NET_CFG_STS_LINK_RATE \
166 (NFP_NET_CFG_STS_LINK_RATE_MASK << NFP_NET_CFG_STS_LINK_RATE_SHIFT)
167 #define NFP_NET_CFG_STS_LINK_RATE_UNSUPPORTED 0
168 #define NFP_NET_CFG_STS_LINK_RATE_UNKNOWN 1
169 #define NFP_NET_CFG_STS_LINK_RATE_1G 2
170 #define NFP_NET_CFG_STS_LINK_RATE_10G 3
171 #define NFP_NET_CFG_STS_LINK_RATE_25G 4
172 #define NFP_NET_CFG_STS_LINK_RATE_40G 5
173 #define NFP_NET_CFG_STS_LINK_RATE_50G 6
174 #define NFP_NET_CFG_STS_LINK_RATE_100G 7
175 #define NFP_NET_CFG_CAP 0x0038
176 #define NFP_NET_CFG_MAX_TXRINGS 0x003c
177 #define NFP_NET_CFG_MAX_RXRINGS 0x0040
178 #define NFP_NET_CFG_MAX_MTU 0x0044
179 /* Next two words are being used by VFs for solving THB350 issue */
180 #define NFP_NET_CFG_START_TXQ 0x0048
181 #define NFP_NET_CFG_START_RXQ 0x004c
183 /* Prepend configuration
185 #define NFP_NET_CFG_RX_OFFSET 0x0050
186 #define NFP_NET_CFG_RX_OFFSET_DYNAMIC 0 /* Prepend mode */
189 * %NFP_NET_CFG_RSS_CAP_HFUNC: supported hash functions (same bits as
190 * %NFP_NET_CFG_RSS_HFUNC)
192 #define NFP_NET_CFG_RSS_CAP 0x0054
193 #define NFP_NET_CFG_RSS_CAP_HFUNC 0xff000000
196 * %NFP_NET_CFG_TLV_BASE: start anchor of the TLV area
198 #define NFP_NET_CFG_TLV_BASE 0x0058
200 /* VXLAN/UDP encap configuration
201 * %NFP_NET_CFG_VXLAN_PORT: Base address of table of tunnels' UDP dst ports
202 * %NFP_NET_CFG_VXLAN_SZ: Size of the UDP port table in bytes
204 #define NFP_NET_CFG_VXLAN_PORT 0x0060
205 #define NFP_NET_CFG_VXLAN_SZ 0x0008
208 * %NFP_NET_CFG_BPF_ABI: BPF ABI version
209 * %NFP_NET_CFG_BPF_CAP: BPF capabilities
210 * %NFP_NET_CFG_BPF_MAX_LEN: Maximum size of JITed BPF code in bytes
211 * %NFP_NET_CFG_BPF_START: Offset at which BPF will be loaded
212 * %NFP_NET_CFG_BPF_DONE: Offset to jump to on exit
213 * %NFP_NET_CFG_BPF_STACK_SZ: Total size of stack area in 64B chunks
214 * %NFP_NET_CFG_BPF_INL_MTU: Packet data split offset in 64B chunks
215 * %NFP_NET_CFG_BPF_SIZE: Size of the JITed BPF code in instructions
216 * %NFP_NET_CFG_BPF_ADDR: DMA address of the buffer with JITed BPF code
218 #define NFP_NET_CFG_BPF_ABI 0x0080
219 #define NFP_NET_CFG_BPF_CAP 0x0081
220 #define NFP_NET_BPF_CAP_RELO (1 << 0) /* seamless reload */
221 #define NFP_NET_CFG_BPF_MAX_LEN 0x0082
222 #define NFP_NET_CFG_BPF_START 0x0084
223 #define NFP_NET_CFG_BPF_DONE 0x0086
224 #define NFP_NET_CFG_BPF_STACK_SZ 0x0088
225 #define NFP_NET_CFG_BPF_INL_MTU 0x0089
226 #define NFP_NET_CFG_BPF_SIZE 0x008e
227 #define NFP_NET_CFG_BPF_ADDR 0x0090
228 #define NFP_NET_CFG_BPF_CFG_8CTX (1 << 0) /* 8ctx mode */
229 #define NFP_NET_CFG_BPF_CFG_MASK 7ULL
230 #define NFP_NET_CFG_BPF_ADDR_MASK (~NFP_NET_CFG_BPF_CFG_MASK)
232 /* 40B reserved for future use (0x0098 - 0x00c0)
234 #define NFP_NET_CFG_RESERVED 0x0098
235 #define NFP_NET_CFG_RESERVED_SZ 0x0028
237 /* RSS configuration (0x0100 - 0x01ac):
238 * Used only when NFP_NET_CFG_CTRL_RSS is enabled
239 * %NFP_NET_CFG_RSS_CFG: RSS configuration word
240 * %NFP_NET_CFG_RSS_KEY: RSS "secret" key
241 * %NFP_NET_CFG_RSS_ITBL: RSS indirection table
243 #define NFP_NET_CFG_RSS_BASE 0x0100
244 #define NFP_NET_CFG_RSS_CTRL NFP_NET_CFG_RSS_BASE
245 #define NFP_NET_CFG_RSS_MASK (0x7f)
246 #define NFP_NET_CFG_RSS_MASK_of(_x) ((_x) & 0x7f)
247 #define NFP_NET_CFG_RSS_IPV4 (1 << 8) /* RSS for IPv4 */
248 #define NFP_NET_CFG_RSS_IPV6 (1 << 9) /* RSS for IPv6 */
249 #define NFP_NET_CFG_RSS_IPV4_TCP (1 << 10) /* RSS for IPv4/TCP */
250 #define NFP_NET_CFG_RSS_IPV4_UDP (1 << 11) /* RSS for IPv4/UDP */
251 #define NFP_NET_CFG_RSS_IPV6_TCP (1 << 12) /* RSS for IPv6/TCP */
252 #define NFP_NET_CFG_RSS_IPV6_UDP (1 << 13) /* RSS for IPv6/UDP */
253 #define NFP_NET_CFG_RSS_HFUNC 0xff000000
254 #define NFP_NET_CFG_RSS_TOEPLITZ (1 << 24) /* Use Toeplitz hash */
255 #define NFP_NET_CFG_RSS_XOR (1 << 25) /* Use XOR as hash */
256 #define NFP_NET_CFG_RSS_CRC32 (1 << 26) /* Use CRC32 as hash */
257 #define NFP_NET_CFG_RSS_HFUNCS 3
258 #define NFP_NET_CFG_RSS_KEY (NFP_NET_CFG_RSS_BASE + 0x4)
259 #define NFP_NET_CFG_RSS_KEY_SZ 0x28
260 #define NFP_NET_CFG_RSS_ITBL (NFP_NET_CFG_RSS_BASE + 0x4 + \
261 NFP_NET_CFG_RSS_KEY_SZ)
262 #define NFP_NET_CFG_RSS_ITBL_SZ 0x80
264 /* TX ring configuration (0x200 - 0x800)
265 * %NFP_NET_CFG_TXR_BASE: Base offset for TX ring configuration
266 * %NFP_NET_CFG_TXR_ADDR: Per TX ring DMA address (8B entries)
267 * %NFP_NET_CFG_TXR_WB_ADDR: Per TX ring write back DMA address (8B entries)
268 * %NFP_NET_CFG_TXR_SZ: Per TX ring ring size (1B entries)
269 * %NFP_NET_CFG_TXR_VEC: Per TX ring MSI-X table entry (1B entries)
270 * %NFP_NET_CFG_TXR_PRIO: Per TX ring priority (1B entries)
271 * %NFP_NET_CFG_TXR_IRQ_MOD: Per TX ring interrupt moderation packet
273 #define NFP_NET_CFG_TXR_BASE 0x0200
274 #define NFP_NET_CFG_TXR_ADDR(_x) (NFP_NET_CFG_TXR_BASE + ((_x) * 0x8))
275 #define NFP_NET_CFG_TXR_WB_ADDR(_x) (NFP_NET_CFG_TXR_BASE + 0x200 + \
277 #define NFP_NET_CFG_TXR_SZ(_x) (NFP_NET_CFG_TXR_BASE + 0x400 + (_x))
278 #define NFP_NET_CFG_TXR_VEC(_x) (NFP_NET_CFG_TXR_BASE + 0x440 + (_x))
279 #define NFP_NET_CFG_TXR_PRIO(_x) (NFP_NET_CFG_TXR_BASE + 0x480 + (_x))
280 #define NFP_NET_CFG_TXR_IRQ_MOD(_x) (NFP_NET_CFG_TXR_BASE + 0x500 + \
283 /* RX ring configuration (0x0800 - 0x0c00)
284 * %NFP_NET_CFG_RXR_BASE: Base offset for RX ring configuration
285 * %NFP_NET_CFG_RXR_ADDR: Per RX ring DMA address (8B entries)
286 * %NFP_NET_CFG_RXR_SZ: Per RX ring ring size (1B entries)
287 * %NFP_NET_CFG_RXR_VEC: Per RX ring MSI-X table entry (1B entries)
288 * %NFP_NET_CFG_RXR_PRIO: Per RX ring priority (1B entries)
289 * %NFP_NET_CFG_RXR_IRQ_MOD: Per RX ring interrupt moderation (4B entries)
291 #define NFP_NET_CFG_RXR_BASE 0x0800
292 #define NFP_NET_CFG_RXR_ADDR(_x) (NFP_NET_CFG_RXR_BASE + ((_x) * 0x8))
293 #define NFP_NET_CFG_RXR_SZ(_x) (NFP_NET_CFG_RXR_BASE + 0x200 + (_x))
294 #define NFP_NET_CFG_RXR_VEC(_x) (NFP_NET_CFG_RXR_BASE + 0x240 + (_x))
295 #define NFP_NET_CFG_RXR_PRIO(_x) (NFP_NET_CFG_RXR_BASE + 0x280 + (_x))
296 #define NFP_NET_CFG_RXR_IRQ_MOD(_x) (NFP_NET_CFG_RXR_BASE + 0x300 + \
299 /* Interrupt Control/Cause registers (0x0c00 - 0x0d00)
300 * These registers are only used when MSI-X auto-masking is not
301 * enabled (%NFP_NET_CFG_CTRL_MSIXAUTO not set). The array is index
302 * by MSI-X entry and are 1B in size. If an entry is zero, the
303 * corresponding entry is enabled. If the FW generates an interrupt,
304 * it writes a cause into the corresponding field. This also masks
305 * the MSI-X entry and the host driver must clear the register to
306 * re-enable the interrupt.
308 #define NFP_NET_CFG_ICR_BASE 0x0c00
309 #define NFP_NET_CFG_ICR(_x) (NFP_NET_CFG_ICR_BASE + (_x))
310 #define NFP_NET_CFG_ICR_UNMASKED 0x0
311 #define NFP_NET_CFG_ICR_RXTX 0x1
312 #define NFP_NET_CFG_ICR_LSC 0x2
314 /* General device stats (0x0d00 - 0x0d90)
315 * all counters are 64bit.
317 #define NFP_NET_CFG_STATS_BASE 0x0d00
318 #define NFP_NET_CFG_STATS_RX_DISCARDS (NFP_NET_CFG_STATS_BASE + 0x00)
319 #define NFP_NET_CFG_STATS_RX_ERRORS (NFP_NET_CFG_STATS_BASE + 0x08)
320 #define NFP_NET_CFG_STATS_RX_OCTETS (NFP_NET_CFG_STATS_BASE + 0x10)
321 #define NFP_NET_CFG_STATS_RX_UC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x18)
322 #define NFP_NET_CFG_STATS_RX_MC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x20)
323 #define NFP_NET_CFG_STATS_RX_BC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x28)
324 #define NFP_NET_CFG_STATS_RX_FRAMES (NFP_NET_CFG_STATS_BASE + 0x30)
325 #define NFP_NET_CFG_STATS_RX_MC_FRAMES (NFP_NET_CFG_STATS_BASE + 0x38)
326 #define NFP_NET_CFG_STATS_RX_BC_FRAMES (NFP_NET_CFG_STATS_BASE + 0x40)
328 #define NFP_NET_CFG_STATS_TX_DISCARDS (NFP_NET_CFG_STATS_BASE + 0x48)
329 #define NFP_NET_CFG_STATS_TX_ERRORS (NFP_NET_CFG_STATS_BASE + 0x50)
330 #define NFP_NET_CFG_STATS_TX_OCTETS (NFP_NET_CFG_STATS_BASE + 0x58)
331 #define NFP_NET_CFG_STATS_TX_UC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x60)
332 #define NFP_NET_CFG_STATS_TX_MC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x68)
333 #define NFP_NET_CFG_STATS_TX_BC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x70)
334 #define NFP_NET_CFG_STATS_TX_FRAMES (NFP_NET_CFG_STATS_BASE + 0x78)
335 #define NFP_NET_CFG_STATS_TX_MC_FRAMES (NFP_NET_CFG_STATS_BASE + 0x80)
336 #define NFP_NET_CFG_STATS_TX_BC_FRAMES (NFP_NET_CFG_STATS_BASE + 0x88)
338 #define NFP_NET_CFG_STATS_APP0_FRAMES (NFP_NET_CFG_STATS_BASE + 0x90)
339 #define NFP_NET_CFG_STATS_APP0_BYTES (NFP_NET_CFG_STATS_BASE + 0x98)
340 #define NFP_NET_CFG_STATS_APP1_FRAMES (NFP_NET_CFG_STATS_BASE + 0xa0)
341 #define NFP_NET_CFG_STATS_APP1_BYTES (NFP_NET_CFG_STATS_BASE + 0xa8)
342 #define NFP_NET_CFG_STATS_APP2_FRAMES (NFP_NET_CFG_STATS_BASE + 0xb0)
343 #define NFP_NET_CFG_STATS_APP2_BYTES (NFP_NET_CFG_STATS_BASE + 0xb8)
344 #define NFP_NET_CFG_STATS_APP3_FRAMES (NFP_NET_CFG_STATS_BASE + 0xc0)
345 #define NFP_NET_CFG_STATS_APP3_BYTES (NFP_NET_CFG_STATS_BASE + 0xc8)
347 /* Per ring stats (0x1000 - 0x1800)
348 * options, 64bit per entry
349 * %NFP_NET_CFG_TXR_STATS: TX ring statistics (Packet and Byte count)
350 * %NFP_NET_CFG_RXR_STATS: RX ring statistics (Packet and Byte count)
352 #define NFP_NET_CFG_TXR_STATS_BASE 0x1000
353 #define NFP_NET_CFG_TXR_STATS(_x) (NFP_NET_CFG_TXR_STATS_BASE + \
355 #define NFP_NET_CFG_RXR_STATS_BASE 0x1400
356 #define NFP_NET_CFG_RXR_STATS(_x) (NFP_NET_CFG_RXR_STATS_BASE + \
359 /* General use mailbox area (0x1800 - 0x19ff)
360 * 4B used for update command and 4B return code
361 * followed by a max of 504B of variable length value
363 #define NFP_NET_CFG_MBOX_BASE 0x1800
364 #define NFP_NET_CFG_MBOX_VAL_MAX_SZ 0x1F8
366 #define NFP_NET_CFG_MBOX_SIMPLE_CMD 0x0
367 #define NFP_NET_CFG_MBOX_SIMPLE_RET 0x4
368 #define NFP_NET_CFG_MBOX_SIMPLE_VAL 0x8
370 #define NFP_NET_CFG_MBOX_CMD_CTAG_FILTER_ADD 1
371 #define NFP_NET_CFG_MBOX_CMD_CTAG_FILTER_KILL 2
373 #define NFP_NET_CFG_MBOX_CMD_PCI_DSCP_PRIOMAP_SET 5
374 #define NFP_NET_CFG_MBOX_CMD_TLV_CMSG 6
376 /* VLAN filtering using general use mailbox
377 * %NFP_NET_CFG_VLAN_FILTER: Base address of VLAN filter mailbox
378 * %NFP_NET_CFG_VLAN_FILTER_VID: VLAN ID to filter
379 * %NFP_NET_CFG_VLAN_FILTER_PROTO: VLAN proto to filter
380 * %NFP_NET_CFG_VXLAN_SZ: Size of the VLAN filter mailbox in bytes
382 #define NFP_NET_CFG_VLAN_FILTER NFP_NET_CFG_MBOX_SIMPLE_VAL
383 #define NFP_NET_CFG_VLAN_FILTER_VID NFP_NET_CFG_VLAN_FILTER
384 #define NFP_NET_CFG_VLAN_FILTER_PROTO (NFP_NET_CFG_VLAN_FILTER + 2)
385 #define NFP_NET_CFG_VLAN_FILTER_SZ 0x0004
388 * %NFP_NET_CFG_TLV_TYPE: Offset of type within the TLV
389 * %NFP_NET_CFG_TLV_TYPE_REQUIRED: Driver must be able to parse the TLV
390 * %NFP_NET_CFG_TLV_LENGTH: Offset of length within the TLV
391 * %NFP_NET_CFG_TLV_LENGTH_INC: TLV length increments
392 * %NFP_NET_CFG_TLV_VALUE: Offset of value with the TLV
394 * List of simple TLV structures, first one starts at %NFP_NET_CFG_TLV_BASE.
395 * Last structure must be of type %NFP_NET_CFG_TLV_TYPE_END. Presence of TLVs
396 * is indicated by %NFP_NET_CFG_TLV_BASE being non-zero. TLV structures may
397 * fill the entire remainder of the BAR or be shorter. FW must make sure TLVs
398 * don't conflict with other features which allocate space beyond
399 * %NFP_NET_CFG_TLV_BASE. %NFP_NET_CFG_TLV_TYPE_RESERVED should be used to wrap
400 * space used by such features.
401 * Note that the 4 byte TLV header is not counted in %NFP_NET_CFG_TLV_LENGTH.
403 #define NFP_NET_CFG_TLV_TYPE 0x00
404 #define NFP_NET_CFG_TLV_TYPE_REQUIRED 0x8000
405 #define NFP_NET_CFG_TLV_LENGTH 0x02
406 #define NFP_NET_CFG_TLV_LENGTH_INC 4
407 #define NFP_NET_CFG_TLV_VALUE 0x04
409 #define NFP_NET_CFG_TLV_HEADER_REQUIRED 0x80000000
410 #define NFP_NET_CFG_TLV_HEADER_TYPE 0x7fff0000
411 #define NFP_NET_CFG_TLV_HEADER_LENGTH 0x0000ffff
413 /* Capability TLV types
415 * %NFP_NET_CFG_TLV_TYPE_UNKNOWN:
416 * Special TLV type to catch bugs, should never be encountered. Drivers should
417 * treat encountering this type as error and refuse to probe.
419 * %NFP_NET_CFG_TLV_TYPE_RESERVED:
420 * Reserved space, may contain legacy fixed-offset fields, or be used for
421 * padding. The use of this type should be otherwise avoided.
423 * %NFP_NET_CFG_TLV_TYPE_END:
424 * Empty, end of TLV list. Must be the last TLV. Drivers will stop processing
425 * further TLVs when encountered.
427 * %NFP_NET_CFG_TLV_TYPE_ME_FREQ:
428 * Single word, ME frequency in MHz as used in calculation for
429 * %NFP_NET_CFG_RXR_IRQ_MOD and %NFP_NET_CFG_TXR_IRQ_MOD.
431 * %NFP_NET_CFG_TLV_TYPE_MBOX:
432 * Variable, mailbox area. Overwrites the default location which is
433 * %NFP_NET_CFG_MBOX_BASE and length %NFP_NET_CFG_MBOX_VAL_MAX_SZ.
435 * %NFP_NET_CFG_TLV_TYPE_EXPERIMENTAL0:
436 * %NFP_NET_CFG_TLV_TYPE_EXPERIMENTAL1:
437 * Variable, experimental IDs. IDs designated for internal development and
438 * experiments before a stable TLV ID has been allocated to a feature. Should
439 * never be present in production firmware.
441 * %NFP_NET_CFG_TLV_TYPE_REPR_CAP:
442 * Single word, equivalent of %NFP_NET_CFG_CAP for representors, features which
443 * can be used on representors.
445 * %NFP_NET_CFG_TLV_TYPE_MBOX_CMSG_TYPES:
446 * Variable, bitmap of control message types supported by the mailbox handler.
447 * Bit 0 corresponds to message type 0, bit 1 to 1, etc. Control messages are
448 * encapsulated into simple TLVs, with an end TLV and written to the Mailbox.
450 * %NFP_NET_CFG_TLV_TYPE_CRYPTO_OPS:
451 * 8 words, bitmaps of supported and enabled crypto operations.
452 * First 16B (4 words) contains a bitmap of supported crypto operations,
453 * and next 16B contain the enabled operations.
454 * This capability is made obsolete by ones with better sync methods.
456 * %NFP_NET_CFG_TLV_TYPE_VNIC_STATS:
457 * Variable, per-vNIC statistics, data should be 8B aligned (FW should insert
458 * zero-length RESERVED TLV to pad).
459 * TLV data has two sections. First is an array of statistics' IDs (2B each).
460 * Second 8B statistics themselves. Statistics are 8B aligned, meaning there
461 * may be a padding between sections.
462 * Number of statistics can be determined as floor(tlv.length / (2 + 8)).
463 * This TLV overwrites %NFP_NET_CFG_STATS_* values (statistics in this TLV
464 * duplicate the old ones, so driver should be careful not to unnecessarily
467 * %NFP_NET_CFG_TLV_TYPE_CRYPTO_OPS_RX_SCAN:
468 * Same as %NFP_NET_CFG_TLV_TYPE_CRYPTO_OPS, but crypto TLS does stream scan
469 * RX sync, rather than kernel-assisted sync.
471 #define NFP_NET_CFG_TLV_TYPE_UNKNOWN 0
472 #define NFP_NET_CFG_TLV_TYPE_RESERVED 1
473 #define NFP_NET_CFG_TLV_TYPE_END 2
474 #define NFP_NET_CFG_TLV_TYPE_ME_FREQ 3
475 #define NFP_NET_CFG_TLV_TYPE_MBOX 4
476 #define NFP_NET_CFG_TLV_TYPE_EXPERIMENTAL0 5
477 #define NFP_NET_CFG_TLV_TYPE_EXPERIMENTAL1 6
478 #define NFP_NET_CFG_TLV_TYPE_REPR_CAP 7
479 #define NFP_NET_CFG_TLV_TYPE_MBOX_CMSG_TYPES 10
480 #define NFP_NET_CFG_TLV_TYPE_CRYPTO_OPS 11 /* see crypto/fw.h */
481 #define NFP_NET_CFG_TLV_TYPE_VNIC_STATS 12
482 #define NFP_NET_CFG_TLV_TYPE_CRYPTO_OPS_RX_SCAN 13
486 /* struct nfp_net_tlv_caps - parsed control BAR TLV capabilities
487 * @me_freq_mhz: ME clock_freq (MHz)
488 * @mbox_off: vNIC mailbox area offset
489 * @mbox_len: vNIC mailbox area length
490 * @repr_cap: capabilities for representors
491 * @mbox_cmsg_types: cmsgs which can be passed through the mailbox
492 * @crypto_ops: supported crypto operations
493 * @crypto_enable_off: offset of crypto ops enable region
494 * @vnic_stats_off: offset of vNIC stats area
495 * @vnic_stats_cnt: number of vNIC stats
496 * @tls_resync_ss: TLS resync will be performed via stream scan
498 struct nfp_net_tlv_caps {
500 unsigned int mbox_off;
501 unsigned int mbox_len;
505 unsigned int crypto_enable_off;
506 unsigned int vnic_stats_off;
507 unsigned int vnic_stats_cnt;
508 unsigned int tls_resync_ss:1;
511 int nfp_net_tlv_caps_parse(struct device *dev, u8 __iomem *ctrl_mem,
512 struct nfp_net_tlv_caps *caps);
513 #endif /* _NFP_NET_CTRL_H_ */