1 /******************************************************************************
2 * This software may be used and distributed according to the terms of
3 * the GNU General Public License (GPL), incorporated herein by reference.
4 * Drivers based on or derived from this code fall under the GPL and must
5 * retain the authorship, copyright and license notice. This file is not
6 * a complete program and may only be used when the entire operating
7 * system is licensed under the GPL.
8 * See the file COPYING in this distribution for more information.
10 * vxge-traffic.c: Driver for Exar Corp's X3100 Series 10GbE PCIe I/O
11 * Virtualized Server Adapter.
12 * Copyright(c) 2002-2010 Exar Corp.
13 ******************************************************************************/
14 #include <linux/etherdevice.h>
15 #include <linux/io-64-nonatomic-lo-hi.h>
16 #include <linux/prefetch.h>
18 #include "vxge-traffic.h"
19 #include "vxge-config.h"
20 #include "vxge-main.h"
23 * vxge_hw_vpath_intr_enable - Enable vpath interrupts.
24 * @vp: Virtual Path handle.
26 * Enable vpath interrupts. The function is to be executed the last in
27 * vpath initialization sequence.
29 * See also: vxge_hw_vpath_intr_disable()
31 enum vxge_hw_status vxge_hw_vpath_intr_enable(struct __vxge_hw_vpath_handle *vp)
33 struct __vxge_hw_virtualpath *vpath;
34 struct vxge_hw_vpath_reg __iomem *vp_reg;
35 enum vxge_hw_status status = VXGE_HW_OK;
37 status = VXGE_HW_ERR_INVALID_HANDLE;
43 if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
44 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
48 vp_reg = vpath->vp_reg;
50 writeq(VXGE_HW_INTR_MASK_ALL, &vp_reg->kdfcctl_errors_reg);
52 __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
53 &vp_reg->general_errors_reg);
55 __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
56 &vp_reg->pci_config_errors_reg);
58 __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
59 &vp_reg->mrpcim_to_vpath_alarm_reg);
61 __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
62 &vp_reg->srpcim_to_vpath_alarm_reg);
64 __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
65 &vp_reg->vpath_ppif_int_status);
67 __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
68 &vp_reg->srpcim_msg_to_vpath_reg);
70 __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
71 &vp_reg->vpath_pcipif_int_status);
73 __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
74 &vp_reg->prc_alarm_reg);
76 __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
77 &vp_reg->wrdma_alarm_status);
79 __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
80 &vp_reg->asic_ntwk_vp_err_reg);
82 __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
83 &vp_reg->xgmac_vp_int_status);
85 readq(&vp_reg->vpath_general_int_status);
87 /* Mask unwanted interrupts */
89 __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
90 &vp_reg->vpath_pcipif_int_mask);
92 __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
93 &vp_reg->srpcim_msg_to_vpath_mask);
95 __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
96 &vp_reg->srpcim_to_vpath_alarm_mask);
98 __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
99 &vp_reg->mrpcim_to_vpath_alarm_mask);
101 __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
102 &vp_reg->pci_config_errors_mask);
104 /* Unmask the individual interrupts */
106 writeq((u32)vxge_bVALn((VXGE_HW_GENERAL_ERRORS_REG_DBLGEN_FIFO1_OVRFLOW|
107 VXGE_HW_GENERAL_ERRORS_REG_DBLGEN_FIFO2_OVRFLOW|
108 VXGE_HW_GENERAL_ERRORS_REG_STATSB_DROP_TIMEOUT_REQ|
109 VXGE_HW_GENERAL_ERRORS_REG_STATSB_PIF_CHAIN_ERR), 0, 32),
110 &vp_reg->general_errors_mask);
112 __vxge_hw_pio_mem_write32_upper(
113 (u32)vxge_bVALn((VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO1_OVRWR|
114 VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO2_OVRWR|
115 VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO1_POISON|
116 VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO2_POISON|
117 VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO1_DMA_ERR|
118 VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO2_DMA_ERR), 0, 32),
119 &vp_reg->kdfcctl_errors_mask);
121 __vxge_hw_pio_mem_write32_upper(0, &vp_reg->vpath_ppif_int_mask);
123 __vxge_hw_pio_mem_write32_upper(
124 (u32)vxge_bVALn(VXGE_HW_PRC_ALARM_REG_PRC_RING_BUMP, 0, 32),
125 &vp_reg->prc_alarm_mask);
127 __vxge_hw_pio_mem_write32_upper(0, &vp_reg->wrdma_alarm_mask);
128 __vxge_hw_pio_mem_write32_upper(0, &vp_reg->xgmac_vp_int_mask);
130 if (vpath->hldev->first_vp_id != vpath->vp_id)
131 __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
132 &vp_reg->asic_ntwk_vp_err_mask);
134 __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn((
135 VXGE_HW_ASIC_NTWK_VP_ERR_REG_XMACJ_NTWK_REAFFIRMED_FAULT |
136 VXGE_HW_ASIC_NTWK_VP_ERR_REG_XMACJ_NTWK_REAFFIRMED_OK), 0, 32),
137 &vp_reg->asic_ntwk_vp_err_mask);
139 __vxge_hw_pio_mem_write32_upper(0,
140 &vp_reg->vpath_general_int_mask);
147 * vxge_hw_vpath_intr_disable - Disable vpath interrupts.
148 * @vp: Virtual Path handle.
150 * Disable vpath interrupts. The function is to be executed the last in
151 * vpath initialization sequence.
153 * See also: vxge_hw_vpath_intr_enable()
155 enum vxge_hw_status vxge_hw_vpath_intr_disable(
156 struct __vxge_hw_vpath_handle *vp)
158 struct __vxge_hw_virtualpath *vpath;
159 enum vxge_hw_status status = VXGE_HW_OK;
160 struct vxge_hw_vpath_reg __iomem *vp_reg;
162 status = VXGE_HW_ERR_INVALID_HANDLE;
168 if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
169 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
172 vp_reg = vpath->vp_reg;
174 __vxge_hw_pio_mem_write32_upper(
175 (u32)VXGE_HW_INTR_MASK_ALL,
176 &vp_reg->vpath_general_int_mask);
178 writeq(VXGE_HW_INTR_MASK_ALL, &vp_reg->kdfcctl_errors_mask);
180 __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
181 &vp_reg->general_errors_mask);
183 __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
184 &vp_reg->pci_config_errors_mask);
186 __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
187 &vp_reg->mrpcim_to_vpath_alarm_mask);
189 __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
190 &vp_reg->srpcim_to_vpath_alarm_mask);
192 __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
193 &vp_reg->vpath_ppif_int_mask);
195 __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
196 &vp_reg->srpcim_msg_to_vpath_mask);
198 __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
199 &vp_reg->vpath_pcipif_int_mask);
201 __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
202 &vp_reg->wrdma_alarm_mask);
204 __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
205 &vp_reg->prc_alarm_mask);
207 __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
208 &vp_reg->xgmac_vp_int_mask);
210 __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
211 &vp_reg->asic_ntwk_vp_err_mask);
217 void vxge_hw_vpath_tti_ci_set(struct __vxge_hw_fifo *fifo)
219 struct vxge_hw_vpath_reg __iomem *vp_reg;
220 struct vxge_hw_vp_config *config;
223 if (fifo->config->enable != VXGE_HW_FIFO_ENABLE)
226 vp_reg = fifo->vp_reg;
227 config = container_of(fifo->config, struct vxge_hw_vp_config, fifo);
229 if (config->tti.timer_ci_en != VXGE_HW_TIM_TIMER_CI_ENABLE) {
230 config->tti.timer_ci_en = VXGE_HW_TIM_TIMER_CI_ENABLE;
231 val64 = readq(&vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_TX]);
232 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI;
233 fifo->tim_tti_cfg1_saved = val64;
234 writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_TX]);
238 void vxge_hw_vpath_dynamic_rti_ci_set(struct __vxge_hw_ring *ring)
240 u64 val64 = ring->tim_rti_cfg1_saved;
242 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI;
243 ring->tim_rti_cfg1_saved = val64;
244 writeq(val64, &ring->vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_RX]);
247 void vxge_hw_vpath_dynamic_tti_rtimer_set(struct __vxge_hw_fifo *fifo)
249 u64 val64 = fifo->tim_tti_cfg3_saved;
250 u64 timer = (fifo->rtimer * 1000) / 272;
252 val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL(0x3ffffff);
254 val64 |= VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL(timer) |
255 VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_EVENT_SF(5);
257 writeq(val64, &fifo->vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_TX]);
258 /* tti_cfg3_saved is not updated again because it is
259 * initialized at one place only - init time.
263 void vxge_hw_vpath_dynamic_rti_rtimer_set(struct __vxge_hw_ring *ring)
265 u64 val64 = ring->tim_rti_cfg3_saved;
266 u64 timer = (ring->rtimer * 1000) / 272;
268 val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL(0x3ffffff);
270 val64 |= VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL(timer) |
271 VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_EVENT_SF(4);
273 writeq(val64, &ring->vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_RX]);
274 /* rti_cfg3_saved is not updated again because it is
275 * initialized at one place only - init time.
280 * vxge_hw_channel_msix_mask - Mask MSIX Vector.
281 * @channel: Channel for rx or tx handle
284 * The function masks the msix interrupt for the given msix_id
288 void vxge_hw_channel_msix_mask(struct __vxge_hw_channel *channel, int msix_id)
291 __vxge_hw_pio_mem_write32_upper(
292 (u32)vxge_bVALn(vxge_mBIT(msix_id >> 2), 0, 32),
293 &channel->common_reg->set_msix_mask_vect[msix_id%4]);
297 * vxge_hw_channel_msix_unmask - Unmask the MSIX Vector.
298 * @channel: Channel for rx or tx handle
301 * The function unmasks the msix interrupt for the given msix_id
306 vxge_hw_channel_msix_unmask(struct __vxge_hw_channel *channel, int msix_id)
309 __vxge_hw_pio_mem_write32_upper(
310 (u32)vxge_bVALn(vxge_mBIT(msix_id >> 2), 0, 32),
311 &channel->common_reg->clear_msix_mask_vect[msix_id%4]);
315 * vxge_hw_channel_msix_clear - Unmask the MSIX Vector.
316 * @channel: Channel for rx or tx handle
319 * The function unmasks the msix interrupt for the given msix_id
320 * if configured in MSIX oneshot mode
324 void vxge_hw_channel_msix_clear(struct __vxge_hw_channel *channel, int msix_id)
326 __vxge_hw_pio_mem_write32_upper(
327 (u32) vxge_bVALn(vxge_mBIT(msix_id >> 2), 0, 32),
328 &channel->common_reg->clr_msix_one_shot_vec[msix_id % 4]);
332 * vxge_hw_device_set_intr_type - Updates the configuration
333 * with new interrupt type.
334 * @hldev: HW device handle.
335 * @intr_mode: New interrupt type
337 u32 vxge_hw_device_set_intr_type(struct __vxge_hw_device *hldev, u32 intr_mode)
340 if ((intr_mode != VXGE_HW_INTR_MODE_IRQLINE) &&
341 (intr_mode != VXGE_HW_INTR_MODE_MSIX) &&
342 (intr_mode != VXGE_HW_INTR_MODE_MSIX_ONE_SHOT) &&
343 (intr_mode != VXGE_HW_INTR_MODE_DEF))
344 intr_mode = VXGE_HW_INTR_MODE_IRQLINE;
346 hldev->config.intr_mode = intr_mode;
351 * vxge_hw_device_intr_enable - Enable interrupts.
352 * @hldev: HW device handle.
354 * Enable Titan interrupts. The function is to be executed the last in
355 * Titan initialization sequence.
357 * See also: vxge_hw_device_intr_disable()
359 void vxge_hw_device_intr_enable(struct __vxge_hw_device *hldev)
365 vxge_hw_device_mask_all(hldev);
367 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
369 if (!(hldev->vpaths_deployed & vxge_mBIT(i)))
372 vxge_hw_vpath_intr_enable(
373 VXGE_HW_VIRTUAL_PATH_HANDLE(&hldev->virtual_paths[i]));
376 if (hldev->config.intr_mode == VXGE_HW_INTR_MODE_IRQLINE) {
377 val64 = hldev->tim_int_mask0[VXGE_HW_VPATH_INTR_TX] |
378 hldev->tim_int_mask0[VXGE_HW_VPATH_INTR_RX];
381 writeq(val64, &hldev->common_reg->tim_int_status0);
383 writeq(~val64, &hldev->common_reg->tim_int_mask0);
386 val32 = hldev->tim_int_mask1[VXGE_HW_VPATH_INTR_TX] |
387 hldev->tim_int_mask1[VXGE_HW_VPATH_INTR_RX];
390 __vxge_hw_pio_mem_write32_upper(val32,
391 &hldev->common_reg->tim_int_status1);
393 __vxge_hw_pio_mem_write32_upper(~val32,
394 &hldev->common_reg->tim_int_mask1);
398 val64 = readq(&hldev->common_reg->titan_general_int_status);
400 vxge_hw_device_unmask_all(hldev);
404 * vxge_hw_device_intr_disable - Disable Titan interrupts.
405 * @hldev: HW device handle.
407 * Disable Titan interrupts.
409 * See also: vxge_hw_device_intr_enable()
411 void vxge_hw_device_intr_disable(struct __vxge_hw_device *hldev)
415 vxge_hw_device_mask_all(hldev);
417 /* mask all the tim interrupts */
418 writeq(VXGE_HW_INTR_MASK_ALL, &hldev->common_reg->tim_int_mask0);
419 __vxge_hw_pio_mem_write32_upper(VXGE_HW_DEFAULT_32,
420 &hldev->common_reg->tim_int_mask1);
422 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
424 if (!(hldev->vpaths_deployed & vxge_mBIT(i)))
427 vxge_hw_vpath_intr_disable(
428 VXGE_HW_VIRTUAL_PATH_HANDLE(&hldev->virtual_paths[i]));
433 * vxge_hw_device_mask_all - Mask all device interrupts.
434 * @hldev: HW device handle.
436 * Mask all device interrupts.
438 * See also: vxge_hw_device_unmask_all()
440 void vxge_hw_device_mask_all(struct __vxge_hw_device *hldev)
444 val64 = VXGE_HW_TITAN_MASK_ALL_INT_ALARM |
445 VXGE_HW_TITAN_MASK_ALL_INT_TRAFFIC;
447 __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(val64, 0, 32),
448 &hldev->common_reg->titan_mask_all_int);
452 * vxge_hw_device_unmask_all - Unmask all device interrupts.
453 * @hldev: HW device handle.
455 * Unmask all device interrupts.
457 * See also: vxge_hw_device_mask_all()
459 void vxge_hw_device_unmask_all(struct __vxge_hw_device *hldev)
463 if (hldev->config.intr_mode == VXGE_HW_INTR_MODE_IRQLINE)
464 val64 = VXGE_HW_TITAN_MASK_ALL_INT_TRAFFIC;
466 __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(val64, 0, 32),
467 &hldev->common_reg->titan_mask_all_int);
471 * vxge_hw_device_flush_io - Flush io writes.
472 * @hldev: HW device handle.
474 * The function performs a read operation to flush io writes.
478 void vxge_hw_device_flush_io(struct __vxge_hw_device *hldev)
480 readl(&hldev->common_reg->titan_general_int_status);
484 * __vxge_hw_device_handle_error - Handle error
487 * @type: Error type. Please see enum vxge_hw_event{}
491 static enum vxge_hw_status
492 __vxge_hw_device_handle_error(struct __vxge_hw_device *hldev, u32 vp_id,
493 enum vxge_hw_event type)
496 case VXGE_HW_EVENT_UNKNOWN:
498 case VXGE_HW_EVENT_RESET_START:
499 case VXGE_HW_EVENT_RESET_COMPLETE:
500 case VXGE_HW_EVENT_LINK_DOWN:
501 case VXGE_HW_EVENT_LINK_UP:
503 case VXGE_HW_EVENT_ALARM_CLEARED:
505 case VXGE_HW_EVENT_ECCERR:
506 case VXGE_HW_EVENT_MRPCIM_ECCERR:
508 case VXGE_HW_EVENT_FIFO_ERR:
509 case VXGE_HW_EVENT_VPATH_ERR:
510 case VXGE_HW_EVENT_CRITICAL_ERR:
511 case VXGE_HW_EVENT_SERR:
513 case VXGE_HW_EVENT_SRPCIM_SERR:
514 case VXGE_HW_EVENT_MRPCIM_SERR:
516 case VXGE_HW_EVENT_SLOT_FREEZE:
524 if (hldev->uld_callbacks->crit_err)
525 hldev->uld_callbacks->crit_err(hldev,
533 * __vxge_hw_device_handle_link_down_ind
534 * @hldev: HW device handle.
536 * Link down indication handler. The function is invoked by HW when
537 * Titan indicates that the link is down.
539 static enum vxge_hw_status
540 __vxge_hw_device_handle_link_down_ind(struct __vxge_hw_device *hldev)
543 * If the previous link state is not down, return.
545 if (hldev->link_state == VXGE_HW_LINK_DOWN)
548 hldev->link_state = VXGE_HW_LINK_DOWN;
551 if (hldev->uld_callbacks->link_down)
552 hldev->uld_callbacks->link_down(hldev);
558 * __vxge_hw_device_handle_link_up_ind
559 * @hldev: HW device handle.
561 * Link up indication handler. The function is invoked by HW when
562 * Titan indicates that the link is up for programmable amount of time.
564 static enum vxge_hw_status
565 __vxge_hw_device_handle_link_up_ind(struct __vxge_hw_device *hldev)
568 * If the previous link state is not down, return.
570 if (hldev->link_state == VXGE_HW_LINK_UP)
573 hldev->link_state = VXGE_HW_LINK_UP;
576 if (hldev->uld_callbacks->link_up)
577 hldev->uld_callbacks->link_up(hldev);
583 * __vxge_hw_vpath_alarm_process - Process Alarms.
584 * @vpath: Virtual Path.
585 * @skip_alarms: Do not clear the alarms
587 * Process vpath alarms.
590 static enum vxge_hw_status
591 __vxge_hw_vpath_alarm_process(struct __vxge_hw_virtualpath *vpath,
597 struct __vxge_hw_device *hldev = NULL;
598 enum vxge_hw_event alarm_event = VXGE_HW_EVENT_UNKNOWN;
600 struct vxge_hw_vpath_stats_sw_info *sw_stats;
601 struct vxge_hw_vpath_reg __iomem *vp_reg;
604 alarm_event = VXGE_HW_SET_LEVEL(VXGE_HW_EVENT_UNKNOWN,
609 hldev = vpath->hldev;
610 vp_reg = vpath->vp_reg;
611 alarm_status = readq(&vp_reg->vpath_general_int_status);
613 if (alarm_status == VXGE_HW_ALL_FOXES) {
614 alarm_event = VXGE_HW_SET_LEVEL(VXGE_HW_EVENT_SLOT_FREEZE,
619 sw_stats = vpath->sw_stats;
621 if (alarm_status & ~(
622 VXGE_HW_VPATH_GENERAL_INT_STATUS_PIC_INT |
623 VXGE_HW_VPATH_GENERAL_INT_STATUS_PCI_INT |
624 VXGE_HW_VPATH_GENERAL_INT_STATUS_WRDMA_INT |
625 VXGE_HW_VPATH_GENERAL_INT_STATUS_XMAC_INT)) {
626 sw_stats->error_stats.unknown_alarms++;
628 alarm_event = VXGE_HW_SET_LEVEL(VXGE_HW_EVENT_UNKNOWN,
633 if (alarm_status & VXGE_HW_VPATH_GENERAL_INT_STATUS_XMAC_INT) {
635 val64 = readq(&vp_reg->xgmac_vp_int_status);
638 VXGE_HW_XGMAC_VP_INT_STATUS_ASIC_NTWK_VP_ERR_ASIC_NTWK_VP_INT) {
640 val64 = readq(&vp_reg->asic_ntwk_vp_err_reg);
643 VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_FLT) &&
645 VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_OK))) ||
647 VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_FLT_OCCURR) &&
649 VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_OK_OCCURR)
651 sw_stats->error_stats.network_sustained_fault++;
654 VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_FLT,
655 &vp_reg->asic_ntwk_vp_err_mask);
657 __vxge_hw_device_handle_link_down_ind(hldev);
658 alarm_event = VXGE_HW_SET_LEVEL(
659 VXGE_HW_EVENT_LINK_DOWN, alarm_event);
663 VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_OK) &&
665 VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_FLT))) ||
667 VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_OK_OCCURR) &&
669 VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_FLT_OCCURR)
672 sw_stats->error_stats.network_sustained_ok++;
675 VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_OK,
676 &vp_reg->asic_ntwk_vp_err_mask);
678 __vxge_hw_device_handle_link_up_ind(hldev);
679 alarm_event = VXGE_HW_SET_LEVEL(
680 VXGE_HW_EVENT_LINK_UP, alarm_event);
683 writeq(VXGE_HW_INTR_MASK_ALL,
684 &vp_reg->asic_ntwk_vp_err_reg);
686 alarm_event = VXGE_HW_SET_LEVEL(
687 VXGE_HW_EVENT_ALARM_CLEARED, alarm_event);
694 if (alarm_status & VXGE_HW_VPATH_GENERAL_INT_STATUS_PIC_INT) {
696 pic_status = readq(&vp_reg->vpath_ppif_int_status);
699 VXGE_HW_VPATH_PPIF_INT_STATUS_GENERAL_ERRORS_GENERAL_INT) {
701 val64 = readq(&vp_reg->general_errors_reg);
702 mask64 = readq(&vp_reg->general_errors_mask);
705 VXGE_HW_GENERAL_ERRORS_REG_INI_SERR_DET) &
707 sw_stats->error_stats.ini_serr_det++;
709 alarm_event = VXGE_HW_SET_LEVEL(
710 VXGE_HW_EVENT_SERR, alarm_event);
714 VXGE_HW_GENERAL_ERRORS_REG_DBLGEN_FIFO0_OVRFLOW) &
716 sw_stats->error_stats.dblgen_fifo0_overflow++;
718 alarm_event = VXGE_HW_SET_LEVEL(
719 VXGE_HW_EVENT_FIFO_ERR, alarm_event);
723 VXGE_HW_GENERAL_ERRORS_REG_STATSB_PIF_CHAIN_ERR) &
725 sw_stats->error_stats.statsb_pif_chain_error++;
728 VXGE_HW_GENERAL_ERRORS_REG_STATSB_DROP_TIMEOUT_REQ) &
730 sw_stats->error_stats.statsb_drop_timeout++;
733 VXGE_HW_GENERAL_ERRORS_REG_TGT_ILLEGAL_ACCESS) &
735 sw_stats->error_stats.target_illegal_access++;
738 writeq(VXGE_HW_INTR_MASK_ALL,
739 &vp_reg->general_errors_reg);
740 alarm_event = VXGE_HW_SET_LEVEL(
741 VXGE_HW_EVENT_ALARM_CLEARED,
747 VXGE_HW_VPATH_PPIF_INT_STATUS_KDFCCTL_ERRORS_KDFCCTL_INT) {
749 val64 = readq(&vp_reg->kdfcctl_errors_reg);
750 mask64 = readq(&vp_reg->kdfcctl_errors_mask);
753 VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO0_OVRWR) &
755 sw_stats->error_stats.kdfcctl_fifo0_overwrite++;
757 alarm_event = VXGE_HW_SET_LEVEL(
758 VXGE_HW_EVENT_FIFO_ERR,
763 VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO0_POISON) &
765 sw_stats->error_stats.kdfcctl_fifo0_poison++;
767 alarm_event = VXGE_HW_SET_LEVEL(
768 VXGE_HW_EVENT_FIFO_ERR,
773 VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO0_DMA_ERR) &
775 sw_stats->error_stats.kdfcctl_fifo0_dma_error++;
777 alarm_event = VXGE_HW_SET_LEVEL(
778 VXGE_HW_EVENT_FIFO_ERR,
783 writeq(VXGE_HW_INTR_MASK_ALL,
784 &vp_reg->kdfcctl_errors_reg);
785 alarm_event = VXGE_HW_SET_LEVEL(
786 VXGE_HW_EVENT_ALARM_CLEARED,
793 if (alarm_status & VXGE_HW_VPATH_GENERAL_INT_STATUS_WRDMA_INT) {
795 val64 = readq(&vp_reg->wrdma_alarm_status);
797 if (val64 & VXGE_HW_WRDMA_ALARM_STATUS_PRC_ALARM_PRC_INT) {
799 val64 = readq(&vp_reg->prc_alarm_reg);
800 mask64 = readq(&vp_reg->prc_alarm_mask);
802 if ((val64 & VXGE_HW_PRC_ALARM_REG_PRC_RING_BUMP)&
804 sw_stats->error_stats.prc_ring_bumps++;
806 if ((val64 & VXGE_HW_PRC_ALARM_REG_PRC_RXDCM_SC_ERR) &
808 sw_stats->error_stats.prc_rxdcm_sc_err++;
810 alarm_event = VXGE_HW_SET_LEVEL(
811 VXGE_HW_EVENT_VPATH_ERR,
815 if ((val64 & VXGE_HW_PRC_ALARM_REG_PRC_RXDCM_SC_ABORT)
817 sw_stats->error_stats.prc_rxdcm_sc_abort++;
819 alarm_event = VXGE_HW_SET_LEVEL(
820 VXGE_HW_EVENT_VPATH_ERR,
824 if ((val64 & VXGE_HW_PRC_ALARM_REG_PRC_QUANTA_SIZE_ERR)
826 sw_stats->error_stats.prc_quanta_size_err++;
828 alarm_event = VXGE_HW_SET_LEVEL(
829 VXGE_HW_EVENT_VPATH_ERR,
834 writeq(VXGE_HW_INTR_MASK_ALL,
835 &vp_reg->prc_alarm_reg);
836 alarm_event = VXGE_HW_SET_LEVEL(
837 VXGE_HW_EVENT_ALARM_CLEARED,
843 hldev->stats.sw_dev_err_stats.vpath_alarms++;
845 if ((alarm_event == VXGE_HW_EVENT_ALARM_CLEARED) ||
846 (alarm_event == VXGE_HW_EVENT_UNKNOWN))
849 __vxge_hw_device_handle_error(hldev, vpath->vp_id, alarm_event);
851 if (alarm_event == VXGE_HW_EVENT_SERR)
852 return VXGE_HW_ERR_CRITICAL;
854 return (alarm_event == VXGE_HW_EVENT_SLOT_FREEZE) ?
855 VXGE_HW_ERR_SLOT_FREEZE :
856 (alarm_event == VXGE_HW_EVENT_FIFO_ERR) ? VXGE_HW_ERR_FIFO :
861 * vxge_hw_device_begin_irq - Begin IRQ processing.
862 * @hldev: HW device handle.
863 * @skip_alarms: Do not clear the alarms
864 * @reason: "Reason" for the interrupt, the value of Titan's
865 * general_int_status register.
867 * The function performs two actions, It first checks whether (shared IRQ) the
868 * interrupt was raised by the device. Next, it masks the device interrupts.
871 * vxge_hw_device_begin_irq() does not flush MMIO writes through the
872 * bridge. Therefore, two back-to-back interrupts are potentially possible.
874 * Returns: 0, if the interrupt is not "ours" (note that in this case the
875 * device remain enabled).
876 * Otherwise, vxge_hw_device_begin_irq() returns 64bit general adapter
879 enum vxge_hw_status vxge_hw_device_begin_irq(struct __vxge_hw_device *hldev,
880 u32 skip_alarms, u64 *reason)
886 enum vxge_hw_status ret = VXGE_HW_OK;
888 val64 = readq(&hldev->common_reg->titan_general_int_status);
890 if (unlikely(!val64)) {
891 /* not Titan interrupt */
893 ret = VXGE_HW_ERR_WRONG_IRQ;
897 if (unlikely(val64 == VXGE_HW_ALL_FOXES)) {
899 adapter_status = readq(&hldev->common_reg->adapter_status);
901 if (adapter_status == VXGE_HW_ALL_FOXES) {
903 __vxge_hw_device_handle_error(hldev,
904 NULL_VPID, VXGE_HW_EVENT_SLOT_FREEZE);
906 ret = VXGE_HW_ERR_SLOT_FREEZE;
911 hldev->stats.sw_dev_info_stats.total_intr_cnt++;
915 vpath_mask = hldev->vpaths_deployed >>
916 (64 - VXGE_HW_MAX_VIRTUAL_PATHS);
919 VXGE_HW_TITAN_GENERAL_INT_STATUS_VPATH_TRAFFIC_INT(vpath_mask)) {
920 hldev->stats.sw_dev_info_stats.traffic_intr_cnt++;
925 hldev->stats.sw_dev_info_stats.not_traffic_intr_cnt++;
928 VXGE_HW_TITAN_GENERAL_INT_STATUS_VPATH_ALARM_INT)) {
930 enum vxge_hw_status error_level = VXGE_HW_OK;
932 hldev->stats.sw_dev_err_stats.vpath_alarms++;
934 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
936 if (!(hldev->vpaths_deployed & vxge_mBIT(i)))
939 ret = __vxge_hw_vpath_alarm_process(
940 &hldev->virtual_paths[i], skip_alarms);
942 error_level = VXGE_HW_SET_LEVEL(ret, error_level);
944 if (unlikely((ret == VXGE_HW_ERR_CRITICAL) ||
945 (ret == VXGE_HW_ERR_SLOT_FREEZE)))
956 * vxge_hw_device_clear_tx_rx - Acknowledge (that is, clear) the
957 * condition that has caused the Tx and RX interrupt.
960 * Acknowledge (that is, clear) the condition that has caused
961 * the Tx and Rx interrupt.
962 * See also: vxge_hw_device_begin_irq(),
963 * vxge_hw_device_mask_tx_rx(), vxge_hw_device_unmask_tx_rx().
965 void vxge_hw_device_clear_tx_rx(struct __vxge_hw_device *hldev)
968 if ((hldev->tim_int_mask0[VXGE_HW_VPATH_INTR_TX] != 0) ||
969 (hldev->tim_int_mask0[VXGE_HW_VPATH_INTR_RX] != 0)) {
970 writeq((hldev->tim_int_mask0[VXGE_HW_VPATH_INTR_TX] |
971 hldev->tim_int_mask0[VXGE_HW_VPATH_INTR_RX]),
972 &hldev->common_reg->tim_int_status0);
975 if ((hldev->tim_int_mask1[VXGE_HW_VPATH_INTR_TX] != 0) ||
976 (hldev->tim_int_mask1[VXGE_HW_VPATH_INTR_RX] != 0)) {
977 __vxge_hw_pio_mem_write32_upper(
978 (hldev->tim_int_mask1[VXGE_HW_VPATH_INTR_TX] |
979 hldev->tim_int_mask1[VXGE_HW_VPATH_INTR_RX]),
980 &hldev->common_reg->tim_int_status1);
985 * vxge_hw_channel_dtr_alloc - Allocate a dtr from the channel
987 * @dtrh: Buffer to return the DTR pointer
989 * Allocates a dtr from the reserve array. If the reserve array is empty,
990 * it swaps the reserve and free arrays.
993 static enum vxge_hw_status
994 vxge_hw_channel_dtr_alloc(struct __vxge_hw_channel *channel, void **dtrh)
996 if (channel->reserve_ptr - channel->reserve_top > 0) {
998 *dtrh = channel->reserve_arr[--channel->reserve_ptr];
1003 /* switch between empty and full arrays */
1005 /* the idea behind such a design is that by having free and reserved
1006 * arrays separated we basically separated irq and non-irq parts.
1007 * i.e. no additional lock need to be done when we free a resource */
1009 if (channel->length - channel->free_ptr > 0) {
1010 swap(channel->reserve_arr, channel->free_arr);
1011 channel->reserve_ptr = channel->length;
1012 channel->reserve_top = channel->free_ptr;
1013 channel->free_ptr = channel->length;
1015 channel->stats->reserve_free_swaps_cnt++;
1017 goto _alloc_after_swap;
1020 channel->stats->full_cnt++;
1023 return VXGE_HW_INF_OUT_OF_DESCRIPTORS;
1027 * vxge_hw_channel_dtr_post - Post a dtr to the channel
1028 * @channelh: Channel
1029 * @dtrh: DTR pointer
1031 * Posts a dtr to work array.
1035 vxge_hw_channel_dtr_post(struct __vxge_hw_channel *channel, void *dtrh)
1037 vxge_assert(channel->work_arr[channel->post_index] == NULL);
1039 channel->work_arr[channel->post_index++] = dtrh;
1042 if (channel->post_index == channel->length)
1043 channel->post_index = 0;
1047 * vxge_hw_channel_dtr_try_complete - Returns next completed dtr
1049 * @dtr: Buffer to return the next completed DTR pointer
1051 * Returns the next completed dtr with out removing it from work array
1055 vxge_hw_channel_dtr_try_complete(struct __vxge_hw_channel *channel, void **dtrh)
1057 vxge_assert(channel->compl_index < channel->length);
1059 *dtrh = channel->work_arr[channel->compl_index];
1064 * vxge_hw_channel_dtr_complete - Removes next completed dtr from the work array
1065 * @channel: Channel handle
1067 * Removes the next completed dtr from work array
1070 void vxge_hw_channel_dtr_complete(struct __vxge_hw_channel *channel)
1072 channel->work_arr[channel->compl_index] = NULL;
1075 if (++channel->compl_index == channel->length)
1076 channel->compl_index = 0;
1078 channel->stats->total_compl_cnt++;
1082 * vxge_hw_channel_dtr_free - Frees a dtr
1083 * @channel: Channel handle
1086 * Returns the dtr to free array
1089 void vxge_hw_channel_dtr_free(struct __vxge_hw_channel *channel, void *dtrh)
1091 channel->free_arr[--channel->free_ptr] = dtrh;
1095 * vxge_hw_channel_dtr_count
1096 * @channel: Channel handle. Obtained via vxge_hw_channel_open().
1098 * Retrieve number of DTRs available. This function can not be called
1099 * from data path. ring_initial_replenishi() is the only user.
1101 int vxge_hw_channel_dtr_count(struct __vxge_hw_channel *channel)
1103 return (channel->reserve_ptr - channel->reserve_top) +
1104 (channel->length - channel->free_ptr);
1108 * vxge_hw_ring_rxd_reserve - Reserve ring descriptor.
1109 * @ring: Handle to the ring object used for receive
1110 * @rxdh: Reserved descriptor. On success HW fills this "out" parameter
1111 * with a valid handle.
1113 * Reserve Rx descriptor for the subsequent filling-in driver
1114 * and posting on the corresponding channel (@channelh)
1115 * via vxge_hw_ring_rxd_post().
1117 * Returns: VXGE_HW_OK - success.
1118 * VXGE_HW_INF_OUT_OF_DESCRIPTORS - Currently no descriptors available.
1121 enum vxge_hw_status vxge_hw_ring_rxd_reserve(struct __vxge_hw_ring *ring,
1124 enum vxge_hw_status status;
1125 struct __vxge_hw_channel *channel;
1127 channel = &ring->channel;
1129 status = vxge_hw_channel_dtr_alloc(channel, rxdh);
1131 if (status == VXGE_HW_OK) {
1132 struct vxge_hw_ring_rxd_1 *rxdp =
1133 (struct vxge_hw_ring_rxd_1 *)*rxdh;
1135 rxdp->control_0 = rxdp->control_1 = 0;
1142 * vxge_hw_ring_rxd_free - Free descriptor.
1143 * @ring: Handle to the ring object used for receive
1144 * @rxdh: Descriptor handle.
1146 * Free the reserved descriptor. This operation is "symmetrical" to
1147 * vxge_hw_ring_rxd_reserve. The "free-ing" completes the descriptor's
1150 * After free-ing (see vxge_hw_ring_rxd_free()) the descriptor again can
1153 * - reserved (vxge_hw_ring_rxd_reserve);
1155 * - posted (vxge_hw_ring_rxd_post);
1157 * - completed (vxge_hw_ring_rxd_next_completed);
1159 * - and recycled again (vxge_hw_ring_rxd_free).
1161 * For alternative state transitions and more details please refer to
1165 void vxge_hw_ring_rxd_free(struct __vxge_hw_ring *ring, void *rxdh)
1167 struct __vxge_hw_channel *channel;
1169 channel = &ring->channel;
1171 vxge_hw_channel_dtr_free(channel, rxdh);
1176 * vxge_hw_ring_rxd_pre_post - Prepare rxd and post
1177 * @ring: Handle to the ring object used for receive
1178 * @rxdh: Descriptor handle.
1180 * This routine prepares a rxd and posts
1182 void vxge_hw_ring_rxd_pre_post(struct __vxge_hw_ring *ring, void *rxdh)
1184 struct __vxge_hw_channel *channel;
1186 channel = &ring->channel;
1188 vxge_hw_channel_dtr_post(channel, rxdh);
1192 * vxge_hw_ring_rxd_post_post - Process rxd after post.
1193 * @ring: Handle to the ring object used for receive
1194 * @rxdh: Descriptor handle.
1196 * Processes rxd after post
1198 void vxge_hw_ring_rxd_post_post(struct __vxge_hw_ring *ring, void *rxdh)
1200 struct vxge_hw_ring_rxd_1 *rxdp = (struct vxge_hw_ring_rxd_1 *)rxdh;
1202 rxdp->control_0 = VXGE_HW_RING_RXD_LIST_OWN_ADAPTER;
1204 if (ring->stats->common_stats.usage_cnt > 0)
1205 ring->stats->common_stats.usage_cnt--;
1209 * vxge_hw_ring_rxd_post - Post descriptor on the ring.
1210 * @ring: Handle to the ring object used for receive
1211 * @rxdh: Descriptor obtained via vxge_hw_ring_rxd_reserve().
1213 * Post descriptor on the ring.
1214 * Prior to posting the descriptor should be filled in accordance with
1215 * Host/Titan interface specification for a given service (LL, etc.).
1218 void vxge_hw_ring_rxd_post(struct __vxge_hw_ring *ring, void *rxdh)
1220 struct vxge_hw_ring_rxd_1 *rxdp = (struct vxge_hw_ring_rxd_1 *)rxdh;
1221 struct __vxge_hw_channel *channel;
1223 channel = &ring->channel;
1226 rxdp->control_0 = VXGE_HW_RING_RXD_LIST_OWN_ADAPTER;
1228 vxge_hw_channel_dtr_post(channel, rxdh);
1230 if (ring->stats->common_stats.usage_cnt > 0)
1231 ring->stats->common_stats.usage_cnt--;
1235 * vxge_hw_ring_rxd_post_post_wmb - Process rxd after post with memory barrier.
1236 * @ring: Handle to the ring object used for receive
1237 * @rxdh: Descriptor handle.
1239 * Processes rxd after post with memory barrier.
1241 void vxge_hw_ring_rxd_post_post_wmb(struct __vxge_hw_ring *ring, void *rxdh)
1244 vxge_hw_ring_rxd_post_post(ring, rxdh);
1248 * vxge_hw_ring_rxd_next_completed - Get the _next_ completed descriptor.
1249 * @ring: Handle to the ring object used for receive
1250 * @rxdh: Descriptor handle. Returned by HW.
1251 * @t_code: Transfer code, as per Titan User Guide,
1252 * Receive Descriptor Format. Returned by HW.
1254 * Retrieve the _next_ completed descriptor.
1255 * HW uses ring callback (*vxge_hw_ring_callback_f) to notifiy
1256 * driver of new completed descriptors. After that
1257 * the driver can use vxge_hw_ring_rxd_next_completed to retrieve the rest
1258 * completions (the very first completion is passed by HW via
1259 * vxge_hw_ring_callback_f).
1261 * Implementation-wise, the driver is free to call
1262 * vxge_hw_ring_rxd_next_completed either immediately from inside the
1263 * ring callback, or in a deferred fashion and separate (from HW)
1266 * Non-zero @t_code means failure to fill-in receive buffer(s)
1267 * of the descriptor.
1268 * For instance, parity error detected during the data transfer.
1269 * In this case Titan will complete the descriptor and indicate
1270 * for the host that the received data is not to be used.
1271 * For details please refer to Titan User Guide.
1273 * Returns: VXGE_HW_OK - success.
1274 * VXGE_HW_INF_NO_MORE_COMPLETED_DESCRIPTORS - No completed descriptors
1275 * are currently available for processing.
1277 * See also: vxge_hw_ring_callback_f{},
1278 * vxge_hw_fifo_rxd_next_completed(), enum vxge_hw_status{}.
1280 enum vxge_hw_status vxge_hw_ring_rxd_next_completed(
1281 struct __vxge_hw_ring *ring, void **rxdh, u8 *t_code)
1283 struct __vxge_hw_channel *channel;
1284 struct vxge_hw_ring_rxd_1 *rxdp;
1285 enum vxge_hw_status status = VXGE_HW_OK;
1288 channel = &ring->channel;
1290 vxge_hw_channel_dtr_try_complete(channel, rxdh);
1294 status = VXGE_HW_INF_NO_MORE_COMPLETED_DESCRIPTORS;
1298 control_0 = rxdp->control_0;
1299 own = control_0 & VXGE_HW_RING_RXD_LIST_OWN_ADAPTER;
1300 *t_code = (u8)VXGE_HW_RING_RXD_T_CODE_GET(control_0);
1302 /* check whether it is not the end */
1303 if (!own || *t_code == VXGE_HW_RING_T_CODE_FRM_DROP) {
1305 vxge_assert((rxdp)->host_control !=
1309 vxge_hw_channel_dtr_complete(channel);
1311 vxge_assert(*t_code != VXGE_HW_RING_RXD_T_CODE_UNUSED);
1313 ring->stats->common_stats.usage_cnt++;
1314 if (ring->stats->common_stats.usage_max <
1315 ring->stats->common_stats.usage_cnt)
1316 ring->stats->common_stats.usage_max =
1317 ring->stats->common_stats.usage_cnt;
1319 status = VXGE_HW_OK;
1323 /* reset it. since we don't want to return
1324 * garbage to the driver */
1326 status = VXGE_HW_INF_NO_MORE_COMPLETED_DESCRIPTORS;
1332 * vxge_hw_ring_handle_tcode - Handle transfer code.
1333 * @ring: Handle to the ring object used for receive
1334 * @rxdh: Descriptor handle.
1335 * @t_code: One of the enumerated (and documented in the Titan user guide)
1338 * Handle descriptor's transfer code. The latter comes with each completed
1341 * Returns: one of the enum vxge_hw_status{} enumerated types.
1342 * VXGE_HW_OK - for success.
1343 * VXGE_HW_ERR_CRITICAL - when encounters critical error.
1345 enum vxge_hw_status vxge_hw_ring_handle_tcode(
1346 struct __vxge_hw_ring *ring, void *rxdh, u8 t_code)
1348 enum vxge_hw_status status = VXGE_HW_OK;
1350 /* If the t_code is not supported and if the
1351 * t_code is other than 0x5 (unparseable packet
1352 * such as unknown UPV6 header), Drop it !!!
1355 if (t_code == VXGE_HW_RING_T_CODE_OK ||
1356 t_code == VXGE_HW_RING_T_CODE_L3_PKT_ERR) {
1357 status = VXGE_HW_OK;
1361 if (t_code > VXGE_HW_RING_T_CODE_MULTI_ERR) {
1362 status = VXGE_HW_ERR_INVALID_TCODE;
1366 ring->stats->rxd_t_code_err_cnt[t_code]++;
1372 * __vxge_hw_non_offload_db_post - Post non offload doorbell
1375 * @txdl_ptr: The starting location of the TxDL in host memory
1376 * @num_txds: The highest TxD in this TxDL (0 to 255 means 1 to 256)
1377 * @no_snoop: No snoop flags
1379 * This function posts a non-offload doorbell to doorbell FIFO
1382 static void __vxge_hw_non_offload_db_post(struct __vxge_hw_fifo *fifo,
1383 u64 txdl_ptr, u32 num_txds, u32 no_snoop)
1385 writeq(VXGE_HW_NODBW_TYPE(VXGE_HW_NODBW_TYPE_NODBW) |
1386 VXGE_HW_NODBW_LAST_TXD_NUMBER(num_txds) |
1387 VXGE_HW_NODBW_GET_NO_SNOOP(no_snoop),
1388 &fifo->nofl_db->control_0);
1390 writeq(txdl_ptr, &fifo->nofl_db->txdl_ptr);
1394 * vxge_hw_fifo_free_txdl_count_get - returns the number of txdls available in
1396 * @fifoh: Handle to the fifo object used for non offload send
1398 u32 vxge_hw_fifo_free_txdl_count_get(struct __vxge_hw_fifo *fifoh)
1400 return vxge_hw_channel_dtr_count(&fifoh->channel);
1404 * vxge_hw_fifo_txdl_reserve - Reserve fifo descriptor.
1405 * @fifo: Handle to the fifo object used for non offload send
1406 * @txdlh: Reserved descriptor. On success HW fills this "out" parameter
1407 * with a valid handle.
1408 * @txdl_priv: Buffer to return the pointer to per txdl space
1410 * Reserve a single TxDL (that is, fifo descriptor)
1411 * for the subsequent filling-in by driver)
1412 * and posting on the corresponding channel (@channelh)
1413 * via vxge_hw_fifo_txdl_post().
1415 * Note: it is the responsibility of driver to reserve multiple descriptors
1416 * for lengthy (e.g., LSO) transmit operation. A single fifo descriptor
1417 * carries up to configured number (fifo.max_frags) of contiguous buffers.
1419 * Returns: VXGE_HW_OK - success;
1420 * VXGE_HW_INF_OUT_OF_DESCRIPTORS - Currently no descriptors available
1423 enum vxge_hw_status vxge_hw_fifo_txdl_reserve(
1424 struct __vxge_hw_fifo *fifo,
1425 void **txdlh, void **txdl_priv)
1427 struct __vxge_hw_channel *channel;
1428 enum vxge_hw_status status;
1431 channel = &fifo->channel;
1433 status = vxge_hw_channel_dtr_alloc(channel, txdlh);
1435 if (status == VXGE_HW_OK) {
1436 struct vxge_hw_fifo_txd *txdp =
1437 (struct vxge_hw_fifo_txd *)*txdlh;
1438 struct __vxge_hw_fifo_txdl_priv *priv;
1440 priv = __vxge_hw_fifo_txdl_priv(fifo, txdp);
1442 /* reset the TxDL's private */
1443 priv->align_dma_offset = 0;
1444 priv->align_vaddr_start = priv->align_vaddr;
1445 priv->align_used_frags = 0;
1447 priv->alloc_frags = fifo->config->max_frags;
1448 priv->next_txdl_priv = NULL;
1450 *txdl_priv = (void *)(size_t)txdp->host_control;
1452 for (i = 0; i < fifo->config->max_frags; i++) {
1453 txdp = ((struct vxge_hw_fifo_txd *)*txdlh) + i;
1454 txdp->control_0 = txdp->control_1 = 0;
1462 * vxge_hw_fifo_txdl_buffer_set - Set transmit buffer pointer in the
1464 * @fifo: Handle to the fifo object used for non offload send
1465 * @txdlh: Descriptor handle.
1466 * @frag_idx: Index of the data buffer in the caller's scatter-gather list
1468 * @dma_pointer: DMA address of the data buffer referenced by @frag_idx.
1469 * @size: Size of the data buffer (in bytes).
1471 * This API is part of the preparation of the transmit descriptor for posting
1472 * (via vxge_hw_fifo_txdl_post()). The related "preparation" APIs include
1473 * vxge_hw_fifo_txdl_mss_set() and vxge_hw_fifo_txdl_cksum_set_bits().
1474 * All three APIs fill in the fields of the fifo descriptor,
1475 * in accordance with the Titan specification.
1478 void vxge_hw_fifo_txdl_buffer_set(struct __vxge_hw_fifo *fifo,
1479 void *txdlh, u32 frag_idx,
1480 dma_addr_t dma_pointer, u32 size)
1482 struct __vxge_hw_fifo_txdl_priv *txdl_priv;
1483 struct vxge_hw_fifo_txd *txdp, *txdp_last;
1485 txdl_priv = __vxge_hw_fifo_txdl_priv(fifo, txdlh);
1486 txdp = (struct vxge_hw_fifo_txd *)txdlh + txdl_priv->frags;
1489 txdp->control_0 = txdp->control_1 = 0;
1491 txdp->control_0 |= VXGE_HW_FIFO_TXD_GATHER_CODE(
1492 VXGE_HW_FIFO_TXD_GATHER_CODE_FIRST);
1493 txdp->control_1 |= fifo->interrupt_type;
1494 txdp->control_1 |= VXGE_HW_FIFO_TXD_INT_NUMBER(
1496 if (txdl_priv->frags) {
1497 txdp_last = (struct vxge_hw_fifo_txd *)txdlh +
1498 (txdl_priv->frags - 1);
1499 txdp_last->control_0 |= VXGE_HW_FIFO_TXD_GATHER_CODE(
1500 VXGE_HW_FIFO_TXD_GATHER_CODE_LAST);
1504 vxge_assert(frag_idx < txdl_priv->alloc_frags);
1506 txdp->buffer_pointer = (u64)dma_pointer;
1507 txdp->control_0 |= VXGE_HW_FIFO_TXD_BUFFER_SIZE(size);
1508 fifo->stats->total_buffers++;
1513 * vxge_hw_fifo_txdl_post - Post descriptor on the fifo channel.
1514 * @fifo: Handle to the fifo object used for non offload send
1515 * @txdlh: Descriptor obtained via vxge_hw_fifo_txdl_reserve()
1517 * Post descriptor on the 'fifo' type channel for transmission.
1518 * Prior to posting the descriptor should be filled in accordance with
1519 * Host/Titan interface specification for a given service (LL, etc.).
1522 void vxge_hw_fifo_txdl_post(struct __vxge_hw_fifo *fifo, void *txdlh)
1524 struct __vxge_hw_fifo_txdl_priv *txdl_priv;
1525 struct vxge_hw_fifo_txd *txdp_last;
1526 struct vxge_hw_fifo_txd *txdp_first;
1528 txdl_priv = __vxge_hw_fifo_txdl_priv(fifo, txdlh);
1531 txdp_last = (struct vxge_hw_fifo_txd *)txdlh + (txdl_priv->frags - 1);
1532 txdp_last->control_0 |=
1533 VXGE_HW_FIFO_TXD_GATHER_CODE(VXGE_HW_FIFO_TXD_GATHER_CODE_LAST);
1534 txdp_first->control_0 |= VXGE_HW_FIFO_TXD_LIST_OWN_ADAPTER;
1536 vxge_hw_channel_dtr_post(&fifo->channel, txdlh);
1538 __vxge_hw_non_offload_db_post(fifo,
1539 (u64)txdl_priv->dma_addr,
1540 txdl_priv->frags - 1,
1541 fifo->no_snoop_bits);
1543 fifo->stats->total_posts++;
1544 fifo->stats->common_stats.usage_cnt++;
1545 if (fifo->stats->common_stats.usage_max <
1546 fifo->stats->common_stats.usage_cnt)
1547 fifo->stats->common_stats.usage_max =
1548 fifo->stats->common_stats.usage_cnt;
1552 * vxge_hw_fifo_txdl_next_completed - Retrieve next completed descriptor.
1553 * @fifo: Handle to the fifo object used for non offload send
1554 * @txdlh: Descriptor handle. Returned by HW.
1555 * @t_code: Transfer code, as per Titan User Guide,
1556 * Transmit Descriptor Format.
1559 * Retrieve the _next_ completed descriptor.
1560 * HW uses channel callback (*vxge_hw_channel_callback_f) to notifiy
1561 * driver of new completed descriptors. After that
1562 * the driver can use vxge_hw_fifo_txdl_next_completed to retrieve the rest
1563 * completions (the very first completion is passed by HW via
1564 * vxge_hw_channel_callback_f).
1566 * Implementation-wise, the driver is free to call
1567 * vxge_hw_fifo_txdl_next_completed either immediately from inside the
1568 * channel callback, or in a deferred fashion and separate (from HW)
1571 * Non-zero @t_code means failure to process the descriptor.
1572 * The failure could happen, for instance, when the link is
1573 * down, in which case Titan completes the descriptor because it
1574 * is not able to send the data out.
1576 * For details please refer to Titan User Guide.
1578 * Returns: VXGE_HW_OK - success.
1579 * VXGE_HW_INF_NO_MORE_COMPLETED_DESCRIPTORS - No completed descriptors
1580 * are currently available for processing.
1583 enum vxge_hw_status vxge_hw_fifo_txdl_next_completed(
1584 struct __vxge_hw_fifo *fifo, void **txdlh,
1585 enum vxge_hw_fifo_tcode *t_code)
1587 struct __vxge_hw_channel *channel;
1588 struct vxge_hw_fifo_txd *txdp;
1589 enum vxge_hw_status status = VXGE_HW_OK;
1591 channel = &fifo->channel;
1593 vxge_hw_channel_dtr_try_complete(channel, txdlh);
1597 status = VXGE_HW_INF_NO_MORE_COMPLETED_DESCRIPTORS;
1601 /* check whether host owns it */
1602 if (!(txdp->control_0 & VXGE_HW_FIFO_TXD_LIST_OWN_ADAPTER)) {
1604 vxge_assert(txdp->host_control != 0);
1606 vxge_hw_channel_dtr_complete(channel);
1608 *t_code = (u8)VXGE_HW_FIFO_TXD_T_CODE_GET(txdp->control_0);
1610 if (fifo->stats->common_stats.usage_cnt > 0)
1611 fifo->stats->common_stats.usage_cnt--;
1613 status = VXGE_HW_OK;
1617 /* no more completions */
1619 status = VXGE_HW_INF_NO_MORE_COMPLETED_DESCRIPTORS;
1625 * vxge_hw_fifo_handle_tcode - Handle transfer code.
1626 * @fifo: Handle to the fifo object used for non offload send
1627 * @txdlh: Descriptor handle.
1628 * @t_code: One of the enumerated (and documented in the Titan user guide)
1631 * Handle descriptor's transfer code. The latter comes with each completed
1634 * Returns: one of the enum vxge_hw_status{} enumerated types.
1635 * VXGE_HW_OK - for success.
1636 * VXGE_HW_ERR_CRITICAL - when encounters critical error.
1638 enum vxge_hw_status vxge_hw_fifo_handle_tcode(struct __vxge_hw_fifo *fifo,
1640 enum vxge_hw_fifo_tcode t_code)
1642 enum vxge_hw_status status = VXGE_HW_OK;
1644 if (((t_code & 0x7) < 0) || ((t_code & 0x7) > 0x4)) {
1645 status = VXGE_HW_ERR_INVALID_TCODE;
1649 fifo->stats->txd_t_code_err_cnt[t_code]++;
1655 * vxge_hw_fifo_txdl_free - Free descriptor.
1656 * @fifo: Handle to the fifo object used for non offload send
1657 * @txdlh: Descriptor handle.
1659 * Free the reserved descriptor. This operation is "symmetrical" to
1660 * vxge_hw_fifo_txdl_reserve. The "free-ing" completes the descriptor's
1663 * After free-ing (see vxge_hw_fifo_txdl_free()) the descriptor again can
1666 * - reserved (vxge_hw_fifo_txdl_reserve);
1668 * - posted (vxge_hw_fifo_txdl_post);
1670 * - completed (vxge_hw_fifo_txdl_next_completed);
1672 * - and recycled again (vxge_hw_fifo_txdl_free).
1674 * For alternative state transitions and more details please refer to
1678 void vxge_hw_fifo_txdl_free(struct __vxge_hw_fifo *fifo, void *txdlh)
1680 struct __vxge_hw_channel *channel;
1682 channel = &fifo->channel;
1684 vxge_hw_channel_dtr_free(channel, txdlh);
1688 * vxge_hw_vpath_mac_addr_add - Add the mac address entry for this vpath to MAC address table.
1689 * @vp: Vpath handle.
1690 * @macaddr: MAC address to be added for this vpath into the list
1691 * @macaddr_mask: MAC address mask for macaddr
1692 * @duplicate_mode: Duplicate MAC address add mode. Please see
1693 * enum vxge_hw_vpath_mac_addr_add_mode{}
1695 * Adds the given mac address and mac address mask into the list for this
1697 * see also: vxge_hw_vpath_mac_addr_delete, vxge_hw_vpath_mac_addr_get and
1698 * vxge_hw_vpath_mac_addr_get_next
1702 vxge_hw_vpath_mac_addr_add(
1703 struct __vxge_hw_vpath_handle *vp,
1706 enum vxge_hw_vpath_mac_addr_add_mode duplicate_mode)
1711 enum vxge_hw_status status = VXGE_HW_OK;
1714 status = VXGE_HW_ERR_INVALID_HANDLE;
1718 for (i = 0; i < ETH_ALEN; i++) {
1720 data1 |= (u8)macaddr[i];
1723 data2 |= (u8)macaddr_mask[i];
1726 switch (duplicate_mode) {
1727 case VXGE_HW_VPATH_MAC_ADDR_ADD_DUPLICATE:
1730 case VXGE_HW_VPATH_MAC_ADDR_DISCARD_DUPLICATE:
1733 case VXGE_HW_VPATH_MAC_ADDR_REPLACE_DUPLICATE:
1741 status = __vxge_hw_vpath_rts_table_set(vp,
1742 VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_ADD_ENTRY,
1743 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA,
1745 VXGE_HW_RTS_ACCESS_STEER_DATA0_DA_MAC_ADDR(data1),
1746 VXGE_HW_RTS_ACCESS_STEER_DATA1_DA_MAC_ADDR_MASK(data2)|
1747 VXGE_HW_RTS_ACCESS_STEER_DATA1_DA_MAC_ADDR_MODE(i));
1753 * vxge_hw_vpath_mac_addr_get - Get the first mac address entry
1754 * @vp: Vpath handle.
1755 * @macaddr: First MAC address entry for this vpath in the list
1756 * @macaddr_mask: MAC address mask for macaddr
1758 * Get the first mac address entry for this vpath from MAC address table.
1759 * Return: the first mac address and mac address mask in the list for this
1761 * see also: vxge_hw_vpath_mac_addr_get_next
1765 vxge_hw_vpath_mac_addr_get(
1766 struct __vxge_hw_vpath_handle *vp,
1773 enum vxge_hw_status status = VXGE_HW_OK;
1776 status = VXGE_HW_ERR_INVALID_HANDLE;
1780 status = __vxge_hw_vpath_rts_table_get(vp,
1781 VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_LIST_FIRST_ENTRY,
1782 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA,
1785 if (status != VXGE_HW_OK)
1788 data1 = VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_DA_MAC_ADDR(data1);
1790 data2 = VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_DA_MAC_ADDR_MASK(data2);
1792 for (i = ETH_ALEN; i > 0; i--) {
1793 macaddr[i-1] = (u8)(data1 & 0xFF);
1796 macaddr_mask[i-1] = (u8)(data2 & 0xFF);
1804 * vxge_hw_vpath_mac_addr_get_next - Get the next mac address entry
1805 * @vp: Vpath handle.
1806 * @macaddr: Next MAC address entry for this vpath in the list
1807 * @macaddr_mask: MAC address mask for macaddr
1809 * Get the next mac address entry for this vpath from MAC address table.
1810 * Return: the next mac address and mac address mask in the list for this
1812 * see also: vxge_hw_vpath_mac_addr_get
1816 vxge_hw_vpath_mac_addr_get_next(
1817 struct __vxge_hw_vpath_handle *vp,
1824 enum vxge_hw_status status = VXGE_HW_OK;
1827 status = VXGE_HW_ERR_INVALID_HANDLE;
1831 status = __vxge_hw_vpath_rts_table_get(vp,
1832 VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_LIST_NEXT_ENTRY,
1833 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA,
1836 if (status != VXGE_HW_OK)
1839 data1 = VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_DA_MAC_ADDR(data1);
1841 data2 = VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_DA_MAC_ADDR_MASK(data2);
1843 for (i = ETH_ALEN; i > 0; i--) {
1844 macaddr[i-1] = (u8)(data1 & 0xFF);
1847 macaddr_mask[i-1] = (u8)(data2 & 0xFF);
1856 * vxge_hw_vpath_mac_addr_delete - Delete the mac address entry for this vpath to MAC address table.
1857 * @vp: Vpath handle.
1858 * @macaddr: MAC address to be added for this vpath into the list
1859 * @macaddr_mask: MAC address mask for macaddr
1861 * Delete the given mac address and mac address mask into the list for this
1863 * see also: vxge_hw_vpath_mac_addr_add, vxge_hw_vpath_mac_addr_get and
1864 * vxge_hw_vpath_mac_addr_get_next
1868 vxge_hw_vpath_mac_addr_delete(
1869 struct __vxge_hw_vpath_handle *vp,
1876 enum vxge_hw_status status = VXGE_HW_OK;
1879 status = VXGE_HW_ERR_INVALID_HANDLE;
1883 for (i = 0; i < ETH_ALEN; i++) {
1885 data1 |= (u8)macaddr[i];
1888 data2 |= (u8)macaddr_mask[i];
1891 status = __vxge_hw_vpath_rts_table_set(vp,
1892 VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_DELETE_ENTRY,
1893 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA,
1895 VXGE_HW_RTS_ACCESS_STEER_DATA0_DA_MAC_ADDR(data1),
1896 VXGE_HW_RTS_ACCESS_STEER_DATA1_DA_MAC_ADDR_MASK(data2));
1902 * vxge_hw_vpath_vid_add - Add the vlan id entry for this vpath to vlan id table.
1903 * @vp: Vpath handle.
1904 * @vid: vlan id to be added for this vpath into the list
1906 * Adds the given vlan id into the list for this vpath.
1907 * see also: vxge_hw_vpath_vid_delete
1911 vxge_hw_vpath_vid_add(struct __vxge_hw_vpath_handle *vp, u64 vid)
1913 enum vxge_hw_status status = VXGE_HW_OK;
1916 status = VXGE_HW_ERR_INVALID_HANDLE;
1920 status = __vxge_hw_vpath_rts_table_set(vp,
1921 VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_ADD_ENTRY,
1922 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_VID,
1923 0, VXGE_HW_RTS_ACCESS_STEER_DATA0_VLAN_ID(vid), 0);
1929 * vxge_hw_vpath_vid_delete - Delete the vlan id entry for this vpath
1931 * @vp: Vpath handle.
1932 * @vid: vlan id to be added for this vpath into the list
1934 * Adds the given vlan id into the list for this vpath.
1935 * see also: vxge_hw_vpath_vid_add
1939 vxge_hw_vpath_vid_delete(struct __vxge_hw_vpath_handle *vp, u64 vid)
1941 enum vxge_hw_status status = VXGE_HW_OK;
1944 status = VXGE_HW_ERR_INVALID_HANDLE;
1948 status = __vxge_hw_vpath_rts_table_set(vp,
1949 VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_DELETE_ENTRY,
1950 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_VID,
1951 0, VXGE_HW_RTS_ACCESS_STEER_DATA0_VLAN_ID(vid), 0);
1957 * vxge_hw_vpath_promisc_enable - Enable promiscuous mode.
1958 * @vp: Vpath handle.
1960 * Enable promiscuous mode of Titan-e operation.
1962 * See also: vxge_hw_vpath_promisc_disable().
1964 enum vxge_hw_status vxge_hw_vpath_promisc_enable(
1965 struct __vxge_hw_vpath_handle *vp)
1968 struct __vxge_hw_virtualpath *vpath;
1969 enum vxge_hw_status status = VXGE_HW_OK;
1971 if ((vp == NULL) || (vp->vpath->ringh == NULL)) {
1972 status = VXGE_HW_ERR_INVALID_HANDLE;
1978 /* Enable promiscuous mode for function 0 only */
1979 if (!(vpath->hldev->access_rights &
1980 VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM))
1983 val64 = readq(&vpath->vp_reg->rxmac_vcfg0);
1985 if (!(val64 & VXGE_HW_RXMAC_VCFG0_UCAST_ALL_ADDR_EN)) {
1987 val64 |= VXGE_HW_RXMAC_VCFG0_UCAST_ALL_ADDR_EN |
1988 VXGE_HW_RXMAC_VCFG0_MCAST_ALL_ADDR_EN |
1989 VXGE_HW_RXMAC_VCFG0_BCAST_EN |
1990 VXGE_HW_RXMAC_VCFG0_ALL_VID_EN;
1992 writeq(val64, &vpath->vp_reg->rxmac_vcfg0);
1999 * vxge_hw_vpath_promisc_disable - Disable promiscuous mode.
2000 * @vp: Vpath handle.
2002 * Disable promiscuous mode of Titan-e operation.
2004 * See also: vxge_hw_vpath_promisc_enable().
2006 enum vxge_hw_status vxge_hw_vpath_promisc_disable(
2007 struct __vxge_hw_vpath_handle *vp)
2010 struct __vxge_hw_virtualpath *vpath;
2011 enum vxge_hw_status status = VXGE_HW_OK;
2013 if ((vp == NULL) || (vp->vpath->ringh == NULL)) {
2014 status = VXGE_HW_ERR_INVALID_HANDLE;
2020 val64 = readq(&vpath->vp_reg->rxmac_vcfg0);
2022 if (val64 & VXGE_HW_RXMAC_VCFG0_UCAST_ALL_ADDR_EN) {
2024 val64 &= ~(VXGE_HW_RXMAC_VCFG0_UCAST_ALL_ADDR_EN |
2025 VXGE_HW_RXMAC_VCFG0_MCAST_ALL_ADDR_EN |
2026 VXGE_HW_RXMAC_VCFG0_ALL_VID_EN);
2028 writeq(val64, &vpath->vp_reg->rxmac_vcfg0);
2035 * vxge_hw_vpath_bcast_enable - Enable broadcast
2036 * @vp: Vpath handle.
2038 * Enable receiving broadcasts.
2040 enum vxge_hw_status vxge_hw_vpath_bcast_enable(
2041 struct __vxge_hw_vpath_handle *vp)
2044 struct __vxge_hw_virtualpath *vpath;
2045 enum vxge_hw_status status = VXGE_HW_OK;
2047 if ((vp == NULL) || (vp->vpath->ringh == NULL)) {
2048 status = VXGE_HW_ERR_INVALID_HANDLE;
2054 val64 = readq(&vpath->vp_reg->rxmac_vcfg0);
2056 if (!(val64 & VXGE_HW_RXMAC_VCFG0_BCAST_EN)) {
2057 val64 |= VXGE_HW_RXMAC_VCFG0_BCAST_EN;
2058 writeq(val64, &vpath->vp_reg->rxmac_vcfg0);
2065 * vxge_hw_vpath_mcast_enable - Enable multicast addresses.
2066 * @vp: Vpath handle.
2068 * Enable Titan-e multicast addresses.
2069 * Returns: VXGE_HW_OK on success.
2072 enum vxge_hw_status vxge_hw_vpath_mcast_enable(
2073 struct __vxge_hw_vpath_handle *vp)
2076 struct __vxge_hw_virtualpath *vpath;
2077 enum vxge_hw_status status = VXGE_HW_OK;
2079 if ((vp == NULL) || (vp->vpath->ringh == NULL)) {
2080 status = VXGE_HW_ERR_INVALID_HANDLE;
2086 val64 = readq(&vpath->vp_reg->rxmac_vcfg0);
2088 if (!(val64 & VXGE_HW_RXMAC_VCFG0_MCAST_ALL_ADDR_EN)) {
2089 val64 |= VXGE_HW_RXMAC_VCFG0_MCAST_ALL_ADDR_EN;
2090 writeq(val64, &vpath->vp_reg->rxmac_vcfg0);
2097 * vxge_hw_vpath_mcast_disable - Disable multicast addresses.
2098 * @vp: Vpath handle.
2100 * Disable Titan-e multicast addresses.
2101 * Returns: VXGE_HW_OK - success.
2102 * VXGE_HW_ERR_INVALID_HANDLE - Invalid handle
2106 vxge_hw_vpath_mcast_disable(struct __vxge_hw_vpath_handle *vp)
2109 struct __vxge_hw_virtualpath *vpath;
2110 enum vxge_hw_status status = VXGE_HW_OK;
2112 if ((vp == NULL) || (vp->vpath->ringh == NULL)) {
2113 status = VXGE_HW_ERR_INVALID_HANDLE;
2119 val64 = readq(&vpath->vp_reg->rxmac_vcfg0);
2121 if (val64 & VXGE_HW_RXMAC_VCFG0_MCAST_ALL_ADDR_EN) {
2122 val64 &= ~VXGE_HW_RXMAC_VCFG0_MCAST_ALL_ADDR_EN;
2123 writeq(val64, &vpath->vp_reg->rxmac_vcfg0);
2130 * vxge_hw_vpath_alarm_process - Process Alarms.
2131 * @vpath: Virtual Path.
2132 * @skip_alarms: Do not clear the alarms
2134 * Process vpath alarms.
2137 enum vxge_hw_status vxge_hw_vpath_alarm_process(
2138 struct __vxge_hw_vpath_handle *vp,
2141 enum vxge_hw_status status = VXGE_HW_OK;
2144 status = VXGE_HW_ERR_INVALID_HANDLE;
2148 status = __vxge_hw_vpath_alarm_process(vp->vpath, skip_alarms);
2154 * vxge_hw_vpath_msix_set - Associate MSIX vectors with TIM interrupts and
2156 * @vp: Virtual Path handle.
2157 * @tim_msix_id: MSIX vectors associated with VXGE_HW_MAX_INTR_PER_VP number of
2158 * interrupts(Can be repeated). If fifo or ring are not enabled
2159 * the MSIX vector for that should be set to 0
2160 * @alarm_msix_id: MSIX vector for alarm.
2162 * This API will associate a given MSIX vector numbers with the four TIM
2163 * interrupts and alarm interrupt.
2166 vxge_hw_vpath_msix_set(struct __vxge_hw_vpath_handle *vp, int *tim_msix_id,
2170 struct __vxge_hw_virtualpath *vpath = vp->vpath;
2171 struct vxge_hw_vpath_reg __iomem *vp_reg = vpath->vp_reg;
2172 u32 vp_id = vp->vpath->vp_id;
2174 val64 = VXGE_HW_INTERRUPT_CFG0_GROUP0_MSIX_FOR_TXTI(
2175 (vp_id * 4) + tim_msix_id[0]) |
2176 VXGE_HW_INTERRUPT_CFG0_GROUP1_MSIX_FOR_TXTI(
2177 (vp_id * 4) + tim_msix_id[1]);
2179 writeq(val64, &vp_reg->interrupt_cfg0);
2181 writeq(VXGE_HW_INTERRUPT_CFG2_ALARM_MAP_TO_MSG(
2182 (vpath->hldev->first_vp_id * 4) + alarm_msix_id),
2183 &vp_reg->interrupt_cfg2);
2185 if (vpath->hldev->config.intr_mode ==
2186 VXGE_HW_INTR_MODE_MSIX_ONE_SHOT) {
2187 __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(
2188 VXGE_HW_ONE_SHOT_VECT0_EN_ONE_SHOT_VECT0_EN,
2189 0, 32), &vp_reg->one_shot_vect0_en);
2190 __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(
2191 VXGE_HW_ONE_SHOT_VECT1_EN_ONE_SHOT_VECT1_EN,
2192 0, 32), &vp_reg->one_shot_vect1_en);
2193 __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(
2194 VXGE_HW_ONE_SHOT_VECT2_EN_ONE_SHOT_VECT2_EN,
2195 0, 32), &vp_reg->one_shot_vect2_en);
2200 * vxge_hw_vpath_msix_mask - Mask MSIX Vector.
2201 * @vp: Virtual Path handle.
2204 * The function masks the msix interrupt for the given msix_id
2207 * Otherwise, VXGE_HW_ERR_WRONG_IRQ if the msix index is out of range
2212 vxge_hw_vpath_msix_mask(struct __vxge_hw_vpath_handle *vp, int msix_id)
2214 struct __vxge_hw_device *hldev = vp->vpath->hldev;
2215 __vxge_hw_pio_mem_write32_upper(
2216 (u32) vxge_bVALn(vxge_mBIT(msix_id >> 2), 0, 32),
2217 &hldev->common_reg->set_msix_mask_vect[msix_id % 4]);
2221 * vxge_hw_vpath_msix_clear - Clear MSIX Vector.
2222 * @vp: Virtual Path handle.
2225 * The function clears the msix interrupt for the given msix_id
2228 * Otherwise, VXGE_HW_ERR_WRONG_IRQ if the msix index is out of range
2232 void vxge_hw_vpath_msix_clear(struct __vxge_hw_vpath_handle *vp, int msix_id)
2234 struct __vxge_hw_device *hldev = vp->vpath->hldev;
2236 if (hldev->config.intr_mode == VXGE_HW_INTR_MODE_MSIX_ONE_SHOT)
2237 __vxge_hw_pio_mem_write32_upper(
2238 (u32) vxge_bVALn(vxge_mBIT((msix_id >> 2)), 0, 32),
2239 &hldev->common_reg->clr_msix_one_shot_vec[msix_id % 4]);
2241 __vxge_hw_pio_mem_write32_upper(
2242 (u32) vxge_bVALn(vxge_mBIT((msix_id >> 2)), 0, 32),
2243 &hldev->common_reg->clear_msix_mask_vect[msix_id % 4]);
2247 * vxge_hw_vpath_msix_unmask - Unmask the MSIX Vector.
2248 * @vp: Virtual Path handle.
2251 * The function unmasks the msix interrupt for the given msix_id
2254 * Otherwise, VXGE_HW_ERR_WRONG_IRQ if the msix index is out of range
2259 vxge_hw_vpath_msix_unmask(struct __vxge_hw_vpath_handle *vp, int msix_id)
2261 struct __vxge_hw_device *hldev = vp->vpath->hldev;
2262 __vxge_hw_pio_mem_write32_upper(
2263 (u32)vxge_bVALn(vxge_mBIT(msix_id >> 2), 0, 32),
2264 &hldev->common_reg->clear_msix_mask_vect[msix_id%4]);
2268 * vxge_hw_vpath_inta_mask_tx_rx - Mask Tx and Rx interrupts.
2269 * @vp: Virtual Path handle.
2271 * Mask Tx and Rx vpath interrupts.
2273 * See also: vxge_hw_vpath_inta_mask_tx_rx()
2275 void vxge_hw_vpath_inta_mask_tx_rx(struct __vxge_hw_vpath_handle *vp)
2277 u64 tim_int_mask0[4] = {[0 ...3] = 0};
2278 u32 tim_int_mask1[4] = {[0 ...3] = 0};
2280 struct __vxge_hw_device *hldev = vp->vpath->hldev;
2282 VXGE_HW_DEVICE_TIM_INT_MASK_SET(tim_int_mask0,
2283 tim_int_mask1, vp->vpath->vp_id);
2285 val64 = readq(&hldev->common_reg->tim_int_mask0);
2287 if ((tim_int_mask0[VXGE_HW_VPATH_INTR_TX] != 0) ||
2288 (tim_int_mask0[VXGE_HW_VPATH_INTR_RX] != 0)) {
2289 writeq((tim_int_mask0[VXGE_HW_VPATH_INTR_TX] |
2290 tim_int_mask0[VXGE_HW_VPATH_INTR_RX] | val64),
2291 &hldev->common_reg->tim_int_mask0);
2294 val64 = readl(&hldev->common_reg->tim_int_mask1);
2296 if ((tim_int_mask1[VXGE_HW_VPATH_INTR_TX] != 0) ||
2297 (tim_int_mask1[VXGE_HW_VPATH_INTR_RX] != 0)) {
2298 __vxge_hw_pio_mem_write32_upper(
2299 (tim_int_mask1[VXGE_HW_VPATH_INTR_TX] |
2300 tim_int_mask1[VXGE_HW_VPATH_INTR_RX] | val64),
2301 &hldev->common_reg->tim_int_mask1);
2306 * vxge_hw_vpath_inta_unmask_tx_rx - Unmask Tx and Rx interrupts.
2307 * @vp: Virtual Path handle.
2309 * Unmask Tx and Rx vpath interrupts.
2311 * See also: vxge_hw_vpath_inta_mask_tx_rx()
2313 void vxge_hw_vpath_inta_unmask_tx_rx(struct __vxge_hw_vpath_handle *vp)
2315 u64 tim_int_mask0[4] = {[0 ...3] = 0};
2316 u32 tim_int_mask1[4] = {[0 ...3] = 0};
2318 struct __vxge_hw_device *hldev = vp->vpath->hldev;
2320 VXGE_HW_DEVICE_TIM_INT_MASK_SET(tim_int_mask0,
2321 tim_int_mask1, vp->vpath->vp_id);
2323 val64 = readq(&hldev->common_reg->tim_int_mask0);
2325 if ((tim_int_mask0[VXGE_HW_VPATH_INTR_TX] != 0) ||
2326 (tim_int_mask0[VXGE_HW_VPATH_INTR_RX] != 0)) {
2327 writeq((~(tim_int_mask0[VXGE_HW_VPATH_INTR_TX] |
2328 tim_int_mask0[VXGE_HW_VPATH_INTR_RX])) & val64,
2329 &hldev->common_reg->tim_int_mask0);
2332 if ((tim_int_mask1[VXGE_HW_VPATH_INTR_TX] != 0) ||
2333 (tim_int_mask1[VXGE_HW_VPATH_INTR_RX] != 0)) {
2334 __vxge_hw_pio_mem_write32_upper(
2335 (~(tim_int_mask1[VXGE_HW_VPATH_INTR_TX] |
2336 tim_int_mask1[VXGE_HW_VPATH_INTR_RX])) & val64,
2337 &hldev->common_reg->tim_int_mask1);
2342 * vxge_hw_vpath_poll_rx - Poll Rx Virtual Path for completed
2343 * descriptors and process the same.
2344 * @ring: Handle to the ring object used for receive
2346 * The function polls the Rx for the completed descriptors and calls
2347 * the driver via supplied completion callback.
2349 * Returns: VXGE_HW_OK, if the polling is completed successful.
2350 * VXGE_HW_COMPLETIONS_REMAIN: There are still more completed
2351 * descriptors available which are yet to be processed.
2353 * See also: vxge_hw_vpath_poll_rx()
2355 enum vxge_hw_status vxge_hw_vpath_poll_rx(struct __vxge_hw_ring *ring)
2358 enum vxge_hw_status status = VXGE_HW_OK;
2364 status = vxge_hw_ring_rxd_next_completed(ring, &first_rxdh, &t_code);
2365 if (status == VXGE_HW_OK)
2366 ring->callback(ring, first_rxdh,
2367 t_code, ring->channel.userdata);
2369 if (ring->cmpl_cnt != 0) {
2370 ring->doorbell_cnt += ring->cmpl_cnt;
2371 if (ring->doorbell_cnt >= ring->rxds_limit) {
2373 * Each RxD is of 4 qwords, update the number of
2374 * qwords replenished
2376 new_count = (ring->doorbell_cnt * 4);
2378 /* For each block add 4 more qwords */
2379 ring->total_db_cnt += ring->doorbell_cnt;
2380 if (ring->total_db_cnt >= ring->rxds_per_block) {
2382 /* Reset total count */
2383 ring->total_db_cnt %= ring->rxds_per_block;
2385 writeq(VXGE_HW_PRC_RXD_DOORBELL_NEW_QW_CNT(new_count),
2386 &ring->vp_reg->prc_rxd_doorbell);
2387 readl(&ring->common_reg->titan_general_int_status);
2388 ring->doorbell_cnt = 0;
2396 * vxge_hw_vpath_poll_tx - Poll Tx for completed descriptors and process the same.
2397 * @fifo: Handle to the fifo object used for non offload send
2398 * @skb_ptr: pointer to skb
2399 * @nr_skb: number of skbs
2400 * @more: more is coming
2402 * The function polls the Tx for the completed descriptors and calls
2403 * the driver via supplied completion callback.
2405 * Returns: VXGE_HW_OK, if the polling is completed successful.
2406 * VXGE_HW_COMPLETIONS_REMAIN: There are still more completed
2407 * descriptors available which are yet to be processed.
2409 enum vxge_hw_status vxge_hw_vpath_poll_tx(struct __vxge_hw_fifo *fifo,
2410 struct sk_buff ***skb_ptr, int nr_skb,
2413 enum vxge_hw_fifo_tcode t_code;
2415 enum vxge_hw_status status = VXGE_HW_OK;
2416 struct __vxge_hw_channel *channel;
2418 channel = &fifo->channel;
2420 status = vxge_hw_fifo_txdl_next_completed(fifo,
2421 &first_txdlh, &t_code);
2422 if (status == VXGE_HW_OK)
2423 if (fifo->callback(fifo, first_txdlh, t_code,
2424 channel->userdata, skb_ptr, nr_skb, more) != VXGE_HW_OK)
2425 status = VXGE_HW_COMPLETIONS_REMAIN;